1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6 * Copyright (c) 2017, 2019, 2020, 2023 Paul Boddie <paul@boddie.org.uk>
7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
8 */
9
10 #include <linux/compiler.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/seq_file.h>
21 #include <linux/slab.h>
22
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28
29 #include "core.h"
30 #include "pinconf.h"
31 #include "pinmux.h"
32
33 #define GPIO_PIN 0x00
34 #define GPIO_MSK 0x20
35
36 #define JZ4730_GPIO_DATA 0x00
37 #define JZ4730_GPIO_GPDIR 0x04
38 #define JZ4730_GPIO_GPPUR 0x0c
39 #define JZ4730_GPIO_GPALR 0x10
40 #define JZ4730_GPIO_GPAUR 0x14
41 #define JZ4730_GPIO_GPIDLR 0x18
42 #define JZ4730_GPIO_GPIDUR 0x1c
43 #define JZ4730_GPIO_GPIER 0x20
44 #define JZ4730_GPIO_GPIMR 0x24
45 #define JZ4730_GPIO_GPFR 0x28
46
47 #define JZ4740_GPIO_DATA 0x10
48 #define JZ4740_GPIO_PULL_DIS 0x30
49 #define JZ4740_GPIO_FUNC 0x40
50 #define JZ4740_GPIO_SELECT 0x50
51 #define JZ4740_GPIO_DIR 0x60
52 #define JZ4740_GPIO_TRIG 0x70
53 #define JZ4740_GPIO_FLAG 0x80
54
55 #define JZ4770_GPIO_INT 0x10
56 #define JZ4770_GPIO_PAT1 0x30
57 #define JZ4770_GPIO_PAT0 0x40
58 #define JZ4770_GPIO_FLAG 0x50
59 #define JZ4770_GPIO_PEN 0x70
60
61 #define X1600_GPIO_PU 0x80
62
63 #define X1830_GPIO_PEL 0x110
64 #define X1830_GPIO_PEH 0x120
65 #define X1830_GPIO_SR 0x150
66 #define X1830_GPIO_SMT 0x160
67
68 #define X2000_GPIO_EDG 0x70
69 #define X2000_GPIO_PEPU 0x80
70 #define X2000_GPIO_PEPD 0x90
71 #define X2000_GPIO_SR 0xd0
72 #define X2000_GPIO_SMT 0xe0
73
74 #define REG_SET(x) ((x) + 0x4)
75 #define REG_CLEAR(x) ((x) + 0x8)
76
77 #define REG_PZ_BASE(x) ((x) * 7)
78 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
79
80 #define GPIO_PULL_DIS 0
81 #define GPIO_PULL_UP 1
82 #define GPIO_PULL_DOWN 2
83
84 #define PINS_PER_GPIO_CHIP 32
85 #define JZ4730_PINS_PER_PAIRED_REG 16
86
87 #define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs) \
88 { \
89 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \
90 .data = funcs, \
91 }
92
93 #define INGENIC_PIN_GROUP(_name_, id, func) \
94 { \
95 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \
96 .data = (void *)func, \
97 }
98
99 #define INGENIC_PIN_FUNCTION(_name_, id) \
100 { \
101 .func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
102 .data = NULL, \
103 }
104
105 enum jz_version {
106 ID_JZ4730,
107 ID_JZ4740,
108 ID_JZ4725B,
109 ID_JZ4750,
110 ID_JZ4755,
111 ID_JZ4760,
112 ID_JZ4770,
113 ID_JZ4775,
114 ID_JZ4780,
115 ID_X1000,
116 ID_X1500,
117 ID_X1600,
118 ID_X1830,
119 ID_X2000,
120 ID_X2100,
121 };
122
123 struct ingenic_chip_info {
124 unsigned int num_chips;
125 unsigned int reg_offset;
126 enum jz_version version;
127
128 const struct group_desc *groups;
129 unsigned int num_groups;
130
131 const struct function_desc *functions;
132 unsigned int num_functions;
133
134 const u32 *pull_ups, *pull_downs;
135
136 const struct regmap_access_table *access_table;
137 };
138
139 struct ingenic_pinctrl {
140 struct device *dev;
141 struct regmap *map;
142 struct pinctrl_dev *pctl;
143 struct pinctrl_pin_desc *pdesc;
144
145 const struct ingenic_chip_info *info;
146
147 struct gpio_chip *gc;
148 };
149
150 struct ingenic_gpio_chip {
151 struct ingenic_pinctrl *jzpc;
152 struct gpio_chip gc;
153 unsigned int irq, reg_base;
154 };
155
156 static const unsigned long enabled_socs =
157 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
158 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
159 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
160 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
161 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
162 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
163 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
164 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
165 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
166 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
167 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
168 IS_ENABLED(CONFIG_MACH_X1600) << ID_X1600 |
169 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
170 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
171 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
172
173 static bool
is_soc_or_above(const struct ingenic_pinctrl * jzpc,enum jz_version version)174 is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
175 {
176 return (enabled_socs >> version) &&
177 (!(enabled_socs & GENMASK(version - 1, 0))
178 || jzpc->info->version >= version);
179 }
180
181 static const u32 jz4730_pull_ups[4] = {
182 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
183 };
184
185 static const u32 jz4730_pull_downs[4] = {
186 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
187 };
188
189 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
190 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
191 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
192 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
193 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
194 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
195 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
196 static int jz4730_lcd_8bit_pins[] = {
197 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
198 0x3a, 0x39, 0x38,
199 };
200 static int jz4730_lcd_16bit_pins[] = {
201 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
202 };
203 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
204 static int jz4730_lcd_generic_pins[] = { 0x3b, };
205 static int jz4730_nand_cs1_pins[] = { 0x53, };
206 static int jz4730_nand_cs2_pins[] = { 0x54, };
207 static int jz4730_nand_cs3_pins[] = { 0x55, };
208 static int jz4730_nand_cs4_pins[] = { 0x56, };
209 static int jz4730_nand_cs5_pins[] = { 0x57, };
210 static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
211 static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
212
213 static int jz4730_mii_pins[] = { 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
214 0x77, 0x78, 0x19, 0x7a, 0x1b, 0x7c, };
215
216 static int jz4730_i2s_mclk_pins[] = { 0x44, };
217 static int jz4730_i2s_acreset_pins[] = { 0x45, };
218 static int jz4730_i2s_data_pins[] = { 0x46, 0x47, };
219 static int jz4730_i2s_clock_pins[] = { 0x4d, 0x4e, };
220
221 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
222
223 static const struct group_desc jz4730_groups[] = {
224 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
225 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
226 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
227 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
228 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
229 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
230 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
231 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
232 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
233 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
234 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
235 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
236 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
237 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
238 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
239 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
240 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
241 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
242 INGENIC_PIN_GROUP("mii", jz4730_mii, 1),
243 INGENIC_PIN_GROUP("i2s-mclk-out", jz4730_i2s_mclk, 1),
244 INGENIC_PIN_GROUP("i2s-acreset", jz4730_i2s_acreset, 1),
245 INGENIC_PIN_GROUP("i2s-data", jz4730_i2s_data, 1),
246 INGENIC_PIN_GROUP("i2s-master", jz4730_i2s_clock, 1),
247 INGENIC_PIN_GROUP("i2s-slave", jz4730_i2s_clock, 2),
248 };
249
250 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
251 static const char *jz4730_uart0_groups[] = { "uart0-data", };
252 static const char *jz4730_uart1_groups[] = { "uart1-data", };
253 static const char *jz4730_uart2_groups[] = { "uart2-data", };
254 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
255 static const char *jz4730_lcd_groups[] = {
256 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
257 };
258 static const char *jz4730_nand_groups[] = {
259 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
260 };
261 static const char *jz4730_pwm0_groups[] = { "pwm0", };
262 static const char *jz4730_pwm1_groups[] = { "pwm1", };
263 static const char *jz4730_mii_groups[] = { "mii", };
264 static const char *jz4730_i2s_groups[] = { "i2s-data", "i2s-master", "i2s-slave", };
265
266 static const struct function_desc jz4730_functions[] = {
267 INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),
268 INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),
269 INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),
270 INGENIC_PIN_FUNCTION("uart2", jz4730_uart2),
271 INGENIC_PIN_FUNCTION("uart3", jz4730_uart3),
272 INGENIC_PIN_FUNCTION("lcd", jz4730_lcd),
273 INGENIC_PIN_FUNCTION("nand", jz4730_nand),
274 INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0),
275 INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1),
276 INGENIC_PIN_FUNCTION("mii", jz4730_mii),
277 INGENIC_PIN_FUNCTION("i2s", jz4730_i2s),
278 };
279
280 static const struct ingenic_chip_info jz4730_chip_info = {
281 .num_chips = 4,
282 .reg_offset = 0x30,
283 .version = ID_JZ4730,
284 .groups = jz4730_groups,
285 .num_groups = ARRAY_SIZE(jz4730_groups),
286 .functions = jz4730_functions,
287 .num_functions = ARRAY_SIZE(jz4730_functions),
288 .pull_ups = jz4730_pull_ups,
289 .pull_downs = jz4730_pull_downs,
290 };
291
292 static const u32 jz4740_pull_ups[4] = {
293 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
294 };
295
296 static const u32 jz4740_pull_downs[4] = {
297 0x00000000, 0x00000000, 0x00000000, 0x00000000,
298 };
299
300 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
301 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
302 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
303 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
304 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
305 static int jz4740_lcd_8bit_pins[] = {
306 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
307 0x52, 0x53, 0x54,
308 };
309 static int jz4740_lcd_16bit_pins[] = {
310 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
311 };
312 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
313 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
314 static int jz4740_lcd_generic_pins[] = { 0x55, };
315 static int jz4740_nand_cs1_pins[] = { 0x39, };
316 static int jz4740_nand_cs2_pins[] = { 0x3a, };
317 static int jz4740_nand_cs3_pins[] = { 0x3b, };
318 static int jz4740_nand_cs4_pins[] = { 0x3c, };
319 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
320 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
321 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
322 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
323 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
324 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
325 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
326 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
327 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
328
329 static const struct group_desc jz4740_groups[] = {
330 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
331 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
332 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
333 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
334 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
335 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
336 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
337 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
338 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
339 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
340 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
341 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
342 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
343 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
344 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
345 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
346 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
347 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
348 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
349 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
350 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
351 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
352 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
353 };
354
355 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
356 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
357 static const char *jz4740_uart1_groups[] = { "uart1-data", };
358 static const char *jz4740_lcd_groups[] = {
359 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
360 };
361 static const char *jz4740_nand_groups[] = {
362 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
363 };
364 static const char *jz4740_pwm0_groups[] = { "pwm0", };
365 static const char *jz4740_pwm1_groups[] = { "pwm1", };
366 static const char *jz4740_pwm2_groups[] = { "pwm2", };
367 static const char *jz4740_pwm3_groups[] = { "pwm3", };
368 static const char *jz4740_pwm4_groups[] = { "pwm4", };
369 static const char *jz4740_pwm5_groups[] = { "pwm5", };
370 static const char *jz4740_pwm6_groups[] = { "pwm6", };
371 static const char *jz4740_pwm7_groups[] = { "pwm7", };
372
373 static const struct function_desc jz4740_functions[] = {
374 INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),
375 INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),
376 INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),
377 INGENIC_PIN_FUNCTION("lcd", jz4740_lcd),
378 INGENIC_PIN_FUNCTION("nand", jz4740_nand),
379 INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0),
380 INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1),
381 INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2),
382 INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3),
383 INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4),
384 INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5),
385 INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6),
386 INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7),
387 };
388
389 static const struct ingenic_chip_info jz4740_chip_info = {
390 .num_chips = 4,
391 .reg_offset = 0x100,
392 .version = ID_JZ4740,
393 .groups = jz4740_groups,
394 .num_groups = ARRAY_SIZE(jz4740_groups),
395 .functions = jz4740_functions,
396 .num_functions = ARRAY_SIZE(jz4740_functions),
397 .pull_ups = jz4740_pull_ups,
398 .pull_downs = jz4740_pull_downs,
399 };
400
401 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
402 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
403 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
404 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
405 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
406 static int jz4725b_lcd_8bit_pins[] = {
407 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
408 0x72, 0x73, 0x74,
409 };
410 static int jz4725b_lcd_16bit_pins[] = {
411 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
412 };
413 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
414 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
415 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
416 static int jz4725b_lcd_generic_pins[] = { 0x75, };
417 static int jz4725b_nand_cs1_pins[] = { 0x55, };
418 static int jz4725b_nand_cs2_pins[] = { 0x56, };
419 static int jz4725b_nand_cs3_pins[] = { 0x57, };
420 static int jz4725b_nand_cs4_pins[] = { 0x58, };
421 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
422 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
423 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
424 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
425 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
426 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
427 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
428 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
429
430 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
431
432 static const struct group_desc jz4725b_groups[] = {
433 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
434 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
435 jz4725b_mmc0_4bit_funcs),
436 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
437 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
438 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
439 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
440 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
441 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
442 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
443 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
444 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
445 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
446 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
447 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
448 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
449 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
450 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
451 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
452 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
453 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
454 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
455 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
456 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
457 };
458
459 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
460 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
461 static const char *jz4725b_uart_groups[] = { "uart-data", };
462 static const char *jz4725b_lcd_groups[] = {
463 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
464 "lcd-special", "lcd-generic",
465 };
466 static const char *jz4725b_nand_groups[] = {
467 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
468 "nand-cle-ale", "nand-fre-fwe",
469 };
470 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
471 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
472 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
473 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
474 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
475 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
476
477 static const struct function_desc jz4725b_functions[] = {
478 INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),
479 INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),
480 INGENIC_PIN_FUNCTION("uart", jz4725b_uart),
481 INGENIC_PIN_FUNCTION("nand", jz4725b_nand),
482 INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0),
483 INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1),
484 INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2),
485 INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3),
486 INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4),
487 INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5),
488 INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd),
489 };
490
491 static const struct ingenic_chip_info jz4725b_chip_info = {
492 .num_chips = 4,
493 .reg_offset = 0x100,
494 .version = ID_JZ4725B,
495 .groups = jz4725b_groups,
496 .num_groups = ARRAY_SIZE(jz4725b_groups),
497 .functions = jz4725b_functions,
498 .num_functions = ARRAY_SIZE(jz4725b_functions),
499 .pull_ups = jz4740_pull_ups,
500 .pull_downs = jz4740_pull_downs,
501 };
502
503 static const u32 jz4750_pull_ups[6] = {
504 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
505 };
506
507 static const u32 jz4750_pull_downs[6] = {
508 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
509 };
510
511 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
512 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
513 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
514 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
515 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
516 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
517 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
518 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
519 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
520 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
521 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
522 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
523 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
524 static int jz4750_cim_pins[] = {
525 0x89, 0x8b, 0x8a, 0x88,
526 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
527 };
528 static int jz4750_lcd_8bit_pins[] = {
529 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
530 0x72, 0x73, 0x74,
531 };
532 static int jz4750_lcd_16bit_pins[] = {
533 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
534 };
535 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
536 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
537 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
538 static int jz4750_lcd_generic_pins[] = { 0x75, };
539 static int jz4750_nand_cs1_pins[] = { 0x55, };
540 static int jz4750_nand_cs2_pins[] = { 0x56, };
541 static int jz4750_nand_cs3_pins[] = { 0x57, };
542 static int jz4750_nand_cs4_pins[] = { 0x58, };
543 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
544 static int jz4750_pwm_pwm0_pins[] = { 0x94, };
545 static int jz4750_pwm_pwm1_pins[] = { 0x95, };
546 static int jz4750_pwm_pwm2_pins[] = { 0x96, };
547 static int jz4750_pwm_pwm3_pins[] = { 0x97, };
548 static int jz4750_pwm_pwm4_pins[] = { 0x98, };
549 static int jz4750_pwm_pwm5_pins[] = { 0x99, };
550
551 static const struct group_desc jz4750_groups[] = {
552 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
553 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
554 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
555 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
556 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
557 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
558 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
559 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
560 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
561 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
562 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
563 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
564 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
565 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
566 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
567 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
568 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
569 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
570 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
571 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
572 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
573 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
574 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
575 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
576 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
577 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
578 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
579 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
580 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
581 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
582 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
583 };
584
585 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
586 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
587 static const char *jz4750_uart2_groups[] = { "uart2-data", };
588 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
589 static const char *jz4750_mmc0_groups[] = {
590 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
591 };
592 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
593 static const char *jz4750_i2c_groups[] = { "i2c-data", };
594 static const char *jz4750_cim_groups[] = { "cim-data", };
595 static const char *jz4750_lcd_groups[] = {
596 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
597 "lcd-special", "lcd-generic",
598 };
599 static const char *jz4750_nand_groups[] = {
600 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
601 };
602 static const char *jz4750_pwm0_groups[] = { "pwm0", };
603 static const char *jz4750_pwm1_groups[] = { "pwm1", };
604 static const char *jz4750_pwm2_groups[] = { "pwm2", };
605 static const char *jz4750_pwm3_groups[] = { "pwm3", };
606 static const char *jz4750_pwm4_groups[] = { "pwm4", };
607 static const char *jz4750_pwm5_groups[] = { "pwm5", };
608
609 static const struct function_desc jz4750_functions[] = {
610 INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),
611 INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),
612 INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),
613 INGENIC_PIN_FUNCTION("uart3", jz4750_uart3),
614 INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0),
615 INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1),
616 INGENIC_PIN_FUNCTION("i2c", jz4750_i2c),
617 INGENIC_PIN_FUNCTION("cim", jz4750_cim),
618 INGENIC_PIN_FUNCTION("lcd", jz4750_lcd),
619 INGENIC_PIN_FUNCTION("nand", jz4750_nand),
620 INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0),
621 INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1),
622 INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2),
623 INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3),
624 INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4),
625 INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5),
626 };
627
628 static const struct ingenic_chip_info jz4750_chip_info = {
629 .num_chips = 6,
630 .reg_offset = 0x100,
631 .version = ID_JZ4750,
632 .groups = jz4750_groups,
633 .num_groups = ARRAY_SIZE(jz4750_groups),
634 .functions = jz4750_functions,
635 .num_functions = ARRAY_SIZE(jz4750_functions),
636 .pull_ups = jz4750_pull_ups,
637 .pull_downs = jz4750_pull_downs,
638 };
639
640 static const u32 jz4755_pull_ups[6] = {
641 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
642 };
643
644 static const u32 jz4755_pull_downs[6] = {
645 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
646 };
647
648 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
649 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
650 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
651 static int jz4755_uart2_data_pins[] = { 0x9f, };
652 static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
653 static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
654 static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
655 static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
656 static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
657 static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
658 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
659 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
660 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
661 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
662 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
663 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
664 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
665 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
666 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
667 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
668 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
669 static int jz4755_cim_pins[] = {
670 0x89, 0x8b, 0x8a, 0x88,
671 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
672 };
673 static int jz4755_lcd_8bit_pins[] = {
674 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
675 0x72, 0x73, 0x74,
676 };
677 static int jz4755_lcd_16bit_pins[] = {
678 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
679 };
680 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
681 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
682 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
683 static int jz4755_lcd_generic_pins[] = { 0x75, };
684 static int jz4755_nand_cs1_pins[] = { 0x55, };
685 static int jz4755_nand_cs2_pins[] = { 0x56, };
686 static int jz4755_nand_cs3_pins[] = { 0x57, };
687 static int jz4755_nand_cs4_pins[] = { 0x58, };
688 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
689 static int jz4755_pwm_pwm0_pins[] = { 0x94, };
690 static int jz4755_pwm_pwm1_pins[] = { 0xab, };
691 static int jz4755_pwm_pwm2_pins[] = { 0x96, };
692 static int jz4755_pwm_pwm3_pins[] = { 0x97, };
693 static int jz4755_pwm_pwm4_pins[] = { 0x98, };
694 static int jz4755_pwm_pwm5_pins[] = { 0x99, };
695
696 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
697 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
698 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
699
700 static const struct group_desc jz4755_groups[] = {
701 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
702 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
703 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
704 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
705 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
706 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
707 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
708 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
709 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
710 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
711 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
712 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
713 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
714 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
715 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
716 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
717 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
718 jz4755_mmc0_1bit_funcs),
719 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
720 jz4755_mmc0_4bit_funcs),
721 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
722 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
723 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
724 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
725 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
726 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
727 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
728 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
729 jz4755_lcd_24bit_funcs),
730 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
731 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
732 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
733 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
734 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
735 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
736 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
737 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
738 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
739 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
740 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
741 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
742 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
743 };
744
745 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
746 static const char *jz4755_uart1_groups[] = { "uart1-data", };
747 static const char *jz4755_uart2_groups[] = { "uart2-data", };
748 static const char *jz4755_ssi_groups[] = {
749 "ssi-dt-b", "ssi-dt-f",
750 "ssi-dr-b", "ssi-dr-f",
751 "ssi-clk-b", "ssi-clk-f",
752 "ssi-gpc-b", "ssi-gpc-f",
753 "ssi-ce0-b", "ssi-ce0-f",
754 "ssi-ce1-b", "ssi-ce1-f",
755 };
756 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
757 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
758 static const char *jz4755_i2c_groups[] = { "i2c-data", };
759 static const char *jz4755_cim_groups[] = { "cim-data", };
760 static const char *jz4755_lcd_groups[] = {
761 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
762 "lcd-special", "lcd-generic",
763 };
764 static const char *jz4755_nand_groups[] = {
765 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
766 };
767 static const char *jz4755_pwm0_groups[] = { "pwm0", };
768 static const char *jz4755_pwm1_groups[] = { "pwm1", };
769 static const char *jz4755_pwm2_groups[] = { "pwm2", };
770 static const char *jz4755_pwm3_groups[] = { "pwm3", };
771 static const char *jz4755_pwm4_groups[] = { "pwm4", };
772 static const char *jz4755_pwm5_groups[] = { "pwm5", };
773
774 static const struct function_desc jz4755_functions[] = {
775 INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),
776 INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),
777 INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),
778 INGENIC_PIN_FUNCTION("ssi", jz4755_ssi),
779 INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0),
780 INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1),
781 INGENIC_PIN_FUNCTION("i2c", jz4755_i2c),
782 INGENIC_PIN_FUNCTION("cim", jz4755_cim),
783 INGENIC_PIN_FUNCTION("lcd", jz4755_lcd),
784 INGENIC_PIN_FUNCTION("nand", jz4755_nand),
785 INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0),
786 INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1),
787 INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2),
788 INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3),
789 INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4),
790 INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5),
791 };
792
793 static const struct ingenic_chip_info jz4755_chip_info = {
794 .num_chips = 6,
795 .reg_offset = 0x100,
796 .version = ID_JZ4755,
797 .groups = jz4755_groups,
798 .num_groups = ARRAY_SIZE(jz4755_groups),
799 .functions = jz4755_functions,
800 .num_functions = ARRAY_SIZE(jz4755_functions),
801 .pull_ups = jz4755_pull_ups,
802 .pull_downs = jz4755_pull_downs,
803 };
804
805 static const u32 jz4760_pull_ups[6] = {
806 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
807 };
808
809 static const u32 jz4760_pull_downs[6] = {
810 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
811 };
812
813 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
814 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
815 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
816 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
817 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
818 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
819 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
820 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
821 static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
822 static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
823 static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
824 static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
825 static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
826 static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
827 static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
828 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
829 static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
830 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
831 static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
832 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
833 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
834 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
835 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
836 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
837 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
838 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
839 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
840 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
841 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
842 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
843 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
844 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
845 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
846 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
847 static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
848 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
849 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
850 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
851 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
852 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
853 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
854 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
855 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
856 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
857 static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
858 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
859 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
860 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
861 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
862 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
863 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
864 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
865 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
866 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
867 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
868 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
869 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
870 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
871 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
872 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
873 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
874 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
875 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
876 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
877 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
878 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
879 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
880 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
881 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
882 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
883 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
884 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
885 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
886 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
887 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
888 static int jz4760_nemc_8bit_data_pins[] = {
889 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
890 };
891 static int jz4760_nemc_16bit_data_pins[] = {
892 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
893 };
894 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
895 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
896 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
897 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
898 static int jz4760_nemc_wait_pins[] = { 0x1b, };
899 static int jz4760_nemc_cs1_pins[] = { 0x15, };
900 static int jz4760_nemc_cs2_pins[] = { 0x16, };
901 static int jz4760_nemc_cs3_pins[] = { 0x17, };
902 static int jz4760_nemc_cs4_pins[] = { 0x18, };
903 static int jz4760_nemc_cs5_pins[] = { 0x19, };
904 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
905 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
906 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
907 static int jz4760_cim_pins[] = {
908 0x26, 0x27, 0x28, 0x29,
909 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
910 };
911 static int jz4760_lcd_8bit_pins[] = {
912 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
913 0x4d, 0x52, 0x53,
914 };
915 static int jz4760_lcd_16bit_pins[] = {
916 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
917 };
918 static int jz4760_lcd_18bit_pins[] = {
919 0x5a, 0x5b,
920 };
921 static int jz4760_lcd_24bit_pins[] = {
922 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
923 };
924 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
925 static int jz4760_lcd_generic_pins[] = { 0x49, };
926 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
927 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
928 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
929 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
930 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
931 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
932 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
933 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
934 static int jz4760_otg_pins[] = { 0x8a, };
935
936 static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
937 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
938
939 static const struct group_desc jz4760_groups[] = {
940 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
941 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
942 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
943 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
944 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
945 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
946 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
947 jz4760_uart3_data_funcs),
948 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
949 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
950 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
951 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
952 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
953 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
954 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
955 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
956 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
957 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
958 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
959 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
960 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
961 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
962 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
963 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
964 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
965 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
966 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
967 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
968 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
969 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
970 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
971 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
972 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
973 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
974 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
975 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
976 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
977 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
978 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
979 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
980 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
981 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
982 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
983 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
984 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
985 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
986 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
987 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
988 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
989 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
990 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
991 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
992 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
993 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
994 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
995 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
996 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
997 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
998 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
999 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
1000 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
1001 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
1002 jz4760_mmc0_1bit_a_funcs),
1003 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
1004 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
1005 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
1006 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
1007 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
1008 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
1009 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
1010 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
1011 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
1012 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
1013 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
1014 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
1015 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
1016 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
1017 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
1018 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
1019 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
1020 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
1021 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
1022 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
1023 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
1024 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
1025 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
1026 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
1027 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
1028 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
1029 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
1030 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1031 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1032 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1033 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1034 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1035 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1036 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1037 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1038 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1039 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
1040 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
1041 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
1042 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
1043 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
1044 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
1045 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
1046 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
1047 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1048 };
1049
1050 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1051 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1052 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1053 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1054 static const char *jz4760_ssi0_groups[] = {
1055 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1056 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1057 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1058 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1059 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1060 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1061 };
1062 static const char *jz4760_ssi1_groups[] = {
1063 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1064 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1065 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1066 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1067 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1068 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1069 };
1070 static const char *jz4760_mmc0_groups[] = {
1071 "mmc0-1bit-a", "mmc0-4bit-a",
1072 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1073 };
1074 static const char *jz4760_mmc1_groups[] = {
1075 "mmc1-1bit-d", "mmc1-4bit-d",
1076 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1077 };
1078 static const char *jz4760_mmc2_groups[] = {
1079 "mmc2-1bit-b", "mmc2-4bit-b",
1080 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1081 };
1082 static const char *jz4760_nemc_groups[] = {
1083 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1084 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1085 };
1086 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1087 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1088 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1089 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1090 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1091 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1092 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1093 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1094 static const char *jz4760_cim_groups[] = { "cim-data", };
1095 static const char *jz4760_lcd_groups[] = {
1096 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1097 "lcd-special", "lcd-generic",
1098 };
1099 static const char *jz4760_pwm0_groups[] = { "pwm0", };
1100 static const char *jz4760_pwm1_groups[] = { "pwm1", };
1101 static const char *jz4760_pwm2_groups[] = { "pwm2", };
1102 static const char *jz4760_pwm3_groups[] = { "pwm3", };
1103 static const char *jz4760_pwm4_groups[] = { "pwm4", };
1104 static const char *jz4760_pwm5_groups[] = { "pwm5", };
1105 static const char *jz4760_pwm6_groups[] = { "pwm6", };
1106 static const char *jz4760_pwm7_groups[] = { "pwm7", };
1107 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1108
1109 static const struct function_desc jz4760_functions[] = {
1110 INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),
1111 INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),
1112 INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),
1113 INGENIC_PIN_FUNCTION("uart3", jz4760_uart3),
1114 INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0),
1115 INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1),
1116 INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0),
1117 INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1),
1118 INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2),
1119 INGENIC_PIN_FUNCTION("nemc", jz4760_nemc),
1120 INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
1121 INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
1122 INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
1123 INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
1124 INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
1125 INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
1126 INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0),
1127 INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1),
1128 INGENIC_PIN_FUNCTION("cim", jz4760_cim),
1129 INGENIC_PIN_FUNCTION("lcd", jz4760_lcd),
1130 INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0),
1131 INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1),
1132 INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2),
1133 INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3),
1134 INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4),
1135 INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5),
1136 INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6),
1137 INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7),
1138 INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1139 };
1140
1141 static const struct ingenic_chip_info jz4760_chip_info = {
1142 .num_chips = 6,
1143 .reg_offset = 0x100,
1144 .version = ID_JZ4760,
1145 .groups = jz4760_groups,
1146 .num_groups = ARRAY_SIZE(jz4760_groups),
1147 .functions = jz4760_functions,
1148 .num_functions = ARRAY_SIZE(jz4760_functions),
1149 .pull_ups = jz4760_pull_ups,
1150 .pull_downs = jz4760_pull_downs,
1151 };
1152
1153 static const u32 jz4770_pull_ups[6] = {
1154 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
1155 };
1156
1157 static const u32 jz4770_pull_downs[6] = {
1158 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
1159 };
1160
1161 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
1162 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1163 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
1164 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1165 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
1166 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
1167 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
1168 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
1169 static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
1170 static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
1171 static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
1172 static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
1173 static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
1174 static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
1175 static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
1176 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
1177 static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
1178 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
1179 static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
1180 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
1181 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
1182 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
1183 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
1184 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
1185 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
1186 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
1187 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
1188 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
1189 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
1190 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
1191 static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
1192 static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
1193 static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
1194 static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
1195 static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
1196 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
1197 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
1198 static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
1199 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
1200 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
1201 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
1202 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
1203 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
1204 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
1205 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
1206 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
1207 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
1208 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
1209 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1210 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1211 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1212 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1213 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1214 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1215 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1216 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1217 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1218 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1219 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1220 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1221 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1222 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1223 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1224 static int jz4770_nemc_8bit_data_pins[] = {
1225 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1226 };
1227 static int jz4770_nemc_16bit_data_pins[] = {
1228 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1229 };
1230 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1231 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1232 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
1233 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1234 static int jz4770_nemc_wait_pins[] = { 0x1b, };
1235 static int jz4770_nemc_cs1_pins[] = { 0x15, };
1236 static int jz4770_nemc_cs2_pins[] = { 0x16, };
1237 static int jz4770_nemc_cs3_pins[] = { 0x17, };
1238 static int jz4770_nemc_cs4_pins[] = { 0x18, };
1239 static int jz4770_nemc_cs5_pins[] = { 0x19, };
1240 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
1241 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
1242 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
1243 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
1244 static int jz4770_cim_8bit_pins[] = {
1245 0x26, 0x27, 0x28, 0x29,
1246 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1247 };
1248 static int jz4770_cim_12bit_pins[] = {
1249 0x32, 0x33, 0xb0, 0xb1,
1250 };
1251 static int jz4770_lcd_8bit_pins[] = {
1252 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1253 0x48, 0x52, 0x53,
1254 };
1255 static int jz4770_lcd_16bit_pins[] = {
1256 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1257 };
1258 static int jz4770_lcd_18bit_pins[] = {
1259 0x5a, 0x5b,
1260 };
1261 static int jz4770_lcd_24bit_pins[] = {
1262 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
1263 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
1264 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
1265 0x58, 0x59, 0x5a, 0x5b,
1266 };
1267 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1268 static int jz4770_lcd_generic_pins[] = { 0x49, };
1269 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
1270 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
1271 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
1272 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
1273 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
1274 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
1275 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
1276 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
1277 static int jz4770_mac_rmii_pins[] = {
1278 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1279 };
1280 static int jz4770_mac_mii_pins[] = {
1281 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1282 };
1283
1284 static const struct group_desc jz4770_groups[] = {
1285 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1286 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1287 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1288 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1289 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1290 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1291 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1292 jz4760_uart3_data_funcs),
1293 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1294 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1295 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1296 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1297 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1298 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1299 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1300 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1301 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1302 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1303 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1304 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1305 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1306 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1307 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1308 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1309 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1310 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1311 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1312 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1313 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1314 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1315 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1316 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1317 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1318 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1319 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1320 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1321 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1322 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1323 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1324 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1325 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1326 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1327 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1328 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1329 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1330 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1331 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1332 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1333 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1334 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1335 jz4760_mmc0_1bit_a_funcs),
1336 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1337 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1338 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1339 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1340 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1341 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1342 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1343 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1344 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1345 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1346 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1347 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1348 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1349 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1350 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1351 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1352 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1353 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1354 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1355 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1356 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1357 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1358 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1359 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1360 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1361 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1362 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1363 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1364 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1365 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1366 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1367 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1368 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1369 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1370 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1371 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1372 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1373 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1374 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1375 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1376 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1377 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1378 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1379 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1380 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1381 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1382 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1383 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1384 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1385 };
1386
1387 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1388 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1389 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1390 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1391 static const char *jz4770_ssi0_groups[] = {
1392 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1393 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1394 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1395 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1396 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1397 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1398 };
1399 static const char *jz4770_ssi1_groups[] = {
1400 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1401 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1402 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1403 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1404 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1405 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1406 };
1407 static const char *jz4770_mmc0_groups[] = {
1408 "mmc0-1bit-a", "mmc0-4bit-a",
1409 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1410 };
1411 static const char *jz4770_mmc1_groups[] = {
1412 "mmc1-1bit-d", "mmc1-4bit-d",
1413 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1414 };
1415 static const char *jz4770_mmc2_groups[] = {
1416 "mmc2-1bit-b", "mmc2-4bit-b",
1417 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1418 };
1419 static const char *jz4770_nemc_groups[] = {
1420 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1421 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1422 };
1423 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1424 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1425 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1426 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1427 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1428 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1429 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1430 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1431 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1432 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1433 static const char *jz4770_lcd_groups[] = {
1434 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1435 "lcd-special", "lcd-generic",
1436 };
1437 static const char *jz4770_pwm0_groups[] = { "pwm0", };
1438 static const char *jz4770_pwm1_groups[] = { "pwm1", };
1439 static const char *jz4770_pwm2_groups[] = { "pwm2", };
1440 static const char *jz4770_pwm3_groups[] = { "pwm3", };
1441 static const char *jz4770_pwm4_groups[] = { "pwm4", };
1442 static const char *jz4770_pwm5_groups[] = { "pwm5", };
1443 static const char *jz4770_pwm6_groups[] = { "pwm6", };
1444 static const char *jz4770_pwm7_groups[] = { "pwm7", };
1445 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1446
1447 static const struct function_desc jz4770_functions[] = {
1448 INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1449 INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1450 INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),
1451 INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1452 INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0),
1453 INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1),
1454 INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0),
1455 INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1),
1456 INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2),
1457 INGENIC_PIN_FUNCTION("nemc", jz4770_nemc),
1458 INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1459 INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1460 INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1461 INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1462 INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1463 INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1464 INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1465 INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1466 INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
1467 INGENIC_PIN_FUNCTION("cim", jz4770_cim),
1468 INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
1469 INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
1470 INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
1471 INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
1472 INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
1473 INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
1474 INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
1475 INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
1476 INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
1477 INGENIC_PIN_FUNCTION("mac", jz4770_mac),
1478 INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1479 };
1480
1481 static const struct ingenic_chip_info jz4770_chip_info = {
1482 .num_chips = 6,
1483 .reg_offset = 0x100,
1484 .version = ID_JZ4770,
1485 .groups = jz4770_groups,
1486 .num_groups = ARRAY_SIZE(jz4770_groups),
1487 .functions = jz4770_functions,
1488 .num_functions = ARRAY_SIZE(jz4770_functions),
1489 .pull_ups = jz4770_pull_ups,
1490 .pull_downs = jz4770_pull_downs,
1491 };
1492
1493 static const u32 jz4775_pull_ups[7] = {
1494 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
1495 };
1496
1497 static const u32 jz4775_pull_downs[7] = {
1498 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
1499 };
1500
1501 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
1502 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1503 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
1504 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1505 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
1506 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
1507 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
1508 static int jz4775_ssi_dt_a_pins[] = { 0x13, };
1509 static int jz4775_ssi_dt_d_pins[] = { 0x75, };
1510 static int jz4775_ssi_dr_a_pins[] = { 0x14, };
1511 static int jz4775_ssi_dr_d_pins[] = { 0x74, };
1512 static int jz4775_ssi_clk_a_pins[] = { 0x12, };
1513 static int jz4775_ssi_clk_d_pins[] = { 0x78, };
1514 static int jz4775_ssi_gpc_pins[] = { 0x76, };
1515 static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
1516 static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
1517 static int jz4775_ssi_ce1_pins[] = { 0x77, };
1518 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1519 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1520 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
1521 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1522 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1523 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1524 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1525 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1526 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1527 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1528 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1529 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1530 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1531 static int jz4775_nemc_8bit_data_pins[] = {
1532 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1533 };
1534 static int jz4775_nemc_16bit_data_pins[] = {
1535 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
1536 };
1537 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1538 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1539 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
1540 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1541 static int jz4775_nemc_wait_pins[] = { 0x1b, };
1542 static int jz4775_nemc_cs1_pins[] = { 0x15, };
1543 static int jz4775_nemc_cs2_pins[] = { 0x16, };
1544 static int jz4775_nemc_cs3_pins[] = { 0x17, };
1545 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
1546 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
1547 static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
1548 static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
1549 static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
1550 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
1551 static int jz4775_i2s_sysclk_pins[] = { 0x83, };
1552 static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
1553 static int jz4775_cim_pins[] = {
1554 0x26, 0x27, 0x28, 0x29,
1555 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1556 };
1557 static int jz4775_lcd_8bit_pins[] = {
1558 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1559 0x48, 0x52, 0x53,
1560 };
1561 static int jz4775_lcd_16bit_pins[] = {
1562 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1563 };
1564 static int jz4775_lcd_18bit_pins[] = {
1565 0x5a, 0x5b,
1566 };
1567 static int jz4775_lcd_24bit_pins[] = {
1568 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
1569 };
1570 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1571 static int jz4775_lcd_generic_pins[] = { 0x49, };
1572 static int jz4775_pwm_pwm0_pins[] = { 0x80, };
1573 static int jz4775_pwm_pwm1_pins[] = { 0x81, };
1574 static int jz4775_pwm_pwm2_pins[] = { 0x82, };
1575 static int jz4775_pwm_pwm3_pins[] = { 0x83, };
1576 static int jz4775_mac_rmii_pins[] = {
1577 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1578 };
1579 static int jz4775_mac_mii_pins[] = {
1580 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1581 };
1582 static int jz4775_mac_rgmii_pins[] = {
1583 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
1584 0xad, 0xae, 0xa7, 0xa6,
1585 };
1586 static int jz4775_mac_gmii_pins[] = {
1587 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
1588 0xa8, 0x28, 0x24, 0xaf,
1589 };
1590 static int jz4775_otg_pins[] = { 0x8a, };
1591
1592 static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
1593 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
1594 static u8 jz4775_mac_rgmii_funcs[] = {
1595 0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
1596 0, 0, 0, 0,
1597 };
1598 static u8 jz4775_mac_gmii_funcs[] = {
1599 1, 1, 1, 1, 1, 1, 1, 1,
1600 0, 1, 1, 0,
1601 };
1602
1603 static const struct group_desc jz4775_groups[] = {
1604 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1605 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1606 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1607 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1608 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1609 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1610 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1611 jz4775_uart3_data_funcs),
1612 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1613 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1614 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1615 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1616 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1617 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1618 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1619 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1620 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1621 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1622 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1623 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1624 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1625 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1626 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1627 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1628 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1629 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1630 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1631 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1632 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1633 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1634 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1635 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1636 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1637 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1638 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1639 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1640 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1641 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1642 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1643 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1644 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1645 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1646 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1647 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1648 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1649 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1650 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1651 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1652 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
1653 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1654 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1655 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1656 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1657 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1658 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1659 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1660 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
1661 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
1662 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
1663 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
1664 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1665 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1666 jz4775_mac_mii_funcs),
1667 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1668 jz4775_mac_rgmii_funcs),
1669 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1670 jz4775_mac_gmii_funcs),
1671 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1672 };
1673
1674 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1675 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1676 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1677 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1678 static const char *jz4775_ssi_groups[] = {
1679 "ssi-dt-a", "ssi-dt-d",
1680 "ssi-dr-a", "ssi-dr-d",
1681 "ssi-clk-a", "ssi-clk-d",
1682 "ssi-gpc",
1683 "ssi-ce0-a", "ssi-ce0-d",
1684 "ssi-ce1",
1685 };
1686 static const char *jz4775_mmc0_groups[] = {
1687 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1688 "mmc0-1bit-e", "mmc0-4bit-e",
1689 };
1690 static const char *jz4775_mmc1_groups[] = {
1691 "mmc1-1bit-d", "mmc1-4bit-d",
1692 "mmc1-1bit-e", "mmc1-4bit-e",
1693 };
1694 static const char *jz4775_mmc2_groups[] = {
1695 "mmc2-1bit-b", "mmc2-4bit-b",
1696 "mmc2-1bit-e", "mmc2-4bit-e",
1697 };
1698 static const char *jz4775_nemc_groups[] = {
1699 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1700 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1701 };
1702 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1703 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1704 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1705 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1706 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1707 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1708 static const char *jz4775_i2s_groups[] = {
1709 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1710 };
1711 static const char *jz4775_dmic_groups[] = { "dmic", };
1712 static const char *jz4775_cim_groups[] = { "cim-data", };
1713 static const char *jz4775_lcd_groups[] = {
1714 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1715 "lcd-special", "lcd-generic",
1716 };
1717 static const char *jz4775_pwm0_groups[] = { "pwm0", };
1718 static const char *jz4775_pwm1_groups[] = { "pwm1", };
1719 static const char *jz4775_pwm2_groups[] = { "pwm2", };
1720 static const char *jz4775_pwm3_groups[] = { "pwm3", };
1721 static const char *jz4775_mac_groups[] = {
1722 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1723 };
1724 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1725
1726 static const struct function_desc jz4775_functions[] = {
1727 INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),
1728 INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),
1729 INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),
1730 INGENIC_PIN_FUNCTION("uart3", jz4775_uart3),
1731 INGENIC_PIN_FUNCTION("ssi", jz4775_ssi),
1732 INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0),
1733 INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1),
1734 INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2),
1735 INGENIC_PIN_FUNCTION("nemc", jz4775_nemc),
1736 INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
1737 INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
1738 INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
1739 INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0),
1740 INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1),
1741 INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2),
1742 INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),
1743 INGENIC_PIN_FUNCTION("dmic", jz4775_dmic),
1744 INGENIC_PIN_FUNCTION("cim", jz4775_cim),
1745 INGENIC_PIN_FUNCTION("lcd", jz4775_lcd),
1746 INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0),
1747 INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1),
1748 INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2),
1749 INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3),
1750 INGENIC_PIN_FUNCTION("mac", jz4775_mac),
1751 INGENIC_PIN_FUNCTION("otg", jz4775_otg),
1752 };
1753
1754 static const struct ingenic_chip_info jz4775_chip_info = {
1755 .num_chips = 7,
1756 .reg_offset = 0x100,
1757 .version = ID_JZ4775,
1758 .groups = jz4775_groups,
1759 .num_groups = ARRAY_SIZE(jz4775_groups),
1760 .functions = jz4775_functions,
1761 .num_functions = ARRAY_SIZE(jz4775_functions),
1762 .pull_ups = jz4775_pull_ups,
1763 .pull_downs = jz4775_pull_downs,
1764 };
1765
1766 static const u32 jz4780_pull_ups[6] = {
1767 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1768 };
1769
1770 static const u32 jz4780_pull_downs[6] = {
1771 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1772 };
1773
1774 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1775 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1776 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
1777 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1778 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1779 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1780 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
1781 static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
1782 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1783 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1784 static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
1785 static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
1786 static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1787 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1788 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
1789 static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
1790 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
1791 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
1792 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1793 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1794 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
1795 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
1796 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
1797 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
1798 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
1799 static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
1800 static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
1801 static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
1802 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
1803 static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
1804 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
1805 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
1806 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
1807 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
1808 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
1809 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
1810 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1811 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1812 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1813 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
1814 static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1815 static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1816 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1817 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1818 static int jz4780_i2s_sysclk_pins[] = { 0x85, };
1819 static int jz4780_dmic_pins[] = { 0x32, 0x33, };
1820 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
1821
1822 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
1823
1824 static const struct group_desc jz4780_groups[] = {
1825 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1826 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1827 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1828 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1829 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1830 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1831 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1832 jz4760_uart3_data_funcs),
1833 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1834 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1835 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1836 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1837 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1838 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1839 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1840 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1841 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1842 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1843 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1844 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1845 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1846 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1847 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1848 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1849 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1850 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1851 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1852 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1853 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1854 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1855 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1856 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1857 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1858 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1859 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1860 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1861 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1862 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1863 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1864 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1865 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1866 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1867 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1868 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1869 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1870 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1871 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1872 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1873 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1874 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1875 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1876 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1877 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1878 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1879 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1880 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1881 jz4760_mmc0_1bit_a_funcs),
1882 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1883 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1884 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1885 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1886 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1887 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1888 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1889 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1890 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1891 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1892 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1893 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1894 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1895 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1896 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1897 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1898 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1899 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1900 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1901 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1902 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1903 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1904 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1905 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1906 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1907 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1908 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1909 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1910 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1911 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1912 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1913 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1914 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1915 jz4780_i2s_clk_txrx_funcs),
1916 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1917 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1918 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
1919 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1920 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1921 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1922 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1923 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1924 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1925 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1926 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1927 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1928 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1929 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1930 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1931 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1932 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1933 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1934 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1935 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1936 };
1937
1938 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1939 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1940 static const char *jz4780_ssi0_groups[] = {
1941 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1942 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1943 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1944 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1945 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1946 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1947 };
1948 static const char *jz4780_ssi1_groups[] = {
1949 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1950 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1951 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1952 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1953 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1954 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1955 };
1956 static const char *jz4780_mmc0_groups[] = {
1957 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1958 "mmc0-1bit-e", "mmc0-4bit-e",
1959 };
1960 static const char *jz4780_mmc1_groups[] = {
1961 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1962 };
1963 static const char *jz4780_mmc2_groups[] = {
1964 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1965 };
1966 static const char *jz4780_nemc_groups[] = {
1967 "nemc-data", "nemc-cle-ale", "nemc-addr",
1968 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1969 };
1970 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1971 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1972 static const char *jz4780_i2s_groups[] = {
1973 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1974 };
1975 static const char *jz4780_dmic_groups[] = { "dmic", };
1976 static const char *jz4780_cim_groups[] = { "cim-data", };
1977 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1978
1979 static const struct function_desc jz4780_functions[] = {
1980 INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1981 INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1982 INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),
1983 INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1984 INGENIC_PIN_FUNCTION("uart4", jz4780_uart4),
1985 INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0),
1986 INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1),
1987 INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0),
1988 INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1),
1989 INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2),
1990 INGENIC_PIN_FUNCTION("nemc", jz4780_nemc),
1991 INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1992 INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1993 INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1994 INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1995 INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1996 INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1997 INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1998 INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1999 INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
2000 INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3),
2001 INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4),
2002 INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),
2003 INGENIC_PIN_FUNCTION("dmic", jz4780_dmic),
2004 INGENIC_PIN_FUNCTION("cim", jz4780_cim),
2005 INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
2006 INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
2007 INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
2008 INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
2009 INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
2010 INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
2011 INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
2012 INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
2013 INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
2014 INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
2015 };
2016
2017 static const struct ingenic_chip_info jz4780_chip_info = {
2018 .num_chips = 6,
2019 .reg_offset = 0x100,
2020 .version = ID_JZ4780,
2021 .groups = jz4780_groups,
2022 .num_groups = ARRAY_SIZE(jz4780_groups),
2023 .functions = jz4780_functions,
2024 .num_functions = ARRAY_SIZE(jz4780_functions),
2025 .pull_ups = jz4780_pull_ups,
2026 .pull_downs = jz4780_pull_downs,
2027 };
2028
2029 static const u32 x1000_pull_ups[4] = {
2030 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
2031 };
2032
2033 static const u32 x1000_pull_downs[4] = {
2034 0x00000000, 0x02000000, 0x02000000, 0x00000000,
2035 };
2036
2037 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
2038 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2039 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
2040 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
2041 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
2042 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
2043 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
2044 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
2045 static int x1000_sfc_clk_pins[] = { 0x1a, };
2046 static int x1000_sfc_ce_pins[] = { 0x1b, };
2047 static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
2048 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
2049 static int x1000_ssi_dt_d_pins[] = { 0x62, };
2050 static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
2051 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
2052 static int x1000_ssi_dr_d_pins[] = { 0x63, };
2053 static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
2054 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
2055 static int x1000_ssi_clk_d_pins[] = { 0x60, };
2056 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
2057 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
2058 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
2059 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
2060 static int x1000_ssi_ce0_d_pins[] = { 0x61, };
2061 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
2062 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
2063 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
2064 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
2065 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
2066 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
2067 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
2068 static int x1000_emc_8bit_data_pins[] = {
2069 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2070 };
2071 static int x1000_emc_16bit_data_pins[] = {
2072 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2073 };
2074 static int x1000_emc_addr_pins[] = {
2075 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2076 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2077 };
2078 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
2079 static int x1000_emc_wait_pins[] = { 0x34, };
2080 static int x1000_emc_cs1_pins[] = { 0x32, };
2081 static int x1000_emc_cs2_pins[] = { 0x33, };
2082 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
2083 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
2084 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
2085 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
2086 static int x1000_i2s_data_tx_pins[] = { 0x24, };
2087 static int x1000_i2s_data_rx_pins[] = { 0x23, };
2088 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2089 static int x1000_i2s_sysclk_pins[] = { 0x20, };
2090 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
2091 static int x1000_dmic_if1_pins[] = { 0x25, };
2092 static int x1000_cim_pins[] = {
2093 0x08, 0x09, 0x0a, 0x0b,
2094 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2095 };
2096 static int x1000_lcd_8bit_pins[] = {
2097 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2098 0x30, 0x31, 0x32, 0x33, 0x34,
2099 };
2100 static int x1000_lcd_16bit_pins[] = {
2101 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2102 };
2103 static int x1000_pwm_pwm0_pins[] = { 0x59, };
2104 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
2105 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
2106 static int x1000_pwm_pwm3_pins[] = { 0x26, };
2107 static int x1000_pwm_pwm4_pins[] = { 0x58, };
2108 static int x1000_mac_pins[] = {
2109 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
2110 };
2111
2112 static const struct group_desc x1000_groups[] = {
2113 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2114 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2115 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2116 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2117 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2118 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2119 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2120 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2121 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2122 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2123 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2124 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2125 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2126 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2127 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2128 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2129 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2130 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2131 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2132 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2133 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2134 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2135 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2136 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2137 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2138 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2139 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2140 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2141 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2142 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2143 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2144 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2145 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2146 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2147 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2148 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2149 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2150 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2151 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2152 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2153 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2154 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2155 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2156 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2157 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2158 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2159 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2160 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2161 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2162 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2163 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2164 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
2165 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
2166 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
2167 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2168 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
2169 INGENIC_PIN_GROUP("mac", x1000_mac, 1),
2170 };
2171
2172 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2173 static const char *x1000_uart1_groups[] = {
2174 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2175 };
2176 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2177 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2178 static const char *x1000_ssi_groups[] = {
2179 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2180 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2181 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2182 "ssi-gpc-a-20", "ssi-gpc-a-31",
2183 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2184 "ssi-ce1-a-21", "ssi-ce1-a-30",
2185 };
2186 static const char *x1000_mmc0_groups[] = {
2187 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2188 };
2189 static const char *x1000_mmc1_groups[] = {
2190 "mmc1-1bit", "mmc1-4bit",
2191 };
2192 static const char *x1000_emc_groups[] = {
2193 "emc-8bit-data", "emc-16bit-data",
2194 "emc-addr", "emc-rd-we", "emc-wait",
2195 };
2196 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2197 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2198 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2199 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2200 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2201 static const char *x1000_i2s_groups[] = {
2202 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2203 };
2204 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2205 static const char *x1000_cim_groups[] = { "cim-data", };
2206 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2207 static const char *x1000_pwm0_groups[] = { "pwm0", };
2208 static const char *x1000_pwm1_groups[] = { "pwm1", };
2209 static const char *x1000_pwm2_groups[] = { "pwm2", };
2210 static const char *x1000_pwm3_groups[] = { "pwm3", };
2211 static const char *x1000_pwm4_groups[] = { "pwm4", };
2212 static const char *x1000_mac_groups[] = { "mac", };
2213
2214 static const struct function_desc x1000_functions[] = {
2215 INGENIC_PIN_FUNCTION("uart0", x1000_uart0),
2216 INGENIC_PIN_FUNCTION("uart1", x1000_uart1),
2217 INGENIC_PIN_FUNCTION("uart2", x1000_uart2),
2218 INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2219 INGENIC_PIN_FUNCTION("ssi", x1000_ssi),
2220 INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0),
2221 INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1),
2222 INGENIC_PIN_FUNCTION("emc", x1000_emc),
2223 INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
2224 INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
2225 INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0),
2226 INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1),
2227 INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2),
2228 INGENIC_PIN_FUNCTION("i2s", x1000_i2s),
2229 INGENIC_PIN_FUNCTION("dmic", x1000_dmic),
2230 INGENIC_PIN_FUNCTION("cim", x1000_cim),
2231 INGENIC_PIN_FUNCTION("lcd", x1000_lcd),
2232 INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0),
2233 INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1),
2234 INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2),
2235 INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3),
2236 INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4),
2237 INGENIC_PIN_FUNCTION("mac", x1000_mac),
2238 };
2239
2240 static const struct regmap_range x1000_access_ranges[] = {
2241 regmap_reg_range(0x000, 0x400 - 4),
2242 regmap_reg_range(0x700, 0x800 - 4),
2243 };
2244
2245 /* shared with X1500 */
2246 static const struct regmap_access_table x1000_access_table = {
2247 .yes_ranges = x1000_access_ranges,
2248 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
2249 };
2250
2251 static const struct ingenic_chip_info x1000_chip_info = {
2252 .num_chips = 4,
2253 .reg_offset = 0x100,
2254 .version = ID_X1000,
2255 .groups = x1000_groups,
2256 .num_groups = ARRAY_SIZE(x1000_groups),
2257 .functions = x1000_functions,
2258 .num_functions = ARRAY_SIZE(x1000_functions),
2259 .pull_ups = x1000_pull_ups,
2260 .pull_downs = x1000_pull_downs,
2261 .access_table = &x1000_access_table,
2262 };
2263
2264 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
2265 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2266 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
2267 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
2268 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
2269 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
2270 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
2271 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
2272 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
2273 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
2274 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
2275 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
2276 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
2277 static int x1500_i2s_data_tx_pins[] = { 0x24, };
2278 static int x1500_i2s_data_rx_pins[] = { 0x23, };
2279 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2280 static int x1500_i2s_sysclk_pins[] = { 0x20, };
2281 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
2282 static int x1500_dmic_if1_pins[] = { 0x25, };
2283 static int x1500_cim_pins[] = {
2284 0x08, 0x09, 0x0a, 0x0b,
2285 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2286 };
2287 static int x1500_pwm_pwm0_pins[] = { 0x59, };
2288 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
2289 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
2290 static int x1500_pwm_pwm3_pins[] = { 0x26, };
2291 static int x1500_pwm_pwm4_pins[] = { 0x58, };
2292
2293 static const struct group_desc x1500_groups[] = {
2294 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2295 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2296 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2297 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2298 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2299 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2300 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2301 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2302 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2303 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2304 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2305 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2306 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2307 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2308 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2309 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2310 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2311 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2312 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2313 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2314 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2315 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2316 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2317 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
2318 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
2319 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
2320 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2321 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
2322 };
2323
2324 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2325 static const char *x1500_uart1_groups[] = {
2326 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2327 };
2328 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2329 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2330 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2331 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2332 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2333 static const char *x1500_i2s_groups[] = {
2334 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2335 };
2336 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2337 static const char *x1500_cim_groups[] = { "cim-data", };
2338 static const char *x1500_pwm0_groups[] = { "pwm0", };
2339 static const char *x1500_pwm1_groups[] = { "pwm1", };
2340 static const char *x1500_pwm2_groups[] = { "pwm2", };
2341 static const char *x1500_pwm3_groups[] = { "pwm3", };
2342 static const char *x1500_pwm4_groups[] = { "pwm4", };
2343
2344 static const struct function_desc x1500_functions[] = {
2345 INGENIC_PIN_FUNCTION("uart0", x1500_uart0),
2346 INGENIC_PIN_FUNCTION("uart1", x1500_uart1),
2347 INGENIC_PIN_FUNCTION("uart2", x1500_uart2),
2348 INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2349 INGENIC_PIN_FUNCTION("mmc", x1500_mmc),
2350 INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0),
2351 INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1),
2352 INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2),
2353 INGENIC_PIN_FUNCTION("i2s", x1500_i2s),
2354 INGENIC_PIN_FUNCTION("dmic", x1500_dmic),
2355 INGENIC_PIN_FUNCTION("cim", x1500_cim),
2356 INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0),
2357 INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1),
2358 INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2),
2359 INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3),
2360 INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4),
2361 };
2362
2363 static const struct ingenic_chip_info x1500_chip_info = {
2364 .num_chips = 4,
2365 .reg_offset = 0x100,
2366 .version = ID_X1500,
2367 .groups = x1500_groups,
2368 .num_groups = ARRAY_SIZE(x1500_groups),
2369 .functions = x1500_functions,
2370 .num_functions = ARRAY_SIZE(x1500_functions),
2371 .pull_ups = x1000_pull_ups,
2372 .pull_downs = x1000_pull_downs,
2373 .access_table = &x1000_access_table,
2374 };
2375
2376 static const u32 x1600_pull_ups[4] = {
2377 0xffffffff, 0xdffbf7bf, 0x987e0000, 0x0000003f,
2378 };
2379
2380 static const u32 x1600_pull_downs[4] = {
2381 0x00000000, 0x00000000, 0x07000007, 0x00000000,
2382 };
2383
2384 static int x1600_uart0_data_pins[] = { 0x27, 0x28, };
2385 static int x1600_uart0_hwflow_pins[] = { 0x29, 0x2a, };
2386 static int x1600_uart1_data_pins[] = { 0x23, 0x22, };
2387 static int x1600_uart1_hwflow_pins[] = { 0x25, 0x24, };
2388 static int x1600_uart2_data_a_pins[] = { 0x1f, 0x1e, };
2389 static int x1600_uart2_data_b_pins[] = { 0x21, 0x20, };
2390 static int x1600_uart3_data_b_pins[] = { 0x25, 0x24, };
2391 static int x1600_uart3_data_d_pins[] = { 0x65, 0x64, };
2392 static int x1600_sfc_pins[] = { 0x53, 0x54, 0x55, 0x56, 0x51, 0x52, 0x24, };
2393 static int x1600_ssi_dt_a_pins[] = { 0x1e, };
2394 static int x1600_ssi_dt_b_pins[] = { 0x2d, };
2395 static int x1600_ssi_dr_a_pins[] = { 0x1d, };
2396 static int x1600_ssi_dr_b_pins[] = { 0x2e, };
2397 static int x1600_ssi_clk_a_pins[] = { 0x1f, };
2398 static int x1600_ssi_clk_b_pins[] = { 0x2c, };
2399 static int x1600_ssi_ce0_a_pins[] = { 0x1c, };
2400 static int x1600_ssi_ce0_b_pins[] = { 0x31, };
2401 static int x1600_ssi_ce1_a_pins[] = { 0x22, };
2402 static int x1600_ssi_ce1_b_pins[] = { 0x30, };
2403 static int x1600_mmc0_1bit_b_pins[] = { 0x2c, 0x2d, 0x2e, };
2404 static int x1600_mmc0_4bit_b_pins[] = { 0x2f, 0x30, 0x31, };
2405 static int x1600_mmc0_1bit_c_pins[] = { 0x51, 0x53, 0x54, };
2406 static int x1600_mmc0_4bit_c_pins[] = { 0x56, 0x55, 0x52, };
2407 static int x1600_mmc1_1bit_pins[] = { 0x60, 0x61, 0x62, };
2408 static int x1600_mmc1_4bit_pins[] = { 0x63, 0x64, 0x65, };
2409 static int x1600_i2c0_a_pins[] = { 0x1d, 0x1c, };
2410 static int x1600_i2c0_b_pins[] = { 0x3f, 0x3e, };
2411 static int x1600_i2c1_b_15_pins[] = { 0x30, 0x2f, };
2412 static int x1600_i2c1_b_19_pins[] = { 0x34, 0x33, };
2413 static int x1600_i2s_data_tx_pins[] = { 0x39, };
2414 static int x1600_i2s_data_rx_pins[] = { 0x35, };
2415 static int x1600_i2s_clk_rx_pins[] = { 0x37, 0x38, };
2416 static int x1600_i2s_clk_tx_pins[] = { 0x3b, 0x3c, };
2417 static int x1600_i2s_sysclk_pins[] = { 0x36, 0x3a, };
2418
2419 static int x1600_cim_pins[] = {
2420 0x14, 0x16, 0x15, 0x18, 0x13,
2421 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2422 };
2423
2424 static int x1600_slcd_8bit_pins[] = {
2425 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2426 0x17, 0x19, 0x1a, 0x1b,
2427 };
2428
2429 static int x1600_slcd_16bit_pins[] = {
2430 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2431 };
2432
2433 static int x1600_lcd_16bit_pins[] = {
2434 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2435 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2436 0x18, 0x19, 0x1a, 0x1b,
2437 };
2438
2439 static int x1600_lcd_18bit_pins[] = {
2440 0x10, 0x11,
2441 };
2442
2443 static int x1600_lcd_24bit_pins[] = {
2444 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
2445 };
2446
2447 static int x1600_pwm_pwm0_pins[] = { 0x40, };
2448 static int x1600_pwm_pwm1_pins[] = { 0x41, };
2449 static int x1600_pwm_pwm2_pins[] = { 0x42, };
2450 static int x1600_pwm_pwm3_pins[] = { 0x58, };
2451 static int x1600_pwm_pwm4_pins[] = { 0x59, };
2452 static int x1600_pwm_pwm5_b_pins[] = { 0x33, };
2453 static int x1600_pwm_pwm5_c_pins[] = { 0x5a, };
2454 static int x1600_pwm_pwm6_b9_pins[] = { 0x29, };
2455 static int x1600_pwm_pwm6_b20_pins[] = { 0x34, };
2456 static int x1600_pwm_pwm7_b10_pins[] = { 0x2a, };
2457 static int x1600_pwm_pwm7_b21_pins[] = { 0x35, };
2458
2459 static int x1600_mac_pins[] = {
2460 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c,
2461 };
2462
2463 static int x1600_sfc_funcs[] = { 0, 0, 0, 0, 0, 0, 2, };
2464
2465 static const struct group_desc x1600_groups[] = {
2466 INGENIC_PIN_GROUP("uart0-data", x1600_uart0_data, 0),
2467 INGENIC_PIN_GROUP("uart0-hwflow", x1600_uart0_hwflow, 0),
2468 INGENIC_PIN_GROUP("uart1-data", x1600_uart1_data, 1),
2469 INGENIC_PIN_GROUP("uart1-hwflow", x1600_uart1_hwflow, 1),
2470 INGENIC_PIN_GROUP("uart2-data-a", x1600_uart2_data_a, 2),
2471 INGENIC_PIN_GROUP("uart2-data-b", x1600_uart2_data_b, 1),
2472 INGENIC_PIN_GROUP("uart3-data-b", x1600_uart3_data_b, 0),
2473 INGENIC_PIN_GROUP("uart3-data-d", x1600_uart3_data_d, 2),
2474 INGENIC_PIN_GROUP_FUNCS("sfc", x1600_sfc, x1600_sfc_funcs),
2475 INGENIC_PIN_GROUP("ssi-dt-a", x1600_ssi_dt_a, 0),
2476 INGENIC_PIN_GROUP("ssi-dt-b", x1600_ssi_dt_b, 1),
2477 INGENIC_PIN_GROUP("ssi-dr-a", x1600_ssi_dr_a, 0),
2478 INGENIC_PIN_GROUP("ssi-dr-b", x1600_ssi_dr_b, 1),
2479 INGENIC_PIN_GROUP("ssi-clk-a", x1600_ssi_clk_a, 0),
2480 INGENIC_PIN_GROUP("ssi-clk-b", x1600_ssi_clk_b, 1),
2481 INGENIC_PIN_GROUP("ssi-ce0-a", x1600_ssi_ce0_a, 0),
2482 INGENIC_PIN_GROUP("ssi-ce0-b", x1600_ssi_ce0_b, 1),
2483 INGENIC_PIN_GROUP("ssi-ce1-a", x1600_ssi_ce1_a, 2),
2484 INGENIC_PIN_GROUP("ssi-ce1-b", x1600_ssi_ce1_b, 1),
2485 INGENIC_PIN_GROUP("mmc0-1bit-b", x1600_mmc0_1bit_b, 0),
2486 INGENIC_PIN_GROUP("mmc0-4bit-b", x1600_mmc0_4bit_b, 0),
2487 INGENIC_PIN_GROUP("mmc0-1bit-c", x1600_mmc0_1bit_c, 1),
2488 INGENIC_PIN_GROUP("mmc0-4bit-c", x1600_mmc0_4bit_c, 1),
2489 INGENIC_PIN_GROUP("mmc1-1bit", x1600_mmc1_1bit, 0),
2490 INGENIC_PIN_GROUP("mmc1-4bit", x1600_mmc1_4bit, 0),
2491 INGENIC_PIN_GROUP("i2c0-data-a", x1600_i2c0_a, 2),
2492 INGENIC_PIN_GROUP("i2c0-data-b", x1600_i2c0_b, 0),
2493 INGENIC_PIN_GROUP("i2c1-data-b-15", x1600_i2c1_b_15, 2),
2494 INGENIC_PIN_GROUP("i2c1-data-b-19", x1600_i2c1_b_19, 0),
2495 INGENIC_PIN_GROUP("i2s-data-tx", x1600_i2s_data_tx, 0),
2496 INGENIC_PIN_GROUP("i2s-data-rx", x1600_i2s_data_rx, 0),
2497 INGENIC_PIN_GROUP("i2s-clk-rx", x1600_i2s_clk_rx, 0),
2498 INGENIC_PIN_GROUP("i2s-clk-tx", x1600_i2s_clk_tx, 0),
2499 INGENIC_PIN_GROUP("i2s-sysclk", x1600_i2s_sysclk, 0),
2500 INGENIC_PIN_GROUP("cim-data", x1600_cim, 2),
2501 INGENIC_PIN_GROUP("slcd-8bit", x1600_slcd_8bit, 1),
2502 INGENIC_PIN_GROUP("slcd-16bit", x1600_slcd_16bit, 1),
2503 INGENIC_PIN_GROUP("lcd-16bit", x1600_lcd_16bit, 0),
2504 INGENIC_PIN_GROUP("lcd-18bit", x1600_lcd_18bit, 0),
2505 INGENIC_PIN_GROUP("lcd-24bit", x1600_lcd_24bit, 0),
2506 INGENIC_PIN_GROUP("pwm0", x1600_pwm_pwm0, 0),
2507 INGENIC_PIN_GROUP("pwm1", x1600_pwm_pwm1, 0),
2508 INGENIC_PIN_GROUP("pwm2", x1600_pwm_pwm2, 0),
2509 INGENIC_PIN_GROUP("pwm3", x1600_pwm_pwm3, 1),
2510 INGENIC_PIN_GROUP("pwm4", x1600_pwm_pwm4, 1),
2511 INGENIC_PIN_GROUP("pwm5-b", x1600_pwm_pwm5_b, 2),
2512 INGENIC_PIN_GROUP("pwm5-c", x1600_pwm_pwm5_c, 1),
2513 INGENIC_PIN_GROUP("pwm6-b9", x1600_pwm_pwm6_b9, 1),
2514 INGENIC_PIN_GROUP("pwm6-b20", x1600_pwm_pwm6_b20, 2),
2515 INGENIC_PIN_GROUP("pwm7-b10", x1600_pwm_pwm7_b10, 1),
2516 INGENIC_PIN_GROUP("pwm7-b21", x1600_pwm_pwm7_b21, 2),
2517 INGENIC_PIN_GROUP("mac", x1600_mac, 1),
2518 };
2519
2520 static const char * const x1600_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2521 static const char * const x1600_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2522 static const char * const x1600_uart2_groups[] = { "uart2-data-a", "uart2-data-b", };
2523 static const char * const x1600_uart3_groups[] = { "uart3-data-b", "uart3-data-d", };
2524
2525 static const char * const x1600_sfc_groups[] = { "sfc", };
2526
2527 static const char * const x1600_ssi_groups[] = {
2528 "ssi-dt-a", "ssi-dt-b",
2529 "ssi-dr-a", "ssi-dr-b",
2530 "ssi-clk-a", "ssi-clk-b",
2531 "ssi-ce0-a", "ssi-ce0-b",
2532 "ssi-ce1-a", "ssi-ce1-b",
2533 };
2534
2535 static const char * const x1600_mmc0_groups[] = { "mmc0-1bit-b", "mmc0-4bit-b",
2536 "mmc0-1bit-c", "mmc0-4bit-c",
2537 };
2538
2539 static const char * const x1600_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2540
2541 static const char * const x1600_i2c0_groups[] = { "i2c0-data-a", "i2c0-data-b", };
2542 static const char * const x1600_i2c1_groups[] = { "i2c1-data-b-15", "i2c1-data-b-19", };
2543
2544 static const char * const x1600_i2s_groups[] = {
2545 "i2s-data-tx", "i2s-data-rx", "i2s-clk-rx", "i2s-clk-tx", "i2s-sysclk",
2546 };
2547
2548 static const char * const x1600_cim_groups[] = { "cim-data", };
2549
2550 static const char * const x1600_lcd_groups[] = { "slcd-8bit", "slcd-16bit",
2551 "lcd-16bit", "lcd-18bit", "lcd-24bit", "lcd-no-pins",
2552 };
2553
2554 static const char * const x1600_pwm0_groups[] = { "pwm0", };
2555 static const char * const x1600_pwm1_groups[] = { "pwm1", };
2556 static const char * const x1600_pwm2_groups[] = { "pwm2", };
2557 static const char * const x1600_pwm3_groups[] = { "pwm3", };
2558 static const char * const x1600_pwm4_groups[] = { "pwm4", };
2559 static const char * const x1600_pwm5_groups[] = { "pwm5-b", "pwm5-c", };
2560 static const char * const x1600_pwm6_groups[] = { "pwm6-b9", "pwm6-b20", };
2561 static const char * const x1600_pwm7_groups[] = { "pwm7-b10", "pwm7-b21", };
2562
2563 static const char * const x1600_mac_groups[] = { "mac", };
2564
2565 static const struct function_desc x1600_functions[] = {
2566 INGENIC_PIN_FUNCTION("uart0", x1600_uart0),
2567 INGENIC_PIN_FUNCTION("uart1", x1600_uart1),
2568 INGENIC_PIN_FUNCTION("uart2", x1600_uart2),
2569 INGENIC_PIN_FUNCTION("uart3", x1600_uart3),
2570 INGENIC_PIN_FUNCTION("sfc", x1600_sfc),
2571 INGENIC_PIN_FUNCTION("ssi", x1600_ssi),
2572 INGENIC_PIN_FUNCTION("mmc0", x1600_mmc0),
2573 INGENIC_PIN_FUNCTION("mmc1", x1600_mmc1),
2574 INGENIC_PIN_FUNCTION("i2c0", x1600_i2c0),
2575 INGENIC_PIN_FUNCTION("i2c1", x1600_i2c1),
2576 INGENIC_PIN_FUNCTION("i2s", x1600_i2s),
2577 INGENIC_PIN_FUNCTION("cim", x1600_cim),
2578 INGENIC_PIN_FUNCTION("lcd", x1600_lcd),
2579 INGENIC_PIN_FUNCTION("pwm0", x1600_pwm0),
2580 INGENIC_PIN_FUNCTION("pwm1", x1600_pwm1),
2581 INGENIC_PIN_FUNCTION("pwm2", x1600_pwm2),
2582 INGENIC_PIN_FUNCTION("pwm3", x1600_pwm3),
2583 INGENIC_PIN_FUNCTION("pwm4", x1600_pwm4),
2584 INGENIC_PIN_FUNCTION("pwm5", x1600_pwm5),
2585 INGENIC_PIN_FUNCTION("pwm6", x1600_pwm6),
2586 INGENIC_PIN_FUNCTION("pwm7", x1600_pwm7),
2587 INGENIC_PIN_FUNCTION("mac", x1600_mac),
2588 };
2589
2590 static const struct ingenic_chip_info x1600_chip_info = {
2591 .num_chips = 4,
2592 .reg_offset = 0x100,
2593 .version = ID_X1600,
2594 .groups = x1600_groups,
2595 .num_groups = ARRAY_SIZE(x1600_groups),
2596 .functions = x1600_functions,
2597 .num_functions = ARRAY_SIZE(x1600_functions),
2598 .pull_ups = x1600_pull_ups,
2599 .pull_downs = x1600_pull_downs,
2600 .access_table = &x1000_access_table,
2601 };
2602
2603 static const u32 x1830_pull_ups[4] = {
2604 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2605 };
2606
2607 static const u32 x1830_pull_downs[4] = {
2608 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2609 };
2610
2611 static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
2612 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
2613 static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
2614 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
2615 static int x1830_sfc_clk_pins[] = { 0x1b, };
2616 static int x1830_sfc_ce_pins[] = { 0x1c, };
2617 static int x1830_ssi0_dt_pins[] = { 0x4c, };
2618 static int x1830_ssi0_dr_pins[] = { 0x4b, };
2619 static int x1830_ssi0_clk_pins[] = { 0x4f, };
2620 static int x1830_ssi0_gpc_pins[] = { 0x4d, };
2621 static int x1830_ssi0_ce0_pins[] = { 0x50, };
2622 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
2623 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
2624 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
2625 static int x1830_ssi1_dr_c_pins[] = { 0x54, };
2626 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
2627 static int x1830_ssi1_clk_c_pins[] = { 0x57, };
2628 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
2629 static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
2630 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
2631 static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
2632 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
2633 static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
2634 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
2635 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
2636 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
2637 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
2638 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
2639 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
2640 static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
2641 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
2642 static int x1830_i2s_data_tx_pins[] = { 0x53, };
2643 static int x1830_i2s_data_rx_pins[] = { 0x54, };
2644 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
2645 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
2646 static int x1830_i2s_sysclk_pins[] = { 0x57, };
2647 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
2648 static int x1830_dmic_if1_pins[] = { 0x5a, };
2649 static int x1830_lcd_tft_8bit_pins[] = {
2650 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
2651 0x68, 0x73, 0x72, 0x69,
2652 };
2653 static int x1830_lcd_tft_24bit_pins[] = {
2654 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
2655 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
2656 };
2657 static int x1830_lcd_slcd_8bit_pins[] = {
2658 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
2659 0x69, 0x72, 0x73, 0x7b, 0x7a,
2660 };
2661 static int x1830_lcd_slcd_16bit_pins[] = {
2662 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
2663 };
2664 static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
2665 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
2666 static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
2667 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
2668 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
2669 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
2670 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
2671 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
2672 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
2673 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
2674 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
2675 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
2676 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
2677 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
2678 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
2679 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
2680 static int x1830_mac_pins[] = {
2681 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
2682 };
2683
2684 static const struct group_desc x1830_groups[] = {
2685 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2686 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2687 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2688 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2689 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2690 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2691 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2692 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2693 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2694 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2695 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2696 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2697 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2698 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2699 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2700 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2701 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2702 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2703 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2704 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2705 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2706 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2707 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2708 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2709 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2710 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2711 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2712 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2713 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2714 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2715 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2716 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2717 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2718 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2719 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2720 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2721 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2722 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2723 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2724 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2725 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2726 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2727 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2728 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2729 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2730 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2731 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2732 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2733 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2734 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2735 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2736 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2737 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2738 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2739 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2740 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2741 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2742 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2743 INGENIC_PIN_GROUP("mac", x1830_mac, 0),
2744 };
2745
2746 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2747 static const char *x1830_uart1_groups[] = { "uart1-data", };
2748 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2749 static const char *x1830_ssi0_groups[] = {
2750 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2751 };
2752 static const char *x1830_ssi1_groups[] = {
2753 "ssi1-dt-c", "ssi1-dt-d",
2754 "ssi1-dr-c", "ssi1-dr-d",
2755 "ssi1-clk-c", "ssi1-clk-d",
2756 "ssi1-gpc-c", "ssi1-gpc-d",
2757 "ssi1-ce0-c", "ssi1-ce0-d",
2758 "ssi1-ce1-c", "ssi1-ce1-d",
2759 };
2760 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2761 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2762 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2763 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2764 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2765 static const char *x1830_i2s_groups[] = {
2766 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2767 };
2768 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2769 static const char *x1830_lcd_groups[] = {
2770 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2771 };
2772 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2773 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2774 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2775 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2776 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2777 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2778 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2779 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2780 static const char *x1830_mac_groups[] = { "mac", };
2781
2782 static const struct function_desc x1830_functions[] = {
2783 INGENIC_PIN_FUNCTION("uart0", x1830_uart0),
2784 INGENIC_PIN_FUNCTION("uart1", x1830_uart1),
2785 INGENIC_PIN_FUNCTION("sfc", x1830_sfc),
2786 INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0),
2787 INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1),
2788 INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0),
2789 INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1),
2790 INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0),
2791 INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1),
2792 INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2),
2793 INGENIC_PIN_FUNCTION("i2s", x1830_i2s),
2794 INGENIC_PIN_FUNCTION("dmic", x1830_dmic),
2795 INGENIC_PIN_FUNCTION("lcd", x1830_lcd),
2796 INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0),
2797 INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1),
2798 INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2),
2799 INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3),
2800 INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4),
2801 INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5),
2802 INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6),
2803 INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7),
2804 INGENIC_PIN_FUNCTION("mac", x1830_mac),
2805 };
2806
2807 static const struct regmap_range x1830_access_ranges[] = {
2808 regmap_reg_range(0x0000, 0x4000 - 4),
2809 regmap_reg_range(0x7000, 0x8000 - 4),
2810 };
2811
2812 static const struct regmap_access_table x1830_access_table = {
2813 .yes_ranges = x1830_access_ranges,
2814 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
2815 };
2816
2817 static const struct ingenic_chip_info x1830_chip_info = {
2818 .num_chips = 4,
2819 .reg_offset = 0x1000,
2820 .version = ID_X1830,
2821 .groups = x1830_groups,
2822 .num_groups = ARRAY_SIZE(x1830_groups),
2823 .functions = x1830_functions,
2824 .num_functions = ARRAY_SIZE(x1830_functions),
2825 .pull_ups = x1830_pull_ups,
2826 .pull_downs = x1830_pull_downs,
2827 .access_table = &x1830_access_table,
2828 };
2829
2830 static const u32 x2000_pull_ups[5] = {
2831 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
2832 };
2833
2834 static const u32 x2000_pull_downs[5] = {
2835 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
2836 };
2837
2838 static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
2839 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
2840 static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
2841 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
2842 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
2843 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
2844 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
2845 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
2846 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
2847 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
2848 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
2849 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
2850 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
2851 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
2852 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
2853 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
2854 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
2855 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
2856 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
2857 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
2858 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
2859 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
2860 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
2861 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2862 static int x2000_sfc_clk_d_pins[] = { 0x71, };
2863 static int x2000_sfc_clk_e_pins[] = { 0x90, };
2864 static int x2000_sfc_ce_d_pins[] = { 0x72, };
2865 static int x2000_sfc_ce_e_pins[] = { 0x91, };
2866 static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
2867 static int x2000_ssi0_dt_d_pins[] = { 0x69, };
2868 static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
2869 static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
2870 static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
2871 static int x2000_ssi0_clk_d_pins[] = { 0x68, };
2872 static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
2873 static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
2874 static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
2875 static int x2000_ssi1_dt_d_pins[] = { 0x72, };
2876 static int x2000_ssi1_dt_e_pins[] = { 0x91, };
2877 static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
2878 static int x2000_ssi1_dr_d_pins[] = { 0x73, };
2879 static int x2000_ssi1_dr_e_pins[] = { 0x92, };
2880 static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
2881 static int x2000_ssi1_clk_d_pins[] = { 0x71, };
2882 static int x2000_ssi1_clk_e_pins[] = { 0x90, };
2883 static int x2000_ssi1_ce_c_pins[] = { 0x49, };
2884 static int x2000_ssi1_ce_d_pins[] = { 0x76, };
2885 static int x2000_ssi1_ce_e_pins[] = { 0x95, };
2886 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
2887 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
2888 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2889 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
2890 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
2891 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
2892 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
2893 static int x2000_emc_8bit_data_pins[] = {
2894 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2895 };
2896 static int x2000_emc_16bit_data_pins[] = {
2897 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
2898 };
2899 static int x2000_emc_addr_pins[] = {
2900 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2901 0x28, 0x29, 0x2a, 0x2b, 0x2c,
2902 };
2903 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
2904 static int x2000_emc_wait_pins[] = { 0x2f, };
2905 static int x2000_emc_cs1_pins[] = { 0x57, };
2906 static int x2000_emc_cs2_pins[] = { 0x58, };
2907 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
2908 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
2909 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
2910 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
2911 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
2912 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
2913 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
2914 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
2915 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
2916 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
2917 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
2918 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
2919 static int x2000_i2s1_data_tx_pins[] = { 0x47, };
2920 static int x2000_i2s1_data_rx_pins[] = { 0x44, };
2921 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
2922 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
2923 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
2924 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
2925 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
2926 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
2927 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
2928 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
2929 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
2930 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
2931 static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
2932 static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
2933 static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
2934 static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
2935 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
2936 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
2937 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
2938 static int x2000_dmic_if1_pins[] = { 0x56, };
2939 static int x2000_dmic_if2_pins[] = { 0x57, };
2940 static int x2000_dmic_if3_pins[] = { 0x58, };
2941 static int x2000_cim_8bit_pins[] = {
2942 0x0e, 0x0c, 0x0d, 0x4f,
2943 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2944 };
2945 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
2946 static int x2000_lcd_tft_8bit_pins[] = {
2947 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2948 0x38, 0x3a, 0x39, 0x3b,
2949 };
2950 static int x2000_lcd_tft_16bit_pins[] = {
2951 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2952 };
2953 static int x2000_lcd_tft_18bit_pins[] = {
2954 0x30, 0x31,
2955 };
2956 static int x2000_lcd_tft_24bit_pins[] = {
2957 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2958 };
2959 static int x2000_lcd_slcd_8bit_pins[] = {
2960 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2961 0x3a, 0x38, 0x3b, 0x30, 0x39,
2962 };
2963 static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
2964 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
2965 static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
2966 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
2967 static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
2968 static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
2969 static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
2970 static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
2971 static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
2972 static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
2973 static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
2974 static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
2975 static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
2976 static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
2977 static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
2978 static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
2979 static int x2000_pwm_pwm8_pins[] = { 0x48, };
2980 static int x2000_pwm_pwm9_pins[] = { 0x49, };
2981 static int x2000_pwm_pwm10_pins[] = { 0x4a, };
2982 static int x2000_pwm_pwm11_pins[] = { 0x4b, };
2983 static int x2000_pwm_pwm12_pins[] = { 0x4c, };
2984 static int x2000_pwm_pwm13_pins[] = { 0x4d, };
2985 static int x2000_pwm_pwm14_pins[] = { 0x4e, };
2986 static int x2000_pwm_pwm15_pins[] = { 0x4f, };
2987 static int x2000_mac0_rmii_pins[] = {
2988 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
2989 };
2990 static int x2000_mac0_rgmii_pins[] = {
2991 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
2992 0x4c, 0x4d, 0x4f, 0x4e, 0x41,
2993 };
2994 static int x2000_mac1_rmii_pins[] = {
2995 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
2996 };
2997 static int x2000_mac1_rgmii_pins[] = {
2998 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
2999 0x33, 0x34, 0x36, 0x35, 0x37,
3000 };
3001 static int x2000_otg_pins[] = { 0x96, };
3002
3003 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
3004
3005 static const struct group_desc x2000_groups[] = {
3006 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3007 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3008 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3009 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3010 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3011 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3012 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3013 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3014 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3015 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3016 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3017 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3018 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3019 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3020 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3021 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3022 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3023 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3024 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3025 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3026 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3027 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3028 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3029 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3030 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3031 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3032 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3033 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3034 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3035 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3036 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3037 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3038 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3039 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3040 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3041 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3042 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3043 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3044 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3045 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3046 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3047 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3048 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3049 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3050 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3051 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3052 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3053 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3054 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3055 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3056 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3057 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3058 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3059 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3060 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3061 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3062 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3063 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3064 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3065 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3066 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3067 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3068 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3069 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3070 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3071 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3072 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3073 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3074 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3075 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3076 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3077 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3078 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3079 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3080 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3081 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3082 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3083 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3084 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3085 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3086 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3087 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3088 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3089 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3090 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3091 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3092 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3093 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3094 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3095 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3096 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3097 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3098 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3099 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3100 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3101 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3102 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3103 x2000_cim_8bit_funcs),
3104 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3105 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3106 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3107 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3108 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3109 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3110 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3111 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3112 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3113 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3114 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3115 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3116 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3117 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3118 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3119 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3120 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3121 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3122 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3123 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3124 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3125 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3126 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3127 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3128 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3129 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3130 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3131 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3132 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3133 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3134 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3135 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
3136 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
3137 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
3138 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
3139 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
3140 };
3141
3142 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
3143 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
3144 static const char *x2000_uart2_groups[] = { "uart2-data", };
3145 static const char *x2000_uart3_groups[] = {
3146 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
3147 };
3148 static const char *x2000_uart4_groups[] = {
3149 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
3150 };
3151 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
3152 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
3153 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
3154 static const char *x2000_uart8_groups[] = { "uart8-data", };
3155 static const char *x2000_uart9_groups[] = { "uart9-data", };
3156 static const char *x2000_sfc_groups[] = {
3157 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
3158 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
3159 };
3160 static const char *x2000_ssi0_groups[] = {
3161 "ssi0-dt-b", "ssi0-dt-d",
3162 "ssi0-dr-b", "ssi0-dr-d",
3163 "ssi0-clk-b", "ssi0-clk-d",
3164 "ssi0-ce-b", "ssi0-ce-d",
3165 };
3166 static const char *x2000_ssi1_groups[] = {
3167 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
3168 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
3169 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
3170 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
3171 };
3172 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
3173 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
3174 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
3175 static const char *x2000_emc_groups[] = {
3176 "emc-8bit-data", "emc-16bit-data",
3177 "emc-addr", "emc-rd-we", "emc-wait",
3178 };
3179 static const char *x2000_cs1_groups[] = { "emc-cs1", };
3180 static const char *x2000_cs2_groups[] = { "emc-cs2", };
3181 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
3182 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
3183 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
3184 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
3185 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
3186 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
3187 static const char *x2000_i2s1_groups[] = {
3188 "i2s1-data-tx", "i2s1-data-rx",
3189 "i2s1-clk-tx", "i2s1-clk-rx",
3190 "i2s1-sysclk-tx", "i2s1-sysclk-rx",
3191 };
3192 static const char *x2000_i2s2_groups[] = {
3193 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
3194 "i2s2-clk-rx", "i2s2-sysclk-rx",
3195 };
3196 static const char *x2000_i2s3_groups[] = {
3197 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
3198 "i2s3-clk-tx", "i2s3-sysclk-tx",
3199 };
3200 static const char *x2000_dmic_groups[] = {
3201 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
3202 };
3203 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
3204 static const char *x2000_lcd_groups[] = {
3205 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
3206 "lcd-slcd-8bit", "lcd-slcd-16bit",
3207 };
3208 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
3209 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
3210 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
3211 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
3212 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
3213 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
3214 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
3215 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
3216 static const char *x2000_pwm8_groups[] = { "pwm8", };
3217 static const char *x2000_pwm9_groups[] = { "pwm9", };
3218 static const char *x2000_pwm10_groups[] = { "pwm10", };
3219 static const char *x2000_pwm11_groups[] = { "pwm11", };
3220 static const char *x2000_pwm12_groups[] = { "pwm12", };
3221 static const char *x2000_pwm13_groups[] = { "pwm13", };
3222 static const char *x2000_pwm14_groups[] = { "pwm14", };
3223 static const char *x2000_pwm15_groups[] = { "pwm15", };
3224 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
3225 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
3226 static const char *x2000_otg_groups[] = { "otg-vbus", };
3227
3228 static const struct function_desc x2000_functions[] = {
3229 INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3230 INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3231 INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
3232 INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
3233 INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
3234 INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
3235 INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
3236 INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
3237 INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
3238 INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
3239 INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
3240 INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
3241 INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
3242 INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
3243 INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
3244 INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
3245 INGENIC_PIN_FUNCTION("emc", x2000_emc),
3246 INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3247 INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3248 INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
3249 INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
3250 INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
3251 INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
3252 INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
3253 INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3254 INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3255 INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3256 INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3257 INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3258 INGENIC_PIN_FUNCTION("cim", x2000_cim),
3259 INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3260 INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3261 INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3262 INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3263 INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3264 INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3265 INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3266 INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3267 INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3268 INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3269 INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3270 INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3271 INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3272 INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3273 INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3274 INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3275 INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3276 INGENIC_PIN_FUNCTION("mac0", x2000_mac0),
3277 INGENIC_PIN_FUNCTION("mac1", x2000_mac1),
3278 INGENIC_PIN_FUNCTION("otg", x2000_otg),
3279 };
3280
3281 static const struct regmap_range x2000_access_ranges[] = {
3282 regmap_reg_range(0x000, 0x500 - 4),
3283 regmap_reg_range(0x700, 0x800 - 4),
3284 };
3285
3286 /* shared with X2100 */
3287 static const struct regmap_access_table x2000_access_table = {
3288 .yes_ranges = x2000_access_ranges,
3289 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
3290 };
3291
3292 static const struct ingenic_chip_info x2000_chip_info = {
3293 .num_chips = 5,
3294 .reg_offset = 0x100,
3295 .version = ID_X2000,
3296 .groups = x2000_groups,
3297 .num_groups = ARRAY_SIZE(x2000_groups),
3298 .functions = x2000_functions,
3299 .num_functions = ARRAY_SIZE(x2000_functions),
3300 .pull_ups = x2000_pull_ups,
3301 .pull_downs = x2000_pull_downs,
3302 .access_table = &x2000_access_table,
3303 };
3304
3305 static const u32 x2100_pull_ups[5] = {
3306 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
3307 };
3308
3309 static const u32 x2100_pull_downs[5] = {
3310 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
3311 };
3312
3313 static int x2100_mac_pins[] = {
3314 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
3315 };
3316
3317 static const struct group_desc x2100_groups[] = {
3318 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3319 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3320 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3321 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3322 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3323 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3324 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3325 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3326 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3327 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3328 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3329 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3330 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3331 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3332 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3333 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3334 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3335 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3336 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3337 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3338 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3339 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3340 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3341 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3342 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3343 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3344 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3345 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3346 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3347 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3348 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3349 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3350 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3351 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3352 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3353 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3354 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3355 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3356 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3357 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3358 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3359 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3360 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3361 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3362 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3363 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3364 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3365 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3366 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3367 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3368 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3369 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3370 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3371 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3372 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3373 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3374 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3375 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3376 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3377 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3378 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3379 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3380 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3381 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3382 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3383 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3384 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3385 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3386 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3387 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3388 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3389 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3390 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3391 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3392 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3393 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3394 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3395 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3396 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3397 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3398 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3399 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3400 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3401 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3402 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3403 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3404 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3405 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3406 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3407 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3408 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3409 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3410 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3411 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3412 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3413 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3414 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3415 x2000_cim_8bit_funcs),
3416 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3417 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3418 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3419 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3420 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3421 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3422 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3423 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3424 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3425 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3426 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3427 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3428 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3429 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3430 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3431 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3432 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3433 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3434 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3435 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3436 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3437 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3438 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3439 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3440 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3441 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3442 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3443 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3444 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3445 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3446 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3447 INGENIC_PIN_GROUP("mac", x2100_mac, 1),
3448 };
3449
3450 static const char *x2100_mac_groups[] = { "mac", };
3451
3452 static const struct function_desc x2100_functions[] = {
3453 INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3454 INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3455 INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
3456 INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
3457 INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
3458 INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
3459 INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
3460 INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
3461 INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
3462 INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
3463 INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
3464 INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
3465 INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
3466 INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
3467 INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
3468 INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
3469 INGENIC_PIN_FUNCTION("emc", x2000_emc),
3470 INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3471 INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3472 INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
3473 INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
3474 INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
3475 INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
3476 INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
3477 INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3478 INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3479 INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3480 INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3481 INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3482 INGENIC_PIN_FUNCTION("cim", x2000_cim),
3483 INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3484 INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3485 INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3486 INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3487 INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3488 INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3489 INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3490 INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3491 INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3492 INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3493 INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3494 INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3495 INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3496 INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3497 INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3498 INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3499 INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3500 INGENIC_PIN_FUNCTION("mac", x2100_mac),
3501 };
3502
3503 static const struct ingenic_chip_info x2100_chip_info = {
3504 .num_chips = 5,
3505 .reg_offset = 0x100,
3506 .version = ID_X2100,
3507 .groups = x2100_groups,
3508 .num_groups = ARRAY_SIZE(x2100_groups),
3509 .functions = x2100_functions,
3510 .num_functions = ARRAY_SIZE(x2100_functions),
3511 .pull_ups = x2100_pull_ups,
3512 .pull_downs = x2100_pull_downs,
3513 .access_table = &x2000_access_table,
3514 };
3515
ingenic_gpio_read_reg(struct ingenic_gpio_chip * jzgc,u8 reg)3516 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3517 {
3518 unsigned int val;
3519
3520 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3521
3522 return (u32) val;
3523 }
3524
ingenic_gpio_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3525 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3526 u8 reg, u8 offset, bool set)
3527 {
3528 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3529 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3530 BIT(offset), set ? BIT(offset) : 0);
3531 return;
3532 }
3533
3534 if (set)
3535 reg = REG_SET(reg);
3536 else
3537 reg = REG_CLEAR(reg);
3538
3539 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3540 }
3541
ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3542 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3543 u8 reg, u8 offset, bool set)
3544 {
3545 if (set)
3546 reg = REG_SET(reg);
3547 else
3548 reg = REG_CLEAR(reg);
3549
3550 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3551 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3552 }
3553
ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip * jzgc)3554 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3555 {
3556 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3557 jzgc->jzpc->info->reg_offset),
3558 jzgc->gc.base / PINS_PER_GPIO_CHIP);
3559 }
3560
jz4730_gpio_set_bits(struct ingenic_gpio_chip * jzgc,u8 reg_upper,u8 reg_lower,u8 offset,u8 value)3561 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3562 u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
3563 {
3564 /*
3565 * JZ4730 function and IRQ registers support two-bits-per-pin
3566 * definitions, split into two groups of 16.
3567 */
3568 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3569 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
3570 unsigned int mask = GENMASK(1, 0) << idx * 2;
3571
3572 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3573 }
3574
ingenic_gpio_get_value(struct ingenic_gpio_chip * jzgc,u8 offset)3575 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3576 u8 offset)
3577 {
3578 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3579
3580 return !!(val & BIT(offset));
3581 }
3582
ingenic_gpio_set_value(struct ingenic_gpio_chip * jzgc,u8 offset,int value)3583 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3584 u8 offset, int value)
3585 {
3586 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3587 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3588 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3589 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3590 else
3591 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3592 }
3593
irq_set_type(struct ingenic_gpio_chip * jzgc,u8 offset,unsigned int type)3594 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3595 u8 offset, unsigned int type)
3596 {
3597 u8 reg1, reg2;
3598 bool val1, val2, val3;
3599
3600 switch (type) {
3601 case IRQ_TYPE_EDGE_BOTH:
3602 val1 = val2 = false;
3603 val3 = true;
3604 break;
3605 case IRQ_TYPE_EDGE_RISING:
3606 val1 = val2 = true;
3607 val3 = false;
3608 break;
3609 case IRQ_TYPE_EDGE_FALLING:
3610 val1 = val3 = false;
3611 val2 = true;
3612 break;
3613 case IRQ_TYPE_LEVEL_HIGH:
3614 val1 = true;
3615 val2 = val3 = false;
3616 break;
3617 case IRQ_TYPE_LEVEL_LOW:
3618 default:
3619 val1 = val2 = val3 = false;
3620 break;
3621 }
3622
3623 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
3624 reg1 = JZ4770_GPIO_PAT1;
3625 reg2 = JZ4770_GPIO_PAT0;
3626 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3627 reg1 = JZ4740_GPIO_TRIG;
3628 reg2 = JZ4740_GPIO_DIR;
3629 } else {
3630 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3631 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3632 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
3633 return;
3634 }
3635
3636 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3637 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3638 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3639 ingenic_gpio_shadow_set_bit_load(jzgc);
3640 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3641 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
3642 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3643 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3644 ingenic_gpio_shadow_set_bit_load(jzgc);
3645 } else {
3646 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3647 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3648 }
3649 }
3650
ingenic_gpio_irq_mask(struct irq_data * irqd)3651 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
3652 {
3653 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3654 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3655 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3656
3657 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3658 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3659 else
3660 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3661 }
3662
ingenic_gpio_irq_unmask(struct irq_data * irqd)3663 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
3664 {
3665 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3666 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3667 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3668
3669 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3670 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3671 else
3672 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3673 }
3674
ingenic_gpio_irq_enable(struct irq_data * irqd)3675 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
3676 {
3677 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3678 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3679 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3680
3681 gpiochip_enable_irq(gc, irq);
3682
3683 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3684 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3685 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3686 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3687 else
3688 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3689
3690 ingenic_gpio_irq_unmask(irqd);
3691 }
3692
ingenic_gpio_irq_disable(struct irq_data * irqd)3693 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
3694 {
3695 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3696 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3697 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3698
3699 ingenic_gpio_irq_mask(irqd);
3700
3701 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3702 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3703 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3704 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3705 else
3706 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3707
3708 gpiochip_disable_irq(gc, irq);
3709 }
3710
ingenic_gpio_irq_ack(struct irq_data * irqd)3711 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
3712 {
3713 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3714 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3715 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3716 bool high;
3717
3718 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
3719 !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3720 /*
3721 * Switch to an interrupt for the opposite edge to the one that
3722 * triggered the interrupt being ACKed.
3723 */
3724 high = ingenic_gpio_get_value(jzgc, irq);
3725 if (high)
3726 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3727 else
3728 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3729 }
3730
3731 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3732 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3733 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3734 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3735 else
3736 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3737 }
3738
ingenic_gpio_irq_set_type(struct irq_data * irqd,unsigned int type)3739 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
3740 {
3741 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3742 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3743 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3744
3745 switch (type) {
3746 case IRQ_TYPE_EDGE_BOTH:
3747 case IRQ_TYPE_EDGE_RISING:
3748 case IRQ_TYPE_EDGE_FALLING:
3749 irq_set_handler_locked(irqd, handle_edge_irq);
3750 break;
3751 case IRQ_TYPE_LEVEL_HIGH:
3752 case IRQ_TYPE_LEVEL_LOW:
3753 irq_set_handler_locked(irqd, handle_level_irq);
3754 break;
3755 default:
3756 irq_set_handler_locked(irqd, handle_bad_irq);
3757 }
3758
3759 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3760 /*
3761 * The hardware does not support interrupts on both edges. The
3762 * best we can do is to set up a single-edge interrupt and then
3763 * switch to the opposing edge when ACKing the interrupt.
3764 */
3765 bool high = ingenic_gpio_get_value(jzgc, irq);
3766
3767 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
3768 }
3769
3770 irq_set_type(jzgc, irq, type);
3771 return 0;
3772 }
3773
ingenic_gpio_irq_set_wake(struct irq_data * irqd,unsigned int on)3774 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
3775 {
3776 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3777 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3778
3779 return irq_set_irq_wake(jzgc->irq, on);
3780 }
3781
ingenic_gpio_irq_handler(struct irq_desc * desc)3782 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
3783 {
3784 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3785 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3786 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
3787 unsigned long flag, i;
3788
3789 chained_irq_enter(irq_chip, desc);
3790
3791 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3792 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3793 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3794 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3795 else
3796 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3797
3798 for_each_set_bit(i, &flag, 32)
3799 generic_handle_domain_irq(gc->irq.domain, i);
3800 chained_irq_exit(irq_chip, desc);
3801 }
3802
ingenic_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)3803 static int ingenic_gpio_set(struct gpio_chip *gc, unsigned int offset,
3804 int value)
3805 {
3806 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3807
3808 ingenic_gpio_set_value(jzgc, offset, value);
3809
3810 return 0;
3811 }
3812
ingenic_gpio_get(struct gpio_chip * gc,unsigned int offset)3813 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
3814 {
3815 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3816
3817 return (int) ingenic_gpio_get_value(jzgc, offset);
3818 }
3819
ingenic_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)3820 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
3821 unsigned int offset, int value)
3822 {
3823 ingenic_gpio_set(gc, offset, value);
3824 return pinctrl_gpio_direction_output(gc, offset);
3825 }
3826
ingenic_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg,bool set)3827 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
3828 unsigned int pin, unsigned int reg, bool set)
3829 {
3830 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3831 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3832
3833 if (set) {
3834 if (is_soc_or_above(jzpc, ID_JZ4740))
3835 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3836 REG_SET(reg), BIT(idx));
3837 else
3838 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
3839 reg, BIT(idx));
3840 } else {
3841 if (is_soc_or_above(jzpc, ID_JZ4740))
3842 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3843 REG_CLEAR(reg), BIT(idx));
3844 else
3845 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
3846 reg, BIT(idx));
3847 }
3848 }
3849
ingenic_shadow_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg,bool set)3850 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
3851 unsigned int pin, u8 reg, bool set)
3852 {
3853 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3854
3855 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
3856 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
3857 }
3858
ingenic_shadow_config_pin_load(struct ingenic_pinctrl * jzpc,unsigned int pin)3859 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
3860 unsigned int pin)
3861 {
3862 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
3863 pin / PINS_PER_GPIO_CHIP);
3864 }
3865
jz4730_config_pin_function(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg_upper,u8 reg_lower,u8 value)3866 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
3867 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3868 {
3869 /*
3870 * JZ4730 function and IRQ registers support two-bits-per-pin
3871 * definitions, split into two groups of 16.
3872 */
3873 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
3874 unsigned int mask = GENMASK(1, 0) << idx * 2;
3875 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3876 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3877
3878 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
3879 mask, value << (idx * 2));
3880 }
3881
ingenic_get_pin_config(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg)3882 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
3883 unsigned int pin, unsigned int reg)
3884 {
3885 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3886 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3887 unsigned int val;
3888
3889 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
3890
3891 return val & BIT(idx);
3892 }
3893
ingenic_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)3894 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
3895 {
3896 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3897 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
3898 unsigned int pin = gc->base + offset;
3899
3900 if (is_soc_or_above(jzpc, ID_JZ4770)) {
3901 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
3902 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3903 return GPIO_LINE_DIRECTION_IN;
3904 return GPIO_LINE_DIRECTION_OUT;
3905 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
3906 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
3907 return GPIO_LINE_DIRECTION_IN;
3908 return GPIO_LINE_DIRECTION_OUT;
3909 }
3910
3911 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3912 return GPIO_LINE_DIRECTION_IN;
3913
3914 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
3915 return GPIO_LINE_DIRECTION_OUT;
3916
3917 return GPIO_LINE_DIRECTION_IN;
3918 }
3919
3920 static const struct pinctrl_ops ingenic_pctlops = {
3921 .get_groups_count = pinctrl_generic_get_group_count,
3922 .get_group_name = pinctrl_generic_get_group_name,
3923 .get_group_pins = pinctrl_generic_get_group_pins,
3924 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3925 .dt_free_map = pinconf_generic_dt_free_map,
3926 };
3927
ingenic_gpio_irq_request(struct irq_data * data)3928 static int ingenic_gpio_irq_request(struct irq_data *data)
3929 {
3930 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3931 irq_hw_number_t irq = irqd_to_hwirq(data);
3932 int ret;
3933
3934 ret = pinctrl_gpio_direction_input(gpio_chip, irq);
3935 if (ret)
3936 return ret;
3937
3938 return gpiochip_reqres_irq(gpio_chip, irq);
3939 }
3940
ingenic_gpio_irq_release(struct irq_data * data)3941 static void ingenic_gpio_irq_release(struct irq_data *data)
3942 {
3943 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3944 irq_hw_number_t irq = irqd_to_hwirq(data);
3945
3946 return gpiochip_relres_irq(gpio_chip, irq);
3947 }
3948
ingenic_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)3949 static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
3950 {
3951 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3952
3953 seq_puts(p, gpio_chip->label);
3954 }
3955
3956 static const struct irq_chip ingenic_gpio_irqchip = {
3957 .irq_enable = ingenic_gpio_irq_enable,
3958 .irq_disable = ingenic_gpio_irq_disable,
3959 .irq_unmask = ingenic_gpio_irq_unmask,
3960 .irq_mask = ingenic_gpio_irq_mask,
3961 .irq_ack = ingenic_gpio_irq_ack,
3962 .irq_set_type = ingenic_gpio_irq_set_type,
3963 .irq_set_wake = ingenic_gpio_irq_set_wake,
3964 .irq_request_resources = ingenic_gpio_irq_request,
3965 .irq_release_resources = ingenic_gpio_irq_release,
3966 .irq_print_chip = ingenic_gpio_irq_print_chip,
3967 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
3968 };
3969
ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl * jzpc,int pin,int func)3970 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
3971 int pin, int func)
3972 {
3973 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3974 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3975
3976 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
3977 'A' + offt, idx, func);
3978
3979 if (is_soc_or_above(jzpc, ID_X1000)) {
3980 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3981 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
3982 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3983 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3984 ingenic_shadow_config_pin_load(jzpc, pin);
3985 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3986 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3987 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
3988 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3989 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3990 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3991 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
3992 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
3993 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
3994 } else {
3995 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3996 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
3997 }
3998
3999 return 0;
4000 }
4001
ingenic_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)4002 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
4003 unsigned int selector, unsigned int group)
4004 {
4005 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4006 struct function_desc *func;
4007 struct group_desc *grp;
4008 unsigned int i;
4009 uintptr_t mode;
4010 u8 *pin_modes;
4011
4012 func = pinmux_generic_get_function(pctldev, selector);
4013 if (!func)
4014 return -EINVAL;
4015
4016 grp = pinctrl_generic_get_group(pctldev, group);
4017 if (!grp)
4018 return -EINVAL;
4019
4020 dev_dbg(pctldev->dev, "enable function %s group %s\n",
4021 func->func.name, grp->grp.name);
4022
4023 mode = (uintptr_t)grp->data;
4024 if (mode <= 3) {
4025 for (i = 0; i < grp->grp.npins; i++)
4026 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);
4027 } else {
4028 pin_modes = grp->data;
4029
4030 for (i = 0; i < grp->grp.npins; i++)
4031 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);
4032 }
4033
4034 return 0;
4035 }
4036
ingenic_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)4037 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
4038 struct pinctrl_gpio_range *range,
4039 unsigned int pin, bool input)
4040 {
4041 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4042 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4043 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4044
4045 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
4046 'A' + offt, idx, input ? "in" : "out");
4047
4048 if (is_soc_or_above(jzpc, ID_X1000)) {
4049 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
4050 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
4051 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
4052 ingenic_shadow_config_pin_load(jzpc, pin);
4053 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
4054 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
4055 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
4056 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
4057 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
4058 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
4059 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
4060 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
4061 } else {
4062 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
4063 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
4064 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
4065 }
4066
4067 return 0;
4068 }
4069
4070 static const struct pinmux_ops ingenic_pmxops = {
4071 .get_functions_count = pinmux_generic_get_function_count,
4072 .get_function_name = pinmux_generic_get_function_name,
4073 .get_function_groups = pinmux_generic_get_function_groups,
4074 .set_mux = ingenic_pinmux_set_mux,
4075 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
4076 };
4077
ingenic_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)4078 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
4079 unsigned int pin, unsigned long *config)
4080 {
4081 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4082 enum pin_config_param param = pinconf_to_config_param(*config);
4083 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4084 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4085 unsigned int arg = 1;
4086 unsigned int bias, reg;
4087 bool pull, pullup, pulldown;
4088
4089 if (is_soc_or_above(jzpc, ID_X2000)) {
4090 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
4091 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
4092 (jzpc->info->pull_ups[offt] & BIT(idx));
4093 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
4094 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
4095 (jzpc->info->pull_downs[offt] & BIT(idx));
4096
4097 } else if (is_soc_or_above(jzpc, ID_X1830)) {
4098 unsigned int half = PINS_PER_GPIO_CHIP / 2;
4099 unsigned int idxh = (pin % half) * 2;
4100
4101 if (idx < half)
4102 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
4103 X1830_GPIO_PEL, &bias);
4104 else
4105 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
4106 X1830_GPIO_PEH, &bias);
4107
4108 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
4109
4110 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
4111 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
4112
4113 } else {
4114 if (is_soc_or_above(jzpc, ID_X1600))
4115 pull = ingenic_get_pin_config(jzpc, pin, X1600_GPIO_PU);
4116 else if (is_soc_or_above(jzpc, ID_JZ4770))
4117 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
4118 else if (is_soc_or_above(jzpc, ID_JZ4740))
4119 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
4120 else
4121 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
4122
4123 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
4124 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
4125 }
4126
4127 switch (param) {
4128 case PIN_CONFIG_BIAS_DISABLE:
4129 if (pullup || pulldown)
4130 return -EINVAL;
4131
4132 break;
4133
4134 case PIN_CONFIG_BIAS_PULL_UP:
4135 if (!pullup)
4136 return -EINVAL;
4137
4138 break;
4139
4140 case PIN_CONFIG_BIAS_PULL_DOWN:
4141 if (!pulldown)
4142 return -EINVAL;
4143
4144 break;
4145
4146 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4147 if (is_soc_or_above(jzpc, ID_X2000))
4148 reg = X2000_GPIO_SMT;
4149 else if (is_soc_or_above(jzpc, ID_X1830))
4150 reg = X1830_GPIO_SMT;
4151 else
4152 return -EINVAL;
4153
4154 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
4155 break;
4156
4157 case PIN_CONFIG_SLEW_RATE:
4158 if (is_soc_or_above(jzpc, ID_X2000))
4159 reg = X2000_GPIO_SR;
4160 else if (is_soc_or_above(jzpc, ID_X1830))
4161 reg = X1830_GPIO_SR;
4162 else
4163 return -EINVAL;
4164
4165 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
4166 break;
4167
4168 default:
4169 return -ENOTSUPP;
4170 }
4171
4172 *config = pinconf_to_config_packed(param, arg);
4173 return 0;
4174 }
4175
ingenic_set_bias(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int bias)4176 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
4177 unsigned int pin, unsigned int bias)
4178 {
4179 if (is_soc_or_above(jzpc, ID_X2000)) {
4180 switch (bias) {
4181 case GPIO_PULL_UP:
4182 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
4183 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
4184 break;
4185
4186 case GPIO_PULL_DOWN:
4187 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
4188 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
4189 break;
4190
4191 case GPIO_PULL_DIS:
4192 default:
4193 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
4194 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
4195 }
4196
4197 } else if (is_soc_or_above(jzpc, ID_X1830)) {
4198 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4199 unsigned int half = PINS_PER_GPIO_CHIP / 2;
4200 unsigned int idxh = (pin % half) * 2;
4201 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4202
4203 if (idx < half) {
4204 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
4205 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
4206 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
4207 REG_SET(X1830_GPIO_PEL), bias << idxh);
4208 } else {
4209 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
4210 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
4211 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
4212 REG_SET(X1830_GPIO_PEH), bias << idxh);
4213 }
4214
4215 } else if (is_soc_or_above(jzpc, ID_X1600)) {
4216 ingenic_config_pin(jzpc, pin, X1600_GPIO_PU, bias);
4217 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
4218 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
4219 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
4220 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
4221 } else {
4222 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
4223 }
4224 }
4225
ingenic_set_schmitt_trigger(struct ingenic_pinctrl * jzpc,unsigned int pin,bool enable)4226 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
4227 unsigned int pin, bool enable)
4228 {
4229 if (is_soc_or_above(jzpc, ID_X2000))
4230 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
4231 else
4232 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
4233 }
4234
ingenic_set_output_level(struct ingenic_pinctrl * jzpc,unsigned int pin,bool high)4235 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
4236 unsigned int pin, bool high)
4237 {
4238 if (is_soc_or_above(jzpc, ID_JZ4770))
4239 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
4240 else if (is_soc_or_above(jzpc, ID_JZ4740))
4241 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
4242 else
4243 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
4244 }
4245
ingenic_set_slew_rate(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int slew)4246 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
4247 unsigned int pin, unsigned int slew)
4248 {
4249 if (is_soc_or_above(jzpc, ID_X2000))
4250 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
4251 else
4252 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
4253 }
4254
ingenic_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)4255 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
4256 unsigned long *configs, unsigned int num_configs)
4257 {
4258 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4259 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4260 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4261 unsigned int cfg, arg;
4262 int ret;
4263
4264 for (cfg = 0; cfg < num_configs; cfg++) {
4265 switch (pinconf_to_config_param(configs[cfg])) {
4266 case PIN_CONFIG_BIAS_DISABLE:
4267 case PIN_CONFIG_BIAS_PULL_UP:
4268 case PIN_CONFIG_BIAS_PULL_DOWN:
4269 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4270 case PIN_CONFIG_OUTPUT:
4271 case PIN_CONFIG_SLEW_RATE:
4272 continue;
4273 default:
4274 return -ENOTSUPP;
4275 }
4276 }
4277
4278 for (cfg = 0; cfg < num_configs; cfg++) {
4279 arg = pinconf_to_config_argument(configs[cfg]);
4280
4281 switch (pinconf_to_config_param(configs[cfg])) {
4282 case PIN_CONFIG_BIAS_DISABLE:
4283 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
4284 'A' + offt, idx);
4285 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
4286 break;
4287
4288 case PIN_CONFIG_BIAS_PULL_UP:
4289 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
4290 return -EINVAL;
4291 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
4292 'A' + offt, idx);
4293 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
4294 break;
4295
4296 case PIN_CONFIG_BIAS_PULL_DOWN:
4297 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
4298 return -EINVAL;
4299 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
4300 'A' + offt, idx);
4301 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
4302 break;
4303
4304 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4305 if (!is_soc_or_above(jzpc, ID_X1830))
4306 return -EINVAL;
4307
4308 ingenic_set_schmitt_trigger(jzpc, pin, arg);
4309 break;
4310
4311 case PIN_CONFIG_OUTPUT:
4312 ret = pinctrl_gpio_direction_output(jzpc->gc,
4313 pin - jzpc->gc->base);
4314 if (ret)
4315 return ret;
4316
4317 ingenic_set_output_level(jzpc, pin, arg);
4318 break;
4319
4320 case PIN_CONFIG_SLEW_RATE:
4321 if (!is_soc_or_above(jzpc, ID_X1830))
4322 return -EINVAL;
4323
4324 ingenic_set_slew_rate(jzpc, pin, arg);
4325 break;
4326
4327 default:
4328 /* unreachable */
4329 break;
4330 }
4331 }
4332
4333 return 0;
4334 }
4335
ingenic_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)4336 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
4337 unsigned int group, unsigned long *config)
4338 {
4339 const unsigned int *pins;
4340 unsigned int i, npins, old = 0;
4341 int ret;
4342
4343 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4344 if (ret)
4345 return ret;
4346
4347 for (i = 0; i < npins; i++) {
4348 if (ingenic_pinconf_get(pctldev, pins[i], config))
4349 return -ENOTSUPP;
4350
4351 /* configs do not match between two pins */
4352 if (i && (old != *config))
4353 return -ENOTSUPP;
4354
4355 old = *config;
4356 }
4357
4358 return 0;
4359 }
4360
ingenic_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)4361 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
4362 unsigned int group, unsigned long *configs,
4363 unsigned int num_configs)
4364 {
4365 const unsigned int *pins;
4366 unsigned int i, npins;
4367 int ret;
4368
4369 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4370 if (ret)
4371 return ret;
4372
4373 for (i = 0; i < npins; i++) {
4374 ret = ingenic_pinconf_set(pctldev,
4375 pins[i], configs, num_configs);
4376 if (ret)
4377 return ret;
4378 }
4379
4380 return 0;
4381 }
4382
4383 static const struct pinconf_ops ingenic_confops = {
4384 .is_generic = true,
4385 .pin_config_get = ingenic_pinconf_get,
4386 .pin_config_set = ingenic_pinconf_set,
4387 .pin_config_group_get = ingenic_pinconf_group_get,
4388 .pin_config_group_set = ingenic_pinconf_group_set,
4389 };
4390
4391 static const struct regmap_config ingenic_pinctrl_regmap_config = {
4392 .reg_bits = 32,
4393 .val_bits = 32,
4394 .reg_stride = 4,
4395 };
4396
4397 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
4398 { .compatible = "ingenic,jz4730-gpio" },
4399 { .compatible = "ingenic,jz4740-gpio" },
4400 { .compatible = "ingenic,jz4725b-gpio" },
4401 { .compatible = "ingenic,jz4750-gpio" },
4402 { .compatible = "ingenic,jz4755-gpio" },
4403 { .compatible = "ingenic,jz4760-gpio" },
4404 { .compatible = "ingenic,jz4770-gpio" },
4405 { .compatible = "ingenic,jz4775-gpio" },
4406 { .compatible = "ingenic,jz4780-gpio" },
4407 { .compatible = "ingenic,x1000-gpio" },
4408 { .compatible = "ingenic,x1600-gpio" },
4409 { .compatible = "ingenic,x1830-gpio" },
4410 { .compatible = "ingenic,x2000-gpio" },
4411 { .compatible = "ingenic,x2100-gpio" },
4412 {},
4413 };
4414
ingenic_gpio_probe(struct ingenic_pinctrl * jzpc,struct fwnode_handle * fwnode)4415 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
4416 struct fwnode_handle *fwnode)
4417 {
4418 struct ingenic_gpio_chip *jzgc;
4419 struct device *dev = jzpc->dev;
4420 struct gpio_irq_chip *girq;
4421 unsigned int bank;
4422 int err;
4423
4424 err = fwnode_property_read_u32(fwnode, "reg", &bank);
4425 if (err) {
4426 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
4427 return err;
4428 }
4429
4430 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4431 if (!jzgc)
4432 return -ENOMEM;
4433
4434 jzpc->gc = &jzgc->gc;
4435
4436 jzgc->jzpc = jzpc;
4437 jzgc->reg_base = bank * jzpc->info->reg_offset;
4438
4439 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4440 if (!jzgc->gc.label)
4441 return -ENOMEM;
4442
4443 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
4444 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
4445 * <linux/gpio/consumer.h> INSTEAD.
4446 */
4447 jzgc->gc.base = bank * 32;
4448
4449 jzgc->gc.ngpio = 32;
4450 jzgc->gc.parent = dev;
4451 jzgc->gc.fwnode = fwnode;
4452 jzgc->gc.owner = THIS_MODULE;
4453
4454 jzgc->gc.set_rv = ingenic_gpio_set;
4455 jzgc->gc.get = ingenic_gpio_get;
4456 jzgc->gc.direction_input = pinctrl_gpio_direction_input;
4457 jzgc->gc.direction_output = ingenic_gpio_direction_output;
4458 jzgc->gc.get_direction = ingenic_gpio_get_direction;
4459 jzgc->gc.request = gpiochip_generic_request;
4460 jzgc->gc.free = gpiochip_generic_free;
4461
4462 err = fwnode_irq_get(fwnode, 0);
4463 if (err < 0)
4464 return err;
4465 if (!err)
4466 return -EINVAL;
4467 jzgc->irq = err;
4468
4469 girq = &jzgc->gc.irq;
4470 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
4471 girq->parent_handler = ingenic_gpio_irq_handler;
4472 girq->num_parents = 1;
4473 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
4474 GFP_KERNEL);
4475 if (!girq->parents)
4476 return -ENOMEM;
4477
4478 girq->parents[0] = jzgc->irq;
4479 girq->default_type = IRQ_TYPE_NONE;
4480 girq->handler = handle_level_irq;
4481
4482 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
4483 if (err)
4484 return err;
4485
4486 return 0;
4487 }
4488
ingenic_pinctrl_probe(struct platform_device * pdev)4489 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
4490 {
4491 struct device *dev = &pdev->dev;
4492 struct ingenic_pinctrl *jzpc;
4493 struct pinctrl_desc *pctl_desc;
4494 void __iomem *base;
4495 const struct ingenic_chip_info *chip_info;
4496 struct regmap_config regmap_config;
4497 struct fwnode_handle *fwnode;
4498 unsigned int i;
4499 int err;
4500
4501 chip_info = device_get_match_data(dev);
4502 if (!chip_info) {
4503 dev_err(dev, "Unsupported SoC\n");
4504 return -EINVAL;
4505 }
4506
4507 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
4508 if (!jzpc)
4509 return -ENOMEM;
4510
4511 base = devm_platform_ioremap_resource(pdev, 0);
4512 if (IS_ERR(base))
4513 return PTR_ERR(base);
4514
4515 regmap_config = ingenic_pinctrl_regmap_config;
4516 if (chip_info->access_table) {
4517 regmap_config.rd_table = chip_info->access_table;
4518 regmap_config.wr_table = chip_info->access_table;
4519 } else {
4520 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
4521 }
4522
4523 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config);
4524 if (IS_ERR(jzpc->map)) {
4525 dev_err(dev, "Failed to create regmap\n");
4526 return PTR_ERR(jzpc->map);
4527 }
4528
4529 jzpc->dev = dev;
4530 jzpc->info = chip_info;
4531
4532 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
4533 if (!pctl_desc)
4534 return -ENOMEM;
4535
4536 /* fill in pinctrl_desc structure */
4537 pctl_desc->name = dev_name(dev);
4538 pctl_desc->owner = THIS_MODULE;
4539 pctl_desc->pctlops = &ingenic_pctlops;
4540 pctl_desc->pmxops = &ingenic_pmxops;
4541 pctl_desc->confops = &ingenic_confops;
4542 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
4543 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
4544 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
4545 if (!jzpc->pdesc)
4546 return -ENOMEM;
4547
4548 for (i = 0; i < pctl_desc->npins; i++) {
4549 jzpc->pdesc[i].number = i;
4550 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
4551 'A' + (i / PINS_PER_GPIO_CHIP),
4552 i % PINS_PER_GPIO_CHIP);
4553 }
4554
4555 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
4556 if (IS_ERR(jzpc->pctl)) {
4557 dev_err(dev, "Failed to register pinctrl\n");
4558 return PTR_ERR(jzpc->pctl);
4559 }
4560
4561 for (i = 0; i < chip_info->num_groups; i++) {
4562 const struct group_desc *group = &chip_info->groups[i];
4563 const struct pingroup *grp = &group->grp;
4564
4565 err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,
4566 group->data);
4567 if (err < 0) {
4568 dev_err(dev, "Failed to register group %s\n", grp->name);
4569 return err;
4570 }
4571 }
4572
4573 for (i = 0; i < chip_info->num_functions; i++) {
4574 const struct function_desc *function = &chip_info->functions[i];
4575 const struct pinfunction *func = &function->func;
4576
4577 err = pinmux_generic_add_function(jzpc->pctl, func->name,
4578 func->groups, func->ngroups,
4579 function->data);
4580 if (err < 0) {
4581 dev_err(dev, "Failed to register function %s\n", func->name);
4582 return err;
4583 }
4584 }
4585
4586 dev_set_drvdata(dev, jzpc->map);
4587
4588 device_for_each_child_node(dev, fwnode) {
4589 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
4590 err = ingenic_gpio_probe(jzpc, fwnode);
4591 if (err) {
4592 fwnode_handle_put(fwnode);
4593 return err;
4594 }
4595 }
4596 }
4597
4598 return 0;
4599 }
4600
4601 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
4602
4603 static const struct of_device_id ingenic_pinctrl_of_matches[] = {
4604 {
4605 .compatible = "ingenic,jz4730-pinctrl",
4606 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
4607 },
4608 {
4609 .compatible = "ingenic,jz4740-pinctrl",
4610 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
4611 },
4612 {
4613 .compatible = "ingenic,jz4725b-pinctrl",
4614 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
4615 },
4616 {
4617 .compatible = "ingenic,jz4750-pinctrl",
4618 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
4619 },
4620 {
4621 .compatible = "ingenic,jz4755-pinctrl",
4622 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
4623 },
4624 {
4625 .compatible = "ingenic,jz4760-pinctrl",
4626 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4627 },
4628 {
4629 .compatible = "ingenic,jz4760b-pinctrl",
4630 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4631 },
4632 {
4633 .compatible = "ingenic,jz4770-pinctrl",
4634 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
4635 },
4636 {
4637 .compatible = "ingenic,jz4775-pinctrl",
4638 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
4639 },
4640 {
4641 .compatible = "ingenic,jz4780-pinctrl",
4642 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
4643 },
4644 {
4645 .compatible = "ingenic,x1000-pinctrl",
4646 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4647 },
4648 {
4649 .compatible = "ingenic,x1000e-pinctrl",
4650 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4651 },
4652 {
4653 .compatible = "ingenic,x1500-pinctrl",
4654 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
4655 },
4656 {
4657 .compatible = "ingenic,x1600-pinctrl",
4658 .data = IF_ENABLED(CONFIG_MACH_X1600, &x1600_chip_info)
4659 },
4660 {
4661 .compatible = "ingenic,x1830-pinctrl",
4662 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
4663 },
4664 {
4665 .compatible = "ingenic,x2000-pinctrl",
4666 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4667 },
4668 {
4669 .compatible = "ingenic,x2000e-pinctrl",
4670 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4671 },
4672 {
4673 .compatible = "ingenic,x2100-pinctrl",
4674 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
4675 },
4676 { /* sentinel */ },
4677 };
4678
4679 static struct platform_driver ingenic_pinctrl_driver = {
4680 .driver = {
4681 .name = "pinctrl-ingenic",
4682 .of_match_table = ingenic_pinctrl_of_matches,
4683 },
4684 };
4685
ingenic_pinctrl_drv_register(void)4686 static int __init ingenic_pinctrl_drv_register(void)
4687 {
4688 return platform_driver_probe(&ingenic_pinctrl_driver,
4689 ingenic_pinctrl_probe);
4690 }
4691 subsys_initcall(ingenic_pinctrl_drv_register);
4692