1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for IDT/Renesas 79RC3243x Interrupt Controller */
3
4 #include <linux/bitops.h>
5 #include <linux/gpio/driver.h>
6 #include <linux/gpio/generic.h>
7 #include <linux/irq.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/spinlock.h>
11
12 #define IDT_PIC_IRQ_PEND 0x00
13 #define IDT_PIC_IRQ_MASK 0x08
14
15 #define IDT_GPIO_DIR 0x00
16 #define IDT_GPIO_DATA 0x04
17 #define IDT_GPIO_ILEVEL 0x08
18 #define IDT_GPIO_ISTAT 0x0C
19
20 struct idt_gpio_ctrl {
21 struct gpio_generic_chip chip;
22 void __iomem *pic;
23 void __iomem *gpio;
24 u32 mask_cache;
25 };
26
idt_gpio_dispatch(struct irq_desc * desc)27 static void idt_gpio_dispatch(struct irq_desc *desc)
28 {
29 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
30 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
31 struct irq_chip *host_chip = irq_desc_get_chip(desc);
32 unsigned int bit, virq;
33 unsigned long pending;
34
35 chained_irq_enter(host_chip, desc);
36
37 pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND);
38 pending &= ~ctrl->mask_cache;
39 for_each_set_bit(bit, &pending, gc->ngpio) {
40 virq = irq_find_mapping(gc->irq.domain, bit);
41 if (virq)
42 generic_handle_irq(virq);
43 }
44
45 chained_irq_exit(host_chip, desc);
46 }
47
idt_gpio_irq_set_type(struct irq_data * d,unsigned int flow_type)48 static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
49 {
50 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
51 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
52 unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK;
53 u32 ilevel;
54
55 /* hardware only supports level triggered */
56 if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH))
57 return -EINVAL;
58
59 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
60
61 ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL);
62 if (sense & IRQ_TYPE_LEVEL_HIGH)
63 ilevel |= BIT(d->hwirq);
64 else if (sense & IRQ_TYPE_LEVEL_LOW)
65 ilevel &= ~BIT(d->hwirq);
66
67 writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
68 irq_set_handler_locked(d, handle_level_irq);
69
70 return 0;
71 }
72
idt_gpio_ack(struct irq_data * d)73 static void idt_gpio_ack(struct irq_data *d)
74 {
75 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
76 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
77
78 writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT);
79 }
80
idt_gpio_mask(struct irq_data * d)81 static void idt_gpio_mask(struct irq_data *d)
82 {
83 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
84 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
85
86 scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) {
87 ctrl->mask_cache |= BIT(d->hwirq);
88 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
89 }
90
91 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
92 }
93
idt_gpio_unmask(struct irq_data * d)94 static void idt_gpio_unmask(struct irq_data *d)
95 {
96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
97 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
98
99 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
100
101 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
102
103 ctrl->mask_cache &= ~BIT(d->hwirq);
104 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
105 }
106
idt_gpio_irq_init_hw(struct gpio_chip * gc)107 static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
108 {
109 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
110
111 /* Mask interrupts. */
112 ctrl->mask_cache = 0xffffffff;
113 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
114
115 return 0;
116 }
117
118 static const struct irq_chip idt_gpio_irqchip = {
119 .name = "IDTGPIO",
120 .irq_mask = idt_gpio_mask,
121 .irq_ack = idt_gpio_ack,
122 .irq_unmask = idt_gpio_unmask,
123 .irq_set_type = idt_gpio_irq_set_type,
124 .flags = IRQCHIP_IMMUTABLE,
125 GPIOCHIP_IRQ_RESOURCE_HELPERS,
126 };
127
idt_gpio_probe(struct platform_device * pdev)128 static int idt_gpio_probe(struct platform_device *pdev)
129 {
130 struct gpio_generic_chip_config config;
131 struct device *dev = &pdev->dev;
132 struct gpio_irq_chip *girq;
133 struct idt_gpio_ctrl *ctrl;
134 int parent_irq;
135 int ngpios;
136 int ret;
137
138
139 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
140 if (!ctrl)
141 return -ENOMEM;
142
143 ctrl->gpio = devm_platform_ioremap_resource_byname(pdev, "gpio");
144 if (IS_ERR(ctrl->gpio))
145 return PTR_ERR(ctrl->gpio);
146
147 ctrl->chip.gc.parent = dev;
148
149 config = (struct gpio_generic_chip_config) {
150 .dev = &pdev->dev,
151 .sz = 4,
152 .dat = ctrl->gpio + IDT_GPIO_DATA,
153 .dirout = ctrl->gpio + IDT_GPIO_DIR,
154 };
155
156 ret = gpio_generic_chip_init(&ctrl->chip, &config);
157 if (ret) {
158 dev_err(dev, "failed to initialize the generic GPIO chip\n");
159 return ret;
160 }
161
162 ret = device_property_read_u32(dev, "ngpios", &ngpios);
163 if (!ret)
164 ctrl->chip.gc.ngpio = ngpios;
165
166 if (device_property_read_bool(dev, "interrupt-controller")) {
167 ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic");
168 if (IS_ERR(ctrl->pic))
169 return PTR_ERR(ctrl->pic);
170
171 parent_irq = platform_get_irq(pdev, 0);
172 if (parent_irq < 0)
173 return parent_irq;
174
175 girq = &ctrl->chip.gc.irq;
176 gpio_irq_chip_set_chip(girq, &idt_gpio_irqchip);
177 girq->init_hw = idt_gpio_irq_init_hw;
178 girq->parent_handler = idt_gpio_dispatch;
179 girq->num_parents = 1;
180 girq->parents = devm_kcalloc(dev, girq->num_parents,
181 sizeof(*girq->parents),
182 GFP_KERNEL);
183 if (!girq->parents)
184 return -ENOMEM;
185
186 girq->parents[0] = parent_irq;
187 girq->default_type = IRQ_TYPE_NONE;
188 girq->handler = handle_bad_irq;
189 }
190
191 return devm_gpiochip_add_data(&pdev->dev, &ctrl->chip.gc, ctrl);
192 }
193
194 static const struct of_device_id idt_gpio_of_match[] = {
195 { .compatible = "idt,32434-gpio" },
196 { }
197 };
198 MODULE_DEVICE_TABLE(of, idt_gpio_of_match);
199
200 static struct platform_driver idt_gpio_driver = {
201 .probe = idt_gpio_probe,
202 .driver = {
203 .name = "idt3243x-gpio",
204 .of_match_table = idt_gpio_of_match,
205 },
206 };
207 module_platform_driver(idt_gpio_driver);
208
209 MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver");
210 MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
211 MODULE_LICENSE("GPL");
212