1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001-2024, Intel Corporation
5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "if_igc.h"
32 #include <sys/sbuf.h>
33 #include <machine/_inttypes.h>
34
35 #ifdef RSS
36 #include <net/rss_config.h>
37 #include <netinet/in_rss.h>
38 #endif
39
40 /*********************************************************************
41 * PCI Device ID Table
42 *
43 * Used by probe to select devices to load on
44 * Last entry must be all 0s
45 *
46 * { Vendor ID, Device ID, String }
47 *********************************************************************/
48
49 static const pci_vendor_info_t igc_vendor_info_array[] =
50 {
51 /* Intel(R) PRO/1000 Network Connection - igc */
52 PVID(0x8086, IGC_DEV_ID_I225_LM,
53 "Intel(R) Ethernet Controller I225-LM"),
54 PVID(0x8086, IGC_DEV_ID_I225_V,
55 "Intel(R) Ethernet Controller I225-V"),
56 PVID(0x8086, IGC_DEV_ID_I225_K,
57 "Intel(R) Ethernet Controller I225-K"),
58 PVID(0x8086, IGC_DEV_ID_I225_I,
59 "Intel(R) Ethernet Controller I225-IT"),
60 PVID(0x8086, IGC_DEV_ID_I220_V,
61 "Intel(R) Ethernet Controller I220-V"),
62 PVID(0x8086, IGC_DEV_ID_I225_K2,
63 "Intel(R) Ethernet Controller I225-K(2)"),
64 PVID(0x8086, IGC_DEV_ID_I225_LMVP,
65 "Intel(R) Ethernet Controller I225-LMvP(2)"),
66 PVID(0x8086, IGC_DEV_ID_I226_K,
67 "Intel(R) Ethernet Controller I226-K"),
68 PVID(0x8086, IGC_DEV_ID_I226_LMVP,
69 "Intel(R) Ethernet Controller I226-LMvP"),
70 PVID(0x8086, IGC_DEV_ID_I225_IT,
71 "Intel(R) Ethernet Controller I225-IT(2)"),
72 PVID(0x8086, IGC_DEV_ID_I226_LM,
73 "Intel(R) Ethernet Controller I226-LM"),
74 PVID(0x8086, IGC_DEV_ID_I226_V,
75 "Intel(R) Ethernet Controller I226-V"),
76 PVID(0x8086, IGC_DEV_ID_I226_IT,
77 "Intel(R) Ethernet Controller I226-IT"),
78 PVID(0x8086, IGC_DEV_ID_I221_V,
79 "Intel(R) Ethernet Controller I221-V"),
80 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM,
81 "Intel(R) Ethernet Controller I226(blankNVM)"),
82 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM,
83 "Intel(R) Ethernet Controller I225(blankNVM)"),
84 /* required last entry */
85 PVID_END
86 };
87
88 /*********************************************************************
89 * Function prototypes
90 *********************************************************************/
91 static void *igc_register(device_t);
92 static int igc_if_attach_pre(if_ctx_t);
93 static int igc_if_attach_post(if_ctx_t);
94 static int igc_if_detach(if_ctx_t);
95 static int igc_if_shutdown(if_ctx_t);
96 static int igc_if_suspend(if_ctx_t);
97 static int igc_if_resume(if_ctx_t);
98
99 static int igc_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
100 int);
101 static int igc_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
102 int);
103 static void igc_if_queues_free(if_ctx_t);
104
105 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter);
106 static void igc_if_init(if_ctx_t);
107 static void igc_if_stop(if_ctx_t);
108 static void igc_if_media_status(if_ctx_t, struct ifmediareq *);
109 static int igc_if_media_change(if_ctx_t);
110 static int igc_if_mtu_set(if_ctx_t, uint32_t);
111 static void igc_if_timer(if_ctx_t, uint16_t);
112 static void igc_if_watchdog_reset(if_ctx_t);
113 static bool igc_if_needs_restart(if_ctx_t, enum iflib_restart_event);
114
115 static void igc_identify_hardware(if_ctx_t);
116 static int igc_allocate_pci_resources(if_ctx_t);
117 static void igc_free_pci_resources(if_ctx_t);
118 static void igc_reset(if_ctx_t);
119 static int igc_setup_interface(if_ctx_t);
120 static int igc_setup_msix(if_ctx_t);
121
122 static void igc_initialize_transmit_unit(if_ctx_t);
123 static void igc_initialize_receive_unit(if_ctx_t);
124
125 static void igc_if_intr_enable(if_ctx_t);
126 static void igc_if_intr_disable(if_ctx_t);
127 static int igc_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
128 static int igc_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
129 static void igc_if_multi_set(if_ctx_t);
130 static void igc_if_update_admin_status(if_ctx_t);
131 static void igc_if_debug(if_ctx_t);
132 static void igc_update_stats_counters(struct igc_softc *);
133 static void igc_add_hw_stats(struct igc_softc *);
134 static int igc_if_set_promisc(if_ctx_t, int);
135 static void igc_setup_vlan_hw_support(if_ctx_t);
136 static void igc_fw_version(struct igc_softc *);
137 static void igc_sbuf_fw_version(struct igc_fw_version *, struct sbuf *);
138 static void igc_print_fw_version(struct igc_softc *);
139 static int igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
140 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
141 static void igc_print_nvm_info(struct igc_softc *);
142 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
143 static int igc_get_rs(SYSCTL_HANDLER_ARGS);
144 static void igc_print_debug_info(struct igc_softc *);
145 static int igc_is_valid_ether_addr(u8 *);
146 static void igc_neweitr(struct igc_softc *, struct igc_rx_queue *,
147 struct tx_ring *, struct rx_ring *);
148 static int igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
149 /* Management and WOL Support */
150 static void igc_get_hw_control(struct igc_softc *);
151 static void igc_release_hw_control(struct igc_softc *);
152 static void igc_get_wakeup(if_ctx_t);
153 static void igc_enable_wakeup(if_ctx_t);
154
155 int igc_intr(void *);
156
157 /* MSI-X handlers */
158 static int igc_if_msix_intr_assign(if_ctx_t, int);
159 static int igc_msix_link(void *);
160 static void igc_handle_link(void *context);
161
162 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS);
163 static int igc_sysctl_dmac(SYSCTL_HANDLER_ARGS);
164 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS);
165
166 static int igc_get_regs(SYSCTL_HANDLER_ARGS);
167
168 static void igc_configure_queues(struct igc_softc *);
169
170
171 /*********************************************************************
172 * FreeBSD Device Interface Entry Points
173 *********************************************************************/
174 static device_method_t igc_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_register, igc_register),
177 DEVMETHOD(device_probe, iflib_device_probe),
178 DEVMETHOD(device_attach, iflib_device_attach),
179 DEVMETHOD(device_detach, iflib_device_detach),
180 DEVMETHOD(device_shutdown, iflib_device_shutdown),
181 DEVMETHOD(device_suspend, iflib_device_suspend),
182 DEVMETHOD(device_resume, iflib_device_resume),
183 DEVMETHOD_END
184 };
185
186 static driver_t igc_driver = {
187 "igc", igc_methods, sizeof(struct igc_softc),
188 };
189
190 DRIVER_MODULE(igc, pci, igc_driver, 0, 0);
191
192 MODULE_DEPEND(igc, pci, 1, 1, 1);
193 MODULE_DEPEND(igc, ether, 1, 1, 1);
194 MODULE_DEPEND(igc, iflib, 1, 1, 1);
195
196 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array);
197
198 static device_method_t igc_if_methods[] = {
199 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre),
200 DEVMETHOD(ifdi_attach_post, igc_if_attach_post),
201 DEVMETHOD(ifdi_detach, igc_if_detach),
202 DEVMETHOD(ifdi_shutdown, igc_if_shutdown),
203 DEVMETHOD(ifdi_suspend, igc_if_suspend),
204 DEVMETHOD(ifdi_resume, igc_if_resume),
205 DEVMETHOD(ifdi_init, igc_if_init),
206 DEVMETHOD(ifdi_stop, igc_if_stop),
207 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign),
208 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable),
209 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable),
210 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc),
211 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc),
212 DEVMETHOD(ifdi_queues_free, igc_if_queues_free),
213 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status),
214 DEVMETHOD(ifdi_multi_set, igc_if_multi_set),
215 DEVMETHOD(ifdi_media_status, igc_if_media_status),
216 DEVMETHOD(ifdi_media_change, igc_if_media_change),
217 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set),
218 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc),
219 DEVMETHOD(ifdi_timer, igc_if_timer),
220 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset),
221 DEVMETHOD(ifdi_get_counter, igc_if_get_counter),
222 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable),
223 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable),
224 DEVMETHOD(ifdi_debug, igc_if_debug),
225 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart),
226 DEVMETHOD_END
227 };
228
229 static driver_t igc_if_driver = {
230 "igc_if", igc_if_methods, sizeof(struct igc_softc)
231 };
232
233 /*********************************************************************
234 * Tunable default values.
235 *********************************************************************/
236
237 /* Allow common code without TSO */
238 #ifndef CSUM_TSO
239 #define CSUM_TSO 0
240 #endif
241
242 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
243 "igc driver parameters");
244
245 static int igc_disable_crc_stripping = 0;
246 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
247 &igc_disable_crc_stripping, 0, "Disable CRC Stripping");
248
249 static int igc_smart_pwr_down = false;
250 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN,
251 &igc_smart_pwr_down,
252 0, "Set to true to leave smart power down enabled on newer adapters");
253
254 /* Controls whether promiscuous also shows bad packets */
255 static int igc_debug_sbp = false;
256 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0,
257 "Show bad packets in promiscuous mode");
258
259 /* Energy efficient ethernet - default to OFF */
260 static int igc_eee_setting = 1;
261 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0,
262 "Enable Energy Efficient Ethernet");
263
264 /*
265 * AIM: Adaptive Interrupt Moderation
266 * which means that the interrupt rate is varied over time based on the
267 * traffic for that interrupt vector
268 */
269 static int igc_enable_aim = 1;
270 SYSCTL_INT(_hw_igc, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &igc_enable_aim,
271 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)");
272
273 /*
274 ** Tuneable Interrupt rate
275 */
276 static int igc_max_interrupt_rate = IGC_INTS_DEFAULT;
277 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
278 &igc_max_interrupt_rate, 0, "Maximum interrupts per second");
279
280 extern struct if_txrx igc_txrx;
281
282 static struct if_shared_ctx igc_sctx_init = {
283 .isc_magic = IFLIB_MAGIC,
284 .isc_q_align = PAGE_SIZE,
285 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header),
286 .isc_tx_maxsegsize = PAGE_SIZE,
287 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header),
288 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE,
289 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE,
290 .isc_rx_nsegments = 1,
291 .isc_rx_maxsegsize = MJUM9BYTES,
292 .isc_nfl = 1,
293 .isc_nrxqs = 1,
294 .isc_ntxqs = 1,
295 .isc_admin_intrcnt = 1,
296 .isc_vendor_info = igc_vendor_info_array,
297 .isc_driver_version = "1",
298 .isc_driver = &igc_if_driver,
299 .isc_flags =
300 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
301
302 .isc_nrxd_min = {IGC_MIN_RXD},
303 .isc_ntxd_min = {IGC_MIN_TXD},
304 .isc_nrxd_max = {IGC_MAX_RXD},
305 .isc_ntxd_max = {IGC_MAX_TXD},
306 .isc_nrxd_default = {IGC_DEFAULT_RXD},
307 .isc_ntxd_default = {IGC_DEFAULT_TXD},
308 };
309
310 /*****************************************************************
311 *
312 * Dump Registers
313 *
314 ****************************************************************/
315 #define IGC_REGS_LEN 739
316
igc_get_regs(SYSCTL_HANDLER_ARGS)317 static int igc_get_regs(SYSCTL_HANDLER_ARGS)
318 {
319 struct igc_softc *sc = (struct igc_softc *)arg1;
320 struct igc_hw *hw = &sc->hw;
321 struct sbuf *sb;
322 u32 *regs_buff;
323 int rc;
324
325 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK);
326 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32));
327
328 rc = sysctl_wire_old_buffer(req, 0);
329 MPASS(rc == 0);
330 if (rc != 0) {
331 free(regs_buff, M_DEVBUF);
332 return (rc);
333 }
334
335 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
336 MPASS(sb != NULL);
337 if (sb == NULL) {
338 free(regs_buff, M_DEVBUF);
339 return (ENOMEM);
340 }
341
342 /* General Registers */
343 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL);
344 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS);
345 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT);
346 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR);
347 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL);
348 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0));
349 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0));
350 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0));
351 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0));
352 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0));
353 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0));
354 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL);
355 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0));
356 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0));
357 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0));
358 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0));
359 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0));
360 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0));
361
362 sbuf_printf(sb, "General Registers\n");
363 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
364 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
365 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
366
367 sbuf_printf(sb, "Interrupt Registers\n");
368 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
369
370 sbuf_printf(sb, "RX Registers\n");
371 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
372 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
373 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
374 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
375 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
376 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
377 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
378
379 sbuf_printf(sb, "TX Registers\n");
380 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
381 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
382 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
383 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
384 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
385 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
386 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
387 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
388 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
389 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
390 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
391
392 free(regs_buff, M_DEVBUF);
393
394 #ifdef DUMP_DESCS
395 {
396 if_softc_ctx_t scctx = sc->shared;
397 struct rx_ring *rxr = &rx_que->rxr;
398 struct tx_ring *txr = &tx_que->txr;
399 int ntxd = scctx->isc_ntxd[0];
400 int nrxd = scctx->isc_nrxd[0];
401 int j;
402
403 for (j = 0; j < nrxd; j++) {
404 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
405 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
406 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08"
407 PRIx64 " Error:%d Length:%d\n",
408 j, rxr->rx_base[j].read.buffer_addr, staterr, length);
409 }
410
411 for (j = 0; j < min(ntxd, 256); j++) {
412 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
413
414 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x"
415 "[3]: %08x eop: %d DD=%d\n",
416 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
417 buf->eop != -1 ?
418 txr->tx_base[buf->eop].upper.fields.status &
419 IGC_TXD_STAT_DD : 0);
420
421 }
422 }
423 #endif
424
425 rc = sbuf_finish(sb);
426 sbuf_delete(sb);
427 return(rc);
428 }
429
430 static void *
igc_register(device_t dev)431 igc_register(device_t dev)
432 {
433 return (&igc_sctx_init);
434 }
435
436 static int
igc_set_num_queues(if_ctx_t ctx)437 igc_set_num_queues(if_ctx_t ctx)
438 {
439 int maxqueues;
440
441 maxqueues = 4;
442
443 return (maxqueues);
444 }
445
446 #define IGC_CAPS \
447 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
448 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \
449 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6
450
451 /*********************************************************************
452 * Device initialization routine
453 *
454 * The attach entry point is called when the driver is being loaded.
455 * This routine identifies the type of hardware, allocates all resources
456 * and initializes the hardware.
457 *
458 * return 0 on success, positive on failure
459 *********************************************************************/
460 static int
igc_if_attach_pre(if_ctx_t ctx)461 igc_if_attach_pre(if_ctx_t ctx)
462 {
463 struct igc_softc *sc;
464 if_softc_ctx_t scctx;
465 device_t dev;
466 struct igc_hw *hw;
467 int error = 0;
468
469 INIT_DEBUGOUT("igc_if_attach_pre: begin");
470 dev = iflib_get_dev(ctx);
471 sc = iflib_get_softc(ctx);
472
473 sc->ctx = sc->osdep.ctx = ctx;
474 sc->dev = sc->osdep.dev = dev;
475 scctx = sc->shared = iflib_get_softc_ctx(ctx);
476 sc->media = iflib_get_media(ctx);
477 hw = &sc->hw;
478
479 /* SYSCTL stuff */
480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
482 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
483 sc, 0, igc_sysctl_nvm_info, "I", "NVM Information");
484
485 sc->enable_aim = igc_enable_aim;
486 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
487 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
488 OID_AUTO, "enable_aim", CTLFLAG_RW,
489 &sc->enable_aim, 0,
490 "Interrupt Moderation (1=normal, 2=lowlatency)");
491
492 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
493 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
494 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD,
495 sc, 0, igc_sysctl_print_fw_version, "A",
496 "Prints FW/NVM Versions");
497
498 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
499 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
500 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
501 sc, 0, igc_sysctl_debug_info, "I", "Debug Information");
502
503 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
505 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
506 sc, 0, igc_set_flowcntl, "I", "Flow Control");
507
508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
509 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
510 OID_AUTO, "reg_dump",
511 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
512 igc_get_regs, "A", "Dump Registers");
513
514 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
516 OID_AUTO, "rs_dump",
517 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
518 igc_get_rs, "I", "Dump RS indexes");
519
520 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
522 OID_AUTO, "dmac",
523 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
524 igc_sysctl_dmac, "I", "DMA Coalesce");
525
526 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
527 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
528 OID_AUTO, "tso_tcp_flags_mask_first_segment",
529 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
530 sc, 0, igc_sysctl_tso_tcp_flags_mask, "IU",
531 "TSO TCP flags mask for first segment");
532
533 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
534 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
535 OID_AUTO, "tso_tcp_flags_mask_middle_segment",
536 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
537 sc, 1, igc_sysctl_tso_tcp_flags_mask, "IU",
538 "TSO TCP flags mask for middle segment");
539
540 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
542 OID_AUTO, "tso_tcp_flags_mask_last_segment",
543 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
544 sc, 2, igc_sysctl_tso_tcp_flags_mask, "IU",
545 "TSO TCP flags mask for last segment");
546
547 /* Determine hardware and mac info */
548 igc_identify_hardware(ctx);
549
550 scctx->isc_tx_nsegments = IGC_MAX_SCATTER;
551 scctx->isc_nrxqsets_max =
552 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx);
553 if (bootverbose)
554 device_printf(dev, "attach_pre capping queues at %d\n",
555 scctx->isc_ntxqsets_max);
556
557 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
558 sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN);
559 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
560 sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN);
561 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc);
562 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc);
563 scctx->isc_txrx = &igc_txrx;
564 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER;
565 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE;
566 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE;
567 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS;
568 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
569 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP;
570
571 /*
572 ** Some new devices, as with ixgbe, now may
573 ** use a different BAR, so we need to keep
574 ** track of which is used.
575 */
576 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR);
577 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
578 scctx->isc_msix_bar += 4;
579
580 /* Setup PCI resources */
581 if (igc_allocate_pci_resources(ctx)) {
582 device_printf(dev, "Allocation of PCI resources failed\n");
583 error = ENXIO;
584 goto err_pci;
585 }
586
587 /* Do Shared Code initialization */
588 error = igc_setup_init_funcs(hw, true);
589 if (error) {
590 device_printf(dev, "Setup of Shared code failed, error %d\n",
591 error);
592 error = ENXIO;
593 goto err_pci;
594 }
595
596 igc_setup_msix(ctx);
597 igc_get_bus_info(hw);
598
599 hw->mac.autoneg = DO_AUTO_NEG;
600 hw->phy.autoneg_wait_to_complete = false;
601 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
602
603 /* Copper options */
604 if (hw->phy.media_type == igc_media_type_copper) {
605 hw->phy.mdix = AUTO_ALL_MODES;
606 }
607
608 /*
609 * Set the frame limits assuming
610 * standard ethernet sized frames.
611 */
612 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
613 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
614
615 /* Allocate multicast array memory. */
616 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
617 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
618 if (sc->mta == NULL) {
619 device_printf(dev,
620 "Can not allocate multicast setup array\n");
621 error = ENOMEM;
622 goto err_late;
623 }
624
625 /* Check SOL/IDER usage */
626 if (igc_check_reset_block(hw))
627 device_printf(dev, "PHY reset is blocked"
628 " due to SOL/IDER session.\n");
629
630 /* Sysctl for setting Energy Efficient Ethernet */
631 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting;
632 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
633 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
634 OID_AUTO, "eee_control",
635 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
636 sc, 0, igc_sysctl_eee, "I",
637 "Disable Energy Efficient Ethernet");
638
639 /*
640 ** Start from a known state, this is
641 ** important in reading the nvm and
642 ** mac from that.
643 */
644 igc_reset_hw(hw);
645
646 /* Make sure we have a good EEPROM before we read from it */
647 if (igc_validate_nvm_checksum(hw) < 0) {
648 /*
649 ** Some PCI-E parts fail the first check due to
650 ** the link being in sleep state, call it again,
651 ** if it fails a second time its a real issue.
652 */
653 if (igc_validate_nvm_checksum(hw) < 0) {
654 device_printf(dev,
655 "The EEPROM Checksum Is Not Valid\n");
656 error = EIO;
657 goto err_late;
658 }
659 }
660
661 /* Copy the permanent MAC address out of the EEPROM */
662 if (igc_read_mac_addr(hw) < 0) {
663 device_printf(dev, "EEPROM read error while reading MAC"
664 " address\n");
665 error = EIO;
666 goto err_late;
667 }
668
669 if (!igc_is_valid_ether_addr(hw->mac.addr)) {
670 device_printf(dev, "Invalid MAC address\n");
671 error = EIO;
672 goto err_late;
673 }
674
675 /* Save the EEPROM/NVM versions */
676 igc_fw_version(sc);
677
678 igc_print_fw_version(sc);
679
680 /*
681 * Get Wake-on-Lan and Management info for later use
682 */
683 igc_get_wakeup(ctx);
684
685 /* Enable only WOL MAGIC by default */
686 scctx->isc_capenable &= ~IFCAP_WOL;
687 if (sc->wol != 0)
688 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
689
690 iflib_set_mac(ctx, hw->mac.addr);
691
692 return (0);
693
694 err_late:
695 igc_release_hw_control(sc);
696 err_pci:
697 igc_free_pci_resources(ctx);
698 free(sc->mta, M_DEVBUF);
699
700 return (error);
701 }
702
703 static int
igc_if_attach_post(if_ctx_t ctx)704 igc_if_attach_post(if_ctx_t ctx)
705 {
706 struct igc_softc *sc = iflib_get_softc(ctx);
707 struct igc_hw *hw = &sc->hw;
708 int error = 0;
709
710 /* Setup OS specific network interface */
711 error = igc_setup_interface(ctx);
712 if (error != 0) {
713 goto err_late;
714 }
715
716 igc_reset(ctx);
717
718 /* Initialize statistics */
719 igc_update_stats_counters(sc);
720 hw->mac.get_link_status = true;
721 igc_if_update_admin_status(ctx);
722 igc_add_hw_stats(sc);
723
724 /* the driver can now take control from firmware */
725 igc_get_hw_control(sc);
726
727 INIT_DEBUGOUT("igc_if_attach_post: end");
728
729 return (error);
730
731 err_late:
732 igc_release_hw_control(sc);
733 igc_free_pci_resources(ctx);
734 igc_if_queues_free(ctx);
735 free(sc->mta, M_DEVBUF);
736
737 return (error);
738 }
739
740 /*********************************************************************
741 * Device removal routine
742 *
743 * The detach entry point is called when the driver is being removed.
744 * This routine stops the adapter and deallocates all the resources
745 * that were allocated for driver operation.
746 *
747 * return 0 on success, positive on failure
748 *********************************************************************/
749 static int
igc_if_detach(if_ctx_t ctx)750 igc_if_detach(if_ctx_t ctx)
751 {
752 struct igc_softc *sc = iflib_get_softc(ctx);
753
754 INIT_DEBUGOUT("igc_if_detach: begin");
755
756 igc_phy_hw_reset(&sc->hw);
757
758 igc_release_hw_control(sc);
759 igc_free_pci_resources(ctx);
760
761 return (0);
762 }
763
764 /*********************************************************************
765 *
766 * Shutdown entry point
767 *
768 **********************************************************************/
769
770 static int
igc_if_shutdown(if_ctx_t ctx)771 igc_if_shutdown(if_ctx_t ctx)
772 {
773 return igc_if_suspend(ctx);
774 }
775
776 /*
777 * Suspend/resume device methods.
778 */
779 static int
igc_if_suspend(if_ctx_t ctx)780 igc_if_suspend(if_ctx_t ctx)
781 {
782 struct igc_softc *sc = iflib_get_softc(ctx);
783
784 igc_release_hw_control(sc);
785 igc_enable_wakeup(ctx);
786 return (0);
787 }
788
789 static int
igc_if_resume(if_ctx_t ctx)790 igc_if_resume(if_ctx_t ctx)
791 {
792 igc_if_init(ctx);
793
794 return(0);
795 }
796
797 static int
igc_if_mtu_set(if_ctx_t ctx,uint32_t mtu)798 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
799 {
800 int max_frame_size;
801 struct igc_softc *sc = iflib_get_softc(ctx);
802 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
803
804 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
805
806 /* 9K Jumbo Frame size */
807 max_frame_size = 9234;
808
809 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
810 return (EINVAL);
811 }
812
813 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
814 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
815 return (0);
816 }
817
818 /*********************************************************************
819 * Init entry point
820 *
821 * This routine is used in two ways. It is used by the stack as
822 * init entry point in network interface structure. It is also used
823 * by the driver as a hw/sw initialization routine to get to a
824 * consistent state.
825 *
826 **********************************************************************/
827 static void
igc_if_init(if_ctx_t ctx)828 igc_if_init(if_ctx_t ctx)
829 {
830 struct igc_softc *sc = iflib_get_softc(ctx);
831 if_softc_ctx_t scctx = sc->shared;
832 if_t ifp = iflib_get_ifp(ctx);
833 struct igc_tx_queue *tx_que;
834 int i;
835
836 INIT_DEBUGOUT("igc_if_init: begin");
837
838 /* Get the latest mac address, User can use a LAA */
839 bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
840 ETHER_ADDR_LEN);
841
842 /* Put the address into the Receive Address Array */
843 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0);
844
845 /* Initialize the hardware */
846 igc_reset(ctx);
847 igc_if_update_admin_status(ctx);
848
849 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
850 i++, tx_que++) {
851 struct tx_ring *txr = &tx_que->txr;
852
853 txr->tx_rs_cidx = txr->tx_rs_pidx;
854
855 /* Initialize the last processed descriptor to be the end of
856 * the ring, rather than the start, so that we avoid an
857 * off-by-one error when calculating how many descriptors are
858 * done in the credits_update function.
859 */
860 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
861 }
862
863 /* Setup VLAN support, basic and offload if available */
864 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN);
865
866 /* Prepare transmit descriptors and buffers */
867 igc_initialize_transmit_unit(ctx);
868
869 /* Setup Multicast table */
870 igc_if_multi_set(ctx);
871
872 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
873 igc_initialize_receive_unit(ctx);
874
875 /* Set up VLAN support */
876 igc_setup_vlan_hw_support(ctx);
877
878 /* Don't lose promiscuous settings */
879 igc_if_set_promisc(ctx, if_getflags(ifp));
880 igc_clear_hw_cntrs_base_generic(&sc->hw);
881
882 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
883 igc_configure_queues(sc);
884
885 /* this clears any pending interrupts */
886 IGC_READ_REG(&sc->hw, IGC_ICR);
887 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC);
888
889 /* the driver can now take control from firmware */
890 igc_get_hw_control(sc);
891
892 /* Set Energy Efficient Ethernet */
893 igc_set_eee_i225(&sc->hw, true, true, true);
894 }
895
896 enum eitr_latency_target {
897 eitr_latency_disabled = 0,
898 eitr_latency_lowest = 1,
899 eitr_latency_low = 2,
900 eitr_latency_bulk = 3
901 };
902 /*********************************************************************
903 *
904 * Helper to calculate next EITR value for AIM
905 *
906 *********************************************************************/
907 static void
igc_neweitr(struct igc_softc * sc,struct igc_rx_queue * que,struct tx_ring * txr,struct rx_ring * rxr)908 igc_neweitr(struct igc_softc *sc, struct igc_rx_queue *que,
909 struct tx_ring *txr, struct rx_ring *rxr)
910 {
911 struct igc_hw *hw = &sc->hw;
912 unsigned long bytes, bytes_per_packet, packets;
913 unsigned long rxbytes, rxpackets, txbytes, txpackets;
914 u32 neweitr;
915 u8 nextlatency;
916
917 rxbytes = atomic_load_long(&rxr->rx_bytes);
918 txbytes = atomic_load_long(&txr->tx_bytes);
919
920 /* Idle, do nothing */
921 if (txbytes == 0 && rxbytes == 0)
922 return;
923
924 neweitr = 0;
925
926 if (sc->enable_aim) {
927 nextlatency = rxr->rx_nextlatency;
928
929 /* Use half default (4K) ITR if sub-gig */
930 if (sc->link_speed < 1000) {
931 neweitr = IGC_INTS_4K;
932 goto igc_set_next_eitr;
933 }
934 /* Want at least enough packet buffer for two frames to AIM */
935 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) {
936 neweitr = igc_max_interrupt_rate;
937 sc->enable_aim = 0;
938 goto igc_set_next_eitr;
939 }
940
941 bytes = bytes_per_packet = 0;
942 /* Get largest values from the associated tx and rx ring */
943 txpackets = atomic_load_long(&txr->tx_packets);
944 if (txpackets != 0) {
945 bytes = txbytes;
946 bytes_per_packet = txbytes / txpackets;
947 packets = txpackets;
948 }
949 rxpackets = atomic_load_long(&rxr->rx_packets);
950 if (rxpackets != 0) {
951 bytes = lmax(bytes, rxbytes);
952 bytes_per_packet =
953 lmax(bytes_per_packet, rxbytes / rxpackets);
954 packets = lmax(packets, rxpackets);
955 }
956
957 /* Latency state machine */
958 switch (nextlatency) {
959 case eitr_latency_disabled: /* Bootstrapping */
960 nextlatency = eitr_latency_low;
961 break;
962 case eitr_latency_lowest: /* 70k ints/s */
963 /* TSO and jumbo frames */
964 if (bytes_per_packet > 8000)
965 nextlatency = eitr_latency_bulk;
966 else if ((packets < 5) && (bytes > 512))
967 nextlatency = eitr_latency_low;
968 break;
969 case eitr_latency_low: /* 20k ints/s */
970 if (bytes > 10000) {
971 /* Handle TSO */
972 if (bytes_per_packet > 8000)
973 nextlatency = eitr_latency_bulk;
974 else if ((packets < 10) ||
975 (bytes_per_packet > 1200))
976 nextlatency = eitr_latency_bulk;
977 else if (packets > 35)
978 nextlatency = eitr_latency_lowest;
979 } else if (bytes_per_packet > 2000) {
980 nextlatency = eitr_latency_bulk;
981 } else if (packets < 3 && bytes < 512) {
982 nextlatency = eitr_latency_lowest;
983 }
984 break;
985 case eitr_latency_bulk: /* 4k ints/s */
986 if (bytes > 25000) {
987 if (packets > 35)
988 nextlatency = eitr_latency_low;
989 } else if (bytes < 1500)
990 nextlatency = eitr_latency_low;
991 break;
992 default:
993 nextlatency = eitr_latency_low;
994 device_printf(sc->dev,
995 "Unexpected neweitr transition %d\n",
996 nextlatency);
997 break;
998 }
999
1000 /* Trim itr_latency_lowest for default AIM setting */
1001 if (sc->enable_aim == 1 && nextlatency == eitr_latency_lowest)
1002 nextlatency = eitr_latency_low;
1003
1004 /* Request new latency */
1005 rxr->rx_nextlatency = nextlatency;
1006 } else {
1007 /* We may have toggled to AIM disabled */
1008 nextlatency = eitr_latency_disabled;
1009 rxr->rx_nextlatency = nextlatency;
1010 }
1011
1012 /* ITR state machine */
1013 switch(nextlatency) {
1014 case eitr_latency_lowest:
1015 neweitr = IGC_INTS_70K;
1016 break;
1017 case eitr_latency_low:
1018 neweitr = IGC_INTS_20K;
1019 break;
1020 case eitr_latency_bulk:
1021 neweitr = IGC_INTS_4K;
1022 break;
1023 case eitr_latency_disabled:
1024 default:
1025 neweitr = igc_max_interrupt_rate;
1026 break;
1027 }
1028
1029 igc_set_next_eitr:
1030 neweitr = IGC_INTS_TO_EITR(neweitr);
1031
1032 neweitr |= IGC_EITR_CNT_IGNR;
1033
1034 if (neweitr != que->eitr_setting) {
1035 que->eitr_setting = neweitr;
1036 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting);
1037 }
1038 }
1039
1040 /*********************************************************************
1041 *
1042 * Fast Legacy/MSI Combined Interrupt Service routine
1043 *
1044 *********************************************************************/
1045 int
igc_intr(void * arg)1046 igc_intr(void *arg)
1047 {
1048 struct igc_softc *sc = arg;
1049 struct igc_hw *hw = &sc->hw;
1050 struct igc_rx_queue *que = &sc->rx_queues[0];
1051 struct tx_ring *txr = &sc->tx_queues[0].txr;
1052 struct rx_ring *rxr = &que->rxr;
1053 if_ctx_t ctx = sc->ctx;
1054 u32 reg_icr;
1055
1056 reg_icr = IGC_READ_REG(hw, IGC_ICR);
1057
1058 /* Hot eject? */
1059 if (reg_icr == 0xffffffff)
1060 return FILTER_STRAY;
1061
1062 /* Definitely not our interrupt. */
1063 if (reg_icr == 0x0)
1064 return FILTER_STRAY;
1065
1066 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0)
1067 return FILTER_STRAY;
1068
1069 /*
1070 * Only MSI-X interrupts have one-shot behavior by taking advantage
1071 * of the EIAC register. Thus, explicitly disable interrupts. This
1072 * also works around the MSI message reordering errata on certain
1073 * systems.
1074 */
1075 IFDI_INTR_DISABLE(ctx);
1076
1077 /* Link status change */
1078 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC))
1079 igc_handle_link(ctx);
1080
1081 if (reg_icr & IGC_ICR_RXO)
1082 sc->rx_overruns++;
1083
1084 igc_neweitr(sc, que, txr, rxr);
1085
1086 /* Reset state */
1087 txr->tx_bytes = 0;
1088 txr->tx_packets = 0;
1089 rxr->rx_bytes = 0;
1090 rxr->rx_packets = 0;
1091
1092 return (FILTER_SCHEDULE_THREAD);
1093 }
1094
1095 static int
igc_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)1096 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1097 {
1098 struct igc_softc *sc = iflib_get_softc(ctx);
1099 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid];
1100
1101 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims);
1102 return (0);
1103 }
1104
1105 static int
igc_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t txqid)1106 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1107 {
1108 struct igc_softc *sc = iflib_get_softc(ctx);
1109 struct igc_tx_queue *txq = &sc->tx_queues[txqid];
1110
1111 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims);
1112 return (0);
1113 }
1114
1115 /*********************************************************************
1116 *
1117 * MSI-X RX Interrupt Service routine
1118 *
1119 **********************************************************************/
1120 static int
igc_msix_que(void * arg)1121 igc_msix_que(void *arg)
1122 {
1123 struct igc_rx_queue *que = arg;
1124 struct igc_softc *sc = que->sc;
1125 struct tx_ring *txr = &sc->tx_queues[que->msix].txr;
1126 struct rx_ring *rxr = &que->rxr;
1127
1128 ++que->irqs;
1129
1130 igc_neweitr(sc, que, txr, rxr);
1131
1132 /* Reset state */
1133 txr->tx_bytes = 0;
1134 txr->tx_packets = 0;
1135 rxr->rx_bytes = 0;
1136 rxr->rx_packets = 0;
1137
1138 return (FILTER_SCHEDULE_THREAD);
1139 }
1140
1141 /*********************************************************************
1142 *
1143 * MSI-X Link Fast Interrupt Service routine
1144 *
1145 **********************************************************************/
1146 static int
igc_msix_link(void * arg)1147 igc_msix_link(void *arg)
1148 {
1149 struct igc_softc *sc = arg;
1150 u32 reg_icr;
1151
1152 ++sc->link_irq;
1153 MPASS(sc->hw.back != NULL);
1154 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR);
1155
1156 if (reg_icr & IGC_ICR_RXO)
1157 sc->rx_overruns++;
1158
1159 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
1160 igc_handle_link(sc->ctx);
1161 }
1162
1163 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC);
1164 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask);
1165
1166 return (FILTER_HANDLED);
1167 }
1168
1169 static void
igc_handle_link(void * context)1170 igc_handle_link(void *context)
1171 {
1172 if_ctx_t ctx = context;
1173 struct igc_softc *sc = iflib_get_softc(ctx);
1174
1175 sc->hw.mac.get_link_status = true;
1176 iflib_admin_intr_deferred(ctx);
1177 }
1178
1179 /*********************************************************************
1180 *
1181 * Media Ioctl callback
1182 *
1183 * This routine is called whenever the user queries the status of
1184 * the interface using ifconfig.
1185 *
1186 **********************************************************************/
1187 static void
igc_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)1188 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1189 {
1190 struct igc_softc *sc = iflib_get_softc(ctx);
1191
1192 INIT_DEBUGOUT("igc_if_media_status: begin");
1193
1194 iflib_admin_intr_deferred(ctx);
1195
1196 ifmr->ifm_status = IFM_AVALID;
1197 ifmr->ifm_active = IFM_ETHER;
1198
1199 if (!sc->link_active) {
1200 return;
1201 }
1202
1203 ifmr->ifm_status |= IFM_ACTIVE;
1204
1205 switch (sc->link_speed) {
1206 case 10:
1207 ifmr->ifm_active |= IFM_10_T;
1208 break;
1209 case 100:
1210 ifmr->ifm_active |= IFM_100_TX;
1211 break;
1212 case 1000:
1213 ifmr->ifm_active |= IFM_1000_T;
1214 break;
1215 case 2500:
1216 ifmr->ifm_active |= IFM_2500_T;
1217 break;
1218 }
1219
1220 if (sc->link_duplex == FULL_DUPLEX)
1221 ifmr->ifm_active |= IFM_FDX;
1222 else
1223 ifmr->ifm_active |= IFM_HDX;
1224 }
1225
1226 /*********************************************************************
1227 *
1228 * Media Ioctl callback
1229 *
1230 * This routine is called when the user changes speed/duplex using
1231 * media/mediopt option with ifconfig.
1232 *
1233 **********************************************************************/
1234 static int
igc_if_media_change(if_ctx_t ctx)1235 igc_if_media_change(if_ctx_t ctx)
1236 {
1237 struct igc_softc *sc = iflib_get_softc(ctx);
1238 struct ifmedia *ifm = iflib_get_media(ctx);
1239
1240 INIT_DEBUGOUT("igc_if_media_change: begin");
1241
1242 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1243 return (EINVAL);
1244
1245 sc->hw.mac.autoneg = DO_AUTO_NEG;
1246
1247 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1248 case IFM_AUTO:
1249 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1250 break;
1251 case IFM_2500_T:
1252 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;
1253 break;
1254 case IFM_1000_T:
1255 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1256 break;
1257 case IFM_100_TX:
1258 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1259 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
1260 else
1261 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
1262 break;
1263 case IFM_10_T:
1264 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1265 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
1266 else
1267 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
1268 break;
1269 default:
1270 device_printf(sc->dev, "Unsupported media type\n");
1271 }
1272
1273 igc_if_init(ctx);
1274
1275 return (0);
1276 }
1277
1278 static int
igc_if_set_promisc(if_ctx_t ctx,int flags)1279 igc_if_set_promisc(if_ctx_t ctx, int flags)
1280 {
1281 struct igc_softc *sc = iflib_get_softc(ctx);
1282 if_t ifp = iflib_get_ifp(ctx);
1283 u32 reg_rctl;
1284 int mcnt = 0;
1285
1286 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
1287 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE);
1288 if (flags & IFF_ALLMULTI)
1289 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1290 else
1291 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1292
1293 /* Don't disable if in MAX groups */
1294 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1295 reg_rctl &= (~IGC_RCTL_MPE);
1296 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1297
1298 if (flags & IFF_PROMISC) {
1299 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1300 /* Turn this on if you want to see bad packets */
1301 if (igc_debug_sbp)
1302 reg_rctl |= IGC_RCTL_SBP;
1303 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1304 } else if (flags & IFF_ALLMULTI) {
1305 reg_rctl |= IGC_RCTL_MPE;
1306 reg_rctl &= ~IGC_RCTL_UPE;
1307 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1308 }
1309 return (0);
1310 }
1311
1312 static u_int
igc_copy_maddr(void * arg,struct sockaddr_dl * sdl,u_int idx)1313 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1314 {
1315 u8 *mta = arg;
1316
1317 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1318 return (0);
1319
1320 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1321
1322 return (1);
1323 }
1324
1325 /*********************************************************************
1326 * Multicast Update
1327 *
1328 * This routine is called whenever multicast address list is updated.
1329 *
1330 **********************************************************************/
1331
1332 static void
igc_if_multi_set(if_ctx_t ctx)1333 igc_if_multi_set(if_ctx_t ctx)
1334 {
1335 struct igc_softc *sc = iflib_get_softc(ctx);
1336 if_t ifp = iflib_get_ifp(ctx);
1337 u8 *mta; /* Multicast array memory */
1338 u32 reg_rctl = 0;
1339 int mcnt = 0;
1340
1341 IOCTL_DEBUGOUT("igc_set_multi: begin");
1342
1343 mta = sc->mta;
1344 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1345
1346 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta);
1347
1348 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
1349
1350 if (if_getflags(ifp) & IFF_PROMISC) {
1351 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1352 /* Turn this on if you want to see bad packets */
1353 if (igc_debug_sbp)
1354 reg_rctl |= IGC_RCTL_SBP;
1355 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1356 if_getflags(ifp) & IFF_ALLMULTI) {
1357 reg_rctl |= IGC_RCTL_MPE;
1358 reg_rctl &= ~IGC_RCTL_UPE;
1359 } else
1360 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
1361
1362 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1363 igc_update_mc_addr_list(&sc->hw, mta, mcnt);
1364
1365 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1366 }
1367
1368 /*********************************************************************
1369 * Timer routine
1370 *
1371 * This routine schedules igc_if_update_admin_status() to check for
1372 * link status and to gather statistics as well as to perform some
1373 * controller-specific hardware patting.
1374 *
1375 **********************************************************************/
1376 static void
igc_if_timer(if_ctx_t ctx,uint16_t qid)1377 igc_if_timer(if_ctx_t ctx, uint16_t qid)
1378 {
1379
1380 if (qid != 0)
1381 return;
1382
1383 iflib_admin_intr_deferred(ctx);
1384 }
1385
1386 static void
igc_if_update_admin_status(if_ctx_t ctx)1387 igc_if_update_admin_status(if_ctx_t ctx)
1388 {
1389 struct igc_softc *sc = iflib_get_softc(ctx);
1390 struct igc_hw *hw = &sc->hw;
1391 device_t dev = iflib_get_dev(ctx);
1392 u32 link_check, thstat, ctrl;
1393
1394 link_check = thstat = ctrl = 0;
1395 /* Get the cached link value or read phy for real */
1396 switch (hw->phy.media_type) {
1397 case igc_media_type_copper:
1398 if (hw->mac.get_link_status == true) {
1399 /* Do the work to read phy */
1400 igc_check_for_link(hw);
1401 link_check = !hw->mac.get_link_status;
1402 } else
1403 link_check = true;
1404 break;
1405 case igc_media_type_unknown:
1406 igc_check_for_link(hw);
1407 link_check = !hw->mac.get_link_status;
1408 /* FALLTHROUGH */
1409 default:
1410 break;
1411 }
1412
1413 /* Now check for a transition */
1414 if (link_check && (sc->link_active == 0)) {
1415 igc_get_speed_and_duplex(hw, &sc->link_speed,
1416 &sc->link_duplex);
1417 if (bootverbose)
1418 device_printf(dev, "Link is up %d Mbps %s\n",
1419 sc->link_speed,
1420 ((sc->link_duplex == FULL_DUPLEX) ?
1421 "Full Duplex" : "Half Duplex"));
1422 sc->link_active = 1;
1423 iflib_link_state_change(ctx, LINK_STATE_UP,
1424 IF_Mbps(sc->link_speed));
1425 } else if (!link_check && (sc->link_active == 1)) {
1426 sc->link_speed = 0;
1427 sc->link_duplex = 0;
1428 sc->link_active = 0;
1429 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1430 }
1431 igc_update_stats_counters(sc);
1432 }
1433
1434 static void
igc_if_watchdog_reset(if_ctx_t ctx)1435 igc_if_watchdog_reset(if_ctx_t ctx)
1436 {
1437 struct igc_softc *sc = iflib_get_softc(ctx);
1438
1439 /*
1440 * Just count the event; iflib(4) will already trigger a
1441 * sufficient reset of the controller.
1442 */
1443 sc->watchdog_events++;
1444 }
1445
1446 /*********************************************************************
1447 *
1448 * This routine disables all traffic on the adapter by issuing a
1449 * global reset on the MAC.
1450 *
1451 **********************************************************************/
1452 static void
igc_if_stop(if_ctx_t ctx)1453 igc_if_stop(if_ctx_t ctx)
1454 {
1455 struct igc_softc *sc = iflib_get_softc(ctx);
1456
1457 INIT_DEBUGOUT("igc_if_stop: begin");
1458
1459 igc_reset_hw(&sc->hw);
1460 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0);
1461 }
1462
1463 /*********************************************************************
1464 *
1465 * Determine hardware revision.
1466 *
1467 **********************************************************************/
1468 static void
igc_identify_hardware(if_ctx_t ctx)1469 igc_identify_hardware(if_ctx_t ctx)
1470 {
1471 device_t dev = iflib_get_dev(ctx);
1472 struct igc_softc *sc = iflib_get_softc(ctx);
1473
1474 /* Make sure our PCI config space has the necessary stuff set */
1475 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1476
1477 /* Save off the information about this board */
1478 sc->hw.vendor_id = pci_get_vendor(dev);
1479 sc->hw.device_id = pci_get_device(dev);
1480 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1481 sc->hw.subsystem_vendor_id =
1482 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1483 sc->hw.subsystem_device_id =
1484 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1485
1486 /* Do Shared Code Init and Setup */
1487 if (igc_set_mac_type(&sc->hw)) {
1488 device_printf(dev, "Setup init failure\n");
1489 return;
1490 }
1491 }
1492
1493 static int
igc_allocate_pci_resources(if_ctx_t ctx)1494 igc_allocate_pci_resources(if_ctx_t ctx)
1495 {
1496 struct igc_softc *sc = iflib_get_softc(ctx);
1497 device_t dev = iflib_get_dev(ctx);
1498 int rid;
1499
1500 rid = PCIR_BAR(0);
1501 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1502 &rid, RF_ACTIVE);
1503 if (sc->memory == NULL) {
1504 device_printf(dev,
1505 "Unable to allocate bus resource: memory\n");
1506 return (ENXIO);
1507 }
1508 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
1509 sc->osdep.mem_bus_space_handle =
1510 rman_get_bushandle(sc->memory);
1511 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
1512
1513 sc->hw.back = &sc->osdep;
1514
1515 return (0);
1516 }
1517
1518 /*********************************************************************
1519 *
1520 * Set up the MSI-X Interrupt handlers
1521 *
1522 **********************************************************************/
1523 static int
igc_if_msix_intr_assign(if_ctx_t ctx,int msix)1524 igc_if_msix_intr_assign(if_ctx_t ctx, int msix)
1525 {
1526 struct igc_softc *sc = iflib_get_softc(ctx);
1527 struct igc_rx_queue *rx_que = sc->rx_queues;
1528 struct igc_tx_queue *tx_que = sc->tx_queues;
1529 int error, rid, i, vector = 0, rx_vectors;
1530 char buf[16];
1531
1532 /* First set up ring resources */
1533 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
1534 rid = vector + 1;
1535 snprintf(buf, sizeof(buf), "rxq%d", i);
1536 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
1537 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf);
1538 if (error) {
1539 device_printf(iflib_get_dev(ctx),
1540 "Failed to allocate que int %d err: %d",
1541 i, error);
1542 sc->rx_num_queues = i + 1;
1543 goto fail;
1544 }
1545
1546 rx_que->msix = vector;
1547
1548 /*
1549 * Set the bit to enable interrupt
1550 * in IGC_IMS -- bits 20 and 21
1551 * are for RX0 and RX1, note this has
1552 * NOTHING to do with the MSI-X vector
1553 */
1554 rx_que->eims = 1 << vector;
1555 }
1556 rx_vectors = vector;
1557
1558 vector = 0;
1559 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
1560 snprintf(buf, sizeof(buf), "txq%d", i);
1561 tx_que = &sc->tx_queues[i];
1562 iflib_softirq_alloc_generic(ctx,
1563 &sc->rx_queues[i % sc->rx_num_queues].que_irq,
1564 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1565
1566 tx_que->msix = (vector % sc->rx_num_queues);
1567
1568 /*
1569 * Set the bit to enable interrupt
1570 * in IGC_IMS -- bits 22 and 23
1571 * are for TX0 and TX1, note this has
1572 * NOTHING to do with the MSI-X vector
1573 */
1574 tx_que->eims = 1 << i;
1575 }
1576
1577 /* Link interrupt */
1578 rid = rx_vectors + 1;
1579 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN,
1580 igc_msix_link, sc, 0, "aq");
1581
1582 if (error) {
1583 device_printf(iflib_get_dev(ctx),
1584 "Failed to register admin handler");
1585 goto fail;
1586 }
1587 sc->linkvec = rx_vectors;
1588 return (0);
1589 fail:
1590 iflib_irq_free(ctx, &sc->irq);
1591 rx_que = sc->rx_queues;
1592 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
1593 iflib_irq_free(ctx, &rx_que->que_irq);
1594 return (error);
1595 }
1596
1597 static void
igc_configure_queues(struct igc_softc * sc)1598 igc_configure_queues(struct igc_softc *sc)
1599 {
1600 struct igc_hw *hw = &sc->hw;
1601 struct igc_rx_queue *rx_que;
1602 struct igc_tx_queue *tx_que;
1603 u32 ivar = 0, newitr = 0;
1604
1605 /* First turn on RSS capability */
1606 IGC_WRITE_REG(hw, IGC_GPIE,
1607 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA |
1608 IGC_GPIE_NSICR);
1609
1610 /* Turn on MSI-X */
1611 /* RX entries */
1612 for (int i = 0; i < sc->rx_num_queues; i++) {
1613 u32 index = i >> 1;
1614 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index);
1615 rx_que = &sc->rx_queues[i];
1616 if (i & 1) {
1617 ivar &= 0xFF00FFFF;
1618 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16;
1619 } else {
1620 ivar &= 0xFFFFFF00;
1621 ivar |= rx_que->msix | IGC_IVAR_VALID;
1622 }
1623 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar);
1624 }
1625 /* TX entries */
1626 for (int i = 0; i < sc->tx_num_queues; i++) {
1627 u32 index = i >> 1;
1628 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index);
1629 tx_que = &sc->tx_queues[i];
1630 if (i & 1) {
1631 ivar &= 0x00FFFFFF;
1632 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24;
1633 } else {
1634 ivar &= 0xFFFF00FF;
1635 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8;
1636 }
1637 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar);
1638 sc->que_mask |= tx_que->eims;
1639 }
1640
1641 /* And for the link interrupt */
1642 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8;
1643 sc->link_mask = 1 << sc->linkvec;
1644 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar);
1645
1646 /* Set the starting interrupt rate */
1647 if (igc_max_interrupt_rate > 0)
1648 newitr = IGC_INTS_TO_EITR(igc_max_interrupt_rate);
1649
1650 newitr |= IGC_EITR_CNT_IGNR;
1651
1652 for (int i = 0; i < sc->rx_num_queues; i++) {
1653 rx_que = &sc->rx_queues[i];
1654 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr);
1655 }
1656
1657 return;
1658 }
1659
1660 static void
igc_free_pci_resources(if_ctx_t ctx)1661 igc_free_pci_resources(if_ctx_t ctx)
1662 {
1663 struct igc_softc *sc = iflib_get_softc(ctx);
1664 struct igc_rx_queue *que = sc->rx_queues;
1665 device_t dev = iflib_get_dev(ctx);
1666
1667 /* Release all MSI-X queue resources */
1668 if (sc->intr_type == IFLIB_INTR_MSIX)
1669 iflib_irq_free(ctx, &sc->irq);
1670
1671 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
1672 iflib_irq_free(ctx, &que->que_irq);
1673 }
1674
1675 if (sc->memory != NULL) {
1676 bus_release_resource(dev, SYS_RES_MEMORY,
1677 rman_get_rid(sc->memory), sc->memory);
1678 sc->memory = NULL;
1679 }
1680
1681 if (sc->flash != NULL) {
1682 bus_release_resource(dev, SYS_RES_MEMORY,
1683 rman_get_rid(sc->flash), sc->flash);
1684 sc->flash = NULL;
1685 }
1686
1687 if (sc->ioport != NULL) {
1688 bus_release_resource(dev, SYS_RES_IOPORT,
1689 rman_get_rid(sc->ioport), sc->ioport);
1690 sc->ioport = NULL;
1691 }
1692 }
1693
1694 /* Set up MSI or MSI-X */
1695 static int
igc_setup_msix(if_ctx_t ctx)1696 igc_setup_msix(if_ctx_t ctx)
1697 {
1698 return (0);
1699 }
1700
1701 /*********************************************************************
1702 *
1703 * Initialize the DMA Coalescing feature
1704 *
1705 **********************************************************************/
1706 static void
igc_init_dmac(struct igc_softc * sc,u32 pba)1707 igc_init_dmac(struct igc_softc *sc, u32 pba)
1708 {
1709 device_t dev = sc->dev;
1710 struct igc_hw *hw = &sc->hw;
1711 u32 dmac, reg = ~IGC_DMACR_DMAC_EN;
1712 u16 hwm;
1713 u16 max_frame_size;
1714 int status;
1715
1716 max_frame_size = sc->shared->isc_max_frame_size;
1717
1718 if (sc->dmac == 0) { /* Disabling it */
1719 IGC_WRITE_REG(hw, IGC_DMACR, reg);
1720 return;
1721 } else
1722 device_printf(dev, "DMA Coalescing enabled\n");
1723
1724 /* Set starting threshold */
1725 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0);
1726
1727 hwm = 64 * pba - max_frame_size / 16;
1728 if (hwm < 64 * (pba - 6))
1729 hwm = 64 * (pba - 6);
1730 reg = IGC_READ_REG(hw, IGC_FCRTC);
1731 reg &= ~IGC_FCRTC_RTH_COAL_MASK;
1732 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT)
1733 & IGC_FCRTC_RTH_COAL_MASK);
1734 IGC_WRITE_REG(hw, IGC_FCRTC, reg);
1735
1736 dmac = pba - max_frame_size / 512;
1737 if (dmac < pba - 10)
1738 dmac = pba - 10;
1739 reg = IGC_READ_REG(hw, IGC_DMACR);
1740 reg &= ~IGC_DMACR_DMACTHR_MASK;
1741 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT)
1742 & IGC_DMACR_DMACTHR_MASK);
1743
1744 /* transition to L0x or L1 if available..*/
1745 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK);
1746
1747 /* Check if status is 2.5Gb backplane connection
1748 * before configuration of watchdog timer, which is
1749 * in msec values in 12.8usec intervals
1750 * watchdog timer= msec values in 32usec intervals
1751 * for non 2.5Gb connection
1752 */
1753 status = IGC_READ_REG(hw, IGC_STATUS);
1754 if ((status & IGC_STATUS_2P5_SKU) &&
1755 (!(status & IGC_STATUS_2P5_SKU_OVER)))
1756 reg |= ((sc->dmac * 5) >> 6);
1757 else
1758 reg |= (sc->dmac >> 5);
1759
1760 IGC_WRITE_REG(hw, IGC_DMACR, reg);
1761
1762 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0);
1763
1764 /* Set the interval before transition */
1765 reg = IGC_READ_REG(hw, IGC_DMCTLX);
1766 reg |= IGC_DMCTLX_DCFLUSH_DIS;
1767
1768 /*
1769 ** in 2.5Gb connection, TTLX unit is 0.4 usec
1770 ** which is 0x4*2 = 0xA. But delay is still 4 usec
1771 */
1772 status = IGC_READ_REG(hw, IGC_STATUS);
1773 if ((status & IGC_STATUS_2P5_SKU) &&
1774 (!(status & IGC_STATUS_2P5_SKU_OVER)))
1775 reg |= 0xA;
1776 else
1777 reg |= 0x4;
1778
1779 IGC_WRITE_REG(hw, IGC_DMCTLX, reg);
1780
1781 /* free space in tx packet buffer to wake from DMA coal */
1782 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE -
1783 (2 * max_frame_size)) >> 6);
1784
1785 /* make low power state decision controlled by DMA coal */
1786 reg = IGC_READ_REG(hw, IGC_PCIEMISC);
1787 reg &= ~IGC_PCIEMISC_LX_DECISION;
1788 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);
1789 }
1790
1791 /*********************************************************************
1792 *
1793 * Initialize the hardware to a configuration as specified by the
1794 * softc structure.
1795 *
1796 **********************************************************************/
1797 static void
igc_reset(if_ctx_t ctx)1798 igc_reset(if_ctx_t ctx)
1799 {
1800 device_t dev = iflib_get_dev(ctx);
1801 struct igc_softc *sc = iflib_get_softc(ctx);
1802 struct igc_hw *hw = &sc->hw;
1803 u32 rx_buffer_size;
1804 u32 pba;
1805
1806 INIT_DEBUGOUT("igc_reset: begin");
1807 /* Let the firmware know the OS is in control */
1808 igc_get_hw_control(sc);
1809
1810 /*
1811 * Packet Buffer Allocation (PBA)
1812 * Writing PBA sets the receive portion of the buffer
1813 * the remainder is used for the transmit buffer.
1814 */
1815 pba = IGC_PBA_34K;
1816
1817 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba);
1818
1819 /*
1820 * These parameters control the automatic generation (Tx) and
1821 * response (Rx) to Ethernet PAUSE frames.
1822 * - High water mark should allow for at least two frames to be
1823 * received after sending an XOFF.
1824 * - Low water mark works best when it is very near the high water
1825 * mark.
1826 * This allows the receiver to restart by sending XON when it has
1827 * drained a bit. Here we use an arbitrary value of 1500 which will
1828 * restart after one full frame is pulled from the buffer. There
1829 * could be several smaller frames in the buffer and if so they will
1830 * not trigger the XON until their total number reduces the buffer
1831 * by 1500.
1832 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1833 */
1834 rx_buffer_size = (pba & 0xffff) << 10;
1835 hw->fc.high_water = rx_buffer_size -
1836 roundup2(sc->hw.mac.max_frame_size, 1024);
1837 /* 16-byte granularity */
1838 hw->fc.low_water = hw->fc.high_water - 16;
1839
1840 if (sc->fc) /* locally set flow control value? */
1841 hw->fc.requested_mode = sc->fc;
1842 else
1843 hw->fc.requested_mode = igc_fc_full;
1844
1845 hw->fc.pause_time = IGC_FC_PAUSE_TIME;
1846
1847 hw->fc.send_xon = true;
1848
1849 /* Issue a global reset */
1850 igc_reset_hw(hw);
1851 IGC_WRITE_REG(hw, IGC_WUC, 0);
1852
1853 /* and a re-init */
1854 if (igc_init_hw(hw) < 0) {
1855 device_printf(dev, "Hardware Initialization Failed\n");
1856 return;
1857 }
1858
1859 /* Setup DMA Coalescing */
1860 igc_init_dmac(sc, pba);
1861
1862 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */
1863 sc->pba = pba;
1864
1865 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN);
1866 igc_get_phy_info(hw);
1867 igc_check_for_link(hw);
1868 }
1869
1870 /*
1871 * Initialise the RSS mapping for NICs that support multiple transmit/
1872 * receive rings.
1873 */
1874
1875 #define RSSKEYLEN 10
1876 static void
igc_initialize_rss_mapping(struct igc_softc * sc)1877 igc_initialize_rss_mapping(struct igc_softc *sc)
1878 {
1879 struct igc_hw *hw = &sc->hw;
1880 int i;
1881 int queue_id;
1882 u32 reta;
1883 u32 rss_key[RSSKEYLEN], mrqc, shift = 0;
1884
1885 /*
1886 * The redirection table controls which destination
1887 * queue each bucket redirects traffic to.
1888 * Each DWORD represents four queues, with the LSB
1889 * being the first queue in the DWORD.
1890 *
1891 * This just allocates buckets to queues using round-robin
1892 * allocation.
1893 *
1894 * NOTE: It Just Happens to line up with the default
1895 * RSS allocation method.
1896 */
1897
1898 /* Warning FM follows */
1899 reta = 0;
1900 for (i = 0; i < 128; i++) {
1901 #ifdef RSS
1902 queue_id = rss_get_indirection_to_bucket(i);
1903 /*
1904 * If we have more queues than buckets, we'll
1905 * end up mapping buckets to a subset of the
1906 * queues.
1907 *
1908 * If we have more buckets than queues, we'll
1909 * end up instead assigning multiple buckets
1910 * to queues.
1911 *
1912 * Both are suboptimal, but we need to handle
1913 * the case so we don't go out of bounds
1914 * indexing arrays and such.
1915 */
1916 queue_id = queue_id % sc->rx_num_queues;
1917 #else
1918 queue_id = (i % sc->rx_num_queues);
1919 #endif
1920 /* Adjust if required */
1921 queue_id = queue_id << shift;
1922
1923 /*
1924 * The low 8 bits are for hash value (n+0);
1925 * The next 8 bits are for hash value (n+1), etc.
1926 */
1927 reta = reta >> 8;
1928 reta = reta | ( ((uint32_t) queue_id) << 24);
1929 if ((i & 3) == 3) {
1930 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta);
1931 reta = 0;
1932 }
1933 }
1934
1935 /* Now fill in hash table */
1936
1937 /*
1938 * MRQC: Multiple Receive Queues Command
1939 * Set queuing to RSS control, number depends on the device.
1940 */
1941 mrqc = IGC_MRQC_ENABLE_RSS_4Q;
1942
1943 #ifdef RSS
1944 /* XXX ew typecasting */
1945 rss_getkey((uint8_t *) &rss_key);
1946 #else
1947 arc4rand(&rss_key, sizeof(rss_key), 0);
1948 #endif
1949 for (i = 0; i < RSSKEYLEN; i++)
1950 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]);
1951
1952 /*
1953 * Configure the RSS fields to hash upon.
1954 */
1955 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 |
1956 IGC_MRQC_RSS_FIELD_IPV4_TCP);
1957 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 |
1958 IGC_MRQC_RSS_FIELD_IPV6_TCP);
1959 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP |
1960 IGC_MRQC_RSS_FIELD_IPV6_UDP);
1961 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX |
1962 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX);
1963
1964 IGC_WRITE_REG(hw, IGC_MRQC, mrqc);
1965 }
1966
1967 /*********************************************************************
1968 *
1969 * Setup networking device structure and register interface media.
1970 *
1971 **********************************************************************/
1972 static int
igc_setup_interface(if_ctx_t ctx)1973 igc_setup_interface(if_ctx_t ctx)
1974 {
1975 if_t ifp = iflib_get_ifp(ctx);
1976 struct igc_softc *sc = iflib_get_softc(ctx);
1977 if_softc_ctx_t scctx = sc->shared;
1978
1979 INIT_DEBUGOUT("igc_setup_interface: begin");
1980
1981 /* Single Queue */
1982 if (sc->tx_num_queues == 1) {
1983 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
1984 if_setsendqready(ifp);
1985 }
1986
1987 /*
1988 * Specify the media types supported by this adapter and register
1989 * callbacks to update media and link information
1990 */
1991 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1992 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1993 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1994 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1995 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1996 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1997 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1998
1999 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2000 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
2001 return (0);
2002 }
2003
2004 static int
igc_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)2005 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
2006 int ntxqs, int ntxqsets)
2007 {
2008 struct igc_softc *sc = iflib_get_softc(ctx);
2009 if_softc_ctx_t scctx = sc->shared;
2010 int error = IGC_SUCCESS;
2011 struct igc_tx_queue *que;
2012 int i, j;
2013
2014 MPASS(sc->tx_num_queues > 0);
2015 MPASS(sc->tx_num_queues == ntxqsets);
2016
2017 /* First allocate the top level queue structs */
2018 if (!(sc->tx_queues =
2019 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) *
2020 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2021 device_printf(iflib_get_dev(ctx),
2022 "Unable to allocate queue memory\n");
2023 return(ENOMEM);
2024 }
2025
2026 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
2027 /* Set up some basics */
2028
2029 struct tx_ring *txr = &que->txr;
2030 txr->sc = que->sc = sc;
2031 que->me = txr->me = i;
2032
2033 /* Allocate report status array */
2034 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) *
2035 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2036 device_printf(iflib_get_dev(ctx),
2037 "failed to allocate rs_idxs memory\n");
2038 error = ENOMEM;
2039 goto fail;
2040 }
2041 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2042 txr->tx_rsq[j] = QIDX_INVALID;
2043 /* get virtual and physical address of the hardware queues */
2044 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs];
2045 txr->tx_paddr = paddrs[i*ntxqs];
2046 }
2047
2048 if (bootverbose)
2049 device_printf(iflib_get_dev(ctx),
2050 "allocated for %d tx_queues\n", sc->tx_num_queues);
2051 return (0);
2052 fail:
2053 igc_if_queues_free(ctx);
2054 return (error);
2055 }
2056
2057 static int
igc_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)2058 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
2059 int nrxqs, int nrxqsets)
2060 {
2061 struct igc_softc *sc = iflib_get_softc(ctx);
2062 int error = IGC_SUCCESS;
2063 struct igc_rx_queue *que;
2064 int i;
2065
2066 MPASS(sc->rx_num_queues > 0);
2067 MPASS(sc->rx_num_queues == nrxqsets);
2068
2069 /* First allocate the top level queue structs */
2070 if (!(sc->rx_queues =
2071 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) *
2072 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2073 device_printf(iflib_get_dev(ctx),
2074 "Unable to allocate queue memory\n");
2075 error = ENOMEM;
2076 goto fail;
2077 }
2078
2079 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
2080 /* Set up some basics */
2081 struct rx_ring *rxr = &que->rxr;
2082 rxr->sc = que->sc = sc;
2083 rxr->que = que;
2084 que->me = rxr->me = i;
2085
2086 /* get virtual and physical address of the hardware queues */
2087 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs];
2088 rxr->rx_paddr = paddrs[i*nrxqs];
2089 }
2090
2091 if (bootverbose)
2092 device_printf(iflib_get_dev(ctx),
2093 "allocated for %d rx_queues\n", sc->rx_num_queues);
2094
2095 return (0);
2096 fail:
2097 igc_if_queues_free(ctx);
2098 return (error);
2099 }
2100
2101 static void
igc_if_queues_free(if_ctx_t ctx)2102 igc_if_queues_free(if_ctx_t ctx)
2103 {
2104 struct igc_softc *sc = iflib_get_softc(ctx);
2105 struct igc_tx_queue *tx_que = sc->tx_queues;
2106 struct igc_rx_queue *rx_que = sc->rx_queues;
2107
2108 if (tx_que != NULL) {
2109 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
2110 struct tx_ring *txr = &tx_que->txr;
2111 if (txr->tx_rsq == NULL)
2112 break;
2113
2114 free(txr->tx_rsq, M_DEVBUF);
2115 txr->tx_rsq = NULL;
2116 }
2117 free(sc->tx_queues, M_DEVBUF);
2118 sc->tx_queues = NULL;
2119 }
2120
2121 if (rx_que != NULL) {
2122 free(sc->rx_queues, M_DEVBUF);
2123 sc->rx_queues = NULL;
2124 }
2125
2126 if (sc->mta != NULL) {
2127 free(sc->mta, M_DEVBUF);
2128 }
2129 }
2130
2131 /*********************************************************************
2132 *
2133 * Enable transmit unit.
2134 *
2135 **********************************************************************/
2136 static void
igc_initialize_transmit_unit(if_ctx_t ctx)2137 igc_initialize_transmit_unit(if_ctx_t ctx)
2138 {
2139 struct igc_softc *sc = iflib_get_softc(ctx);
2140 if_softc_ctx_t scctx = sc->shared;
2141 struct igc_tx_queue *que;
2142 struct tx_ring *txr;
2143 struct igc_hw *hw = &sc->hw;
2144 u32 tctl, txdctl = 0;
2145
2146 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin");
2147
2148 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
2149 u64 bus_addr;
2150 caddr_t offp, endp;
2151
2152 que = &sc->tx_queues[i];
2153 txr = &que->txr;
2154 bus_addr = txr->tx_paddr;
2155
2156 /* Clear checksum offload context. */
2157 offp = (caddr_t)&txr->csum_flags;
2158 endp = (caddr_t)(txr + 1);
2159 bzero(offp, endp - offp);
2160
2161 /* Base and Len of TX Ring */
2162 IGC_WRITE_REG(hw, IGC_TDLEN(i),
2163 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc));
2164 IGC_WRITE_REG(hw, IGC_TDBAH(i),
2165 (u32)(bus_addr >> 32));
2166 IGC_WRITE_REG(hw, IGC_TDBAL(i),
2167 (u32)bus_addr);
2168 /* Init the HEAD/TAIL indices */
2169 IGC_WRITE_REG(hw, IGC_TDT(i), 0);
2170 IGC_WRITE_REG(hw, IGC_TDH(i), 0);
2171
2172 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2173 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)),
2174 IGC_READ_REG(&sc->hw, IGC_TDLEN(i)));
2175
2176 txdctl = 0; /* clear txdctl */
2177 txdctl |= 0x1f; /* PTHRESH */
2178 txdctl |= 1 << 8; /* HTHRESH */
2179 txdctl |= 1 << 16;/* WTHRESH */
2180 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2181 txdctl |= IGC_TXDCTL_GRAN;
2182 txdctl |= 1 << 25; /* LWTHRESH */
2183
2184 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl);
2185 }
2186
2187 /* Program the Transmit Control Register */
2188 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL);
2189 tctl &= ~IGC_TCTL_CT;
2190 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN |
2191 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT));
2192
2193 /* This write will effectively turn on the transmit unit. */
2194 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl);
2195 }
2196
2197 /*********************************************************************
2198 *
2199 * Enable receive unit.
2200 *
2201 **********************************************************************/
2202 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1)
2203
2204 static void
igc_initialize_receive_unit(if_ctx_t ctx)2205 igc_initialize_receive_unit(if_ctx_t ctx)
2206 {
2207 struct igc_softc *sc = iflib_get_softc(ctx);
2208 if_softc_ctx_t scctx = sc->shared;
2209 if_t ifp = iflib_get_ifp(ctx);
2210 struct igc_hw *hw = &sc->hw;
2211 struct igc_rx_queue *que;
2212 int i;
2213 u32 psize, rctl, rxcsum, srrctl = 0;
2214
2215 INIT_DEBUGOUT("igc_initialize_receive_units: begin");
2216
2217 /*
2218 * Make sure receives are disabled while setting
2219 * up the descriptor ring
2220 */
2221 rctl = IGC_READ_REG(hw, IGC_RCTL);
2222 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN);
2223
2224 /* Setup the Receive Control Register */
2225 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
2226 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM |
2227 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF |
2228 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
2229
2230 /* Do not store bad packets */
2231 rctl &= ~IGC_RCTL_SBP;
2232
2233 /* Enable Long Packet receive */
2234 if (if_getmtu(ifp) > ETHERMTU)
2235 rctl |= IGC_RCTL_LPE;
2236 else
2237 rctl &= ~IGC_RCTL_LPE;
2238
2239 /* Strip the CRC */
2240 if (!igc_disable_crc_stripping)
2241 rctl |= IGC_RCTL_SECRC;
2242
2243 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM);
2244 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
2245 rxcsum |= IGC_RXCSUM_CRCOFL;
2246 if (sc->tx_num_queues > 1)
2247 rxcsum |= IGC_RXCSUM_PCSD;
2248 else
2249 rxcsum |= IGC_RXCSUM_IPPCSE;
2250 } else {
2251 if (sc->tx_num_queues > 1)
2252 rxcsum |= IGC_RXCSUM_PCSD;
2253 else
2254 rxcsum &= ~IGC_RXCSUM_TUOFL;
2255 }
2256 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum);
2257
2258 if (sc->rx_num_queues > 1)
2259 igc_initialize_rss_mapping(sc);
2260
2261 if (if_getmtu(ifp) > ETHERMTU) {
2262 psize = scctx->isc_max_frame_size;
2263 /* are we on a vlan? */
2264 if (if_vlantrunkinuse(ifp))
2265 psize += VLAN_TAG_SIZE;
2266 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize);
2267 }
2268
2269 /* Set maximum packet buffer len */
2270 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
2271 IGC_SRRCTL_BSIZEPKT_SHIFT;
2272 /* srrctl above overrides this but set the register to a sane value */
2273 rctl |= IGC_RCTL_SZ_2048;
2274
2275 /*
2276 * If TX flow control is disabled and there's >1 queue defined,
2277 * enable DROP.
2278 *
2279 * This drops frames rather than hanging the RX MAC for all queues.
2280 */
2281 if ((sc->rx_num_queues > 1) &&
2282 (sc->fc == igc_fc_none ||
2283 sc->fc == igc_fc_rx_pause)) {
2284 srrctl |= IGC_SRRCTL_DROP_EN;
2285 }
2286
2287 /* Setup the Base and Length of the Rx Descriptor Rings */
2288 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
2289 struct rx_ring *rxr = &que->rxr;
2290 u64 bus_addr = rxr->rx_paddr;
2291 u32 rxdctl;
2292
2293 #ifdef notyet
2294 /* Configure for header split? -- ignore for now */
2295 rxr->hdr_split = igc_header_split;
2296 #else
2297 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
2298 #endif
2299
2300 IGC_WRITE_REG(hw, IGC_RDLEN(i),
2301 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc));
2302 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32));
2303 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr);
2304 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl);
2305 /* Setup the Head and Tail Descriptor Pointers */
2306 IGC_WRITE_REG(hw, IGC_RDH(i), 0);
2307 IGC_WRITE_REG(hw, IGC_RDT(i), 0);
2308 /* Enable this Queue */
2309 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i));
2310 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
2311 rxdctl &= 0xFFF00000;
2312 rxdctl |= IGC_RX_PTHRESH;
2313 rxdctl |= IGC_RX_HTHRESH << 8;
2314 rxdctl |= IGC_RX_WTHRESH << 16;
2315 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl);
2316 }
2317
2318 /* Make sure VLAN Filters are off */
2319 rctl &= ~IGC_RCTL_VFE;
2320
2321 /* Write out the settings */
2322 IGC_WRITE_REG(hw, IGC_RCTL, rctl);
2323
2324 return;
2325 }
2326
2327 static void
igc_setup_vlan_hw_support(if_ctx_t ctx)2328 igc_setup_vlan_hw_support(if_ctx_t ctx)
2329 {
2330 struct igc_softc *sc = iflib_get_softc(ctx);
2331 struct igc_hw *hw = &sc->hw;
2332 struct ifnet *ifp = iflib_get_ifp(ctx);
2333 u32 reg;
2334
2335 /* igc hardware doesn't seem to implement VFTA for HWFILTER */
2336
2337 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
2338 !igc_disable_crc_stripping) {
2339 reg = IGC_READ_REG(hw, IGC_CTRL);
2340 reg |= IGC_CTRL_VME;
2341 IGC_WRITE_REG(hw, IGC_CTRL, reg);
2342 } else {
2343 reg = IGC_READ_REG(hw, IGC_CTRL);
2344 reg &= ~IGC_CTRL_VME;
2345 IGC_WRITE_REG(hw, IGC_CTRL, reg);
2346 }
2347 }
2348
2349 static void
igc_if_intr_enable(if_ctx_t ctx)2350 igc_if_intr_enable(if_ctx_t ctx)
2351 {
2352 struct igc_softc *sc = iflib_get_softc(ctx);
2353 struct igc_hw *hw = &sc->hw;
2354 u32 mask;
2355
2356 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
2357 mask = (sc->que_mask | sc->link_mask);
2358 IGC_WRITE_REG(hw, IGC_EIAC, mask);
2359 IGC_WRITE_REG(hw, IGC_EIAM, mask);
2360 IGC_WRITE_REG(hw, IGC_EIMS, mask);
2361 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC);
2362 } else
2363 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK);
2364 IGC_WRITE_FLUSH(hw);
2365 }
2366
2367 static void
igc_if_intr_disable(if_ctx_t ctx)2368 igc_if_intr_disable(if_ctx_t ctx)
2369 {
2370 struct igc_softc *sc = iflib_get_softc(ctx);
2371 struct igc_hw *hw = &sc->hw;
2372
2373 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
2374 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff);
2375 IGC_WRITE_REG(hw, IGC_EIAC, 0);
2376 }
2377 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
2378 IGC_WRITE_FLUSH(hw);
2379 }
2380
2381 /*
2382 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
2383 * For ASF and Pass Through versions of f/w this means
2384 * that the driver is loaded. For AMT version type f/w
2385 * this means that the network i/f is open.
2386 */
2387 static void
igc_get_hw_control(struct igc_softc * sc)2388 igc_get_hw_control(struct igc_softc *sc)
2389 {
2390 u32 ctrl_ext;
2391
2392 if (sc->vf_ifp)
2393 return;
2394
2395 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2396 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT,
2397 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
2398 }
2399
2400 /*
2401 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
2402 * For ASF and Pass Through versions of f/w this means that
2403 * the driver is no longer loaded. For AMT versions of the
2404 * f/w this means that the network i/f is closed.
2405 */
2406 static void
igc_release_hw_control(struct igc_softc * sc)2407 igc_release_hw_control(struct igc_softc *sc)
2408 {
2409 u32 ctrl_ext;
2410
2411 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2412 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT,
2413 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
2414 return;
2415 }
2416
2417 static int
igc_is_valid_ether_addr(u8 * addr)2418 igc_is_valid_ether_addr(u8 *addr)
2419 {
2420 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
2421
2422 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
2423 return (false);
2424 }
2425
2426 return (true);
2427 }
2428
2429 /*
2430 ** Parse the interface capabilities with regard
2431 ** to both system management and wake-on-lan for
2432 ** later use.
2433 */
2434 static void
igc_get_wakeup(if_ctx_t ctx)2435 igc_get_wakeup(if_ctx_t ctx)
2436 {
2437 struct igc_softc *sc = iflib_get_softc(ctx);
2438 u16 eeprom_data = 0, apme_mask;
2439
2440 apme_mask = IGC_WUC_APME;
2441 eeprom_data = IGC_READ_REG(&sc->hw, IGC_WUC);
2442
2443 if (eeprom_data & apme_mask)
2444 sc->wol = IGC_WUFC_LNKC;
2445 }
2446
2447
2448 /*
2449 * Enable PCI Wake On Lan capability
2450 */
2451 static void
igc_enable_wakeup(if_ctx_t ctx)2452 igc_enable_wakeup(if_ctx_t ctx)
2453 {
2454 struct igc_softc *sc = iflib_get_softc(ctx);
2455 device_t dev = iflib_get_dev(ctx);
2456 if_t ifp = iflib_get_ifp(ctx);
2457 int error = 0;
2458 u32 ctrl, rctl;
2459
2460 if (!pci_has_pm(dev))
2461 return;
2462
2463 /*
2464 * Determine type of Wakeup: note that wol
2465 * is set with all bits on by default.
2466 */
2467 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
2468 sc->wol &= ~IGC_WUFC_MAG;
2469
2470 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
2471 sc->wol &= ~IGC_WUFC_EX;
2472
2473 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
2474 sc->wol &= ~IGC_WUFC_MC;
2475 else {
2476 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
2477 rctl |= IGC_RCTL_MPE;
2478 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl);
2479 }
2480
2481 if (!(sc->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC)))
2482 goto pme;
2483
2484 /* Advertise the wakeup capability */
2485 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL);
2486 ctrl |= IGC_CTRL_ADVD3WUC;
2487 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl);
2488
2489 /* Enable wakeup by the MAC */
2490 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN);
2491 IGC_WRITE_REG(&sc->hw, IGC_WUFC, sc->wol);
2492
2493 pme:
2494 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
2495 pci_enable_pme(dev);
2496
2497 return;
2498 }
2499
2500 /**********************************************************************
2501 *
2502 * Update the board statistics counters.
2503 *
2504 **********************************************************************/
2505 static void
igc_update_stats_counters(struct igc_softc * sc)2506 igc_update_stats_counters(struct igc_softc *sc)
2507 {
2508 u64 prev_xoffrxc = sc->stats.xoffrxc;
2509
2510 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS);
2511 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC);
2512 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC);
2513 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL);
2514
2515 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC);
2516 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL);
2517 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC);
2518 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_RERC);
2519 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC);
2520 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC);
2521 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC);
2522 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC);
2523 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC);
2524 /*
2525 * For watchdog management we need to know if we have been
2526 * paused during the last interval, so capture that here.
2527 */
2528 if (sc->stats.xoffrxc != prev_xoffrxc)
2529 sc->shared->isc_pause_frames = 1;
2530 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC);
2531 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC);
2532 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64);
2533 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127);
2534 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255);
2535 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511);
2536 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023);
2537 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522);
2538 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC);
2539 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC);
2540 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC);
2541 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC);
2542 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC);
2543 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC);
2544
2545 /* For the 64-bit byte counters the low dword must be read first. */
2546 /* Both registers clear on the read of the high dword */
2547
2548 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) +
2549 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32);
2550 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) +
2551 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32);
2552
2553 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC);
2554 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC);
2555 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC);
2556 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC);
2557 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC);
2558
2559 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC);
2560 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC);
2561 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC);
2562
2563 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH);
2564 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH);
2565
2566 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR);
2567 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT);
2568 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64);
2569 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127);
2570 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255);
2571 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511);
2572 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023);
2573 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522);
2574 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC);
2575 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC);
2576
2577 /* Interrupt Counts */
2578 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC);
2579 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC);
2580
2581 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC);
2582 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS);
2583 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC);
2584 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC);
2585 }
2586
2587 static uint64_t
igc_if_get_counter(if_ctx_t ctx,ift_counter cnt)2588 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2589 {
2590 struct igc_softc *sc = iflib_get_softc(ctx);
2591 if_t ifp = iflib_get_ifp(ctx);
2592
2593 switch (cnt) {
2594 case IFCOUNTER_COLLISIONS:
2595 return (sc->stats.colc);
2596 case IFCOUNTER_IERRORS:
2597 return (sc->dropped_pkts + sc->stats.rxerrc +
2598 sc->stats.crcerrs + sc->stats.algnerrc +
2599 sc->stats.ruc + sc->stats.roc +
2600 sc->stats.mpc + sc->stats.htdpmc);
2601 case IFCOUNTER_OERRORS:
2602 return (sc->stats.ecol + sc->stats.latecol +
2603 sc->watchdog_events);
2604 default:
2605 return (if_get_counter_default(ifp, cnt));
2606 }
2607 }
2608
2609 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized
2610 * @ctx: iflib context
2611 * @event: event code to check
2612 *
2613 * Defaults to returning false for unknown events.
2614 *
2615 * @returns true if iflib needs to reinit the interface
2616 */
2617 static bool
igc_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)2618 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
2619 {
2620 switch (event) {
2621 case IFLIB_RESTART_VLAN_CONFIG:
2622 default:
2623 return (false);
2624 }
2625 }
2626
2627 /* Export a single 32-bit register via a read-only sysctl. */
2628 static int
igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)2629 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
2630 {
2631 struct igc_softc *sc;
2632 u_int val;
2633
2634 sc = oidp->oid_arg1;
2635 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2);
2636 return (sysctl_handle_int(oidp, &val, 0, req));
2637 }
2638
2639 /* Per queue holdoff interrupt rate handler */
2640 static int
igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)2641 igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
2642 {
2643 struct igc_rx_queue *rque;
2644 struct igc_tx_queue *tque;
2645 struct igc_hw *hw;
2646 int error;
2647 u32 reg, usec, rate;
2648
2649 bool tx = oidp->oid_arg2;
2650
2651 if (tx) {
2652 tque = oidp->oid_arg1;
2653 hw = &tque->sc->hw;
2654 reg = IGC_READ_REG(hw, IGC_EITR(tque->me));
2655 } else {
2656 rque = oidp->oid_arg1;
2657 hw = &rque->sc->hw;
2658 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix));
2659 }
2660
2661 usec = (reg & IGC_QVECTOR_MASK);
2662 if (usec > 0)
2663 rate = IGC_INTS_TO_EITR(usec);
2664 else
2665 rate = 0;
2666
2667 error = sysctl_handle_int(oidp, &rate, 0, req);
2668 if (error || !req->newptr)
2669 return error;
2670 return 0;
2671 }
2672
2673 /*
2674 * Add sysctl variables, one per statistic, to the system.
2675 */
2676 static void
igc_add_hw_stats(struct igc_softc * sc)2677 igc_add_hw_stats(struct igc_softc *sc)
2678 {
2679 device_t dev = iflib_get_dev(sc->ctx);
2680 struct igc_tx_queue *tx_que = sc->tx_queues;
2681 struct igc_rx_queue *rx_que = sc->rx_queues;
2682
2683 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
2684 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
2685 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
2686 struct igc_hw_stats *stats = &sc->stats;
2687
2688 struct sysctl_oid *stat_node, *queue_node, *int_node;
2689 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
2690
2691 #define QUEUE_NAME_LEN 32
2692 char namebuf[QUEUE_NAME_LEN];
2693
2694 /* Driver Statistics */
2695 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
2696 CTLFLAG_RD, &sc->dropped_pkts,
2697 "Driver dropped packets");
2698 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
2699 CTLFLAG_RD, &sc->link_irq,
2700 "Link MSI-X IRQ Handled");
2701 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
2702 CTLFLAG_RD, &sc->rx_overruns,
2703 "RX overruns");
2704 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
2705 CTLFLAG_RD, &sc->watchdog_events,
2706 "Watchdog timeouts");
2707 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
2708 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2709 sc, IGC_CTRL, igc_sysctl_reg_handler, "IU",
2710 "Device Control Register");
2711 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
2712 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2713 sc, IGC_RCTL, igc_sysctl_reg_handler, "IU",
2714 "Receiver Control Register");
2715 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
2716 CTLFLAG_RD, &sc->hw.fc.high_water, 0,
2717 "Flow Control High Watermark");
2718 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
2719 CTLFLAG_RD, &sc->hw.fc.low_water, 0,
2720 "Flow Control Low Watermark");
2721
2722 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
2723 struct tx_ring *txr = &tx_que->txr;
2724 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
2725 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2726 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
2727 queue_list = SYSCTL_CHILDREN(queue_node);
2728
2729 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2730 CTLTYPE_UINT | CTLFLAG_RD, tx_que,
2731 true, igc_sysctl_interrupt_rate_handler, "IU",
2732 "Interrupt Rate");
2733 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
2734 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2735 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU",
2736 "Transmit Descriptor Head");
2737 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
2738 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2739 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU",
2740 "Transmit Descriptor Tail");
2741 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
2742 CTLFLAG_RD, &txr->tx_irq,
2743 "Queue MSI-X Transmit Interrupts");
2744 }
2745
2746 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
2747 struct rx_ring *rxr = &rx_que->rxr;
2748 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
2749 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2750 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
2751 queue_list = SYSCTL_CHILDREN(queue_node);
2752
2753 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2754 CTLTYPE_UINT | CTLFLAG_RD, rx_que,
2755 false, igc_sysctl_interrupt_rate_handler, "IU",
2756 "Interrupt Rate");
2757 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
2758 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2759 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU",
2760 "Receive Descriptor Head");
2761 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
2762 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2763 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU",
2764 "Receive Descriptor Tail");
2765 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
2766 CTLFLAG_RD, &rxr->rx_irq,
2767 "Queue MSI-X Receive Interrupts");
2768 }
2769
2770 /* MAC stats get their own sub node */
2771 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
2772 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
2773 stat_list = SYSCTL_CHILDREN(stat_node);
2774
2775 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
2776 CTLFLAG_RD, &stats->ecol,
2777 "Excessive collisions");
2778 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
2779 CTLFLAG_RD, &stats->scc,
2780 "Single collisions");
2781 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
2782 CTLFLAG_RD, &stats->mcc,
2783 "Multiple collisions");
2784 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
2785 CTLFLAG_RD, &stats->latecol,
2786 "Late collisions");
2787 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
2788 CTLFLAG_RD, &stats->colc,
2789 "Collision Count");
2790 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
2791 CTLFLAG_RD, &sc->stats.symerrs,
2792 "Symbol Errors");
2793 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
2794 CTLFLAG_RD, &sc->stats.sec,
2795 "Sequence Errors");
2796 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
2797 CTLFLAG_RD, &sc->stats.dc,
2798 "Defer Count");
2799 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
2800 CTLFLAG_RD, &sc->stats.mpc,
2801 "Missed Packets");
2802 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors",
2803 CTLFLAG_RD, &sc->stats.rlec,
2804 "Receive Length Errors");
2805 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
2806 CTLFLAG_RD, &sc->stats.rnbc,
2807 "Receive No Buffers");
2808 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
2809 CTLFLAG_RD, &sc->stats.ruc,
2810 "Receive Undersize");
2811 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
2812 CTLFLAG_RD, &sc->stats.rfc,
2813 "Fragmented Packets Received ");
2814 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
2815 CTLFLAG_RD, &sc->stats.roc,
2816 "Oversized Packets Received");
2817 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
2818 CTLFLAG_RD, &sc->stats.rjc,
2819 "Recevied Jabber");
2820 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
2821 CTLFLAG_RD, &sc->stats.rxerrc,
2822 "Receive Errors");
2823 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
2824 CTLFLAG_RD, &sc->stats.crcerrs,
2825 "CRC errors");
2826 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
2827 CTLFLAG_RD, &sc->stats.algnerrc,
2828 "Alignment Errors");
2829 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
2830 CTLFLAG_RD, &sc->stats.xonrxc,
2831 "XON Received");
2832 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
2833 CTLFLAG_RD, &sc->stats.xontxc,
2834 "XON Transmitted");
2835 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
2836 CTLFLAG_RD, &sc->stats.xoffrxc,
2837 "XOFF Received");
2838 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
2839 CTLFLAG_RD, &sc->stats.xofftxc,
2840 "XOFF Transmitted");
2841 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd",
2842 CTLFLAG_RD, &sc->stats.fcruc,
2843 "Unsupported Flow Control Received");
2844 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd",
2845 CTLFLAG_RD, &sc->stats.mgprc,
2846 "Management Packets Received");
2847 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop",
2848 CTLFLAG_RD, &sc->stats.mgpdc,
2849 "Management Packets Dropped");
2850 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd",
2851 CTLFLAG_RD, &sc->stats.mgptc,
2852 "Management Packets Transmitted");
2853
2854 /* Packet Reception Stats */
2855 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
2856 CTLFLAG_RD, &sc->stats.tpr,
2857 "Total Packets Received ");
2858 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
2859 CTLFLAG_RD, &sc->stats.gprc,
2860 "Good Packets Received");
2861 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
2862 CTLFLAG_RD, &sc->stats.bprc,
2863 "Broadcast Packets Received");
2864 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
2865 CTLFLAG_RD, &sc->stats.mprc,
2866 "Multicast Packets Received");
2867 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
2868 CTLFLAG_RD, &sc->stats.prc64,
2869 "64 byte frames received ");
2870 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
2871 CTLFLAG_RD, &sc->stats.prc127,
2872 "65-127 byte frames received");
2873 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
2874 CTLFLAG_RD, &sc->stats.prc255,
2875 "128-255 byte frames received");
2876 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
2877 CTLFLAG_RD, &sc->stats.prc511,
2878 "256-511 byte frames received");
2879 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
2880 CTLFLAG_RD, &sc->stats.prc1023,
2881 "512-1023 byte frames received");
2882 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
2883 CTLFLAG_RD, &sc->stats.prc1522,
2884 "1023-1522 byte frames received");
2885 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
2886 CTLFLAG_RD, &sc->stats.gorc,
2887 "Good Octets Received");
2888
2889 /* Packet Transmission Stats */
2890 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
2891 CTLFLAG_RD, &sc->stats.gotc,
2892 "Good Octets Transmitted");
2893 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
2894 CTLFLAG_RD, &sc->stats.tpt,
2895 "Total Packets Transmitted");
2896 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
2897 CTLFLAG_RD, &sc->stats.gptc,
2898 "Good Packets Transmitted");
2899 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
2900 CTLFLAG_RD, &sc->stats.bptc,
2901 "Broadcast Packets Transmitted");
2902 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
2903 CTLFLAG_RD, &sc->stats.mptc,
2904 "Multicast Packets Transmitted");
2905 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
2906 CTLFLAG_RD, &sc->stats.ptc64,
2907 "64 byte frames transmitted ");
2908 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
2909 CTLFLAG_RD, &sc->stats.ptc127,
2910 "65-127 byte frames transmitted");
2911 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
2912 CTLFLAG_RD, &sc->stats.ptc255,
2913 "128-255 byte frames transmitted");
2914 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
2915 CTLFLAG_RD, &sc->stats.ptc511,
2916 "256-511 byte frames transmitted");
2917 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
2918 CTLFLAG_RD, &sc->stats.ptc1023,
2919 "512-1023 byte frames transmitted");
2920 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
2921 CTLFLAG_RD, &sc->stats.ptc1522,
2922 "1024-1522 byte frames transmitted");
2923 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
2924 CTLFLAG_RD, &sc->stats.tsctc,
2925 "TSO Contexts Transmitted");
2926
2927 /* Interrupt Stats */
2928 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
2929 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
2930 int_list = SYSCTL_CHILDREN(int_node);
2931
2932 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
2933 CTLFLAG_RD, &sc->stats.iac,
2934 "Interrupt Assertion Count");
2935
2936 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
2937 CTLFLAG_RD, &sc->stats.rxdmtc,
2938 "Rx Desc Min Thresh Count");
2939 }
2940
2941 static void
igc_fw_version(struct igc_softc * sc)2942 igc_fw_version(struct igc_softc *sc)
2943 {
2944 struct igc_hw *hw = &sc->hw;
2945 struct igc_fw_version *fw_ver = &sc->fw_ver;
2946
2947 *fw_ver = (struct igc_fw_version){0};
2948
2949 igc_get_fw_version(hw, fw_ver);
2950 }
2951
2952 static void
igc_sbuf_fw_version(struct igc_fw_version * fw_ver,struct sbuf * buf)2953 igc_sbuf_fw_version(struct igc_fw_version *fw_ver, struct sbuf *buf)
2954 {
2955 const char *space = "";
2956
2957 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
2958 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
2959 fw_ver->eep_minor, fw_ver->eep_build);
2960 space = " ";
2961 }
2962
2963 if (fw_ver->invm_major || fw_ver->invm_minor ||
2964 fw_ver->invm_img_type) {
2965 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
2966 space, fw_ver->invm_major, fw_ver->invm_minor,
2967 fw_ver->invm_img_type);
2968 space = " ";
2969 }
2970
2971 if (fw_ver->or_valid) {
2972 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
2973 space, fw_ver->or_major, fw_ver->or_build,
2974 fw_ver->or_patch);
2975 space = " ";
2976 }
2977
2978 if (fw_ver->etrack_id)
2979 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
2980 }
2981
2982 static void
igc_print_fw_version(struct igc_softc * sc)2983 igc_print_fw_version(struct igc_softc *sc )
2984 {
2985 device_t dev = sc->dev;
2986 struct sbuf *buf;
2987 int error = 0;
2988
2989 buf = sbuf_new_auto();
2990 if (!buf) {
2991 device_printf(dev, "Could not allocate sbuf for output.\n");
2992 return;
2993 }
2994
2995 igc_sbuf_fw_version(&sc->fw_ver, buf);
2996
2997 error = sbuf_finish(buf);
2998 if (error)
2999 device_printf(dev, "Error finishing sbuf: %d\n", error);
3000 else if (sbuf_len(buf))
3001 device_printf(dev, "%s\n", sbuf_data(buf));
3002
3003 sbuf_delete(buf);
3004 }
3005
3006 static int
igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)3007 igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
3008 {
3009 struct igc_softc *sc = (struct igc_softc *)arg1;
3010 device_t dev = sc->dev;
3011 struct sbuf *buf;
3012 int error = 0;
3013
3014 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
3015 if (!buf) {
3016 device_printf(dev, "Could not allocate sbuf for output.\n");
3017 return (ENOMEM);
3018 }
3019
3020 igc_sbuf_fw_version(&sc->fw_ver, buf);
3021
3022 error = sbuf_finish(buf);
3023 if (error)
3024 device_printf(dev, "Error finishing sbuf: %d\n", error);
3025
3026 sbuf_delete(buf);
3027
3028 return (0);
3029 }
3030
3031 /**********************************************************************
3032 *
3033 * This routine provides a way to dump out the adapter eeprom,
3034 * often a useful debug/service tool. This only dumps the first
3035 * 32 words, stuff that matters is in that extent.
3036 *
3037 **********************************************************************/
3038 static int
igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)3039 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
3040 {
3041 struct igc_softc *sc = (struct igc_softc *)arg1;
3042 int error;
3043 int result;
3044
3045 result = -1;
3046 error = sysctl_handle_int(oidp, &result, 0, req);
3047
3048 if (error || !req->newptr)
3049 return (error);
3050
3051 /*
3052 * This value will cause a hex dump of the
3053 * first 32 16-bit words of the EEPROM to
3054 * the screen.
3055 */
3056 if (result == 1)
3057 igc_print_nvm_info(sc);
3058
3059 return (error);
3060 }
3061
3062 static void
igc_print_nvm_info(struct igc_softc * sc)3063 igc_print_nvm_info(struct igc_softc *sc)
3064 {
3065 u16 eeprom_data;
3066 int i, j, row = 0;
3067
3068 /* Its a bit crude, but it gets the job done */
3069 printf("\nInterface EEPROM Dump:\n");
3070 printf("Offset\n0x0000 ");
3071 for (i = 0, j = 0; i < 32; i++, j++) {
3072 if (j == 8) { /* Make the offset block */
3073 j = 0; ++row;
3074 printf("\n0x00%x0 ",row);
3075 }
3076 igc_read_nvm(&sc->hw, i, 1, &eeprom_data);
3077 printf("%04x ", eeprom_data);
3078 }
3079 printf("\n");
3080 }
3081
3082 static int
igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)3083 igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
3084 {
3085 struct igc_softc *sc;
3086 u32 reg, val, shift;
3087 int error, mask;
3088
3089 sc = oidp->oid_arg1;
3090 switch (oidp->oid_arg2) {
3091 case 0:
3092 reg = IGC_DTXTCPFLGL;
3093 shift = 0;
3094 break;
3095 case 1:
3096 reg = IGC_DTXTCPFLGL;
3097 shift = 16;
3098 break;
3099 case 2:
3100 reg = IGC_DTXTCPFLGH;
3101 shift = 0;
3102 break;
3103 default:
3104 return (EINVAL);
3105 break;
3106 }
3107 val = IGC_READ_REG(&sc->hw, reg);
3108 mask = (val >> shift) & 0xfff;
3109 error = sysctl_handle_int(oidp, &mask, 0, req);
3110 if (error != 0 || req->newptr == NULL)
3111 return (error);
3112 if (mask < 0 || mask > 0xfff)
3113 return (EINVAL);
3114 val = (val & ~(0xfff << shift)) | (mask << shift);
3115 IGC_WRITE_REG(&sc->hw, reg, val);
3116 return (0);
3117 }
3118
3119 /*
3120 * Set flow control using sysctl:
3121 * Flow control values:
3122 * 0 - off
3123 * 1 - rx pause
3124 * 2 - tx pause
3125 * 3 - full
3126 */
3127 static int
igc_set_flowcntl(SYSCTL_HANDLER_ARGS)3128 igc_set_flowcntl(SYSCTL_HANDLER_ARGS)
3129 {
3130 int error;
3131 static int input = 3; /* default is full */
3132 struct igc_softc *sc = (struct igc_softc *) arg1;
3133
3134 error = sysctl_handle_int(oidp, &input, 0, req);
3135
3136 if ((error) || (req->newptr == NULL))
3137 return (error);
3138
3139 if (input == sc->fc) /* no change? */
3140 return (error);
3141
3142 switch (input) {
3143 case igc_fc_rx_pause:
3144 case igc_fc_tx_pause:
3145 case igc_fc_full:
3146 case igc_fc_none:
3147 sc->hw.fc.requested_mode = input;
3148 sc->fc = input;
3149 break;
3150 default:
3151 /* Do nothing */
3152 return (error);
3153 }
3154
3155 sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
3156 igc_force_mac_fc(&sc->hw);
3157 return (error);
3158 }
3159
3160 /*
3161 * Manage DMA Coalesce:
3162 * Control values:
3163 * 0/1 - off/on
3164 * Legal timer values are:
3165 * 250,500,1000-10000 in thousands
3166 */
3167 static int
igc_sysctl_dmac(SYSCTL_HANDLER_ARGS)3168 igc_sysctl_dmac(SYSCTL_HANDLER_ARGS)
3169 {
3170 struct igc_softc *sc = (struct igc_softc *) arg1;
3171 int error;
3172
3173 error = sysctl_handle_int(oidp, &sc->dmac, 0, req);
3174
3175 if ((error) || (req->newptr == NULL))
3176 return (error);
3177
3178 switch (sc->dmac) {
3179 case 0:
3180 /* Disabling */
3181 break;
3182 case 1: /* Just enable and use default */
3183 sc->dmac = 1000;
3184 break;
3185 case 250:
3186 case 500:
3187 case 1000:
3188 case 2000:
3189 case 3000:
3190 case 4000:
3191 case 5000:
3192 case 6000:
3193 case 7000:
3194 case 8000:
3195 case 9000:
3196 case 10000:
3197 /* Legal values - allow */
3198 break;
3199 default:
3200 /* Do nothing, illegal value */
3201 sc->dmac = 0;
3202 return (EINVAL);
3203 }
3204 /* Reinit the interface */
3205 igc_if_init(sc->ctx);
3206 return (error);
3207 }
3208
3209 /*
3210 * Manage Energy Efficient Ethernet:
3211 * Control values:
3212 * 0/1 - enabled/disabled
3213 */
3214 static int
igc_sysctl_eee(SYSCTL_HANDLER_ARGS)3215 igc_sysctl_eee(SYSCTL_HANDLER_ARGS)
3216 {
3217 struct igc_softc *sc = (struct igc_softc *) arg1;
3218 int error, value;
3219
3220 value = sc->hw.dev_spec._i225.eee_disable;
3221 error = sysctl_handle_int(oidp, &value, 0, req);
3222 if (error || req->newptr == NULL)
3223 return (error);
3224
3225 sc->hw.dev_spec._i225.eee_disable = (value != 0);
3226 igc_if_init(sc->ctx);
3227
3228 return (0);
3229 }
3230
3231 static int
igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS)3232 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3233 {
3234 struct igc_softc *sc;
3235 int error;
3236 int result;
3237
3238 result = -1;
3239 error = sysctl_handle_int(oidp, &result, 0, req);
3240
3241 if (error || !req->newptr)
3242 return (error);
3243
3244 if (result == 1) {
3245 sc = (struct igc_softc *) arg1;
3246 igc_print_debug_info(sc);
3247 }
3248
3249 return (error);
3250 }
3251
3252 static int
igc_get_rs(SYSCTL_HANDLER_ARGS)3253 igc_get_rs(SYSCTL_HANDLER_ARGS)
3254 {
3255 struct igc_softc *sc = (struct igc_softc *) arg1;
3256 int error;
3257 int result;
3258
3259 result = 0;
3260 error = sysctl_handle_int(oidp, &result, 0, req);
3261
3262 if (error || !req->newptr || result != 1)
3263 return (error);
3264 igc_dump_rs(sc);
3265
3266 return (error);
3267 }
3268
3269 static void
igc_if_debug(if_ctx_t ctx)3270 igc_if_debug(if_ctx_t ctx)
3271 {
3272 igc_dump_rs(iflib_get_softc(ctx));
3273 }
3274
3275 /*
3276 * This routine is meant to be fluid, add whatever is
3277 * needed for debugging a problem. -jfv
3278 */
3279 static void
igc_print_debug_info(struct igc_softc * sc)3280 igc_print_debug_info(struct igc_softc *sc)
3281 {
3282 device_t dev = iflib_get_dev(sc->ctx);
3283 if_t ifp = iflib_get_ifp(sc->ctx);
3284 struct tx_ring *txr = &sc->tx_queues->txr;
3285 struct rx_ring *rxr = &sc->rx_queues->rxr;
3286
3287 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3288 printf("Interface is RUNNING ");
3289 else
3290 printf("Interface is NOT RUNNING\n");
3291
3292 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
3293 printf("and INACTIVE\n");
3294 else
3295 printf("and ACTIVE\n");
3296
3297 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3298 device_printf(dev, "TX Queue %d ------\n", i);
3299 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3300 IGC_READ_REG(&sc->hw, IGC_TDH(i)),
3301 IGC_READ_REG(&sc->hw, IGC_TDT(i)));
3302
3303 }
3304 for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
3305 device_printf(dev, "RX Queue %d ------\n", j);
3306 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3307 IGC_READ_REG(&sc->hw, IGC_RDH(j)),
3308 IGC_READ_REG(&sc->hw, IGC_RDT(j)));
3309 }
3310 }
3311