1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
3
4 #include "igc.h"
5 #include "igc_base.h"
6 #include "igc_hw.h"
7 #include "igc_tsn.h"
8
9 #define MIN_MULTPLIER_TX_MIN_FRAG 0
10 #define MAX_MULTPLIER_TX_MIN_FRAG 3
11 /* Frag size is based on the Section 8.12.2 of the SW User Manual */
12 #define TX_MIN_FRAG_SIZE 64
13 #define TX_MAX_FRAG_SIZE (TX_MIN_FRAG_SIZE * \
14 (MAX_MULTPLIER_TX_MIN_FRAG + 1))
15
16 enum tx_queue {
17 TX_QUEUE_0 = 0,
18 TX_QUEUE_1,
19 TX_QUEUE_2,
20 TX_QUEUE_3,
21 };
22
23 DEFINE_STATIC_KEY_FALSE(igc_fpe_enabled);
24
igc_fpe_init_smd_frame(struct igc_ring * ring,struct igc_tx_buffer * buffer,struct sk_buff * skb)25 static int igc_fpe_init_smd_frame(struct igc_ring *ring,
26 struct igc_tx_buffer *buffer,
27 struct sk_buff *skb)
28 {
29 dma_addr_t dma = dma_map_single(ring->dev, skb->data, skb->len,
30 DMA_TO_DEVICE);
31
32 if (dma_mapping_error(ring->dev, dma)) {
33 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
34 return -ENOMEM;
35 }
36
37 buffer->type = IGC_TX_BUFFER_TYPE_SKB;
38 buffer->skb = skb;
39 buffer->protocol = 0;
40 buffer->bytecount = skb->len;
41 buffer->gso_segs = 1;
42 buffer->time_stamp = jiffies;
43 dma_unmap_len_set(buffer, len, skb->len);
44 dma_unmap_addr_set(buffer, dma, dma);
45
46 return 0;
47 }
48
igc_fpe_init_tx_descriptor(struct igc_ring * ring,struct sk_buff * skb,enum igc_txd_popts_type type)49 static int igc_fpe_init_tx_descriptor(struct igc_ring *ring,
50 struct sk_buff *skb,
51 enum igc_txd_popts_type type)
52 {
53 u32 cmd_type, olinfo_status = 0;
54 struct igc_tx_buffer *buffer;
55 union igc_adv_tx_desc *desc;
56 int err;
57
58 if (!igc_desc_unused(ring))
59 return -EBUSY;
60
61 buffer = &ring->tx_buffer_info[ring->next_to_use];
62 err = igc_fpe_init_smd_frame(ring, buffer, skb);
63 if (err)
64 return err;
65
66 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
67 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
68 buffer->bytecount;
69
70 olinfo_status |= FIELD_PREP(IGC_ADVTXD_PAYLEN_MASK, buffer->bytecount);
71
72 switch (type) {
73 case SMD_V:
74 case SMD_R:
75 olinfo_status |= FIELD_PREP(IGC_TXD_POPTS_SMD_MASK, type);
76 break;
77 }
78
79 desc = IGC_TX_DESC(ring, ring->next_to_use);
80 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
81 desc->read.olinfo_status = cpu_to_le32(olinfo_status);
82 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(buffer, dma));
83
84 netdev_tx_sent_queue(txring_txq(ring), skb->len);
85
86 buffer->next_to_watch = desc;
87 ring->next_to_use = (ring->next_to_use + 1) % ring->count;
88
89 return 0;
90 }
91
igc_fpe_xmit_smd_frame(struct igc_adapter * adapter,enum igc_txd_popts_type type)92 static int igc_fpe_xmit_smd_frame(struct igc_adapter *adapter,
93 enum igc_txd_popts_type type)
94 {
95 int cpu = smp_processor_id();
96 struct netdev_queue *nq;
97 struct igc_ring *ring;
98 struct sk_buff *skb;
99 int err;
100
101 ring = igc_get_tx_ring(adapter, cpu);
102 nq = txring_txq(ring);
103
104 skb = alloc_skb(SMD_FRAME_SIZE, GFP_ATOMIC);
105 if (!skb)
106 return -ENOMEM;
107
108 skb_put_zero(skb, SMD_FRAME_SIZE);
109
110 __netif_tx_lock(nq, cpu);
111
112 err = igc_fpe_init_tx_descriptor(ring, skb, type);
113 if (err)
114 goto err_free_skb_any;
115
116 igc_flush_tx_descriptors(ring);
117 __netif_tx_unlock(nq);
118 return 0;
119
120 err_free_skb_any:
121 __netif_tx_unlock(nq);
122 dev_kfree_skb_any(skb);
123 return err;
124 }
125
igc_fpe_configure_tx(struct ethtool_mmsv * mmsv,bool tx_enable)126 static void igc_fpe_configure_tx(struct ethtool_mmsv *mmsv, bool tx_enable)
127 {
128 struct igc_fpe_t *fpe = container_of(mmsv, struct igc_fpe_t, mmsv);
129 struct igc_adapter *adapter;
130
131 adapter = container_of(fpe, struct igc_adapter, fpe);
132 adapter->fpe.tx_enabled = tx_enable;
133
134 /* Update config since tx_enabled affects preemptible queue configuration */
135 igc_tsn_offload_apply(adapter);
136 }
137
igc_fpe_send_mpacket(struct ethtool_mmsv * mmsv,enum ethtool_mpacket type)138 static void igc_fpe_send_mpacket(struct ethtool_mmsv *mmsv,
139 enum ethtool_mpacket type)
140 {
141 struct igc_fpe_t *fpe = container_of(mmsv, struct igc_fpe_t, mmsv);
142 struct igc_adapter *adapter;
143 int err;
144
145 adapter = container_of(fpe, struct igc_adapter, fpe);
146
147 if (type == ETHTOOL_MPACKET_VERIFY) {
148 err = igc_fpe_xmit_smd_frame(adapter, SMD_V);
149 if (err && net_ratelimit())
150 netdev_err(adapter->netdev, "Error sending SMD-V\n");
151 } else if (type == ETHTOOL_MPACKET_RESPONSE) {
152 err = igc_fpe_xmit_smd_frame(adapter, SMD_R);
153 if (err && net_ratelimit())
154 netdev_err(adapter->netdev, "Error sending SMD-R frame\n");
155 }
156 }
157
158 static const struct ethtool_mmsv_ops igc_mmsv_ops = {
159 .configure_tx = igc_fpe_configure_tx,
160 .send_mpacket = igc_fpe_send_mpacket,
161 };
162
igc_fpe_init(struct igc_adapter * adapter)163 void igc_fpe_init(struct igc_adapter *adapter)
164 {
165 adapter->fpe.tx_min_frag_size = TX_MIN_FRAG_SIZE;
166 adapter->fpe.tx_enabled = false;
167 ethtool_mmsv_init(&adapter->fpe.mmsv, adapter->netdev, &igc_mmsv_ops);
168 }
169
igc_fpe_clear_preempt_queue(struct igc_adapter * adapter)170 void igc_fpe_clear_preempt_queue(struct igc_adapter *adapter)
171 {
172 for (int i = 0; i < adapter->num_tx_queues; i++) {
173 struct igc_ring *tx_ring = adapter->tx_ring[i];
174
175 tx_ring->preemptible = false;
176 }
177 }
178
igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter * adapter,unsigned long preemptible_tcs)179 static u32 igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter *adapter,
180 unsigned long preemptible_tcs)
181 {
182 struct net_device *dev = adapter->netdev;
183 u32 i, queue = 0;
184
185 for (i = 0; i < dev->num_tc; i++) {
186 u32 offset, count;
187
188 if (!(preemptible_tcs & BIT(i)))
189 continue;
190
191 offset = dev->tc_to_txq[i].offset;
192 count = dev->tc_to_txq[i].count;
193 queue |= GENMASK(offset + count - 1, offset);
194 }
195
196 return queue;
197 }
198
igc_fpe_save_preempt_queue(struct igc_adapter * adapter,const struct tc_mqprio_qopt_offload * mqprio)199 void igc_fpe_save_preempt_queue(struct igc_adapter *adapter,
200 const struct tc_mqprio_qopt_offload *mqprio)
201 {
202 u32 preemptible_queue = igc_fpe_map_preempt_tc_to_queue(adapter,
203 mqprio->preemptible_tcs);
204
205 for (int i = 0; i < adapter->num_tx_queues; i++) {
206 struct igc_ring *tx_ring = adapter->tx_ring[i];
207
208 tx_ring->preemptible = !!(preemptible_queue & BIT(i));
209 }
210 }
211
is_any_launchtime(struct igc_adapter * adapter)212 static bool is_any_launchtime(struct igc_adapter *adapter)
213 {
214 int i;
215
216 for (i = 0; i < adapter->num_tx_queues; i++) {
217 struct igc_ring *ring = adapter->tx_ring[i];
218
219 if (ring->launchtime_enable)
220 return true;
221 }
222
223 return false;
224 }
225
is_cbs_enabled(struct igc_adapter * adapter)226 static bool is_cbs_enabled(struct igc_adapter *adapter)
227 {
228 int i;
229
230 for (i = 0; i < adapter->num_tx_queues; i++) {
231 struct igc_ring *ring = adapter->tx_ring[i];
232
233 if (ring->cbs_enable)
234 return true;
235 }
236
237 return false;
238 }
239
igc_tsn_new_flags(struct igc_adapter * adapter)240 static unsigned int igc_tsn_new_flags(struct igc_adapter *adapter)
241 {
242 unsigned int new_flags = adapter->flags & ~IGC_FLAG_TSN_ANY_ENABLED;
243
244
245 if (adapter->taprio_offload_enable || is_any_launchtime(adapter) ||
246 adapter->strict_priority_enable)
247 new_flags |= IGC_FLAG_TSN_QBV_ENABLED;
248
249 if (is_cbs_enabled(adapter))
250 new_flags |= IGC_FLAG_TSN_QAV_ENABLED;
251
252 if (adapter->fpe.mmsv.pmac_enabled)
253 new_flags |= IGC_FLAG_TSN_PREEMPT_ENABLED;
254
255 return new_flags;
256 }
257
igc_tsn_is_tx_mode_in_tsn(struct igc_adapter * adapter)258 static bool igc_tsn_is_tx_mode_in_tsn(struct igc_adapter *adapter)
259 {
260 struct igc_hw *hw = &adapter->hw;
261
262 return !!(rd32(IGC_TQAVCTRL) & IGC_TQAVCTRL_TRANSMIT_MODE_TSN);
263 }
264
igc_tsn_adjust_txtime_offset(struct igc_adapter * adapter)265 void igc_tsn_adjust_txtime_offset(struct igc_adapter *adapter)
266 {
267 struct igc_hw *hw = &adapter->hw;
268 u16 txoffset;
269
270 if (!igc_tsn_is_tx_mode_in_tsn(adapter))
271 return;
272
273 switch (adapter->link_speed) {
274 case SPEED_10:
275 txoffset = IGC_TXOFFSET_SPEED_10;
276 break;
277 case SPEED_100:
278 txoffset = IGC_TXOFFSET_SPEED_100;
279 break;
280 case SPEED_1000:
281 txoffset = IGC_TXOFFSET_SPEED_1000;
282 break;
283 case SPEED_2500:
284 txoffset = IGC_TXOFFSET_SPEED_2500;
285 break;
286 default:
287 txoffset = 0;
288 break;
289 }
290
291 wr32(IGC_GTXOFFSET, txoffset);
292 }
293
igc_tsn_restore_retx_default(struct igc_adapter * adapter)294 static void igc_tsn_restore_retx_default(struct igc_adapter *adapter)
295 {
296 struct igc_hw *hw = &adapter->hw;
297 u32 retxctl;
298
299 retxctl = rd32(IGC_RETX_CTL) & IGC_RETX_CTL_WATERMARK_MASK;
300 wr32(IGC_RETX_CTL, retxctl);
301 }
302
igc_tsn_is_taprio_activated_by_user(struct igc_adapter * adapter)303 bool igc_tsn_is_taprio_activated_by_user(struct igc_adapter *adapter)
304 {
305 struct igc_hw *hw = &adapter->hw;
306
307 return (rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) &&
308 adapter->taprio_offload_enable;
309 }
310
igc_tsn_tx_arb(struct igc_adapter * adapter,bool reverse_prio)311 static void igc_tsn_tx_arb(struct igc_adapter *adapter, bool reverse_prio)
312 {
313 struct igc_hw *hw = &adapter->hw;
314 u32 txarb;
315
316 txarb = rd32(IGC_TXARB);
317
318 txarb &= ~(IGC_TXARB_TXQ_PRIO_0_MASK |
319 IGC_TXARB_TXQ_PRIO_1_MASK |
320 IGC_TXARB_TXQ_PRIO_2_MASK |
321 IGC_TXARB_TXQ_PRIO_3_MASK);
322
323 if (reverse_prio) {
324 txarb |= IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_3);
325 txarb |= IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_2);
326 txarb |= IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_1);
327 txarb |= IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_0);
328 } else {
329 txarb |= IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_0);
330 txarb |= IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_1);
331 txarb |= IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_2);
332 txarb |= IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_3);
333 }
334
335 wr32(IGC_TXARB, txarb);
336 }
337
338 /**
339 * igc_tsn_set_rxpbsize - Set the receive packet buffer size
340 * @adapter: Pointer to the igc_adapter structure
341 * @rxpbs_exp_bmc_be: Value to set the receive packet buffer size, including
342 * express buffer, BMC buffer, and Best Effort buffer
343 *
344 * The IGC_RXPBS register value may include allocations for the Express buffer,
345 * BMC buffer, Best Effort buffer, and the timestamp descriptor buffer
346 * (IGC_RXPBS_CFG_TS_EN).
347 */
igc_tsn_set_rxpbsize(struct igc_adapter * adapter,u32 rxpbs_exp_bmc_be)348 static void igc_tsn_set_rxpbsize(struct igc_adapter *adapter,
349 u32 rxpbs_exp_bmc_be)
350 {
351 struct igc_hw *hw = &adapter->hw;
352 u32 rxpbs = rd32(IGC_RXPBS);
353
354 rxpbs &= ~(IGC_RXPBSIZE_EXP_MASK | IGC_BMC2OSPBSIZE_MASK |
355 IGC_RXPBSIZE_BE_MASK);
356 rxpbs |= rxpbs_exp_bmc_be;
357
358 wr32(IGC_RXPBS, rxpbs);
359 }
360
361 /* Returns the TSN specific registers to their default values after
362 * the adapter is reset.
363 */
igc_tsn_disable_offload(struct igc_adapter * adapter)364 static int igc_tsn_disable_offload(struct igc_adapter *adapter)
365 {
366 struct igc_hw *hw = &adapter->hw;
367 u32 tqavctrl;
368 int i;
369
370 wr32(IGC_GTXOFFSET, 0);
371 wr32(IGC_TXPBS, IGC_TXPBSIZE_DEFAULT);
372 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT);
373
374 igc_tsn_set_rxpbsize(adapter, IGC_RXPBSIZE_EXP_BMC_DEFAULT);
375
376 if (igc_is_device_id_i226(hw))
377 igc_tsn_restore_retx_default(adapter);
378
379 tqavctrl = rd32(IGC_TQAVCTRL);
380 tqavctrl &= ~(IGC_TQAVCTRL_TRANSMIT_MODE_TSN |
381 IGC_TQAVCTRL_ENHANCED_QAV | IGC_TQAVCTRL_FUTSCDDIS |
382 IGC_TQAVCTRL_PREEMPT_ENA | IGC_TQAVCTRL_MIN_FRAG_MASK);
383
384 wr32(IGC_TQAVCTRL, tqavctrl);
385
386 for (i = 0; i < adapter->num_tx_queues; i++) {
387 int reg_idx = adapter->tx_ring[i]->reg_idx;
388 u32 txdctl;
389
390 wr32(IGC_TXQCTL(i), 0);
391 wr32(IGC_STQT(i), 0);
392 wr32(IGC_ENDQT(i), NSEC_PER_SEC);
393
394 txdctl = rd32(IGC_TXDCTL(reg_idx));
395 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
396 wr32(IGC_TXDCTL(reg_idx), txdctl);
397 }
398
399 wr32(IGC_QBVCYCLET_S, 0);
400 wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
401
402 /* Restore the default Tx arbitration: Priority 0 has the highest
403 * priority and is assigned to queue 0 and so on and so forth.
404 */
405 igc_tsn_tx_arb(adapter, false);
406
407 adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;
408
409 return 0;
410 }
411
412 /* To partially fix i226 HW errata, reduce MAC internal buffering from 192 Bytes
413 * to 88 Bytes by setting RETX_CTL register using the recommendation from:
414 * a) Ethernet Controller I225/I226 Specification Update Rev 2.1
415 * Item 9: TSN: Packet Transmission Might Cross the Qbv Window
416 * b) I225/6 SW User Manual Rev 1.2.4: Section 8.11.5 Retry Buffer Control
417 */
igc_tsn_set_retx_qbvfullthreshold(struct igc_adapter * adapter)418 static void igc_tsn_set_retx_qbvfullthreshold(struct igc_adapter *adapter)
419 {
420 struct igc_hw *hw = &adapter->hw;
421 u32 retxctl, watermark;
422
423 retxctl = rd32(IGC_RETX_CTL);
424 watermark = retxctl & IGC_RETX_CTL_WATERMARK_MASK;
425 /* Set QBVFULLTH value using watermark and set QBVFULLEN */
426 retxctl |= (watermark << IGC_RETX_CTL_QBVFULLTH_SHIFT) |
427 IGC_RETX_CTL_QBVFULLEN;
428 wr32(IGC_RETX_CTL, retxctl);
429 }
430
igc_fpe_get_frag_size_mult(const struct igc_fpe_t * fpe)431 static u8 igc_fpe_get_frag_size_mult(const struct igc_fpe_t *fpe)
432 {
433 u8 mult = (fpe->tx_min_frag_size / TX_MIN_FRAG_SIZE) - 1;
434
435 return clamp_t(u8, mult, MIN_MULTPLIER_TX_MIN_FRAG,
436 MAX_MULTPLIER_TX_MIN_FRAG);
437 }
438
igc_fpe_get_supported_frag_size(u32 frag_size)439 u32 igc_fpe_get_supported_frag_size(u32 frag_size)
440 {
441 static const u32 supported_sizes[] = { 64, 128, 192, 256 };
442
443 /* Find the smallest supported size that is >= frag_size */
444 for (int i = 0; i < ARRAY_SIZE(supported_sizes); i++) {
445 if (frag_size <= supported_sizes[i])
446 return supported_sizes[i];
447 }
448
449 /* Should not happen */
450 return TX_MAX_FRAG_SIZE;
451 }
452
igc_tsn_enable_offload(struct igc_adapter * adapter)453 static int igc_tsn_enable_offload(struct igc_adapter *adapter)
454 {
455 struct igc_hw *hw = &adapter->hw;
456 u32 tqavctrl, baset_l, baset_h;
457 u32 sec, nsec, cycle;
458 ktime_t base_time, systim;
459 u32 frag_size_mult;
460 int i;
461
462 wr32(IGC_TSAUXC, 0);
463 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);
464 wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);
465
466 igc_tsn_set_rxpbsize(adapter, IGC_RXPBSIZE_EXP_BMC_BE_TSN);
467
468 if (igc_is_device_id_i226(hw))
469 igc_tsn_set_retx_qbvfullthreshold(adapter);
470
471 if (adapter->strict_priority_enable ||
472 adapter->flags & IGC_FLAG_TSN_REVERSE_TXQ_PRIO)
473 igc_tsn_tx_arb(adapter, true);
474
475 for (i = 0; i < adapter->num_tx_queues; i++) {
476 struct igc_ring *ring = adapter->tx_ring[i];
477 u32 txdctl = rd32(IGC_TXDCTL(ring->reg_idx));
478 u32 txqctl = 0;
479 u16 cbs_value;
480 u32 tqavcc;
481
482 wr32(IGC_STQT(i), ring->start_time);
483 wr32(IGC_ENDQT(i), ring->end_time);
484
485 if (adapter->taprio_offload_enable) {
486 /* If taprio_offload_enable is set we are in "taprio"
487 * mode and we need to be strict about the
488 * cycles: only transmit a packet if it can be
489 * completed during that cycle.
490 *
491 * If taprio_offload_enable is NOT true when
492 * enabling TSN offload, the cycle should have
493 * no external effects, but is only used internally
494 * to adapt the base time register after a second
495 * has passed.
496 *
497 * Enabling strict mode in this case would
498 * unnecessarily prevent the transmission of
499 * certain packets (i.e. at the boundary of a
500 * second) and thus interfere with the launchtime
501 * feature that promises transmission at a
502 * certain point in time.
503 */
504 txqctl |= IGC_TXQCTL_STRICT_CYCLE |
505 IGC_TXQCTL_STRICT_END;
506 }
507
508 if (ring->launchtime_enable)
509 txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
510
511 if (!adapter->fpe.tx_enabled) {
512 /* fpe inactive: clear both flags */
513 txqctl &= ~IGC_TXQCTL_PREEMPTIBLE;
514 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
515 } else if (ring->preemptible) {
516 /* fpe active + preemptible: enable preemptible queue + set low priority */
517 txqctl |= IGC_TXQCTL_PREEMPTIBLE;
518 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
519 } else {
520 /* fpe active + express: enable express queue + set high priority */
521 txqctl &= ~IGC_TXQCTL_PREEMPTIBLE;
522 txdctl |= IGC_TXDCTL_PRIORITY_HIGH;
523 }
524
525 wr32(IGC_TXDCTL(ring->reg_idx), txdctl);
526
527 /* Skip configuring CBS for Q2 and Q3 */
528 if (i > 1)
529 goto skip_cbs;
530
531 if (ring->cbs_enable) {
532 if (i == 0)
533 txqctl |= IGC_TXQCTL_QAV_SEL_CBS0;
534 else
535 txqctl |= IGC_TXQCTL_QAV_SEL_CBS1;
536
537 /* According to i225 datasheet section 7.5.2.7, we
538 * should set the 'idleSlope' field from TQAVCC
539 * register following the equation:
540 *
541 * value = link-speed 0x7736 * BW * 0.2
542 * ---------- * ----------------- (E1)
543 * 100Mbps 2.5
544 *
545 * Note that 'link-speed' is in Mbps.
546 *
547 * 'BW' is the percentage bandwidth out of full
548 * link speed which can be found with the
549 * following equation. Note that idleSlope here
550 * is the parameter from this function
551 * which is in kbps.
552 *
553 * BW = idleSlope
554 * ----------------- (E2)
555 * link-speed * 1000
556 *
557 * That said, we can come up with a generic
558 * equation to calculate the value we should set
559 * it TQAVCC register by replacing 'BW' in E1 by E2.
560 * The resulting equation is:
561 *
562 * value = link-speed * 0x7736 * idleSlope * 0.2
563 * ------------------------------------- (E3)
564 * 100 * 2.5 * link-speed * 1000
565 *
566 * 'link-speed' is present in both sides of the
567 * fraction so it is canceled out. The final
568 * equation is the following:
569 *
570 * value = idleSlope * 61036
571 * ----------------- (E4)
572 * 2500000
573 *
574 * NOTE: For i225, given the above, we can see
575 * that idleslope is represented in
576 * 40.959433 kbps units by the value at
577 * the TQAVCC register (2.5Gbps / 61036),
578 * which reduces the granularity for
579 * idleslope increments.
580 *
581 * In i225 controller, the sendSlope and loCredit
582 * parameters from CBS are not configurable
583 * by software so we don't do any
584 * 'controller configuration' in respect to
585 * these parameters.
586 */
587 cbs_value = DIV_ROUND_UP_ULL(ring->idleslope
588 * 61036ULL, 2500000);
589
590 tqavcc = rd32(IGC_TQAVCC(i));
591 tqavcc &= ~IGC_TQAVCC_IDLESLOPE_MASK;
592 tqavcc |= cbs_value | IGC_TQAVCC_KEEP_CREDITS;
593 wr32(IGC_TQAVCC(i), tqavcc);
594
595 wr32(IGC_TQAVHC(i),
596 0x80000000 + ring->hicredit * 0x7736);
597 } else {
598 /* Disable any CBS for the queue */
599 txqctl &= ~(IGC_TXQCTL_QAV_SEL_MASK);
600
601 /* Set idleSlope to zero. */
602 tqavcc = rd32(IGC_TQAVCC(i));
603 tqavcc &= ~(IGC_TQAVCC_IDLESLOPE_MASK |
604 IGC_TQAVCC_KEEP_CREDITS);
605 wr32(IGC_TQAVCC(i), tqavcc);
606
607 /* Set hiCredit to zero. */
608 wr32(IGC_TQAVHC(i), 0);
609 }
610 skip_cbs:
611 wr32(IGC_TXQCTL(i), txqctl);
612 }
613
614 tqavctrl = rd32(IGC_TQAVCTRL) & ~(IGC_TQAVCTRL_FUTSCDDIS |
615 IGC_TQAVCTRL_PREEMPT_ENA | IGC_TQAVCTRL_MIN_FRAG_MASK);
616 tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
617
618 if (adapter->fpe.mmsv.pmac_enabled)
619 tqavctrl |= IGC_TQAVCTRL_PREEMPT_ENA;
620
621 frag_size_mult = igc_fpe_get_frag_size_mult(&adapter->fpe);
622 tqavctrl |= FIELD_PREP(IGC_TQAVCTRL_MIN_FRAG_MASK, frag_size_mult);
623
624 adapter->qbv_count++;
625
626 cycle = adapter->cycle_time;
627 base_time = adapter->base_time;
628
629 nsec = rd32(IGC_SYSTIML);
630 sec = rd32(IGC_SYSTIMH);
631
632 systim = ktime_set(sec, nsec);
633 if (ktime_compare(systim, base_time) > 0) {
634 s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
635
636 base_time = ktime_add_ns(base_time, (n + 1) * cycle);
637 } else {
638 if (igc_is_device_id_i226(hw)) {
639 ktime_t adjust_time, expires_time;
640
641 /* According to datasheet section 7.5.2.9.3.3, FutScdDis bit
642 * has to be configured before the cycle time and base time.
643 * Tx won't hang if a GCL is already running,
644 * so in this case we don't need to set FutScdDis.
645 */
646 if (!(rd32(IGC_BASET_H) || rd32(IGC_BASET_L)))
647 tqavctrl |= IGC_TQAVCTRL_FUTSCDDIS;
648
649 nsec = rd32(IGC_SYSTIML);
650 sec = rd32(IGC_SYSTIMH);
651 systim = ktime_set(sec, nsec);
652
653 adjust_time = adapter->base_time;
654 expires_time = ktime_sub_ns(adjust_time, systim);
655 hrtimer_start(&adapter->hrtimer, expires_time, HRTIMER_MODE_REL);
656 }
657 }
658
659 wr32(IGC_TQAVCTRL, tqavctrl);
660
661 wr32(IGC_QBVCYCLET_S, cycle);
662 wr32(IGC_QBVCYCLET, cycle);
663
664 baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
665 wr32(IGC_BASET_H, baset_h);
666
667 /* In i226, Future base time is only supported when FutScdDis bit
668 * is enabled and only active for re-configuration.
669 * In this case, initialize the base time with zero to create
670 * "re-configuration" scenario then only set the desired base time.
671 */
672 if (tqavctrl & IGC_TQAVCTRL_FUTSCDDIS)
673 wr32(IGC_BASET_L, 0);
674 wr32(IGC_BASET_L, baset_l);
675
676 return 0;
677 }
678
igc_tsn_reset(struct igc_adapter * adapter)679 int igc_tsn_reset(struct igc_adapter *adapter)
680 {
681 unsigned int new_flags;
682 int err = 0;
683
684 if (adapter->fpe.mmsv.pmac_enabled) {
685 err = igc_enable_empty_addr_recv(adapter);
686 if (err && net_ratelimit())
687 netdev_err(adapter->netdev, "Error adding empty address to MAC filter\n");
688 } else {
689 igc_disable_empty_addr_recv(adapter);
690 }
691
692 new_flags = igc_tsn_new_flags(adapter);
693
694 if (!(new_flags & IGC_FLAG_TSN_ANY_ENABLED))
695 return igc_tsn_disable_offload(adapter);
696
697 err = igc_tsn_enable_offload(adapter);
698 if (err < 0)
699 return err;
700
701 adapter->flags = new_flags;
702
703 return err;
704 }
705
igc_tsn_will_tx_mode_change(struct igc_adapter * adapter)706 static bool igc_tsn_will_tx_mode_change(struct igc_adapter *adapter)
707 {
708 bool any_tsn_enabled = !!(igc_tsn_new_flags(adapter) &
709 IGC_FLAG_TSN_ANY_ENABLED);
710
711 return (any_tsn_enabled && !igc_tsn_is_tx_mode_in_tsn(adapter)) ||
712 (!any_tsn_enabled && igc_tsn_is_tx_mode_in_tsn(adapter));
713 }
714
igc_tsn_offload_apply(struct igc_adapter * adapter)715 int igc_tsn_offload_apply(struct igc_adapter *adapter)
716 {
717 /* Per I225/6 HW Design Section 7.5.2.1 guideline, if tx mode change
718 * from legacy->tsn or tsn->legacy, then reset adapter is needed.
719 */
720 if (netif_running(adapter->netdev) &&
721 igc_tsn_will_tx_mode_change(adapter)) {
722 schedule_work(&adapter->reset_task);
723 return 0;
724 }
725
726 igc_tsn_reset(adapter);
727
728 return 0;
729 }
730