1 // SPDX-License-Identifier: GPL-2.0
2 // SPI to CAN driver for the Texas Instruments TCAN4x5x
3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
4
5 #include "tcan4x5x.h"
6
7 #define TCAN4X5X_EXT_CLK_DEF 40000000
8
9 #define TCAN4X5X_DEV_ID1 0x00
10 #define TCAN4X5X_DEV_ID1_TCAN 0x4e414354 /* ASCII TCAN */
11 #define TCAN4X5X_DEV_ID2 0x04
12 #define TCAN4X5X_REV 0x08
13 #define TCAN4X5X_STATUS 0x0C
14 #define TCAN4X5X_ERROR_STATUS_MASK 0x10
15 #define TCAN4X5X_CONTROL 0x14
16
17 #define TCAN4X5X_CONFIG 0x800
18 #define TCAN4X5X_TS_PRESCALE 0x804
19 #define TCAN4X5X_TEST_REG 0x808
20 #define TCAN4X5X_INT_FLAGS 0x820
21 #define TCAN4X5X_MCAN_INT_REG 0x824
22 #define TCAN4X5X_INT_EN 0x830
23
24 /* Interrupt bits */
25 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
26 #define TCAN4X5X_CANHCANL_INT_EN BIT(29)
27 #define TCAN4X5X_CANHBAT_INT_EN BIT(28)
28 #define TCAN4X5X_CANLGND_INT_EN BIT(27)
29 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
30 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
31 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
32 #define TCAN4X5X_UVSUP_INT_EN BIT(22)
33 #define TCAN4X5X_UVIO_INT_EN BIT(21)
34 #define TCAN4X5X_TSD_INT_EN BIT(19)
35 #define TCAN4X5X_ECCERR_INT_EN BIT(16)
36 #define TCAN4X5X_CANINT_INT_EN BIT(15)
37 #define TCAN4X5X_LWU_INT_EN BIT(14)
38 #define TCAN4X5X_CANSLNT_INT_EN BIT(10)
39 #define TCAN4X5X_CANDOM_INT_EN BIT(8)
40 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
41 #define TCAN4X5X_BUS_FAULT BIT(4)
42 #define TCAN4X5X_MCAN_INT BIT(1)
43 #define TCAN4X5X_ENABLE_TCAN_INT \
44 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
45 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
46
47 /* MCAN Interrupt bits */
48 #define TCAN4X5X_MCAN_IR_ARA BIT(29)
49 #define TCAN4X5X_MCAN_IR_PED BIT(28)
50 #define TCAN4X5X_MCAN_IR_PEA BIT(27)
51 #define TCAN4X5X_MCAN_IR_WD BIT(26)
52 #define TCAN4X5X_MCAN_IR_BO BIT(25)
53 #define TCAN4X5X_MCAN_IR_EW BIT(24)
54 #define TCAN4X5X_MCAN_IR_EP BIT(23)
55 #define TCAN4X5X_MCAN_IR_ELO BIT(22)
56 #define TCAN4X5X_MCAN_IR_BEU BIT(21)
57 #define TCAN4X5X_MCAN_IR_BEC BIT(20)
58 #define TCAN4X5X_MCAN_IR_DRX BIT(19)
59 #define TCAN4X5X_MCAN_IR_TOO BIT(18)
60 #define TCAN4X5X_MCAN_IR_MRAF BIT(17)
61 #define TCAN4X5X_MCAN_IR_TSW BIT(16)
62 #define TCAN4X5X_MCAN_IR_TEFL BIT(15)
63 #define TCAN4X5X_MCAN_IR_TEFF BIT(14)
64 #define TCAN4X5X_MCAN_IR_TEFW BIT(13)
65 #define TCAN4X5X_MCAN_IR_TEFN BIT(12)
66 #define TCAN4X5X_MCAN_IR_TFE BIT(11)
67 #define TCAN4X5X_MCAN_IR_TCF BIT(10)
68 #define TCAN4X5X_MCAN_IR_TC BIT(9)
69 #define TCAN4X5X_MCAN_IR_HPM BIT(8)
70 #define TCAN4X5X_MCAN_IR_RF1L BIT(7)
71 #define TCAN4X5X_MCAN_IR_RF1F BIT(6)
72 #define TCAN4X5X_MCAN_IR_RF1W BIT(5)
73 #define TCAN4X5X_MCAN_IR_RF1N BIT(4)
74 #define TCAN4X5X_MCAN_IR_RF0L BIT(3)
75 #define TCAN4X5X_MCAN_IR_RF0F BIT(2)
76 #define TCAN4X5X_MCAN_IR_RF0W BIT(1)
77 #define TCAN4X5X_MCAN_IR_RF0N BIT(0)
78 #define TCAN4X5X_ENABLE_MCAN_INT \
79 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
80 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
81 TCAN4X5X_MCAN_IR_RF1F)
82
83 #define TCAN4X5X_MRAM_START 0x8000
84 #define TCAN4X5X_MRAM_SIZE 0x800
85 #define TCAN4X5X_MCAN_OFFSET 0x1000
86
87 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
88 #define TCAN4X5X_SET_ALL_INT 0xffffffff
89
90 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
91 #define TCAN4X5X_MODE_SLEEP 0x00
92 #define TCAN4X5X_MODE_STANDBY BIT(6)
93 #define TCAN4X5X_MODE_NORMAL BIT(7)
94
95 #define TCAN4X5X_NWKRQ_VOLTAGE_VIO BIT(19)
96
97 #define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30))
98 #define TCAN4X5X_DISABLE_INH_MSK BIT(9)
99
100 #define TCAN4X5X_SW_RESET BIT(2)
101
102 #define TCAN4X5X_MCAN_CONFIGURED BIT(5)
103 #define TCAN4X5X_WATCHDOG_EN BIT(3)
104 #define TCAN4X5X_WD_60_MS_TIMER 0
105 #define TCAN4X5X_WD_600_MS_TIMER BIT(28)
106 #define TCAN4X5X_WD_3_S_TIMER BIT(29)
107 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
108
109 struct tcan4x5x_version_info {
110 const char *name;
111 u32 id2_register;
112
113 bool has_wake_pin;
114 bool has_state_pin;
115 };
116
117 enum {
118 TCAN4552 = 0,
119 TCAN4553,
120 TCAN4X5X,
121 };
122
123 static const struct tcan4x5x_version_info tcan4x5x_versions[] = {
124 [TCAN4552] = {
125 .name = "4552",
126 .id2_register = 0x32353534,
127 },
128 [TCAN4553] = {
129 .name = "4553",
130 .id2_register = 0x33353534,
131 },
132 /* generic version with no id2_register at the end */
133 [TCAN4X5X] = {
134 .name = "generic",
135 .has_wake_pin = true,
136 .has_state_pin = true,
137 },
138 };
139
cdev_to_priv(struct m_can_classdev * cdev)140 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev)
141 {
142 return container_of(cdev, struct tcan4x5x_priv, cdev);
143 }
144
tcan4x5x_check_wake(struct tcan4x5x_priv * priv)145 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
146 {
147 int wake_state = 0;
148
149 if (priv->device_state_gpio)
150 wake_state = gpiod_get_value(priv->device_state_gpio);
151
152 if (priv->device_wake_gpio && wake_state) {
153 gpiod_set_value(priv->device_wake_gpio, 0);
154 usleep_range(5, 50);
155 gpiod_set_value(priv->device_wake_gpio, 1);
156 }
157 }
158
tcan4x5x_reset(struct tcan4x5x_priv * priv)159 static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
160 {
161 int ret = 0;
162
163 if (priv->reset_gpio) {
164 gpiod_set_value(priv->reset_gpio, 1);
165
166 /* tpulse_width minimum 30us */
167 usleep_range(30, 100);
168 gpiod_set_value(priv->reset_gpio, 0);
169 } else {
170 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
171 TCAN4X5X_SW_RESET);
172 if (ret)
173 return ret;
174 }
175
176 usleep_range(700, 1000);
177
178 return ret;
179 }
180
tcan4x5x_read_reg(struct m_can_classdev * cdev,int reg)181 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
182 {
183 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
184 u32 val;
185
186 regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val);
187
188 return val;
189 }
190
tcan4x5x_read_fifo(struct m_can_classdev * cdev,int addr_offset,void * val,size_t val_count)191 static int tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset,
192 void *val, size_t val_count)
193 {
194 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
195
196 return regmap_bulk_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count);
197 }
198
tcan4x5x_write_reg(struct m_can_classdev * cdev,int reg,int val)199 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
200 {
201 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
202
203 return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val);
204 }
205
tcan4x5x_write_fifo(struct m_can_classdev * cdev,int addr_offset,const void * val,size_t val_count)206 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
207 int addr_offset, const void *val, size_t val_count)
208 {
209 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
210
211 return regmap_bulk_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count);
212 }
213
tcan4x5x_power_enable(struct tcan4x5x_priv * priv,int enable)214 static int tcan4x5x_power_enable(struct tcan4x5x_priv *priv, int enable)
215 {
216 struct regulator *reg = priv->power;
217
218 /*
219 * Put the device into sleep mode if the RST pin is available,
220 * since a wake-up event, RST pin toggle, or power cycle are the only
221 * ways to exit sleep mode.
222 * Redundant if the regulator is exclusive to this device, but that
223 * can't be determined here.
224 *
225 * Datasheet: TCAN4550, section "8.4.3 Sleep Mode"
226 * https://www.ti.com/lit/gpn/tcan4550
227 */
228 if (priv->reset_gpio && !enable) {
229 int ret;
230
231 ret = regmap_update_bits(priv->regmap, TCAN4X5X_CONFIG,
232 TCAN4X5X_MODE_SEL_MASK,
233 TCAN4X5X_MODE_SLEEP);
234 if (ret)
235 dev_err(&priv->spi->dev, "Setting sleep mode failed %pe\n",
236 ERR_PTR(ret));
237 }
238
239 if (IS_ERR_OR_NULL(reg))
240 return 0;
241
242 if (enable)
243 return regulator_enable(reg);
244 else
245 return regulator_disable(reg);
246 }
247
tcan4x5x_write_tcan_reg(struct m_can_classdev * cdev,int reg,int val)248 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
249 int reg, int val)
250 {
251 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
252
253 return regmap_write(priv->regmap, reg, val);
254 }
255
tcan4x5x_clear_interrupts(struct m_can_classdev * cdev)256 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
257 {
258 int ret;
259
260 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
261 TCAN4X5X_CLEAR_ALL_INT);
262 if (ret)
263 return ret;
264
265 return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
266 TCAN4X5X_CLEAR_ALL_INT);
267 }
268
tcan4x5x_init(struct m_can_classdev * cdev)269 static int tcan4x5x_init(struct m_can_classdev *cdev)
270 {
271 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
272 int ret;
273
274 tcan4x5x_check_wake(tcan4x5x);
275
276 ret = tcan4x5x_clear_interrupts(cdev);
277 if (ret)
278 return ret;
279
280 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
281 TCAN4X5X_ENABLE_TCAN_INT);
282 if (ret)
283 return ret;
284
285 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS_MASK,
286 TCAN4X5X_CLEAR_ALL_INT);
287 if (ret)
288 return ret;
289
290 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
291 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
292 if (ret)
293 return ret;
294
295 if (tcan4x5x->nwkrq_voltage_vio) {
296 ret = regmap_set_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
297 TCAN4X5X_NWKRQ_VOLTAGE_VIO);
298 if (ret)
299 return ret;
300 }
301
302 return ret;
303 }
304
tcan4x5x_deinit(struct m_can_classdev * cdev)305 static int tcan4x5x_deinit(struct m_can_classdev *cdev)
306 {
307 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
308
309 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
310 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_STANDBY);
311 };
312
tcan4x5x_disable_wake(struct m_can_classdev * cdev)313 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
314 {
315 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
316
317 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
318 TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
319 }
320
tcan4x5x_disable_state(struct m_can_classdev * cdev)321 static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
322 {
323 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
324
325 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
326 TCAN4X5X_DISABLE_INH_MSK, 0x01);
327 }
328
329 static const struct tcan4x5x_version_info
tcan4x5x_find_version(struct tcan4x5x_priv * priv)330 *tcan4x5x_find_version(struct tcan4x5x_priv *priv)
331 {
332 u32 val;
333 int ret;
334
335 ret = regmap_read(priv->regmap, TCAN4X5X_DEV_ID1, &val);
336 if (ret)
337 return ERR_PTR(ret);
338
339 if (val != TCAN4X5X_DEV_ID1_TCAN) {
340 dev_err(&priv->spi->dev, "Not a tcan device %x\n", val);
341 return ERR_PTR(-ENODEV);
342 }
343
344 ret = regmap_read(priv->regmap, TCAN4X5X_DEV_ID2, &val);
345 if (ret)
346 return ERR_PTR(ret);
347
348 for (int i = 0; i != ARRAY_SIZE(tcan4x5x_versions); ++i) {
349 const struct tcan4x5x_version_info *vinfo = &tcan4x5x_versions[i];
350
351 if (!vinfo->id2_register || val == vinfo->id2_register) {
352 dev_info(&priv->spi->dev, "Detected TCAN device version %s\n",
353 vinfo->name);
354 return vinfo;
355 }
356 }
357
358 return &tcan4x5x_versions[TCAN4X5X];
359 }
360
tcan4x5x_get_dt_data(struct m_can_classdev * cdev)361 static void tcan4x5x_get_dt_data(struct m_can_classdev *cdev)
362 {
363 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
364
365 tcan4x5x->nwkrq_voltage_vio =
366 of_property_read_bool(cdev->dev->of_node, "ti,nwkrq-voltage-vio");
367 }
368
tcan4x5x_get_gpios(struct m_can_classdev * cdev)369 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev)
370 {
371 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
372 int ret;
373
374 tcan4x5x->device_wake_gpio = devm_gpiod_get_optional(cdev->dev,
375 "device-wake",
376 GPIOD_OUT_HIGH);
377 if (IS_ERR(tcan4x5x->device_wake_gpio)) {
378 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER)
379 return -EPROBE_DEFER;
380
381 tcan4x5x->device_wake_gpio = NULL;
382 }
383
384 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
385 GPIOD_OUT_LOW);
386 if (IS_ERR(tcan4x5x->reset_gpio))
387 tcan4x5x->reset_gpio = NULL;
388
389 ret = tcan4x5x_reset(tcan4x5x);
390 if (ret)
391 return ret;
392
393 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
394 "device-state",
395 GPIOD_IN);
396 if (IS_ERR(tcan4x5x->device_state_gpio))
397 tcan4x5x->device_state_gpio = NULL;
398
399 return 0;
400 }
401
tcan4x5x_check_gpios(struct m_can_classdev * cdev,const struct tcan4x5x_version_info * version_info)402 static int tcan4x5x_check_gpios(struct m_can_classdev *cdev,
403 const struct tcan4x5x_version_info *version_info)
404 {
405 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
406 int ret;
407
408 if (version_info->has_wake_pin && !tcan4x5x->device_wake_gpio) {
409 ret = tcan4x5x_disable_wake(cdev);
410 if (ret)
411 return ret;
412 }
413
414 if (version_info->has_state_pin && !tcan4x5x->device_state_gpio) {
415 ret = tcan4x5x_disable_state(cdev);
416 if (ret)
417 return ret;
418 }
419
420 return 0;
421 }
422
423 static const struct m_can_ops tcan4x5x_ops = {
424 .init = tcan4x5x_init,
425 .deinit = tcan4x5x_deinit,
426 .read_reg = tcan4x5x_read_reg,
427 .write_reg = tcan4x5x_write_reg,
428 .write_fifo = tcan4x5x_write_fifo,
429 .read_fifo = tcan4x5x_read_fifo,
430 .clear_interrupts = tcan4x5x_clear_interrupts,
431 };
432
tcan4x5x_can_probe(struct spi_device * spi)433 static int tcan4x5x_can_probe(struct spi_device *spi)
434 {
435 const struct tcan4x5x_version_info *version_info;
436 struct tcan4x5x_priv *priv;
437 struct m_can_classdev *mcan_class;
438 int freq, ret;
439
440 mcan_class = m_can_class_allocate_dev(&spi->dev,
441 sizeof(struct tcan4x5x_priv));
442 if (IS_ERR(mcan_class))
443 return PTR_ERR(mcan_class);
444
445 ret = m_can_check_mram_cfg(mcan_class, TCAN4X5X_MRAM_SIZE);
446 if (ret)
447 goto out_m_can_class_free_dev;
448
449 priv = cdev_to_priv(mcan_class);
450
451 priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
452 if (IS_ERR(priv->power)) {
453 if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
454 ret = -EPROBE_DEFER;
455 goto out_m_can_class_free_dev;
456 }
457 priv->power = NULL;
458 }
459
460 mcan_class->cclk = devm_clk_get(mcan_class->dev, "cclk");
461 if (IS_ERR(mcan_class->cclk)) {
462 dev_err(&spi->dev, "no CAN clock source defined\n");
463 freq = TCAN4X5X_EXT_CLK_DEF;
464 } else {
465 freq = clk_get_rate(mcan_class->cclk);
466 }
467
468 /* Sanity check */
469 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) {
470 dev_err(&spi->dev, "Clock frequency is out of supported range %d\n",
471 freq);
472 ret = -ERANGE;
473 goto out_m_can_class_free_dev;
474 }
475
476 priv->spi = spi;
477
478 mcan_class->pm_clock_support = 0;
479 mcan_class->pm_wake_source = device_property_read_bool(&spi->dev, "wakeup-source");
480 mcan_class->can.clock.freq = freq;
481 mcan_class->dev = &spi->dev;
482 mcan_class->ops = &tcan4x5x_ops;
483 mcan_class->is_peripheral = true;
484 mcan_class->net->irq = spi->irq;
485
486 spi_set_drvdata(spi, priv);
487
488 /* Configure the SPI bus */
489 spi->bits_per_word = 8;
490 ret = spi_setup(spi);
491 if (ret) {
492 dev_err(&spi->dev, "SPI setup failed %pe\n", ERR_PTR(ret));
493 goto out_m_can_class_free_dev;
494 }
495
496 ret = tcan4x5x_regmap_init(priv);
497 if (ret) {
498 dev_err(&spi->dev, "regmap init failed %pe\n", ERR_PTR(ret));
499 goto out_m_can_class_free_dev;
500 }
501
502 ret = tcan4x5x_power_enable(priv, 1);
503 if (ret) {
504 dev_err(&spi->dev, "Enabling regulator failed %pe\n",
505 ERR_PTR(ret));
506 goto out_m_can_class_free_dev;
507 }
508
509 ret = tcan4x5x_get_gpios(mcan_class);
510 if (ret) {
511 dev_err(&spi->dev, "Getting gpios failed %pe\n", ERR_PTR(ret));
512 goto out_power;
513 }
514
515 version_info = tcan4x5x_find_version(priv);
516 if (IS_ERR(version_info)) {
517 ret = PTR_ERR(version_info);
518 goto out_power;
519 }
520
521 ret = tcan4x5x_check_gpios(mcan_class, version_info);
522 if (ret) {
523 dev_err(&spi->dev, "Checking gpios failed %pe\n", ERR_PTR(ret));
524 goto out_power;
525 }
526
527 tcan4x5x_get_dt_data(mcan_class);
528
529 tcan4x5x_check_wake(priv);
530
531 ret = tcan4x5x_write_tcan_reg(mcan_class, TCAN4X5X_INT_EN, 0);
532 if (ret) {
533 dev_err(&spi->dev, "Disabling interrupts failed %pe\n", ERR_PTR(ret));
534 goto out_power;
535 }
536
537 ret = tcan4x5x_clear_interrupts(mcan_class);
538 if (ret) {
539 dev_err(&spi->dev, "Clearing interrupts failed %pe\n", ERR_PTR(ret));
540 goto out_power;
541 }
542
543 if (mcan_class->pm_wake_source)
544 device_init_wakeup(&spi->dev, true);
545
546 ret = m_can_class_register(mcan_class);
547 if (ret) {
548 dev_err(&spi->dev, "Failed registering m_can device %pe\n",
549 ERR_PTR(ret));
550 goto out_power;
551 }
552
553 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
554 return 0;
555
556 out_power:
557 tcan4x5x_power_enable(priv, 0);
558 out_m_can_class_free_dev:
559 m_can_class_free_dev(mcan_class->net);
560 return ret;
561 }
562
tcan4x5x_can_remove(struct spi_device * spi)563 static void tcan4x5x_can_remove(struct spi_device *spi)
564 {
565 struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
566
567 m_can_class_unregister(&priv->cdev);
568
569 tcan4x5x_power_enable(priv, 0);
570
571 m_can_class_free_dev(priv->cdev.net);
572 }
573
tcan4x5x_suspend(struct device * dev)574 static int __maybe_unused tcan4x5x_suspend(struct device *dev)
575 {
576 struct m_can_classdev *cdev = dev_get_drvdata(dev);
577 struct spi_device *spi = to_spi_device(dev);
578
579 if (cdev->pm_wake_source)
580 enable_irq_wake(spi->irq);
581
582 return m_can_class_suspend(dev);
583 }
584
tcan4x5x_resume(struct device * dev)585 static int __maybe_unused tcan4x5x_resume(struct device *dev)
586 {
587 struct m_can_classdev *cdev = dev_get_drvdata(dev);
588 struct spi_device *spi = to_spi_device(dev);
589 int ret = m_can_class_resume(dev);
590
591 if (cdev->pm_wake_source)
592 disable_irq_wake(spi->irq);
593
594 return ret;
595 }
596
597 static const struct of_device_id tcan4x5x_of_match[] = {
598 {
599 .compatible = "ti,tcan4x5x",
600 }, {
601 /* sentinel */
602 },
603 };
604 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
605
606 static const struct spi_device_id tcan4x5x_id_table[] = {
607 {
608 .name = "tcan4x5x",
609 }, {
610 /* sentinel */
611 },
612 };
613 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
614
615 static const struct dev_pm_ops tcan4x5x_pm_ops = {
616 SET_SYSTEM_SLEEP_PM_OPS(tcan4x5x_suspend, tcan4x5x_resume)
617 };
618
619 static struct spi_driver tcan4x5x_can_driver = {
620 .driver = {
621 .name = KBUILD_MODNAME,
622 .of_match_table = tcan4x5x_of_match,
623 .pm = &tcan4x5x_pm_ops,
624 },
625 .id_table = tcan4x5x_id_table,
626 .probe = tcan4x5x_can_probe,
627 .remove = tcan4x5x_can_remove,
628 };
629 module_spi_driver(tcan4x5x_can_driver);
630
631 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
632 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
633 MODULE_LICENSE("GPL v2");
634