1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 3#include <dt-bindings/clock/nvidia,tegra264.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/nvidia,tegra264.h> 7#include <dt-bindings/power/nvidia,tegra264-bpmp.h> 8#include <dt-bindings/reset/nvidia,tegra264.h> 9 10/ { 11 compatible = "nvidia,tegra264"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 shmem_bpmp: shmem@86070000 { 22 compatible = "nvidia,tegra264-bpmp-shmem"; 23 reg = <0x0 0x86070000 0x0 0x2000>; 24 no-map; 25 }; 26 }; 27 28 /* SYSTEM MMIO */ 29 bus@0 { 30 compatible = "simple-bus"; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 ranges = <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ 36 37 misc@100000 { 38 compatible = "nvidia,tegra234-misc"; 39 reg = <0x0 0x00100000 0x0 0x0f000>, 40 <0x0 0x0c140000 0x0 0x10000>; 41 }; 42 43 timer@8000000 { 44 compatible = "nvidia,tegra234-timer"; 45 reg = <0x0 0x08000000 0x0 0x140000>; 46 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 50 status = "disabled"; 51 }; 52 53 hte_lic: hardware-timestamp@8380000 { 54 compatible = "nvidia,tegra264-gte-lic"; 55 reg = <0x0 0x08380000 0x0 0x10000>; 56 interrupts = <GIC_SPI 0x00000268 IRQ_TYPE_LEVEL_HIGH>; 57 nvidia,int-threshold = <1>; 58 #timestamp-cells = <1>; 59 status = "disabled"; 60 }; 61 62 gpcdma: dma-controller@8400000 { 63 compatible = "nvidia,tegra264-gpcdma"; 64 reg = <0x0 0x08400000 0x0 0x210000>; 65 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 97 #dma-cells = <1>; 98 iommus = <&smmu1 0x00000800>; 99 iommu-map = <1 &smmu1 0x801 31>; 100 dma-coherent; 101 dma-channel-mask = <0xfffffffe>; 102 status = "disabled"; 103 }; 104 105 hsp_top: hsp@8800000 { 106 compatible = "nvidia,tegra264-hsp"; 107 reg = <0x0 0x08800000 0x0 0xd0000>; 108 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 118 "shared3", "shared4", "shared5", "shared6", 119 "shared7"; 120 #mbox-cells = <2>; 121 }; 122 123 aconnect@9000000 { 124 compatible = "nvidia,tegra264-aconnect", 125 "nvidia,tegra210-aconnect"; 126 clocks = <&bpmp TEGRA264_CLK_APE>, 127 <&bpmp TEGRA264_CLK_ADSP>; 128 clock-names = "ape", "apb2ape"; 129 power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; 130 status = "disabled"; 131 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; 135 136 adma: dma-controller@9440000 { 137 compatible = "nvidia,tegra264-adma"; 138 reg = <0x0 0x9440000 0x0 0xb0000>; 139 interrupt-parent = <&agic_page0>; 140 interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>; 204 #dma-cells = <1>; 205 clocks = <&bpmp TEGRA264_CLK_AHUB>; 206 clock-names = "d_audio"; 207 status = "disabled"; 208 }; 209 210 tegra_ahub: ahub@9630000 { 211 compatible = "nvidia,tegra264-ahub"; 212 reg = <0x0 0x9630000 0x0 0x10000>; 213 clocks = <&bpmp TEGRA264_CLK_AHUB>; 214 clock-names = "ahub"; 215 assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>; 216 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>; 217 status = "disabled"; 218 219 #address-cells = <2>; 220 #size-cells = <2>; 221 /* ADMA is under AHUB range, its excluded in the defined range */ 222 ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, 223 <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; 224 225 tegra_i2s1: i2s@9280000 { 226 compatible = "nvidia,tegra264-i2s"; 227 reg = <0x0 0x9280000 0x0 0x10000>; 228 clocks = <&bpmp TEGRA264_CLK_I2S1>, 229 <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; 230 clock-names = "i2s", "sync_input"; 231 assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>; 232 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 233 assigned-clock-rates = <1536000>; 234 sound-name-prefix = "I2S1"; 235 status = "disabled"; 236 237 ports { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 port@0 { 242 reg = <0>; 243 244 i2s1_cif: endpoint { 245 remote-endpoint = <&xbar_i2s1>; 246 }; 247 }; 248 249 i2s1_port: port@1 { 250 reg = <1>; 251 252 i2s1_dap: endpoint { 253 dai-format = "i2s"; 254 /* placeholder for external codec */ 255 }; 256 }; 257 }; 258 }; 259 260 tegra_i2s2: i2s@9290000 { 261 compatible = "nvidia,tegra264-i2s"; 262 reg = <0x0 0x9290000 0x0 0x10000>; 263 clocks = <&bpmp TEGRA264_CLK_I2S2>, 264 <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; 265 clock-names = "i2s", "sync_input"; 266 assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>; 267 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 268 assigned-clock-rates = <1536000>; 269 sound-name-prefix = "I2S2"; 270 status = "disabled"; 271 272 ports { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 port@0 { 277 reg = <0>; 278 279 i2s2_cif: endpoint { 280 remote-endpoint = <&xbar_i2s2>; 281 }; 282 }; 283 284 i2s2_port: port@1 { 285 reg = <1>; 286 287 i2s2_dap: endpoint { 288 dai-format = "i2s"; 289 /* placeholder for external codec */ 290 }; 291 }; 292 }; 293 }; 294 295 tegra_i2s3: i2s@92a0000 { 296 compatible = "nvidia,tegra264-i2s"; 297 reg = <0x0 0x92a0000 0x0 0x10000>; 298 clocks = <&bpmp TEGRA264_CLK_I2S3>, 299 <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; 300 clock-names = "i2s", "sync_input"; 301 assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>; 302 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 303 assigned-clock-rates = <1536000>; 304 sound-name-prefix = "I2S3"; 305 status = "disabled"; 306 307 ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 314 i2s3_cif: endpoint { 315 remote-endpoint = <&xbar_i2s3>; 316 }; 317 }; 318 319 i2s3_port: port@1 { 320 reg = <1>; 321 322 i2s3_dap: endpoint { 323 dai-format = "i2s"; 324 /* placeholder for external codec */ 325 }; 326 }; 327 }; 328 }; 329 330 tegra_i2s4: i2s@92b0000 { 331 compatible = "nvidia,tegra264-i2s"; 332 reg = <0x0 0x92b0000 0x0 0x10000>; 333 clocks = <&bpmp TEGRA264_CLK_I2S4>, 334 <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; 335 clock-names = "i2s", "sync_input"; 336 assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>; 337 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 338 assigned-clock-rates = <1536000>; 339 sound-name-prefix = "I2S4"; 340 status = "disabled"; 341 342 ports { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 port@0 { 347 reg = <0>; 348 349 i2s4_cif: endpoint { 350 remote-endpoint = <&xbar_i2s4>; 351 }; 352 }; 353 354 i2s4_port: port@1 { 355 reg = <1>; 356 357 i2s4_dap: endpoint { 358 dai-format = "i2s"; 359 /* placeholder for external codec */ 360 }; 361 }; 362 }; 363 }; 364 365 tegra_i2s5: i2s@92c0000 { 366 compatible = "nvidia,tegra264-i2s"; 367 reg = <0x0 0x92c0000 0x0 0x10000>; 368 clocks = <&bpmp TEGRA264_CLK_I2S5>, 369 <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; 370 clock-names = "i2s", "sync_input"; 371 assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>; 372 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 373 assigned-clock-rates = <1536000>; 374 sound-name-prefix = "I2S5"; 375 status = "disabled"; 376 377 ports { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 381 port@0 { 382 reg = <0>; 383 384 i2s5_cif: endpoint { 385 remote-endpoint = <&xbar_i2s5>; 386 }; 387 }; 388 389 i2s5_port: port@1 { 390 reg = <1>; 391 392 i2s5_dap: endpoint { 393 dai-format = "i2s"; 394 /* placeholder for external codec */ 395 }; 396 }; 397 }; 398 }; 399 400 tegra_i2s6: i2s@92d0000 { 401 compatible = "nvidia,tegra264-i2s"; 402 reg = <0x0 0x92d0000 0x0 0x10000>; 403 clocks = <&bpmp TEGRA264_CLK_I2S6>, 404 <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; 405 clock-names = "i2s", "sync_input"; 406 assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>; 407 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 408 assigned-clock-rates = <1536000>; 409 sound-name-prefix = "I2S6"; 410 status = "disabled"; 411 412 ports { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 416 port@0 { 417 reg = <0>; 418 419 i2s6_cif: endpoint { 420 remote-endpoint = <&xbar_i2s6>; 421 }; 422 }; 423 424 i2s6_port: port@1 { 425 reg = <1>; 426 427 i2s6_dap: endpoint { 428 dai-format = "i2s"; 429 /* placeholder for external codec */ 430 }; 431 }; 432 }; 433 }; 434 435 tegra_i2s7: i2s@92e0000 { 436 compatible = "nvidia,tegra264-i2s"; 437 reg = <0x0 0x92e0000 0x0 0x10000>; 438 clocks = <&bpmp TEGRA264_CLK_I2S7>, 439 <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; 440 clock-names = "i2s", "sync_input"; 441 assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>; 442 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 443 assigned-clock-rates = <1536000>; 444 sound-name-prefix = "I2S7"; 445 status = "disabled"; 446 447 ports { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 port@0 { 452 reg = <0>; 453 454 i2s7_cif: endpoint { 455 remote-endpoint = <&xbar_i2s7>; 456 }; 457 }; 458 459 i2s7_port: port@1 { 460 reg = <1>; 461 462 i2s7_dap: endpoint { 463 dai-format = "i2s"; 464 /* placeholder for external codec */ 465 }; 466 }; 467 }; 468 }; 469 470 tegra_i2s8: i2s@92f0000 { 471 compatible = "nvidia,tegra264-i2s"; 472 reg = <0x0 0x92f0000 0x0 0x10000>; 473 clocks = <&bpmp TEGRA264_CLK_I2S8>, 474 <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; 475 clock-names = "i2s", "sync_input"; 476 assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>; 477 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 478 assigned-clock-rates = <1536000>; 479 sound-name-prefix = "I2S8"; 480 status = "disabled"; 481 482 ports { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 port@0 { 487 reg = <0>; 488 489 i2s8_cif: endpoint { 490 remote-endpoint = <&xbar_i2s8>; 491 }; 492 }; 493 494 i2s8_port: port@1 { 495 reg = <1>; 496 497 i2s8_dap: endpoint { 498 dai-format = "i2s"; 499 /* placeholder for external codec */ 500 }; 501 }; 502 }; 503 }; 504 505 tegra_dmic1: dmic@9300000 { 506 compatible = "nvidia,tegra264-dmic", 507 "nvidia,tegra210-dmic"; 508 reg = <0x0 0x9300000 0x0 0x10000>; 509 clocks = <&bpmp TEGRA264_CLK_DMIC1>; 510 clock-names = "dmic"; 511 assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; 512 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 513 assigned-clock-rates = <3072000>; 514 sound-name-prefix = "DMIC1"; 515 status = "disabled"; 516 517 ports { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 521 port@0 { 522 reg = <0>; 523 524 dmic1_cif: endpoint { 525 remote-endpoint = <&xbar_dmic1>; 526 }; 527 }; 528 529 dmic1_port: port@1 { 530 reg = <1>; 531 532 dmic1_dap: endpoint { 533 /* placeholder for external codec */ 534 }; 535 }; 536 }; 537 }; 538 539 tegra_dmic2: dmic@9310000 { 540 compatible = "nvidia,tegra264-dmic", 541 "nvidia,tegra210-dmic"; 542 reg = <0x0 0x9310000 0x0 0x10000>; 543 clocks = <&bpmp TEGRA264_CLK_DMIC1>; 544 clock-names = "dmic"; 545 assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; 546 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 547 assigned-clock-rates = <3072000>; 548 sound-name-prefix = "DMIC2"; 549 status = "disabled"; 550 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 port@0 { 556 reg = <0>; 557 558 dmic2_cif: endpoint { 559 remote-endpoint = <&xbar_dmic2>; 560 }; 561 }; 562 563 dmic2_port: port@1 { 564 reg = <1>; 565 566 dmic2_dap: endpoint { 567 /* placeholder for external codec */ 568 }; 569 }; 570 }; 571 }; 572 573 tegra_dspk1: dspk@9380000 { 574 compatible = "nvidia,tegra264-dspk", 575 "nvidia,tegra186-dspk"; 576 reg = <0x0 0x9380000 0x0 0x10000>; 577 clocks = <&bpmp TEGRA264_CLK_DSPK1>; 578 clock-names = "dspk"; 579 assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>; 580 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 581 assigned-clock-rates = <12288000>; 582 sound-name-prefix = "DSPK1"; 583 status = "disabled"; 584 585 ports { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 589 port@0 { 590 reg = <0>; 591 592 dspk1_cif: endpoint { 593 remote-endpoint = <&xbar_dspk1>; 594 }; 595 }; 596 597 dspk1_port: port@1 { 598 reg = <1>; 599 600 dspk1_dap: endpoint { 601 /* placeholder for external codec */ 602 }; 603 }; 604 }; 605 }; 606 607 tegra_amx1: amx@9510000 { 608 compatible = "nvidia,tegra264-amx"; 609 reg = <0x0 0x9510000 0x0 0x10000>; 610 sound-name-prefix = "AMX1"; 611 612 ports { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 616 port@0 { 617 reg = <0>; 618 619 amx1_in1: endpoint { 620 remote-endpoint = <&xbar_amx1_in1>; 621 }; 622 }; 623 624 port@1 { 625 reg = <1>; 626 627 amx1_in2: endpoint { 628 remote-endpoint = <&xbar_amx1_in2>; 629 }; 630 }; 631 632 port@2 { 633 reg = <2>; 634 635 amx1_in3: endpoint { 636 remote-endpoint = <&xbar_amx1_in3>; 637 }; 638 }; 639 640 port@3 { 641 reg = <3>; 642 643 amx1_in4: endpoint { 644 remote-endpoint = <&xbar_amx1_in4>; 645 }; 646 }; 647 648 amx1_out_port: port@4 { 649 reg = <4>; 650 651 amx1_out: endpoint { 652 remote-endpoint = <&xbar_amx1_out>; 653 }; 654 }; 655 }; 656 }; 657 658 tegra_amx2: amx@9520000 { 659 compatible = "nvidia,tegra264-amx"; 660 reg = <0x0 0x9520000 0x0 0x10000>; 661 sound-name-prefix = "AMX2"; 662 663 ports { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 667 port@0 { 668 reg = <0>; 669 670 amx2_in1: endpoint { 671 remote-endpoint = <&xbar_amx2_in1>; 672 }; 673 }; 674 675 port@1 { 676 reg = <1>; 677 678 amx2_in2: endpoint { 679 remote-endpoint = <&xbar_amx2_in2>; 680 }; 681 }; 682 683 port@2 { 684 reg = <2>; 685 686 amx2_in3: endpoint { 687 remote-endpoint = <&xbar_amx2_in3>; 688 }; 689 }; 690 691 port@3 { 692 reg = <3>; 693 694 amx2_in4: endpoint { 695 remote-endpoint = <&xbar_amx2_in4>; 696 }; 697 }; 698 699 amx2_out_port: port@4 { 700 reg = <4>; 701 702 amx2_out: endpoint { 703 remote-endpoint = <&xbar_amx2_out>; 704 }; 705 }; 706 }; 707 }; 708 709 tegra_amx3: amx@9530000 { 710 compatible = "nvidia,tegra264-amx"; 711 reg = <0x0 0x9530000 0x0 0x10000>; 712 sound-name-prefix = "AMX3"; 713 714 ports { 715 #address-cells = <1>; 716 #size-cells = <0>; 717 718 port@0 { 719 reg = <0>; 720 721 amx3_in1: endpoint { 722 remote-endpoint = <&xbar_amx3_in1>; 723 }; 724 }; 725 726 port@1 { 727 reg = <1>; 728 729 amx3_in2: endpoint { 730 remote-endpoint = <&xbar_amx3_in2>; 731 }; 732 }; 733 734 port@2 { 735 reg = <2>; 736 737 amx3_in3: endpoint { 738 remote-endpoint = <&xbar_amx3_in3>; 739 }; 740 }; 741 742 port@3 { 743 reg = <3>; 744 745 amx3_in4: endpoint { 746 remote-endpoint = <&xbar_amx3_in4>; 747 }; 748 }; 749 750 amx3_out_port: port@4 { 751 reg = <4>; 752 753 amx3_out: endpoint { 754 remote-endpoint = <&xbar_amx3_out>; 755 }; 756 }; 757 }; 758 }; 759 760 tegra_amx4: amx@9540000 { 761 compatible = "nvidia,tegra264-amx"; 762 reg = <0x0 0x9540000 0x0 0x10000>; 763 sound-name-prefix = "AMX4"; 764 765 ports { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 port@0 { 770 reg = <0>; 771 772 amx4_in1: endpoint { 773 remote-endpoint = <&xbar_amx4_in1>; 774 }; 775 }; 776 777 port@1 { 778 reg = <1>; 779 780 amx4_in2: endpoint { 781 remote-endpoint = <&xbar_amx4_in2>; 782 }; 783 }; 784 785 port@2 { 786 reg = <2>; 787 788 amx4_in3: endpoint { 789 remote-endpoint = <&xbar_amx4_in3>; 790 }; 791 }; 792 793 port@3 { 794 reg = <3>; 795 796 amx4_in4: endpoint { 797 remote-endpoint = <&xbar_amx4_in4>; 798 }; 799 }; 800 801 amx4_out_port: port@4 { 802 reg = <4>; 803 804 amx4_out: endpoint { 805 remote-endpoint = <&xbar_amx4_out>; 806 }; 807 }; 808 }; 809 }; 810 811 tegra_amx5: amx@9550000 { 812 compatible = "nvidia,tegra264-amx"; 813 reg = <0x0 0x9550000 0x0 0x10000>; 814 sound-name-prefix = "AMX5"; 815 816 ports { 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 port@0 { 821 reg = <0>; 822 823 amx5_in1: endpoint { 824 remote-endpoint = <&xbar_amx5_in1>; 825 }; 826 }; 827 828 port@1 { 829 reg = <1>; 830 831 amx5_in2: endpoint { 832 remote-endpoint = <&xbar_amx5_in2>; 833 }; 834 }; 835 836 port@2 { 837 reg = <2>; 838 839 amx5_in3: endpoint { 840 remote-endpoint = <&xbar_amx5_in3>; 841 }; 842 }; 843 844 port@3 { 845 reg = <3>; 846 847 amx5_in4: endpoint { 848 remote-endpoint = <&xbar_amx5_in4>; 849 }; 850 }; 851 852 amx5_out_port: port@4 { 853 reg = <4>; 854 855 amx5_out: endpoint { 856 remote-endpoint = <&xbar_amx5_out>; 857 }; 858 }; 859 }; 860 }; 861 862 tegra_amx6: amx@9560000 { 863 compatible = "nvidia,tegra264-amx"; 864 reg = <0x0 0x9560000 0x0 0x10000>; 865 sound-name-prefix = "AMX6"; 866 867 ports { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 port@0 { 872 reg = <0>; 873 874 amx6_in1: endpoint { 875 remote-endpoint = <&xbar_amx6_in1>; 876 }; 877 }; 878 879 port@1 { 880 reg = <1>; 881 882 amx6_in2: endpoint { 883 remote-endpoint = <&xbar_amx6_in2>; 884 }; 885 }; 886 887 port@2 { 888 reg = <2>; 889 890 amx6_in3: endpoint { 891 remote-endpoint = <&xbar_amx6_in3>; 892 }; 893 }; 894 895 port@3 { 896 reg = <3>; 897 898 amx6_in4: endpoint { 899 remote-endpoint = <&xbar_amx6_in4>; 900 }; 901 }; 902 903 amx6_out_port: port@4 { 904 reg = <4>; 905 906 amx6_out: endpoint { 907 remote-endpoint = <&xbar_amx6_out>; 908 }; 909 }; 910 }; 911 }; 912 913 tegra_adx1: adx@9590000 { 914 compatible = "nvidia,tegra264-adx"; 915 reg = <0x0 0x9590000 0x0 0x10000>; 916 sound-name-prefix = "ADX1"; 917 918 ports { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 port@0 { 923 reg = <0>; 924 925 adx1_in: endpoint { 926 remote-endpoint = <&xbar_adx1_in>; 927 }; 928 }; 929 930 adx1_out1_port: port@1 { 931 reg = <1>; 932 933 adx1_out1: endpoint { 934 remote-endpoint = <&xbar_adx1_out1>; 935 }; 936 }; 937 938 adx1_out2_port: port@2 { 939 reg = <2>; 940 941 adx1_out2: endpoint { 942 remote-endpoint = <&xbar_adx1_out2>; 943 }; 944 }; 945 946 adx1_out3_port: port@3 { 947 reg = <3>; 948 949 adx1_out3: endpoint { 950 remote-endpoint = <&xbar_adx1_out3>; 951 }; 952 }; 953 954 adx1_out4_port: port@4 { 955 reg = <4>; 956 957 adx1_out4: endpoint { 958 remote-endpoint = <&xbar_adx1_out4>; 959 }; 960 }; 961 }; 962 }; 963 964 tegra_adx2: adx@95a0000 { 965 compatible = "nvidia,tegra264-adx"; 966 reg = <0x0 0x95a0000 0x0 0x10000>; 967 sound-name-prefix = "ADX2"; 968 969 ports { 970 #address-cells = <1>; 971 #size-cells = <0>; 972 973 port@0 { 974 reg = <0>; 975 976 adx2_in: endpoint { 977 remote-endpoint = <&xbar_adx2_in>; 978 }; 979 }; 980 981 adx2_out1_port: port@1 { 982 reg = <1>; 983 984 adx2_out1: endpoint { 985 remote-endpoint = <&xbar_adx2_out1>; 986 }; 987 }; 988 989 adx2_out2_port: port@2 { 990 reg = <2>; 991 992 adx2_out2: endpoint { 993 remote-endpoint = <&xbar_adx2_out2>; 994 }; 995 }; 996 997 adx2_out3_port: port@3 { 998 reg = <3>; 999 1000 adx2_out3: endpoint { 1001 remote-endpoint = <&xbar_adx2_out3>; 1002 }; 1003 }; 1004 1005 adx2_out4_port: port@4 { 1006 reg = <4>; 1007 1008 adx2_out4: endpoint { 1009 remote-endpoint = <&xbar_adx2_out4>; 1010 }; 1011 }; 1012 }; 1013 }; 1014 1015 tegra_adx3: adx@95b0000 { 1016 compatible = "nvidia,tegra264-adx"; 1017 reg = <0x0 0x95b0000 0x0 0x10000>; 1018 sound-name-prefix = "ADX3"; 1019 1020 ports { 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 1024 port@0 { 1025 reg = <0>; 1026 1027 adx3_in: endpoint { 1028 remote-endpoint = <&xbar_adx3_in>; 1029 }; 1030 }; 1031 1032 adx3_out1_port: port@1 { 1033 reg = <1>; 1034 1035 adx3_out1: endpoint { 1036 remote-endpoint = <&xbar_adx3_out1>; 1037 }; 1038 }; 1039 1040 adx3_out2_port: port@2 { 1041 reg = <2>; 1042 1043 adx3_out2: endpoint { 1044 remote-endpoint = <&xbar_adx3_out2>; 1045 }; 1046 }; 1047 1048 adx3_out3_port: port@3 { 1049 reg = <3>; 1050 1051 adx3_out3: endpoint { 1052 remote-endpoint = <&xbar_adx3_out3>; 1053 }; 1054 }; 1055 1056 adx3_out4_port: port@4 { 1057 reg = <4>; 1058 1059 adx3_out4: endpoint { 1060 remote-endpoint = <&xbar_adx3_out4>; 1061 }; 1062 }; 1063 }; 1064 }; 1065 1066 tegra_adx4: adx@95c0000 { 1067 compatible = "nvidia,tegra264-adx"; 1068 reg = <0x0 0x95c0000 0x0 0x10000>; 1069 sound-name-prefix = "ADX4"; 1070 1071 ports { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 port@0 { 1076 reg = <0>; 1077 1078 adx4_in: endpoint { 1079 remote-endpoint = <&xbar_adx4_in>; 1080 }; 1081 }; 1082 1083 adx4_out1_port: port@1 { 1084 reg = <1>; 1085 1086 adx4_out1: endpoint { 1087 remote-endpoint = <&xbar_adx4_out1>; 1088 }; 1089 }; 1090 1091 adx4_out2_port: port@2 { 1092 reg = <2>; 1093 1094 adx4_out2: endpoint { 1095 remote-endpoint = <&xbar_adx4_out2>; 1096 }; 1097 }; 1098 1099 adx4_out3_port: port@3 { 1100 reg = <3>; 1101 1102 adx4_out3: endpoint { 1103 remote-endpoint = <&xbar_adx4_out3>; 1104 }; 1105 }; 1106 1107 adx4_out4_port: port@4 { 1108 reg = <4>; 1109 1110 adx4_out4: endpoint { 1111 remote-endpoint = <&xbar_adx4_out4>; 1112 }; 1113 }; 1114 }; 1115 }; 1116 1117 tegra_adx5: adx@95d0000 { 1118 compatible = "nvidia,tegra264-adx"; 1119 reg = <0x0 0x95d0000 0x0 0x10000>; 1120 sound-name-prefix = "ADX5"; 1121 1122 ports { 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 1126 port@0 { 1127 reg = <0>; 1128 1129 adx5_in: endpoint { 1130 remote-endpoint = <&xbar_adx5_in>; 1131 }; 1132 }; 1133 1134 adx5_out1_port: port@1 { 1135 reg = <1>; 1136 1137 adx5_out1: endpoint { 1138 remote-endpoint = <&xbar_adx5_out1>; 1139 }; 1140 }; 1141 1142 adx5_out2_port: port@2 { 1143 reg = <2>; 1144 1145 adx5_out2: endpoint { 1146 remote-endpoint = <&xbar_adx5_out2>; 1147 }; 1148 }; 1149 1150 adx5_out3_port: port@3 { 1151 reg = <3>; 1152 1153 adx5_out3: endpoint { 1154 remote-endpoint = <&xbar_adx5_out3>; 1155 }; 1156 }; 1157 1158 adx5_out4_port: port@4 { 1159 reg = <4>; 1160 1161 adx5_out4: endpoint { 1162 remote-endpoint = <&xbar_adx5_out4>; 1163 }; 1164 }; 1165 }; 1166 }; 1167 1168 tegra_adx6: adx@95e0000 { 1169 compatible = "nvidia,tegra264-adx"; 1170 reg = <0x0 0x95e0000 0x0 0x10000>; 1171 sound-name-prefix = "ADX6"; 1172 1173 ports { 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 1177 port@0 { 1178 reg = <0>; 1179 1180 adx6_in: endpoint { 1181 remote-endpoint = <&xbar_adx6_in>; 1182 }; 1183 }; 1184 1185 adx6_out1_port: port@1 { 1186 reg = <1>; 1187 1188 adx6_out1: endpoint { 1189 remote-endpoint = <&xbar_adx6_out1>; 1190 }; 1191 }; 1192 1193 adx6_out2_port: port@2 { 1194 reg = <2>; 1195 1196 adx6_out2: endpoint { 1197 remote-endpoint = <&xbar_adx6_out2>; 1198 }; 1199 }; 1200 1201 adx6_out3_port: port@3 { 1202 reg = <3>; 1203 1204 adx6_out3: endpoint { 1205 remote-endpoint = <&xbar_adx6_out3>; 1206 }; 1207 }; 1208 1209 adx6_out4_port: port@4 { 1210 reg = <4>; 1211 1212 adx6_out4: endpoint { 1213 remote-endpoint = <&xbar_adx6_out4>; 1214 }; 1215 }; 1216 }; 1217 }; 1218 1219 tegra_admaif: admaif@9610000 { 1220 compatible = "nvidia,tegra264-admaif"; 1221 reg = <0x0 0x9610000 0x0 0x10000>; 1222 dmas = <&adma 1>, <&adma 1>, 1223 <&adma 2>, <&adma 2>, 1224 <&adma 3>, <&adma 3>, 1225 <&adma 4>, <&adma 4>, 1226 <&adma 5>, <&adma 5>, 1227 <&adma 6>, <&adma 6>, 1228 <&adma 7>, <&adma 7>, 1229 <&adma 8>, <&adma 8>, 1230 <&adma 9>, <&adma 9>, 1231 <&adma 10>, <&adma 10>, 1232 <&adma 11>, <&adma 11>, 1233 <&adma 12>, <&adma 12>, 1234 <&adma 13>, <&adma 13>, 1235 <&adma 14>, <&adma 14>, 1236 <&adma 15>, <&adma 15>, 1237 <&adma 16>, <&adma 16>, 1238 <&adma 17>, <&adma 17>, 1239 <&adma 18>, <&adma 18>, 1240 <&adma 19>, <&adma 19>, 1241 <&adma 20>, <&adma 20>, 1242 <&adma 21>, <&adma 21>, 1243 <&adma 22>, <&adma 22>, 1244 <&adma 23>, <&adma 23>, 1245 <&adma 24>, <&adma 24>, 1246 <&adma 25>, <&adma 25>, 1247 <&adma 26>, <&adma 26>, 1248 <&adma 27>, <&adma 27>, 1249 <&adma 28>, <&adma 28>, 1250 <&adma 29>, <&adma 29>, 1251 <&adma 30>, <&adma 30>, 1252 <&adma 31>, <&adma 31>, 1253 <&adma 32>, <&adma 32>; 1254 dma-names = "rx1", "tx1", 1255 "rx2", "tx2", 1256 "rx3", "tx3", 1257 "rx4", "tx4", 1258 "rx5", "tx5", 1259 "rx6", "tx6", 1260 "rx7", "tx7", 1261 "rx8", "tx8", 1262 "rx9", "tx9", 1263 "rx10", "tx10", 1264 "rx11", "tx11", 1265 "rx12", "tx12", 1266 "rx13", "tx13", 1267 "rx14", "tx14", 1268 "rx15", "tx15", 1269 "rx16", "tx16", 1270 "rx17", "tx17", 1271 "rx18", "tx18", 1272 "rx19", "tx19", 1273 "rx20", "tx20", 1274 "rx21", "tx21", 1275 "rx22", "tx22", 1276 "rx23", "tx23", 1277 "rx24", "tx24", 1278 "rx25", "tx25", 1279 "rx26", "tx26", 1280 "rx27", "tx27", 1281 "rx28", "tx28", 1282 "rx29", "tx29", 1283 "rx30", "tx30", 1284 "rx31", "tx31", 1285 "rx32", "tx32"; 1286 1287 interconnects = 1288 <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, 1289 <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; 1290 interconnect-names = "dma-mem", "write"; 1291 1292 iommus = <&smmu1 TEGRA264_SID_APE>; 1293 1294 ports { 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 1298 admaif0_port: port@0 { 1299 reg = <0x0>; 1300 1301 admaif0: endpoint { 1302 remote-endpoint = <&xbar_admaif0>; 1303 }; 1304 }; 1305 1306 admaif1_port: port@1 { 1307 reg = <0x1>; 1308 1309 admaif1: endpoint { 1310 remote-endpoint = <&xbar_admaif1>; 1311 }; 1312 }; 1313 1314 admaif2_port: port@2 { 1315 reg = <0x2>; 1316 1317 admaif2: endpoint { 1318 remote-endpoint = <&xbar_admaif2>; 1319 }; 1320 }; 1321 1322 admaif3_port: port@3 { 1323 reg = <0x3>; 1324 1325 admaif3: endpoint { 1326 remote-endpoint = <&xbar_admaif3>; 1327 }; 1328 }; 1329 1330 admaif4_port: port@4 { 1331 reg = <0x4>; 1332 1333 admaif4: endpoint { 1334 remote-endpoint = <&xbar_admaif4>; 1335 }; 1336 }; 1337 1338 admaif5_port: port@5 { 1339 reg = <0x5>; 1340 1341 admaif5: endpoint { 1342 remote-endpoint = <&xbar_admaif5>; 1343 }; 1344 }; 1345 1346 admaif6_port: port@6 { 1347 reg = <0x6>; 1348 1349 admaif6: endpoint { 1350 remote-endpoint = <&xbar_admaif6>; 1351 }; 1352 }; 1353 1354 admaif7_port: port@7 { 1355 reg = <0x7>; 1356 1357 admaif7: endpoint { 1358 remote-endpoint = <&xbar_admaif7>; 1359 }; 1360 }; 1361 1362 admaif8_port: port@8 { 1363 reg = <0x8>; 1364 1365 admaif8: endpoint { 1366 remote-endpoint = <&xbar_admaif8>; 1367 }; 1368 }; 1369 1370 admaif9_port: port@9 { 1371 reg = <0x9>; 1372 1373 admaif9: endpoint { 1374 remote-endpoint = <&xbar_admaif9>; 1375 }; 1376 }; 1377 1378 admaif10_port: port@a { 1379 reg = <0xa>; 1380 1381 admaif10: endpoint { 1382 remote-endpoint = <&xbar_admaif10>; 1383 }; 1384 }; 1385 1386 admaif11_port: port@b { 1387 reg = <0xb>; 1388 1389 admaif11: endpoint { 1390 remote-endpoint = <&xbar_admaif11>; 1391 }; 1392 }; 1393 1394 admaif12_port: port@c { 1395 reg = <0xc>; 1396 1397 admaif12: endpoint { 1398 remote-endpoint = <&xbar_admaif12>; 1399 }; 1400 }; 1401 1402 admaif13_port: port@d { 1403 reg = <0xd>; 1404 1405 admaif13: endpoint { 1406 remote-endpoint = <&xbar_admaif13>; 1407 }; 1408 }; 1409 1410 admaif14_port: port@e { 1411 reg = <0xe>; 1412 1413 admaif14: endpoint { 1414 remote-endpoint = <&xbar_admaif14>; 1415 }; 1416 }; 1417 1418 admaif15_port: port@f { 1419 reg = <0xf>; 1420 1421 admaif15: endpoint { 1422 remote-endpoint = <&xbar_admaif15>; 1423 }; 1424 }; 1425 1426 admaif16_port: port@10 { 1427 reg = <0x10>; 1428 1429 admaif16: endpoint { 1430 remote-endpoint = <&xbar_admaif16>; 1431 }; 1432 }; 1433 1434 admaif17_port: port@11 { 1435 reg = <0x11>; 1436 1437 admaif17: endpoint { 1438 remote-endpoint = <&xbar_admaif17>; 1439 }; 1440 }; 1441 1442 admaif18_port: port@12 { 1443 reg = <0x12>; 1444 1445 admaif18: endpoint { 1446 remote-endpoint = <&xbar_admaif18>; 1447 }; 1448 }; 1449 1450 admaif19_port: port@13 { 1451 reg = <0x13>; 1452 1453 admaif19: endpoint { 1454 remote-endpoint = <&xbar_admaif19>; 1455 }; 1456 }; 1457 1458 admaif20_port: port@14 { 1459 reg = <0x14>; 1460 1461 admaif20: endpoint { 1462 remote-endpoint = <&xbar_admaif20>; 1463 }; 1464 }; 1465 1466 admaif21_port: port@15 { 1467 reg = <0x15>; 1468 1469 admaif21: endpoint { 1470 remote-endpoint = <&xbar_admaif21>; 1471 }; 1472 }; 1473 1474 admaif22_port: port@16 { 1475 reg = <0x16>; 1476 1477 admaif22: endpoint { 1478 remote-endpoint = <&xbar_admaif22>; 1479 }; 1480 }; 1481 1482 admaif23_port: port@17 { 1483 reg = <0x17>; 1484 1485 admaif23: endpoint { 1486 remote-endpoint = <&xbar_admaif23>; 1487 }; 1488 }; 1489 1490 admaif24_port: port@18 { 1491 reg = <0x18>; 1492 1493 admaif24: endpoint { 1494 remote-endpoint = <&xbar_admaif24>; 1495 }; 1496 }; 1497 1498 admaif25_port: port@19 { 1499 reg = <0x19>; 1500 1501 admaif25: endpoint { 1502 remote-endpoint = <&xbar_admaif25>; 1503 }; 1504 }; 1505 1506 admaif26_port: port@1a { 1507 reg = <0x1a>; 1508 1509 admaif26: endpoint { 1510 remote-endpoint = <&xbar_admaif26>; 1511 }; 1512 }; 1513 1514 admaif27_port: port@1b { 1515 reg = <0x1b>; 1516 1517 admaif27: endpoint { 1518 remote-endpoint = <&xbar_admaif27>; 1519 }; 1520 }; 1521 1522 admaif28_port: port@1c { 1523 reg = <0x1c>; 1524 1525 admaif28: endpoint { 1526 remote-endpoint = <&xbar_admaif28>; 1527 }; 1528 }; 1529 1530 admaif29_port: port@1d { 1531 reg = <0x1d>; 1532 1533 admaif29: endpoint { 1534 remote-endpoint = <&xbar_admaif29>; 1535 }; 1536 }; 1537 1538 admaif30_port: port@1e { 1539 reg = <0x1e>; 1540 1541 admaif30: endpoint { 1542 remote-endpoint = <&xbar_admaif30>; 1543 }; 1544 }; 1545 1546 admaif31_port: port@1f { 1547 reg = <0x1f>; 1548 1549 admaif31: endpoint { 1550 remote-endpoint = <&xbar_admaif31>; 1551 }; 1552 }; 1553 }; 1554 }; 1555 1556 tegra_sfc1: sfc@9700000 { 1557 compatible = "nvidia,tegra264-sfc", 1558 "nvidia,tegra210-sfc"; 1559 reg = <0x0 0x9700000 0x0 0x10000>; 1560 sound-name-prefix = "SFC1"; 1561 1562 ports { 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 1566 port@0 { 1567 reg = <0>; 1568 1569 sfc1_cif_in: endpoint { 1570 remote-endpoint = <&xbar_sfc1_in>; 1571 }; 1572 }; 1573 1574 sfc1_out_port: port@1 { 1575 reg = <1>; 1576 1577 sfc1_cif_out: endpoint { 1578 remote-endpoint = <&xbar_sfc1_out>; 1579 }; 1580 }; 1581 }; 1582 }; 1583 1584 tegra_sfc2: sfc@9710000 { 1585 compatible = "nvidia,tegra264-sfc", 1586 "nvidia,tegra210-sfc"; 1587 reg = <0x0 0x9710000 0x0 0x10000>; 1588 sound-name-prefix = "SFC2"; 1589 1590 ports { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 port@0 { 1595 reg = <0>; 1596 1597 sfc2_cif_in: endpoint { 1598 remote-endpoint = <&xbar_sfc2_in>; 1599 }; 1600 }; 1601 1602 sfc2_out_port: port@1 { 1603 reg = <1>; 1604 1605 sfc2_cif_out: endpoint { 1606 remote-endpoint = <&xbar_sfc2_out>; 1607 }; 1608 }; 1609 }; 1610 }; 1611 1612 tegra_sfc3: sfc@9720000 { 1613 compatible = "nvidia,tegra264-sfc", 1614 "nvidia,tegra210-sfc"; 1615 reg = <0x0 0x9720000 0x0 0x10000>; 1616 sound-name-prefix = "SFC3"; 1617 1618 ports { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 port@0 { 1623 reg = <0>; 1624 1625 sfc3_cif_in: endpoint { 1626 remote-endpoint = <&xbar_sfc3_in>; 1627 }; 1628 }; 1629 1630 sfc3_out_port: port@1 { 1631 reg = <1>; 1632 1633 sfc3_cif_out: endpoint { 1634 remote-endpoint = <&xbar_sfc3_out>; 1635 }; 1636 }; 1637 }; 1638 }; 1639 1640 tegra_sfc4: sfc@9730000 { 1641 compatible = "nvidia,tegra264-sfc", 1642 "nvidia,tegra210-sfc"; 1643 reg = <0x0 0x9730000 0x0 0x10000>; 1644 sound-name-prefix = "SFC4"; 1645 1646 ports { 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 port@0 { 1651 reg = <0>; 1652 1653 sfc4_cif_in: endpoint { 1654 remote-endpoint = <&xbar_sfc4_in>; 1655 }; 1656 }; 1657 1658 sfc4_out_port: port@1 { 1659 reg = <1>; 1660 1661 sfc4_cif_out: endpoint { 1662 remote-endpoint = <&xbar_sfc4_out>; 1663 }; 1664 }; 1665 }; 1666 }; 1667 1668 tegra_ope1: processing-engine@9780000 { 1669 compatible = "nvidia,tegra264-ope", 1670 "nvidia,tegra210-ope"; 1671 reg = <0x0 0x9780000 0x0 0x10000>; 1672 #address-cells = <2>; 1673 #size-cells = <2>; 1674 ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; 1675 sound-name-prefix = "OPE1"; 1676 1677 equalizer@9790000 { 1678 compatible = "nvidia,tegra264-peq", 1679 "nvidia,tegra210-peq"; 1680 reg = <0x0 0x9790000 0x0 0x10000>; 1681 }; 1682 1683 dynamic-range-compressor@97a0000 { 1684 compatible = "nvidia,tegra264-mbdrc", 1685 "nvidia,tegra210-mbdrc"; 1686 reg = <0x0 0x97a0000 0x0 0x10000>; 1687 }; 1688 1689 ports { 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 1693 port@0 { 1694 reg = <0x0>; 1695 1696 ope1_cif_in_ep: endpoint { 1697 remote-endpoint = 1698 <&xbar_ope1_in_ep>; 1699 }; 1700 }; 1701 1702 ope1_out_port: port@1 { 1703 reg = <0x1>; 1704 1705 ope1_cif_out_ep: endpoint { 1706 remote-endpoint = 1707 <&xbar_ope1_out_ep>; 1708 }; 1709 }; 1710 }; 1711 }; 1712 1713 tegra_mvc1: mvc@9800000 { 1714 compatible = "nvidia,tegra264-mvc", 1715 "nvidia,tegra210-mvc"; 1716 reg = <0x0 0x9800000 0x0 0x10000>; 1717 sound-name-prefix = "MVC1"; 1718 1719 ports { 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 1723 port@0 { 1724 reg = <0>; 1725 1726 mvc1_cif_in: endpoint { 1727 remote-endpoint = <&xbar_mvc1_in>; 1728 }; 1729 }; 1730 1731 mvc1_out_port: port@1 { 1732 reg = <1>; 1733 1734 mvc1_cif_out: endpoint { 1735 remote-endpoint = <&xbar_mvc1_out>; 1736 }; 1737 }; 1738 }; 1739 }; 1740 1741 tegra_mvc2: mvc@9810000 { 1742 compatible = "nvidia,tegra264-mvc", 1743 "nvidia,tegra210-mvc"; 1744 reg = <0x0 0x9810000 0x0 0x10000>; 1745 sound-name-prefix = "MVC2"; 1746 1747 ports { 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 1751 port@0 { 1752 reg = <0>; 1753 1754 mvc2_cif_in: endpoint { 1755 remote-endpoint = <&xbar_mvc2_in>; 1756 }; 1757 }; 1758 1759 mvc2_out_port: port@1 { 1760 reg = <1>; 1761 1762 mvc2_cif_out: endpoint { 1763 remote-endpoint = <&xbar_mvc2_out>; 1764 }; 1765 }; 1766 }; 1767 }; 1768 1769 tegra_amixer: amixer@9820000 { 1770 compatible = "nvidia,tegra264-amixer", 1771 "nvidia,tegra210-amixer"; 1772 reg = <0x0 0x9820000 0x0 0x10000>; 1773 sound-name-prefix = "MIXER1"; 1774 1775 ports { 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 1779 port@0 { 1780 reg = <0x0>; 1781 1782 mix_in1: endpoint { 1783 remote-endpoint = <&xbar_mix_in1>; 1784 }; 1785 }; 1786 1787 port@1 { 1788 reg = <0x1>; 1789 1790 mix_in2: endpoint { 1791 remote-endpoint = <&xbar_mix_in2>; 1792 }; 1793 }; 1794 1795 port@2 { 1796 reg = <0x2>; 1797 1798 mix_in3: endpoint { 1799 remote-endpoint = <&xbar_mix_in3>; 1800 }; 1801 }; 1802 1803 port@3 { 1804 reg = <0x3>; 1805 1806 mix_in4: endpoint { 1807 remote-endpoint = <&xbar_mix_in4>; 1808 }; 1809 }; 1810 1811 port@4 { 1812 reg = <0x4>; 1813 1814 mix_in5: endpoint { 1815 remote-endpoint = <&xbar_mix_in5>; 1816 }; 1817 }; 1818 1819 port@5 { 1820 reg = <0x5>; 1821 1822 mix_in6: endpoint { 1823 remote-endpoint = <&xbar_mix_in6>; 1824 }; 1825 }; 1826 1827 port@6 { 1828 reg = <0x6>; 1829 1830 mix_in7: endpoint { 1831 remote-endpoint = <&xbar_mix_in7>; 1832 }; 1833 }; 1834 1835 port@7 { 1836 reg = <0x7>; 1837 1838 mix_in8: endpoint { 1839 remote-endpoint = <&xbar_mix_in8>; 1840 }; 1841 }; 1842 1843 port@8 { 1844 reg = <0x8>; 1845 1846 mix_in9: endpoint { 1847 remote-endpoint = <&xbar_mix_in9>; 1848 }; 1849 }; 1850 1851 port@9 { 1852 reg = <0x9>; 1853 1854 mix_in10: endpoint { 1855 remote-endpoint = <&xbar_mix_in10>; 1856 }; 1857 }; 1858 1859 mix_out1_port: port@a { 1860 reg = <0xa>; 1861 1862 mix_out1: endpoint { 1863 remote-endpoint = <&xbar_mix_out1>; 1864 }; 1865 }; 1866 1867 mix_out2_port: port@b { 1868 reg = <0xb>; 1869 1870 mix_out2: endpoint { 1871 remote-endpoint = <&xbar_mix_out2>; 1872 }; 1873 }; 1874 1875 mix_out3_port: port@c { 1876 reg = <0xc>; 1877 1878 mix_out3: endpoint { 1879 remote-endpoint = <&xbar_mix_out3>; 1880 }; 1881 }; 1882 1883 mix_out4_port: port@d { 1884 reg = <0xd>; 1885 1886 mix_out4: endpoint { 1887 remote-endpoint = <&xbar_mix_out4>; 1888 }; 1889 }; 1890 1891 mix_out5_port: port@e { 1892 reg = <0xe>; 1893 1894 mix_out5: endpoint { 1895 remote-endpoint = <&xbar_mix_out5>; 1896 }; 1897 }; 1898 }; 1899 }; 1900 1901 tegra_asrc: asrc@9850000 { 1902 compatible = "nvidia,tegra264-asrc"; 1903 reg = <0x0 0x9850000 0x0 0x10000>; 1904 sound-name-prefix = "ASRC1"; 1905 1906 ports { 1907 #address-cells = <1>; 1908 #size-cells = <0>; 1909 1910 port@0 { 1911 reg = <0x0>; 1912 1913 asrc_in1_ep: endpoint { 1914 remote-endpoint = 1915 <&xbar_asrc_in1_ep>; 1916 }; 1917 }; 1918 1919 port@1 { 1920 reg = <0x1>; 1921 1922 asrc_in2_ep: endpoint { 1923 remote-endpoint = 1924 <&xbar_asrc_in2_ep>; 1925 }; 1926 }; 1927 1928 port@2 { 1929 reg = <0x2>; 1930 1931 asrc_in3_ep: endpoint { 1932 remote-endpoint = 1933 <&xbar_asrc_in3_ep>; 1934 }; 1935 }; 1936 1937 port@3 { 1938 reg = <0x3>; 1939 1940 asrc_in4_ep: endpoint { 1941 remote-endpoint = 1942 <&xbar_asrc_in4_ep>; 1943 }; 1944 }; 1945 1946 port@4 { 1947 reg = <0x4>; 1948 1949 asrc_in5_ep: endpoint { 1950 remote-endpoint = 1951 <&xbar_asrc_in5_ep>; 1952 }; 1953 }; 1954 1955 port@5 { 1956 reg = <0x5>; 1957 1958 asrc_in6_ep: endpoint { 1959 remote-endpoint = 1960 <&xbar_asrc_in6_ep>; 1961 }; 1962 }; 1963 1964 port@6 { 1965 reg = <0x6>; 1966 1967 asrc_in7_ep: endpoint { 1968 remote-endpoint = 1969 <&xbar_asrc_in7_ep>; 1970 }; 1971 }; 1972 1973 asrc_out1_port: port@7 { 1974 reg = <0x7>; 1975 1976 asrc_out1_ep: endpoint { 1977 remote-endpoint = 1978 <&xbar_asrc_out1_ep>; 1979 }; 1980 }; 1981 1982 asrc_out2_port: port@8 { 1983 reg = <0x8>; 1984 1985 asrc_out2_ep: endpoint { 1986 remote-endpoint = 1987 <&xbar_asrc_out2_ep>; 1988 }; 1989 }; 1990 1991 asrc_out3_port: port@9 { 1992 reg = <0x9>; 1993 1994 asrc_out3_ep: endpoint { 1995 remote-endpoint = 1996 <&xbar_asrc_out3_ep>; 1997 }; 1998 }; 1999 2000 asrc_out4_port: port@a { 2001 reg = <0xa>; 2002 2003 asrc_out4_ep: endpoint { 2004 remote-endpoint = 2005 <&xbar_asrc_out4_ep>; 2006 }; 2007 }; 2008 2009 asrc_out5_port: port@b { 2010 reg = <0xb>; 2011 2012 asrc_out5_ep: endpoint { 2013 remote-endpoint = 2014 <&xbar_asrc_out5_ep>; 2015 }; 2016 }; 2017 2018 asrc_out6_port: port@c { 2019 reg = <0xc>; 2020 2021 asrc_out6_ep: endpoint { 2022 remote-endpoint = 2023 <&xbar_asrc_out6_ep>; 2024 }; 2025 }; 2026 }; 2027 }; 2028 2029 ports { 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 2033 port@0 { 2034 reg = <0x0>; 2035 2036 xbar_admaif0: endpoint { 2037 remote-endpoint = <&admaif0>; 2038 }; 2039 }; 2040 2041 port@1 { 2042 reg = <0x1>; 2043 2044 xbar_admaif1: endpoint { 2045 remote-endpoint = <&admaif1>; 2046 }; 2047 }; 2048 2049 port@2 { 2050 reg = <0x2>; 2051 2052 xbar_admaif2: endpoint { 2053 remote-endpoint = <&admaif2>; 2054 }; 2055 }; 2056 2057 port@3 { 2058 reg = <0x3>; 2059 2060 xbar_admaif3: endpoint { 2061 remote-endpoint = <&admaif3>; 2062 }; 2063 }; 2064 2065 port@4 { 2066 reg = <0x4>; 2067 2068 xbar_admaif4: endpoint { 2069 remote-endpoint = <&admaif4>; 2070 }; 2071 }; 2072 2073 port@5 { 2074 reg = <0x5>; 2075 2076 xbar_admaif5: endpoint { 2077 remote-endpoint = <&admaif5>; 2078 }; 2079 }; 2080 2081 port@6 { 2082 reg = <0x6>; 2083 2084 xbar_admaif6: endpoint { 2085 remote-endpoint = <&admaif6>; 2086 }; 2087 }; 2088 2089 port@7 { 2090 reg = <0x7>; 2091 2092 xbar_admaif7: endpoint { 2093 remote-endpoint = <&admaif7>; 2094 }; 2095 }; 2096 2097 port@8 { 2098 reg = <0x8>; 2099 2100 xbar_admaif8: endpoint { 2101 remote-endpoint = <&admaif8>; 2102 }; 2103 }; 2104 2105 port@9 { 2106 reg = <0x9>; 2107 2108 xbar_admaif9: endpoint { 2109 remote-endpoint = <&admaif9>; 2110 }; 2111 }; 2112 2113 port@a { 2114 reg = <0xa>; 2115 2116 xbar_admaif10: endpoint { 2117 remote-endpoint = <&admaif10>; 2118 }; 2119 }; 2120 2121 port@b { 2122 reg = <0xb>; 2123 2124 xbar_admaif11: endpoint { 2125 remote-endpoint = <&admaif11>; 2126 }; 2127 }; 2128 2129 port@c { 2130 reg = <0xc>; 2131 2132 xbar_admaif12: endpoint { 2133 remote-endpoint = <&admaif12>; 2134 }; 2135 }; 2136 2137 port@d { 2138 reg = <0xd>; 2139 2140 xbar_admaif13: endpoint { 2141 remote-endpoint = <&admaif13>; 2142 }; 2143 }; 2144 2145 port@e { 2146 reg = <0xe>; 2147 2148 xbar_admaif14: endpoint { 2149 remote-endpoint = <&admaif14>; 2150 }; 2151 }; 2152 2153 port@f { 2154 reg = <0xf>; 2155 2156 xbar_admaif15: endpoint { 2157 remote-endpoint = <&admaif15>; 2158 }; 2159 }; 2160 2161 port@10 { 2162 reg = <0x10>; 2163 2164 xbar_admaif16: endpoint { 2165 remote-endpoint = <&admaif16>; 2166 }; 2167 }; 2168 2169 port@11 { 2170 reg = <0x11>; 2171 2172 xbar_admaif17: endpoint { 2173 remote-endpoint = <&admaif17>; 2174 }; 2175 }; 2176 2177 port@12 { 2178 reg = <0x12>; 2179 2180 xbar_admaif18: endpoint { 2181 remote-endpoint = <&admaif18>; 2182 }; 2183 }; 2184 2185 port@13 { 2186 reg = <0x13>; 2187 2188 xbar_admaif19: endpoint { 2189 remote-endpoint = <&admaif19>; 2190 }; 2191 }; 2192 2193 port@14 { 2194 reg = <0x14>; 2195 2196 xbar_admaif20: endpoint { 2197 remote-endpoint = <&admaif20>; 2198 }; 2199 }; 2200 2201 port@15 { 2202 reg = <0x15>; 2203 2204 xbar_admaif21: endpoint { 2205 remote-endpoint = <&admaif21>; 2206 }; 2207 }; 2208 2209 port@16 { 2210 reg = <0x16>; 2211 2212 xbar_admaif22: endpoint { 2213 remote-endpoint = <&admaif22>; 2214 }; 2215 }; 2216 2217 port@17 { 2218 reg = <0x17>; 2219 2220 xbar_admaif23: endpoint { 2221 remote-endpoint = <&admaif23>; 2222 }; 2223 }; 2224 2225 port@18 { 2226 reg = <0x18>; 2227 2228 xbar_admaif24: endpoint { 2229 remote-endpoint = <&admaif24>; 2230 }; 2231 }; 2232 2233 port@19 { 2234 reg = <0x19>; 2235 2236 xbar_admaif25: endpoint { 2237 remote-endpoint = <&admaif25>; 2238 }; 2239 }; 2240 2241 port@1a { 2242 reg = <0x1a>; 2243 2244 xbar_admaif26: endpoint { 2245 remote-endpoint = <&admaif26>; 2246 }; 2247 }; 2248 2249 port@1b { 2250 reg = <0x1b>; 2251 2252 xbar_admaif27: endpoint { 2253 remote-endpoint = <&admaif27>; 2254 }; 2255 }; 2256 2257 port@1c { 2258 reg = <0x1c>; 2259 2260 xbar_admaif28: endpoint { 2261 remote-endpoint = <&admaif28>; 2262 }; 2263 }; 2264 2265 port@1d { 2266 reg = <0x1d>; 2267 2268 xbar_admaif29: endpoint { 2269 remote-endpoint = <&admaif29>; 2270 }; 2271 }; 2272 2273 port@1e { 2274 reg = <0x1e>; 2275 2276 xbar_admaif30: endpoint { 2277 remote-endpoint = <&admaif30>; 2278 }; 2279 }; 2280 2281 port@1f { 2282 reg = <0x1f>; 2283 2284 xbar_admaif31: endpoint { 2285 remote-endpoint = <&admaif31>; 2286 }; 2287 }; 2288 2289 xbar_i2s1_port: port@20 { 2290 reg = <0x20>; 2291 2292 xbar_i2s1: endpoint { 2293 remote-endpoint = <&i2s1_cif>; 2294 }; 2295 }; 2296 2297 xbar_i2s2_port: port@21 { 2298 reg = <0x21>; 2299 2300 xbar_i2s2: endpoint { 2301 remote-endpoint = <&i2s2_cif>; 2302 }; 2303 }; 2304 2305 xbar_i2s3_port: port@22 { 2306 reg = <0x22>; 2307 2308 xbar_i2s3: endpoint { 2309 remote-endpoint = <&i2s3_cif>; 2310 }; 2311 }; 2312 2313 xbar_i2s4_port: port@23 { 2314 reg = <0x23>; 2315 2316 xbar_i2s4: endpoint { 2317 remote-endpoint = <&i2s4_cif>; 2318 }; 2319 }; 2320 2321 xbar_i2s5_port: port@24 { 2322 reg = <0x24>; 2323 2324 xbar_i2s5: endpoint { 2325 remote-endpoint = <&i2s5_cif>; 2326 }; 2327 }; 2328 2329 xbar_i2s6_port: port@25 { 2330 reg = <0x25>; 2331 2332 xbar_i2s6: endpoint { 2333 remote-endpoint = <&i2s6_cif>; 2334 }; 2335 }; 2336 2337 xbar_i2s7_port: port@26 { 2338 reg = <0x26>; 2339 2340 xbar_i2s7: endpoint { 2341 remote-endpoint = <&i2s7_cif>; 2342 }; 2343 }; 2344 2345 xbar_i2s8_port: port@27 { 2346 reg = <0x27>; 2347 2348 xbar_i2s8: endpoint { 2349 remote-endpoint = <&i2s8_cif>; 2350 }; 2351 }; 2352 2353 xbar_dmic1_port: port@28 { 2354 reg = <0x28>; 2355 2356 xbar_dmic1: endpoint { 2357 remote-endpoint = <&dmic1_cif>; 2358 }; 2359 }; 2360 2361 xbar_dmic2_port: port@29 { 2362 reg = <0x29>; 2363 2364 xbar_dmic2: endpoint { 2365 remote-endpoint = <&dmic2_cif>; 2366 }; 2367 }; 2368 2369 xbar_dspk1_port: port@2a { 2370 reg = <0x2a>; 2371 2372 xbar_dspk1: endpoint { 2373 remote-endpoint = <&dspk1_cif>; 2374 }; 2375 }; 2376 2377 xbar_sfc1_in_port: port@2b { 2378 reg = <0x2b>; 2379 2380 xbar_sfc1_in: endpoint { 2381 remote-endpoint = <&sfc1_cif_in>; 2382 }; 2383 }; 2384 2385 port@2c { 2386 reg = <0x2c>; 2387 2388 xbar_sfc1_out: endpoint { 2389 remote-endpoint = <&sfc1_cif_out>; 2390 }; 2391 }; 2392 2393 xbar_sfc2_in_port: port@2d { 2394 reg = <0x2d>; 2395 2396 xbar_sfc2_in: endpoint { 2397 remote-endpoint = <&sfc2_cif_in>; 2398 }; 2399 }; 2400 2401 port@2e { 2402 reg = <0x2e>; 2403 2404 xbar_sfc2_out: endpoint { 2405 remote-endpoint = <&sfc2_cif_out>; 2406 }; 2407 }; 2408 2409 xbar_sfc3_in_port: port@2f { 2410 reg = <0x2f>; 2411 2412 xbar_sfc3_in: endpoint { 2413 remote-endpoint = <&sfc3_cif_in>; 2414 }; 2415 }; 2416 2417 port@30 { 2418 reg = <0x30>; 2419 2420 xbar_sfc3_out: endpoint { 2421 remote-endpoint = <&sfc3_cif_out>; 2422 }; 2423 }; 2424 2425 xbar_sfc4_in_port: port@31 { 2426 reg = <0x31>; 2427 2428 xbar_sfc4_in: endpoint { 2429 remote-endpoint = <&sfc4_cif_in>; 2430 }; 2431 }; 2432 2433 port@32 { 2434 reg = <0x32>; 2435 2436 xbar_sfc4_out: endpoint { 2437 remote-endpoint = <&sfc4_cif_out>; 2438 }; 2439 }; 2440 2441 xbar_mvc1_in_port: port@33 { 2442 reg = <0x33>; 2443 2444 xbar_mvc1_in: endpoint { 2445 remote-endpoint = <&mvc1_cif_in>; 2446 }; 2447 }; 2448 2449 port@34 { 2450 reg = <0x34>; 2451 2452 xbar_mvc1_out: endpoint { 2453 remote-endpoint = <&mvc1_cif_out>; 2454 }; 2455 }; 2456 2457 xbar_mvc2_in_port: port@35 { 2458 reg = <0x35>; 2459 2460 xbar_mvc2_in: endpoint { 2461 remote-endpoint = <&mvc2_cif_in>; 2462 }; 2463 }; 2464 2465 port@36 { 2466 reg = <0x36>; 2467 2468 xbar_mvc2_out: endpoint { 2469 remote-endpoint = <&mvc2_cif_out>; 2470 }; 2471 }; 2472 2473 xbar_amx1_in1_port: port@37 { 2474 reg = <0x37>; 2475 2476 xbar_amx1_in1: endpoint { 2477 remote-endpoint = <&amx1_in1>; 2478 }; 2479 }; 2480 2481 xbar_amx1_in2_port: port@38 { 2482 reg = <0x38>; 2483 2484 xbar_amx1_in2: endpoint { 2485 remote-endpoint = <&amx1_in2>; 2486 }; 2487 }; 2488 2489 xbar_amx1_in3_port: port@39 { 2490 reg = <0x39>; 2491 2492 xbar_amx1_in3: endpoint { 2493 remote-endpoint = <&amx1_in3>; 2494 }; 2495 }; 2496 2497 xbar_amx1_in4_port: port@3a { 2498 reg = <0x3a>; 2499 2500 xbar_amx1_in4: endpoint { 2501 remote-endpoint = <&amx1_in4>; 2502 }; 2503 }; 2504 2505 port@3b { 2506 reg = <0x3b>; 2507 2508 xbar_amx1_out: endpoint { 2509 remote-endpoint = <&amx1_out>; 2510 }; 2511 }; 2512 2513 xbar_amx2_in1_port: port@3c { 2514 reg = <0x3c>; 2515 2516 xbar_amx2_in1: endpoint { 2517 remote-endpoint = <&amx2_in1>; 2518 }; 2519 }; 2520 2521 xbar_amx2_in2_port: port@3d { 2522 reg = <0x3d>; 2523 2524 xbar_amx2_in2: endpoint { 2525 remote-endpoint = <&amx2_in2>; 2526 }; 2527 }; 2528 2529 xbar_amx2_in3_port: port@3e { 2530 reg = <0x3e>; 2531 2532 xbar_amx2_in3: endpoint { 2533 remote-endpoint = <&amx2_in3>; 2534 }; 2535 }; 2536 2537 xbar_amx2_in4_port: port@3f { 2538 reg = <0x3f>; 2539 2540 xbar_amx2_in4: endpoint { 2541 remote-endpoint = <&amx2_in4>; 2542 }; 2543 }; 2544 2545 port@40 { 2546 reg = <0x40>; 2547 2548 xbar_amx2_out: endpoint { 2549 remote-endpoint = <&amx2_out>; 2550 }; 2551 }; 2552 2553 xbar_amx3_in1_port: port@41 { 2554 reg = <0x41>; 2555 2556 xbar_amx3_in1: endpoint { 2557 remote-endpoint = <&amx3_in1>; 2558 }; 2559 }; 2560 2561 xbar_amx3_in2_port: port@42 { 2562 reg = <0x42>; 2563 2564 xbar_amx3_in2: endpoint { 2565 remote-endpoint = <&amx3_in2>; 2566 }; 2567 }; 2568 2569 xbar_amx3_in3_port: port@43 { 2570 reg = <0x43>; 2571 2572 xbar_amx3_in3: endpoint { 2573 remote-endpoint = <&amx3_in3>; 2574 }; 2575 }; 2576 2577 xbar_amx3_in4_port: port@44 { 2578 reg = <0x44>; 2579 2580 xbar_amx3_in4: endpoint { 2581 remote-endpoint = <&amx3_in4>; 2582 }; 2583 }; 2584 2585 port@45 { 2586 reg = <0x45>; 2587 2588 xbar_amx3_out: endpoint { 2589 remote-endpoint = <&amx3_out>; 2590 }; 2591 }; 2592 2593 xbar_amx4_in1_port: port@46 { 2594 reg = <0x46>; 2595 2596 xbar_amx4_in1: endpoint { 2597 remote-endpoint = <&amx4_in1>; 2598 }; 2599 }; 2600 2601 xbar_amx4_in2_port: port@47 { 2602 reg = <0x47>; 2603 2604 xbar_amx4_in2: endpoint { 2605 remote-endpoint = <&amx4_in2>; 2606 }; 2607 }; 2608 2609 xbar_amx4_in3_port: port@48 { 2610 reg = <0x48>; 2611 2612 xbar_amx4_in3: endpoint { 2613 remote-endpoint = <&amx4_in3>; 2614 }; 2615 }; 2616 2617 xbar_amx4_in4_port: port@49 { 2618 reg = <0x49>; 2619 2620 xbar_amx4_in4: endpoint { 2621 remote-endpoint = <&amx4_in4>; 2622 }; 2623 }; 2624 2625 port@4a { 2626 reg = <0x4a>; 2627 2628 xbar_amx4_out: endpoint { 2629 remote-endpoint = <&amx4_out>; 2630 }; 2631 }; 2632 2633 xbar_amx5_in1_port: port@4b { 2634 reg = <0x4b>; 2635 2636 xbar_amx5_in1: endpoint { 2637 remote-endpoint = <&amx5_in1>; 2638 }; 2639 }; 2640 2641 xbar_amx5_in2_port: port@4c { 2642 reg = <0x4c>; 2643 2644 xbar_amx5_in2: endpoint { 2645 remote-endpoint = <&amx5_in2>; 2646 }; 2647 }; 2648 2649 xbar_amx5_in3_port: port@4d { 2650 reg = <0x4d>; 2651 2652 xbar_amx5_in3: endpoint { 2653 remote-endpoint = <&amx5_in3>; 2654 }; 2655 }; 2656 2657 xbar_amx5_in4_port: port@4e { 2658 reg = <0x4e>; 2659 2660 xbar_amx5_in4: endpoint { 2661 remote-endpoint = <&amx5_in4>; 2662 }; 2663 }; 2664 2665 port@4f { 2666 reg = <0x4f>; 2667 2668 xbar_amx5_out: endpoint { 2669 remote-endpoint = <&amx5_out>; 2670 }; 2671 }; 2672 2673 xbar_amx6_in1_port: port@50 { 2674 reg = <0x50>; 2675 2676 xbar_amx6_in1: endpoint { 2677 remote-endpoint = <&amx6_in1>; 2678 }; 2679 }; 2680 2681 xbar_amx6_in2_port: port@51 { 2682 reg = <0x51>; 2683 2684 xbar_amx6_in2: endpoint { 2685 remote-endpoint = <&amx6_in2>; 2686 }; 2687 }; 2688 2689 xbar_amx6_in3_port: port@52 { 2690 reg = <0x52>; 2691 2692 xbar_amx6_in3: endpoint { 2693 remote-endpoint = <&amx6_in3>; 2694 }; 2695 }; 2696 2697 xbar_amx6_in4_port: port@53 { 2698 reg = <0x53>; 2699 2700 xbar_amx6_in4: endpoint { 2701 remote-endpoint = <&amx6_in4>; 2702 }; 2703 }; 2704 2705 port@54 { 2706 reg = <0x54>; 2707 2708 xbar_amx6_out: endpoint { 2709 remote-endpoint = <&amx6_out>; 2710 }; 2711 }; 2712 2713 xbar_adx1_in_port: port@55 { 2714 reg = <0x55>; 2715 2716 xbar_adx1_in: endpoint { 2717 remote-endpoint = <&adx1_in>; 2718 }; 2719 }; 2720 2721 port@56 { 2722 reg = <0x56>; 2723 2724 xbar_adx1_out1: endpoint { 2725 remote-endpoint = <&adx1_out1>; 2726 }; 2727 }; 2728 2729 port@57 { 2730 reg = <0x57>; 2731 2732 xbar_adx1_out2: endpoint { 2733 remote-endpoint = <&adx1_out2>; 2734 }; 2735 }; 2736 2737 port@58 { 2738 reg = <0x58>; 2739 2740 xbar_adx1_out3: endpoint { 2741 remote-endpoint = <&adx1_out3>; 2742 }; 2743 }; 2744 2745 port@59 { 2746 reg = <0x59>; 2747 2748 xbar_adx1_out4: endpoint { 2749 remote-endpoint = <&adx1_out4>; 2750 }; 2751 }; 2752 2753 xbar_adx2_in_port: port@5a { 2754 reg = <0x5a>; 2755 2756 xbar_adx2_in: endpoint { 2757 remote-endpoint = <&adx2_in>; 2758 }; 2759 }; 2760 2761 port@5b { 2762 reg = <0x5b>; 2763 2764 xbar_adx2_out1: endpoint { 2765 remote-endpoint = <&adx2_out1>; 2766 }; 2767 }; 2768 2769 port@5c { 2770 reg = <0x5c>; 2771 2772 xbar_adx2_out2: endpoint { 2773 remote-endpoint = <&adx2_out2>; 2774 }; 2775 }; 2776 2777 port@5d { 2778 reg = <0x5d>; 2779 2780 xbar_adx2_out3: endpoint { 2781 remote-endpoint = <&adx2_out3>; 2782 }; 2783 }; 2784 2785 port@5e { 2786 reg = <0x5e>; 2787 2788 xbar_adx2_out4: endpoint { 2789 remote-endpoint = <&adx2_out4>; 2790 }; 2791 }; 2792 2793 xbar_adx3_in_port: port@5f { 2794 reg = <0x5f>; 2795 2796 xbar_adx3_in: endpoint { 2797 remote-endpoint = <&adx3_in>; 2798 }; 2799 }; 2800 2801 port@60 { 2802 reg = <0x60>; 2803 2804 xbar_adx3_out1: endpoint { 2805 remote-endpoint = <&adx3_out1>; 2806 }; 2807 }; 2808 2809 port@61 { 2810 reg = <0x61>; 2811 2812 xbar_adx3_out2: endpoint { 2813 remote-endpoint = <&adx3_out2>; 2814 }; 2815 }; 2816 2817 port@62 { 2818 reg = <0x62>; 2819 2820 xbar_adx3_out3: endpoint { 2821 remote-endpoint = <&adx3_out3>; 2822 }; 2823 }; 2824 2825 port@63 { 2826 reg = <0x63>; 2827 2828 xbar_adx3_out4: endpoint { 2829 remote-endpoint = <&adx3_out4>; 2830 }; 2831 }; 2832 2833 xbar_adx4_in_port: port@64 { 2834 reg = <0x64>; 2835 2836 xbar_adx4_in: endpoint { 2837 remote-endpoint = <&adx4_in>; 2838 }; 2839 }; 2840 2841 port@65 { 2842 reg = <0x65>; 2843 2844 xbar_adx4_out1: endpoint { 2845 remote-endpoint = <&adx4_out1>; 2846 }; 2847 }; 2848 2849 port@66 { 2850 reg = <0x66>; 2851 2852 xbar_adx4_out2: endpoint { 2853 remote-endpoint = <&adx4_out2>; 2854 }; 2855 }; 2856 2857 port@67 { 2858 reg = <0x67>; 2859 2860 xbar_adx4_out3: endpoint { 2861 remote-endpoint = <&adx4_out3>; 2862 }; 2863 }; 2864 2865 port@68 { 2866 reg = <0x68>; 2867 2868 xbar_adx4_out4: endpoint { 2869 remote-endpoint = <&adx4_out4>; 2870 }; 2871 }; 2872 2873 xbar_adx5_in_port: port@69 { 2874 reg = <0x69>; 2875 2876 xbar_adx5_in: endpoint { 2877 remote-endpoint = <&adx5_in>; 2878 }; 2879 }; 2880 2881 port@6a { 2882 reg = <0x6a>; 2883 2884 xbar_adx5_out1: endpoint { 2885 remote-endpoint = <&adx5_out1>; 2886 }; 2887 }; 2888 2889 port@6b { 2890 reg = <0x6b>; 2891 2892 xbar_adx5_out2: endpoint { 2893 remote-endpoint = <&adx5_out2>; 2894 }; 2895 }; 2896 2897 port@6c { 2898 reg = <0x6c>; 2899 2900 xbar_adx5_out3: endpoint { 2901 remote-endpoint = <&adx5_out3>; 2902 }; 2903 }; 2904 2905 port@6d { 2906 reg = <0x6d>; 2907 2908 xbar_adx5_out4: endpoint { 2909 remote-endpoint = <&adx5_out4>; 2910 }; 2911 }; 2912 2913 xbar_adx6_in_port: port@6e { 2914 reg = <0x6e>; 2915 2916 xbar_adx6_in: endpoint { 2917 remote-endpoint = <&adx6_in>; 2918 }; 2919 }; 2920 2921 port@6f { 2922 reg = <0x6f>; 2923 2924 xbar_adx6_out1: endpoint { 2925 remote-endpoint = <&adx6_out1>; 2926 }; 2927 }; 2928 2929 port@70 { 2930 reg = <0x70>; 2931 2932 xbar_adx6_out2: endpoint { 2933 remote-endpoint = <&adx6_out2>; 2934 }; 2935 }; 2936 2937 port@71 { 2938 reg = <0x71>; 2939 2940 xbar_adx6_out3: endpoint { 2941 remote-endpoint = <&adx6_out3>; 2942 }; 2943 }; 2944 2945 port@72 { 2946 reg = <0x72>; 2947 2948 xbar_adx6_out4: endpoint { 2949 remote-endpoint = <&adx6_out4>; 2950 }; 2951 }; 2952 2953 xbar_mix_in1_port: port@73 { 2954 reg = <0x73>; 2955 2956 xbar_mix_in1: endpoint { 2957 remote-endpoint = <&mix_in1>; 2958 }; 2959 }; 2960 2961 xbar_mix_in2_port: port@74 { 2962 reg = <0x74>; 2963 2964 xbar_mix_in2: endpoint { 2965 remote-endpoint = <&mix_in2>; 2966 }; 2967 }; 2968 2969 xbar_mix_in3_port: port@75 { 2970 reg = <0x75>; 2971 2972 xbar_mix_in3: endpoint { 2973 remote-endpoint = <&mix_in3>; 2974 }; 2975 }; 2976 2977 xbar_mix_in4_port: port@76 { 2978 reg = <0x76>; 2979 2980 xbar_mix_in4: endpoint { 2981 remote-endpoint = <&mix_in4>; 2982 }; 2983 }; 2984 2985 xbar_mix_in5_port: port@77 { 2986 reg = <0x77>; 2987 2988 xbar_mix_in5: endpoint { 2989 remote-endpoint = <&mix_in5>; 2990 }; 2991 }; 2992 2993 xbar_mix_in6_port: port@78 { 2994 reg = <0x78>; 2995 2996 xbar_mix_in6: endpoint { 2997 remote-endpoint = <&mix_in6>; 2998 }; 2999 }; 3000 3001 xbar_mix_in7_port: port@79 { 3002 reg = <0x79>; 3003 3004 xbar_mix_in7: endpoint { 3005 remote-endpoint = <&mix_in7>; 3006 }; 3007 }; 3008 3009 xbar_mix_in8_port: port@7a { 3010 reg = <0x7a>; 3011 3012 xbar_mix_in8: endpoint { 3013 remote-endpoint = <&mix_in8>; 3014 }; 3015 }; 3016 3017 xbar_mix_in9_port: port@7b { 3018 reg = <0x7b>; 3019 3020 xbar_mix_in9: endpoint { 3021 remote-endpoint = <&mix_in9>; 3022 }; 3023 }; 3024 3025 xbar_mix_in10_port: port@7c { 3026 reg = <0x7c>; 3027 3028 xbar_mix_in10: endpoint { 3029 remote-endpoint = <&mix_in10>; 3030 }; 3031 }; 3032 3033 port@7d { 3034 reg = <0x7d>; 3035 3036 xbar_mix_out1: endpoint { 3037 remote-endpoint = <&mix_out1>; 3038 }; 3039 }; 3040 3041 port@7e { 3042 reg = <0x7e>; 3043 3044 xbar_mix_out2: endpoint { 3045 remote-endpoint = <&mix_out2>; 3046 }; 3047 }; 3048 3049 port@7f { 3050 reg = <0x7f>; 3051 3052 xbar_mix_out3: endpoint { 3053 remote-endpoint = <&mix_out3>; 3054 }; 3055 }; 3056 3057 port@80 { 3058 reg = <0x80>; 3059 3060 xbar_mix_out4: endpoint { 3061 remote-endpoint = <&mix_out4>; 3062 }; 3063 }; 3064 3065 port@81 { 3066 reg = <0x81>; 3067 3068 xbar_mix_out5: endpoint { 3069 remote-endpoint = <&mix_out5>; 3070 }; 3071 }; 3072 3073 xbar_asrc_in1_port: port@82 { 3074 reg = <0x82>; 3075 3076 xbar_asrc_in1_ep: endpoint { 3077 remote-endpoint = <&asrc_in1_ep>; 3078 }; 3079 }; 3080 3081 port@83 { 3082 reg = <0x83>; 3083 3084 xbar_asrc_out1_ep: endpoint { 3085 remote-endpoint = <&asrc_out1_ep>; 3086 }; 3087 }; 3088 3089 xbar_asrc_in2_port: port@84 { 3090 reg = <0x84>; 3091 3092 xbar_asrc_in2_ep: endpoint { 3093 remote-endpoint = <&asrc_in2_ep>; 3094 }; 3095 }; 3096 3097 port@85 { 3098 reg = <0x85>; 3099 3100 xbar_asrc_out2_ep: endpoint { 3101 remote-endpoint = <&asrc_out2_ep>; 3102 }; 3103 }; 3104 3105 xbar_asrc_in3_port: port@86 { 3106 reg = <0x86>; 3107 3108 xbar_asrc_in3_ep: endpoint { 3109 remote-endpoint = <&asrc_in3_ep>; 3110 }; 3111 }; 3112 3113 port@87 { 3114 reg = <0x87>; 3115 3116 xbar_asrc_out3_ep: endpoint { 3117 remote-endpoint = <&asrc_out3_ep>; 3118 }; 3119 }; 3120 3121 xbar_asrc_in4_port: port@88 { 3122 reg = <0x88>; 3123 3124 xbar_asrc_in4_ep: endpoint { 3125 remote-endpoint = <&asrc_in4_ep>; 3126 }; 3127 }; 3128 3129 port@89 { 3130 reg = <0x89>; 3131 3132 xbar_asrc_out4_ep: endpoint { 3133 remote-endpoint = <&asrc_out4_ep>; 3134 }; 3135 }; 3136 3137 xbar_asrc_in5_port: port@8a { 3138 reg = <0x8a>; 3139 3140 xbar_asrc_in5_ep: endpoint { 3141 remote-endpoint = <&asrc_in5_ep>; 3142 }; 3143 }; 3144 3145 port@8b { 3146 reg = <0x8b>; 3147 3148 xbar_asrc_out5_ep: endpoint { 3149 remote-endpoint = <&asrc_out5_ep>; 3150 }; 3151 }; 3152 3153 xbar_asrc_in6_port: port@8c { 3154 reg = <0x8c>; 3155 3156 xbar_asrc_in6_ep: endpoint { 3157 remote-endpoint = <&asrc_in6_ep>; 3158 }; 3159 }; 3160 3161 port@8d { 3162 reg = <0x8d>; 3163 3164 xbar_asrc_out6_ep: endpoint { 3165 remote-endpoint = <&asrc_out6_ep>; 3166 }; 3167 }; 3168 3169 xbar_asrc_in7_port: port@8e { 3170 reg = <0x8e>; 3171 3172 xbar_asrc_in7_ep: endpoint { 3173 remote-endpoint = <&asrc_in7_ep>; 3174 }; 3175 }; 3176 3177 xbar_ope1_in_port: port@8f { 3178 reg = <0x8f>; 3179 3180 xbar_ope1_in_ep: endpoint { 3181 remote-endpoint = <&ope1_cif_in_ep>; 3182 }; 3183 }; 3184 3185 port@90 { 3186 reg = <0x90>; 3187 3188 xbar_ope1_out_ep: endpoint { 3189 remote-endpoint = <&ope1_cif_out_ep>; 3190 }; 3191 }; 3192 }; 3193 }; 3194 3195 agic_page0: interrupt-controller@9960000 { 3196 compatible = "nvidia,tegra264-agic", 3197 "nvidia,tegra210-agic"; 3198 #interrupt-cells = <3>; 3199 interrupt-controller; 3200 reg = <0x0 0x9961000 0x0 0x1000>, 3201 <0x0 0x9962000 0x0 0x1000>; 3202 interrupts = <GIC_SPI 0x230 3203 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3204 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3205 clock-names = "clk"; 3206 status = "disabled"; 3207 }; 3208 3209 agic_page1: interrupt-controller@9970000 { 3210 compatible = "nvidia,tegra264-agic", 3211 "nvidia,tegra210-agic"; 3212 #interrupt-cells = <3>; 3213 interrupt-controller; 3214 reg = <0x0 0x9971000 0x0 0x1000>, 3215 <0x0 0x9972000 0x0 0x1000>; 3216 interrupts = <GIC_SPI 0x231 3217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3218 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3219 clock-names = "clk"; 3220 status = "disabled"; 3221 }; 3222 3223 agic_page2: interrupt-controller@9980000 { 3224 compatible = "nvidia,tegra264-agic", 3225 "nvidia,tegra210-agic"; 3226 #interrupt-cells = <3>; 3227 interrupt-controller; 3228 reg = <0x0 0x9981000 0x0 0x1000>, 3229 <0x0 0x9982000 0x0 0x1000>; 3230 interrupts = <GIC_SPI 0x232 3231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3232 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3233 clock-names = "clk"; 3234 status = "disabled"; 3235 }; 3236 3237 agic_page3: interrupt-controller@9990000 { 3238 compatible = "nvidia,tegra264-agic", 3239 "nvidia,tegra210-agic"; 3240 #interrupt-cells = <3>; 3241 interrupt-controller; 3242 reg = <0x0 0x9991000 0x0 0x1000>, 3243 <0x0 0x9992000 0x0 0x1000>; 3244 interrupts = <GIC_SPI 0x233 3245 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3246 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3247 clock-names = "clk"; 3248 status = "disabled"; 3249 }; 3250 3251 agic_page4: interrupt-controller@99a0000 { 3252 compatible = "nvidia,tegra264-agic", 3253 "nvidia,tegra210-agic"; 3254 #interrupt-cells = <3>; 3255 interrupt-controller; 3256 reg = <0x0 0x99a1000 0x0 0x1000>, 3257 <0x0 0x99a2000 0x0 0x1000>; 3258 interrupts = <GIC_SPI 0x234 3259 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3260 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3261 clock-names = "clk"; 3262 status = "disabled"; 3263 }; 3264 3265 agic_page5: interrupt-controller@99b0000 { 3266 compatible = "nvidia,tegra264-agic", 3267 "nvidia,tegra210-agic"; 3268 #interrupt-cells = <3>; 3269 interrupt-controller; 3270 reg = <0x0 0x99b1000 0x0 0x1000>, 3271 <0x0 0x99b2000 0x0 0x1000>; 3272 interrupts = <GIC_SPI 0x235 3273 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3274 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3275 clock-names = "clk"; 3276 status = "disabled"; 3277 }; 3278 }; 3279 3280 hte_aon: hardware-timestamp@c2b0000 { 3281 compatible = "nvidia,tegra264-gte-aon"; 3282 reg = <0x0 0x0c2b0000 0x0 0x10000>; 3283 interrupts = <GIC_SPI 0x00000226 IRQ_TYPE_LEVEL_HIGH>; 3284 nvidia,int-threshold = <1>; 3285 #timestamp-cells = <1>; 3286 nvidia,gpio-controller = <&gpio_aon>; 3287 status = "disabled"; 3288 }; 3289 3290 rtc: rtc@c2c0000 { 3291 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; 3292 reg = <0x0 0x0c2c0000 0x0 0x10000>; 3293 interrupt-parent = <&pmc>; 3294 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 3295 clocks = <&bpmp TEGRA264_CLK_CLK_S>; 3296 clock-names = "rtc"; 3297 status = "disabled"; 3298 }; 3299 3300 serial@c4e0000 { 3301 compatible = "nvidia,tegra264-utc"; 3302 reg = <0x0 0x0c4e0000 0x0 0x8000>, 3303 <0x0 0x0c4e8000 0x0 0x8000>; 3304 reg-names = "tx", "rx"; 3305 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 3306 rx-threshold = <4>; 3307 tx-threshold = <4>; 3308 status = "disabled"; 3309 }; 3310 3311 serial@c5a0000 { 3312 compatible = "nvidia,tegra264-utc"; 3313 reg = <0x0 0x0c5a0000 0x0 0x8000>, 3314 <0x0 0x0c5a8000 0x0 0x8000>; 3315 reg-names = "tx", "rx"; 3316 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 3317 rx-threshold = <4>; 3318 tx-threshold = <4>; 3319 status = "disabled"; 3320 }; 3321 3322 uart0: serial@c5f0000 { 3323 compatible = "arm,sbsa-uart"; 3324 reg = <0x0 0x0c5f0000 0x0 0x10000>; 3325 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 3326 status = "disabled"; 3327 }; 3328 3329 i2c2: i2c@c600000 { 3330 compatible = "nvidia,tegra264-i2c"; 3331 reg = <0x0 0x0c600000 0x0 0x10000>; 3332 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 3333 clock-frequency = <400000>; 3334 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 3335 <&bpmp TEGRA264_CLK_PLLAON>; 3336 clock-names = "div-clk", "parent"; 3337 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 3338 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 3339 resets = <&bpmp TEGRA264_RESET_I2C2>; 3340 reset-names = "i2c"; 3341 status = "disabled"; 3342 }; 3343 3344 i2c3: i2c@c610000 { 3345 compatible = "nvidia,tegra264-i2c"; 3346 reg = <0x0 0x0c610000 0x0 0x10000>; 3347 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 3348 clock-frequency = <400000>; 3349 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 3350 <&bpmp TEGRA264_CLK_PLLAON>; 3351 clock-names = "div-clk", "parent"; 3352 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 3353 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 3354 resets = <&bpmp TEGRA264_RESET_I2C3>; 3355 reset-names = "i2c"; 3356 status = "disabled"; 3357 }; 3358 3359 pwm4: pwm@c6a0000 { 3360 compatible = "nvidia,tegra264-pwm"; 3361 reg = <0x0 0xc6a0000 0x0 0x10000>; 3362 status = "disabled"; 3363 3364 clocks = <&bpmp TEGRA264_CLK_PWM4>; 3365 resets = <&bpmp TEGRA264_RESET_PWM4>; 3366 reset-names = "pwm"; 3367 3368 #pwm-cells = <2>; 3369 }; 3370 3371 pinmux_aon: pinmux@c7a2000 { 3372 compatible = "nvidia,tegra264-pinmux-aon"; 3373 reg = <0x0 0x0c7a2000 0x0 0x2000>; 3374 }; 3375 3376 pmc: pmc@c800000 { 3377 compatible = "nvidia,tegra264-pmc"; 3378 reg = <0x0 0x0c800000 0x0 0x100000>, 3379 <0x0 0x0c990000 0x0 0x10000>, 3380 <0x0 0x0ca00000 0x0 0x10000>, 3381 <0x0 0x0c980000 0x0 0x10000>, 3382 <0x0 0x0c9c0000 0x0 0x40000>; 3383 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 3384 #interrupt-cells = <2>; 3385 interrupt-controller; 3386 }; 3387 3388 gpio_aon: gpio@cf00000 { 3389 compatible = "nvidia,tegra264-gpio-aon"; 3390 reg = <0x0 0x0cf00000 0x0 0x10000>, 3391 <0x0 0x0cf10000 0x0 0x1000>; 3392 reg-names = "security", "gpio"; 3393 wakeup-parent = <&pmc>; 3394 interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; 3398 gpio-controller; 3399 #gpio-cells = <2>; 3400 interrupt-controller; 3401 #interrupt-cells = <2>; 3402 }; 3403 }; 3404 3405 /* TOP_MMIO */ 3406 bus@8100000000 { 3407 compatible = "simple-bus"; 3408 3409 #address-cells = <2>; 3410 #size-cells = <2>; 3411 3412 ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 3413 <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */ 3414 <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 3415 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 3416 3417 smmu1: iommu@5000000 { 3418 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3419 reg = <0x00 0x5000000 0x0 0x200000>; 3420 interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 3421 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; 3422 interrupt-names = "eventq", "gerror"; 3423 status = "disabled"; 3424 3425 #iommu-cells = <1>; 3426 dma-coherent; 3427 nvidia,cmdqv = <&cmdqv1>; 3428 }; 3429 3430 cmdqv1: cmdqv@5200000 { 3431 compatible = "nvidia,tegra264-cmdqv"; 3432 reg = <0x00 0x5200000 0x0 0x830000>; 3433 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 3434 status = "disabled"; 3435 }; 3436 3437 smmu2: iommu@6000000 { 3438 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3439 reg = <0x00 0x6000000 0x0 0x200000>; 3440 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 3441 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 3442 interrupt-names = "eventq", "gerror"; 3443 status = "disabled"; 3444 3445 #iommu-cells = <1>; 3446 dma-coherent; 3447 nvidia,cmdqv = <&cmdqv2>; 3448 }; 3449 3450 cmdqv2: cmdqv@6200000 { 3451 compatible = "nvidia,tegra264-cmdqv"; 3452 reg = <0x00 0x6200000 0x0 0x830000>; 3453 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 3454 status = "disabled"; 3455 }; 3456 3457 mc: memory-controller@8020000 { 3458 compatible = "nvidia,tegra264-mc"; 3459 reg = <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */ 3460 <0x000 0x8040000 0x0 0x20000>, /* MC 0 */ 3461 <0x000 0x8060000 0x0 0x20000>, /* MC 1 */ 3462 <0x000 0x8080000 0x0 0x20000>, /* MC 2 */ 3463 <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */ 3464 <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */ 3465 <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */ 3466 <0x000 0x8100000 0x0 0x20000>, /* MC 6 */ 3467 <0x000 0x8120000 0x0 0x20000>, /* MC 7 */ 3468 <0x000 0x8140000 0x0 0x20000>, /* MC 8 */ 3469 <0x000 0x8160000 0x0 0x20000>, /* MC 9 */ 3470 <0x000 0x8180000 0x0 0x20000>, /* MC 10 */ 3471 <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */ 3472 <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */ 3473 <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */ 3474 <0x000 0x8200000 0x0 0x20000>, /* MC 14 */ 3475 <0x000 0x8220000 0x0 0x20000>; /* MC 15 */ 3476 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", 3477 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", 3478 "ch10", "ch11", "ch12", "ch13", "ch14", 3479 "ch15"; 3480 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 3488 #interconnect-cells = <1>; 3489 3490 #address-cells = <2>; 3491 #size-cells = <2>; 3492 3493 /* limit the DMA range for memory clients to [39:0] */ 3494 dma-ranges = <0x000 0x0 0x000 0x0 0x100 0x0>; 3495 3496 emc: external-memory-controller@8800000 { 3497 compatible = "nvidia,tegra264-emc"; 3498 reg = <0x000 0x8800000 0x0 0x20000>, 3499 <0x000 0x8890000 0x0 0x20000>; 3500 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 3501 clocks = <&bpmp TEGRA264_CLK_EMC>, 3502 <&bpmp TEGRA264_CLK_DBB_UPHY0>; 3503 clock-names = "emc", "dbb"; 3504 3505 #interconnect-cells = <0>; 3506 nvidia,bpmp = <&bpmp>; 3507 }; 3508 }; 3509 3510 smmu0: iommu@a000000 { 3511 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3512 reg = <0x00 0xa000000 0x0 0x200000>; 3513 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 3514 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 3515 interrupt-names = "eventq", "gerror"; 3516 status = "disabled"; 3517 3518 #iommu-cells = <1>; 3519 dma-coherent; 3520 nvidia,cmdqv = <&cmdqv0>; 3521 }; 3522 3523 cmdqv0: cmdqv@a200000 { 3524 compatible = "nvidia,tegra264-cmdqv"; 3525 reg = <0x00 0xa200000 0x0 0x830000>; 3526 interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>; 3527 status = "disabled"; 3528 }; 3529 3530 smmu4: iommu@b000000 { 3531 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3532 reg = <0x00 0xb000000 0x0 0x200000>; 3533 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 3534 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 3535 interrupt-names = "eventq", "gerror"; 3536 status = "disabled"; 3537 3538 #iommu-cells = <1>; 3539 dma-coherent; 3540 nvidia,cmdqv = <&cmdqv4>; 3541 }; 3542 3543 cmdqv4: cmdqv@b200000 { 3544 compatible = "nvidia,tegra264-cmdqv"; 3545 reg = <0x00 0xb200000 0x0 0x830000>; 3546 interrupts = <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; 3547 status = "disabled"; 3548 }; 3549 3550 pci@c000000 { 3551 compatible = "nvidia,tegra264-pcie"; 3552 reg = <0x00 0x0c000000 0x0 0x00004000>, 3553 <0x00 0x0c004000 0x0 0x00001000>, 3554 <0x00 0x0c005000 0x0 0x00001000>, 3555 <0xd0 0xb0000000 0x0 0x10000000>; 3556 reg-names = "xal", "xtl", "xtl-pri", "ecam"; 3557 #address-cells = <3>; 3558 #size-cells = <2>; 3559 device_type = "pci"; 3560 linux,pci-domain = <0x00>; 3561 #interrupt-cells = <0x1>; 3562 3563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 3564 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_HIGH>, 3565 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>, 3566 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>, 3567 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>; 3568 3569 iommu-map = <0x0 &smmu2 0x10000 0x10000>; 3570 msi-map = <0x0 &its 0x210000 0x10000>; 3571 dma-coherent; 3572 3573 ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */ 3574 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */ 3575 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 3576 bus-range = <0x0 0xff>; 3577 3578 nvidia,bpmp = <&bpmp 0>; 3579 status = "disabled"; 3580 3581 pcie@0 { 3582 device_type = "pci"; 3583 compatible = "pciclass,0604"; 3584 reg = <0x0 0x0 0x0 0x0 0x0>; 3585 bus-range = <0x01 0xff>; 3586 #address-cells = <3>; 3587 #size-cells = <2>; 3588 ranges; 3589 }; 3590 }; 3591 3592 pinmux_main: pinmux@c281000 { 3593 compatible = "nvidia,tegra264-pinmux-main"; 3594 reg = <0x00 0x0c281000 0x0 0xc000>; 3595 }; 3596 3597 gpio_main: gpio@c300000 { 3598 compatible = "nvidia,tegra264-gpio"; 3599 reg = <0x00 0x0c300000 0x0 0x4000>, 3600 <0x00 0x0c310000 0x0 0x4000>; 3601 reg-names = "security", "gpio"; 3602 wakeup-parent = <&pmc>; 3603 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3635 gpio-controller; 3636 #gpio-cells = <2>; 3637 interrupt-controller; 3638 #interrupt-cells = <2>; 3639 }; 3640 3641 i2c14: i2c@c410000 { 3642 compatible = "nvidia,tegra264-i2c"; 3643 reg = <0x00 0x0c410000 0x0 0x10000>; 3644 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 3645 clock-frequency = <400000>; 3646 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3647 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3648 clock-names = "div-clk", "parent"; 3649 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3650 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3651 resets = <&bpmp TEGRA264_RESET_I2C14>; 3652 reset-names = "i2c"; 3653 status = "disabled"; 3654 }; 3655 3656 i2c15: i2c@c420000 { 3657 compatible = "nvidia,tegra264-i2c"; 3658 reg = <0x00 0x0c420000 0x0 0x10000>; 3659 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 3660 clock-frequency = <400000>; 3661 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3662 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3663 clock-names = "div-clk", "parent"; 3664 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3665 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3666 resets = <&bpmp TEGRA264_RESET_I2C15>; 3667 reset-names = "i2c"; 3668 status = "disabled"; 3669 }; 3670 3671 i2c16: i2c@c430000 { 3672 compatible = "nvidia,tegra264-i2c"; 3673 reg = <0x00 0x0c430000 0x0 0x10000>; 3674 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 3675 clock-frequency = <400000>; 3676 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3677 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3678 clock-names = "div-clk", "parent"; 3679 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3680 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3681 resets = <&bpmp TEGRA264_RESET_I2C16>; 3682 reset-names = "i2c"; 3683 status = "disabled"; 3684 }; 3685 3686 pwm2: pwm@c5e0000 { 3687 compatible = "nvidia,tegra264-pwm"; 3688 reg = <0x0 0xc5e0000 0x0 0x10000>; 3689 status = "disabled"; 3690 3691 clocks = <&bpmp TEGRA264_CLK_PWM2>; 3692 resets = <&bpmp TEGRA264_RESET_PWM2>; 3693 reset-names = "pwm"; 3694 3695 #pwm-cells = <2>; 3696 }; 3697 3698 pwm3: pwm@c5f0000 { 3699 compatible = "nvidia,tegra264-pwm"; 3700 reg = <0x0 0xc5f0000 0x0 0x10000>; 3701 status = "disabled"; 3702 3703 clocks = <&bpmp TEGRA264_CLK_PWM3>; 3704 resets = <&bpmp TEGRA264_RESET_PWM3>; 3705 reset-names = "pwm"; 3706 3707 #pwm-cells = <2>; 3708 }; 3709 3710 pwm5: pwm@c600000 { 3711 compatible = "nvidia,tegra264-pwm"; 3712 reg = <0x0 0xc600000 0x0 0x10000>; 3713 status = "disabled"; 3714 3715 clocks = <&bpmp TEGRA264_CLK_PWM5>; 3716 resets = <&bpmp TEGRA264_RESET_PWM5>; 3717 reset-names = "pwm"; 3718 3719 #pwm-cells = <2>; 3720 }; 3721 3722 pwm9: pwm@c610000 { 3723 compatible = "nvidia,tegra264-pwm"; 3724 reg = <0x0 0xc610000 0x0 0x10000>; 3725 status = "disabled"; 3726 3727 clocks = <&bpmp TEGRA264_CLK_PWM9>; 3728 resets = <&bpmp TEGRA264_RESET_PWM9>; 3729 reset-names = "pwm"; 3730 3731 #pwm-cells = <2>; 3732 }; 3733 3734 pwm10: pwm@c620000 { 3735 compatible = "nvidia,tegra264-pwm"; 3736 reg = <0x0 0xc620000 0x0 0x10000>; 3737 status = "disabled"; 3738 3739 clocks = <&bpmp TEGRA264_CLK_PWM10>; 3740 resets = <&bpmp TEGRA264_RESET_PWM10>; 3741 reset-names = "pwm"; 3742 3743 #pwm-cells = <2>; 3744 }; 3745 3746 i2c0: i2c@c630000 { 3747 compatible = "nvidia,tegra264-i2c"; 3748 reg = <0x00 0x0c630000 0x0 0x10000>; 3749 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3750 clock-frequency = <400000>; 3751 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3752 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3753 clock-names = "div-clk", "parent"; 3754 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3755 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3756 resets = <&bpmp TEGRA264_RESET_I2C0>; 3757 reset-names = "i2c"; 3758 status = "disabled"; 3759 }; 3760 3761 i2c1: i2c@c640000 { 3762 compatible = "nvidia,tegra264-i2c"; 3763 reg = <0x00 0x0c640000 0x0 0x10000>; 3764 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 3765 clock-frequency = <400000>; 3766 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3767 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3768 clock-names = "div-clk", "parent"; 3769 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3770 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3771 resets = <&bpmp TEGRA264_RESET_I2C1>; 3772 reset-names = "i2c"; 3773 status = "disabled"; 3774 }; 3775 3776 i2c4: i2c@c650000 { 3777 compatible = "nvidia,tegra264-i2c"; 3778 reg = <0x00 0x0c650000 0x0 0x10000>; 3779 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 3780 clock-frequency = <400000>; 3781 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3782 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3783 clock-names = "div-clk", "parent"; 3784 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3785 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3786 resets = <&bpmp TEGRA264_RESET_I2C4>; 3787 reset-names = "i2c"; 3788 status = "disabled"; 3789 }; 3790 3791 i2c6: i2c@c670000 { 3792 compatible = "nvidia,tegra264-i2c"; 3793 reg = <0x00 0x0c670000 0x0 0x10000>; 3794 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3795 clock-frequency = <400000>; 3796 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3797 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3798 clock-names = "div-clk", "parent"; 3799 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3800 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3801 resets = <&bpmp TEGRA264_RESET_I2C6>; 3802 reset-names = "i2c"; 3803 status = "disabled"; 3804 }; 3805 3806 i2c7: i2c@c680000 { 3807 compatible = "nvidia,tegra264-i2c"; 3808 reg = <0x00 0x0c680000 0x0 0x10000>; 3809 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 3810 clock-frequency = <400000>; 3811 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3812 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3813 clock-names = "div-clk", "parent"; 3814 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3815 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3816 resets = <&bpmp TEGRA264_RESET_I2C7>; 3817 reset-names = "i2c"; 3818 status = "disabled"; 3819 }; 3820 3821 i2c8: i2c@c690000 { 3822 compatible = "nvidia,tegra264-i2c"; 3823 reg = <0x00 0x0c690000 0x0 0x10000>; 3824 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 3825 clock-frequency = <400000>; 3826 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3827 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3828 clock-names = "div-clk", "parent"; 3829 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3830 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3831 resets = <&bpmp TEGRA264_RESET_I2C8>; 3832 reset-names = "i2c"; 3833 status = "disabled"; 3834 }; 3835 3836 i2c9: i2c@c6a0000 { 3837 compatible = "nvidia,tegra264-i2c"; 3838 reg = <0x00 0x0c6a0000 0x0 0x10000>; 3839 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3840 clock-frequency = <400000>; 3841 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3842 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3843 clock-names = "div-clk", "parent"; 3844 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3845 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3846 resets = <&bpmp TEGRA264_RESET_I2C9>; 3847 reset-names = "i2c"; 3848 status = "disabled"; 3849 }; 3850 3851 i2c10: i2c@c6b0000 { 3852 compatible = "nvidia,tegra264-i2c"; 3853 reg = <0x00 0x0c6b0000 0x0 0x10000>; 3854 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3855 clock-frequency = <400000>; 3856 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3857 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3858 clock-names = "div-clk", "parent"; 3859 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3860 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3861 resets = <&bpmp TEGRA264_RESET_I2C10>; 3862 reset-names = "i2c"; 3863 status = "disabled"; 3864 }; 3865 3866 i2c11: i2c@c6c0000 { 3867 compatible = "nvidia,tegra264-i2c"; 3868 reg = <0x00 0x0c6c0000 0x0 0x10000>; 3869 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3870 clock-frequency = <400000>; 3871 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3872 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3873 clock-names = "div-clk", "parent"; 3874 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3875 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3876 resets = <&bpmp TEGRA264_RESET_I2C11>; 3877 reset-names = "i2c"; 3878 status = "disabled"; 3879 }; 3880 3881 i2c12: i2c@c6d0000 { 3882 compatible = "nvidia,tegra264-i2c"; 3883 reg = <0x00 0x0c6d0000 0x0 0x10000>; 3884 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3885 clock-frequency = <400000>; 3886 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3887 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3888 clock-names = "div-clk", "parent"; 3889 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3890 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3891 resets = <&bpmp TEGRA264_RESET_I2C12>; 3892 reset-names = "i2c"; 3893 status = "disabled"; 3894 }; 3895 3896 gic: interrupt-controller@46000000 { 3897 compatible = "arm,gic-v3"; 3898 reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ 3899 <0x00 0x46080000 0x0 0x400000>; /* GICR */ 3900 interrupt-parent = <&gic>; 3901 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3902 3903 redistributor-stride = <0x0 0x40000>; 3904 #redistributor-regions = <1>; 3905 #interrupt-cells = <3>; 3906 interrupt-controller; 3907 3908 #address-cells = <2>; 3909 #size-cells = <2>; 3910 3911 ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>; 3912 3913 its: msi-controller@40000 { 3914 compatible = "arm,gic-v3-its"; 3915 reg = <0x0 0x40000 0x0 0x40000>; 3916 #msi-cells = <1>; 3917 msi-controller; 3918 }; 3919 }; 3920 }; 3921 3922 /* VISION MMIO */ 3923 bus@8180000000 { 3924 compatible = "simple-bus"; 3925 #address-cells = <2>; 3926 #size-cells = <2>; 3927 3928 ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */ 3929 <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ 3930 <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 3931 3932 host1x@1200000 { 3933 compatible = "nvidia,tegra264-host1x"; 3934 reg = <0x0 0x1200000 0x0 0x10000>, 3935 <0x0 0x1210000 0x0 0x10000>, 3936 <0x0 0x1240000 0x0 0x10000>; 3937 reg-names = "common", "hypervisor", "vm"; 3938 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 3947 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 3948 "syncpt5", "syncpt6", "syncpt7", "host1x"; 3949 clocks = <&bpmp TEGRA264_CLK_HOST1X>; 3950 clock-names = "host1x"; 3951 3952 #address-cells = <2>; 3953 #size-cells = <2>; 3954 3955 ranges = <0x000 0x00000000 0x00 0x08000000 0x00 0x01000000>, 3956 <0x000 0x02800000 0x00 0x0a800000 0x00 0x00800000>; 3957 3958 interconnects = <&mc TEGRA264_MEMORY_CLIENT_HOST1XR &emc>; 3959 interconnect-names = "dma-mem"; 3960 iommus = <&smmu1 TEGRA264_SID_HOST1X>; 3961 dma-coherent; 3962 3963 /* Context isolation domains */ 3964 iommu-map = <0 &smmu1 (TEGRA264_SID_VIC + 1) 16>; 3965 3966 vic@50000 { 3967 compatible = "nvidia,tegra264-vic"; 3968 reg = <0x0 0x50000 0x0 0x40000>; 3969 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 3970 clocks = <&bpmp TEGRA264_CLK_VIC>; 3971 clock-names = "vic"; 3972 resets = <&bpmp TEGRA264_RESET_VIC>; 3973 reset-names = "vic"; 3974 power-domains = <&bpmp TEGRA264_POWER_DOMAIN_VIC>; 3975 interconnects = <&mc TEGRA264_MEMORY_CLIENT_VICR &emc>, 3976 <&mc TEGRA264_MEMORY_CLIENT_VICW &emc>; 3977 interconnect-names = "dma-mem", "write"; 3978 3979 iommus = <&smmu1 TEGRA264_SID_VIC>; 3980 dma-coherent; 3981 }; 3982 }; 3983 }; 3984 3985 /* DISP_USB MMIO */ 3986 bus@8800000000 { 3987 compatible = "simple-bus"; 3988 #address-cells = <2>; 3989 #size-cells = <2>; 3990 3991 ranges = <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ 3992 3993 smmu3: iommu@6000000 { 3994 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3995 reg = <0x00 0x6000000 0x0 0x200000>; 3996 interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 3997 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; 3998 interrupt-names = "eventq", "gerror"; 3999 status = "disabled"; 4000 4001 #iommu-cells = <1>; 4002 dma-coherent; 4003 nvidia,cmdqv = <&cmdqv3>; 4004 }; 4005 4006 cmdqv3: cmdqv@6200000 { 4007 compatible = "nvidia,tegra264-cmdqv"; 4008 reg = <0x00 0x6200000 0x0 0x830000>; 4009 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>; 4010 status = "disabled"; 4011 }; 4012 4013 hda@90b0000 { 4014 compatible = "nvidia,tegra264-hda"; 4015 reg = <0x0 0x90b0000 0x0 0x10000>; 4016 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 4017 clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; 4018 clock-names = "hda"; 4019 resets = <&bpmp TEGRA264_RESET_HDA>, 4020 <&bpmp TEGRA264_RESET_HDACODEC>; 4021 reset-names = "hda", "hda2codec_2x"; 4022 interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, 4023 <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; 4024 interconnect-names = "dma-mem", "write"; 4025 iommus = <&smmu3 TEGRA264_SID_HDA>; 4026 status = "disabled"; 4027 }; 4028 }; 4029 4030 /* UPHY MMIO */ 4031 bus@a800000000 { 4032 compatible = "simple-bus"; 4033 #address-cells = <2>; 4034 #size-cells = <2>; 4035 4036 ranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 4037 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */ 4038 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 4039 4040 pinmux_uphy: pinmux@82e0000 { 4041 compatible = "nvidia,tegra264-pinmux-uphy"; 4042 reg = <0x00 0x082e0000 0x0 0x4000>; 4043 }; 4044 4045 gpio_uphy: gpio@8300000 { 4046 compatible = "nvidia,tegra264-gpio-uphy"; 4047 reg = <0x00 0x08300000 0x0 0x2000>, 4048 <0x00 0x08310000 0x0 0x2000>; 4049 reg-names = "security", "gpio"; 4050 wakeup-parent = <&pmc>; 4051 interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 4067 gpio-controller; 4068 #gpio-cells = <2>; 4069 interrupt-controller; 4070 #interrupt-cells = <2>; 4071 }; 4072 4073 pci@8400000 { 4074 compatible = "nvidia,tegra264-pcie"; 4075 reg = <0x00 0x08400000 0x0 0x00004000>, 4076 <0x00 0x08404000 0x0 0x00001000>, 4077 <0x00 0x08405000 0x0 0x00001000>, 4078 <0x00 0x08410000 0x0 0x00010000>, 4079 <0xa8 0xb0000000 0x0 0x10000000>; 4080 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4081 #address-cells = <3>; 4082 #size-cells = <2>; 4083 device_type = "pci"; 4084 linux,pci-domain = <0x01>; 4085 #interrupt-cells = <1>; 4086 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4087 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4088 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4089 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4090 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4091 4092 iommu-map = <0x0 &smmu1 0x10000 0x10000>; 4093 msi-map = <0x0 &its 0x110000 0x10000>; 4094 dma-coherent; 4095 4096 ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */ 4097 <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */ 4098 <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4099 bus-range = <0x00 0xff>; 4100 4101 nvidia,bpmp = <&bpmp 1>; 4102 status = "disabled"; 4103 4104 pcie@0 { 4105 device_type = "pci"; 4106 compatible = "pciclass,0604"; 4107 reg = <0x0 0x0 0x0 0x0 0x0>; 4108 bus-range = <0x01 0xff>; 4109 #address-cells = <3>; 4110 #size-cells = <2>; 4111 ranges; 4112 }; 4113 }; 4114 4115 pci@8420000 { 4116 compatible = "nvidia,tegra264-pcie"; 4117 reg = <0x00 0x08420000 0x0 0x00004000>, 4118 <0x00 0x08424000 0x0 0x00001000>, 4119 <0x00 0x08425000 0x0 0x00001000>, 4120 <0x00 0x08430000 0x0 0x00010000>, 4121 <0xb0 0xb0000000 0x0 0x10000000>; 4122 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4123 #address-cells = <3>; 4124 #size-cells = <2>; 4125 device_type = "pci"; 4126 linux,pci-domain = <0x02>; 4127 #interrupt-cells = <1>; 4128 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4129 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4130 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4131 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4132 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4133 4134 iommu-map = <0x0 &smmu1 0x20000 0x10000>; 4135 msi-map = <0x0 &its 0x120000 0x10000>; 4136 dma-coherent; 4137 4138 ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */ 4139 <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */ 4140 <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4141 bus-range = <0x00 0xff>; 4142 4143 nvidia,bpmp = <&bpmp 2>; 4144 status = "disabled"; 4145 4146 pcie@0 { 4147 device_type = "pci"; 4148 compatible = "pciclass,0604"; 4149 reg = <0x0 0x0 0x0 0x0 0x0>; 4150 bus-range = <0x01 0xff>; 4151 #address-cells = <3>; 4152 #size-cells = <2>; 4153 ranges; 4154 }; 4155 }; 4156 4157 pci@8440000 { 4158 compatible = "nvidia,tegra264-pcie"; 4159 reg = <0x00 0x08440000 0x0 0x00004000>, 4160 <0x00 0x08444000 0x0 0x00001000>, 4161 <0x00 0x08445000 0x0 0x00001000>, 4162 <0x00 0x08450000 0x0 0x00010000>, 4163 <0xb8 0xb0000000 0x0 0x10000000>; 4164 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4165 #address-cells = <3>; 4166 #size-cells = <2>; 4167 device_type = "pci"; 4168 linux,pci-domain = <0x03>; 4169 #interrupt-cells = <1>; 4170 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4171 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4172 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4173 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4174 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4175 4176 iommu-map = <0x0 &smmu1 0x30000 0x10000>; 4177 msi-map = <0x0 &its 0x130000 0x10000>; 4178 dma-coherent; 4179 4180 ranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */ 4181 <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */ 4182 <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4183 bus-range = <0x00 0xff>; 4184 4185 nvidia,bpmp = <&bpmp 3>; 4186 status = "disabled"; 4187 4188 pcie@0 { 4189 device_type = "pci"; 4190 compatible = "pciclass,0604"; 4191 reg = <0x0 0x0 0x0 0x0 0x0>; 4192 bus-range = <0x01 0xff>; 4193 #address-cells = <3>; 4194 #size-cells = <2>; 4195 ranges; 4196 }; 4197 }; 4198 4199 pci@8460000 { 4200 compatible = "nvidia,tegra264-pcie"; 4201 reg = <0x00 0x08460000 0x0 0x00004000>, 4202 <0x00 0x08464000 0x0 0x00001000>, 4203 <0x00 0x08465000 0x0 0x00001000>, 4204 <0x00 0x08470000 0x0 0x00010000>, 4205 <0xc0 0xb0000000 0x0 0x10000000>; 4206 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4207 #address-cells = <3>; 4208 #size-cells = <2>; 4209 device_type = "pci"; 4210 linux,pci-domain = <0x04>; 4211 #interrupt-cells = <1>; 4212 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4213 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4214 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4215 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4216 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4217 4218 iommu-map = <0x0 &smmu1 0x40000 0x10000>; 4219 msi-map = <0x0 &its 0x140000 0x10000>; 4220 dma-coherent; 4221 4222 ranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */ 4223 <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */ 4224 <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4225 bus-range = <0x00 0xff>; 4226 4227 nvidia,bpmp = <&bpmp 4>; 4228 status = "disabled"; 4229 4230 pcie@0 { 4231 device_type = "pci"; 4232 compatible = "pciclass,0604"; 4233 reg = <0x0 0x0 0x0 0x0 0x0>; 4234 bus-range = <0x01 0xff>; 4235 #address-cells = <3>; 4236 #size-cells = <2>; 4237 ranges; 4238 }; 4239 }; 4240 4241 pci@8480000 { 4242 compatible = "nvidia,tegra264-pcie"; 4243 reg = <0x00 0x08480000 0x0 0x00004000>, 4244 <0x00 0x08484000 0x0 0x00001000>, 4245 <0x00 0x08485000 0x0 0x00001000>, 4246 <0x00 0x08490000 0x0 0x00010000>, 4247 <0xc8 0xb0000000 0x0 0x10000000>; 4248 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4249 #address-cells = <3>; 4250 #size-cells = <2>; 4251 device_type = "pci"; 4252 linux,pci-domain = <0x05>; 4253 #interrupt-cells = <1>; 4254 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4255 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4256 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4257 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4258 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4259 4260 iommu-map = <0x0 &smmu1 0x50000 0x10000>; 4261 msi-map = <0x0 &its 0x150000 0x10000>; 4262 dma-coherent; 4263 4264 ranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */ 4265 <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */ 4266 <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4267 bus-range = <0x00 0xff>; 4268 4269 nvidia,bpmp = <&bpmp 5>; 4270 status = "disabled"; 4271 4272 pcie@0 { 4273 device_type = "pci"; 4274 compatible = "pciclass,0604"; 4275 reg = <0x0 0x0 0x0 0x0 0x0>; 4276 bus-range = <0x01 0xff>; 4277 #address-cells = <3>; 4278 #size-cells = <2>; 4279 ranges; 4280 }; 4281 }; 4282 }; 4283 4284 bpmp: bpmp { 4285 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; 4286 mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB 4287 TEGRA_HSP_DB_MASTER_BPMP>; 4288 memory-region = <&shmem_bpmp>; 4289 #clock-cells = <1>; 4290 #reset-cells = <1>; 4291 #power-domain-cells = <1>; 4292 4293 i2c { 4294 compatible = "nvidia,tegra186-bpmp-i2c"; 4295 nvidia,bpmp-bus-id = <5>; 4296 #address-cells = <1>; 4297 #size-cells = <0>; 4298 }; 4299 4300 thermal { 4301 compatible = "nvidia,tegra186-bpmp-thermal"; 4302 #thermal-sensor-cells = <1>; 4303 }; 4304 }; 4305 4306 cpus { 4307 #address-cells = <1>; 4308 #size-cells = <0>; 4309 4310 cpu0: cpu@0 { 4311 compatible = "arm,neoverse-v3ae"; 4312 device_type = "cpu"; 4313 reg = <0x00000>; 4314 4315 enable-method = "psci"; 4316 4317 i-cache-size = <65536>; 4318 i-cache-line-size = <64>; 4319 i-cache-sets = <256>; 4320 d-cache-size = <65536>; 4321 d-cache-line-size = <64>; 4322 d-cache-sets = <256>; 4323 next-level-cache = <&l2c0>; 4324 }; 4325 4326 cpu1: cpu@10000 { 4327 compatible = "arm,neoverse-v3ae"; 4328 device_type = "cpu"; 4329 reg = <0x10000>; 4330 4331 enable-method = "psci"; 4332 4333 i-cache-size = <65536>; 4334 i-cache-line-size = <64>; 4335 i-cache-sets = <256>; 4336 d-cache-size = <65536>; 4337 d-cache-line-size = <64>; 4338 d-cache-sets = <256>; 4339 next-level-cache = <&l2c1>; 4340 }; 4341 4342 cpu2: cpu@20000 { 4343 compatible = "arm,neoverse-v3ae"; 4344 device_type = "cpu"; 4345 reg = <0x20000>; 4346 4347 enable-method = "psci"; 4348 4349 i-cache-size = <65536>; 4350 i-cache-line-size = <64>; 4351 i-cache-sets = <256>; 4352 d-cache-size = <65536>; 4353 d-cache-line-size = <64>; 4354 d-cache-sets = <256>; 4355 next-level-cache = <&l2c2>; 4356 }; 4357 4358 cpu3: cpu@30000 { 4359 compatible = "arm,neoverse-v3ae"; 4360 device_type = "cpu"; 4361 reg = <0x30000>; 4362 4363 enable-method = "psci"; 4364 4365 i-cache-size = <65536>; 4366 i-cache-line-size = <64>; 4367 i-cache-sets = <256>; 4368 d-cache-size = <65536>; 4369 d-cache-line-size = <64>; 4370 d-cache-sets = <256>; 4371 next-level-cache = <&l2c3>; 4372 }; 4373 4374 cpu4: cpu@40000 { 4375 compatible = "arm,neoverse-v3ae"; 4376 device_type = "cpu"; 4377 reg = <0x40000>; 4378 4379 enable-method = "psci"; 4380 4381 i-cache-size = <65536>; 4382 i-cache-line-size = <64>; 4383 i-cache-sets = <256>; 4384 d-cache-size = <65536>; 4385 d-cache-line-size = <64>; 4386 d-cache-sets = <256>; 4387 next-level-cache = <&l2c4>; 4388 }; 4389 4390 cpu5: cpu@50000 { 4391 compatible = "arm,neoverse-v3ae"; 4392 device_type = "cpu"; 4393 reg = <0x50000>; 4394 4395 enable-method = "psci"; 4396 4397 i-cache-size = <65536>; 4398 i-cache-line-size = <64>; 4399 i-cache-sets = <256>; 4400 d-cache-size = <65536>; 4401 d-cache-line-size = <64>; 4402 d-cache-sets = <256>; 4403 next-level-cache = <&l2c5>; 4404 }; 4405 4406 cpu6: cpu@60000 { 4407 compatible = "arm,neoverse-v3ae"; 4408 device_type = "cpu"; 4409 reg = <0x60000>; 4410 4411 enable-method = "psci"; 4412 4413 i-cache-size = <65536>; 4414 i-cache-line-size = <64>; 4415 i-cache-sets = <256>; 4416 d-cache-size = <65536>; 4417 d-cache-line-size = <64>; 4418 d-cache-sets = <256>; 4419 next-level-cache = <&l2c6>; 4420 }; 4421 4422 cpu7: cpu@70000 { 4423 compatible = "arm,neoverse-v3ae"; 4424 device_type = "cpu"; 4425 reg = <0x70000>; 4426 4427 enable-method = "psci"; 4428 4429 i-cache-size = <65536>; 4430 i-cache-line-size = <64>; 4431 i-cache-sets = <256>; 4432 d-cache-size = <65536>; 4433 d-cache-line-size = <64>; 4434 d-cache-sets = <256>; 4435 next-level-cache = <&l2c7>; 4436 }; 4437 4438 cpu8: cpu@80000 { 4439 compatible = "arm,neoverse-v3ae"; 4440 device_type = "cpu"; 4441 reg = <0x80000>; 4442 4443 enable-method = "psci"; 4444 4445 i-cache-size = <65536>; 4446 i-cache-line-size = <64>; 4447 i-cache-sets = <256>; 4448 d-cache-size = <65536>; 4449 d-cache-line-size = <64>; 4450 d-cache-sets = <256>; 4451 next-level-cache = <&l2c8>; 4452 }; 4453 4454 cpu9: cpu@90000 { 4455 compatible = "arm,neoverse-v3ae"; 4456 device_type = "cpu"; 4457 reg = <0x90000>; 4458 4459 enable-method = "psci"; 4460 4461 i-cache-size = <65536>; 4462 i-cache-line-size = <64>; 4463 i-cache-sets = <256>; 4464 d-cache-size = <65536>; 4465 d-cache-line-size = <64>; 4466 d-cache-sets = <256>; 4467 next-level-cache = <&l2c9>; 4468 }; 4469 4470 cpu10: cpu@a0000 { 4471 compatible = "arm,neoverse-v3ae"; 4472 device_type = "cpu"; 4473 reg = <0xa0000>; 4474 4475 enable-method = "psci"; 4476 4477 i-cache-size = <65536>; 4478 i-cache-line-size = <64>; 4479 i-cache-sets = <256>; 4480 d-cache-size = <65536>; 4481 d-cache-line-size = <64>; 4482 d-cache-sets = <256>; 4483 next-level-cache = <&l2c10>; 4484 }; 4485 4486 cpu11: cpu@b0000 { 4487 compatible = "arm,neoverse-v3ae"; 4488 device_type = "cpu"; 4489 reg = <0xb0000>; 4490 4491 enable-method = "psci"; 4492 4493 i-cache-size = <65536>; 4494 i-cache-line-size = <64>; 4495 i-cache-sets = <256>; 4496 d-cache-size = <65536>; 4497 d-cache-line-size = <64>; 4498 d-cache-sets = <256>; 4499 next-level-cache = <&l2c11>; 4500 }; 4501 4502 cpu12: cpu@c0000 { 4503 compatible = "arm,neoverse-v3ae"; 4504 device_type = "cpu"; 4505 reg = <0xc0000>; 4506 4507 enable-method = "psci"; 4508 4509 i-cache-size = <65536>; 4510 i-cache-line-size = <64>; 4511 i-cache-sets = <256>; 4512 d-cache-size = <65536>; 4513 d-cache-line-size = <64>; 4514 d-cache-sets = <256>; 4515 next-level-cache = <&l2c12>; 4516 }; 4517 4518 cpu13: cpu@d0000 { 4519 compatible = "arm,neoverse-v3ae"; 4520 device_type = "cpu"; 4521 reg = <0xd0000>; 4522 4523 enable-method = "psci"; 4524 4525 i-cache-size = <65536>; 4526 i-cache-line-size = <64>; 4527 i-cache-sets = <256>; 4528 d-cache-size = <65536>; 4529 d-cache-line-size = <64>; 4530 d-cache-sets = <256>; 4531 next-level-cache = <&l2c13>; 4532 }; 4533 4534 l2c0: l2-cache-0 { 4535 compatible = "cache"; 4536 cache-level = <2>; 4537 cache-size = <1048576>; 4538 cache-line-size = <64>; 4539 cache-sets = <2048>; 4540 cache-unified; 4541 }; 4542 4543 l2c1: l2-cache-1 { 4544 compatible = "cache"; 4545 cache-level = <2>; 4546 cache-size = <1048576>; 4547 cache-line-size = <64>; 4548 cache-sets = <2048>; 4549 cache-unified; 4550 }; 4551 4552 l2c2: l2-cache-2 { 4553 compatible = "cache"; 4554 cache-level = <2>; 4555 cache-size = <1048576>; 4556 cache-line-size = <64>; 4557 cache-sets = <2048>; 4558 cache-unified; 4559 }; 4560 4561 l2c3: l2-cache-3 { 4562 compatible = "cache"; 4563 cache-level = <2>; 4564 cache-size = <1048576>; 4565 cache-line-size = <64>; 4566 cache-sets = <2048>; 4567 cache-unified; 4568 }; 4569 4570 l2c4: l2-cache-4 { 4571 compatible = "cache"; 4572 cache-level = <2>; 4573 cache-size = <1048576>; 4574 cache-line-size = <64>; 4575 cache-sets = <2048>; 4576 cache-unified; 4577 }; 4578 4579 l2c5: l2-cache-5 { 4580 compatible = "cache"; 4581 cache-level = <2>; 4582 cache-size = <1048576>; 4583 cache-line-size = <64>; 4584 cache-sets = <2048>; 4585 cache-unified; 4586 }; 4587 4588 l2c6: l2-cache-6 { 4589 compatible = "cache"; 4590 cache-level = <2>; 4591 cache-size = <1048576>; 4592 cache-line-size = <64>; 4593 cache-sets = <2048>; 4594 cache-unified; 4595 }; 4596 4597 l2c7: l2-cache-7 { 4598 compatible = "cache"; 4599 cache-level = <2>; 4600 cache-size = <1048576>; 4601 cache-line-size = <64>; 4602 cache-sets = <2048>; 4603 cache-unified; 4604 }; 4605 4606 l2c8: l2-cache-8 { 4607 compatible = "cache"; 4608 cache-level = <2>; 4609 cache-size = <1048576>; 4610 cache-line-size = <64>; 4611 cache-sets = <2048>; 4612 cache-unified; 4613 }; 4614 4615 l2c9: l2-cache-9 { 4616 compatible = "cache"; 4617 cache-level = <2>; 4618 cache-size = <1048576>; 4619 cache-line-size = <64>; 4620 cache-sets = <2048>; 4621 cache-unified; 4622 }; 4623 4624 l2c10: l2-cache-10 { 4625 compatible = "cache"; 4626 cache-level = <2>; 4627 cache-size = <1048576>; 4628 cache-line-size = <64>; 4629 cache-sets = <2048>; 4630 cache-unified; 4631 }; 4632 4633 l2c11: l2-cache-11 { 4634 compatible = "cache"; 4635 cache-level = <2>; 4636 cache-size = <1048576>; 4637 cache-line-size = <64>; 4638 cache-sets = <2048>; 4639 cache-unified; 4640 }; 4641 4642 l2c12: l2-cache-12 { 4643 compatible = "cache"; 4644 cache-level = <2>; 4645 cache-size = <1048576>; 4646 cache-line-size = <64>; 4647 cache-sets = <2048>; 4648 cache-unified; 4649 }; 4650 4651 l2c13: l2-cache-13 { 4652 compatible = "cache"; 4653 cache-level = <2>; 4654 cache-size = <1048576>; 4655 cache-line-size = <64>; 4656 cache-sets = <2048>; 4657 cache-unified; 4658 }; 4659 4660 }; 4661 4662 pmu { 4663 compatible = "arm,armv8-pmuv3"; 4664 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 4665 }; 4666 4667 psci { 4668 compatible = "arm,psci-1.0"; 4669 method = "smc"; 4670 }; 4671 4672 sound { 4673 compatible = "nvidia,tegra264-audio-graph-card"; 4674 4675 clocks = <&bpmp TEGRA264_CLK_PLLA1>, 4676 <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 4677 clock-names = "pll_a", "plla_out0"; 4678 assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>, 4679 <&bpmp TEGRA264_CLK_PLLA1_OUT1>, 4680 <&bpmp TEGRA264_CLK_AUD_MCLK>; 4681 assigned-clock-parents = <0>, 4682 <&bpmp TEGRA264_CLK_PLLA1>, 4683 <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 4684 4685 status = "disabled"; 4686 }; 4687 4688 timer { 4689 compatible = "arm,armv8-timer"; 4690 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4691 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4692 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4693 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 4694 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 4695 }; 4696}; 4697