1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7 *
8 * Driver for Semtech SX150X I2C GPIO Expanders
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
10 *
11 * Author: Gregory Bean <gbean@codeaurora.org>
12 */
13
14 #include <linux/regmap.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/mutex.h>
20 #include <linux/slab.h>
21 #include <linux/of.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27
28 #include "core.h"
29 #include "pinconf.h"
30 #include "pinctrl-utils.h"
31
32 /* The chip models of sx150x */
33 enum {
34 SX150X_123 = 0,
35 SX150X_456,
36 SX150X_789,
37 };
38 enum {
39 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
40 SX150X_MAX_REGISTER = 0xad,
41 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
42 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
43 SX150X_789_RESET_KEY1 = 0x12,
44 SX150X_789_RESET_KEY2 = 0x34,
45 };
46
47 struct sx150x_123_pri {
48 u8 reg_pld_mode;
49 u8 reg_pld_table0;
50 u8 reg_pld_table1;
51 u8 reg_pld_table2;
52 u8 reg_pld_table3;
53 u8 reg_pld_table4;
54 u8 reg_advanced;
55 };
56
57 struct sx150x_456_pri {
58 u8 reg_pld_mode;
59 u8 reg_pld_table0;
60 u8 reg_pld_table1;
61 u8 reg_pld_table2;
62 u8 reg_pld_table3;
63 u8 reg_pld_table4;
64 u8 reg_advanced;
65 };
66
67 struct sx150x_789_pri {
68 u8 reg_drain;
69 u8 reg_polarity;
70 u8 reg_clock;
71 u8 reg_misc;
72 u8 reg_reset;
73 u8 ngpios;
74 };
75
76 struct sx150x_device_data {
77 u8 model;
78 u8 reg_pullup;
79 u8 reg_pulldn;
80 u8 reg_dir;
81 u8 reg_data;
82 u8 reg_irq_mask;
83 u8 reg_irq_src;
84 u8 reg_sense;
85 u8 ngpios;
86 union {
87 struct sx150x_123_pri x123;
88 struct sx150x_456_pri x456;
89 struct sx150x_789_pri x789;
90 } pri;
91 const struct pinctrl_pin_desc *pins;
92 unsigned int npins;
93 };
94
95 struct sx150x_pinctrl {
96 struct device *dev;
97 struct i2c_client *client;
98 struct pinctrl_dev *pctldev;
99 struct pinctrl_desc pinctrl_desc;
100 struct gpio_chip gpio;
101 struct regmap *regmap;
102 struct {
103 u32 sense;
104 u32 masked;
105 } irq;
106 struct mutex lock;
107 const struct sx150x_device_data *data;
108 };
109
110 static const struct pinctrl_pin_desc sx150x_4_pins[] = {
111 PINCTRL_PIN(0, "gpio0"),
112 PINCTRL_PIN(1, "gpio1"),
113 PINCTRL_PIN(2, "gpio2"),
114 PINCTRL_PIN(3, "gpio3"),
115 PINCTRL_PIN(4, "oscio"),
116 };
117
118 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
119 PINCTRL_PIN(0, "gpio0"),
120 PINCTRL_PIN(1, "gpio1"),
121 PINCTRL_PIN(2, "gpio2"),
122 PINCTRL_PIN(3, "gpio3"),
123 PINCTRL_PIN(4, "gpio4"),
124 PINCTRL_PIN(5, "gpio5"),
125 PINCTRL_PIN(6, "gpio6"),
126 PINCTRL_PIN(7, "gpio7"),
127 PINCTRL_PIN(8, "oscio"),
128 };
129
130 static const struct pinctrl_pin_desc sx150x_16_pins[] = {
131 PINCTRL_PIN(0, "gpio0"),
132 PINCTRL_PIN(1, "gpio1"),
133 PINCTRL_PIN(2, "gpio2"),
134 PINCTRL_PIN(3, "gpio3"),
135 PINCTRL_PIN(4, "gpio4"),
136 PINCTRL_PIN(5, "gpio5"),
137 PINCTRL_PIN(6, "gpio6"),
138 PINCTRL_PIN(7, "gpio7"),
139 PINCTRL_PIN(8, "gpio8"),
140 PINCTRL_PIN(9, "gpio9"),
141 PINCTRL_PIN(10, "gpio10"),
142 PINCTRL_PIN(11, "gpio11"),
143 PINCTRL_PIN(12, "gpio12"),
144 PINCTRL_PIN(13, "gpio13"),
145 PINCTRL_PIN(14, "gpio14"),
146 PINCTRL_PIN(15, "gpio15"),
147 PINCTRL_PIN(16, "oscio"),
148 };
149
150 static const struct sx150x_device_data sx1501q_device_data = {
151 .model = SX150X_123,
152 .reg_pullup = 0x02,
153 .reg_pulldn = 0x03,
154 .reg_dir = 0x01,
155 .reg_data = 0x00,
156 .reg_irq_mask = 0x05,
157 .reg_irq_src = 0x08,
158 .reg_sense = 0x07,
159 .pri.x123 = {
160 .reg_pld_mode = 0x10,
161 .reg_pld_table0 = 0x11,
162 .reg_pld_table2 = 0x13,
163 .reg_advanced = 0xad,
164 },
165 .ngpios = 4,
166 .pins = sx150x_4_pins,
167 .npins = 4, /* oscio not available */
168 };
169
170 static const struct sx150x_device_data sx1502q_device_data = {
171 .model = SX150X_123,
172 .reg_pullup = 0x02,
173 .reg_pulldn = 0x03,
174 .reg_dir = 0x01,
175 .reg_data = 0x00,
176 .reg_irq_mask = 0x05,
177 .reg_irq_src = 0x08,
178 .reg_sense = 0x06,
179 .pri.x123 = {
180 .reg_pld_mode = 0x10,
181 .reg_pld_table0 = 0x11,
182 .reg_pld_table1 = 0x12,
183 .reg_pld_table2 = 0x13,
184 .reg_pld_table3 = 0x14,
185 .reg_pld_table4 = 0x15,
186 .reg_advanced = 0xad,
187 },
188 .ngpios = 8,
189 .pins = sx150x_8_pins,
190 .npins = 8, /* oscio not available */
191 };
192
193 static const struct sx150x_device_data sx1503q_device_data = {
194 .model = SX150X_123,
195 .reg_pullup = 0x04,
196 .reg_pulldn = 0x06,
197 .reg_dir = 0x02,
198 .reg_data = 0x00,
199 .reg_irq_mask = 0x08,
200 .reg_irq_src = 0x0e,
201 .reg_sense = 0x0a,
202 .pri.x123 = {
203 .reg_pld_mode = 0x20,
204 .reg_pld_table0 = 0x22,
205 .reg_pld_table1 = 0x24,
206 .reg_pld_table2 = 0x26,
207 .reg_pld_table3 = 0x28,
208 .reg_pld_table4 = 0x2a,
209 .reg_advanced = 0xad,
210 },
211 .ngpios = 16,
212 .pins = sx150x_16_pins,
213 .npins = 16, /* oscio not available */
214 };
215
216 static const struct sx150x_device_data sx1504q_device_data = {
217 .model = SX150X_456,
218 .reg_pullup = 0x02,
219 .reg_pulldn = 0x03,
220 .reg_dir = 0x01,
221 .reg_data = 0x00,
222 .reg_irq_mask = 0x05,
223 .reg_irq_src = 0x08,
224 .reg_sense = 0x07,
225 .pri.x456 = {
226 .reg_pld_mode = 0x10,
227 .reg_pld_table0 = 0x11,
228 .reg_pld_table2 = 0x13,
229 },
230 .ngpios = 4,
231 .pins = sx150x_4_pins,
232 .npins = 4, /* oscio not available */
233 };
234
235 static const struct sx150x_device_data sx1505q_device_data = {
236 .model = SX150X_456,
237 .reg_pullup = 0x02,
238 .reg_pulldn = 0x03,
239 .reg_dir = 0x01,
240 .reg_data = 0x00,
241 .reg_irq_mask = 0x05,
242 .reg_irq_src = 0x08,
243 .reg_sense = 0x06,
244 .pri.x456 = {
245 .reg_pld_mode = 0x10,
246 .reg_pld_table0 = 0x11,
247 .reg_pld_table1 = 0x12,
248 .reg_pld_table2 = 0x13,
249 .reg_pld_table3 = 0x14,
250 .reg_pld_table4 = 0x15,
251 },
252 .ngpios = 8,
253 .pins = sx150x_8_pins,
254 .npins = 8, /* oscio not available */
255 };
256
257 static const struct sx150x_device_data sx1506q_device_data = {
258 .model = SX150X_456,
259 .reg_pullup = 0x04,
260 .reg_pulldn = 0x06,
261 .reg_dir = 0x02,
262 .reg_data = 0x00,
263 .reg_irq_mask = 0x08,
264 .reg_irq_src = 0x0e,
265 .reg_sense = 0x0a,
266 .pri.x456 = {
267 .reg_pld_mode = 0x20,
268 .reg_pld_table0 = 0x22,
269 .reg_pld_table1 = 0x24,
270 .reg_pld_table2 = 0x26,
271 .reg_pld_table3 = 0x28,
272 .reg_pld_table4 = 0x2a,
273 .reg_advanced = 0xad,
274 },
275 .ngpios = 16,
276 .pins = sx150x_16_pins,
277 .npins = 16, /* oscio not available */
278 };
279
280 static const struct sx150x_device_data sx1507q_device_data = {
281 .model = SX150X_789,
282 .reg_pullup = 0x03,
283 .reg_pulldn = 0x04,
284 .reg_dir = 0x07,
285 .reg_data = 0x08,
286 .reg_irq_mask = 0x09,
287 .reg_irq_src = 0x0b,
288 .reg_sense = 0x0a,
289 .pri.x789 = {
290 .reg_drain = 0x05,
291 .reg_polarity = 0x06,
292 .reg_clock = 0x0d,
293 .reg_misc = 0x0e,
294 .reg_reset = 0x7d,
295 },
296 .ngpios = 4,
297 .pins = sx150x_4_pins,
298 .npins = ARRAY_SIZE(sx150x_4_pins),
299 };
300
301 static const struct sx150x_device_data sx1508q_device_data = {
302 .model = SX150X_789,
303 .reg_pullup = 0x03,
304 .reg_pulldn = 0x04,
305 .reg_dir = 0x07,
306 .reg_data = 0x08,
307 .reg_irq_mask = 0x09,
308 .reg_irq_src = 0x0c,
309 .reg_sense = 0x0a,
310 .pri.x789 = {
311 .reg_drain = 0x05,
312 .reg_polarity = 0x06,
313 .reg_clock = 0x0f,
314 .reg_misc = 0x10,
315 .reg_reset = 0x7d,
316 },
317 .ngpios = 8,
318 .pins = sx150x_8_pins,
319 .npins = ARRAY_SIZE(sx150x_8_pins),
320 };
321
322 static const struct sx150x_device_data sx1509q_device_data = {
323 .model = SX150X_789,
324 .reg_pullup = 0x06,
325 .reg_pulldn = 0x08,
326 .reg_dir = 0x0e,
327 .reg_data = 0x10,
328 .reg_irq_mask = 0x12,
329 .reg_irq_src = 0x18,
330 .reg_sense = 0x14,
331 .pri.x789 = {
332 .reg_drain = 0x0a,
333 .reg_polarity = 0x0c,
334 .reg_clock = 0x1e,
335 .reg_misc = 0x1f,
336 .reg_reset = 0x7d,
337 },
338 .ngpios = 16,
339 .pins = sx150x_16_pins,
340 .npins = ARRAY_SIZE(sx150x_16_pins),
341 };
342
sx150x_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)343 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
344 {
345 return 0;
346 }
347
sx150x_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)348 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
349 unsigned int group)
350 {
351 return NULL;
352 }
353
sx150x_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)354 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
355 unsigned int group,
356 const unsigned int **pins,
357 unsigned int *num_pins)
358 {
359 return -ENOTSUPP;
360 }
361
362 static const struct pinctrl_ops sx150x_pinctrl_ops = {
363 .get_groups_count = sx150x_pinctrl_get_groups_count,
364 .get_group_name = sx150x_pinctrl_get_group_name,
365 .get_group_pins = sx150x_pinctrl_get_group_pins,
366 #ifdef CONFIG_OF
367 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
368 .dt_free_map = pinctrl_utils_free_map,
369 #endif
370 };
371
sx150x_pin_is_oscio(struct sx150x_pinctrl * pctl,unsigned int pin)372 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
373 {
374 if (pin >= pctl->data->npins)
375 return false;
376
377 /* OSCIO pin is only present in 789 devices */
378 if (pctl->data->model != SX150X_789)
379 return false;
380
381 return !strcmp(pctl->data->pins[pin].name, "oscio");
382 }
383
sx150x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)384 static int sx150x_gpio_get_direction(struct gpio_chip *chip,
385 unsigned int offset)
386 {
387 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
388 unsigned int value;
389 int ret;
390
391 if (sx150x_pin_is_oscio(pctl, offset))
392 return GPIO_LINE_DIRECTION_OUT;
393
394 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
395 if (ret < 0)
396 return ret;
397
398 if (value & BIT(offset))
399 return GPIO_LINE_DIRECTION_IN;
400
401 return GPIO_LINE_DIRECTION_OUT;
402 }
403
sx150x_gpio_get(struct gpio_chip * chip,unsigned int offset)404 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
405 {
406 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
407 unsigned int value;
408 int ret;
409
410 if (sx150x_pin_is_oscio(pctl, offset))
411 return -EINVAL;
412
413 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
414 if (ret < 0)
415 return ret;
416
417 return !!(value & BIT(offset));
418 }
419
__sx150x_gpio_set(struct sx150x_pinctrl * pctl,unsigned int offset,int value)420 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
421 int value)
422 {
423 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
424 BIT(offset), value ? BIT(offset) : 0);
425 }
426
sx150x_gpio_oscio_set(struct sx150x_pinctrl * pctl,int value)427 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
428 int value)
429 {
430 return regmap_write(pctl->regmap,
431 pctl->data->pri.x789.reg_clock,
432 (value ? 0x1f : 0x10));
433 }
434
sx150x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)435 static int sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
436 int value)
437 {
438 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
439
440 if (sx150x_pin_is_oscio(pctl, offset))
441 return sx150x_gpio_oscio_set(pctl, value);
442
443 return __sx150x_gpio_set(pctl, offset, value);
444 }
445
sx150x_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)446 static int sx150x_gpio_set_multiple(struct gpio_chip *chip,
447 unsigned long *mask,
448 unsigned long *bits)
449 {
450 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
451
452 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask,
453 *bits);
454 }
455
sx150x_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)456 static int sx150x_gpio_direction_input(struct gpio_chip *chip,
457 unsigned int offset)
458 {
459 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
460
461 if (sx150x_pin_is_oscio(pctl, offset))
462 return -EINVAL;
463
464 return regmap_write_bits(pctl->regmap,
465 pctl->data->reg_dir,
466 BIT(offset), BIT(offset));
467 }
468
sx150x_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)469 static int sx150x_gpio_direction_output(struct gpio_chip *chip,
470 unsigned int offset, int value)
471 {
472 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
473 int ret;
474
475 if (sx150x_pin_is_oscio(pctl, offset))
476 return sx150x_gpio_oscio_set(pctl, value);
477
478 ret = __sx150x_gpio_set(pctl, offset, value);
479 if (ret < 0)
480 return ret;
481
482 return regmap_write_bits(pctl->regmap,
483 pctl->data->reg_dir,
484 BIT(offset), 0);
485 }
486
sx150x_irq_mask(struct irq_data * d)487 static void sx150x_irq_mask(struct irq_data *d)
488 {
489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
490 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
491 unsigned int n = irqd_to_hwirq(d);
492
493 pctl->irq.masked |= BIT(n);
494 gpiochip_disable_irq(gc, n);
495 }
496
sx150x_irq_unmask(struct irq_data * d)497 static void sx150x_irq_unmask(struct irq_data *d)
498 {
499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
500 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
501 unsigned int n = irqd_to_hwirq(d);
502
503 gpiochip_enable_irq(gc, n);
504 pctl->irq.masked &= ~BIT(n);
505 }
506
sx150x_irq_set_sense(struct sx150x_pinctrl * pctl,unsigned int line,unsigned int sense)507 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
508 unsigned int line, unsigned int sense)
509 {
510 /*
511 * Every interrupt line is represented by two bits shifted
512 * proportionally to the line number
513 */
514 const unsigned int n = line * 2;
515 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
516 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
517
518 pctl->irq.sense &= mask;
519 pctl->irq.sense |= sense << n;
520 }
521
sx150x_irq_set_type(struct irq_data * d,unsigned int flow_type)522 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
523 {
524 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
525 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
526 unsigned int n, val = 0;
527
528 if (flow_type & IRQ_TYPE_LEVEL_MASK)
529 return -EINVAL;
530
531 n = irqd_to_hwirq(d);
532
533 if (flow_type & IRQ_TYPE_EDGE_RISING)
534 val |= SX150X_IRQ_TYPE_EDGE_RISING;
535 if (flow_type & IRQ_TYPE_EDGE_FALLING)
536 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
537
538 sx150x_irq_set_sense(pctl, n, val);
539 return 0;
540 }
541
sx150x_irq_thread_fn(int irq,void * dev_id)542 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
543 {
544 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
545 unsigned long n, status;
546 unsigned int val;
547 int err;
548
549 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
550 if (err < 0)
551 return IRQ_NONE;
552
553 if (!val)
554 return IRQ_NONE;
555
556 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
557 if (err < 0)
558 return IRQ_NONE;
559
560 status = val;
561 for_each_set_bit(n, &status, pctl->data->ngpios)
562 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
563
564 return IRQ_HANDLED;
565 }
566
sx150x_irq_bus_lock(struct irq_data * d)567 static void sx150x_irq_bus_lock(struct irq_data *d)
568 {
569 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
570 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
571
572 mutex_lock(&pctl->lock);
573 }
574
sx150x_irq_bus_sync_unlock(struct irq_data * d)575 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
576 {
577 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
578 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
579
580 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
581 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
582 mutex_unlock(&pctl->lock);
583 }
584
585
sx150x_irq_print_chip(struct irq_data * d,struct seq_file * p)586 static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p)
587 {
588 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
589 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
590
591 seq_puts(p, pctl->client->name);
592 }
593
594 static const struct irq_chip sx150x_irq_chip = {
595 .irq_mask = sx150x_irq_mask,
596 .irq_unmask = sx150x_irq_unmask,
597 .irq_set_type = sx150x_irq_set_type,
598 .irq_bus_lock = sx150x_irq_bus_lock,
599 .irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock,
600 .irq_print_chip = sx150x_irq_print_chip,
601 .flags = IRQCHIP_IMMUTABLE,
602 GPIOCHIP_IRQ_RESOURCE_HELPERS,
603 };
604
sx150x_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)605 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
606 unsigned long *config)
607 {
608 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
609 unsigned int param = pinconf_to_config_param(*config);
610 int ret;
611 u32 arg;
612 unsigned int data;
613
614 if (sx150x_pin_is_oscio(pctl, pin)) {
615 switch (param) {
616 case PIN_CONFIG_DRIVE_PUSH_PULL:
617 case PIN_CONFIG_LEVEL:
618 ret = regmap_read(pctl->regmap,
619 pctl->data->pri.x789.reg_clock,
620 &data);
621 if (ret < 0)
622 return ret;
623
624 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
625 arg = (data & 0x1f) ? 1 : 0;
626 else {
627 if ((data & 0x1f) == 0x1f)
628 arg = 1;
629 else if ((data & 0x1f) == 0x10)
630 arg = 0;
631 else
632 return -EINVAL;
633 }
634
635 break;
636 default:
637 return -ENOTSUPP;
638 }
639
640 goto out;
641 }
642
643 switch (param) {
644 case PIN_CONFIG_BIAS_PULL_DOWN:
645 ret = regmap_read(pctl->regmap,
646 pctl->data->reg_pulldn,
647 &data);
648 data &= BIT(pin);
649
650 if (ret < 0)
651 return ret;
652
653 if (!ret)
654 return -EINVAL;
655
656 arg = 1;
657 break;
658
659 case PIN_CONFIG_BIAS_PULL_UP:
660 ret = regmap_read(pctl->regmap,
661 pctl->data->reg_pullup,
662 &data);
663 data &= BIT(pin);
664
665 if (ret < 0)
666 return ret;
667
668 if (!ret)
669 return -EINVAL;
670
671 arg = 1;
672 break;
673
674 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
675 if (pctl->data->model != SX150X_789)
676 return -ENOTSUPP;
677
678 ret = regmap_read(pctl->regmap,
679 pctl->data->pri.x789.reg_drain,
680 &data);
681 data &= BIT(pin);
682
683 if (ret < 0)
684 return ret;
685
686 if (!data)
687 return -EINVAL;
688
689 arg = 1;
690 break;
691
692 case PIN_CONFIG_DRIVE_PUSH_PULL:
693 if (pctl->data->model != SX150X_789)
694 arg = true;
695 else {
696 ret = regmap_read(pctl->regmap,
697 pctl->data->pri.x789.reg_drain,
698 &data);
699 data &= BIT(pin);
700
701 if (ret < 0)
702 return ret;
703
704 if (data)
705 return -EINVAL;
706
707 arg = 1;
708 }
709 break;
710
711 case PIN_CONFIG_LEVEL:
712 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
713 if (ret < 0)
714 return ret;
715
716 if (ret == GPIO_LINE_DIRECTION_IN)
717 return -EINVAL;
718
719 ret = sx150x_gpio_get(&pctl->gpio, pin);
720 if (ret < 0)
721 return ret;
722
723 arg = ret;
724 break;
725
726 default:
727 return -ENOTSUPP;
728 }
729
730 out:
731 *config = pinconf_to_config_packed(param, arg);
732
733 return 0;
734 }
735
sx150x_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)736 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
737 unsigned long *configs, unsigned int num_configs)
738 {
739 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
740 enum pin_config_param param;
741 u32 arg;
742 int i;
743 int ret;
744
745 for (i = 0; i < num_configs; i++) {
746 param = pinconf_to_config_param(configs[i]);
747 arg = pinconf_to_config_argument(configs[i]);
748
749 if (sx150x_pin_is_oscio(pctl, pin)) {
750 if (param == PIN_CONFIG_LEVEL) {
751 ret = sx150x_gpio_direction_output(&pctl->gpio,
752 pin, arg);
753 if (ret < 0)
754 return ret;
755
756 continue;
757 } else
758 return -ENOTSUPP;
759 }
760
761 switch (param) {
762 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
763 case PIN_CONFIG_BIAS_DISABLE:
764 ret = regmap_write_bits(pctl->regmap,
765 pctl->data->reg_pulldn,
766 BIT(pin), 0);
767 if (ret < 0)
768 return ret;
769
770 ret = regmap_write_bits(pctl->regmap,
771 pctl->data->reg_pullup,
772 BIT(pin), 0);
773 if (ret < 0)
774 return ret;
775
776 break;
777
778 case PIN_CONFIG_BIAS_PULL_UP:
779 ret = regmap_write_bits(pctl->regmap,
780 pctl->data->reg_pullup,
781 BIT(pin), BIT(pin));
782 if (ret < 0)
783 return ret;
784
785 break;
786
787 case PIN_CONFIG_BIAS_PULL_DOWN:
788 ret = regmap_write_bits(pctl->regmap,
789 pctl->data->reg_pulldn,
790 BIT(pin), BIT(pin));
791 if (ret < 0)
792 return ret;
793
794 break;
795
796 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
797 if (pctl->data->model != SX150X_789 ||
798 sx150x_pin_is_oscio(pctl, pin))
799 return -ENOTSUPP;
800
801 ret = regmap_write_bits(pctl->regmap,
802 pctl->data->pri.x789.reg_drain,
803 BIT(pin), BIT(pin));
804 if (ret < 0)
805 return ret;
806
807 break;
808
809 case PIN_CONFIG_DRIVE_PUSH_PULL:
810 if (pctl->data->model != SX150X_789 ||
811 sx150x_pin_is_oscio(pctl, pin))
812 return 0;
813
814 ret = regmap_write_bits(pctl->regmap,
815 pctl->data->pri.x789.reg_drain,
816 BIT(pin), 0);
817 if (ret < 0)
818 return ret;
819
820 break;
821
822 case PIN_CONFIG_LEVEL:
823 ret = sx150x_gpio_direction_output(&pctl->gpio,
824 pin, arg);
825 if (ret < 0)
826 return ret;
827
828 break;
829
830 default:
831 return -ENOTSUPP;
832 }
833 } /* for each config */
834
835 return 0;
836 }
837
838 static const struct pinconf_ops sx150x_pinconf_ops = {
839 .pin_config_get = sx150x_pinconf_get,
840 .pin_config_set = sx150x_pinconf_set,
841 .is_generic = true,
842 };
843
844 static const struct i2c_device_id sx150x_id[] = {
845 { .name = "sx1501q", .driver_data = (kernel_ulong_t)&sx1501q_device_data },
846 { .name = "sx1502q", .driver_data = (kernel_ulong_t)&sx1502q_device_data },
847 { .name = "sx1503q", .driver_data = (kernel_ulong_t)&sx1503q_device_data },
848 { .name = "sx1504q", .driver_data = (kernel_ulong_t)&sx1504q_device_data },
849 { .name = "sx1505q", .driver_data = (kernel_ulong_t)&sx1505q_device_data },
850 { .name = "sx1506q", .driver_data = (kernel_ulong_t)&sx1506q_device_data },
851 { .name = "sx1507q", .driver_data = (kernel_ulong_t)&sx1507q_device_data },
852 { .name = "sx1508q", .driver_data = (kernel_ulong_t)&sx1508q_device_data },
853 { .name = "sx1509q", .driver_data = (kernel_ulong_t)&sx1509q_device_data },
854 { }
855 };
856 MODULE_DEVICE_TABLE(i2c, sx150x_id);
857
858 static const struct of_device_id sx150x_of_match[] = {
859 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
860 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
861 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
862 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
863 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
864 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
865 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
866 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
867 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
868 {},
869 };
870 MODULE_DEVICE_TABLE(of, sx150x_of_match);
871
sx150x_reset(struct sx150x_pinctrl * pctl)872 static int sx150x_reset(struct sx150x_pinctrl *pctl)
873 {
874 int err;
875
876 err = i2c_smbus_write_byte_data(pctl->client,
877 pctl->data->pri.x789.reg_reset,
878 SX150X_789_RESET_KEY1);
879 if (err < 0)
880 return err;
881
882 err = i2c_smbus_write_byte_data(pctl->client,
883 pctl->data->pri.x789.reg_reset,
884 SX150X_789_RESET_KEY2);
885 return err;
886 }
887
sx150x_init_misc(struct sx150x_pinctrl * pctl)888 static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
889 {
890 u8 reg, value;
891
892 switch (pctl->data->model) {
893 case SX150X_789:
894 reg = pctl->data->pri.x789.reg_misc;
895 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
896 break;
897 case SX150X_456:
898 reg = pctl->data->pri.x456.reg_advanced;
899 value = 0x00;
900
901 /*
902 * Only SX1506 has RegAdvanced, SX1504/5 are expected
903 * to initialize this offset to zero
904 */
905 if (!reg)
906 return 0;
907 break;
908 case SX150X_123:
909 reg = pctl->data->pri.x123.reg_advanced;
910 value = 0x00;
911 break;
912 default:
913 WARN(1, "Unknown chip model %d\n", pctl->data->model);
914 return -EINVAL;
915 }
916
917 return regmap_write(pctl->regmap, reg, value);
918 }
919
sx150x_init_hw(struct sx150x_pinctrl * pctl)920 static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
921 {
922 const u8 reg[] = {
923 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
924 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
925 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
926 };
927 int err;
928
929 if (pctl->data->model == SX150X_789 &&
930 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
931 err = sx150x_reset(pctl);
932 if (err < 0)
933 return err;
934 }
935
936 err = sx150x_init_misc(pctl);
937 if (err < 0)
938 return err;
939
940 /* Set all pins to work in normal mode */
941 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
942 }
943
sx150x_regmap_reg_width(struct sx150x_pinctrl * pctl,unsigned int reg)944 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
945 unsigned int reg)
946 {
947 const struct sx150x_device_data *data = pctl->data;
948
949 if (reg == data->reg_sense) {
950 /*
951 * RegSense packs two bits of configuration per GPIO,
952 * so we'd need to read twice as many bits as there
953 * are GPIO in our chip
954 */
955 return 2 * data->ngpios;
956 } else if ((data->model == SX150X_789 &&
957 (reg == data->pri.x789.reg_misc ||
958 reg == data->pri.x789.reg_clock ||
959 reg == data->pri.x789.reg_reset))
960 ||
961 (data->model == SX150X_123 &&
962 reg == data->pri.x123.reg_advanced)
963 ||
964 (data->model == SX150X_456 &&
965 data->pri.x456.reg_advanced &&
966 reg == data->pri.x456.reg_advanced)) {
967 return 8;
968 } else {
969 return data->ngpios;
970 }
971 }
972
sx150x_maybe_swizzle(struct sx150x_pinctrl * pctl,unsigned int reg,unsigned int val)973 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
974 unsigned int reg, unsigned int val)
975 {
976 unsigned int a, b;
977 const struct sx150x_device_data *data = pctl->data;
978
979 /*
980 * Whereas SX1509 presents RegSense in a simple layout as such:
981 * reg [ f f e e d d c c ]
982 * reg + 1 [ b b a a 9 9 8 8 ]
983 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
984 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
985 *
986 * SX1503 and SX1506 deviate from that data layout, instead storing
987 * their contents as follows:
988 *
989 * reg [ f f e e d d c c ]
990 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
991 * reg + 2 [ b b a a 9 9 8 8 ]
992 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
993 *
994 * so, taking that into account, we swap two
995 * inner bytes of a 4-byte result
996 */
997
998 if (reg == data->reg_sense &&
999 data->ngpios == 16 &&
1000 (data->model == SX150X_123 ||
1001 data->model == SX150X_456)) {
1002 a = val & 0x00ff0000;
1003 b = val & 0x0000ff00;
1004
1005 val &= 0xff0000ff;
1006 val |= b << 8;
1007 val |= a >> 8;
1008 }
1009
1010 return val;
1011 }
1012
1013 /*
1014 * In order to mask the differences between 16 and 8 bit expander
1015 * devices we set up a sligthly ficticious regmap that pretends to be
1016 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
1017 * pair/quartet) registers and transparently reconstructs those
1018 * registers via multiple I2C/SMBus reads
1019 *
1020 * This way the rest of the driver code, interfacing with the chip via
1021 * regmap API, can work assuming that each GPIO pin is represented by
1022 * a group of bits at an offset proportional to GPIO number within a
1023 * given register.
1024 */
sx150x_regmap_reg_read(void * context,unsigned int reg,unsigned int * result)1025 static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1026 unsigned int *result)
1027 {
1028 int ret, n;
1029 struct sx150x_pinctrl *pctl = context;
1030 struct i2c_client *i2c = pctl->client;
1031 const int width = sx150x_regmap_reg_width(pctl, reg);
1032 unsigned int idx, val;
1033
1034 /*
1035 * There are four potential cases covered by this function:
1036 *
1037 * 1) 8-pin chip, single configuration bit register
1038 *
1039 * This is trivial the code below just needs to read:
1040 * reg [ 7 6 5 4 3 2 1 0 ]
1041 *
1042 * 2) 8-pin chip, double configuration bit register (RegSense)
1043 *
1044 * The read will be done as follows:
1045 * reg [ 7 7 6 6 5 5 4 4 ]
1046 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
1047 *
1048 * 3) 16-pin chip, single configuration bit register
1049 *
1050 * The read will be done as follows:
1051 * reg [ f e d c b a 9 8 ]
1052 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
1053 *
1054 * 4) 16-pin chip, double configuration bit register (RegSense)
1055 *
1056 * The read will be done as follows:
1057 * reg [ f f e e d d c c ]
1058 * reg + 1 [ b b a a 9 9 8 8 ]
1059 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
1060 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
1061 */
1062
1063 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1064 val <<= 8;
1065
1066 ret = i2c_smbus_read_byte_data(i2c, idx);
1067 if (ret < 0)
1068 return ret;
1069
1070 val |= ret;
1071 }
1072
1073 *result = sx150x_maybe_swizzle(pctl, reg, val);
1074
1075 return 0;
1076 }
1077
sx150x_regmap_reg_write(void * context,unsigned int reg,unsigned int val)1078 static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1079 unsigned int val)
1080 {
1081 int ret, n;
1082 struct sx150x_pinctrl *pctl = context;
1083 struct i2c_client *i2c = pctl->client;
1084 const int width = sx150x_regmap_reg_width(pctl, reg);
1085
1086 val = sx150x_maybe_swizzle(pctl, reg, val);
1087
1088 n = (width - 1) & ~7;
1089 do {
1090 const u8 byte = (val >> n) & 0xff;
1091
1092 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1093 if (ret < 0)
1094 return ret;
1095
1096 reg++;
1097 n -= 8;
1098 } while (n >= 0);
1099
1100 return 0;
1101 }
1102
sx150x_reg_volatile(struct device * dev,unsigned int reg)1103 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1104 {
1105 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1106
1107 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1108 }
1109
1110 static const struct regmap_config sx150x_regmap_config = {
1111 .reg_bits = 8,
1112 .val_bits = 32,
1113
1114 .cache_type = REGCACHE_MAPLE,
1115
1116 .reg_read = sx150x_regmap_reg_read,
1117 .reg_write = sx150x_regmap_reg_write,
1118
1119 .max_register = SX150X_MAX_REGISTER,
1120 .volatile_reg = sx150x_reg_volatile,
1121 };
1122
sx150x_probe(struct i2c_client * client)1123 static int sx150x_probe(struct i2c_client *client)
1124 {
1125 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1126 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1127 struct device *dev = &client->dev;
1128 struct sx150x_pinctrl *pctl;
1129 u32 irq_type;
1130 int ret;
1131
1132 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1133 return -ENOSYS;
1134
1135 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1136 if (!pctl)
1137 return -ENOMEM;
1138
1139 i2c_set_clientdata(client, pctl);
1140
1141 pctl->dev = dev;
1142 pctl->client = client;
1143
1144 pctl->data = i2c_get_match_data(client);
1145 if (!pctl->data)
1146 return -EINVAL;
1147
1148 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1149 &sx150x_regmap_config);
1150 if (IS_ERR(pctl->regmap)) {
1151 ret = PTR_ERR(pctl->regmap);
1152 dev_err(dev, "Failed to allocate register map: %d\n",
1153 ret);
1154 return ret;
1155 }
1156
1157 mutex_init(&pctl->lock);
1158
1159 ret = sx150x_init_hw(pctl);
1160 if (ret)
1161 return ret;
1162
1163 /* Pinctrl_desc */
1164 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1165 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1166 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1167 pctl->pinctrl_desc.pins = pctl->data->pins;
1168 pctl->pinctrl_desc.npins = pctl->data->npins;
1169 pctl->pinctrl_desc.owner = THIS_MODULE;
1170
1171 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1172 pctl, &pctl->pctldev);
1173 if (ret) {
1174 dev_err(dev, "Failed to register pinctrl device\n");
1175 return ret;
1176 }
1177
1178 /* Register GPIO controller */
1179 pctl->gpio.base = -1;
1180 pctl->gpio.ngpio = pctl->data->npins;
1181 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1182 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1183 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1184 pctl->gpio.get = sx150x_gpio_get;
1185 pctl->gpio.set = sx150x_gpio_set;
1186 pctl->gpio.set_config = gpiochip_generic_config;
1187 pctl->gpio.parent = dev;
1188 pctl->gpio.can_sleep = true;
1189 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1190 if (!pctl->gpio.label)
1191 return -ENOMEM;
1192
1193 /*
1194 * Setting multiple pins is not safe when all pins are not
1195 * handled by the same regmap register. The oscio pin (present
1196 * on the SX150X_789 chips) lives in its own register, so
1197 * would require locking that is not in place at this time.
1198 */
1199 if (pctl->data->model != SX150X_789)
1200 pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1201
1202 /* Add Interrupt support if an irq is specified */
1203 if (client->irq > 0) {
1204 struct gpio_irq_chip *girq;
1205
1206 pctl->irq.masked = ~0;
1207 pctl->irq.sense = 0;
1208 /*
1209 * Because sx150x_irq_threaded_fn invokes all of the
1210 * nested interrupt handlers via handle_nested_irq,
1211 * any "handler" assigned to struct gpio_irq_chip
1212 * below is going to be ignored, so the choice of the
1213 * function does not matter that much.
1214 *
1215 * We set it to handle_bad_irq to avoid confusion,
1216 * plus it will be instantly noticeable if it is ever
1217 * called (should not happen)
1218 */
1219 girq = &pctl->gpio.irq;
1220 gpio_irq_chip_set_chip(girq, &sx150x_irq_chip);
1221 /* This will let us handle the parent IRQ in the driver */
1222 girq->parent_handler = NULL;
1223 girq->num_parents = 0;
1224 girq->parents = NULL;
1225 girq->default_type = IRQ_TYPE_NONE;
1226 girq->handler = handle_bad_irq;
1227 girq->threaded = true;
1228
1229 irq_type = irq_get_trigger_type(client->irq);
1230 switch (irq_type) {
1231 case IRQF_TRIGGER_FALLING:
1232 case IRQF_TRIGGER_LOW:
1233 break;
1234 case IRQF_TRIGGER_NONE:
1235 irq_type = IRQF_TRIGGER_FALLING;
1236 break;
1237 default:
1238 return dev_err_probe(dev, -EINVAL,
1239 "unsupported irq trigger type %x\n",
1240 irq_type);
1241 }
1242
1243 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1244 sx150x_irq_thread_fn,
1245 IRQF_ONESHOT | IRQF_SHARED |
1246 irq_type,
1247 client->name, pctl);
1248 if (ret < 0)
1249 return ret;
1250 }
1251
1252 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1253 if (ret)
1254 return ret;
1255
1256 /*
1257 * Pin control functions need to be enabled AFTER registering the
1258 * GPIO chip because sx150x_pinconf_set() calls
1259 * sx150x_gpio_direction_output().
1260 */
1261 ret = pinctrl_enable(pctl->pctldev);
1262 if (ret) {
1263 dev_err(dev, "Failed to enable pinctrl device\n");
1264 return ret;
1265 }
1266
1267 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1268 0, 0, pctl->data->npins);
1269 if (ret)
1270 return ret;
1271
1272 return 0;
1273 }
1274
1275 static struct i2c_driver sx150x_driver = {
1276 .driver = {
1277 .name = "sx150x-pinctrl",
1278 .of_match_table = sx150x_of_match,
1279 },
1280 .probe = sx150x_probe,
1281 .id_table = sx150x_id,
1282 };
1283
sx150x_init(void)1284 static int __init sx150x_init(void)
1285 {
1286 return i2c_add_driver(&sx150x_driver);
1287 }
1288 subsys_initcall(sx150x_init);
1289
1290 MODULE_DESCRIPTION("Semtech SX150x I2C GPIO expander pinctrl driver");
1291 MODULE_LICENSE("GPL");
1292