1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) 29 #define MT7530_STATS_RATE_LIMIT (HZ / 10) 30 31 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 32 { 33 return container_of(pcs, struct mt753x_pcs, pcs); 34 } 35 36 /* String, offset, and register size in bytes if different from 4 bytes */ 37 static const struct mt7530_mib_desc mt7530_mib[] = { 38 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 40 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 44 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 45 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 46 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 47 }; 48 49 static void 50 mt7530_mutex_lock(struct mt7530_priv *priv) 51 { 52 if (priv->bus) 53 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 54 } 55 56 static void 57 mt7530_mutex_unlock(struct mt7530_priv *priv) 58 { 59 if (priv->bus) 60 mutex_unlock(&priv->bus->mdio_lock); 61 } 62 63 static void 64 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 65 { 66 struct mii_bus *bus = priv->bus; 67 int ret; 68 69 mt7530_mutex_lock(priv); 70 71 /* Write the desired MMD Devad */ 72 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 73 MII_MMD_CTRL, MDIO_MMD_VEND2); 74 if (ret < 0) 75 goto err; 76 77 /* Write the desired MMD register address */ 78 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 79 MII_MMD_DATA, reg); 80 if (ret < 0) 81 goto err; 82 83 /* Select the Function : DATA with no post increment */ 84 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 86 if (ret < 0) 87 goto err; 88 89 /* Write the data into MMD's selected register */ 90 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 91 MII_MMD_DATA, val); 92 err: 93 if (ret < 0) 94 dev_err(&bus->dev, "failed to write mmd register\n"); 95 96 mt7530_mutex_unlock(priv); 97 } 98 99 static void 100 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 101 { 102 struct mii_bus *bus = priv->bus; 103 u32 val; 104 int ret; 105 106 mt7530_mutex_lock(priv); 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 110 MII_MMD_CTRL, MDIO_MMD_VEND2); 111 if (ret < 0) 112 goto err; 113 114 /* Write the desired MMD register address */ 115 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 116 MII_MMD_DATA, reg); 117 if (ret < 0) 118 goto err; 119 120 /* Select the Function : DATA with no post increment */ 121 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 123 if (ret < 0) 124 goto err; 125 126 /* Read the content of the MMD's selected register */ 127 ret = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 128 MII_MMD_DATA); 129 if (ret < 0) 130 goto err; 131 val = ret; 132 133 val &= ~mask; 134 val |= set; 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 137 MII_MMD_DATA, val); 138 err: 139 if (ret < 0) 140 dev_err(&bus->dev, "failed to write mmd register\n"); 141 142 mt7530_mutex_unlock(priv); 143 } 144 145 static void 146 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 147 { 148 core_rmw(priv, reg, 0, val); 149 } 150 151 static void 152 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 153 { 154 core_rmw(priv, reg, val, 0); 155 } 156 157 static int 158 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 159 { 160 u32 val; 161 int ret; 162 163 /* Set the command operating upon the MAC address entries */ 164 val = ATC_BUSY | ATC_MAT(0) | cmd; 165 ret = regmap_write(priv->regmap, MT7530_ATC, val); 166 if (ret) 167 return ret; 168 169 ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, 170 !(val & ATC_BUSY), 20, 20000); 171 if (!ret) 172 ret = regmap_read(priv->regmap, MT7530_ATC, &val); 173 174 if (ret < 0) { 175 dev_err(priv->dev, "reset timeout\n"); 176 return ret; 177 } 178 179 /* Additional sanity for read command if the specified 180 * entry is invalid 181 */ 182 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 183 return -EINVAL; 184 185 if (rsp) 186 *rsp = val; 187 188 return 0; 189 } 190 191 static void mt7530_port_fast_age(struct dsa_switch *ds, int port) 192 { 193 struct mt7530_priv *priv = ds->priv; 194 u32 val; 195 int ret; 196 197 mutex_lock(&priv->reg_mutex); 198 199 /* Flush all non-static MAC address entries */ 200 val = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH; 201 ret = regmap_write(priv->regmap, MT7530_ATC, val); 202 if (!ret) 203 ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, 204 !(val & ATC_BUSY), 20, 20000); 205 if (ret < 0) 206 dev_err(priv->dev, "fast age failed: %d\n", ret); 207 208 mutex_unlock(&priv->reg_mutex); 209 } 210 211 static void 212 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 213 { 214 u32 reg[3]; 215 int i; 216 217 /* Read from ARL table into an array */ 218 for (i = 0; i < 3; i++) { 219 regmap_read(priv->regmap, MT7530_TSRA1 + (i * 4), 220 ®[i]); 221 222 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 223 __func__, __LINE__, i, reg[i]); 224 } 225 226 fdb->vid = FIELD_GET(CVID_MASK, reg[1]); 227 fdb->aging = FIELD_GET(AGE_TIMER_MASK, reg[2]); 228 fdb->port_mask = FIELD_GET(PORT_MAP_MASK, reg[2]); 229 fdb->mac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]); 230 fdb->mac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]); 231 fdb->mac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]); 232 fdb->mac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]); 233 fdb->mac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]); 234 fdb->mac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]); 235 fdb->noarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT; 236 } 237 238 static void 239 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 240 u8 port_mask, const u8 *mac, 241 u8 aging, u8 type) 242 { 243 u32 reg[3] = { 0 }; 244 int i; 245 246 reg[1] |= FIELD_PREP(CVID_MASK, vid); 247 reg[1] |= ATA2_IVL; 248 reg[1] |= ATA2_FID(FID_BRIDGED); 249 reg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging); 250 reg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask); 251 /* STATIC_ENT indicate that entry is static wouldn't 252 * be aged out and STATIC_EMP specified as erasing an 253 * entry 254 */ 255 reg[2] |= FIELD_PREP(ENT_STATUS_MASK, type); 256 reg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]); 257 reg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]); 258 reg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]); 259 reg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]); 260 reg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]); 261 reg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]); 262 263 /* Write array into the ARL table */ 264 for (i = 0; i < 3; i++) 265 regmap_write(priv->regmap, MT7530_ATA1 + (i * 4), reg[i]); 266 } 267 268 /* Set up switch core clock for MT7530 */ 269 static void mt7530_pll_setup(struct mt7530_priv *priv) 270 { 271 /* Disable core clock */ 272 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 273 274 /* Disable PLL */ 275 core_write(priv, CORE_GSWPLL_GRP1, 0); 276 277 /* Set core clock into 500Mhz */ 278 core_write(priv, CORE_GSWPLL_GRP2, 279 RG_GSWPLL_POSDIV_500M(1) | 280 RG_GSWPLL_FBKDIV_500M(25)); 281 282 /* Enable PLL */ 283 core_write(priv, CORE_GSWPLL_GRP1, 284 RG_GSWPLL_EN_PRE | 285 RG_GSWPLL_POSDIV_200M(2) | 286 RG_GSWPLL_FBKDIV_200M(32)); 287 288 udelay(20); 289 290 /* Enable core clock */ 291 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 292 } 293 294 /* If port 6 is available as a CPU port, always prefer that as the default, 295 * otherwise don't care. 296 */ 297 static struct dsa_port * 298 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 299 { 300 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 301 302 if (dsa_port_is_cpu(cpu_dp)) 303 return cpu_dp; 304 305 return NULL; 306 } 307 308 /* Setup port 6 interface mode and TRGMII TX circuit */ 309 static void 310 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 311 { 312 struct mt7530_priv *priv = ds->priv; 313 u32 ncpo1, ssc_delta, xtal; 314 315 /* Disable the MT7530 TRGMII clocks */ 316 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 317 318 if (interface == PHY_INTERFACE_MODE_RGMII) { 319 regmap_update_bits(priv->regmap, MT7530_P6ECR, 320 P6_INTF_MODE_MASK, P6_INTF_MODE(0)); 321 return; 322 } 323 324 regmap_update_bits(priv->regmap, MT7530_P6ECR, P6_INTF_MODE_MASK, 325 P6_INTF_MODE(1)); 326 327 regmap_read(priv->regmap, MT753X_MTRAP, &xtal); 328 xtal &= MT7530_XTAL_MASK; 329 330 if (xtal == MT7530_XTAL_25MHZ) 331 ssc_delta = 0x57; 332 else 333 ssc_delta = 0x87; 334 335 if (priv->id == ID_MT7621) { 336 /* PLL frequency: 125MHz: 1.0GBit */ 337 if (xtal == MT7530_XTAL_40MHZ) 338 ncpo1 = 0x0640; 339 if (xtal == MT7530_XTAL_25MHZ) 340 ncpo1 = 0x0a00; 341 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 342 if (xtal == MT7530_XTAL_40MHZ) 343 ncpo1 = 0x0c80; 344 if (xtal == MT7530_XTAL_25MHZ) 345 ncpo1 = 0x1400; 346 } 347 348 /* Setup the MT7530 TRGMII Tx Clock */ 349 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 350 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 351 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 352 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 353 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 354 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 355 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 356 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 357 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 358 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 359 360 /* Enable the MT7530 TRGMII clocks */ 361 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 362 } 363 364 static void 365 mt7531_pll_setup(struct mt7530_priv *priv) 366 { 367 enum mt7531_xtal_fsel xtal; 368 u32 top_sig; 369 u32 hwstrap; 370 u32 val; 371 372 regmap_read(priv->regmap, MT7531_CREV, &val); 373 regmap_read(priv->regmap, MT7531_TOP_SIG_SR, &top_sig); 374 regmap_read(priv->regmap, MT753X_TRAP, &hwstrap); 375 if ((val & CHIP_REV_M) > 0) 376 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 377 MT7531_XTAL_FSEL_25MHZ; 378 else 379 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 380 MT7531_XTAL_FSEL_40MHZ; 381 382 /* Step 1 : Disable MT7531 COREPLL */ 383 regmap_read(priv->regmap, MT7531_PLLGP_EN, &val); 384 val &= ~EN_COREPLL; 385 regmap_write(priv->regmap, MT7531_PLLGP_EN, val); 386 387 /* Step 2: switch to XTAL output */ 388 regmap_read(priv->regmap, MT7531_PLLGP_EN, &val); 389 val |= SW_CLKSW; 390 regmap_write(priv->regmap, MT7531_PLLGP_EN, val); 391 392 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 393 val &= ~RG_COREPLL_EN; 394 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 395 396 /* Step 3: disable PLLGP and enable program PLLGP */ 397 regmap_read(priv->regmap, MT7531_PLLGP_EN, &val); 398 val |= SW_PLLGP; 399 regmap_write(priv->regmap, MT7531_PLLGP_EN, val); 400 401 /* Step 4: program COREPLL output frequency to 500MHz */ 402 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 403 val &= ~RG_COREPLL_POSDIV_MASK; 404 val |= RG_COREPLL_POSDIV(2); 405 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 406 usleep_range(25, 35); 407 408 switch (xtal) { 409 case MT7531_XTAL_FSEL_25MHZ: 410 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 411 val &= ~RG_COREPLL_SDM_PCW_MASK; 412 val |= RG_COREPLL_SDM_PCW(0x140000); 413 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 414 break; 415 case MT7531_XTAL_FSEL_40MHZ: 416 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 417 val &= ~RG_COREPLL_SDM_PCW_MASK; 418 val |= RG_COREPLL_SDM_PCW(0x190000); 419 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 420 break; 421 } 422 423 /* Set feedback divide ratio update signal to high */ 424 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 425 val |= RG_COREPLL_SDM_PCW_CHG; 426 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 427 /* Wait for at least 16 XTAL clocks */ 428 usleep_range(10, 20); 429 430 /* Step 5: set feedback divide ratio update signal to low */ 431 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 432 val &= ~RG_COREPLL_SDM_PCW_CHG; 433 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 434 435 /* Enable 325M clock for SGMII */ 436 regmap_write(priv->regmap, MT7531_ANA_PLLGP_CR5, 0xad0000); 437 438 /* Enable 250SSC clock for RGMII */ 439 regmap_write(priv->regmap, MT7531_ANA_PLLGP_CR2, 0x4f40000); 440 441 /* Step 6: Enable MT7531 PLL */ 442 regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val); 443 val |= RG_COREPLL_EN; 444 regmap_write(priv->regmap, MT7531_PLLGP_CR0, val); 445 446 regmap_read(priv->regmap, MT7531_PLLGP_EN, &val); 447 val |= EN_COREPLL; 448 regmap_write(priv->regmap, MT7531_PLLGP_EN, val); 449 usleep_range(25, 35); 450 } 451 452 static void 453 mt7530_mib_reset(struct dsa_switch *ds) 454 { 455 struct mt7530_priv *priv = ds->priv; 456 457 regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH); 458 regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 459 } 460 461 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 462 { 463 return mdiobus_read_nested(priv->bus, port, regnum); 464 } 465 466 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 467 u16 val) 468 { 469 return mdiobus_write_nested(priv->bus, port, regnum, val); 470 } 471 472 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 473 int devad, int regnum) 474 { 475 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 476 } 477 478 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 479 int regnum, u16 val) 480 { 481 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 482 } 483 484 static int 485 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 486 int regnum) 487 { 488 u32 reg, val; 489 int ret; 490 491 mutex_lock(&priv->reg_mutex); 492 493 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 494 !(val & MT7531_PHY_ACS_ST), 20, 100000); 495 if (ret < 0) { 496 dev_err(priv->dev, "poll timeout\n"); 497 goto out; 498 } 499 500 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 501 MT7531_MDIO_DEV_ADDR(devad) | regnum; 502 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 503 reg | MT7531_PHY_ACS_ST); 504 if (ret < 0) 505 goto out; 506 507 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 508 !(val & MT7531_PHY_ACS_ST), 20, 100000); 509 if (ret < 0) { 510 dev_err(priv->dev, "poll timeout\n"); 511 goto out; 512 } 513 514 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 515 MT7531_MDIO_DEV_ADDR(devad); 516 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 517 reg | MT7531_PHY_ACS_ST); 518 if (ret < 0) 519 goto out; 520 521 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 522 !(val & MT7531_PHY_ACS_ST), 20, 100000); 523 if (ret < 0) { 524 dev_err(priv->dev, "poll timeout\n"); 525 goto out; 526 } 527 528 ret = val & MT7531_MDIO_RW_DATA_MASK; 529 out: 530 mutex_unlock(&priv->reg_mutex); 531 532 return ret; 533 } 534 535 static int 536 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 537 int regnum, u16 data) 538 { 539 u32 val, reg; 540 int ret; 541 542 mutex_lock(&priv->reg_mutex); 543 544 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 545 !(val & MT7531_PHY_ACS_ST), 20, 100000); 546 if (ret < 0) { 547 dev_err(priv->dev, "poll timeout\n"); 548 goto out; 549 } 550 551 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 552 MT7531_MDIO_DEV_ADDR(devad) | regnum; 553 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 554 reg | MT7531_PHY_ACS_ST); 555 if (ret < 0) 556 goto out; 557 558 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 559 !(val & MT7531_PHY_ACS_ST), 20, 100000); 560 if (ret < 0) { 561 dev_err(priv->dev, "poll timeout\n"); 562 goto out; 563 } 564 565 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 566 MT7531_MDIO_DEV_ADDR(devad) | data; 567 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 568 reg | MT7531_PHY_ACS_ST); 569 if (ret < 0) 570 goto out; 571 572 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 573 !(val & MT7531_PHY_ACS_ST), 20, 100000); 574 if (ret < 0) { 575 dev_err(priv->dev, "poll timeout\n"); 576 goto out; 577 } 578 579 out: 580 mutex_unlock(&priv->reg_mutex); 581 582 return ret; 583 } 584 585 static int 586 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 587 { 588 int ret; 589 u32 val; 590 591 mutex_lock(&priv->reg_mutex); 592 593 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 594 !(val & MT7531_PHY_ACS_ST), 20, 100000); 595 if (ret < 0) { 596 dev_err(priv->dev, "poll timeout\n"); 597 goto out; 598 } 599 600 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 601 MT7531_MDIO_REG_ADDR(regnum); 602 603 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 604 val | MT7531_PHY_ACS_ST); 605 if (ret < 0) 606 goto out; 607 608 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 609 !(val & MT7531_PHY_ACS_ST), 20, 100000); 610 if (ret < 0) { 611 dev_err(priv->dev, "poll timeout\n"); 612 goto out; 613 } 614 615 ret = val & MT7531_MDIO_RW_DATA_MASK; 616 out: 617 mutex_unlock(&priv->reg_mutex); 618 619 return ret; 620 } 621 622 static int 623 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 624 u16 data) 625 { 626 int ret; 627 u32 reg; 628 629 mutex_lock(&priv->reg_mutex); 630 631 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 632 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 633 if (ret < 0) { 634 dev_err(priv->dev, "poll timeout\n"); 635 goto out; 636 } 637 638 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 639 MT7531_MDIO_REG_ADDR(regnum) | data; 640 641 ret = regmap_write(priv->regmap, MT7531_PHY_IAC, 642 reg | MT7531_PHY_ACS_ST); 643 if (ret < 0) 644 goto out; 645 646 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 647 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 648 if (ret < 0) { 649 dev_err(priv->dev, "poll timeout\n"); 650 goto out; 651 } 652 653 out: 654 mutex_unlock(&priv->reg_mutex); 655 656 return ret; 657 } 658 659 static int 660 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 661 { 662 struct mt7530_priv *priv = bus->priv; 663 664 return priv->info->phy_read_c22(priv, port, regnum); 665 } 666 667 static int 668 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 669 { 670 struct mt7530_priv *priv = bus->priv; 671 672 return priv->info->phy_read_c45(priv, port, devad, regnum); 673 } 674 675 static int 676 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 677 { 678 struct mt7530_priv *priv = bus->priv; 679 680 return priv->info->phy_write_c22(priv, port, regnum, val); 681 } 682 683 static int 684 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 685 u16 val) 686 { 687 struct mt7530_priv *priv = bus->priv; 688 689 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 690 } 691 692 static void 693 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 694 uint8_t *data) 695 { 696 int i; 697 698 if (stringset != ETH_SS_STATS) 699 return; 700 701 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 702 ethtool_puts(&data, mt7530_mib[i].name); 703 } 704 705 static void 706 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 707 u32 offset, u8 size, uint64_t *data) 708 { 709 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 710 711 regmap_read(priv->regmap, reg, &val); 712 *data = val; 713 714 if (size == 2) { 715 regmap_read(priv->regmap, reg + 4, &val); 716 *data |= (u64)val << 32; 717 } 718 } 719 720 static void 721 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 722 uint64_t *data) 723 { 724 struct mt7530_priv *priv = ds->priv; 725 const struct mt7530_mib_desc *mib; 726 int i; 727 728 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 729 mib = &mt7530_mib[i]; 730 731 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 732 data + i); 733 } 734 } 735 736 static int 737 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 738 { 739 if (sset != ETH_SS_STATS) 740 return 0; 741 742 return ARRAY_SIZE(mt7530_mib); 743 } 744 745 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 746 struct ethtool_eth_mac_stats *mac_stats) 747 { 748 struct mt7530_priv *priv = ds->priv; 749 750 /* MIB counter doesn't provide a FramesTransmittedOK but instead 751 * provide stats for Unicast, Broadcast and Multicast frames separately. 752 * To simulate a global frame counter, read Unicast and addition Multicast 753 * and Broadcast later 754 */ 755 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 756 &mac_stats->FramesTransmittedOK); 757 758 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 759 &mac_stats->SingleCollisionFrames); 760 761 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 762 &mac_stats->MultipleCollisionFrames); 763 764 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 765 &mac_stats->FramesReceivedOK); 766 767 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 768 &mac_stats->OctetsTransmittedOK); 769 770 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 771 &mac_stats->AlignmentErrors); 772 773 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 774 &mac_stats->FramesWithDeferredXmissions); 775 776 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 777 &mac_stats->LateCollisions); 778 779 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 780 &mac_stats->FramesAbortedDueToXSColls); 781 782 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 783 &mac_stats->OctetsReceivedOK); 784 785 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 786 &mac_stats->MulticastFramesXmittedOK); 787 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 788 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 789 &mac_stats->BroadcastFramesXmittedOK); 790 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 791 792 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 793 &mac_stats->MulticastFramesReceivedOK); 794 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 795 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 796 &mac_stats->BroadcastFramesReceivedOK); 797 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 798 } 799 800 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 801 { 0, 64 }, 802 { 65, 127 }, 803 { 128, 255 }, 804 { 256, 511 }, 805 { 512, 1023 }, 806 { 1024, MT7530_MAX_MTU }, 807 {} 808 }; 809 810 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 811 struct ethtool_rmon_stats *rmon_stats, 812 const struct ethtool_rmon_hist_range **ranges) 813 { 814 struct mt7530_priv *priv = ds->priv; 815 816 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 817 &rmon_stats->undersize_pkts); 818 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 819 &rmon_stats->oversize_pkts); 820 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 821 &rmon_stats->fragments); 822 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 823 &rmon_stats->jabbers); 824 825 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 826 &rmon_stats->hist[0]); 827 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 828 &rmon_stats->hist[1]); 829 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 830 &rmon_stats->hist[2]); 831 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 832 &rmon_stats->hist[3]); 833 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 834 &rmon_stats->hist[4]); 835 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 836 &rmon_stats->hist[5]); 837 838 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 839 &rmon_stats->hist_tx[0]); 840 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 841 &rmon_stats->hist_tx[1]); 842 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 843 &rmon_stats->hist_tx[2]); 844 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 845 &rmon_stats->hist_tx[3]); 846 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 847 &rmon_stats->hist_tx[4]); 848 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 849 &rmon_stats->hist_tx[5]); 850 851 *ranges = mt7530_rmon_ranges; 852 } 853 854 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, 855 struct rtnl_link_stats64 *storage) 856 { 857 uint64_t data; 858 859 /* MIB counter doesn't provide a FramesTransmittedOK but instead 860 * provide stats for Unicast, Broadcast and Multicast frames separately. 861 * To simulate a global frame counter, read Unicast and addition Multicast 862 * and Broadcast later 863 */ 864 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 865 &storage->rx_packets); 866 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 867 &storage->multicast); 868 storage->rx_packets += storage->multicast; 869 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 870 &data); 871 storage->rx_packets += data; 872 873 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 874 &storage->tx_packets); 875 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 876 &data); 877 storage->tx_packets += data; 878 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 879 &data); 880 storage->tx_packets += data; 881 882 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 883 &storage->rx_bytes); 884 885 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 886 &storage->tx_bytes); 887 888 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 889 &storage->rx_dropped); 890 891 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 892 &storage->tx_dropped); 893 894 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 895 &storage->rx_crc_errors); 896 } 897 898 static void mt7530_stats_refresh(struct mt7530_priv *priv) 899 { 900 struct rtnl_link_stats64 stats = {}; 901 struct dsa_port *dp; 902 int port; 903 904 dsa_switch_for_each_user_port(dp, priv->ds) { 905 port = dp->index; 906 907 mt7530_read_port_stats64(priv, port, &stats); 908 909 spin_lock_bh(&priv->stats_lock); 910 priv->ports[port].stats = stats; 911 priv->stats_last = jiffies; 912 spin_unlock_bh(&priv->stats_lock); 913 } 914 } 915 916 static void mt7530_stats_poll(struct work_struct *work) 917 { 918 struct mt7530_priv *priv = container_of(work, struct mt7530_priv, 919 stats_work.work); 920 921 mt7530_stats_refresh(priv); 922 schedule_delayed_work(&priv->stats_work, 923 MT7530_STATS_POLL_INTERVAL); 924 } 925 926 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 927 struct rtnl_link_stats64 *storage) 928 { 929 struct mt7530_priv *priv = ds->priv; 930 bool refresh; 931 932 if (priv->bus) { 933 spin_lock_bh(&priv->stats_lock); 934 *storage = priv->ports[port].stats; 935 refresh = time_after(jiffies, priv->stats_last + 936 MT7530_STATS_RATE_LIMIT); 937 spin_unlock_bh(&priv->stats_lock); 938 if (refresh) 939 mod_delayed_work(system_percpu_wq, 940 &priv->stats_work, 0); 941 } else { 942 mt7530_read_port_stats64(priv, port, storage); 943 } 944 } 945 946 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 947 struct ethtool_eth_ctrl_stats *ctrl_stats) 948 { 949 struct mt7530_priv *priv = ds->priv; 950 951 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 952 &ctrl_stats->MACControlFramesTransmitted); 953 954 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 955 &ctrl_stats->MACControlFramesReceived); 956 } 957 958 static int 959 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 960 { 961 struct mt7530_priv *priv = ds->priv; 962 unsigned int secs = msecs / 1000; 963 unsigned int tmp_age_count; 964 unsigned int error = -1; 965 unsigned int age_count; 966 unsigned int age_unit; 967 968 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds. 969 * The DSA core has already validated the range using 970 * ds->ageing_time_min and ds->ageing_time_max. 971 * 972 * Iterate through all possible age_count values to find the closest 973 * pair. Start from 1 because the per-entry aging counter is 974 * initialized to AGE_CNT and a value of 0 means the entry will 975 * never be aged out. 976 */ 977 for (tmp_age_count = 1; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 978 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 979 980 if (tmp_age_unit <= AGE_UNIT_MAX) { 981 unsigned int tmp_error = secs - 982 (tmp_age_count + 1) * (tmp_age_unit + 1); 983 984 /* found a closer pair */ 985 if (error > tmp_error) { 986 error = tmp_error; 987 age_count = tmp_age_count; 988 age_unit = tmp_age_unit; 989 } 990 991 /* found the exact match, so break the loop */ 992 if (!error) 993 break; 994 } 995 } 996 997 regmap_write(priv->regmap, MT7530_AAC, 998 AGE_CNT(age_count) | AGE_UNIT(age_unit)); 999 1000 return 0; 1001 } 1002 1003 static const char *mt7530_p5_mode_str(unsigned int mode) 1004 { 1005 switch (mode) { 1006 case MUX_PHY_P0: 1007 return "MUX PHY P0"; 1008 case MUX_PHY_P4: 1009 return "MUX PHY P4"; 1010 default: 1011 return "GMAC5"; 1012 } 1013 } 1014 1015 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1016 { 1017 struct mt7530_priv *priv = ds->priv; 1018 u8 tx_delay = 0; 1019 u32 val; 1020 1021 mutex_lock(&priv->reg_mutex); 1022 1023 regmap_read(priv->regmap, MT753X_MTRAP, &val); 1024 1025 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1026 1027 switch (priv->p5_mode) { 1028 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1029 case MUX_PHY_P0: 1030 val |= MT7530_P5_PHY0_SEL; 1031 fallthrough; 1032 1033 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1034 case MUX_PHY_P4: 1035 /* Setup the MAC by default for the cpu port */ 1036 regmap_write(priv->regmap, MT753X_PMCR_P(5), 0x56300); 1037 break; 1038 1039 /* GMAC5: P5 -> SoC MAC or external PHY */ 1040 default: 1041 val |= MT7530_P5_MAC_SEL; 1042 break; 1043 } 1044 1045 /* Setup RGMII settings */ 1046 if (phy_interface_mode_is_rgmii(interface)) { 1047 val |= MT7530_P5_RGMII_MODE; 1048 1049 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1050 regmap_write(priv->regmap, MT7530_P5RGMIIRXCR, 1051 CSR_RGMII_EDGE_ALIGN); 1052 1053 /* Don't set delay in DSA mode */ 1054 if (!dsa_is_dsa_port(priv->ds, 5) && 1055 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1056 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1057 tx_delay = 4; /* n * 0.5 ns */ 1058 1059 /* P5 RGMII TX Clock Control: delay x */ 1060 regmap_write(priv->regmap, MT7530_P5RGMIITXCR, 1061 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1062 1063 /* reduce P5 RGMII Tx driving, 8mA */ 1064 regmap_write(priv->regmap, MT7530_IO_DRV_CR, 1065 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1066 } 1067 1068 regmap_write(priv->regmap, MT753X_MTRAP, val); 1069 1070 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1071 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1072 1073 mutex_unlock(&priv->reg_mutex); 1074 } 1075 1076 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1077 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1078 * described; the medium access control (MAC) and logical link control (LLC) 1079 * sublayers. The MAC sublayer is the one facing the physical layer. 1080 * 1081 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1082 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1083 * of the Bridge, at least two Ports, and higher layer entities with at least a 1084 * Spanning Tree Protocol Entity included. 1085 * 1086 * Each Bridge Port also functions as an end station and shall provide the MAC 1087 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1088 * distinct LLC Entity that supports protocol identification, multiplexing, and 1089 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1090 * one or more higher layer entities. 1091 * 1092 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1093 * Entity associated with each Bridge Port is modeled as being directly 1094 * connected to the attached Local Area Network (LAN). 1095 * 1096 * On the switch with CPU port architecture, CPU port functions as Management 1097 * Port, and the Management Port functionality is provided by software which 1098 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1099 * wholly contained within the system that incorporates the Bridge. Software 1100 * provides access to the LLC Entity associated with each Bridge Port by the 1101 * value of the source port field on the special tag on the frame received by 1102 * software. 1103 * 1104 * We call frames that carry control information to determine the active 1105 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1106 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1107 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1108 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1109 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1110 * forwarded by a Bridge. Permanently configured entries in the filtering 1111 * database (FDB) ensure that such frames are discarded by the Forwarding 1112 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1113 * 1114 * Each of the reserved MAC addresses specified in Table 8-1 1115 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1116 * permanently configured in the FDB in C-VLAN components and ERs. 1117 * 1118 * Each of the reserved MAC addresses specified in Table 8-2 1119 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1120 * configured in the FDB in S-VLAN components. 1121 * 1122 * Each of the reserved MAC addresses specified in Table 8-3 1123 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1124 * TPMR components. 1125 * 1126 * The FDB entries for reserved MAC addresses shall specify filtering for all 1127 * Bridge Ports and all VIDs. Management shall not provide the capability to 1128 * modify or remove entries for reserved MAC addresses. 1129 * 1130 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1131 * propagation of PDUs within a Bridged Network, as follows: 1132 * 1133 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1134 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1135 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1136 * PDUs transmitted using this destination address, or any other addresses 1137 * that appear in Table 8-1, Table 8-2, and Table 8-3 1138 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1139 * therefore travel no further than those stations that can be reached via a 1140 * single individual LAN from the originating station. 1141 * 1142 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1143 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1144 * Bridge can forward; however, this address is relayed by a TPMR component. 1145 * PDUs using this destination address, or any of the other addresses that 1146 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1147 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1148 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1149 * C-VLAN component, or MAC Bridge. 1150 * 1151 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1152 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1153 * relayed by TPMR components and S-VLAN components. PDUs using this 1154 * destination address, or any of the other addresses that appear in Table 8-1 1155 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1156 * will be relayed by TPMR components and S-VLAN components but will propagate 1157 * no further than the nearest C-VLAN component or MAC Bridge. 1158 * 1159 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1160 * port, we must not filter these frames but forward them to CPU port. 1161 * 1162 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1163 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1164 * For link-local frames, only CPU port should be designated as destination port 1165 * in the FDB, and the other functions of the Forwarding Process must not 1166 * interfere with the decision of the transmission Port. We call this process 1167 * trapping frames to CPU port. 1168 * 1169 * Therefore, on the switch with CPU port architecture, link-local frames must 1170 * be trapped to CPU port, and certain link-local frames received by a Port of a 1171 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1172 * from it. 1173 * 1174 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1175 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1176 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1177 * doesn't count) of this architecture will either function as a standard MAC 1178 * Bridge or a standard VLAN Bridge. 1179 * 1180 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1181 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1182 * we don't need to relay PDUs using the destination addresses specified on the 1183 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1184 * section where they must be relayed by TPMR components. 1185 * 1186 * One option to trap link-local frames to CPU port is to add static FDB entries 1187 * with CPU port designated as destination port. However, because that 1188 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1189 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1190 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1191 * entries. This switch intellectual property can only hold a maximum of 2048 1192 * entries. Using this option, there also isn't a mechanism to prevent 1193 * link-local frames from being discarded when the spanning tree Port State of 1194 * the reception Port is discarding. 1195 * 1196 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1197 * registers. Whilst this applies to every VID, it doesn't contain all of the 1198 * reserved MAC addresses without affecting the remaining Standard Group MAC 1199 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1200 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1201 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1202 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1203 * The latter option provides better but not complete conformance. 1204 * 1205 * This switch intellectual property also does not provide a mechanism to trap 1206 * link-local frames with specific destination addresses to CPU port by Bridge, 1207 * to conform to the filtering rules for the distinct Bridge components. 1208 * 1209 * Therefore, regardless of the type of the Bridge component, link-local frames 1210 * with these destination addresses will be trapped to CPU port: 1211 * 1212 * 01-80-C2-00-00-[00,01,02,03,0E] 1213 * 1214 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1215 * 1216 * Link-local frames with these destination addresses won't be trapped to CPU 1217 * port which won't conform to IEEE Std 802.1Q-2022: 1218 * 1219 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1220 * 1221 * In a Bridge comprising an S-VLAN component: 1222 * 1223 * Link-local frames with these destination addresses will be trapped to CPU 1224 * port which won't conform to IEEE Std 802.1Q-2022: 1225 * 1226 * 01-80-C2-00-00-00 1227 * 1228 * Link-local frames with these destination addresses won't be trapped to CPU 1229 * port which won't conform to IEEE Std 802.1Q-2022: 1230 * 1231 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1232 * 1233 * To trap link-local frames to CPU port as conformant as this switch 1234 * intellectual property can allow, link-local frames are made to be regarded as 1235 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1236 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1237 * State function of the Forwarding Process. 1238 * 1239 * The only remaining interference is the ingress rules. When the reception Port 1240 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1241 * There doesn't seem to be a mechanism on the switch intellectual property to 1242 * have link-local frames bypass this function of the Forwarding Process. 1243 */ 1244 static void 1245 mt753x_trap_frames(struct mt7530_priv *priv) 1246 { 1247 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress 1248 * them with the EG_TAG attribute set to disabled (system default) 1249 * so that any VLAN tags in the frame are not modified by the 1250 * switch egress VLAN tag processing. This preserves VLAN tags 1251 * for reception on VLAN sub-interfaces. 1252 */ 1253 regmap_update_bits(priv->regmap, MT753X_BPC, 1254 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1255 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1256 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1257 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1258 BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1259 TO_CPU_FW_CPU_ONLY); 1260 1261 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and 1262 * egress them with EG_TAG disabled. 1263 */ 1264 regmap_update_bits(priv->regmap, MT753X_RGAC1, 1265 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1266 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1267 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1268 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1269 R01_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1270 TO_CPU_FW_CPU_ONLY); 1271 1272 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and 1273 * egress them with EG_TAG disabled. 1274 */ 1275 regmap_update_bits(priv->regmap, MT753X_RGAC2, 1276 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1277 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1278 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1279 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1280 R03_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1281 TO_CPU_FW_CPU_ONLY); 1282 } 1283 1284 static void 1285 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1286 { 1287 struct mt7530_priv *priv = ds->priv; 1288 1289 /* Enable Mediatek header mode on the cpu port */ 1290 regmap_write(priv->regmap, MT7530_PVC_P(port), PORT_SPEC_TAG); 1291 1292 /* Enable flooding on the CPU port */ 1293 regmap_set_bits(priv->regmap, MT753X_MFC, 1294 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1295 1296 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1297 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1298 * is affine to the inbound user port. 1299 */ 1300 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1301 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1302 regmap_set_bits(priv->regmap, MT7531_CFC, 1303 MT7531_CPU_PMAP(BIT(port))); 1304 1305 /* CPU port gets connected to all user ports of 1306 * the switch. 1307 */ 1308 regmap_write(priv->regmap, MT7530_PCR_P(port), 1309 PCR_MATRIX(dsa_user_ports(priv->ds))); 1310 1311 /* Set to fallback mode for independent VLAN learning */ 1312 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1313 PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE); 1314 } 1315 1316 static int 1317 mt7530_port_enable(struct dsa_switch *ds, int port, 1318 struct phy_device *phy) 1319 { 1320 struct dsa_port *dp = dsa_to_port(ds, port); 1321 struct mt7530_priv *priv = ds->priv; 1322 1323 mutex_lock(&priv->reg_mutex); 1324 1325 /* Allow the user port gets connected to the cpu port and also 1326 * restore the port matrix if the port is the member of a certain 1327 * bridge. 1328 */ 1329 if (dsa_port_is_user(dp)) { 1330 struct dsa_port *cpu_dp = dp->cpu_dp; 1331 1332 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1333 } 1334 priv->ports[port].enable = true; 1335 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1336 priv->ports[port].pm); 1337 1338 mutex_unlock(&priv->reg_mutex); 1339 1340 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1341 return 0; 1342 1343 if (port == 5) 1344 regmap_clear_bits(priv->regmap, MT753X_MTRAP, MT7530_P5_DIS); 1345 else if (port == 6) 1346 regmap_clear_bits(priv->regmap, MT753X_MTRAP, MT7530_P6_DIS); 1347 1348 return 0; 1349 } 1350 1351 static void 1352 mt7530_port_disable(struct dsa_switch *ds, int port) 1353 { 1354 struct mt7530_priv *priv = ds->priv; 1355 1356 mutex_lock(&priv->reg_mutex); 1357 1358 /* Clear up all port matrix which could be restored in the next 1359 * enablement for the port. 1360 */ 1361 priv->ports[port].enable = false; 1362 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1363 PCR_MATRIX_CLR); 1364 1365 mutex_unlock(&priv->reg_mutex); 1366 1367 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1368 return; 1369 1370 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1371 if (port == 5 && priv->p5_mode == GMAC5) 1372 regmap_set_bits(priv->regmap, MT753X_MTRAP, MT7530_P5_DIS); 1373 else if (port == 6) 1374 regmap_set_bits(priv->regmap, MT753X_MTRAP, MT7530_P6_DIS); 1375 } 1376 1377 static int 1378 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1379 { 1380 struct mt7530_priv *priv = ds->priv; 1381 int length; 1382 u32 val; 1383 1384 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1385 * largest MTU of the user ports. Because the switch only has a global 1386 * RX length register, only allowing CPU port here is enough. 1387 */ 1388 if (!dsa_is_cpu_port(ds, port)) 1389 return 0; 1390 1391 regmap_read(priv->regmap, MT7530_GMACCR, &val); 1392 val &= ~MAX_RX_PKT_LEN_MASK; 1393 1394 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1395 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1396 if (length <= 1522) { 1397 val |= MAX_RX_PKT_LEN_1522; 1398 } else if (length <= 1536) { 1399 val |= MAX_RX_PKT_LEN_1536; 1400 } else if (length <= 1552) { 1401 val |= MAX_RX_PKT_LEN_1552; 1402 } else { 1403 val &= ~MAX_RX_JUMBO_MASK; 1404 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1405 val |= MAX_RX_PKT_LEN_JUMBO; 1406 } 1407 1408 regmap_write(priv->regmap, MT7530_GMACCR, val); 1409 1410 return 0; 1411 } 1412 1413 static int 1414 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1415 { 1416 return MT7530_MAX_MTU; 1417 } 1418 1419 static void 1420 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1421 { 1422 struct mt7530_priv *priv = ds->priv; 1423 u32 stp_state; 1424 1425 switch (state) { 1426 case BR_STATE_DISABLED: 1427 stp_state = MT7530_STP_DISABLED; 1428 break; 1429 case BR_STATE_BLOCKING: 1430 stp_state = MT7530_STP_BLOCKING; 1431 break; 1432 case BR_STATE_LISTENING: 1433 stp_state = MT7530_STP_LISTENING; 1434 break; 1435 case BR_STATE_LEARNING: 1436 stp_state = MT7530_STP_LEARNING; 1437 break; 1438 case BR_STATE_FORWARDING: 1439 default: 1440 stp_state = MT7530_STP_FORWARDING; 1441 break; 1442 } 1443 1444 regmap_update_bits(priv->regmap, MT7530_SSP_P(port), 1445 FID_PST_MASK(FID_BRIDGED), 1446 FID_PST(FID_BRIDGED, stp_state)); 1447 } 1448 1449 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1450 const struct net_device *bridge_dev, 1451 bool join) __must_hold(&priv->reg_mutex) 1452 { 1453 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1454 struct mt7530_port *p = &priv->ports[port], *other_p; 1455 struct dsa_port *cpu_dp = dp->cpu_dp; 1456 u32 port_bitmap = BIT(cpu_dp->index); 1457 int other_port; 1458 bool isolated; 1459 1460 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1461 other_port = other_dp->index; 1462 other_p = &priv->ports[other_port]; 1463 1464 if (dp == other_dp) 1465 continue; 1466 1467 /* Add/remove this port to/from the port matrix of the other 1468 * ports in the same bridge. If the port is disabled, port 1469 * matrix is kept and not being setup until the port becomes 1470 * enabled. 1471 */ 1472 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1473 continue; 1474 1475 isolated = p->isolated && other_p->isolated; 1476 1477 if (join && !isolated) { 1478 other_p->pm |= PCR_MATRIX(BIT(port)); 1479 port_bitmap |= BIT(other_port); 1480 } else { 1481 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1482 } 1483 1484 if (other_p->enable) 1485 regmap_update_bits(priv->regmap, 1486 MT7530_PCR_P(other_port), 1487 PCR_MATRIX_MASK, other_p->pm); 1488 } 1489 1490 /* Add/remove the all other ports to this port matrix. For !join 1491 * (leaving the bridge), only the CPU port will remain in the port matrix 1492 * of this port. 1493 */ 1494 p->pm = PCR_MATRIX(port_bitmap); 1495 if (priv->ports[port].enable) 1496 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1497 PCR_MATRIX_MASK, p->pm); 1498 } 1499 1500 static int 1501 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1502 struct switchdev_brport_flags flags, 1503 struct netlink_ext_ack *extack) 1504 { 1505 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1506 BR_BCAST_FLOOD | BR_ISOLATED)) 1507 return -EINVAL; 1508 1509 return 0; 1510 } 1511 1512 static int 1513 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1514 struct switchdev_brport_flags flags, 1515 struct netlink_ext_ack *extack) 1516 { 1517 struct mt7530_priv *priv = ds->priv; 1518 1519 if (flags.mask & BR_LEARNING) 1520 regmap_update_bits(priv->regmap, MT7530_PSC_P(port), SA_DIS, 1521 flags.val & BR_LEARNING ? 0 : SA_DIS); 1522 1523 if (flags.mask & BR_FLOOD) 1524 regmap_update_bits(priv->regmap, MT753X_MFC, 1525 UNU_FFP(BIT(port)), 1526 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1527 1528 if (flags.mask & BR_MCAST_FLOOD) 1529 regmap_update_bits(priv->regmap, MT753X_MFC, 1530 UNM_FFP(BIT(port)), 1531 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1532 1533 if (flags.mask & BR_BCAST_FLOOD) 1534 regmap_update_bits(priv->regmap, MT753X_MFC, 1535 BC_FFP(BIT(port)), 1536 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1537 1538 if (flags.mask & BR_ISOLATED) { 1539 struct dsa_port *dp = dsa_to_port(ds, port); 1540 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1541 1542 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1543 1544 mutex_lock(&priv->reg_mutex); 1545 mt7530_update_port_member(priv, port, bridge_dev, true); 1546 mutex_unlock(&priv->reg_mutex); 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int 1553 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1554 struct dsa_bridge bridge, bool *tx_fwd_offload, 1555 struct netlink_ext_ack *extack) 1556 { 1557 struct mt7530_priv *priv = ds->priv; 1558 1559 mutex_lock(&priv->reg_mutex); 1560 1561 mt7530_update_port_member(priv, port, bridge.dev, true); 1562 1563 /* Set to fallback mode for independent VLAN learning */ 1564 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1565 PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE); 1566 1567 mutex_unlock(&priv->reg_mutex); 1568 1569 return 0; 1570 } 1571 1572 static int 1573 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1574 { 1575 u32 val; 1576 int ret; 1577 1578 val = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid); 1579 ret = regmap_write(priv->regmap, MT7530_VTCR, val); 1580 if (ret) 1581 return ret; 1582 1583 ret = regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val, 1584 !(val & VTCR_BUSY), 20, 20000); 1585 if (!ret) 1586 ret = regmap_read(priv->regmap, MT7530_VTCR, &val); 1587 1588 if (ret < 0) { 1589 dev_err(priv->dev, "poll timeout\n"); 1590 return ret; 1591 } 1592 1593 if (val & VTCR_INVALID) { 1594 dev_err(priv->dev, "read VTCR invalid\n"); 1595 return -EINVAL; 1596 } 1597 1598 return 0; 1599 } 1600 1601 static int 1602 mt7530_setup_vlan0(struct mt7530_priv *priv) 1603 { 1604 u32 val; 1605 1606 /* Validate the entry with independent learning, keep the original 1607 * ingress tag attribute. 1608 */ 1609 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1610 VLAN_VALID; 1611 regmap_write(priv->regmap, MT7530_VAWD1, val); 1612 regmap_write(priv->regmap, MT7530_VAWD2, 0); 1613 1614 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1615 } 1616 1617 static void 1618 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1619 { 1620 struct mt7530_priv *priv = ds->priv; 1621 bool all_user_ports_removed = true; 1622 int i; 1623 1624 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1625 * bridge. Don't set standalone ports to fallback mode. 1626 */ 1627 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1628 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1629 PCR_PORT_VLAN_MASK, 1630 MT7530_PORT_FALLBACK_MODE); 1631 1632 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 1633 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1634 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1635 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1636 MT7530_VLAN_ACC_ALL); 1637 1638 /* Set PVID to 0 */ 1639 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), 1640 G0_PORT_VID_MASK, G0_PORT_VID_DEF); 1641 1642 for (i = 0; i < priv->ds->num_ports; i++) { 1643 if (i == port) 1644 continue; 1645 if (dsa_is_user_port(ds, i) && 1646 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1647 all_user_ports_removed = false; 1648 break; 1649 } 1650 } 1651 1652 /* CPU port also does the same thing until all user ports belonging to 1653 * the CPU port get out of VLAN filtering mode. 1654 */ 1655 if (all_user_ports_removed) { 1656 mutex_lock(&priv->reg_mutex); 1657 mt7530_setup_vlan0(priv); 1658 mutex_unlock(&priv->reg_mutex); 1659 } 1660 } 1661 1662 static void 1663 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1664 { 1665 struct mt7530_priv *priv = ds->priv; 1666 1667 /* Trapped into security mode allows packet forwarding through VLAN 1668 * table lookup. 1669 */ 1670 if (dsa_is_user_port(ds, port)) { 1671 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1672 PCR_PORT_VLAN_MASK, 1673 MT7530_PORT_SECURITY_MODE); 1674 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), 1675 G0_PORT_VID_MASK, 1676 G0_PORT_VID(priv->ports[port].pvid)); 1677 1678 /* Only accept tagged frames if PVID is not set */ 1679 if (!priv->ports[port].pvid) 1680 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 1681 ACC_FRM_MASK, 1682 MT7530_VLAN_ACC_TAGGED); 1683 1684 /* Set the port as a user port which is to be able to recognize 1685 * VID from incoming packets before fetching entry within the 1686 * VLAN table. 1687 */ 1688 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 1689 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1690 VLAN_ATTR(MT7530_VLAN_USER) | 1691 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1692 } else { 1693 /* Also set CPU ports to the "user" VLAN port attribute, to 1694 * allow VLAN classification, but keep the EG_TAG attribute as 1695 * "consistent" (i.o.w. don't change its value) for packets 1696 * received by the switch from the CPU, so that tagged packets 1697 * are forwarded to user ports as tagged, and untagged as 1698 * untagged. 1699 */ 1700 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 1701 VLAN_ATTR_MASK, 1702 VLAN_ATTR(MT7530_VLAN_USER)); 1703 } 1704 } 1705 1706 static void 1707 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1708 struct dsa_bridge bridge) 1709 { 1710 struct mt7530_priv *priv = ds->priv; 1711 1712 mutex_lock(&priv->reg_mutex); 1713 1714 mt7530_update_port_member(priv, port, bridge.dev, false); 1715 1716 /* When a port is removed from the bridge, the port would be set up 1717 * back to the default as is at initial boot which is a VLAN-unaware 1718 * port. 1719 */ 1720 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 1721 PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE); 1722 1723 mutex_unlock(&priv->reg_mutex); 1724 } 1725 1726 static int 1727 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1728 const unsigned char *addr, u16 vid, 1729 struct dsa_db db) 1730 { 1731 struct mt7530_priv *priv = ds->priv; 1732 int ret; 1733 u8 port_mask = BIT(port); 1734 1735 mutex_lock(&priv->reg_mutex); 1736 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1737 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1738 mutex_unlock(&priv->reg_mutex); 1739 1740 return ret; 1741 } 1742 1743 static int 1744 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1745 const unsigned char *addr, u16 vid, 1746 struct dsa_db db) 1747 { 1748 struct mt7530_priv *priv = ds->priv; 1749 int ret; 1750 u8 port_mask = BIT(port); 1751 1752 mutex_lock(&priv->reg_mutex); 1753 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1754 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1755 mutex_unlock(&priv->reg_mutex); 1756 1757 return ret; 1758 } 1759 1760 static int 1761 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1762 dsa_fdb_dump_cb_t *cb, void *data) 1763 { 1764 struct mt7530_priv *priv = ds->priv; 1765 struct mt7530_fdb _fdb = { 0 }; 1766 int cnt = MT7530_NUM_FDB_RECORDS; 1767 int ret = 0; 1768 u32 rsp = 0; 1769 1770 mutex_lock(&priv->reg_mutex); 1771 1772 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1773 if (ret < 0) 1774 goto err; 1775 1776 do { 1777 if (rsp & ATC_SRCH_HIT) { 1778 mt7530_fdb_read(priv, &_fdb); 1779 if (_fdb.port_mask & BIT(port)) { 1780 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1781 data); 1782 if (ret < 0) 1783 break; 1784 } 1785 } 1786 } while (--cnt && 1787 !(rsp & ATC_SRCH_END) && 1788 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1789 err: 1790 mutex_unlock(&priv->reg_mutex); 1791 1792 return 0; 1793 } 1794 1795 static int 1796 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1797 const struct switchdev_obj_port_mdb *mdb, 1798 struct dsa_db db) 1799 { 1800 struct mt7530_priv *priv = ds->priv; 1801 const u8 *addr = mdb->addr; 1802 u16 vid = mdb->vid; 1803 u8 port_mask = 0; 1804 u32 val; 1805 int ret; 1806 1807 mutex_lock(&priv->reg_mutex); 1808 1809 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1810 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) { 1811 regmap_read(priv->regmap, MT7530_ATRD, &val); 1812 port_mask = FIELD_GET(PORT_MAP_MASK, val); 1813 } 1814 1815 port_mask |= BIT(port); 1816 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1817 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1818 1819 mutex_unlock(&priv->reg_mutex); 1820 1821 return ret; 1822 } 1823 1824 static int 1825 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1826 const struct switchdev_obj_port_mdb *mdb, 1827 struct dsa_db db) 1828 { 1829 struct mt7530_priv *priv = ds->priv; 1830 const u8 *addr = mdb->addr; 1831 u16 vid = mdb->vid; 1832 u8 port_mask = 0; 1833 u32 val; 1834 int ret; 1835 1836 mutex_lock(&priv->reg_mutex); 1837 1838 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1839 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) { 1840 regmap_read(priv->regmap, MT7530_ATRD, &val); 1841 port_mask = FIELD_GET(PORT_MAP_MASK, val); 1842 } 1843 1844 port_mask &= ~BIT(port); 1845 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1846 port_mask ? STATIC_ENT : STATIC_EMP); 1847 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1848 1849 mutex_unlock(&priv->reg_mutex); 1850 1851 return ret; 1852 } 1853 1854 static int 1855 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1856 struct netlink_ext_ack *extack) 1857 { 1858 struct dsa_port *dp = dsa_to_port(ds, port); 1859 struct dsa_port *cpu_dp = dp->cpu_dp; 1860 1861 if (vlan_filtering) { 1862 /* The port is being kept as VLAN-unaware port when bridge is 1863 * set up with vlan_filtering not being set, Otherwise, the 1864 * port and the corresponding CPU port is required the setup 1865 * for becoming a VLAN-aware port. 1866 */ 1867 mt7530_port_set_vlan_aware(ds, port); 1868 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1869 } else { 1870 mt7530_port_set_vlan_unaware(ds, port); 1871 } 1872 1873 return 0; 1874 } 1875 1876 static void 1877 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1878 struct mt7530_hw_vlan_entry *entry) 1879 { 1880 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1881 u8 new_members; 1882 u32 val; 1883 1884 new_members = entry->old_members | BIT(entry->port); 1885 1886 /* Validate the entry with independent learning, create egress tag per 1887 * VLAN and joining the port as one of the port members. 1888 */ 1889 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1890 VLAN_VALID; 1891 regmap_write(priv->regmap, MT7530_VAWD1, val); 1892 1893 /* Decide whether adding tag or not for those outgoing packets from the 1894 * port inside the VLAN. 1895 * CPU port is always taken as a tagged port for serving more than one 1896 * VLANs across and also being applied with egress type stack mode for 1897 * that VLAN tags would be appended after hardware special tag used as 1898 * DSA tag. 1899 */ 1900 if (dsa_port_is_cpu(dp)) 1901 val = MT7530_VLAN_EGRESS_STACK; 1902 else if (entry->untagged) 1903 val = MT7530_VLAN_EGRESS_UNTAG; 1904 else 1905 val = MT7530_VLAN_EGRESS_TAG; 1906 regmap_update_bits(priv->regmap, MT7530_VAWD2, 1907 ETAG_CTRL_P_MASK(entry->port), 1908 ETAG_CTRL_P(entry->port, val)); 1909 } 1910 1911 static void 1912 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1913 struct mt7530_hw_vlan_entry *entry) 1914 { 1915 u8 new_members; 1916 u32 val; 1917 1918 new_members = entry->old_members & ~BIT(entry->port); 1919 1920 regmap_read(priv->regmap, MT7530_VAWD1, &val); 1921 if (!(val & VLAN_VALID)) { 1922 dev_err(priv->dev, 1923 "Cannot be deleted due to invalid entry\n"); 1924 return; 1925 } 1926 1927 if (new_members) { 1928 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1929 VLAN_VALID; 1930 regmap_write(priv->regmap, MT7530_VAWD1, val); 1931 } else { 1932 regmap_write(priv->regmap, MT7530_VAWD1, 0); 1933 regmap_write(priv->regmap, MT7530_VAWD2, 0); 1934 } 1935 } 1936 1937 static void 1938 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1939 struct mt7530_hw_vlan_entry *entry, 1940 mt7530_vlan_op vlan_op) 1941 { 1942 u32 val; 1943 1944 /* Fetch entry */ 1945 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1946 1947 regmap_read(priv->regmap, MT7530_VAWD1, &val); 1948 1949 entry->old_members = FIELD_GET(PORT_MEM_MASK, val); 1950 1951 /* Manipulate entry */ 1952 vlan_op(priv, entry); 1953 1954 /* Flush result to hardware */ 1955 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1956 } 1957 1958 static int 1959 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1960 const struct switchdev_obj_port_vlan *vlan, 1961 struct netlink_ext_ack *extack) 1962 { 1963 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1964 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1965 struct mt7530_hw_vlan_entry new_entry; 1966 struct mt7530_priv *priv = ds->priv; 1967 1968 mutex_lock(&priv->reg_mutex); 1969 1970 /* VID 0 is managed exclusively by mt7530_setup_vlan0() for 1971 * VLAN-unaware bridge operation. Don't let the bridge overwrite 1972 * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. 1973 */ 1974 if (vlan->vid == 0) 1975 goto skip_vlan_table; 1976 1977 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1978 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1979 1980 skip_vlan_table: 1981 1982 if (pvid) { 1983 priv->ports[port].pvid = vlan->vid; 1984 1985 /* Accept all frames if PVID is set */ 1986 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 1987 ACC_FRM_MASK, MT7530_VLAN_ACC_ALL); 1988 1989 /* Only configure PVID if VLAN filtering is enabled */ 1990 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1991 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), 1992 G0_PORT_VID_MASK, 1993 G0_PORT_VID(vlan->vid)); 1994 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1995 /* This VLAN is overwritten without PVID, so unset it */ 1996 priv->ports[port].pvid = G0_PORT_VID_DEF; 1997 1998 /* Only accept tagged frames if the port is VLAN-aware */ 1999 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2000 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 2001 ACC_FRM_MASK, 2002 MT7530_VLAN_ACC_TAGGED); 2003 2004 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), 2005 G0_PORT_VID_MASK, G0_PORT_VID_DEF); 2006 } 2007 2008 mutex_unlock(&priv->reg_mutex); 2009 2010 return 0; 2011 } 2012 2013 static int 2014 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 2015 const struct switchdev_obj_port_vlan *vlan) 2016 { 2017 struct mt7530_hw_vlan_entry target_entry; 2018 struct mt7530_priv *priv = ds->priv; 2019 2020 mutex_lock(&priv->reg_mutex); 2021 2022 /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */ 2023 if (vlan->vid == 0) 2024 goto skip_vlan_table; 2025 2026 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2027 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2028 mt7530_hw_vlan_del); 2029 2030 skip_vlan_table: 2031 /* PVID is being restored to the default whenever the PVID port 2032 * is being removed from the VLAN. 2033 */ 2034 if (priv->ports[port].pvid == vlan->vid) { 2035 priv->ports[port].pvid = G0_PORT_VID_DEF; 2036 2037 /* Only accept tagged frames if the port is VLAN-aware */ 2038 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2039 regmap_update_bits(priv->regmap, MT7530_PVC_P(port), 2040 ACC_FRM_MASK, 2041 MT7530_VLAN_ACC_TAGGED); 2042 2043 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), 2044 G0_PORT_VID_MASK, G0_PORT_VID_DEF); 2045 } 2046 2047 2048 mutex_unlock(&priv->reg_mutex); 2049 2050 return 0; 2051 } 2052 2053 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2054 struct dsa_mall_mirror_tc_entry *mirror, 2055 bool ingress, struct netlink_ext_ack *extack) 2056 { 2057 struct mt7530_priv *priv = ds->priv; 2058 int monitor_port; 2059 u32 val; 2060 2061 /* Check for existent entry */ 2062 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2063 return -EEXIST; 2064 2065 regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val); 2066 2067 /* MT7530 only supports one monitor port */ 2068 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2069 if (val & MT753X_MIRROR_EN(priv->id) && 2070 monitor_port != mirror->to_local_port) 2071 return -EEXIST; 2072 2073 val |= MT753X_MIRROR_EN(priv->id); 2074 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2075 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2076 regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val); 2077 2078 regmap_read(priv->regmap, MT7530_PCR_P(port), &val); 2079 if (ingress) { 2080 val |= PORT_RX_MIR; 2081 priv->mirror_rx |= BIT(port); 2082 } else { 2083 val |= PORT_TX_MIR; 2084 priv->mirror_tx |= BIT(port); 2085 } 2086 regmap_write(priv->regmap, MT7530_PCR_P(port), val); 2087 2088 return 0; 2089 } 2090 2091 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2092 struct dsa_mall_mirror_tc_entry *mirror) 2093 { 2094 struct mt7530_priv *priv = ds->priv; 2095 u32 val; 2096 2097 regmap_read(priv->regmap, MT7530_PCR_P(port), &val); 2098 if (mirror->ingress) { 2099 val &= ~PORT_RX_MIR; 2100 priv->mirror_rx &= ~BIT(port); 2101 } else { 2102 val &= ~PORT_TX_MIR; 2103 priv->mirror_tx &= ~BIT(port); 2104 } 2105 regmap_write(priv->regmap, MT7530_PCR_P(port), val); 2106 2107 if (!priv->mirror_rx && !priv->mirror_tx) { 2108 regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val); 2109 val &= ~MT753X_MIRROR_EN(priv->id); 2110 regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val); 2111 } 2112 } 2113 2114 static enum dsa_tag_protocol 2115 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2116 enum dsa_tag_protocol mp) 2117 { 2118 return DSA_TAG_PROTO_MTK; 2119 } 2120 2121 #ifdef CONFIG_GPIOLIB 2122 static inline u32 2123 mt7530_gpio_to_bit(unsigned int offset) 2124 { 2125 /* Map GPIO offset to register bit 2126 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2127 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2128 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2129 * [14:12] port 3 LED 0..2 as GPIO 9..11 2130 * [18:16] port 4 LED 0..2 as GPIO 12..14 2131 */ 2132 return BIT(offset + offset / 3); 2133 } 2134 2135 static int 2136 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2137 { 2138 struct mt7530_priv *priv = gpiochip_get_data(gc); 2139 u32 bit = mt7530_gpio_to_bit(offset); 2140 u32 val; 2141 2142 regmap_read(priv->regmap, MT7530_LED_GPIO_DATA, &val); 2143 2144 return !!(val & bit); 2145 } 2146 2147 static int 2148 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2149 { 2150 struct mt7530_priv *priv = gpiochip_get_data(gc); 2151 u32 bit = mt7530_gpio_to_bit(offset); 2152 2153 regmap_assign_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit, value); 2154 2155 return 0; 2156 } 2157 2158 static int 2159 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2160 { 2161 struct mt7530_priv *priv = gpiochip_get_data(gc); 2162 u32 bit = mt7530_gpio_to_bit(offset); 2163 u32 val; 2164 2165 regmap_read(priv->regmap, MT7530_LED_GPIO_DIR, &val); 2166 2167 return (val & bit) ? 2168 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2169 } 2170 2171 static int 2172 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2173 { 2174 struct mt7530_priv *priv = gpiochip_get_data(gc); 2175 u32 bit = mt7530_gpio_to_bit(offset); 2176 2177 regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_OE, bit); 2178 regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_DIR, bit); 2179 2180 return 0; 2181 } 2182 2183 static int 2184 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2185 { 2186 struct mt7530_priv *priv = gpiochip_get_data(gc); 2187 u32 bit = mt7530_gpio_to_bit(offset); 2188 2189 regmap_set_bits(priv->regmap, MT7530_LED_GPIO_DIR, bit); 2190 2191 regmap_assign_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit, value); 2192 2193 regmap_set_bits(priv->regmap, MT7530_LED_GPIO_OE, bit); 2194 2195 return 0; 2196 } 2197 2198 static int 2199 mt7530_setup_gpio(struct mt7530_priv *priv) 2200 { 2201 struct device *dev = priv->dev; 2202 struct gpio_chip *gc; 2203 2204 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2205 if (!gc) 2206 return -ENOMEM; 2207 2208 regmap_write(priv->regmap, MT7530_LED_GPIO_OE, 0); 2209 regmap_write(priv->regmap, MT7530_LED_GPIO_DIR, 0); 2210 regmap_write(priv->regmap, MT7530_LED_IO_MODE, 0); 2211 2212 gc->label = "mt7530"; 2213 gc->parent = dev; 2214 gc->owner = THIS_MODULE; 2215 gc->get_direction = mt7530_gpio_get_direction; 2216 gc->direction_input = mt7530_gpio_direction_input; 2217 gc->direction_output = mt7530_gpio_direction_output; 2218 gc->get = mt7530_gpio_get; 2219 gc->set = mt7530_gpio_set; 2220 gc->base = -1; 2221 gc->ngpio = 15; 2222 gc->can_sleep = true; 2223 2224 return devm_gpiochip_add_data(dev, gc, priv); 2225 } 2226 #endif /* CONFIG_GPIOLIB */ 2227 2228 static void 2229 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2230 { 2231 struct dsa_switch *ds = priv->ds; 2232 int p; 2233 2234 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2235 if (BIT(p) & ds->phys_mii_mask) { 2236 unsigned int irq; 2237 2238 irq = irq_create_mapping(priv->irq_domain, p); 2239 ds->user_mii_bus->irq[p] = irq; 2240 } 2241 } 2242 } 2243 2244 static const struct regmap_irq mt7530_irqs[] = { 2245 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2246 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2247 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2248 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2249 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2250 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2251 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2252 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2253 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2254 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2255 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2256 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2257 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2258 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2259 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2260 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2261 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2262 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2263 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2264 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2265 }; 2266 2267 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2268 .name = KBUILD_MODNAME, 2269 .status_base = MT7530_SYS_INT_STS, 2270 .unmask_base = MT7530_SYS_INT_EN, 2271 .ack_base = MT7530_SYS_INT_STS, 2272 .init_ack_masked = true, 2273 .irqs = mt7530_irqs, 2274 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2275 .num_regs = 1, 2276 }; 2277 2278 static int 2279 mt7530_setup_irq(struct mt7530_priv *priv) 2280 { 2281 struct regmap_irq_chip_data *irq_data; 2282 struct device *dev = priv->dev; 2283 struct device_node *np = dev->of_node; 2284 int irq, ret; 2285 2286 if (!of_property_read_bool(np, "interrupt-controller")) { 2287 dev_info(dev, "no interrupt support\n"); 2288 return 0; 2289 } 2290 2291 irq = of_irq_get(np, 0); 2292 if (irq <= 0) { 2293 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2294 return irq ? : -EINVAL; 2295 } 2296 2297 /* This register must be set for MT7530 to properly fire interrupts */ 2298 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2299 regmap_set_bits(priv->regmap, MT7530_TOP_SIG_CTRL, 2300 TOP_SIG_CTRL_NORMAL); 2301 2302 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2303 priv->regmap, irq, 2304 IRQF_ONESHOT, 2305 0, &mt7530_regmap_irq_chip, 2306 &irq_data); 2307 if (ret) 2308 return ret; 2309 2310 priv->irq_domain = regmap_irq_get_domain(irq_data); 2311 2312 return 0; 2313 } 2314 2315 static void 2316 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2317 { 2318 int p; 2319 2320 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2321 if (BIT(p) & priv->ds->phys_mii_mask) { 2322 unsigned int irq; 2323 2324 irq = irq_find_mapping(priv->irq_domain, p); 2325 irq_dispose_mapping(irq); 2326 } 2327 } 2328 } 2329 2330 static int 2331 mt7530_setup_mdio(struct mt7530_priv *priv) 2332 { 2333 struct device_node *mnp, *np = priv->dev->of_node; 2334 struct dsa_switch *ds = priv->ds; 2335 struct device *dev = priv->dev; 2336 struct mii_bus *bus; 2337 static int idx; 2338 int ret = 0; 2339 2340 mnp = of_get_child_by_name(np, "mdio"); 2341 2342 if (mnp && !of_device_is_available(mnp)) 2343 goto out; 2344 2345 bus = devm_mdiobus_alloc(dev); 2346 if (!bus) { 2347 ret = -ENOMEM; 2348 goto out; 2349 } 2350 2351 if (!mnp) 2352 ds->user_mii_bus = bus; 2353 2354 bus->priv = priv; 2355 bus->name = KBUILD_MODNAME "-mii"; 2356 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2357 bus->read = mt753x_phy_read_c22; 2358 bus->write = mt753x_phy_write_c22; 2359 bus->read_c45 = mt753x_phy_read_c45; 2360 bus->write_c45 = mt753x_phy_write_c45; 2361 bus->parent = dev; 2362 bus->phy_mask = ~ds->phys_mii_mask; 2363 2364 if (priv->irq_domain && !mnp) 2365 mt7530_setup_mdio_irq(priv); 2366 2367 ret = devm_of_mdiobus_register(dev, bus, mnp); 2368 if (ret) { 2369 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2370 if (priv->irq_domain && !mnp) 2371 mt7530_free_mdio_irq(priv); 2372 } 2373 2374 out: 2375 of_node_put(mnp); 2376 return ret; 2377 } 2378 2379 static int 2380 mt7530_setup(struct dsa_switch *ds) 2381 { 2382 struct mt7530_priv *priv = ds->priv; 2383 struct device_node *dn = NULL; 2384 struct device_node *phy_node; 2385 struct device_node *mac_np; 2386 phy_interface_t interface; 2387 struct dsa_port *cpu_dp; 2388 u32 id, val; 2389 int ret, i; 2390 2391 /* The parent node of conduit netdev which holds the common system 2392 * controller also is the container for two GMACs nodes representing 2393 * as two netdev instances. 2394 */ 2395 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2396 dn = cpu_dp->conduit->dev.of_node->parent; 2397 /* It doesn't matter which CPU port is found first, 2398 * their conduits should share the same parent OF node 2399 */ 2400 break; 2401 } 2402 2403 if (!dn) { 2404 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2405 return -EINVAL; 2406 } 2407 2408 ds->assisted_learning_on_cpu_port = true; 2409 ds->untag_vlan_aware_bridge_pvid = true; 2410 ds->mtu_enforcement_ingress = true; 2411 ds->ageing_time_min = 2 * 1000; 2412 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2413 2414 if (priv->id == ID_MT7530) { 2415 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2416 ret = regulator_enable(priv->core_pwr); 2417 if (ret < 0) { 2418 dev_err(priv->dev, 2419 "Failed to enable core power: %d\n", ret); 2420 return ret; 2421 } 2422 2423 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2424 ret = regulator_enable(priv->io_pwr); 2425 if (ret < 0) { 2426 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2427 ret); 2428 return ret; 2429 } 2430 } 2431 2432 /* Reset whole chip through gpio pin or memory-mapped registers for 2433 * different type of hardware 2434 */ 2435 if (priv->mcm) { 2436 reset_control_assert(priv->rstc); 2437 usleep_range(5000, 5100); 2438 reset_control_deassert(priv->rstc); 2439 } else { 2440 gpiod_set_value_cansleep(priv->reset, 0); 2441 usleep_range(5000, 5100); 2442 gpiod_set_value_cansleep(priv->reset, 1); 2443 } 2444 2445 /* Waiting for MT7530 got to stable */ 2446 ret = regmap_read_poll_timeout(priv->regmap, MT753X_TRAP, val, 2447 val != 0, 20, 1000000); 2448 if (ret < 0) { 2449 dev_err(priv->dev, "reset timeout\n"); 2450 return ret; 2451 } 2452 2453 regmap_read(priv->regmap, MT7530_CREV, &id); 2454 id = FIELD_GET(CHIP_NAME_MASK, id); 2455 if (id != MT7530_ID) { 2456 dev_err(priv->dev, "chip %x can't be supported\n", id); 2457 return -ENODEV; 2458 } 2459 2460 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2461 dev_err(priv->dev, 2462 "MT7530 with a 20MHz XTAL is not supported!\n"); 2463 return -EINVAL; 2464 } 2465 2466 /* Reset the switch through internal reset */ 2467 regmap_write(priv->regmap, MT7530_SYS_CTRL, 2468 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2469 2470 /* Lower Tx driving for TRGMII path */ 2471 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2472 regmap_write(priv->regmap, MT7530_TRGMII_TD_ODT(i), 2473 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2474 2475 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2476 regmap_update_bits(priv->regmap, MT7530_TRGMII_RD(i), 2477 RD_TAP_MASK, RD_TAP(16)); 2478 2479 /* Allow modifying the trap and directly access PHY registers via the 2480 * MDIO bus the switch is on. 2481 */ 2482 regmap_update_bits(priv->regmap, MT753X_MTRAP, 2483 MT7530_CHG_TRAP | MT7530_PHY_INDIRECT_ACCESS, 2484 MT7530_CHG_TRAP); 2485 2486 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2487 mt7530_pll_setup(priv); 2488 2489 mt753x_trap_frames(priv); 2490 2491 /* Enable and reset MIB counters */ 2492 mt7530_mib_reset(ds); 2493 2494 for (i = 0; i < priv->ds->num_ports; i++) { 2495 /* Clear link settings and enable force mode to force link down 2496 * on all ports until they're enabled later. 2497 */ 2498 regmap_update_bits(priv->regmap, MT753X_PMCR_P(i), 2499 PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv->id), 2500 MT753X_FORCE_MODE(priv->id)); 2501 2502 /* Disable forwarding by default on all ports */ 2503 regmap_update_bits(priv->regmap, MT7530_PCR_P(i), 2504 PCR_MATRIX_MASK, PCR_MATRIX_CLR); 2505 2506 /* Disable learning by default on all ports */ 2507 regmap_set_bits(priv->regmap, MT7530_PSC_P(i), SA_DIS); 2508 2509 if (dsa_is_cpu_port(ds, i)) { 2510 mt753x_cpu_port_enable(ds, i); 2511 } else { 2512 mt7530_port_disable(ds, i); 2513 2514 /* Set default PVID to 0 on all user ports */ 2515 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i), 2516 G0_PORT_VID_MASK, G0_PORT_VID_DEF); 2517 } 2518 /* Enable consistent egress tag */ 2519 regmap_update_bits(priv->regmap, MT7530_PVC_P(i), 2520 PVC_EG_TAG_MASK, 2521 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2522 } 2523 2524 /* Allow mirroring frames received on the local port (monitor port). */ 2525 regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN); 2526 2527 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2528 ret = mt7530_setup_vlan0(priv); 2529 if (ret) 2530 return ret; 2531 2532 /* Check for PHY muxing on port 5 */ 2533 if (dsa_is_unused_port(ds, 5)) { 2534 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2535 * Set priv->p5_mode to the appropriate value if PHY muxing is 2536 * detected. 2537 */ 2538 for_each_child_of_node(dn, mac_np) { 2539 if (!of_device_is_compatible(mac_np, 2540 "mediatek,eth-mac")) 2541 continue; 2542 2543 ret = of_property_read_u32(mac_np, "reg", &id); 2544 if (ret < 0 || id != 1) 2545 continue; 2546 2547 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2548 if (!phy_node) 2549 continue; 2550 2551 if (phy_node->parent == priv->dev->of_node->parent || 2552 phy_node->parent->parent == priv->dev->of_node) { 2553 ret = of_get_phy_mode(mac_np, &interface); 2554 if (ret && ret != -ENODEV) { 2555 of_node_put(mac_np); 2556 of_node_put(phy_node); 2557 return ret; 2558 } 2559 id = of_mdio_parse_addr(ds->dev, phy_node); 2560 if (id == 0) 2561 priv->p5_mode = MUX_PHY_P0; 2562 if (id == 4) 2563 priv->p5_mode = MUX_PHY_P4; 2564 } 2565 of_node_put(mac_np); 2566 of_node_put(phy_node); 2567 break; 2568 } 2569 2570 if (priv->p5_mode == MUX_PHY_P0 || 2571 priv->p5_mode == MUX_PHY_P4) { 2572 regmap_clear_bits(priv->regmap, MT753X_MTRAP, 2573 MT7530_P5_DIS); 2574 mt7530_setup_port5(ds, interface); 2575 } 2576 } 2577 2578 #ifdef CONFIG_GPIOLIB 2579 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2580 ret = mt7530_setup_gpio(priv); 2581 if (ret) 2582 return ret; 2583 } 2584 #endif /* CONFIG_GPIOLIB */ 2585 2586 /* Flush the FDB table */ 2587 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2588 if (ret < 0) 2589 return ret; 2590 2591 return 0; 2592 } 2593 2594 static int 2595 mt7531_setup_common(struct dsa_switch *ds) 2596 { 2597 struct mt7530_priv *priv = ds->priv; 2598 int ret, i; 2599 2600 ds->assisted_learning_on_cpu_port = true; 2601 ds->untag_vlan_aware_bridge_pvid = true; 2602 ds->mtu_enforcement_ingress = true; 2603 ds->ageing_time_min = 2 * 1000; 2604 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2605 2606 mt753x_trap_frames(priv); 2607 2608 /* Enable and reset MIB counters */ 2609 mt7530_mib_reset(ds); 2610 2611 /* Disable flooding on all ports */ 2612 regmap_clear_bits(priv->regmap, MT753X_MFC, 2613 BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK); 2614 2615 for (i = 0; i < priv->ds->num_ports; i++) { 2616 /* Clear link settings and enable force mode to force link down 2617 * on all ports until they're enabled later. 2618 */ 2619 regmap_update_bits(priv->regmap, MT753X_PMCR_P(i), 2620 PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv->id), 2621 MT753X_FORCE_MODE(priv->id)); 2622 2623 /* Disable forwarding by default on all ports */ 2624 regmap_update_bits(priv->regmap, MT7530_PCR_P(i), 2625 PCR_MATRIX_MASK, PCR_MATRIX_CLR); 2626 2627 /* Disable learning by default on all ports */ 2628 regmap_set_bits(priv->regmap, MT7530_PSC_P(i), SA_DIS); 2629 2630 regmap_set_bits(priv->regmap, MT7531_DBG_CNT(i), 2631 MT7531_DIS_CLR); 2632 2633 if (dsa_is_cpu_port(ds, i)) { 2634 mt753x_cpu_port_enable(ds, i); 2635 } else { 2636 mt7530_port_disable(ds, i); 2637 2638 /* Set default PVID to 0 on all user ports */ 2639 regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i), 2640 G0_PORT_VID_MASK, G0_PORT_VID_DEF); 2641 } 2642 2643 /* Enable consistent egress tag */ 2644 regmap_update_bits(priv->regmap, MT7530_PVC_P(i), 2645 PVC_EG_TAG_MASK, 2646 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2647 } 2648 2649 /* Allow mirroring frames received on the local port (monitor port). */ 2650 regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN); 2651 2652 /* Enable Special Tag for rx frames */ 2653 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2654 regmap_write(priv->regmap, MT753X_CPORT_SPTAG_CFG, 2655 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2656 2657 /* Flush the FDB table */ 2658 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2659 if (ret < 0) 2660 return ret; 2661 2662 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2663 return mt7530_setup_vlan0(priv); 2664 } 2665 2666 static int 2667 mt7531_setup(struct dsa_switch *ds) 2668 { 2669 struct mt7530_priv *priv = ds->priv; 2670 u32 val, id; 2671 int ret, i; 2672 2673 /* Reset whole chip through gpio pin or memory-mapped registers for 2674 * different type of hardware 2675 */ 2676 if (priv->mcm) { 2677 reset_control_assert(priv->rstc); 2678 usleep_range(5000, 5100); 2679 reset_control_deassert(priv->rstc); 2680 } else { 2681 gpiod_set_value_cansleep(priv->reset, 0); 2682 usleep_range(5000, 5100); 2683 gpiod_set_value_cansleep(priv->reset, 1); 2684 } 2685 2686 /* Waiting for MT7530 got to stable */ 2687 ret = regmap_read_poll_timeout(priv->regmap, MT753X_TRAP, val, 2688 val != 0, 20, 1000000); 2689 if (ret < 0) { 2690 dev_err(priv->dev, "reset timeout\n"); 2691 return ret; 2692 } 2693 2694 regmap_read(priv->regmap, MT7531_CREV, &id); 2695 id = FIELD_GET(CHIP_NAME_MASK, id); 2696 2697 if (id != MT7531_ID) { 2698 dev_err(priv->dev, "chip %x can't be supported\n", id); 2699 return -ENODEV; 2700 } 2701 2702 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2703 * MT7531BE has got only one SGMII unit which is for port 6. 2704 */ 2705 regmap_read(priv->regmap, MT7531_TOP_SIG_SR, &val); 2706 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2707 2708 /* Force link down on all ports before internal reset */ 2709 for (i = 0; i < priv->ds->num_ports; i++) 2710 regmap_write(priv->regmap, MT753X_PMCR_P(i), 2711 MT7531_FORCE_MODE_LNK); 2712 2713 /* Reset the switch through internal reset */ 2714 regmap_write(priv->regmap, MT7530_SYS_CTRL, 2715 SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2716 2717 if (!priv->p5_sgmii) { 2718 mt7531_pll_setup(priv); 2719 } else { 2720 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2721 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2722 * to expose the MDIO bus of the switch. 2723 */ 2724 regmap_update_bits(priv->regmap, MT7531_GPIO_MODE1, 2725 MT7531_GPIO11_RG_RXD2_MASK, 2726 MT7531_EXT_P_MDC_11); 2727 regmap_update_bits(priv->regmap, MT7531_GPIO_MODE1, 2728 MT7531_GPIO12_RG_RXD3_MASK, 2729 MT7531_EXT_P_MDIO_12); 2730 } 2731 2732 regmap_update_bits(priv->regmap, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2733 MT7531_GPIO0_INTERRUPT); 2734 2735 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2736 * phy_device has not yet been created provided for 2737 * phy_[read,write]_mmd_indirect is called, we provide our own 2738 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2739 */ 2740 ret = mt7531_ind_c45_phy_read(priv, 2741 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2742 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2743 if (ret < 0) 2744 return ret; 2745 2746 val = ret; 2747 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2748 val &= ~MT7531_PHY_PLL_OFF; 2749 ret = mt7531_ind_c45_phy_write(priv, 2750 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2751 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2752 if (ret < 0) 2753 return ret; 2754 2755 /* Disable EEE advertisement on the switch PHYs. */ 2756 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2757 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2758 i++) { 2759 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2760 0); 2761 } 2762 2763 ret = mt7531_setup_common(ds); 2764 if (ret) 2765 return ret; 2766 2767 return 0; 2768 } 2769 2770 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2771 struct phylink_config *config) 2772 { 2773 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2774 2775 switch (port) { 2776 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2777 case 0 ... 4: 2778 __set_bit(PHY_INTERFACE_MODE_GMII, 2779 config->supported_interfaces); 2780 break; 2781 2782 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2783 case 5: 2784 phy_interface_set_rgmii(config->supported_interfaces); 2785 __set_bit(PHY_INTERFACE_MODE_MII, 2786 config->supported_interfaces); 2787 __set_bit(PHY_INTERFACE_MODE_GMII, 2788 config->supported_interfaces); 2789 break; 2790 2791 /* Port 6 supports rgmii and trgmii. */ 2792 case 6: 2793 __set_bit(PHY_INTERFACE_MODE_RGMII, 2794 config->supported_interfaces); 2795 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2796 config->supported_interfaces); 2797 break; 2798 } 2799 } 2800 2801 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2802 struct phylink_config *config) 2803 { 2804 struct mt7530_priv *priv = ds->priv; 2805 2806 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2807 2808 switch (port) { 2809 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2810 case 0 ... 4: 2811 __set_bit(PHY_INTERFACE_MODE_GMII, 2812 config->supported_interfaces); 2813 break; 2814 2815 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2816 * MT7531AE. 2817 */ 2818 case 5: 2819 if (!priv->p5_sgmii) { 2820 phy_interface_set_rgmii(config->supported_interfaces); 2821 break; 2822 } 2823 fallthrough; 2824 2825 /* Port 6 supports sgmii/802.3z. */ 2826 case 6: 2827 __set_bit(PHY_INTERFACE_MODE_SGMII, 2828 config->supported_interfaces); 2829 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2830 config->supported_interfaces); 2831 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2832 config->supported_interfaces); 2833 2834 config->mac_capabilities |= MAC_2500FD; 2835 break; 2836 } 2837 } 2838 2839 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2840 struct phylink_config *config) 2841 { 2842 switch (port) { 2843 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2844 case 0 ... 3: 2845 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2846 config->supported_interfaces); 2847 2848 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2849 break; 2850 2851 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2852 case 6: 2853 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2854 config->supported_interfaces); 2855 2856 config->mac_capabilities |= MAC_10000FD; 2857 break; 2858 } 2859 } 2860 2861 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2862 struct phylink_config *config) 2863 { 2864 switch (port) { 2865 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2866 case 0 ... 4: 2867 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2868 config->supported_interfaces); 2869 2870 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2871 break; 2872 2873 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2874 case 6: 2875 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2876 config->supported_interfaces); 2877 2878 config->mac_capabilities |= MAC_10000FD; 2879 break; 2880 } 2881 } 2882 2883 static void en7528_mac_port_get_caps(struct dsa_switch *ds, int port, 2884 struct phylink_config *config) 2885 { 2886 switch (port) { 2887 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2888 case 1 ... 4: 2889 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2890 config->supported_interfaces); 2891 2892 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2893 break; 2894 2895 /* Port 6 is connected to SoC's GMAC at 1000 Mbps full duplex. There 2896 * is no MII pinout. 2897 */ 2898 case 6: 2899 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2900 config->supported_interfaces); 2901 2902 config->mac_capabilities |= MAC_1000FD; 2903 break; 2904 } 2905 } 2906 2907 static void 2908 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2909 phy_interface_t interface) 2910 { 2911 struct mt7530_priv *priv = ds->priv; 2912 2913 if (port == 5) 2914 mt7530_setup_port5(priv->ds, interface); 2915 else if (port == 6) 2916 mt7530_setup_port6(priv->ds, interface); 2917 } 2918 2919 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2920 phy_interface_t interface, 2921 struct phy_device *phydev) 2922 { 2923 u32 val; 2924 2925 regmap_read(priv->regmap, MT7531_CLKGEN_CTRL, &val); 2926 val |= GP_CLK_EN; 2927 val &= ~GP_MODE_MASK; 2928 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2929 val &= ~CLK_SKEW_IN_MASK; 2930 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2931 val &= ~CLK_SKEW_OUT_MASK; 2932 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2933 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2934 2935 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2936 if (!phydev || phy_driver_is_genphy(phydev)) { 2937 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2938 switch (interface) { 2939 case PHY_INTERFACE_MODE_RGMII: 2940 val |= TXCLK_NO_REVERSE; 2941 val |= RXCLK_NO_DELAY; 2942 break; 2943 case PHY_INTERFACE_MODE_RGMII_RXID: 2944 val |= TXCLK_NO_REVERSE; 2945 break; 2946 case PHY_INTERFACE_MODE_RGMII_TXID: 2947 val |= RXCLK_NO_DELAY; 2948 break; 2949 case PHY_INTERFACE_MODE_RGMII_ID: 2950 break; 2951 default: 2952 break; 2953 } 2954 } 2955 2956 regmap_write(priv->regmap, MT7531_CLKGEN_CTRL, val); 2957 } 2958 2959 static void 2960 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2961 phy_interface_t interface) 2962 { 2963 struct mt7530_priv *priv = ds->priv; 2964 struct phy_device *phydev; 2965 struct dsa_port *dp; 2966 2967 if (phy_interface_mode_is_rgmii(interface)) { 2968 dp = dsa_to_port(ds, port); 2969 phydev = dp->user->phydev; 2970 mt7531_rgmii_setup(priv, interface, phydev); 2971 } 2972 } 2973 2974 static struct phylink_pcs * 2975 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2976 phy_interface_t interface) 2977 { 2978 struct dsa_port *dp = dsa_phylink_to_port(config); 2979 struct mt7530_priv *priv = dp->ds->priv; 2980 2981 switch (interface) { 2982 case PHY_INTERFACE_MODE_TRGMII: 2983 return &priv->pcs[dp->index].pcs; 2984 case PHY_INTERFACE_MODE_SGMII: 2985 case PHY_INTERFACE_MODE_1000BASEX: 2986 case PHY_INTERFACE_MODE_2500BASEX: 2987 return priv->ports[dp->index].sgmii_pcs; 2988 default: 2989 return NULL; 2990 } 2991 } 2992 2993 static void 2994 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2995 const struct phylink_link_state *state) 2996 { 2997 struct dsa_port *dp = dsa_phylink_to_port(config); 2998 struct dsa_switch *ds = dp->ds; 2999 struct mt7530_priv *priv; 3000 int port = dp->index; 3001 3002 priv = ds->priv; 3003 3004 if ((port == 5 || port == 6) && priv->info->mac_port_config) 3005 priv->info->mac_port_config(ds, port, mode, state->interface); 3006 3007 /* Are we connected to external phy */ 3008 if (port == 5 && dsa_is_user_port(ds, 5)) 3009 regmap_set_bits(priv->regmap, MT753X_PMCR_P(port), 3010 PMCR_EXT_PHY); 3011 } 3012 3013 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 3014 unsigned int mode, 3015 phy_interface_t interface) 3016 { 3017 struct dsa_port *dp = dsa_phylink_to_port(config); 3018 struct mt7530_priv *priv = dp->ds->priv; 3019 3020 regmap_clear_bits(priv->regmap, MT753X_PMCR_P(dp->index), 3021 PMCR_LINK_SETTINGS_MASK); 3022 } 3023 3024 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 3025 struct phy_device *phydev, 3026 unsigned int mode, 3027 phy_interface_t interface, 3028 int speed, int duplex, 3029 bool tx_pause, bool rx_pause) 3030 { 3031 struct dsa_port *dp = dsa_phylink_to_port(config); 3032 struct mt7530_priv *priv = dp->ds->priv; 3033 u32 mcr; 3034 3035 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 3036 3037 switch (speed) { 3038 case SPEED_1000: 3039 case SPEED_2500: 3040 case SPEED_10000: 3041 mcr |= PMCR_FORCE_SPEED_1000; 3042 break; 3043 case SPEED_100: 3044 mcr |= PMCR_FORCE_SPEED_100; 3045 break; 3046 } 3047 if (duplex == DUPLEX_FULL) { 3048 mcr |= PMCR_FORCE_FDX; 3049 if (tx_pause) 3050 mcr |= PMCR_FORCE_TX_FC_EN; 3051 if (rx_pause) 3052 mcr |= PMCR_FORCE_RX_FC_EN; 3053 } 3054 3055 regmap_set_bits(priv->regmap, MT753X_PMCR_P(dp->index), mcr); 3056 } 3057 3058 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 3059 { 3060 struct dsa_port *dp = dsa_phylink_to_port(config); 3061 struct mt7530_priv *priv = dp->ds->priv; 3062 3063 regmap_clear_bits(priv->regmap, MT753X_PMCR_P(dp->index), 3064 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3065 } 3066 3067 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 3068 u32 timer, bool tx_clock_stop) 3069 { 3070 struct dsa_port *dp = dsa_phylink_to_port(config); 3071 struct mt7530_priv *priv = dp->ds->priv; 3072 u32 val; 3073 3074 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3075 * system to enter LPI mode immediately rather than waiting for 3076 * the LPI threshold. 3077 */ 3078 if (!timer) 3079 val = LPI_MODE_EN; 3080 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3081 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3082 else 3083 val = LPI_THRESH_MASK; 3084 3085 regmap_update_bits(priv->regmap, MT753X_PMEEECR_P(dp->index), 3086 LPI_THRESH_MASK | LPI_MODE_EN, val); 3087 3088 regmap_set_bits(priv->regmap, MT753X_PMCR_P(dp->index), 3089 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3090 3091 return 0; 3092 } 3093 3094 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3095 struct phylink_config *config) 3096 { 3097 struct mt7530_priv *priv = ds->priv; 3098 3099 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3100 3101 priv->info->mac_port_get_caps(ds, port, config); 3102 3103 /* The EN7528 GPHYs report EEE capability, but negotiating EEE with 3104 * common link partners (e.g. Realtek GbE NICs) results in an unstable 3105 * link with dropped frames. Leave the LPI capabilities empty so that 3106 * phylink disables EEE on these PHYs and refuses to enable it from 3107 * userspace. 3108 */ 3109 if (priv->id != ID_EN7528 && 3110 config->mac_capabilities & (MAC_100FD | MAC_1000FD)) { 3111 u32 eeecr; 3112 3113 regmap_read(priv->regmap, MT753X_PMEEECR_P(port), &eeecr); 3114 3115 /* LPI above 1 Gbps is not supported */ 3116 config->lpi_capabilities = config->mac_capabilities & 3117 (MAC_100FD | MAC_1000FD); 3118 phy_interface_copy(config->lpi_interfaces, 3119 config->supported_interfaces); 3120 __clear_bit(PHY_INTERFACE_MODE_2500BASEX, 3121 config->lpi_interfaces); 3122 3123 /* tx_lpi_timer should be in microseconds. The time units for 3124 * LPI threshold are unspecified. 3125 */ 3126 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3127 } 3128 } 3129 3130 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3131 unsigned long *supported, 3132 const struct phylink_link_state *state) 3133 { 3134 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3135 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3136 phy_interface_mode_is_8023z(state->interface)) 3137 phylink_clear(supported, Autoneg); 3138 3139 return 0; 3140 } 3141 3142 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3143 struct phylink_link_state *state) 3144 { 3145 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3146 int port = pcs_to_mt753x_pcs(pcs)->port; 3147 u32 pmsr; 3148 3149 regmap_read(priv->regmap, MT7530_PMSR_P(port), &pmsr); 3150 3151 state->link = (pmsr & PMSR_LINK); 3152 state->an_complete = state->link; 3153 state->duplex = !!(pmsr & PMSR_DPX); 3154 3155 switch (pmsr & PMSR_SPEED_MASK) { 3156 case PMSR_SPEED_10: 3157 state->speed = SPEED_10; 3158 break; 3159 case PMSR_SPEED_100: 3160 state->speed = SPEED_100; 3161 break; 3162 case PMSR_SPEED_1000: 3163 state->speed = SPEED_1000; 3164 break; 3165 default: 3166 state->speed = SPEED_UNKNOWN; 3167 break; 3168 } 3169 3170 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3171 if (pmsr & PMSR_RX_FC) 3172 state->pause |= MLO_PAUSE_RX; 3173 if (pmsr & PMSR_TX_FC) 3174 state->pause |= MLO_PAUSE_TX; 3175 } 3176 3177 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3178 phy_interface_t interface, 3179 const unsigned long *advertising, 3180 bool permit_pause_to_mac) 3181 { 3182 return 0; 3183 } 3184 3185 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3186 { 3187 } 3188 3189 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3190 .pcs_validate = mt753x_pcs_validate, 3191 .pcs_get_state = mt7530_pcs_get_state, 3192 .pcs_config = mt753x_pcs_config, 3193 .pcs_an_restart = mt7530_pcs_an_restart, 3194 }; 3195 3196 static int 3197 mt753x_setup(struct dsa_switch *ds) 3198 { 3199 struct mt7530_priv *priv = ds->priv; 3200 int ret = priv->info->sw_setup(ds); 3201 int i; 3202 3203 if (ret) 3204 return ret; 3205 3206 ret = mt7530_setup_irq(priv); 3207 if (ret) 3208 return ret; 3209 3210 ret = mt7530_setup_mdio(priv); 3211 if (ret) 3212 return ret; 3213 3214 /* Initialise the PCS devices */ 3215 for (i = 0; i < priv->ds->num_ports; i++) { 3216 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3217 priv->pcs[i].priv = priv; 3218 priv->pcs[i].port = i; 3219 } 3220 3221 if (priv->create_sgmii) 3222 ret = priv->create_sgmii(priv); 3223 3224 if (ret && priv->irq_domain) 3225 mt7530_free_mdio_irq(priv); 3226 3227 if (!ret && priv->bus) { 3228 mt7530_stats_refresh(priv); 3229 schedule_delayed_work(&priv->stats_work, 3230 MT7530_STATS_POLL_INTERVAL); 3231 } 3232 3233 return ret; 3234 } 3235 3236 static void 3237 mt753x_teardown(struct dsa_switch *ds) 3238 { 3239 struct mt7530_priv *priv = ds->priv; 3240 3241 if (priv->bus) 3242 cancel_delayed_work_sync(&priv->stats_work); 3243 } 3244 3245 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3246 struct ethtool_keee *e) 3247 { 3248 if (e->tx_lpi_timer > 0xFFF) 3249 return -EINVAL; 3250 3251 return 0; 3252 } 3253 3254 static int 3255 mt753x_port_change_conduit(struct dsa_switch *ds, int port, 3256 struct net_device *conduit, 3257 struct netlink_ext_ack *extack) 3258 { 3259 struct dsa_port *new_cpu_dp = conduit->dsa_ptr; 3260 struct dsa_port *dp = dsa_to_port(ds, port); 3261 struct mt7530_priv *priv = ds->priv; 3262 3263 if (priv->id != ID_MT7531) { 3264 NL_SET_ERR_MSG_MOD(extack, 3265 "Changing DSA conduit is only supported on MT7531"); 3266 return -EOPNOTSUPP; 3267 } 3268 3269 if (new_cpu_dp->ds != ds) { 3270 NL_SET_ERR_MSG_MOD(extack, 3271 "Cannot assign a conduit on a different switch"); 3272 return -EOPNOTSUPP; 3273 } 3274 3275 mutex_lock(&priv->reg_mutex); 3276 3277 /* dp->cpu_dp still points to the old CPU port */ 3278 priv->ports[port].pm &= ~PCR_MATRIX(BIT(dp->cpu_dp->index)); 3279 priv->ports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp->index)); 3280 if (priv->ports[port].enable) 3281 regmap_update_bits(priv->regmap, MT7530_PCR_P(port), 3282 PCR_MATRIX_MASK, priv->ports[port].pm); 3283 3284 mutex_unlock(&priv->reg_mutex); 3285 3286 mt7530_port_fast_age(ds, port); 3287 3288 return 0; 3289 } 3290 3291 static void 3292 mt753x_conduit_state_change(struct dsa_switch *ds, 3293 const struct net_device *conduit, 3294 bool operational) 3295 { 3296 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3297 struct mt7530_priv *priv = ds->priv; 3298 int val = 0; 3299 u8 mask; 3300 3301 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3302 * forwarded to the numerically smallest CPU port whose conduit 3303 * interface is up. 3304 */ 3305 if (priv->id != ID_MT7530 && priv->id != ID_MT7621 && 3306 priv->id != ID_EN7528) 3307 return; 3308 3309 mask = BIT(cpu_dp->index); 3310 3311 if (operational) 3312 priv->active_cpu_ports |= mask; 3313 else 3314 priv->active_cpu_ports &= ~mask; 3315 3316 if (priv->active_cpu_ports) { 3317 val = MT7530_CPU_EN | 3318 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3319 } 3320 3321 regmap_update_bits(priv->regmap, MT753X_MFC, 3322 MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3323 } 3324 3325 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3326 struct tc_tbf_qopt_offload *qopt) 3327 { 3328 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3329 struct mt7530_priv *priv = ds->priv; 3330 u32 rate = 0; 3331 3332 switch (qopt->command) { 3333 case TC_TBF_REPLACE: 3334 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3335 fallthrough; 3336 case TC_TBF_DESTROY: { 3337 u32 val, tick; 3338 3339 regmap_update_bits(priv->regmap, MT753X_GERLCR, EGR_BC_MASK, 3340 EGR_BC_CRC_IPG_PREAMBLE); 3341 3342 /* if rate is greater than 10Mbps tick is 1/32 ms, 3343 * 1ms otherwise 3344 */ 3345 tick = rate > 10000 ? 2 : 7; 3346 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3347 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3348 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3349 ERLCR_TBF_MODE_MASK | 3350 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3351 regmap_write(priv->regmap, MT753X_ERLCR_P(port), val); 3352 break; 3353 } 3354 default: 3355 return -EOPNOTSUPP; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3362 enum tc_setup_type type, void *type_data) 3363 { 3364 switch (type) { 3365 case TC_SETUP_QDISC_TBF: 3366 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3367 default: 3368 return -EOPNOTSUPP; 3369 } 3370 } 3371 3372 static int mt7988_setup(struct dsa_switch *ds) 3373 { 3374 struct mt7530_priv *priv = ds->priv; 3375 3376 /* Reset the switch */ 3377 reset_control_assert(priv->rstc); 3378 usleep_range(20, 50); 3379 reset_control_deassert(priv->rstc); 3380 usleep_range(20, 50); 3381 3382 /* AN7583 require additional tweak to CONN_CFG */ 3383 if (priv->id == ID_AN7583) 3384 regmap_update_bits(priv->regmap, AN7583_GEPHY_CONN_CFG, 3385 AN7583_CSR_DPHY_CKIN_SEL | 3386 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3387 AN7583_CSR_ETHER_AFE_PWD, 3388 AN7583_CSR_DPHY_CKIN_SEL | 3389 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3390 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3391 3392 /* Reset the switch PHYs */ 3393 regmap_write(priv->regmap, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3394 3395 return mt7531_setup_common(ds); 3396 } 3397 3398 static const struct dsa_switch_ops mt7530_switch_ops = { 3399 .get_tag_protocol = mtk_get_tag_protocol, 3400 .setup = mt753x_setup, 3401 .teardown = mt753x_teardown, 3402 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3403 .port_change_conduit = mt753x_port_change_conduit, 3404 .get_strings = mt7530_get_strings, 3405 .get_ethtool_stats = mt7530_get_ethtool_stats, 3406 .get_sset_count = mt7530_get_sset_count, 3407 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3408 .get_rmon_stats = mt7530_get_rmon_stats, 3409 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3410 .get_stats64 = mt7530_get_stats64, 3411 .set_ageing_time = mt7530_set_ageing_time, 3412 .port_enable = mt7530_port_enable, 3413 .port_disable = mt7530_port_disable, 3414 .port_change_mtu = mt7530_port_change_mtu, 3415 .port_max_mtu = mt7530_port_max_mtu, 3416 .port_stp_state_set = mt7530_stp_state_set, 3417 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3418 .port_bridge_flags = mt7530_port_bridge_flags, 3419 .port_bridge_join = mt7530_port_bridge_join, 3420 .port_bridge_leave = mt7530_port_bridge_leave, 3421 .port_fast_age = mt7530_port_fast_age, 3422 .port_fdb_add = mt7530_port_fdb_add, 3423 .port_fdb_del = mt7530_port_fdb_del, 3424 .port_fdb_dump = mt7530_port_fdb_dump, 3425 .port_mdb_add = mt7530_port_mdb_add, 3426 .port_mdb_del = mt7530_port_mdb_del, 3427 .port_vlan_filtering = mt7530_port_vlan_filtering, 3428 .port_vlan_add = mt7530_port_vlan_add, 3429 .port_vlan_del = mt7530_port_vlan_del, 3430 .port_mirror_add = mt753x_port_mirror_add, 3431 .port_mirror_del = mt753x_port_mirror_del, 3432 .phylink_get_caps = mt753x_phylink_get_caps, 3433 .support_eee = dsa_supports_eee, 3434 .set_mac_eee = mt753x_set_mac_eee, 3435 .conduit_state_change = mt753x_conduit_state_change, 3436 .port_setup_tc = mt753x_setup_tc, 3437 .port_hsr_join = dsa_port_simple_hsr_join, 3438 .port_hsr_leave = dsa_port_simple_hsr_leave, 3439 }; 3440 3441 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3442 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3443 .mac_config = mt753x_phylink_mac_config, 3444 .mac_link_down = mt753x_phylink_mac_link_down, 3445 .mac_link_up = mt753x_phylink_mac_link_up, 3446 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3447 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3448 }; 3449 3450 const struct mt753x_info mt753x_table[] = { 3451 [ID_MT7621] = { 3452 .id = ID_MT7621, 3453 .pcs_ops = &mt7530_pcs_ops, 3454 .sw_setup = mt7530_setup, 3455 .phy_read_c22 = mt7530_phy_read_c22, 3456 .phy_write_c22 = mt7530_phy_write_c22, 3457 .phy_read_c45 = mt7530_phy_read_c45, 3458 .phy_write_c45 = mt7530_phy_write_c45, 3459 .mac_port_get_caps = mt7530_mac_port_get_caps, 3460 .mac_port_config = mt7530_mac_config, 3461 }, 3462 [ID_MT7530] = { 3463 .id = ID_MT7530, 3464 .pcs_ops = &mt7530_pcs_ops, 3465 .sw_setup = mt7530_setup, 3466 .phy_read_c22 = mt7530_phy_read_c22, 3467 .phy_write_c22 = mt7530_phy_write_c22, 3468 .phy_read_c45 = mt7530_phy_read_c45, 3469 .phy_write_c45 = mt7530_phy_write_c45, 3470 .mac_port_get_caps = mt7530_mac_port_get_caps, 3471 .mac_port_config = mt7530_mac_config, 3472 }, 3473 [ID_MT7531] = { 3474 .id = ID_MT7531, 3475 .pcs_ops = &mt7530_pcs_ops, 3476 .sw_setup = mt7531_setup, 3477 .phy_read_c22 = mt7531_ind_c22_phy_read, 3478 .phy_write_c22 = mt7531_ind_c22_phy_write, 3479 .phy_read_c45 = mt7531_ind_c45_phy_read, 3480 .phy_write_c45 = mt7531_ind_c45_phy_write, 3481 .mac_port_get_caps = mt7531_mac_port_get_caps, 3482 .mac_port_config = mt7531_mac_config, 3483 }, 3484 [ID_MT7988] = { 3485 .id = ID_MT7988, 3486 .pcs_ops = &mt7530_pcs_ops, 3487 .sw_setup = mt7988_setup, 3488 .phy_read_c22 = mt7531_ind_c22_phy_read, 3489 .phy_write_c22 = mt7531_ind_c22_phy_write, 3490 .phy_read_c45 = mt7531_ind_c45_phy_read, 3491 .phy_write_c45 = mt7531_ind_c45_phy_write, 3492 .mac_port_get_caps = mt7988_mac_port_get_caps, 3493 }, 3494 [ID_EN7581] = { 3495 .id = ID_EN7581, 3496 .pcs_ops = &mt7530_pcs_ops, 3497 .sw_setup = mt7988_setup, 3498 .phy_read_c22 = mt7531_ind_c22_phy_read, 3499 .phy_write_c22 = mt7531_ind_c22_phy_write, 3500 .phy_read_c45 = mt7531_ind_c45_phy_read, 3501 .phy_write_c45 = mt7531_ind_c45_phy_write, 3502 .mac_port_get_caps = en7581_mac_port_get_caps, 3503 }, 3504 [ID_AN7583] = { 3505 .id = ID_AN7583, 3506 .pcs_ops = &mt7530_pcs_ops, 3507 .sw_setup = mt7988_setup, 3508 .phy_read_c22 = mt7531_ind_c22_phy_read, 3509 .phy_write_c22 = mt7531_ind_c22_phy_write, 3510 .phy_read_c45 = mt7531_ind_c45_phy_read, 3511 .phy_write_c45 = mt7531_ind_c45_phy_write, 3512 .mac_port_get_caps = en7581_mac_port_get_caps, 3513 }, 3514 [ID_EN7528] = { 3515 .id = ID_EN7528, 3516 .pcs_ops = &mt7530_pcs_ops, 3517 .sw_setup = mt7988_setup, 3518 .phy_read_c22 = mt7531_ind_c22_phy_read, 3519 .phy_write_c22 = mt7531_ind_c22_phy_write, 3520 .phy_read_c45 = mt7531_ind_c45_phy_read, 3521 .phy_write_c45 = mt7531_ind_c45_phy_write, 3522 .mac_port_get_caps = en7528_mac_port_get_caps, 3523 }, 3524 }; 3525 EXPORT_SYMBOL_GPL(mt753x_table); 3526 3527 int 3528 mt7530_probe_common(struct mt7530_priv *priv) 3529 { 3530 struct device *dev = priv->dev; 3531 3532 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3533 if (!priv->ds) 3534 return -ENOMEM; 3535 3536 priv->ds->dev = dev; 3537 priv->ds->num_ports = MT7530_NUM_PORTS; 3538 3539 /* Get the hardware identifier from the devicetree node. 3540 * We will need it for some of the clock and regulator setup. 3541 */ 3542 priv->info = of_device_get_match_data(dev); 3543 if (!priv->info) 3544 return -EINVAL; 3545 3546 priv->id = priv->info->id; 3547 priv->dev = dev; 3548 priv->ds->priv = priv; 3549 priv->ds->ops = &mt7530_switch_ops; 3550 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3551 mutex_init(&priv->reg_mutex); 3552 spin_lock_init(&priv->stats_lock); 3553 INIT_DELAYED_WORK(&priv->stats_work, mt7530_stats_poll); 3554 3555 dev_set_drvdata(dev, priv); 3556 3557 return 0; 3558 } 3559 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3560 3561 void 3562 mt7530_remove_common(struct mt7530_priv *priv) 3563 { 3564 dsa_unregister_switch(priv->ds); 3565 3566 mutex_destroy(&priv->reg_mutex); 3567 } 3568 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3569 3570 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3571 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3572 MODULE_LICENSE("GPL"); 3573