1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = OPP_ID_INVALID; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 103 void hubp1_clear_underflow(struct hubp *hubp) 104 { 105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108 } 109 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 111 { 112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113 uint32_t blank_en = blank ? 1 : 0; 114 115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 116 } 117 118 void hubp1_vready_workaround(struct hubp *hubp, 119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 120 { 121 uint32_t value = 0; 122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 123 124 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 125 value = REG_READ(HUBPREQ_DEBUG_DB); 126 127 /* hack mode disable */ 128 value |= 0x100; 129 value &= ~0x1000; 130 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 133 /* if (eco_fix_needed(otg_global_sync_timing) 134 * set HBUBREQ_DEBUG_DB[12] = 1 */ 135 value |= 0x1000; 136 } 137 138 REG_WRITE(HUBPREQ_DEBUG_DB, value); 139 } 140 141 void hubp1_program_tiling( 142 struct hubp *hubp, 143 const struct dc_tiling_info *info, 144 const enum surface_pixel_format pixel_format) 145 { 146 (void)pixel_format; 147 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 148 149 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 150 NUM_PIPES, log_2(info->gfx9.num_pipes), 151 NUM_BANKS, log_2(info->gfx9.num_banks), 152 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 153 NUM_SE, log_2(info->gfx9.num_shader_engines), 154 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 155 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 156 157 REG_UPDATE_4(DCSURF_TILING_CONFIG, 158 SW_MODE, info->gfx9.swizzle, 159 META_LINEAR, info->gfx9.meta_linear, 160 RB_ALIGNED, info->gfx9.rb_aligned, 161 PIPE_ALIGNED, info->gfx9.pipe_aligned); 162 } 163 164 void hubp1_program_size( 165 struct hubp *hubp, 166 enum surface_pixel_format format, 167 const struct plane_size *plane_size, 168 struct dc_plane_dcc_param *dcc) 169 { 170 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 171 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 172 173 /* Program data and meta surface pitch (calculation from addrlib) 174 * 444 or 420 luma 175 */ 176 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 177 ASSERT(plane_size->chroma_pitch != 0); 178 /* Chroma pitch zero can cause system hang! */ 179 180 pitch = plane_size->surface_pitch - 1; 181 meta_pitch = dcc->meta_pitch - 1; 182 pitch_c = plane_size->chroma_pitch - 1; 183 meta_pitch_c = dcc->meta_pitch_c - 1; 184 } else { 185 pitch = plane_size->surface_pitch - 1; 186 meta_pitch = dcc->meta_pitch - 1; 187 pitch_c = 0; 188 meta_pitch_c = 0; 189 } 190 191 if (!dcc->enable) { 192 meta_pitch = 0; 193 meta_pitch_c = 0; 194 } 195 196 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 197 PITCH, pitch, META_PITCH, meta_pitch); 198 199 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 200 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 201 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 202 } 203 204 void hubp1_program_rotation( 205 struct hubp *hubp, 206 enum dc_rotation_angle rotation, 207 bool horizontal_mirror) 208 { 209 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 210 uint32_t mirror; 211 212 213 if (horizontal_mirror) 214 mirror = 1; 215 else 216 mirror = 0; 217 218 /* Program rotation angle and horz mirror - no mirror */ 219 if (rotation == ROTATION_ANGLE_0) 220 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 221 ROTATION_ANGLE, 0, 222 H_MIRROR_EN, mirror); 223 else if (rotation == ROTATION_ANGLE_90) 224 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 225 ROTATION_ANGLE, 1, 226 H_MIRROR_EN, mirror); 227 else if (rotation == ROTATION_ANGLE_180) 228 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 229 ROTATION_ANGLE, 2, 230 H_MIRROR_EN, mirror); 231 else if (rotation == ROTATION_ANGLE_270) 232 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 233 ROTATION_ANGLE, 3, 234 H_MIRROR_EN, mirror); 235 } 236 237 void hubp1_program_pixel_format( 238 struct hubp *hubp, 239 enum surface_pixel_format format) 240 { 241 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 242 uint32_t red_bar = 3; 243 uint32_t blue_bar = 2; 244 245 /* swap for ABGR format */ 246 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 249 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 250 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 251 red_bar = 2; 252 blue_bar = 3; 253 } 254 255 REG_UPDATE_2(HUBPRET_CONTROL, 256 CROSSBAR_SRC_CB_B, blue_bar, 257 CROSSBAR_SRC_CR_R, red_bar); 258 259 /* Mapping is same as ipp programming (cnvc) */ 260 261 switch (format) { 262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 263 REG_UPDATE(DCSURF_SURFACE_CONFIG, 264 SURFACE_PIXEL_FORMAT, 1); 265 break; 266 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 267 REG_UPDATE(DCSURF_SURFACE_CONFIG, 268 SURFACE_PIXEL_FORMAT, 3); 269 break; 270 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 272 REG_UPDATE(DCSURF_SURFACE_CONFIG, 273 SURFACE_PIXEL_FORMAT, 8); 274 break; 275 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 277 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 278 REG_UPDATE(DCSURF_SURFACE_CONFIG, 279 SURFACE_PIXEL_FORMAT, 10); 280 break; 281 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 282 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 283 REG_UPDATE(DCSURF_SURFACE_CONFIG, 284 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 285 break; 286 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 287 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 288 REG_UPDATE(DCSURF_SURFACE_CONFIG, 289 SURFACE_PIXEL_FORMAT, 24); 290 break; 291 292 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 293 REG_UPDATE(DCSURF_SURFACE_CONFIG, 294 SURFACE_PIXEL_FORMAT, 65); 295 break; 296 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 297 REG_UPDATE(DCSURF_SURFACE_CONFIG, 298 SURFACE_PIXEL_FORMAT, 64); 299 break; 300 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 301 REG_UPDATE(DCSURF_SURFACE_CONFIG, 302 SURFACE_PIXEL_FORMAT, 67); 303 break; 304 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 305 REG_UPDATE(DCSURF_SURFACE_CONFIG, 306 SURFACE_PIXEL_FORMAT, 66); 307 break; 308 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 309 REG_UPDATE(DCSURF_SURFACE_CONFIG, 310 SURFACE_PIXEL_FORMAT, 12); 311 break; 312 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 313 REG_UPDATE(DCSURF_SURFACE_CONFIG, 314 SURFACE_PIXEL_FORMAT, 112); 315 break; 316 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 317 REG_UPDATE(DCSURF_SURFACE_CONFIG, 318 SURFACE_PIXEL_FORMAT, 113); 319 break; 320 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 321 REG_UPDATE(DCSURF_SURFACE_CONFIG, 322 SURFACE_PIXEL_FORMAT, 114); 323 break; 324 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 325 REG_UPDATE(DCSURF_SURFACE_CONFIG, 326 SURFACE_PIXEL_FORMAT, 118); 327 break; 328 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 329 REG_UPDATE(DCSURF_SURFACE_CONFIG, 330 SURFACE_PIXEL_FORMAT, 119); 331 break; 332 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 333 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 334 SURFACE_PIXEL_FORMAT, 116, 335 ALPHA_PLANE_EN, 0); 336 break; 337 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 338 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 339 SURFACE_PIXEL_FORMAT, 116, 340 ALPHA_PLANE_EN, 1); 341 break; 342 default: 343 BREAK_TO_DEBUGGER(); 344 break; 345 } 346 347 /* don't see the need of program the xbar in DCN 1.0 */ 348 } 349 350 bool hubp1_program_surface_flip_and_addr( 351 struct hubp *hubp, 352 const struct dc_plane_address *address, 353 bool flip_immediate) 354 { 355 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 356 357 358 //program flip type 359 REG_UPDATE(DCSURF_FLIP_CONTROL, 360 SURFACE_FLIP_TYPE, flip_immediate); 361 362 363 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 364 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 365 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 366 367 } else { 368 // turn off stereo if not in stereo 369 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 370 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 371 } 372 373 374 375 /* HW automatically latch rest of address register on write to 376 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 377 * 378 * program high first and then the low addr, order matters! 379 */ 380 switch (address->type) { 381 case PLN_ADDR_TYPE_GRAPHICS: 382 /* DCN1.0 does not support const color 383 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 384 * base on address->grph.dcc_const_color 385 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 386 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 387 */ 388 389 if (address->grph.addr.quad_part == 0) 390 break; 391 392 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 393 PRIMARY_SURFACE_TMZ, address->tmz_surface, 394 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 395 396 if (address->grph.meta_addr.quad_part != 0) { 397 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 398 PRIMARY_META_SURFACE_ADDRESS_HIGH, 399 address->grph.meta_addr.high_part); 400 401 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 402 PRIMARY_META_SURFACE_ADDRESS, 403 address->grph.meta_addr.low_part); 404 } 405 406 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 407 PRIMARY_SURFACE_ADDRESS_HIGH, 408 address->grph.addr.high_part); 409 410 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 411 PRIMARY_SURFACE_ADDRESS, 412 address->grph.addr.low_part); 413 break; 414 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 415 if (address->video_progressive.luma_addr.quad_part == 0 416 || address->video_progressive.chroma_addr.quad_part == 0) 417 break; 418 419 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 420 PRIMARY_SURFACE_TMZ, address->tmz_surface, 421 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 422 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 423 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 424 425 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 426 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 427 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 428 address->video_progressive.chroma_meta_addr.high_part); 429 430 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 431 PRIMARY_META_SURFACE_ADDRESS_C, 432 address->video_progressive.chroma_meta_addr.low_part); 433 434 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 435 PRIMARY_META_SURFACE_ADDRESS_HIGH, 436 address->video_progressive.luma_meta_addr.high_part); 437 438 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 439 PRIMARY_META_SURFACE_ADDRESS, 440 address->video_progressive.luma_meta_addr.low_part); 441 } 442 443 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 444 PRIMARY_SURFACE_ADDRESS_HIGH_C, 445 address->video_progressive.chroma_addr.high_part); 446 447 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 448 PRIMARY_SURFACE_ADDRESS_C, 449 address->video_progressive.chroma_addr.low_part); 450 451 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 452 PRIMARY_SURFACE_ADDRESS_HIGH, 453 address->video_progressive.luma_addr.high_part); 454 455 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 456 PRIMARY_SURFACE_ADDRESS, 457 address->video_progressive.luma_addr.low_part); 458 break; 459 case PLN_ADDR_TYPE_GRPH_STEREO: 460 if (address->grph_stereo.left_addr.quad_part == 0) 461 break; 462 if (address->grph_stereo.right_addr.quad_part == 0) 463 break; 464 465 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 466 PRIMARY_SURFACE_TMZ, address->tmz_surface, 467 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 468 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 469 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 470 SECONDARY_SURFACE_TMZ, address->tmz_surface, 471 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 472 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 473 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 474 475 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 476 477 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 478 SECONDARY_META_SURFACE_ADDRESS_HIGH, 479 address->grph_stereo.right_meta_addr.high_part); 480 481 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 482 SECONDARY_META_SURFACE_ADDRESS, 483 address->grph_stereo.right_meta_addr.low_part); 484 } 485 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 486 487 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 488 PRIMARY_META_SURFACE_ADDRESS_HIGH, 489 address->grph_stereo.left_meta_addr.high_part); 490 491 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 492 PRIMARY_META_SURFACE_ADDRESS, 493 address->grph_stereo.left_meta_addr.low_part); 494 } 495 496 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 497 SECONDARY_SURFACE_ADDRESS_HIGH, 498 address->grph_stereo.right_addr.high_part); 499 500 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 501 SECONDARY_SURFACE_ADDRESS, 502 address->grph_stereo.right_addr.low_part); 503 504 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 505 PRIMARY_SURFACE_ADDRESS_HIGH, 506 address->grph_stereo.left_addr.high_part); 507 508 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 509 PRIMARY_SURFACE_ADDRESS, 510 address->grph_stereo.left_addr.low_part); 511 break; 512 default: 513 BREAK_TO_DEBUGGER(); 514 break; 515 } 516 517 hubp->request_address = *address; 518 519 return true; 520 } 521 522 void hubp1_clear_tiling(struct hubp *hubp) 523 { 524 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 525 526 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); 527 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); 528 529 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 530 PRIMARY_SURFACE_DCC_EN, 0, 531 PRIMARY_SURFACE_DCC_IND_64B_BLK, 0, 532 SECONDARY_SURFACE_DCC_EN, 0, 533 SECONDARY_SURFACE_DCC_IND_64B_BLK, 0); 534 } 535 536 void hubp1_dcc_control(struct hubp *hubp, bool enable, 537 enum hubp_ind_block_size independent_64b_blks) 538 { 539 uint32_t dcc_en = enable ? 1 : 0; 540 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 541 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 542 543 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 544 PRIMARY_SURFACE_DCC_EN, dcc_en, 545 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 546 SECONDARY_SURFACE_DCC_EN, dcc_en, 547 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 548 } 549 550 void hubp_reset(struct hubp *hubp) 551 { 552 memset(&hubp->pos, 0, sizeof(hubp->pos)); 553 memset(&hubp->att, 0, sizeof(hubp->att)); 554 hubp->cursor_offload = false; 555 } 556 557 void hubp1_program_surface_config( 558 struct hubp *hubp, 559 enum surface_pixel_format format, 560 struct dc_tiling_info *tiling_info, 561 struct plane_size *plane_size, 562 enum dc_rotation_angle rotation, 563 struct dc_plane_dcc_param *dcc, 564 bool horizontal_mirror, 565 unsigned int compat_level) 566 { 567 (void)compat_level; 568 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 569 hubp1_program_tiling(hubp, tiling_info, format); 570 hubp1_program_size(hubp, format, plane_size, dcc); 571 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 572 hubp1_program_pixel_format(hubp, format); 573 } 574 575 void hubp1_program_requestor( 576 struct hubp *hubp, 577 struct _vcs_dpi_display_rq_regs_st *rq_regs) 578 { 579 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 580 581 REG_UPDATE(HUBPRET_CONTROL, 582 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 583 REG_SET_4(DCN_EXPANSION_MODE, 0, 584 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 585 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 586 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 587 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 588 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 589 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 590 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 591 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 592 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 593 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 594 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 595 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 596 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 597 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 598 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 599 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 600 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 601 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 602 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 603 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 604 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 605 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 606 } 607 608 609 void hubp1_program_deadline( 610 struct hubp *hubp, 611 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 612 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 613 { 614 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 615 616 /* DLG - Per hubp */ 617 REG_SET_2(BLANK_OFFSET_0, 0, 618 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 619 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 620 621 REG_SET(BLANK_OFFSET_1, 0, 622 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 623 624 REG_SET(DST_DIMENSIONS, 0, 625 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 626 627 REG_SET_2(DST_AFTER_SCALER, 0, 628 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 629 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 630 631 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 632 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 633 634 /* DLG - Per luma/chroma */ 635 REG_SET(VBLANK_PARAMETERS_1, 0, 636 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 637 638 if (REG(NOM_PARAMETERS_0)) 639 REG_SET(NOM_PARAMETERS_0, 0, 640 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 641 642 if (REG(NOM_PARAMETERS_1)) 643 REG_SET(NOM_PARAMETERS_1, 0, 644 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 645 646 REG_SET(NOM_PARAMETERS_4, 0, 647 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 648 649 REG_SET(NOM_PARAMETERS_5, 0, 650 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 651 652 REG_SET_2(PER_LINE_DELIVERY, 0, 653 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 654 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 655 656 REG_SET(VBLANK_PARAMETERS_2, 0, 657 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 658 659 if (REG(NOM_PARAMETERS_2)) 660 REG_SET(NOM_PARAMETERS_2, 0, 661 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 662 663 if (REG(NOM_PARAMETERS_3)) 664 REG_SET(NOM_PARAMETERS_3, 0, 665 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 666 667 REG_SET(NOM_PARAMETERS_6, 0, 668 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 669 670 REG_SET(NOM_PARAMETERS_7, 0, 671 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 672 673 /* TTU - per hubp */ 674 REG_SET_2(DCN_TTU_QOS_WM, 0, 675 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 676 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 677 678 /* TTU - per luma/chroma */ 679 /* Assumed surf0 is luma and 1 is chroma */ 680 681 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 682 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 683 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 684 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 685 686 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 687 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 688 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 689 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 690 691 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 692 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 693 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 694 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 695 } 696 697 static void hubp1_setup( 698 struct hubp *hubp, 699 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 700 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 701 struct _vcs_dpi_display_rq_regs_st *rq_regs, 702 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 703 { 704 /* otg is locked when this func is called. Register are double buffered. 705 * disable the requestors is not needed 706 */ 707 hubp1_program_requestor(hubp, rq_regs); 708 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 709 hubp1_vready_workaround(hubp, pipe_dest); 710 } 711 712 static void hubp1_setup_interdependent( 713 struct hubp *hubp, 714 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 715 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 716 { 717 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 718 719 REG_SET_2(PREFETCH_SETTINS, 0, 720 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 721 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 722 723 REG_SET(PREFETCH_SETTINS_C, 0, 724 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 725 726 REG_SET_2(VBLANK_PARAMETERS_0, 0, 727 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 728 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 729 730 REG_SET(VBLANK_PARAMETERS_3, 0, 731 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 732 733 REG_SET(VBLANK_PARAMETERS_4, 0, 734 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 735 736 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 737 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 738 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 739 740 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 741 REFCYC_PER_REQ_DELIVERY_PRE, 742 ttu_attr->refcyc_per_req_delivery_pre_l); 743 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 744 REFCYC_PER_REQ_DELIVERY_PRE, 745 ttu_attr->refcyc_per_req_delivery_pre_c); 746 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 747 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 748 749 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 750 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 751 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 752 } 753 754 bool hubp1_is_flip_pending(struct hubp *hubp) 755 { 756 uint32_t flip_pending = 0; 757 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 758 struct dc_plane_address earliest_inuse_address; 759 760 if (hubp && hubp->power_gated) 761 return false; 762 763 REG_GET(DCSURF_FLIP_CONTROL, 764 SURFACE_FLIP_PENDING, &flip_pending); 765 766 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 767 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 768 769 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 770 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 771 772 if (flip_pending) 773 return true; 774 775 if (hubp && 776 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 777 return true; 778 779 return false; 780 } 781 782 static uint32_t aperture_default_system = 1; 783 static uint32_t context0_default_system; /* = 0;*/ 784 785 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 786 struct vm_system_aperture_param *apt) 787 { 788 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 789 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 790 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 791 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 792 793 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 794 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 795 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 796 797 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 798 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 799 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 800 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 801 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 802 803 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 804 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 805 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 806 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 807 808 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 809 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 810 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 811 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 812 } 813 814 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 815 const struct vm_context0_param *vm0) 816 { 817 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 818 /* pte base */ 819 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 820 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 821 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 822 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 823 824 /* pte start */ 825 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 826 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 827 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 828 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 829 830 /* pte end */ 831 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 832 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 833 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 834 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 835 836 /* fault handling */ 837 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 838 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 839 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 840 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 841 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 842 843 /* control: enable VM PTE*/ 844 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 845 ENABLE_L1_TLB, 1, 846 SYSTEM_ACCESS_MODE, 3); 847 } 848 849 void min_set_viewport( 850 struct hubp *hubp, 851 const struct rect *viewport, 852 const struct rect *viewport_c) 853 { 854 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 855 856 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 857 PRI_VIEWPORT_WIDTH, viewport->width, 858 PRI_VIEWPORT_HEIGHT, viewport->height); 859 860 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 861 PRI_VIEWPORT_X_START, viewport->x, 862 PRI_VIEWPORT_Y_START, viewport->y); 863 864 /*for stereo*/ 865 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 866 SEC_VIEWPORT_WIDTH, viewport->width, 867 SEC_VIEWPORT_HEIGHT, viewport->height); 868 869 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 870 SEC_VIEWPORT_X_START, viewport->x, 871 SEC_VIEWPORT_Y_START, viewport->y); 872 873 /* DC supports NV12 only at the moment */ 874 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 875 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 876 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 877 878 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 879 PRI_VIEWPORT_X_START_C, viewport_c->x, 880 PRI_VIEWPORT_Y_START_C, viewport_c->y); 881 882 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 883 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 884 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 885 886 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 887 SEC_VIEWPORT_X_START_C, viewport_c->x, 888 SEC_VIEWPORT_Y_START_C, viewport_c->y); 889 } 890 891 void hubp1_read_state_common(struct hubp *hubp) 892 { 893 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 894 struct dcn_hubp_state *s = &hubp1->state; 895 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 896 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 897 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 898 uint32_t aperture_low_msb, aperture_low_lsb; 899 uint32_t aperture_high_msb, aperture_high_lsb; 900 901 /* Requester */ 902 REG_GET(HUBPRET_CONTROL, 903 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 904 REG_GET_4(DCN_EXPANSION_MODE, 905 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 906 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 907 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 908 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 909 910 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 911 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb); 912 913 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 914 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb); 915 916 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 917 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb); 918 919 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 920 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb); 921 922 // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format 923 rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6); 924 rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6); 925 926 /* DLG - Per hubp */ 927 REG_GET_2(BLANK_OFFSET_0, 928 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 929 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 930 931 REG_GET(BLANK_OFFSET_1, 932 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 933 934 REG_GET(DST_DIMENSIONS, 935 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 936 937 REG_GET_2(DST_AFTER_SCALER, 938 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 939 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 940 941 if (REG(PREFETCH_SETTINS)) 942 REG_GET_2(PREFETCH_SETTINS, 943 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 944 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 945 else 946 REG_GET_2(PREFETCH_SETTINGS, 947 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 948 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 949 950 REG_GET_2(VBLANK_PARAMETERS_0, 951 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 952 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 953 954 REG_GET(REF_FREQ_TO_PIX_FREQ, 955 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 956 957 /* DLG - Per luma/chroma */ 958 REG_GET(VBLANK_PARAMETERS_1, 959 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 960 961 REG_GET(VBLANK_PARAMETERS_3, 962 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 963 964 if (REG(NOM_PARAMETERS_0)) 965 REG_GET(NOM_PARAMETERS_0, 966 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 967 968 if (REG(NOM_PARAMETERS_1)) 969 REG_GET(NOM_PARAMETERS_1, 970 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 971 972 REG_GET(NOM_PARAMETERS_4, 973 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 974 975 REG_GET(NOM_PARAMETERS_5, 976 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 977 978 REG_GET_2(PER_LINE_DELIVERY_PRE, 979 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 980 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 981 982 REG_GET_2(PER_LINE_DELIVERY, 983 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 984 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 985 986 if (REG(PREFETCH_SETTINS_C)) 987 REG_GET(PREFETCH_SETTINS_C, 988 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 989 else 990 REG_GET(PREFETCH_SETTINGS_C, 991 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 992 993 REG_GET(VBLANK_PARAMETERS_2, 994 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 995 996 REG_GET(VBLANK_PARAMETERS_4, 997 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 998 999 if (REG(NOM_PARAMETERS_2)) 1000 REG_GET(NOM_PARAMETERS_2, 1001 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1002 1003 if (REG(NOM_PARAMETERS_3)) 1004 REG_GET(NOM_PARAMETERS_3, 1005 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1006 1007 REG_GET(NOM_PARAMETERS_6, 1008 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1009 1010 REG_GET(NOM_PARAMETERS_7, 1011 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1012 1013 /* TTU - per hubp */ 1014 REG_GET_2(DCN_TTU_QOS_WM, 1015 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1016 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1017 1018 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1019 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1020 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1021 1022 /* TTU - per luma/chroma */ 1023 /* Assumed surf0 is luma and 1 is chroma */ 1024 1025 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1026 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1027 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1028 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1029 1030 REG_GET(DCN_SURF0_TTU_CNTL1, 1031 REFCYC_PER_REQ_DELIVERY_PRE, 1032 &ttu_attr->refcyc_per_req_delivery_pre_l); 1033 1034 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1035 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1036 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1037 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1038 1039 REG_GET(DCN_SURF1_TTU_CNTL1, 1040 REFCYC_PER_REQ_DELIVERY_PRE, 1041 &ttu_attr->refcyc_per_req_delivery_pre_c); 1042 1043 /* Rest of hubp */ 1044 REG_GET(DCSURF_SURFACE_CONFIG, 1045 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1046 1047 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1048 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1049 1050 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1051 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1052 1053 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1054 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1055 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1056 1057 REG_GET_2(DCSURF_SURFACE_CONFIG, 1058 ROTATION_ANGLE, &s->rotation_angle, 1059 H_MIRROR_EN, &s->h_mirror_en); 1060 1061 REG_GET(DCSURF_TILING_CONFIG, 1062 SW_MODE, &s->sw_mode); 1063 1064 REG_GET(DCSURF_SURFACE_CONTROL, 1065 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1066 1067 REG_GET_3(DCHUBP_CNTL, 1068 HUBP_BLANK_EN, &s->blank_en, 1069 HUBP_TTU_DISABLE, &s->ttu_disable, 1070 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1071 1072 REG_GET(HUBP_CLK_CNTL, 1073 HUBP_CLOCK_ENABLE, &s->clock_en); 1074 1075 REG_GET(DCN_GLOBAL_TTU_CNTL, 1076 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1077 1078 REG_GET_2(DCN_TTU_QOS_WM, 1079 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1080 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1081 1082 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1083 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1084 1085 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1086 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1087 1088 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1089 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1090 1091 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1092 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1093 } 1094 1095 void hubp1_read_state(struct hubp *hubp) 1096 { 1097 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1098 struct dcn_hubp_state *s = &hubp1->state; 1099 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1100 1101 hubp1_read_state_common(hubp); 1102 1103 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1104 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1105 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1106 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1107 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1108 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1109 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1110 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1111 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1112 1113 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1114 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1115 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1116 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1117 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1118 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1119 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1120 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1121 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1122 1123 } 1124 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1125 { 1126 enum cursor_pitch hw_pitch; 1127 1128 switch (pitch) { 1129 case 64: 1130 hw_pitch = CURSOR_PITCH_64_PIXELS; 1131 break; 1132 case 128: 1133 hw_pitch = CURSOR_PITCH_128_PIXELS; 1134 break; 1135 case 256: 1136 hw_pitch = CURSOR_PITCH_256_PIXELS; 1137 break; 1138 default: 1139 DC_ERR("Invalid cursor pitch of %d. " 1140 "Only 64/128/256 is supported on DCN.\n", pitch); 1141 hw_pitch = CURSOR_PITCH_64_PIXELS; 1142 break; 1143 } 1144 return hw_pitch; 1145 } 1146 1147 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1148 unsigned int cur_width, 1149 enum dc_cursor_color_format format) 1150 { 1151 enum cursor_lines_per_chunk line_per_chunk; 1152 1153 if (format == CURSOR_MODE_MONO) 1154 /* impl B. expansion in CUR Buffer reader */ 1155 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1156 else if (cur_width <= 32) 1157 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1158 else if (cur_width <= 64) 1159 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1160 else if (cur_width <= 128) 1161 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1162 else 1163 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1164 1165 return line_per_chunk; 1166 } 1167 1168 void hubp1_cursor_set_attributes( 1169 struct hubp *hubp, 1170 const struct dc_cursor_attributes *attr) 1171 { 1172 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1173 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1174 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1175 attr->width, attr->color_format); 1176 1177 hubp->curs_attr = *attr; 1178 1179 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1180 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1181 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1182 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1183 1184 REG_UPDATE_2(CURSOR_SIZE, 1185 CURSOR_WIDTH, attr->width, 1186 CURSOR_HEIGHT, attr->height); 1187 1188 REG_UPDATE_3(CURSOR_CONTROL, 1189 CURSOR_MODE, attr->color_format, 1190 CURSOR_PITCH, hw_pitch, 1191 CURSOR_LINES_PER_CHUNK, lpc); 1192 1193 REG_SET_2(CURSOR_SETTINS, 0, 1194 /* no shift of the cursor HDL schedule */ 1195 CURSOR0_DST_Y_OFFSET, 0, 1196 /* used to shift the cursor chunk request deadline */ 1197 CURSOR0_CHUNK_HDL_ADJUST, 3); 1198 } 1199 1200 void hubp1_cursor_set_position( 1201 struct hubp *hubp, 1202 const struct dc_cursor_position *pos, 1203 const struct dc_cursor_mi_param *param) 1204 { 1205 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1206 int x_pos = pos->x - param->viewport.x; 1207 int y_pos = pos->y - param->viewport.y; 1208 int x_hotspot = pos->x_hotspot; 1209 int y_hotspot = pos->y_hotspot; 1210 int src_x_offset = x_pos - pos->x_hotspot; 1211 int src_y_offset = y_pos - pos->y_hotspot; 1212 int cursor_height = (int)hubp->curs_attr.height; 1213 int cursor_width = (int)hubp->curs_attr.width; 1214 uint32_t dst_x_offset; 1215 uint32_t cur_en = pos->enable ? 1 : 0; 1216 1217 hubp->curs_pos = *pos; 1218 1219 /* 1220 * Guard aganst cursor_set_position() from being called with invalid 1221 * attributes 1222 * 1223 * TODO: Look at combining cursor_set_position() and 1224 * cursor_set_attributes() into cursor_update() 1225 */ 1226 if (hubp->curs_attr.address.quad_part == 0) 1227 return; 1228 1229 // Transform cursor width / height and hotspots for offset calculations 1230 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1231 swap(cursor_height, cursor_width); 1232 swap(x_hotspot, y_hotspot); 1233 1234 if (param->rotation == ROTATION_ANGLE_90) { 1235 // hotspot = (-y, x) 1236 src_x_offset = x_pos - (cursor_width - x_hotspot); 1237 src_y_offset = y_pos - y_hotspot; 1238 } else if (param->rotation == ROTATION_ANGLE_270) { 1239 // hotspot = (y, -x) 1240 src_x_offset = x_pos - x_hotspot; 1241 src_y_offset = y_pos - (cursor_height - y_hotspot); 1242 } 1243 } else if (param->rotation == ROTATION_ANGLE_180) { 1244 // hotspot = (-x, -y) 1245 if (!param->mirror) 1246 src_x_offset = x_pos - (cursor_width - x_hotspot); 1247 1248 src_y_offset = y_pos - (cursor_height - y_hotspot); 1249 } 1250 1251 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1252 dst_x_offset *= param->ref_clk_khz; 1253 dst_x_offset /= param->pixel_clk_khz; 1254 1255 ASSERT(param->h_scale_ratio.value); 1256 1257 if (param->h_scale_ratio.value) 1258 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1259 dc_fixpt_from_int(dst_x_offset), 1260 param->h_scale_ratio)); 1261 1262 if (src_x_offset >= (int)param->viewport.width) 1263 cur_en = 0; /* not visible beyond right edge*/ 1264 1265 if (src_x_offset + cursor_width <= 0) 1266 cur_en = 0; /* not visible beyond left edge*/ 1267 1268 if (src_y_offset >= (int)param->viewport.height) 1269 cur_en = 0; /* not visible beyond bottom edge*/ 1270 1271 if (src_y_offset + cursor_height <= 0) 1272 cur_en = 0; /* not visible beyond top edge*/ 1273 1274 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1275 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1276 1277 REG_UPDATE(CURSOR_CONTROL, 1278 CURSOR_ENABLE, cur_en); 1279 1280 REG_SET_2(CURSOR_POSITION, 0, 1281 CURSOR_X_POSITION, pos->x, 1282 CURSOR_Y_POSITION, pos->y); 1283 1284 REG_SET_2(CURSOR_HOT_SPOT, 0, 1285 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1286 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1287 1288 REG_SET(CURSOR_DST_OFFSET, 0, 1289 CURSOR_DST_X_OFFSET, dst_x_offset); 1290 /* TODO Handle surface pixel formats other than 4:4:4 */ 1291 } 1292 1293 /** 1294 * hubp1_clk_cntl - Disable or enable clocks for DCHUBP 1295 * 1296 * @hubp: hubp struct reference. 1297 * @enable: Set true for enabling gate clock. 1298 * 1299 * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk. 1300 */ 1301 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1302 { 1303 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1304 uint32_t clk_enable = enable ? 1 : 0; 1305 1306 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1307 } 1308 1309 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1310 { 1311 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1312 1313 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1314 } 1315 1316 bool hubp1_in_blank(struct hubp *hubp) 1317 { 1318 uint32_t in_blank; 1319 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1320 1321 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); 1322 return in_blank ? true : false; 1323 } 1324 1325 void hubp1_soft_reset(struct hubp *hubp, bool reset) 1326 { 1327 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1328 1329 REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); 1330 } 1331 1332 /** 1333 * hubp1_set_flip_int - Enable surface flip interrupt 1334 * 1335 * @hubp: hubp struct reference. 1336 */ 1337 void hubp1_set_flip_int(struct hubp *hubp) 1338 { 1339 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1340 1341 REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT, 1342 SURFACE_FLIP_INT_MASK, 1); 1343 1344 return; 1345 } 1346 1347 /** 1348 * hubp1_wait_pipe_read_start - wait for hubp ret path starting read. 1349 * 1350 * @hubp: hubp struct reference. 1351 */ 1352 static void hubp1_wait_pipe_read_start(struct hubp *hubp) 1353 { 1354 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1355 1356 REG_WAIT(HUBPRET_READ_LINE_STATUS, 1357 PIPE_READ_VBLANK, 0, 1358 1, 1000); 1359 } 1360 1361 void hubp1_init(struct hubp *hubp) 1362 { 1363 hubp_reset(hubp); 1364 } 1365 1366 static const struct hubp_funcs dcn10_hubp_funcs = { 1367 .hubp_program_surface_flip_and_addr = 1368 hubp1_program_surface_flip_and_addr, 1369 .hubp_program_surface_config = 1370 hubp1_program_surface_config, 1371 .hubp_is_flip_pending = hubp1_is_flip_pending, 1372 .hubp_setup = hubp1_setup, 1373 .hubp_setup_interdependent = hubp1_setup_interdependent, 1374 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1375 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1376 .set_blank = hubp1_set_blank, 1377 .dcc_control = hubp1_dcc_control, 1378 .hubp_reset = hubp_reset, 1379 .mem_program_viewport = min_set_viewport, 1380 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1381 .set_cursor_attributes = hubp1_cursor_set_attributes, 1382 .set_cursor_position = hubp1_cursor_set_position, 1383 .hubp_disconnect = hubp1_disconnect, 1384 .hubp_clk_cntl = hubp1_clk_cntl, 1385 .hubp_vtg_sel = hubp1_vtg_sel, 1386 .hubp_read_state = hubp1_read_state, 1387 .hubp_clear_underflow = hubp1_clear_underflow, 1388 .hubp_disable_control = hubp1_disable_control, 1389 .hubp_get_underflow_status = hubp1_get_underflow_status, 1390 .hubp_init = hubp1_init, 1391 .hubp_clear_tiling = hubp1_clear_tiling, 1392 1393 .dmdata_set_attributes = NULL, 1394 .dmdata_load = NULL, 1395 .hubp_soft_reset = hubp1_soft_reset, 1396 .hubp_in_blank = hubp1_in_blank, 1397 .hubp_set_flip_int = hubp1_set_flip_int, 1398 .hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start, 1399 }; 1400 1401 /*****************************************/ 1402 /* Constructor, Destructor */ 1403 /*****************************************/ 1404 1405 void dcn10_hubp_construct( 1406 struct dcn10_hubp *hubp1, 1407 struct dc_context *ctx, 1408 uint32_t inst, 1409 const struct dcn_mi_registers *hubp_regs, 1410 const struct dcn_mi_shift *hubp_shift, 1411 const struct dcn_mi_mask *hubp_mask) 1412 { 1413 hubp1->base.funcs = &dcn10_hubp_funcs; 1414 hubp1->base.ctx = ctx; 1415 hubp1->hubp_regs = hubp_regs; 1416 hubp1->hubp_shift = hubp_shift; 1417 hubp1->hubp_mask = hubp_mask; 1418 hubp1->base.inst = inst; 1419 hubp1->base.opp_id = OPP_ID_INVALID; 1420 hubp1->base.mpcc_id = 0xf; 1421 } 1422 1423 1424