1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <linux/iopoll.h> 29 30 #include <drm/display/drm_dsc_helper.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_fixed.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "icl_dsi.h" 38 #include "icl_dsi_regs.h" 39 #include "intel_atomic.h" 40 #include "intel_backlight.h" 41 #include "intel_backlight_regs.h" 42 #include "intel_combo_phy.h" 43 #include "intel_combo_phy_regs.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_ddi.h" 47 #include "intel_de.h" 48 #include "intel_display_regs.h" 49 #include "intel_display_utils.h" 50 #include "intel_dsi.h" 51 #include "intel_dsi_vbt.h" 52 #include "intel_panel.h" 53 #include "intel_pfit.h" 54 #include "intel_vdsc.h" 55 #include "intel_vdsc_regs.h" 56 #include "skl_scaler.h" 57 #include "skl_universal_plane.h" 58 59 static int header_credits_available(struct intel_display *display, 60 enum transcoder dsi_trans) 61 { 62 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 63 >> FREE_HEADER_CREDIT_SHIFT; 64 } 65 66 static int payload_credits_available(struct intel_display *display, 67 enum transcoder dsi_trans) 68 { 69 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 70 >> FREE_PLOAD_CREDIT_SHIFT; 71 } 72 73 static bool wait_for_header_credits(struct intel_display *display, 74 enum transcoder dsi_trans, int hdr_credit) 75 { 76 int ret, available; 77 78 ret = poll_timeout_us(available = header_credits_available(display, dsi_trans), 79 available >= hdr_credit, 80 10, 100, false); 81 if (ret) { 82 drm_err(display->drm, "DSI header credits not released\n"); 83 return false; 84 } 85 86 return true; 87 } 88 89 static bool wait_for_payload_credits(struct intel_display *display, 90 enum transcoder dsi_trans, int payld_credit) 91 { 92 int ret, available; 93 94 ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans), 95 available >= payld_credit, 96 10, 100, false); 97 if (ret) { 98 drm_err(display->drm, "DSI payload credits not released\n"); 99 return false; 100 } 101 102 return true; 103 } 104 105 static enum transcoder dsi_port_to_transcoder(enum port port) 106 { 107 if (port == PORT_A) 108 return TRANSCODER_DSI_0; 109 else 110 return TRANSCODER_DSI_1; 111 } 112 113 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 114 { 115 struct intel_display *display = to_intel_display(encoder); 116 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 117 struct mipi_dsi_device *dsi; 118 enum port port; 119 enum transcoder dsi_trans; 120 int ret; 121 122 /* wait for header/payload credits to be released */ 123 for_each_dsi_port(port, intel_dsi->ports) { 124 dsi_trans = dsi_port_to_transcoder(port); 125 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 126 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT); 127 } 128 129 /* send nop DCS command */ 130 for_each_dsi_port(port, intel_dsi->ports) { 131 dsi = intel_dsi->dsi_hosts[port]->device; 132 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 133 dsi->channel = 0; 134 ret = mipi_dsi_dcs_nop(dsi); 135 if (ret < 0) 136 drm_err(display->drm, 137 "error sending DCS NOP command\n"); 138 } 139 140 /* wait for header credits to be released */ 141 for_each_dsi_port(port, intel_dsi->ports) { 142 dsi_trans = dsi_port_to_transcoder(port); 143 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 144 } 145 146 /* wait for LP TX in progress bit to be cleared */ 147 for_each_dsi_port(port, intel_dsi->ports) { 148 dsi_trans = dsi_port_to_transcoder(port); 149 150 ret = intel_de_wait_for_clear_us(display, 151 DSI_LP_MSG(dsi_trans), 152 LPTX_IN_PROGRESS, 20); 153 if (ret) 154 drm_err(display->drm, "LPTX bit not cleared\n"); 155 } 156 } 157 158 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 159 const struct mipi_dsi_packet *packet) 160 { 161 struct intel_dsi *intel_dsi = host->intel_dsi; 162 struct intel_display *display = to_intel_display(&intel_dsi->base); 163 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 164 const u8 *data = packet->payload; 165 u32 len = packet->payload_length; 166 int i, j; 167 168 /* payload queue can accept *256 bytes*, check limit */ 169 if (len > MAX_PLOAD_CREDIT * 4) { 170 drm_err(display->drm, "payload size exceeds max queue limit\n"); 171 return -EINVAL; 172 } 173 174 for (i = 0; i < len; i += 4) { 175 u32 tmp = 0; 176 177 if (!wait_for_payload_credits(display, dsi_trans, 1)) 178 return -EBUSY; 179 180 for (j = 0; j < min_t(u32, len - i, 4); j++) 181 tmp |= *data++ << 8 * j; 182 183 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); 184 } 185 186 return 0; 187 } 188 189 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 190 const struct mipi_dsi_packet *packet, 191 bool enable_lpdt) 192 { 193 struct intel_dsi *intel_dsi = host->intel_dsi; 194 struct intel_display *display = to_intel_display(&intel_dsi->base); 195 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 196 u32 tmp; 197 198 if (!wait_for_header_credits(display, dsi_trans, 1)) 199 return -EBUSY; 200 201 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); 202 203 if (packet->payload) 204 tmp |= PAYLOAD_PRESENT; 205 else 206 tmp &= ~PAYLOAD_PRESENT; 207 208 tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH); 209 210 if (enable_lpdt) 211 tmp |= LP_DATA_TRANSFER; 212 else 213 tmp |= PIPELINE_FLUSH; 214 215 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 216 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 217 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 218 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 219 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 220 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); 221 222 return 0; 223 } 224 225 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 226 { 227 struct intel_display *display = to_intel_display(crtc_state); 228 u32 mode_flags; 229 enum port port; 230 231 mode_flags = crtc_state->mode_flags; 232 233 /* 234 * case 1 also covers dual link 235 * In case of dual link, frame update should be set on 236 * DSI_0 237 */ 238 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 239 port = PORT_A; 240 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 241 port = PORT_B; 242 else 243 return; 244 245 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, 246 DSI_FRAME_UPDATE_REQUEST); 247 } 248 249 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 250 { 251 struct intel_display *display = to_intel_display(encoder); 252 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 253 enum phy phy; 254 u32 tmp, mask, val; 255 int lane; 256 257 for_each_dsi_phy(phy, intel_dsi->phys) { 258 /* 259 * Program voltage swing and pre-emphasis level values as per 260 * table in BSPEC under DDI buffer programming. 261 */ 262 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 263 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 264 RTERM_SELECT(0x6); 265 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 266 tmp &= ~mask; 267 tmp |= val; 268 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 269 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); 270 271 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 272 RCOMP_SCALAR_MASK; 273 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 274 RCOMP_SCALAR(0x98); 275 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 276 tmp &= ~mask; 277 tmp |= val; 278 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 279 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); 280 281 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 282 CURSOR_COEFF_MASK; 283 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 284 CURSOR_COEFF(0x3f); 285 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); 286 287 /* Bspec: must not use GRP register for write */ 288 for (lane = 0; lane <= 3; lane++) 289 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 290 mask, val); 291 } 292 } 293 294 static void configure_dual_link_mode(struct intel_encoder *encoder, 295 const struct intel_crtc_state *pipe_config) 296 { 297 struct intel_display *display = to_intel_display(encoder); 298 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 299 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 300 u32 dss_ctl1; 301 302 /* FIXME: Move all DSS handling to intel_vdsc.c */ 303 if (DISPLAY_VER(display) >= 12) { 304 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 305 306 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 307 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 308 } else { 309 dss_ctl1_reg = DSS_CTL1; 310 dss_ctl2_reg = DSS_CTL2; 311 } 312 313 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); 314 dss_ctl1 |= SPLITTER_ENABLE; 315 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 316 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 317 318 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 319 const struct drm_display_mode *adjusted_mode = 320 &pipe_config->hw.adjusted_mode; 321 u16 hactive = adjusted_mode->crtc_hdisplay; 322 u16 dl_buffer_depth; 323 324 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 325 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 326 327 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 328 drm_err(display->drm, 329 "DL buffer depth exceed max value\n"); 330 331 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 332 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 333 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 334 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 335 } else { 336 /* Interleave */ 337 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 338 } 339 340 intel_de_write(display, dss_ctl1_reg, dss_ctl1); 341 } 342 343 /* aka DSI 8X clock */ 344 static int afe_clk(struct intel_encoder *encoder, 345 const struct intel_crtc_state *crtc_state) 346 { 347 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 348 int bpp; 349 350 if (crtc_state->dsc.compression_enable) 351 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 352 else 353 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 354 355 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 356 } 357 358 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 359 const struct intel_crtc_state *crtc_state) 360 { 361 struct intel_display *display = to_intel_display(encoder); 362 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 363 enum port port; 364 int afe_clk_khz; 365 int theo_word_clk, act_word_clk; 366 u32 esc_clk_div_m, esc_clk_div_m_phy; 367 368 afe_clk_khz = afe_clk(encoder, crtc_state); 369 370 if (display->platform.alderlake_s || display->platform.alderlake_p) { 371 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 372 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 373 esc_clk_div_m = act_word_clk * 8; 374 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 375 } else { 376 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 377 } 378 379 for_each_dsi_port(port, intel_dsi->ports) { 380 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), 381 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 382 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); 383 } 384 385 for_each_dsi_port(port, intel_dsi->ports) { 386 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), 387 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 388 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 389 } 390 391 if (display->platform.alderlake_s || display->platform.alderlake_p) { 392 for_each_dsi_port(port, intel_dsi->ports) { 393 intel_de_write(display, ADL_MIPIO_DW(port, 8), 394 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 395 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); 396 } 397 } 398 } 399 400 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) 401 { 402 struct intel_display *display = to_intel_display(&intel_dsi->base); 403 enum port port; 404 405 for_each_dsi_port(port, intel_dsi->ports) { 406 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); 407 intel_dsi->io_wakeref[port] = 408 intel_display_power_get(display, 409 port == PORT_A ? 410 POWER_DOMAIN_PORT_DDI_IO_A : 411 POWER_DOMAIN_PORT_DDI_IO_B); 412 } 413 } 414 415 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 416 { 417 struct intel_display *display = to_intel_display(encoder); 418 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 419 enum port port; 420 421 for_each_dsi_port(port, intel_dsi->ports) 422 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 423 0, COMBO_PHY_MODE_DSI); 424 425 get_dsi_io_power_domains(intel_dsi); 426 } 427 428 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 429 { 430 struct intel_display *display = to_intel_display(encoder); 431 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 432 enum phy phy; 433 434 for_each_dsi_phy(phy, intel_dsi->phys) 435 intel_combo_phy_power_up_lanes(display, phy, true, 436 intel_dsi->lane_count, false); 437 } 438 439 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 440 { 441 struct intel_display *display = to_intel_display(encoder); 442 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 443 enum phy phy; 444 u32 tmp; 445 int lane; 446 447 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 448 for_each_dsi_phy(phy, intel_dsi->phys) { 449 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), 450 LOADGEN_SELECT, 0); 451 for (lane = 0; lane <= 3; lane++) 452 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 453 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 454 } 455 456 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 457 for_each_dsi_phy(phy, intel_dsi->phys) { 458 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), 459 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 460 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 461 tmp &= ~FRC_LATENCY_OPTIM_MASK; 462 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 463 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 464 465 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 466 if (display->platform.jasperlake || display->platform.elkhartlake || 467 (DISPLAY_VER(display) >= 12)) { 468 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 469 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 470 471 tmp = intel_de_read(display, 472 ICL_PORT_PCS_DW1_LN(0, phy)); 473 tmp &= ~LATENCY_OPTIM_MASK; 474 tmp |= LATENCY_OPTIM_VAL(0x1); 475 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), 476 tmp); 477 } 478 } 479 480 } 481 482 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 483 { 484 struct intel_display *display = to_intel_display(encoder); 485 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 486 u32 tmp; 487 enum phy phy; 488 489 /* clear common keeper enable bit */ 490 for_each_dsi_phy(phy, intel_dsi->phys) { 491 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 492 tmp &= ~COMMON_KEEPER_EN; 493 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp); 494 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 495 } 496 497 /* 498 * Set SUS Clock Config bitfield to 11b 499 * Note: loadgen select program is done 500 * as part of lane phy sequence configuration 501 */ 502 for_each_dsi_phy(phy, intel_dsi->phys) 503 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, 504 SUS_CLOCK_CONFIG); 505 506 /* Clear training enable to change swing values */ 507 for_each_dsi_phy(phy, intel_dsi->phys) { 508 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 509 tmp &= ~TX_TRAINING_EN; 510 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 511 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 512 } 513 514 /* Program swing and de-emphasis */ 515 dsi_program_swing_and_deemphasis(encoder); 516 517 /* Set training enable to trigger update */ 518 for_each_dsi_phy(phy, intel_dsi->phys) { 519 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 520 tmp |= TX_TRAINING_EN; 521 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 522 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 523 } 524 } 525 526 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 527 { 528 struct intel_display *display = to_intel_display(encoder); 529 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 530 enum port port; 531 int ret; 532 533 for_each_dsi_port(port, intel_dsi->ports) { 534 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 535 536 ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port), 537 DDI_BUF_IS_IDLE, 500); 538 if (ret) 539 drm_err(display->drm, "DDI port:%c buffer idle\n", 540 port_name(port)); 541 } 542 } 543 544 static void 545 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state) 547 { 548 struct intel_display *display = to_intel_display(encoder); 549 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 550 enum port port; 551 enum phy phy; 552 553 /* Program DPHY clock lanes timings */ 554 for_each_dsi_port(port, intel_dsi->ports) 555 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port), 556 intel_dsi->dphy_reg); 557 558 /* Program DPHY data lanes timings */ 559 for_each_dsi_port(port, intel_dsi->ports) 560 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port), 561 intel_dsi->dphy_data_lane_reg); 562 563 /* 564 * If DSI link operating at or below an 800 MHz, 565 * TA_SURE should be override and programmed to 566 * a value '0' inside TA_PARAM_REGISTERS otherwise 567 * leave all fields at HW default values. 568 */ 569 if (DISPLAY_VER(display) == 11) { 570 if (afe_clk(encoder, crtc_state) <= 800000) { 571 for_each_dsi_port(port, intel_dsi->ports) 572 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port), 573 TA_SURE_MASK, 574 TA_SURE_OVERRIDE | TA_SURE(0)); 575 } 576 } 577 578 if (display->platform.jasperlake || display->platform.elkhartlake) { 579 for_each_dsi_phy(phy, intel_dsi->phys) 580 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 581 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 582 } 583 } 584 585 static void 586 gen11_dsi_setup_timings(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_display *display = to_intel_display(encoder); 590 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 591 enum port port; 592 593 /* Program T-INIT master registers */ 594 for_each_dsi_port(port, intel_dsi->ports) 595 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port), 596 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 597 598 /* shadow register inside display core */ 599 for_each_dsi_port(port, intel_dsi->ports) 600 intel_de_write(display, DSI_CLK_TIMING_PARAM(port), 601 intel_dsi->dphy_reg); 602 603 /* shadow register inside display core */ 604 for_each_dsi_port(port, intel_dsi->ports) 605 intel_de_write(display, DSI_DATA_TIMING_PARAM(port), 606 intel_dsi->dphy_data_lane_reg); 607 608 /* shadow register inside display core */ 609 if (DISPLAY_VER(display) == 11) { 610 if (afe_clk(encoder, crtc_state) <= 800000) { 611 for_each_dsi_port(port, intel_dsi->ports) { 612 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port), 613 TA_SURE_MASK, 614 TA_SURE_OVERRIDE | TA_SURE(0)); 615 } 616 } 617 } 618 } 619 620 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 621 { 622 struct intel_display *display = to_intel_display(encoder); 623 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 624 u32 tmp; 625 enum phy phy; 626 627 mutex_lock(&display->dpll.lock); 628 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 629 for_each_dsi_phy(phy, intel_dsi->phys) 630 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 631 632 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 633 mutex_unlock(&display->dpll.lock); 634 } 635 636 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 637 { 638 struct intel_display *display = to_intel_display(encoder); 639 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 640 u32 tmp; 641 enum phy phy; 642 643 mutex_lock(&display->dpll.lock); 644 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 645 for_each_dsi_phy(phy, intel_dsi->phys) 646 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 647 648 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 649 mutex_unlock(&display->dpll.lock); 650 } 651 652 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 653 { 654 struct intel_display *display = to_intel_display(encoder); 655 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 656 bool clock_enabled = false; 657 enum phy phy; 658 u32 tmp; 659 660 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 661 662 for_each_dsi_phy(phy, intel_dsi->phys) { 663 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 664 clock_enabled = true; 665 } 666 667 return clock_enabled; 668 } 669 670 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 671 const struct intel_crtc_state *crtc_state) 672 { 673 struct intel_display *display = to_intel_display(encoder); 674 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 675 struct intel_dpll *pll = crtc_state->intel_dpll; 676 enum phy phy; 677 u32 val; 678 679 mutex_lock(&display->dpll.lock); 680 681 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); 682 for_each_dsi_phy(phy, intel_dsi->phys) { 683 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 684 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 685 } 686 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 687 688 for_each_dsi_phy(phy, intel_dsi->phys) { 689 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 690 } 691 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 692 693 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); 694 695 mutex_unlock(&display->dpll.lock); 696 } 697 698 static void 699 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 700 const struct intel_crtc_state *pipe_config) 701 { 702 struct intel_display *display = to_intel_display(encoder); 703 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 704 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 705 enum pipe pipe = crtc->pipe; 706 u32 tmp; 707 enum port port; 708 enum transcoder dsi_trans; 709 710 for_each_dsi_port(port, intel_dsi->ports) { 711 dsi_trans = dsi_port_to_transcoder(port); 712 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 713 714 if (intel_dsi->eot_pkt) 715 tmp &= ~EOTP_DISABLED; 716 else 717 tmp |= EOTP_DISABLED; 718 719 /* enable link calibration if freq > 1.5Gbps */ 720 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 721 tmp &= ~LINK_CALIBRATION_MASK; 722 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 723 } 724 725 /* configure continuous clock */ 726 tmp &= ~CONTINUOUS_CLK_MASK; 727 if (intel_dsi->clock_stop) 728 tmp |= CLK_ENTER_LP_AFTER_DATA; 729 else 730 tmp |= CLK_HS_CONTINUOUS; 731 732 if (DISPLAY_VER(display) >= 12 && 733 intel_dsi->lp_clock_during_lpm) 734 tmp |= LP_CLK_DURING_LPM; 735 else 736 tmp &= ~LP_CLK_DURING_LPM; 737 738 /* configure buffer threshold limit to minimum */ 739 tmp &= ~PIX_BUF_THRESHOLD_MASK; 740 tmp |= PIX_BUF_THRESHOLD_1_4; 741 742 /* set virtual channel to '0' */ 743 tmp &= ~PIX_VIRT_CHAN_MASK; 744 tmp |= PIX_VIRT_CHAN(0); 745 746 /* program BGR transmission */ 747 if (intel_dsi->bgr_enabled) 748 tmp |= BGR_TRANSMISSION; 749 750 /* select pixel format */ 751 tmp &= ~PIX_FMT_MASK; 752 if (pipe_config->dsc.compression_enable) { 753 tmp |= PIX_FMT_COMPRESSED; 754 } else { 755 switch (intel_dsi->pixel_format) { 756 default: 757 MISSING_CASE(intel_dsi->pixel_format); 758 fallthrough; 759 case MIPI_DSI_FMT_RGB565: 760 tmp |= PIX_FMT_RGB565; 761 break; 762 case MIPI_DSI_FMT_RGB666_PACKED: 763 tmp |= PIX_FMT_RGB666_PACKED; 764 break; 765 case MIPI_DSI_FMT_RGB666: 766 tmp |= PIX_FMT_RGB666_LOOSE; 767 break; 768 case MIPI_DSI_FMT_RGB888: 769 tmp |= PIX_FMT_RGB888; 770 break; 771 } 772 } 773 774 if (DISPLAY_VER(display) >= 12 && 775 is_vid_mode(intel_dsi) && intel_dsi->blanking_pkt) 776 tmp |= BLANKING_PACKET_ENABLE; 777 else 778 tmp &= ~BLANKING_PACKET_ENABLE; 779 780 /* program DSI operation mode */ 781 if (is_vid_mode(intel_dsi)) { 782 tmp &= ~OP_MODE_MASK; 783 switch (intel_dsi->video_mode) { 784 default: 785 MISSING_CASE(intel_dsi->video_mode); 786 fallthrough; 787 case NON_BURST_SYNC_EVENTS: 788 tmp |= VIDEO_MODE_SYNC_EVENT; 789 break; 790 case NON_BURST_SYNC_PULSE: 791 tmp |= VIDEO_MODE_SYNC_PULSE; 792 break; 793 } 794 } else { 795 /* 796 * FIXME: Retrieve this info from VBT. 797 * As per the spec when dsi transcoder is operating 798 * in TE GATE mode, TE comes from GPIO 799 * which is UTIL PIN for DSI 0. 800 * Also this GPIO would not be used for other 801 * purposes is an assumption. 802 */ 803 tmp &= ~OP_MODE_MASK; 804 tmp |= CMD_MODE_TE_GATE; 805 tmp |= TE_SOURCE_GPIO; 806 } 807 808 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 809 } 810 811 /* enable port sync mode if dual link */ 812 if (intel_dsi->dual_link) { 813 for_each_dsi_port(port, intel_dsi->ports) { 814 dsi_trans = dsi_port_to_transcoder(port); 815 intel_de_rmw(display, 816 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 817 0, PORT_SYNC_MODE_ENABLE); 818 } 819 820 /* configure stream splitting */ 821 configure_dual_link_mode(encoder, pipe_config); 822 } 823 824 for_each_dsi_port(port, intel_dsi->ports) { 825 dsi_trans = dsi_port_to_transcoder(port); 826 827 /* select data lane width */ 828 tmp = intel_de_read(display, 829 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 830 tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; 831 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); 832 833 /* select input pipe */ 834 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 835 switch (pipe) { 836 default: 837 MISSING_CASE(pipe); 838 fallthrough; 839 case PIPE_A: 840 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 841 break; 842 case PIPE_B: 843 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 844 break; 845 case PIPE_C: 846 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 847 break; 848 case PIPE_D: 849 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 850 break; 851 } 852 853 /* enable DDI buffer */ 854 tmp |= TRANS_DDI_FUNC_ENABLE; 855 intel_de_write(display, 856 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp); 857 } 858 859 /* wait for link ready */ 860 for_each_dsi_port(port, intel_dsi->ports) { 861 int ret; 862 863 dsi_trans = dsi_port_to_transcoder(port); 864 865 ret = intel_de_wait_for_set_us(display, 866 DSI_TRANS_FUNC_CONF(dsi_trans), 867 LINK_READY, 2500); 868 if (ret) 869 drm_err(display->drm, "DSI link not ready\n"); 870 } 871 } 872 873 static void 874 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 875 const struct intel_crtc_state *crtc_state) 876 { 877 struct intel_display *display = to_intel_display(encoder); 878 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 879 const struct drm_display_mode *adjusted_mode = 880 &crtc_state->hw.adjusted_mode; 881 enum port port; 882 enum transcoder dsi_trans; 883 /* horizontal timings */ 884 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 885 u16 hback_porch; 886 /* vertical timings */ 887 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 888 int mul = 1, div = 1; 889 890 /* 891 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 892 * for slower link speed if DSC is enabled. 893 * 894 * The compression frequency ratio is the ratio between compressed and 895 * non-compressed link speeds, and simplifies down to the ratio between 896 * compressed and non-compressed bpp. 897 */ 898 if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) { 899 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 900 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 901 } 902 903 hactive = adjusted_mode->crtc_hdisplay; 904 905 if (is_vid_mode(intel_dsi)) 906 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 907 else 908 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 909 910 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 911 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 912 hsync_size = hsync_end - hsync_start; 913 hback_porch = (adjusted_mode->crtc_htotal - 914 adjusted_mode->crtc_hsync_end); 915 vactive = adjusted_mode->crtc_vdisplay; 916 917 if (is_vid_mode(intel_dsi)) { 918 vtotal = adjusted_mode->crtc_vtotal; 919 } else { 920 int bpp, line_time_us, byte_clk_period_ns; 921 922 if (crtc_state->dsc.compression_enable) 923 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 924 else 925 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 926 927 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 928 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 929 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 930 } 931 vsync_start = adjusted_mode->crtc_vsync_start; 932 vsync_end = adjusted_mode->crtc_vsync_end; 933 vsync_shift = hsync_start - htotal / 2; 934 935 if (intel_dsi->dual_link) { 936 hactive /= 2; 937 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 938 hactive += intel_dsi->pixel_overlap; 939 htotal /= 2; 940 } 941 942 /* minimum hactive as per bspec: 256 pixels */ 943 if (adjusted_mode->crtc_hdisplay < 256) 944 drm_err(display->drm, "hactive is less then 256 pixels\n"); 945 946 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 947 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 948 drm_err(display->drm, 949 "hactive pixels are not multiple of 4\n"); 950 951 /* program TRANS_HTOTAL register */ 952 for_each_dsi_port(port, intel_dsi->ports) { 953 dsi_trans = dsi_port_to_transcoder(port); 954 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans), 955 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 956 } 957 958 /* TRANS_HSYNC register to be programmed only for video mode */ 959 if (is_vid_mode(intel_dsi)) { 960 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 961 /* BSPEC: hsync size should be atleast 16 pixels */ 962 if (hsync_size < 16) 963 drm_err(display->drm, 964 "hsync size < 16 pixels\n"); 965 } 966 967 if (hback_porch < 16) 968 drm_err(display->drm, "hback porch < 16 pixels\n"); 969 970 if (intel_dsi->dual_link) { 971 hsync_start /= 2; 972 hsync_end /= 2; 973 } 974 975 for_each_dsi_port(port, intel_dsi->ports) { 976 dsi_trans = dsi_port_to_transcoder(port); 977 intel_de_write(display, 978 TRANS_HSYNC(display, dsi_trans), 979 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 980 } 981 } 982 983 /* program TRANS_VTOTAL register */ 984 for_each_dsi_port(port, intel_dsi->ports) { 985 dsi_trans = dsi_port_to_transcoder(port); 986 /* 987 * FIXME: Programming this by assuming progressive mode, since 988 * non-interlaced info from VBT is not saved inside 989 * struct drm_display_mode. 990 * For interlace mode: program required pixel minus 2 991 */ 992 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans), 993 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 994 } 995 996 if (vsync_end < vsync_start || vsync_end > vtotal) 997 drm_err(display->drm, "Invalid vsync_end value\n"); 998 999 if (vsync_start < vactive) 1000 drm_err(display->drm, "vsync_start less than vactive\n"); 1001 1002 /* program TRANS_VSYNC register for video mode only */ 1003 if (is_vid_mode(intel_dsi)) { 1004 for_each_dsi_port(port, intel_dsi->ports) { 1005 dsi_trans = dsi_port_to_transcoder(port); 1006 intel_de_write(display, 1007 TRANS_VSYNC(display, dsi_trans), 1008 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 1009 } 1010 } 1011 1012 /* 1013 * FIXME: It has to be programmed only for video modes and interlaced 1014 * modes. Put the check condition here once interlaced 1015 * info available as described above. 1016 * program TRANS_VSYNCSHIFT register 1017 */ 1018 if (is_vid_mode(intel_dsi)) { 1019 for_each_dsi_port(port, intel_dsi->ports) { 1020 dsi_trans = dsi_port_to_transcoder(port); 1021 intel_de_write(display, 1022 TRANS_VSYNCSHIFT(display, dsi_trans), 1023 vsync_shift); 1024 } 1025 } 1026 1027 /* 1028 * program TRANS_VBLANK register, should be same as vtotal programmed 1029 * 1030 * FIXME get rid of these local hacks and do it right, 1031 * this will not handle eg. delayed vblank correctly. 1032 */ 1033 if (DISPLAY_VER(display) >= 12) { 1034 for_each_dsi_port(port, intel_dsi->ports) { 1035 dsi_trans = dsi_port_to_transcoder(port); 1036 intel_de_write(display, 1037 TRANS_VBLANK(display, dsi_trans), 1038 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 1039 } 1040 } 1041 } 1042 1043 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1044 { 1045 struct intel_display *display = to_intel_display(encoder); 1046 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1047 enum port port; 1048 enum transcoder dsi_trans; 1049 1050 for_each_dsi_port(port, intel_dsi->ports) { 1051 dsi_trans = dsi_port_to_transcoder(port); 1052 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, 1053 TRANSCONF_ENABLE); 1054 1055 /* wait for transcoder to be enabled */ 1056 if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans), 1057 TRANSCONF_STATE_ENABLE, 10)) 1058 drm_err(display->drm, 1059 "DSI transcoder not enabled\n"); 1060 } 1061 } 1062 1063 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1064 const struct intel_crtc_state *crtc_state) 1065 { 1066 struct intel_display *display = to_intel_display(encoder); 1067 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1068 enum port port; 1069 enum transcoder dsi_trans; 1070 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1071 1072 /* 1073 * escape clock count calculation: 1074 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1075 * UI (nsec) = (10^6)/Bitrate 1076 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1077 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1078 */ 1079 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1080 mul = 8 * 1000000; 1081 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1082 divisor); 1083 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1084 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1085 1086 for_each_dsi_port(port, intel_dsi->ports) { 1087 dsi_trans = dsi_port_to_transcoder(port); 1088 1089 /* program hst_tx_timeout */ 1090 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), 1091 HSTX_TIMEOUT_VALUE_MASK, 1092 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1093 1094 /* FIXME: DSI_CALIB_TO */ 1095 1096 /* program lp_rx_host timeout */ 1097 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans), 1098 LPRX_TIMEOUT_VALUE_MASK, 1099 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1100 1101 /* FIXME: DSI_PWAIT_TO */ 1102 1103 /* program turn around timeout */ 1104 intel_de_rmw(display, DSI_TA_TO(dsi_trans), 1105 TA_TIMEOUT_VALUE_MASK, 1106 TA_TIMEOUT_VALUE(ta_timeout)); 1107 } 1108 } 1109 1110 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1111 bool enable) 1112 { 1113 struct intel_display *display = to_intel_display(encoder); 1114 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1115 u32 tmp; 1116 1117 /* 1118 * used as TE i/p for DSI0, 1119 * for dual link/DSI1 TE is from slave DSI1 1120 * through GPIO. 1121 */ 1122 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1123 return; 1124 1125 tmp = intel_de_read(display, UTIL_PIN_CTL); 1126 1127 if (enable) { 1128 tmp |= UTIL_PIN_DIRECTION_INPUT; 1129 tmp |= UTIL_PIN_ENABLE; 1130 } else { 1131 tmp &= ~UTIL_PIN_ENABLE; 1132 } 1133 intel_de_write(display, UTIL_PIN_CTL, tmp); 1134 } 1135 1136 static void 1137 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1138 const struct intel_crtc_state *crtc_state) 1139 { 1140 /* step 4a: power up all lanes of the DDI used by DSI */ 1141 gen11_dsi_power_up_lanes(encoder); 1142 1143 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1144 gen11_dsi_config_phy_lanes_sequence(encoder); 1145 1146 /* step 4c: configure voltage swing and skew */ 1147 gen11_dsi_voltage_swing_program_seq(encoder); 1148 1149 /* setup D-PHY timings */ 1150 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1151 1152 /* enable DDI buffer */ 1153 gen11_dsi_enable_ddi_buffer(encoder); 1154 1155 gen11_dsi_gate_clocks(encoder); 1156 1157 gen11_dsi_setup_timings(encoder, crtc_state); 1158 1159 /* Since transcoder is configured to take events from GPIO */ 1160 gen11_dsi_config_util_pin(encoder, true); 1161 1162 /* step 4h: setup DSI protocol timeouts */ 1163 gen11_dsi_setup_timeouts(encoder, crtc_state); 1164 1165 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1166 gen11_dsi_configure_transcoder(encoder, crtc_state); 1167 } 1168 1169 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1170 { 1171 struct intel_display *display = to_intel_display(encoder); 1172 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1173 struct mipi_dsi_device *dsi; 1174 enum port port; 1175 enum transcoder dsi_trans; 1176 u32 tmp; 1177 int ret; 1178 1179 /* set maximum return packet size */ 1180 for_each_dsi_port(port, intel_dsi->ports) { 1181 dsi_trans = dsi_port_to_transcoder(port); 1182 1183 /* 1184 * FIXME: This uses the number of DW's currently in the payload 1185 * receive queue. This is probably not what we want here. 1186 */ 1187 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans)); 1188 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1189 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1190 tmp = tmp * 4; 1191 dsi = intel_dsi->dsi_hosts[port]->device; 1192 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1193 if (ret < 0) 1194 drm_err(display->drm, 1195 "error setting max return pkt size%d\n", tmp); 1196 } 1197 1198 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1199 1200 /* ensure all panel commands dispatched before enabling transcoder */ 1201 wait_for_cmds_dispatched_to_panel(encoder); 1202 } 1203 1204 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1205 struct intel_encoder *encoder, 1206 const struct intel_crtc_state *crtc_state, 1207 const struct drm_connector_state *conn_state) 1208 { 1209 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1210 1211 intel_dsi_wait_panel_power_cycle(intel_dsi); 1212 1213 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1214 msleep(intel_dsi->panel_on_delay); 1215 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1216 1217 /* step2: enable IO power */ 1218 gen11_dsi_enable_io_power(encoder); 1219 1220 /* step3: enable DSI PLL */ 1221 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1222 } 1223 1224 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1225 struct intel_encoder *encoder, 1226 const struct intel_crtc_state *pipe_config, 1227 const struct drm_connector_state *conn_state) 1228 { 1229 /* step3b */ 1230 gen11_dsi_map_pll(encoder, pipe_config); 1231 1232 /* step4: enable DSI port and DPHY */ 1233 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1234 1235 /* step5: program and powerup panel */ 1236 gen11_dsi_powerup_panel(encoder); 1237 1238 intel_dsc_dsi_pps_write(encoder, pipe_config); 1239 1240 /* step6c: configure transcoder timings */ 1241 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1242 } 1243 1244 /* 1245 * Wa_1409054076:icl,jsl,ehl 1246 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1247 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1248 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1249 * it set while DSI is enabled on pipe B 1250 */ 1251 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1252 enum pipe pipe, bool enable) 1253 { 1254 struct intel_display *display = to_intel_display(encoder); 1255 1256 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) 1257 intel_de_rmw(display, CHICKEN_PAR1_1, 1258 IGNORE_KVMR_PIPE_A, 1259 enable ? IGNORE_KVMR_PIPE_A : 0); 1260 } 1261 1262 /* 1263 * Wa_16012360555:adl-p 1264 * SW will have to program the "LP to HS Wakeup Guardband" 1265 * to account for the repeaters on the HS Request/Ready 1266 * PPI signaling between the Display engine and the DPHY. 1267 */ 1268 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1269 { 1270 struct intel_display *display = to_intel_display(encoder); 1271 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1272 enum port port; 1273 1274 if (DISPLAY_VER(display) == 13) { 1275 for_each_dsi_port(port, intel_dsi->ports) 1276 intel_de_rmw(display, TGL_DSI_CHKN_REG(port), 1277 TGL_DSI_CHKN_LSHS_GB_MASK, 1278 TGL_DSI_CHKN_LSHS_GB(4)); 1279 } 1280 } 1281 1282 static void gen11_dsi_enable(struct intel_atomic_state *state, 1283 struct intel_encoder *encoder, 1284 const struct intel_crtc_state *crtc_state, 1285 const struct drm_connector_state *conn_state) 1286 { 1287 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1288 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1289 1290 /* Wa_1409054076:icl,jsl,ehl */ 1291 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1292 1293 /* Wa_16012360555:adl-p */ 1294 adlp_set_lp_hs_wakeup_gb(encoder); 1295 1296 /* step6d: enable dsi transcoder */ 1297 gen11_dsi_enable_transcoder(encoder); 1298 1299 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1300 1301 /* step7: enable backlight */ 1302 intel_backlight_enable(crtc_state, conn_state); 1303 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1304 1305 intel_panel_prepare(crtc_state, conn_state); 1306 1307 intel_crtc_vblank_on(crtc_state); 1308 } 1309 1310 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1311 { 1312 struct intel_display *display = to_intel_display(encoder); 1313 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1314 enum port port; 1315 enum transcoder dsi_trans; 1316 1317 for_each_dsi_port(port, intel_dsi->ports) { 1318 dsi_trans = dsi_port_to_transcoder(port); 1319 1320 /* disable transcoder */ 1321 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 1322 TRANSCONF_ENABLE, 0); 1323 1324 /* wait for transcoder to be disabled */ 1325 if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans), 1326 TRANSCONF_STATE_ENABLE, 50)) 1327 drm_err(display->drm, 1328 "DSI trancoder not disabled\n"); 1329 } 1330 } 1331 1332 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1333 { 1334 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1335 1336 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1337 1338 /* ensure cmds dispatched to panel */ 1339 wait_for_cmds_dispatched_to_panel(encoder); 1340 } 1341 1342 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1343 { 1344 struct intel_display *display = to_intel_display(encoder); 1345 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1346 enum port port; 1347 enum transcoder dsi_trans; 1348 u32 tmp; 1349 int ret; 1350 1351 /* disable periodic update mode */ 1352 if (is_cmd_mode(intel_dsi)) { 1353 for_each_dsi_port(port, intel_dsi->ports) 1354 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 1355 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1356 } 1357 1358 /* put dsi link in ULPS */ 1359 for_each_dsi_port(port, intel_dsi->ports) { 1360 dsi_trans = dsi_port_to_transcoder(port); 1361 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); 1362 tmp |= LINK_ENTER_ULPS; 1363 tmp &= ~LINK_ULPS_TYPE_LP11; 1364 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp); 1365 1366 ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans), 1367 LINK_IN_ULPS, 10); 1368 if (ret) 1369 drm_err(display->drm, "DSI link not in ULPS\n"); 1370 } 1371 1372 /* disable ddi function */ 1373 for_each_dsi_port(port, intel_dsi->ports) { 1374 dsi_trans = dsi_port_to_transcoder(port); 1375 intel_de_rmw(display, 1376 TRANS_DDI_FUNC_CTL(display, dsi_trans), 1377 TRANS_DDI_FUNC_ENABLE, 0); 1378 } 1379 1380 /* disable port sync mode if dual link */ 1381 if (intel_dsi->dual_link) { 1382 for_each_dsi_port(port, intel_dsi->ports) { 1383 dsi_trans = dsi_port_to_transcoder(port); 1384 intel_de_rmw(display, 1385 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 1386 PORT_SYNC_MODE_ENABLE, 0); 1387 } 1388 } 1389 } 1390 1391 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1392 { 1393 struct intel_display *display = to_intel_display(encoder); 1394 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1395 enum port port; 1396 int ret; 1397 1398 gen11_dsi_ungate_clocks(encoder); 1399 for_each_dsi_port(port, intel_dsi->ports) { 1400 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1401 1402 ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port), 1403 DDI_BUF_IS_IDLE, 8); 1404 1405 if (ret) 1406 drm_err(display->drm, 1407 "DDI port:%c buffer not idle\n", 1408 port_name(port)); 1409 } 1410 gen11_dsi_gate_clocks(encoder); 1411 } 1412 1413 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1414 { 1415 struct intel_display *display = to_intel_display(encoder); 1416 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1417 enum port port; 1418 1419 for_each_dsi_port(port, intel_dsi->ports) { 1420 struct ref_tracker *wakeref; 1421 1422 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1423 intel_display_power_put(display, 1424 port == PORT_A ? 1425 POWER_DOMAIN_PORT_DDI_IO_A : 1426 POWER_DOMAIN_PORT_DDI_IO_B, 1427 wakeref); 1428 } 1429 1430 /* set mode to DDI */ 1431 for_each_dsi_port(port, intel_dsi->ports) 1432 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 1433 COMBO_PHY_MODE_DSI, 0); 1434 } 1435 1436 static void gen11_dsi_disable(struct intel_atomic_state *state, 1437 struct intel_encoder *encoder, 1438 const struct intel_crtc_state *old_crtc_state, 1439 const struct drm_connector_state *old_conn_state) 1440 { 1441 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1442 1443 intel_panel_unprepare(old_conn_state); 1444 1445 /* step1: turn off backlight */ 1446 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1447 intel_backlight_disable(old_conn_state); 1448 } 1449 1450 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1451 struct intel_encoder *encoder, 1452 const struct intel_crtc_state *old_crtc_state, 1453 const struct drm_connector_state *old_conn_state) 1454 { 1455 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1456 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1457 1458 intel_crtc_vblank_off(old_crtc_state); 1459 1460 /* step2d,e: disable transcoder and wait */ 1461 gen11_dsi_disable_transcoder(encoder); 1462 1463 /* Wa_1409054076:icl,jsl,ehl */ 1464 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1465 1466 /* step2f,g: powerdown panel */ 1467 gen11_dsi_powerdown_panel(encoder); 1468 1469 /* step2h,i,j: deconfig trancoder */ 1470 gen11_dsi_deconfigure_trancoder(encoder); 1471 1472 intel_dsc_disable(old_crtc_state); 1473 skl_scaler_disable(old_crtc_state); 1474 1475 /* step3: disable port */ 1476 gen11_dsi_disable_port(encoder); 1477 1478 gen11_dsi_config_util_pin(encoder, false); 1479 1480 /* step4: disable IO power */ 1481 gen11_dsi_disable_io_power(encoder); 1482 1483 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1484 1485 msleep(intel_dsi->panel_off_delay); 1486 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1487 1488 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1489 } 1490 1491 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1492 const struct drm_display_mode *mode) 1493 { 1494 struct intel_display *display = to_intel_display(connector->dev); 1495 enum drm_mode_status status; 1496 1497 status = intel_cpu_transcoder_mode_valid(display, mode); 1498 if (status != MODE_OK) 1499 return status; 1500 1501 /* FIXME: DSC? */ 1502 return intel_dsi_mode_valid(connector, mode); 1503 } 1504 1505 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1506 struct intel_crtc_state *pipe_config) 1507 { 1508 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1509 struct drm_display_mode *adjusted_mode = 1510 &pipe_config->hw.adjusted_mode; 1511 1512 if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) { 1513 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1514 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1515 1516 adjusted_mode->crtc_htotal = 1517 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1518 adjusted_mode->crtc_hsync_start = 1519 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1520 adjusted_mode->crtc_hsync_end = 1521 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1522 } 1523 1524 if (intel_dsi->dual_link) { 1525 adjusted_mode->crtc_hdisplay *= 2; 1526 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1527 adjusted_mode->crtc_hdisplay -= 1528 intel_dsi->pixel_overlap; 1529 adjusted_mode->crtc_htotal *= 2; 1530 } 1531 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1532 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1533 1534 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1535 if (intel_dsi->dual_link) { 1536 adjusted_mode->crtc_hsync_start *= 2; 1537 adjusted_mode->crtc_hsync_end *= 2; 1538 } 1539 } 1540 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1541 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1542 } 1543 1544 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1545 { 1546 struct intel_display *display = to_intel_display(&intel_dsi->base); 1547 enum transcoder dsi_trans; 1548 u32 val; 1549 1550 if (intel_dsi->ports == BIT(PORT_B)) 1551 dsi_trans = TRANSCODER_DSI_1; 1552 else 1553 dsi_trans = TRANSCODER_DSI_0; 1554 1555 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1556 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1557 } 1558 1559 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1560 struct intel_crtc_state *pipe_config) 1561 { 1562 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1563 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1564 I915_MODE_FLAG_DSI_USE_TE0; 1565 else if (intel_dsi->ports == BIT(PORT_B)) 1566 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1567 else 1568 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1569 } 1570 1571 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1572 struct intel_crtc_state *pipe_config) 1573 { 1574 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1576 1577 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1578 1579 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1580 if (intel_dsi->dual_link) 1581 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1582 1583 gen11_dsi_get_timings(encoder, pipe_config); 1584 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1585 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1586 1587 /* Get the details on which TE should be enabled */ 1588 if (is_cmd_mode(intel_dsi)) 1589 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1590 1591 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1592 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1593 } 1594 1595 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1596 const struct intel_crtc_state *crtc_state) 1597 { 1598 struct intel_display *display = to_intel_display(encoder); 1599 struct intel_crtc *intel_crtc; 1600 enum pipe pipe; 1601 1602 if (!crtc_state) 1603 return; 1604 1605 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1606 pipe = intel_crtc->pipe; 1607 1608 /* wa verify 1409054076:icl,jsl,ehl */ 1609 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && 1610 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1611 drm_dbg_kms(display->drm, 1612 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1613 encoder->base.base.id, 1614 encoder->base.name); 1615 } 1616 1617 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1618 struct intel_crtc_state *crtc_state) 1619 { 1620 struct intel_display *display = to_intel_display(encoder); 1621 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1622 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; 1623 bool use_dsc; 1624 int ret; 1625 1626 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1627 if (!use_dsc) 1628 return 0; 1629 1630 if (crtc_state->pipe_bpp < 8 * 3) 1631 return -EINVAL; 1632 1633 /* FIXME: initialize from VBT */ 1634 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1635 1636 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1637 1638 ret = intel_dsc_compute_params(crtc_state); 1639 if (ret) 1640 return ret; 1641 1642 /* DSI specific sanity checks on the common code */ 1643 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); 1644 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); 1645 drm_WARN_ON(display->drm, 1646 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1647 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); 1648 drm_WARN_ON(display->drm, 1649 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1650 1651 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1652 if (ret) 1653 return ret; 1654 1655 intel_dsc_enable_on_crtc(crtc_state); 1656 1657 return 0; 1658 } 1659 1660 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1661 struct intel_crtc_state *pipe_config, 1662 struct drm_connector_state *conn_state) 1663 { 1664 struct intel_display *display = to_intel_display(encoder); 1665 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1666 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1667 struct drm_display_mode *adjusted_mode = 1668 &pipe_config->hw.adjusted_mode; 1669 int ret; 1670 1671 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1672 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1673 1674 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1675 if (ret) 1676 return ret; 1677 1678 ret = intel_pfit_compute_config(pipe_config, conn_state); 1679 if (ret) 1680 return ret; 1681 1682 adjusted_mode->flags = 0; 1683 1684 /* Dual link goes to trancoder DSI'0' */ 1685 if (intel_dsi->ports == BIT(PORT_B)) 1686 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1687 else 1688 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1689 1690 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1691 pipe_config->pipe_bpp = 24; 1692 else 1693 pipe_config->pipe_bpp = 18; 1694 1695 pipe_config->clock_set = true; 1696 1697 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1698 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); 1699 1700 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1701 1702 /* 1703 * In case of TE GATE cmd mode, we 1704 * receive TE from the slave if 1705 * dual link is enabled 1706 */ 1707 if (is_cmd_mode(intel_dsi)) 1708 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1709 1710 return 0; 1711 } 1712 1713 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1714 struct intel_crtc_state *crtc_state) 1715 { 1716 get_dsi_io_power_domains(enc_to_intel_dsi(encoder)); 1717 } 1718 1719 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1720 enum pipe *pipe) 1721 { 1722 struct intel_display *display = to_intel_display(encoder); 1723 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1724 enum transcoder dsi_trans; 1725 struct ref_tracker *wakeref; 1726 enum port port; 1727 bool ret = false; 1728 u32 tmp; 1729 1730 wakeref = intel_display_power_get_if_enabled(display, 1731 encoder->power_domain); 1732 if (!wakeref) 1733 return false; 1734 1735 for_each_dsi_port(port, intel_dsi->ports) { 1736 dsi_trans = dsi_port_to_transcoder(port); 1737 tmp = intel_de_read(display, 1738 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1739 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1740 case TRANS_DDI_EDP_INPUT_A_ON: 1741 *pipe = PIPE_A; 1742 break; 1743 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1744 *pipe = PIPE_B; 1745 break; 1746 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1747 *pipe = PIPE_C; 1748 break; 1749 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1750 *pipe = PIPE_D; 1751 break; 1752 default: 1753 drm_err(display->drm, "Invalid PIPE input\n"); 1754 goto out; 1755 } 1756 1757 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); 1758 ret = tmp & TRANSCONF_ENABLE; 1759 } 1760 out: 1761 intel_display_power_put(display, encoder->power_domain, wakeref); 1762 return ret; 1763 } 1764 1765 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1766 struct intel_crtc_state *crtc_state) 1767 { 1768 if (crtc_state->dsc.compression_enable) { 1769 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1770 crtc_state->uapi.mode_changed = true; 1771 1772 return false; 1773 } 1774 1775 return true; 1776 } 1777 1778 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1779 { 1780 intel_encoder_destroy(encoder); 1781 } 1782 1783 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1784 .destroy = gen11_dsi_encoder_destroy, 1785 }; 1786 1787 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1788 .detect = intel_panel_detect, 1789 .late_register = intel_connector_register, 1790 .early_unregister = intel_connector_unregister, 1791 .destroy = intel_connector_destroy, 1792 .fill_modes = drm_helper_probe_single_connector_modes, 1793 .atomic_get_property = intel_digital_connector_atomic_get_property, 1794 .atomic_set_property = intel_digital_connector_atomic_set_property, 1795 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1796 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1797 }; 1798 1799 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1800 .get_modes = intel_dsi_get_modes, 1801 .mode_valid = gen11_dsi_mode_valid, 1802 .atomic_check = intel_digital_connector_atomic_check, 1803 }; 1804 1805 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1806 struct mipi_dsi_device *dsi) 1807 { 1808 return 0; 1809 } 1810 1811 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1812 struct mipi_dsi_device *dsi) 1813 { 1814 return 0; 1815 } 1816 1817 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1818 const struct mipi_dsi_msg *msg) 1819 { 1820 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1821 struct mipi_dsi_packet dsi_pkt; 1822 ssize_t ret; 1823 bool enable_lpdt = false; 1824 1825 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1826 if (ret < 0) 1827 return ret; 1828 1829 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1830 enable_lpdt = true; 1831 1832 /* only long packet contains payload */ 1833 if (mipi_dsi_packet_format_is_long(msg->type)) { 1834 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1835 if (ret < 0) 1836 return ret; 1837 } 1838 1839 /* send packet header */ 1840 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1841 if (ret < 0) 1842 return ret; 1843 1844 //TODO: add payload receive code if needed 1845 1846 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1847 1848 return ret; 1849 } 1850 1851 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1852 .attach = gen11_dsi_host_attach, 1853 .detach = gen11_dsi_host_detach, 1854 .transfer = gen11_dsi_host_transfer, 1855 }; 1856 1857 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1858 { 1859 struct intel_connector *connector = intel_dsi->attached_connector; 1860 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1861 u32 tlpx_ns; 1862 u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk; 1863 u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk; 1864 1865 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1866 1867 /* 1868 * The clock and data lane prepare timing parameters are in expressed in 1869 * units of 1/4 escape clocks, and all the other timings parameters in 1870 * escape clocks. 1871 */ 1872 tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns); 1873 tclk_prepare_esc_clk = min(tclk_prepare_esc_clk, 7); 1874 1875 tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1876 mipi_config->tclk_prepare, tlpx_ns); 1877 tclk_zero_esc_clk = min(tclk_zero_esc_clk, 15); 1878 1879 tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1880 tclk_pre_esc_clk = min(tclk_pre_esc_clk, 3); 1881 1882 ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns); 1883 ths_prepare_esc_clk = min(ths_prepare_esc_clk, 7); 1884 1885 ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1886 mipi_config->ths_prepare, tlpx_ns); 1887 ths_zero_esc_clk = min(ths_zero_esc_clk, 15); 1888 1889 ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1890 ths_exit_esc_clk = min(ths_exit_esc_clk, 7); 1891 1892 /* clock lane dphy timings */ 1893 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1894 CLK_PREPARE(tclk_prepare_esc_clk) | 1895 CLK_ZERO_OVERRIDE | 1896 CLK_ZERO(tclk_zero_esc_clk) | 1897 CLK_PRE_OVERRIDE | 1898 CLK_PRE(tclk_pre_esc_clk)); 1899 1900 /* data lanes dphy timings */ 1901 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1902 HS_PREPARE(ths_prepare_esc_clk) | 1903 HS_ZERO_OVERRIDE | 1904 HS_ZERO(ths_zero_esc_clk) | 1905 HS_EXIT_OVERRIDE | 1906 HS_EXIT(ths_exit_esc_clk)); 1907 1908 intel_dsi_log_params(intel_dsi); 1909 } 1910 1911 static void icl_dsi_add_properties(struct intel_connector *connector) 1912 { 1913 const struct drm_display_mode *fixed_mode = 1914 intel_panel_preferred_fixed_mode(connector); 1915 1916 intel_attach_scaling_mode_property(&connector->base); 1917 1918 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1919 intel_dsi_get_panel_orientation(connector), 1920 fixed_mode->hdisplay, 1921 fixed_mode->vdisplay); 1922 } 1923 1924 void icl_dsi_init(struct intel_display *display, 1925 const struct intel_bios_encoder_data *devdata) 1926 { 1927 struct intel_dsi *intel_dsi; 1928 struct intel_encoder *encoder; 1929 struct intel_connector *intel_connector; 1930 struct drm_connector *connector; 1931 enum port port; 1932 1933 port = intel_bios_encoder_port(devdata); 1934 if (port == PORT_NONE) 1935 return; 1936 1937 intel_dsi = kzalloc_obj(*intel_dsi); 1938 if (!intel_dsi) 1939 return; 1940 1941 intel_connector = intel_connector_alloc(); 1942 if (!intel_connector) { 1943 kfree(intel_dsi); 1944 return; 1945 } 1946 1947 encoder = &intel_dsi->base; 1948 intel_dsi->attached_connector = intel_connector; 1949 connector = &intel_connector->base; 1950 1951 encoder->devdata = devdata; 1952 1953 /* register DSI encoder with DRM subsystem */ 1954 drm_encoder_init(display->drm, &encoder->base, 1955 &gen11_dsi_encoder_funcs, 1956 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1957 1958 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1959 encoder->pre_enable = gen11_dsi_pre_enable; 1960 encoder->enable = gen11_dsi_enable; 1961 encoder->disable = gen11_dsi_disable; 1962 encoder->post_disable = gen11_dsi_post_disable; 1963 encoder->port = port; 1964 encoder->get_config = gen11_dsi_get_config; 1965 encoder->sync_state = gen11_dsi_sync_state; 1966 encoder->update_pipe = intel_backlight_update; 1967 encoder->compute_config = gen11_dsi_compute_config; 1968 encoder->get_hw_state = gen11_dsi_get_hw_state; 1969 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1970 encoder->type = INTEL_OUTPUT_DSI; 1971 encoder->cloneable = 0; 1972 encoder->pipe_mask = ~0; 1973 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1974 encoder->get_power_domains = gen11_dsi_get_power_domains; 1975 encoder->disable_clock = gen11_dsi_gate_clocks; 1976 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1977 encoder->shutdown = intel_dsi_shutdown; 1978 1979 /* register DSI connector with DRM subsystem */ 1980 drm_connector_init(display->drm, connector, 1981 &gen11_dsi_connector_funcs, 1982 DRM_MODE_CONNECTOR_DSI); 1983 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1984 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1985 intel_connector->get_hw_state = intel_connector_get_hw_state; 1986 1987 /* attach connector to encoder */ 1988 intel_connector_attach_encoder(intel_connector, encoder); 1989 1990 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1991 1992 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 1993 1994 mutex_lock(&display->drm->mode_config.mutex); 1995 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 1996 mutex_unlock(&display->drm->mode_config.mutex); 1997 1998 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 1999 drm_err(display->drm, "DSI fixed mode info missing\n"); 2000 goto err; 2001 } 2002 2003 intel_panel_init(intel_connector, NULL); 2004 2005 intel_backlight_setup(intel_connector, INVALID_PIPE); 2006 2007 if (intel_connector->panel.vbt.dsi.config->dual_link) 2008 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2009 else 2010 intel_dsi->ports = BIT(port); 2011 2012 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2013 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2014 2015 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2016 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2017 2018 for_each_dsi_port(port, intel_dsi->ports) { 2019 struct intel_dsi_host *host; 2020 2021 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2022 if (!host) 2023 goto err; 2024 2025 intel_dsi->dsi_hosts[port] = host; 2026 } 2027 2028 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2029 drm_dbg_kms(display->drm, "no device found\n"); 2030 goto err; 2031 } 2032 2033 icl_dphy_param_init(intel_dsi); 2034 2035 icl_dsi_add_properties(intel_connector); 2036 return; 2037 2038 err: 2039 drm_connector_cleanup(connector); 2040 drm_encoder_cleanup(&encoder->base); 2041 kfree(intel_dsi); 2042 kfree(intel_connector); 2043 } 2044