1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
42 * 82566DC Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
44 * 82566DM Gigabit Network Connection
45 * 82566MC Gigabit Network Connection
46 * 82566MM Gigabit Network Connection
47 * 82567LM Gigabit Network Connection
48 * 82567LF Gigabit Network Connection
49 * 82567V Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
54 * 82567LM-3 Gigabit Network Connection
55 * 82567LM-4 Gigabit Network Connection
56 * 82577LM Gigabit Network Connection
57 * 82577LC Gigabit Network Connection
58 * 82578DM Gigabit Network Connection
59 * 82578DC Gigabit Network Connection
60 * 82579LM Gigabit Network Connection
61 * 82579V Gigabit Network Connection
62 * Ethernet Connection I217-LM
63 * Ethernet Connection I217-V
64 * Ethernet Connection I218-V
65 * Ethernet Connection I218-LM
66 * Ethernet Connection (2) I218-LM
67 * Ethernet Connection (2) I218-V
68 * Ethernet Connection (3) I218-LM
69 * Ethernet Connection (3) I218-V
70 */
71
72 #include "e1000_api.h"
73
74 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
75 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
81 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
82 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
85 u8 *mc_addr_list,
86 u32 mc_addr_count);
87 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
90 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 bool active);
92 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 bool active);
94 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 u16 words, u16 *data);
96 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 u16 *data);
98 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 u16 words, u16 *data);
100 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
103 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 u16 *data);
105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
106 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
111 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
112 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 u16 *speed, u16 *duplex);
114 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
118 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
121 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
123 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 u32 offset, u8 *data);
128 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 u8 size, u16 *data);
130 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 u32 *data);
132 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 *data);
134 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 u32 offset, u32 data);
136 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 u32 offset, u32 dword);
138 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 u32 offset, u16 *data);
140 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 u32 offset, u8 byte);
142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
149
150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151 /* Offset 04h HSFSTS */
152 union ich8_hws_flash_status {
153 struct ich8_hsfsts {
154 u16 flcdone:1; /* bit 0 Flash Cycle Done */
155 u16 flcerr:1; /* bit 1 Flash Cycle Error */
156 u16 dael:1; /* bit 2 Direct Access error Log */
157 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159 u16 reserved1:2; /* bit 13:6 Reserved */
160 u16 reserved2:6; /* bit 13:6 Reserved */
161 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
163 } hsf_status;
164 u16 regval;
165 };
166
167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168 /* Offset 06h FLCTL */
169 union ich8_hws_flash_ctrl {
170 struct ich8_hsflctl {
171 u16 flcgo:1; /* 0 Flash Cycle Go */
172 u16 flcycle:2; /* 2:1 Flash Cycle */
173 u16 reserved:5; /* 7:3 Reserved */
174 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
175 u16 flockdn:6; /* 15:10 Reserved */
176 } hsf_ctrl;
177 u16 regval;
178 };
179
180 /* ICH Flash Region Access Permissions */
181 union ich8_hws_flash_regacc {
182 struct ich8_flracc {
183 u32 grra:8; /* 0:7 GbE region Read Access */
184 u32 grwa:8; /* 8:15 GbE region Write Access */
185 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
187 } hsf_flregacc;
188 u16 regval;
189 };
190
191 /**
192 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
193 * @hw: pointer to the HW structure
194 *
195 * Test access to the PHY registers by reading the PHY ID registers. If
196 * the PHY ID is already known (e.g. resume path) compare it with known ID,
197 * otherwise assume the read PHY ID is correct if it is valid.
198 *
199 * Assumes the sw/fw/hw semaphore is already acquired.
200 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
202 {
203 u16 phy_reg = 0;
204 u32 phy_id = 0;
205 u32 phy_retries;
206 s32 ret_val = 0;
207 u16 retry_count;
208 u32 mac_reg = 0;
209
210 for (retry_count = 0; retry_count < 2; retry_count++) {
211 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
212 if (ret_val || (phy_reg == 0xFFFF))
213 continue;
214 phy_id = (u32)phy_reg << 16;
215
216 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
217 if (ret_val || (phy_reg == 0xFFFF)) {
218 phy_id = 0;
219 continue;
220 }
221 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
222 break;
223 }
224
225 if (hw->phy.id) {
226 if (hw->phy.id == phy_id)
227 goto out;
228 } else if (phy_id) {
229 hw->phy.id = phy_id;
230 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
231 goto out;
232 }
233
234 /* In case the PHY needs to be in mdio slow mode,
235 * set slow mode and try to get the PHY id again.
236 */
237 if (hw->mac.type < e1000_pch_lpt) {
238 hw->phy.ops.release(hw);
239 ret_val = e1000_set_mdio_slow_mode_hv(hw);
240 if (!ret_val)
241 ret_val = e1000_get_phy_id(hw);
242 hw->phy.ops.acquire(hw);
243 }
244
245 if (ret_val)
246 return false;
247 out:
248 if (hw->mac.type >= e1000_pch_lpt) {
249 /* Only unforce SMBus if ME is not active */
250 if (!(E1000_READ_REG(hw, E1000_FWSM) &
251 E1000_ICH_FWSM_FW_VALID)) {
252 /* Switching the PHY interface returns an expected MDI
253 * error. Do not retry that transaction.
254 */
255 e1000_disable_phy_retry_mechanism(hw, &phy_retries);
256
257 /* Unforce SMBus mode in PHY */
258 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
259 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
260 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
261
262 e1000_enable_phy_retry_mechanism(hw, phy_retries);
263
264 /* Unforce SMBus mode in MAC */
265 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
266 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
267 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
268 }
269 }
270
271 return true;
272 }
273
274 /**
275 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
276 * @hw: pointer to the HW structure
277 *
278 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
279 * used to reset the PHY to a quiescent state when necessary.
280 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)281 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
282 {
283 u32 mac_reg;
284
285 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
286
287 /* Set Phy Config Counter to 50msec */
288 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
289 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
290 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
291 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
292
293 /* Toggle LANPHYPC Value bit */
294 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
295 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
296 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
297 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
298 E1000_WRITE_FLUSH(hw);
299 msec_delay(1);
300 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
301 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
302 E1000_WRITE_FLUSH(hw);
303
304 if (hw->mac.type < e1000_pch_lpt) {
305 msec_delay(50);
306 } else {
307 u16 count = 20;
308
309 do {
310 msec_delay(5);
311 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
312 E1000_CTRL_EXT_LPCD) && count--);
313
314 msec_delay(30);
315 }
316 }
317
318 /**
319 * e1000_reconfigure_k1_exit_timeout - Reconfigure K1 parameters
320 * @hw: pointer to the HW structure
321 *
322 * Reconfigure the PHY power-down state and K1 exit timeout to avoid a
323 * MAC/PHY clock synchronization problem on Meteor Lake and newer PCH.
324 * The caller must hold the PHY semaphore.
325 **/
326 static s32
e1000_reconfigure_k1_exit_timeout(struct e1000_hw * hw)327 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
328 {
329 u32 fextnvm12;
330 u16 phy_timeout;
331 s32 ret_val;
332
333 DEBUGFUNC("e1000_reconfigure_k1_exit_timeout");
334
335 if (hw->mac.type < e1000_pch_mtp ||
336 hw->mac.type >= e1000_82575)
337 return E1000_SUCCESS;
338
339 /* Change the K1 power-down state from P0s to P1. */
340 fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12);
341 fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK;
342 fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1;
343 E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12);
344
345 msec_delay_irq(1);
346
347 ret_val = hw->phy.ops.read_reg_locked(hw, E1000_PHY_TIMEOUTS_REG,
348 &phy_timeout);
349 if (ret_val)
350 return ret_val;
351
352 phy_timeout &= ~E1000_PHY_TIMEOUTS_K1_EXIT_TO_MASK;
353 phy_timeout |= 0xF00;
354 return hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG,
355 phy_timeout);
356 }
357
358 /**
359 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
360 * @hw: pointer to the HW structure
361 *
362 * Workarounds/flow necessary for PHY initialization during driver load
363 * and resume paths.
364 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)365 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
366 {
367 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
368 u32 phy_retries;
369 s32 ret_val;
370
371 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
372
373 /* Gate automatic PHY configuration by hardware on managed and
374 * non-managed 82579 and newer adapters.
375 */
376 e1000_gate_hw_phy_config_ich8lan(hw, true);
377
378 /* It is not possible to be certain of the current state of ULP
379 * so forcibly disable it.
380 */
381 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
382 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
383 if (ret_val)
384 ERROR_REPORT("Failed to disable ULP\n");
385
386 ret_val = hw->phy.ops.acquire(hw);
387 if (ret_val) {
388 DEBUGOUT("Failed to initialize PHY flow\n");
389 goto out;
390 }
391
392 /* The PHY might be inaccessible while its interface is changing. */
393 e1000_disable_phy_retry_mechanism(hw, &phy_retries);
394
395 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
396 * inaccessible and resetting the PHY is not blocked, toggle the
397 * LANPHYPC Value bit to force the interconnect to PCIe mode.
398 */
399 switch (hw->mac.type) {
400 case e1000_pch_mtp:
401 case e1000_pch_ptp:
402 case e1000_pch_nvp:
403 /* The PHY might be inaccessible here, so do not propagate a
404 * failure from this preliminary programming attempt.
405 */
406 if (e1000_reconfigure_k1_exit_timeout(hw))
407 DEBUGOUT("Failed to reconfigure K1 exit timeout\n");
408 /* FALLTHROUGH */
409 case e1000_pch_lpt:
410 case e1000_pch_spt:
411 case e1000_pch_cnp:
412 case e1000_pch_tgp:
413 case e1000_pch_adp:
414 if (e1000_phy_is_accessible_pchlan(hw))
415 break;
416
417 /* Before toggling LANPHYPC, see if PHY is accessible by
418 * forcing MAC to SMBus mode first.
419 */
420 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
421 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
422 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
423
424 /* Wait 50 milliseconds for MAC to finish any retries
425 * that it might be trying to perform from previous
426 * attempts to acknowledge any phy read requests.
427 */
428 msec_delay(50);
429
430 /* FALLTHROUGH */
431 case e1000_pch2lan:
432 if (e1000_phy_is_accessible_pchlan(hw))
433 break;
434
435 /* FALLTHROUGH */
436 case e1000_pchlan:
437 if ((hw->mac.type == e1000_pchlan) &&
438 (fwsm & E1000_ICH_FWSM_FW_VALID))
439 break;
440
441 if (hw->phy.ops.check_reset_block(hw)) {
442 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
443 ret_val = -E1000_ERR_PHY;
444 break;
445 }
446
447 /* Toggle LANPHYPC Value bit */
448 e1000_toggle_lanphypc_pch_lpt(hw);
449 if (hw->mac.type >= e1000_pch_lpt) {
450 if (e1000_phy_is_accessible_pchlan(hw))
451 break;
452
453 /* Toggling LANPHYPC brings the PHY out of SMBus mode
454 * so ensure that the MAC is also out of SMBus mode
455 */
456 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
457 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
458 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
459
460 if (e1000_phy_is_accessible_pchlan(hw))
461 break;
462
463 ret_val = -E1000_ERR_PHY;
464 }
465 break;
466 default:
467 break;
468 }
469
470 e1000_enable_phy_retry_mechanism(hw, phy_retries);
471 hw->phy.ops.release(hw);
472 if (!ret_val) {
473
474 /* Check to see if able to reset PHY. Print error if not */
475 if (hw->phy.ops.check_reset_block(hw)) {
476 ERROR_REPORT("Reset blocked by ME\n");
477 goto out;
478 }
479
480 /* Reset the PHY before any access to it. Doing so, ensures
481 * that the PHY is in a known good state before we read/write
482 * PHY registers. The generic reset is sufficient here,
483 * because we haven't determined the PHY type yet.
484 */
485 ret_val = e1000_phy_hw_reset_generic(hw);
486 if (ret_val)
487 goto out;
488
489 /* On a successful reset, possibly need to wait for the PHY
490 * to quiesce to an accessible state before returning control
491 * to the calling function. If the PHY does not quiesce, then
492 * return E1000E_BLK_PHY_RESET, as this is the condition that
493 * the PHY is in.
494 */
495 ret_val = hw->phy.ops.check_reset_block(hw);
496 if (ret_val) {
497 ERROR_REPORT("ME blocked access to PHY after reset\n");
498 goto out;
499 }
500
501 if (hw->mac.type >= e1000_pch_mtp &&
502 hw->mac.type < e1000_82575) {
503 ret_val = hw->phy.ops.acquire(hw);
504 if (ret_val) {
505 DEBUGOUT("Failed to acquire PHY for K1 setup\n");
506 goto out;
507 }
508 ret_val = e1000_reconfigure_k1_exit_timeout(hw);
509 hw->phy.ops.release(hw);
510 }
511 }
512
513 out:
514 /* Ungate automatic PHY configuration on non-managed 82579 */
515 if ((hw->mac.type == e1000_pch2lan) &&
516 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
517 msec_delay(10);
518 e1000_gate_hw_phy_config_ich8lan(hw, false);
519 }
520
521 return ret_val;
522 }
523
524 /**
525 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
526 * @hw: pointer to the HW structure
527 *
528 * Initialize family-specific PHY parameters and function pointers.
529 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)530 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
531 {
532 struct e1000_phy_info *phy = &hw->phy;
533 s32 ret_val;
534
535 DEBUGFUNC("e1000_init_phy_params_pchlan");
536
537 phy->addr = 1;
538 phy->reset_delay_us = 100;
539
540 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
541 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
542 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
543 phy->ops.set_page = e1000_set_page_igp;
544 phy->ops.read_reg = e1000_read_phy_reg_hv;
545 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
546 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
547 phy->ops.release = e1000_release_swflag_ich8lan;
548 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
549 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
550 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
551 phy->ops.write_reg = e1000_write_phy_reg_hv;
552 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
553 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
554 phy->ops.power_up = e1000_power_up_phy_copper;
555 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
556 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
557
558 phy->id = e1000_phy_unknown;
559 if (hw->mac.type >= e1000_pch_mtp &&
560 hw->mac.type < e1000_82575)
561 phy->current_retry_counter = 2;
562
563 ret_val = e1000_init_phy_workarounds_pchlan(hw);
564 if (ret_val)
565 return ret_val;
566
567 if (phy->id == e1000_phy_unknown)
568 switch (hw->mac.type) {
569 default:
570 ret_val = e1000_get_phy_id(hw);
571 if (ret_val)
572 return ret_val;
573 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
574 break;
575 /* FALLTHROUGH */
576 case e1000_pch2lan:
577 case e1000_pch_lpt:
578 case e1000_pch_spt:
579 case e1000_pch_cnp:
580 case e1000_pch_tgp:
581 case e1000_pch_adp:
582 case e1000_pch_mtp:
583 case e1000_pch_ptp:
584 case e1000_pch_nvp:
585 /* In case the PHY needs to be in mdio slow mode,
586 * set slow mode and try to get the PHY id again.
587 */
588 ret_val = e1000_set_mdio_slow_mode_hv(hw);
589 if (ret_val)
590 return ret_val;
591 ret_val = e1000_get_phy_id(hw);
592 if (ret_val)
593 return ret_val;
594 break;
595 }
596 phy->type = e1000_get_phy_type_from_id(phy->id);
597
598 switch (phy->type) {
599 case e1000_phy_82577:
600 case e1000_phy_82579:
601 case e1000_phy_i217:
602 phy->ops.check_polarity = e1000_check_polarity_82577;
603 phy->ops.force_speed_duplex =
604 e1000_phy_force_speed_duplex_82577;
605 phy->ops.get_cable_length = e1000_get_cable_length_82577;
606 phy->ops.get_info = e1000_get_phy_info_82577;
607 phy->ops.commit = e1000_phy_sw_reset_generic;
608 break;
609 case e1000_phy_82578:
610 phy->ops.check_polarity = e1000_check_polarity_m88;
611 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
612 phy->ops.get_cable_length = e1000_get_cable_length_m88;
613 phy->ops.get_info = e1000_get_phy_info_m88;
614 break;
615 default:
616 ret_val = -E1000_ERR_PHY;
617 break;
618 }
619
620 return ret_val;
621 }
622
623 /**
624 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
625 * @hw: pointer to the HW structure
626 *
627 * Initialize family-specific PHY parameters and function pointers.
628 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)629 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
630 {
631 struct e1000_phy_info *phy = &hw->phy;
632 s32 ret_val;
633 u16 i = 0;
634
635 DEBUGFUNC("e1000_init_phy_params_ich8lan");
636
637 phy->addr = 1;
638 phy->reset_delay_us = 100;
639
640 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
641 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
642 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
643 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
644 phy->ops.read_reg = e1000_read_phy_reg_igp;
645 phy->ops.release = e1000_release_swflag_ich8lan;
646 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
647 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
648 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
649 phy->ops.write_reg = e1000_write_phy_reg_igp;
650 phy->ops.power_up = e1000_power_up_phy_copper;
651 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
652
653 /* We may need to do this twice - once for IGP and if that fails,
654 * we'll set BM func pointers and try again
655 */
656 ret_val = e1000_determine_phy_address(hw);
657 if (ret_val) {
658 phy->ops.write_reg = e1000_write_phy_reg_bm;
659 phy->ops.read_reg = e1000_read_phy_reg_bm;
660 ret_val = e1000_determine_phy_address(hw);
661 if (ret_val) {
662 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
663 return ret_val;
664 }
665 }
666
667 phy->id = 0;
668 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
669 (i++ < 100)) {
670 msec_delay(1);
671 ret_val = e1000_get_phy_id(hw);
672 if (ret_val)
673 return ret_val;
674 }
675
676 /* Verify phy id */
677 switch (phy->id) {
678 case IGP03E1000_E_PHY_ID:
679 phy->type = e1000_phy_igp_3;
680 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
681 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
682 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
683 phy->ops.get_info = e1000_get_phy_info_igp;
684 phy->ops.check_polarity = e1000_check_polarity_igp;
685 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
686 break;
687 case IFE_E_PHY_ID:
688 case IFE_PLUS_E_PHY_ID:
689 case IFE_C_E_PHY_ID:
690 phy->type = e1000_phy_ife;
691 phy->autoneg_mask = E1000_ALL_NOT_GIG;
692 phy->ops.get_info = e1000_get_phy_info_ife;
693 phy->ops.check_polarity = e1000_check_polarity_ife;
694 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
695 break;
696 case BME1000_E_PHY_ID:
697 phy->type = e1000_phy_bm;
698 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
699 phy->ops.read_reg = e1000_read_phy_reg_bm;
700 phy->ops.write_reg = e1000_write_phy_reg_bm;
701 phy->ops.commit = e1000_phy_sw_reset_generic;
702 phy->ops.get_info = e1000_get_phy_info_m88;
703 phy->ops.check_polarity = e1000_check_polarity_m88;
704 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
705 break;
706 default:
707 return -E1000_ERR_PHY;
708 break;
709 }
710
711 return E1000_SUCCESS;
712 }
713
714 /**
715 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
716 * @hw: pointer to the HW structure
717 *
718 * Initialize family-specific NVM parameters and function
719 * pointers.
720 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)721 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
722 {
723 struct e1000_nvm_info *nvm = &hw->nvm;
724 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
725 u32 gfpreg, sector_base_addr, sector_end_addr;
726 u16 i;
727 u32 nvm_size;
728
729 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
730
731 nvm->type = e1000_nvm_flash_sw;
732
733 if (hw->mac.type >= e1000_pch_spt) {
734 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
735 * STRAP register. This is because in SPT the GbE Flash region
736 * is no longer accessed through the flash registers. Instead,
737 * the mechanism has changed, and the Flash region access
738 * registers are now implemented in GbE memory space.
739 */
740 nvm->flash_base_addr = 0;
741 nvm_size =
742 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
743 * NVM_SIZE_MULTIPLIER;
744 nvm->flash_bank_size = nvm_size / 2;
745 /* Adjust to word count */
746 nvm->flash_bank_size /= sizeof(u16);
747 /* Set the base address for flash register access */
748 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
749 } else {
750 /* Can't read flash registers if register set isn't mapped. */
751 if (!hw->flash_address) {
752 DEBUGOUT("ERROR: Flash registers not mapped\n");
753 return -E1000_ERR_CONFIG;
754 }
755
756 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
757
758 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
759 * Add 1 to sector_end_addr since this sector is included in
760 * the overall size.
761 */
762 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
763 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
764
765 /* flash_base_addr is byte-aligned */
766 nvm->flash_base_addr = sector_base_addr
767 << FLASH_SECTOR_ADDR_SHIFT;
768
769 /* find total size of the NVM, then cut in half since the total
770 * size represents two separate NVM banks.
771 */
772 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
773 << FLASH_SECTOR_ADDR_SHIFT);
774 nvm->flash_bank_size /= 2;
775 /* Adjust to word count */
776 nvm->flash_bank_size /= sizeof(u16);
777 }
778
779 nvm->word_size = E1000_SHADOW_RAM_WORDS;
780
781 /* Clear shadow ram */
782 for (i = 0; i < nvm->word_size; i++) {
783 dev_spec->shadow_ram[i].modified = false;
784 dev_spec->shadow_ram[i].value = 0xFFFF;
785 }
786
787 /* Function Pointers */
788 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
789 nvm->ops.release = e1000_release_nvm_ich8lan;
790 if (hw->mac.type >= e1000_pch_spt) {
791 nvm->ops.read = e1000_read_nvm_spt;
792 nvm->ops.update = e1000_update_nvm_checksum_spt;
793 } else {
794 nvm->ops.read = e1000_read_nvm_ich8lan;
795 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
796 }
797 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
798 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
799 nvm->ops.write = e1000_write_nvm_ich8lan;
800
801 return E1000_SUCCESS;
802 }
803
804 /**
805 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
806 * @hw: pointer to the HW structure
807 *
808 * Initialize family-specific MAC parameters and function
809 * pointers.
810 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)811 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
812 {
813 struct e1000_mac_info *mac = &hw->mac;
814
815 DEBUGFUNC("e1000_init_mac_params_ich8lan");
816
817 /* Set media type function pointer */
818 hw->phy.media_type = e1000_media_type_copper;
819
820 /* Set mta register count */
821 mac->mta_reg_count = 32;
822 /* Set rar entry count */
823 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
824 if (mac->type == e1000_ich8lan)
825 mac->rar_entry_count--;
826 /* Set if part includes ASF firmware */
827 mac->asf_firmware_present = true;
828 /* FWSM register */
829 mac->has_fwsm = true;
830 /* ARC subsystem not supported */
831 mac->arc_subsystem_valid = false;
832 /* Adaptive IFS supported */
833 mac->adaptive_ifs = true;
834
835 /* Function pointers */
836
837 /* bus type/speed/width */
838 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
839 /* function id */
840 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
841 /* reset */
842 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
843 /* hw initialization */
844 mac->ops.init_hw = e1000_init_hw_ich8lan;
845 /* link setup */
846 mac->ops.setup_link = e1000_setup_link_ich8lan;
847 /* physical interface setup */
848 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
849 /* check for link */
850 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
851 /* link info */
852 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
853 /* multicast address update */
854 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
855 /* clear hardware counters */
856 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
857
858 /* LED and other operations */
859 switch (mac->type) {
860 case e1000_ich8lan:
861 case e1000_ich9lan:
862 case e1000_ich10lan:
863 /* check management mode */
864 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
865 /* ID LED init */
866 mac->ops.id_led_init = e1000_id_led_init_generic;
867 /* blink LED */
868 mac->ops.blink_led = e1000_blink_led_generic;
869 /* setup LED */
870 mac->ops.setup_led = e1000_setup_led_generic;
871 /* cleanup LED */
872 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
873 /* turn on/off LED */
874 mac->ops.led_on = e1000_led_on_ich8lan;
875 mac->ops.led_off = e1000_led_off_ich8lan;
876 break;
877 case e1000_pch2lan:
878 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
879 mac->ops.rar_set = e1000_rar_set_pch2lan;
880 /* FALLTHROUGH */
881 case e1000_pch_lpt:
882 case e1000_pch_spt:
883 case e1000_pch_cnp:
884 case e1000_pch_tgp:
885 case e1000_pch_adp:
886 case e1000_pch_mtp:
887 case e1000_pch_ptp:
888 case e1000_pch_nvp:
889 /* multicast address update for pch2 */
890 mac->ops.update_mc_addr_list =
891 e1000_update_mc_addr_list_pch2lan;
892 /* FALLTHROUGH */
893 case e1000_pchlan:
894 /* check management mode */
895 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
896 /* ID LED init */
897 mac->ops.id_led_init = e1000_id_led_init_pchlan;
898 /* setup LED */
899 mac->ops.setup_led = e1000_setup_led_pchlan;
900 /* cleanup LED */
901 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
902 /* turn on/off LED */
903 mac->ops.led_on = e1000_led_on_pchlan;
904 mac->ops.led_off = e1000_led_off_pchlan;
905 break;
906 default:
907 break;
908 }
909
910 if (mac->type >= e1000_pch_lpt) {
911 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
912 mac->ops.rar_set = e1000_rar_set_pch_lpt;
913 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
914 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
915 }
916
917 /* Enable PCS Lock-loss workaround for ICH8 */
918 if (mac->type == e1000_ich8lan)
919 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
920
921 return E1000_SUCCESS;
922 }
923
924 /**
925 * __e1000_access_emi_reg_locked - Read/write EMI register
926 * @hw: pointer to the HW structure
927 * @address: EMI address to program
928 * @data: pointer to value to read/write from/to the EMI address
929 * @read: boolean flag to indicate read or write
930 *
931 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
932 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)933 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
934 u16 *data, bool read)
935 {
936 s32 ret_val;
937
938 DEBUGFUNC("__e1000_access_emi_reg_locked");
939
940 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
941 if (ret_val)
942 return ret_val;
943
944 if (read)
945 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
946 data);
947 else
948 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
949 *data);
950
951 return ret_val;
952 }
953
954 /**
955 * e1000_read_emi_reg_locked - Read Extended Management Interface register
956 * @hw: pointer to the HW structure
957 * @addr: EMI address to program
958 * @data: value to be read from the EMI address
959 *
960 * Assumes the SW/FW/HW Semaphore is already acquired.
961 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)962 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
963 {
964 DEBUGFUNC("e1000_read_emi_reg_locked");
965
966 return __e1000_access_emi_reg_locked(hw, addr, data, true);
967 }
968
969 /**
970 * e1000_write_emi_reg_locked - Write Extended Management Interface register
971 * @hw: pointer to the HW structure
972 * @addr: EMI address to program
973 * @data: value to be written to the EMI address
974 *
975 * Assumes the SW/FW/HW Semaphore is already acquired.
976 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)977 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
978 {
979 DEBUGFUNC("e1000_read_emi_reg_locked");
980
981 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
982 }
983
984 /**
985 * e1000_set_eee_pchlan - Enable/disable EEE support
986 * @hw: pointer to the HW structure
987 *
988 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
989 * the link and the EEE capabilities of the link partner. The LPI Control
990 * register bits will remain set only if/when link is up.
991 *
992 * EEE LPI must not be asserted earlier than one second after link is up.
993 * On 82579, EEE LPI should not be enabled until such time otherwise there
994 * can be link issues with some switches. Other devices can have EEE LPI
995 * enabled immediately upon link up since they have a timer in hardware which
996 * prevents LPI from being asserted too early.
997 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)998 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
999 {
1000 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1001 s32 ret_val;
1002 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
1003
1004 DEBUGFUNC("e1000_set_eee_pchlan");
1005
1006 switch (hw->phy.type) {
1007 case e1000_phy_82579:
1008 lpa = I82579_EEE_LP_ABILITY;
1009 pcs_status = I82579_EEE_PCS_STATUS;
1010 adv_addr = I82579_EEE_ADVERTISEMENT;
1011 break;
1012 case e1000_phy_i217:
1013 lpa = I217_EEE_LP_ABILITY;
1014 pcs_status = I217_EEE_PCS_STATUS;
1015 adv_addr = I217_EEE_ADVERTISEMENT;
1016 break;
1017 default:
1018 return E1000_SUCCESS;
1019 }
1020
1021 ret_val = hw->phy.ops.acquire(hw);
1022 if (ret_val)
1023 return ret_val;
1024
1025 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
1026 if (ret_val)
1027 goto release;
1028
1029 /* Clear bits that enable EEE in various speeds */
1030 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
1031
1032 /* Enable EEE if not disabled by user */
1033 if (!dev_spec->eee_disable) {
1034 /* Save off link partner's EEE ability */
1035 ret_val = e1000_read_emi_reg_locked(hw, lpa,
1036 &dev_spec->eee_lp_ability);
1037 if (ret_val)
1038 goto release;
1039
1040 /* Read EEE advertisement */
1041 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
1042 if (ret_val)
1043 goto release;
1044
1045 /* Enable EEE only for speeds in which the link partner is
1046 * EEE capable and for which we advertise EEE.
1047 */
1048 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
1049 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
1050
1051 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
1052 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
1053 if (data & NWAY_LPAR_100TX_FD_CAPS)
1054 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
1055 else
1056 /* EEE is not supported in 100Half, so ignore
1057 * partner's EEE in 100 ability if full-duplex
1058 * is not advertised.
1059 */
1060 dev_spec->eee_lp_ability &=
1061 ~I82579_EEE_100_SUPPORTED;
1062 }
1063 }
1064
1065 if (hw->phy.type == e1000_phy_82579) {
1066 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
1067 &data);
1068 if (ret_val)
1069 goto release;
1070
1071 data &= ~I82579_LPI_100_PLL_SHUT;
1072 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
1073 data);
1074 if (ret_val)
1075 goto release;
1076 }
1077
1078 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
1079 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
1080 if (ret_val)
1081 goto release;
1082
1083 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
1084 release:
1085 hw->phy.ops.release(hw);
1086
1087 return ret_val;
1088 }
1089
1090 /**
1091 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
1092 * @hw: pointer to the HW structure
1093 * @link: link up bool flag
1094 *
1095 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1096 * preventing further DMA write requests. Workaround the issue by disabling
1097 * the de-assertion of the clock request when in 1Gpbs mode.
1098 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1099 * speeds in order to avoid Tx hangs.
1100 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)1101 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1102 {
1103 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1104 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1105 s32 ret_val = E1000_SUCCESS;
1106 u16 reg;
1107
1108 if (link && (status & E1000_STATUS_SPEED_1000)) {
1109 ret_val = hw->phy.ops.acquire(hw);
1110 if (ret_val)
1111 return ret_val;
1112
1113 ret_val =
1114 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1115 ®);
1116 if (ret_val)
1117 goto release;
1118
1119 ret_val =
1120 e1000_write_kmrn_reg_locked(hw,
1121 E1000_KMRNCTRLSTA_K1_CONFIG,
1122 reg &
1123 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1124 if (ret_val)
1125 goto release;
1126
1127 usec_delay(10);
1128
1129 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1130 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1131
1132 ret_val =
1133 e1000_write_kmrn_reg_locked(hw,
1134 E1000_KMRNCTRLSTA_K1_CONFIG,
1135 reg);
1136 release:
1137 hw->phy.ops.release(hw);
1138 } else {
1139 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1140 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1141
1142 if ((hw->phy.revision > 5) || !link ||
1143 ((status & E1000_STATUS_SPEED_100) &&
1144 (status & E1000_STATUS_FD)))
1145 goto update_fextnvm6;
1146
1147 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1148 if (ret_val)
1149 return ret_val;
1150
1151 /* Clear link status transmit timeout */
1152 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1153
1154 if (status & E1000_STATUS_SPEED_100) {
1155 /* Set inband Tx timeout to 5x10us for 100Half */
1156 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1157
1158 /* Do not extend the K1 entry latency for 100Half */
1159 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1160 } else {
1161 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1162 reg |= 50 <<
1163 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1164
1165 /* Extend the K1 entry latency for 10 Mbps */
1166 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1167 }
1168
1169 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1170 if (ret_val)
1171 return ret_val;
1172
1173 update_fextnvm6:
1174 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1175 }
1176
1177 return ret_val;
1178 }
1179
e1000_ltr2ns(u16 ltr)1180 static u64 e1000_ltr2ns(u16 ltr)
1181 {
1182 u32 value, scale;
1183
1184 /* Determine the latency in nsec based on the LTR value & scale */
1185 value = ltr & E1000_LTRV_VALUE_MASK;
1186 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1187
1188 return value * (1ULL << (scale * E1000_LTRV_SCALE_FACTOR));
1189 }
1190
1191 /**
1192 * e1000_platform_pm_pch_lpt - Set platform power management values
1193 * @hw: pointer to the HW structure
1194 * @link: bool indicating link status
1195 *
1196 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1197 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1198 * when link is up (which must not exceed the maximum latency supported
1199 * by the platform), otherwise specify there is no LTR requirement.
1200 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1201 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1202 * Capability register set, on this device LTR is set by writing the
1203 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1204 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1205 * message to the PMC.
1206 *
1207 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1208 * high-water mark.
1209 **/
e1000_platform_pm_pch_lpt(struct e1000_hw * hw,bool link)1210 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1211 {
1212 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1213 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1214 u16 lat_enc = 0; /* latency encoded */
1215 s32 obff_hwm = 0;
1216
1217 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1218
1219 if (link) {
1220 u16 speed, duplex, scale = 0;
1221 u16 max_snoop, max_nosnoop;
1222 u16 max_ltr_enc; /* max LTR latency encoded */
1223 u64 max_ltr_ns;
1224 s64 lat_ns;
1225 s64 value;
1226 u32 rxa;
1227
1228 if (!hw->mac.max_frame_size) {
1229 DEBUGOUT("max_frame_size not set.\n");
1230 return -E1000_ERR_CONFIG;
1231 }
1232
1233 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1234 if (!speed) {
1235 DEBUGOUT("Speed not set.\n");
1236 return -E1000_ERR_CONFIG;
1237 }
1238
1239 /* Rx Packet Buffer Allocation size (KB) */
1240 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1241
1242 /* Determine the maximum latency tolerated by the device.
1243 *
1244 * Per the PCIe spec, the tolerated latencies are encoded as
1245 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1246 * a 10-bit value (0-1023) to provide a range from 1 ns to
1247 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1248 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1249 */
1250 lat_ns = ((s64)rxa * 1024 -
1251 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1252 if (lat_ns < 0)
1253 lat_ns = 0;
1254 else
1255 lat_ns /= speed;
1256 value = lat_ns;
1257
1258 while (value > E1000_LTRV_VALUE_MASK) {
1259 scale++;
1260 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1261 }
1262 if (scale > E1000_LTRV_SCALE_MAX) {
1263 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1264 return -E1000_ERR_CONFIG;
1265 }
1266 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1267
1268 /* Determine the maximum latency tolerated by the platform */
1269 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1270 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1271 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1272 max_ltr_ns = e1000_ltr2ns(max_ltr_enc);
1273
1274 if (e1000_ltr2ns(lat_enc) > max_ltr_ns) {
1275 lat_enc = max_ltr_enc;
1276 lat_ns = max_ltr_ns;
1277 }
1278
1279 if (lat_ns) {
1280 lat_ns *= speed * 1000;
1281 lat_ns /= 8;
1282 lat_ns /= 1000000000;
1283 obff_hwm = (s32)(rxa - lat_ns);
1284 }
1285 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1286 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1287 return -E1000_ERR_CONFIG;
1288 }
1289 }
1290
1291 /* Set Snoop and No-Snoop latencies the same */
1292 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1293 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1294
1295 /* Set OBFF high water mark */
1296 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1297 reg |= obff_hwm;
1298 E1000_WRITE_REG(hw, E1000_SVT, reg);
1299
1300 /* Enable OBFF */
1301 reg = E1000_READ_REG(hw, E1000_SVCR);
1302 reg |= E1000_SVCR_OFF_EN;
1303 /* Always unblock interrupts to the CPU even when the system is
1304 * in OBFF mode. This ensures that small round-robin traffic
1305 * (like ping) does not get dropped or experience long latency.
1306 */
1307 reg |= E1000_SVCR_OFF_MASKINT;
1308 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1309
1310 return E1000_SUCCESS;
1311 }
1312
1313 /**
1314 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1315 * @hw: pointer to the HW structure
1316 * @itr: interrupt throttling rate
1317 *
1318 * Configure OBFF with the updated interrupt rate.
1319 **/
e1000_set_obff_timer_pch_lpt(struct e1000_hw * hw,u32 itr)1320 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1321 {
1322 u32 svcr;
1323 s32 timer;
1324
1325 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1326
1327 /* Convert ITR value into microseconds for OBFF timer */
1328 timer = itr & E1000_ITR_MASK;
1329 timer = (timer * E1000_ITR_MULT) / 1000;
1330
1331 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1332 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1333 return -E1000_ERR_CONFIG;
1334 }
1335
1336 svcr = E1000_READ_REG(hw, E1000_SVCR);
1337 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1338 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1339 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1340
1341 return E1000_SUCCESS;
1342 }
1343
1344 /**
1345 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1346 * @hw: pointer to the HW structure
1347 * @to_sx: boolean indicating a system power state transition to Sx
1348 *
1349 * When link is down, configure ULP mode to significantly reduce the power
1350 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1351 * ME firmware to start the ULP configuration. If not on an ME enabled
1352 * system, configure the ULP mode by software.
1353 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1354 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1355 {
1356 u32 mac_reg;
1357 u32 phy_retries;
1358 s32 ret_val = E1000_SUCCESS;
1359 u16 phy_reg;
1360 u16 oem_reg = 0;
1361
1362 if ((hw->mac.type < e1000_pch_lpt) ||
1363 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1364 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1365 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1366 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1367 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1368 return 0;
1369
1370 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1371 /* Request ME configure ULP mode in the PHY */
1372 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1373 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1374 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1375
1376 goto out;
1377 }
1378
1379 if (!to_sx) {
1380 int i = 0;
1381 /* Poll up to 5 seconds for Cable Disconnected indication */
1382 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1383 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1384 /* Bail if link is re-acquired */
1385 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1386 return -E1000_ERR_PHY;
1387 if (i++ == 100)
1388 break;
1389
1390 msec_delay(50);
1391 }
1392 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1393 (E1000_READ_REG(hw, E1000_FEXT) &
1394 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1395 i * 50);
1396 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1397 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1398 return 0;
1399 }
1400
1401 ret_val = hw->phy.ops.acquire(hw);
1402 if (ret_val)
1403 goto out;
1404
1405 /* Switching the PHY interface returns an expected MDI error. */
1406 e1000_disable_phy_retry_mechanism(hw, &phy_retries);
1407
1408 /* Force SMBus mode in PHY */
1409 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1410 if (ret_val)
1411 goto release;
1412 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1413 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1414
1415 /* Force SMBus mode in MAC */
1416 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1417 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1418 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1419
1420 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1421 * LPLU and disable Gig speed when entering ULP
1422 */
1423 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1424 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1425 &oem_reg);
1426 if (ret_val)
1427 goto release;
1428
1429 phy_reg = oem_reg;
1430 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1431
1432 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1433 phy_reg);
1434
1435 if (ret_val)
1436 goto release;
1437 }
1438
1439 /* Set Inband ULP Exit, Reset to SMBus mode and
1440 * Disable SMBus Release on PERST# in PHY
1441 */
1442 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1443 if (ret_val)
1444 goto release;
1445 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1446 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1447 if (to_sx) {
1448 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1449 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1450 else
1451 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1452
1453 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1454 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1455 } else {
1456 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1457 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1458 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1459 }
1460 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1461
1462 /* Set Disable SMBus Release on PERST# in MAC */
1463 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1464 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1465 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1466
1467 /* Commit ULP changes in PHY by starting auto ULP configuration */
1468 phy_reg |= I218_ULP_CONFIG1_START;
1469 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1470
1471 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1472 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1473 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1474 oem_reg);
1475 if (ret_val)
1476 goto release;
1477 }
1478
1479 release:
1480 e1000_enable_phy_retry_mechanism(hw, phy_retries);
1481 hw->phy.ops.release(hw);
1482 out:
1483 if (ret_val)
1484 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1485 else
1486 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1487
1488 return ret_val;
1489 }
1490
1491 /**
1492 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1493 * @hw: pointer to the HW structure
1494 * @force: boolean indicating whether or not to force disabling ULP
1495 *
1496 * Un-configure ULP mode when link is up, the system is transitioned from
1497 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1498 * system, poll for an indication from ME that ULP has been un-configured.
1499 * If not on an ME enabled system, un-configure the ULP mode by software.
1500 *
1501 * During nominal operation, this function is called when link is acquired
1502 * to disable ULP mode (force=false); otherwise, for example when unloading
1503 * the driver or during Sx->S0 transitions, this is called with force=true
1504 * to forcibly disable ULP.
1505 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1506 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1507 {
1508 s32 ret_val = E1000_SUCCESS;
1509 u16 ulp_exit_timeout = 250;
1510 u32 mac_reg;
1511 u32 phy_retries;
1512 u16 phy_reg;
1513 int i = 0;
1514
1515 if ((hw->mac.type < e1000_pch_lpt) ||
1516 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1517 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1518 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1519 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1520 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1521 return 0;
1522
1523 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1524 if (force) {
1525 /* Request ME un-configure ULP mode in the PHY */
1526 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1527 mac_reg &= ~E1000_H2ME_ULP;
1528 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1529 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1530 }
1531
1532 while (E1000_READ_REG(hw, E1000_FWSM) &
1533 E1000_FWSM_ULP_CFG_DONE) {
1534 if (i++ == ulp_exit_timeout) {
1535 ret_val = -E1000_ERR_PHY;
1536 goto out;
1537 }
1538
1539 msec_delay(10);
1540 }
1541 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1542
1543 if (force) {
1544 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1545 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1546 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1547 } else {
1548 /* Clear H2ME.ULP after ME ULP configuration */
1549 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1550 mac_reg &= ~E1000_H2ME_ULP;
1551 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1552 }
1553
1554 goto out;
1555 }
1556
1557 ret_val = hw->phy.ops.acquire(hw);
1558 if (ret_val)
1559 goto out;
1560
1561 if (force)
1562 /* Toggle LANPHYPC Value bit */
1563 e1000_toggle_lanphypc_pch_lpt(hw);
1564
1565 /* Switching the PHY interface returns an expected MDI error. */
1566 e1000_disable_phy_retry_mechanism(hw, &phy_retries);
1567
1568 /* Unforce SMBus mode in PHY */
1569 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1570 if (ret_val) {
1571 /* The MAC might be in PCIe mode, so temporarily force to
1572 * SMBus mode in order to access the PHY.
1573 */
1574 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1575 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1576 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1577
1578 msec_delay(50);
1579
1580 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1581 &phy_reg);
1582 if (ret_val)
1583 goto release;
1584 }
1585 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1586 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1587
1588 /* Unforce SMBus mode in MAC */
1589 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1590 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1591 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1592
1593 /* When ULP mode was previously entered, K1 was disabled by the
1594 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1595 */
1596 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1597 if (ret_val)
1598 goto release;
1599 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1600 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1601
1602 /* Clear ULP enabled configuration */
1603 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1604 if (ret_val)
1605 goto release;
1606 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1607 I218_ULP_CONFIG1_STICKY_ULP |
1608 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1609 I218_ULP_CONFIG1_WOL_HOST |
1610 I218_ULP_CONFIG1_INBAND_EXIT |
1611 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1612 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1613 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1614 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1615
1616 /* Commit ULP changes by starting auto ULP configuration */
1617 phy_reg |= I218_ULP_CONFIG1_START;
1618 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1619
1620 /* Clear Disable SMBus Release on PERST# in MAC */
1621 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1622 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1623 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1624
1625 release:
1626 e1000_enable_phy_retry_mechanism(hw, phy_retries);
1627 hw->phy.ops.release(hw);
1628 if (force) {
1629 hw->phy.ops.reset(hw);
1630 msec_delay(50);
1631 }
1632 out:
1633 if (ret_val)
1634 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1635 else
1636 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1637
1638 return ret_val;
1639 }
1640
1641 /**
1642 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1643 * @hw: pointer to the HW structure
1644 *
1645 * Checks to see of the link status of the hardware has changed. If a
1646 * change in link status has been detected, then we read the PHY registers
1647 * to get the current speed/duplex if link exists.
1648 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1649 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1650 {
1651 struct e1000_mac_info *mac = &hw->mac;
1652 s32 ret_val, tipg_reg = 0;
1653 u16 emi_addr, emi_val = 0;
1654 bool link;
1655 u16 phy_reg;
1656
1657 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1658
1659 /* We only want to go out to the PHY registers to see if Auto-Neg
1660 * has completed and/or if our link status has changed. The
1661 * get_link_status flag is set upon receiving a Link Status
1662 * Change or Rx Sequence Error interrupt.
1663 */
1664 if (!mac->get_link_status)
1665 return E1000_SUCCESS;
1666
1667 /* First we want to see if the MII Status Register reports
1668 * link. If so, then we want to get the current speed/duplex
1669 * of the PHY.
1670 */
1671 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1672 if (ret_val)
1673 return ret_val;
1674
1675 if (hw->mac.type == e1000_pchlan) {
1676 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1677 if (ret_val)
1678 return ret_val;
1679 }
1680
1681 /* When connected at 10Mbps half-duplex, some parts are excessively
1682 * aggressive resulting in many collisions. To avoid this, increase
1683 * the IPG and reduce Rx latency in the PHY.
1684 */
1685 if ((hw->mac.type >= e1000_pch2lan) && link) {
1686 u16 speed, duplex;
1687
1688 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1689 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1690 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1691
1692 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1693 tipg_reg |= 0xFF;
1694 /* Reduce Rx latency in analog PHY */
1695 emi_val = 0;
1696 } else if (hw->mac.type >= e1000_pch_spt &&
1697 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1698 tipg_reg |= 0xC;
1699 emi_val = 1;
1700 } else {
1701 /* Roll back the default values */
1702 tipg_reg |= 0x08;
1703 emi_val = 1;
1704 }
1705
1706 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1707
1708 ret_val = hw->phy.ops.acquire(hw);
1709 if (ret_val)
1710 return ret_val;
1711
1712 if (hw->mac.type == e1000_pch2lan)
1713 emi_addr = I82579_RX_CONFIG;
1714 else
1715 emi_addr = I217_RX_CONFIG;
1716 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1717
1718
1719 if (hw->mac.type >= e1000_pch_lpt) {
1720 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1721 &phy_reg);
1722 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1723 if (speed == SPEED_100 || speed == SPEED_10)
1724 phy_reg |= 0x3E8;
1725 else if (hw->mac.type >= e1000_pch_mtp &&
1726 hw->mac.type < e1000_82575)
1727 phy_reg |= 0x1D5;
1728 else
1729 phy_reg |= 0xFA;
1730 hw->phy.ops.write_reg_locked(hw,
1731 I217_PLL_CLOCK_GATE_REG,
1732 phy_reg);
1733
1734 if (speed == SPEED_1000) {
1735 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1736 &phy_reg);
1737
1738 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1739
1740 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1741 phy_reg);
1742 }
1743 }
1744 hw->phy.ops.release(hw);
1745
1746 if (ret_val)
1747 return ret_val;
1748
1749 if (hw->mac.type >= e1000_pch_spt) {
1750 u16 data;
1751 u16 ptr_gap;
1752
1753 if (speed == SPEED_1000) {
1754 ret_val = hw->phy.ops.acquire(hw);
1755 if (ret_val)
1756 return ret_val;
1757
1758 ret_val = hw->phy.ops.read_reg_locked(hw,
1759 PHY_REG(776, 20),
1760 &data);
1761 if (ret_val) {
1762 hw->phy.ops.release(hw);
1763 return ret_val;
1764 }
1765
1766 ptr_gap = (data & (0x3FF << 2)) >> 2;
1767 if (ptr_gap < 0x18) {
1768 data &= ~(0x3FF << 2);
1769 data |= (0x18 << 2);
1770 ret_val =
1771 hw->phy.ops.write_reg_locked(hw,
1772 PHY_REG(776, 20), data);
1773 }
1774 hw->phy.ops.release(hw);
1775 if (ret_val)
1776 return ret_val;
1777 } else {
1778 ret_val = hw->phy.ops.acquire(hw);
1779 if (ret_val)
1780 return ret_val;
1781
1782 ret_val = hw->phy.ops.write_reg_locked(hw,
1783 PHY_REG(776, 20),
1784 0xC023);
1785 hw->phy.ops.release(hw);
1786 if (ret_val)
1787 return ret_val;
1788
1789 }
1790 }
1791 }
1792
1793 /* I217 Packet Loss issue:
1794 * ensure that FEXTNVM4 Beacon Duration is set correctly
1795 * on power up.
1796 * Set the Beacon Duration for I217 to 8 usec
1797 */
1798 if (hw->mac.type >= e1000_pch_lpt) {
1799 u32 mac_reg;
1800
1801 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1802 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1803 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1804 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1805 }
1806
1807 /* Work-around I218 hang issue */
1808 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1809 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1810 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1811 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1812 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1813 if (ret_val)
1814 return ret_val;
1815 }
1816 if (hw->mac.type >= e1000_pch_lpt) {
1817 /* Set platform power management values for
1818 * Latency Tolerance Reporting (LTR)
1819 * Optimized Buffer Flush/Fill (OBFF)
1820 */
1821 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1822 if (ret_val)
1823 return ret_val;
1824 }
1825 /* Clear link partner's EEE ability */
1826 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1827
1828 if (hw->mac.type >= e1000_pch_lpt) {
1829 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1830
1831 if (hw->mac.type == e1000_pch_spt) {
1832 /* FEXTNVM6 K1-off workaround - for SPT only */
1833 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1834
1835 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1836 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1837 else
1838 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1839 }
1840
1841 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1842 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1843
1844 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1845
1846 /* Configure K0s minimum time */
1847 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1848 }
1849
1850 if (!link)
1851 return E1000_SUCCESS; /* No link detected */
1852
1853 mac->get_link_status = false;
1854
1855 switch (hw->mac.type) {
1856 case e1000_pch2lan:
1857 ret_val = e1000_k1_workaround_lv(hw);
1858 if (ret_val)
1859 return ret_val;
1860 /* FALLTHROUGH */
1861 case e1000_pchlan:
1862 if (hw->phy.type == e1000_phy_82578) {
1863 ret_val = e1000_link_stall_workaround_hv(hw);
1864 if (ret_val)
1865 return ret_val;
1866 }
1867
1868 /* Workaround for PCHx parts in half-duplex:
1869 * Set the number of preambles removed from the packet
1870 * when it is passed from the PHY to the MAC to prevent
1871 * the MAC from misinterpreting the packet type.
1872 */
1873 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1874 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1875
1876 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1877 E1000_STATUS_FD)
1878 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1879
1880 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1881 break;
1882 default:
1883 break;
1884 }
1885
1886 /* Check if there was DownShift, must be checked
1887 * immediately after link-up
1888 */
1889 e1000_check_downshift_generic(hw);
1890
1891 /* Enable/Disable EEE after link up */
1892 if (hw->phy.type > e1000_phy_82579) {
1893 ret_val = e1000_set_eee_pchlan(hw);
1894 if (ret_val)
1895 return ret_val;
1896 }
1897
1898 /* If we are forcing speed/duplex, then we simply return since
1899 * we have already determined whether we have link or not.
1900 */
1901 if (!mac->autoneg)
1902 return -E1000_ERR_CONFIG;
1903
1904 /* Auto-Neg is enabled. Auto Speed Detection takes care
1905 * of MAC speed/duplex configuration. So we only need to
1906 * configure Collision Distance in the MAC.
1907 */
1908 mac->ops.config_collision_dist(hw);
1909
1910 /* Configure Flow Control now that Auto-Neg has completed.
1911 * First, we need to restore the desired flow control
1912 * settings because we may have had to re-autoneg with a
1913 * different link partner.
1914 */
1915 ret_val = e1000_config_fc_after_link_up_generic(hw);
1916 if (ret_val)
1917 DEBUGOUT("Error configuring flow control\n");
1918
1919 return ret_val;
1920 }
1921
1922 /**
1923 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1924 * @hw: pointer to the HW structure
1925 *
1926 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1927 **/
e1000_init_function_pointers_ich8lan(struct e1000_hw * hw)1928 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1929 {
1930 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1931
1932 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1933 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1934 switch (hw->mac.type) {
1935 case e1000_ich8lan:
1936 case e1000_ich9lan:
1937 case e1000_ich10lan:
1938 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1939 break;
1940 case e1000_pchlan:
1941 case e1000_pch2lan:
1942 case e1000_pch_lpt:
1943 case e1000_pch_spt:
1944 case e1000_pch_cnp:
1945 case e1000_pch_tgp:
1946 case e1000_pch_adp:
1947 case e1000_pch_mtp:
1948 case e1000_pch_ptp:
1949 case e1000_pch_nvp:
1950 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1951 break;
1952 default:
1953 break;
1954 }
1955 }
1956
1957 /**
1958 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1959 * @hw: pointer to the HW structure
1960 *
1961 * Acquires the mutex for performing NVM operations.
1962 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw * hw)1963 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1964 {
1965 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1966
1967 ASSERT_CTX_LOCK_HELD(hw);
1968
1969 return E1000_SUCCESS;
1970 }
1971
1972 /**
1973 * e1000_release_nvm_ich8lan - Release NVM mutex
1974 * @hw: pointer to the HW structure
1975 *
1976 * Releases the mutex used while performing NVM operations.
1977 **/
e1000_release_nvm_ich8lan(struct e1000_hw * hw)1978 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1979 {
1980 DEBUGFUNC("e1000_release_nvm_ich8lan");
1981
1982 ASSERT_CTX_LOCK_HELD(hw);
1983 }
1984
1985 /**
1986 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1987 * @hw: pointer to the HW structure
1988 *
1989 * Acquires the software control flag for performing PHY and select
1990 * MAC CSR accesses.
1991 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1992 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1993 {
1994 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1995 s32 ret_val = E1000_SUCCESS;
1996
1997 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1998
1999 ASSERT_CTX_LOCK_HELD(hw);
2000
2001 while (timeout) {
2002 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2003 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
2004 break;
2005
2006 msec_delay_irq(1);
2007 timeout--;
2008 }
2009
2010 if (!timeout) {
2011 DEBUGOUT("SW has already locked the resource.\n");
2012 ret_val = -E1000_ERR_CONFIG;
2013 goto out;
2014 }
2015
2016 timeout = SW_FLAG_TIMEOUT;
2017
2018 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
2019 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2020
2021 while (timeout) {
2022 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2023 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
2024 break;
2025
2026 msec_delay_irq(1);
2027 timeout--;
2028 }
2029
2030 if (!timeout) {
2031 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
2032 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
2033 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
2034 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2035 ret_val = -E1000_ERR_CONFIG;
2036 goto out;
2037 }
2038
2039 out:
2040 return ret_val;
2041 }
2042
2043 /**
2044 * e1000_release_swflag_ich8lan - Release software control flag
2045 * @hw: pointer to the HW structure
2046 *
2047 * Releases the software control flag for performing PHY and select
2048 * MAC CSR accesses.
2049 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)2050 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
2051 {
2052 u32 extcnf_ctrl;
2053
2054 DEBUGFUNC("e1000_release_swflag_ich8lan");
2055
2056 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2057
2058 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
2059 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
2060 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2061 } else {
2062 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
2063 }
2064 }
2065
2066 /**
2067 * e1000_check_mng_mode_ich8lan - Checks management mode
2068 * @hw: pointer to the HW structure
2069 *
2070 * This checks if the adapter has any manageability enabled.
2071 * This is a function pointer entry point only called by read/write
2072 * routines for the PHY and NVM parts.
2073 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)2074 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
2075 {
2076 u32 fwsm;
2077
2078 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
2079
2080 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2081
2082 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
2083 ((fwsm & E1000_FWSM_MODE_MASK) ==
2084 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
2085 }
2086
2087 /**
2088 * e1000_check_mng_mode_pchlan - Checks management mode
2089 * @hw: pointer to the HW structure
2090 *
2091 * This checks if the adapter has iAMT enabled.
2092 * This is a function pointer entry point only called by read/write
2093 * routines for the PHY and NVM parts.
2094 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)2095 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
2096 {
2097 u32 fwsm;
2098
2099 DEBUGFUNC("e1000_check_mng_mode_pchlan");
2100
2101 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2102
2103 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
2104 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
2105 }
2106
2107 /**
2108 * e1000_rar_set_pch2lan - Set receive address register
2109 * @hw: pointer to the HW structure
2110 * @addr: pointer to the receive address
2111 * @index: receive address array register
2112 *
2113 * Sets the receive address array register at index to the address passed
2114 * in by addr. For 82579, RAR[0] is the base address register that is to
2115 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2116 * Use SHRA[0-3] in place of those reserved for ME.
2117 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)2118 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2119 {
2120 u32 rar_low, rar_high;
2121
2122 DEBUGFUNC("e1000_rar_set_pch2lan");
2123
2124 /* HW expects these in little endian so we reverse the byte order
2125 * from network order (big endian) to little endian
2126 */
2127 rar_low = ((u32) addr[0] |
2128 ((u32) addr[1] << 8) |
2129 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2130
2131 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2132
2133 /* If MAC address zero, no need to set the AV bit */
2134 if (rar_low || rar_high)
2135 rar_high |= E1000_RAH_AV;
2136
2137 if (index == 0) {
2138 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2139 E1000_WRITE_FLUSH(hw);
2140 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2141 E1000_WRITE_FLUSH(hw);
2142 return E1000_SUCCESS;
2143 }
2144
2145 /* RAR[1-6] are owned by manageability. Skip those and program the
2146 * next address into the SHRA register array.
2147 */
2148 if (index < (u32) (hw->mac.rar_entry_count)) {
2149 s32 ret_val;
2150
2151 ret_val = e1000_acquire_swflag_ich8lan(hw);
2152 if (ret_val)
2153 goto out;
2154
2155 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2156 E1000_WRITE_FLUSH(hw);
2157 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2158 E1000_WRITE_FLUSH(hw);
2159
2160 e1000_release_swflag_ich8lan(hw);
2161
2162 /* verify the register updates */
2163 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2164 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2165 return E1000_SUCCESS;
2166
2167 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2168 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2169 }
2170
2171 out:
2172 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2173 return -E1000_ERR_CONFIG;
2174 }
2175
2176 /**
2177 * e1000_rar_set_pch_lpt - Set receive address registers
2178 * @hw: pointer to the HW structure
2179 * @addr: pointer to the receive address
2180 * @index: receive address array register
2181 *
2182 * Sets the receive address register array at index to the address passed
2183 * in by addr. For LPT, RAR[0] is the base address register that is to
2184 * contain the MAC address. SHRA[0-10] are the shared receive address
2185 * registers that are shared between the Host and manageability engine (ME).
2186 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)2187 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2188 {
2189 u32 rar_low, rar_high;
2190 u32 wlock_mac;
2191
2192 DEBUGFUNC("e1000_rar_set_pch_lpt");
2193
2194 /* HW expects these in little endian so we reverse the byte order
2195 * from network order (big endian) to little endian
2196 */
2197 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2198 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2199
2200 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2201
2202 /* If MAC address zero, no need to set the AV bit */
2203 if (rar_low || rar_high)
2204 rar_high |= E1000_RAH_AV;
2205
2206 if (index == 0) {
2207 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2208 E1000_WRITE_FLUSH(hw);
2209 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2210 E1000_WRITE_FLUSH(hw);
2211 return E1000_SUCCESS;
2212 }
2213
2214 /* The manageability engine (ME) can lock certain SHRAR registers that
2215 * it is using - those registers are unavailable for use.
2216 */
2217 if (index < hw->mac.rar_entry_count) {
2218 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2219 E1000_FWSM_WLOCK_MAC_MASK;
2220 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2221
2222 /* Check if all SHRAR registers are locked */
2223 if (wlock_mac == 1)
2224 goto out;
2225
2226 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2227 s32 ret_val;
2228
2229 ret_val = e1000_acquire_swflag_ich8lan(hw);
2230
2231 if (ret_val)
2232 goto out;
2233
2234 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2235 rar_low);
2236 E1000_WRITE_FLUSH(hw);
2237 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2238 rar_high);
2239 E1000_WRITE_FLUSH(hw);
2240
2241 e1000_release_swflag_ich8lan(hw);
2242
2243 /* verify the register updates */
2244 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2245 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2246 return E1000_SUCCESS;
2247 }
2248 }
2249
2250 out:
2251 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2252 return -E1000_ERR_CONFIG;
2253 }
2254
2255 /**
2256 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2257 * @hw: pointer to the HW structure
2258 * @mc_addr_list: array of multicast addresses to program
2259 * @mc_addr_count: number of multicast addresses to program
2260 *
2261 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2262 * The caller must have a packed mc_addr_list of multicast addresses.
2263 **/
e1000_update_mc_addr_list_pch2lan(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)2264 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2265 u8 *mc_addr_list,
2266 u32 mc_addr_count)
2267 {
2268 u16 phy_reg = 0;
2269 int i;
2270 s32 ret_val;
2271
2272 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2273
2274 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2275
2276 ret_val = hw->phy.ops.acquire(hw);
2277 if (ret_val)
2278 return;
2279
2280 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2281 if (ret_val)
2282 goto release;
2283
2284 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2285 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2286 (u16)(hw->mac.mta_shadow[i] &
2287 0xFFFF));
2288 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2289 (u16)((hw->mac.mta_shadow[i] >> 16) &
2290 0xFFFF));
2291 }
2292
2293 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2294
2295 release:
2296 hw->phy.ops.release(hw);
2297 }
2298
2299 /**
2300 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2301 * @hw: pointer to the HW structure
2302 *
2303 * Checks if firmware is blocking the reset of the PHY.
2304 * This is a function pointer entry point only called by
2305 * reset routines.
2306 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)2307 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2308 {
2309 u32 fwsm;
2310 bool blocked = false;
2311 int i = 0;
2312
2313 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2314
2315 do {
2316 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2317 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2318 blocked = true;
2319 msec_delay(10);
2320 continue;
2321 }
2322 blocked = false;
2323 } while (blocked && (i++ < 30));
2324 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2325 }
2326
2327 /**
2328 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2329 * @hw: pointer to the HW structure
2330 *
2331 * Assumes semaphore already acquired.
2332 *
2333 **/
e1000_write_smbus_addr(struct e1000_hw * hw)2334 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2335 {
2336 u16 phy_data;
2337 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2338 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2339 E1000_STRAP_SMT_FREQ_SHIFT;
2340 s32 ret_val;
2341
2342 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2343
2344 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2345 if (ret_val)
2346 return ret_val;
2347
2348 phy_data &= ~HV_SMB_ADDR_MASK;
2349 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2350 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2351
2352 if (hw->phy.type == e1000_phy_i217) {
2353 /* Restore SMBus frequency */
2354 if (freq--) {
2355 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2356 phy_data |= (freq & (1 << 0)) <<
2357 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2358 phy_data |= (freq & (1 << 1)) <<
2359 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2360 } else {
2361 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2362 }
2363 }
2364
2365 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2366 }
2367
2368 /**
2369 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2370 * @hw: pointer to the HW structure
2371 *
2372 * SW should configure the LCD from the NVM extended configuration region
2373 * as a workaround for certain parts.
2374 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)2375 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2376 {
2377 struct e1000_phy_info *phy = &hw->phy;
2378 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2379 s32 ret_val = E1000_SUCCESS;
2380 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2381
2382 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2383
2384 /* Initialize the PHY from the NVM on ICH platforms. This
2385 * is needed due to an issue where the NVM configuration is
2386 * not properly autoloaded after power transitions.
2387 * Therefore, after each PHY reset, we will load the
2388 * configuration data out of the NVM manually.
2389 */
2390 switch (hw->mac.type) {
2391 case e1000_ich8lan:
2392 if (phy->type != e1000_phy_igp_3)
2393 return ret_val;
2394
2395 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2396 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2397 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2398 break;
2399 }
2400 /* FALLTHROUGH */
2401 case e1000_pchlan:
2402 case e1000_pch2lan:
2403 case e1000_pch_lpt:
2404 case e1000_pch_spt:
2405 case e1000_pch_cnp:
2406 case e1000_pch_tgp:
2407 case e1000_pch_adp:
2408 case e1000_pch_mtp:
2409 case e1000_pch_ptp:
2410 case e1000_pch_nvp:
2411 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2412 break;
2413 default:
2414 return ret_val;
2415 }
2416
2417 ret_val = hw->phy.ops.acquire(hw);
2418 if (ret_val)
2419 return ret_val;
2420
2421 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2422 if (!(data & sw_cfg_mask))
2423 goto release;
2424
2425 /* Make sure HW does not configure LCD from PHY
2426 * extended configuration before SW configuration
2427 */
2428 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2429 if ((hw->mac.type < e1000_pch2lan) &&
2430 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2431 goto release;
2432
2433 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2434 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2435 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2436 if (!cnf_size)
2437 goto release;
2438
2439 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2440 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2441
2442 if (((hw->mac.type == e1000_pchlan) &&
2443 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2444 (hw->mac.type > e1000_pchlan)) {
2445 /* HW configures the SMBus address and LEDs when the
2446 * OEM and LCD Write Enable bits are set in the NVM.
2447 * When both NVM bits are cleared, SW will configure
2448 * them instead.
2449 */
2450 ret_val = e1000_write_smbus_addr(hw);
2451 if (ret_val)
2452 goto release;
2453
2454 data = E1000_READ_REG(hw, E1000_LEDCTL);
2455 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2456 (u16)data);
2457 if (ret_val)
2458 goto release;
2459 }
2460
2461 /* Configure LCD from extended configuration region. */
2462
2463 /* cnf_base_addr is in DWORD */
2464 word_addr = (u16)(cnf_base_addr << 1);
2465
2466 for (i = 0; i < cnf_size; i++) {
2467 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2468 ®_data);
2469 if (ret_val)
2470 goto release;
2471
2472 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2473 1, ®_addr);
2474 if (ret_val)
2475 goto release;
2476
2477 /* Save off the PHY page for future writes. */
2478 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2479 phy_page = reg_data;
2480 continue;
2481 }
2482
2483 reg_addr &= PHY_REG_MASK;
2484 reg_addr |= phy_page;
2485
2486 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2487 reg_data);
2488 if (ret_val)
2489 goto release;
2490 }
2491
2492 release:
2493 hw->phy.ops.release(hw);
2494 return ret_val;
2495 }
2496
2497 /**
2498 * e1000_k1_gig_workaround_hv - K1 Si workaround
2499 * @hw: pointer to the HW structure
2500 * @link: link up bool flag
2501 *
2502 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2503 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2504 * If link is down, the function will restore the default K1 setting located
2505 * in the NVM.
2506 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2507 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2508 {
2509 s32 ret_val = E1000_SUCCESS;
2510 u16 status_reg = 0;
2511 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2512
2513 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2514
2515 if (hw->mac.type != e1000_pchlan)
2516 return E1000_SUCCESS;
2517
2518 /* Wrap the whole flow with the sw flag */
2519 ret_val = hw->phy.ops.acquire(hw);
2520 if (ret_val)
2521 return ret_val;
2522
2523 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2524 if (link) {
2525 if (hw->phy.type == e1000_phy_82578) {
2526 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2527 &status_reg);
2528 if (ret_val)
2529 goto release;
2530
2531 status_reg &= (BM_CS_STATUS_LINK_UP |
2532 BM_CS_STATUS_RESOLVED |
2533 BM_CS_STATUS_SPEED_MASK);
2534
2535 if (status_reg == (BM_CS_STATUS_LINK_UP |
2536 BM_CS_STATUS_RESOLVED |
2537 BM_CS_STATUS_SPEED_1000))
2538 k1_enable = false;
2539 }
2540
2541 if (hw->phy.type == e1000_phy_82577) {
2542 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2543 &status_reg);
2544 if (ret_val)
2545 goto release;
2546
2547 status_reg &= (HV_M_STATUS_LINK_UP |
2548 HV_M_STATUS_AUTONEG_COMPLETE |
2549 HV_M_STATUS_SPEED_MASK);
2550
2551 if (status_reg == (HV_M_STATUS_LINK_UP |
2552 HV_M_STATUS_AUTONEG_COMPLETE |
2553 HV_M_STATUS_SPEED_1000))
2554 k1_enable = false;
2555 }
2556
2557 /* Link stall fix for link up */
2558 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2559 0x0100);
2560 if (ret_val)
2561 goto release;
2562
2563 } else {
2564 /* Link stall fix for link down */
2565 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2566 0x4100);
2567 if (ret_val)
2568 goto release;
2569 }
2570
2571 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2572
2573 release:
2574 hw->phy.ops.release(hw);
2575
2576 return ret_val;
2577 }
2578
2579 /**
2580 * e1000_configure_k1_ich8lan - Configure K1 power state
2581 * @hw: pointer to the HW structure
2582 * @k1_enable: K1 state to configure
2583 *
2584 * Configure the K1 power state based on the provided parameter.
2585 * Assumes semaphore already acquired.
2586 *
2587 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2588 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2589 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2590 {
2591 s32 ret_val;
2592 u32 ctrl_reg = 0;
2593 u32 ctrl_ext = 0;
2594 u32 reg = 0;
2595 u16 kmrn_reg = 0;
2596
2597 DEBUGFUNC("e1000_configure_k1_ich8lan");
2598
2599 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2600 &kmrn_reg);
2601 if (ret_val)
2602 return ret_val;
2603
2604 if (k1_enable)
2605 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2606 else
2607 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2608
2609 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2610 kmrn_reg);
2611 if (ret_val)
2612 return ret_val;
2613
2614 usec_delay(20);
2615 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2616 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2617
2618 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2619 reg |= E1000_CTRL_FRCSPD;
2620 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2621
2622 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2623 E1000_WRITE_FLUSH(hw);
2624 usec_delay(20);
2625 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2626 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2627 E1000_WRITE_FLUSH(hw);
2628 usec_delay(20);
2629
2630 return E1000_SUCCESS;
2631 }
2632
2633 /**
2634 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2635 * @hw: pointer to the HW structure
2636 * @d0_state: boolean if entering d0 or d3 device state
2637 *
2638 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2639 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2640 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2641 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2642 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2643 {
2644 s32 ret_val = 0;
2645 u32 mac_reg;
2646 u16 oem_reg;
2647
2648 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2649
2650 if (hw->mac.type < e1000_pchlan)
2651 return ret_val;
2652
2653 ret_val = hw->phy.ops.acquire(hw);
2654 if (ret_val)
2655 return ret_val;
2656
2657 if (hw->mac.type == e1000_pchlan) {
2658 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2659 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2660 goto release;
2661 }
2662
2663 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2664 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2665 goto release;
2666
2667 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2668
2669 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2670 if (ret_val)
2671 goto release;
2672
2673 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2674
2675 if (d0_state) {
2676 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2677 oem_reg |= HV_OEM_BITS_GBE_DIS;
2678
2679 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2680 oem_reg |= HV_OEM_BITS_LPLU;
2681 } else {
2682 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2683 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2684 oem_reg |= HV_OEM_BITS_GBE_DIS;
2685
2686 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2687 E1000_PHY_CTRL_NOND0A_LPLU))
2688 oem_reg |= HV_OEM_BITS_LPLU;
2689 }
2690
2691 /* Set Restart auto-neg to activate the bits */
2692 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2693 !hw->phy.ops.check_reset_block(hw))
2694 oem_reg |= HV_OEM_BITS_RESTART_AN;
2695
2696 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2697
2698 release:
2699 hw->phy.ops.release(hw);
2700
2701 return ret_val;
2702 }
2703
2704
2705 /**
2706 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2707 * @hw: pointer to the HW structure
2708 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2709 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2710 {
2711 s32 ret_val;
2712 u16 data;
2713
2714 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2715
2716 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2717 if (ret_val)
2718 return ret_val;
2719
2720 data |= HV_KMRN_MDIO_SLOW;
2721
2722 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2723
2724 return ret_val;
2725 }
2726
2727 /**
2728 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2729 * done after every PHY reset.
2730 * @hw: pointer to the HW structure
2731 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2732 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2733 {
2734 s32 ret_val = E1000_SUCCESS;
2735 u16 phy_data;
2736
2737 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2738
2739 if (hw->mac.type != e1000_pchlan)
2740 return E1000_SUCCESS;
2741
2742 /* Set MDIO slow mode before any other MDIO access */
2743 if (hw->phy.type == e1000_phy_82577) {
2744 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2745 if (ret_val)
2746 return ret_val;
2747 }
2748
2749 if (((hw->phy.type == e1000_phy_82577) &&
2750 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2751 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2752 /* Disable generation of early preamble */
2753 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2754 if (ret_val)
2755 return ret_val;
2756
2757 /* Preamble tuning for SSC */
2758 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2759 0xA204);
2760 if (ret_val)
2761 return ret_val;
2762 }
2763
2764 if (hw->phy.type == e1000_phy_82578) {
2765 /* Return registers to default by doing a soft reset then
2766 * writing 0x3140 to the control register.
2767 */
2768 if (hw->phy.revision < 2) {
2769 e1000_phy_sw_reset_generic(hw);
2770 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2771 0x3140);
2772 if (ret_val)
2773 return ret_val;
2774 }
2775 }
2776
2777 /* Select page 0 */
2778 ret_val = hw->phy.ops.acquire(hw);
2779 if (ret_val)
2780 return ret_val;
2781
2782 hw->phy.addr = 1;
2783 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2784 hw->phy.ops.release(hw);
2785 if (ret_val)
2786 return ret_val;
2787
2788 /* Configure the K1 Si workaround during phy reset assuming there is
2789 * link so that it disables K1 if link is in 1Gbps.
2790 */
2791 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2792 if (ret_val)
2793 return ret_val;
2794
2795 /* Workaround for link disconnects on a busy hub in half duplex */
2796 ret_val = hw->phy.ops.acquire(hw);
2797 if (ret_val)
2798 return ret_val;
2799 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2800 if (ret_val)
2801 goto release;
2802 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2803 phy_data & 0x00FF);
2804 if (ret_val)
2805 goto release;
2806
2807 /* set MSE higher to enable link to stay up when noise is high */
2808 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2809 release:
2810 hw->phy.ops.release(hw);
2811
2812 return ret_val;
2813 }
2814
2815 /**
2816 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2817 * @hw: pointer to the HW structure
2818 *
2819 * Returns E1000_SUCCESS when every PHY receive address was programmed.
2820 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2821 s32 e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2822 {
2823 u32 mac_reg;
2824 u16 i, phy_reg = 0;
2825 s32 ret_val, restore_val;
2826
2827 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2828
2829 ret_val = hw->phy.ops.acquire(hw);
2830 if (ret_val)
2831 return ret_val;
2832 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2833 if (ret_val)
2834 goto release;
2835
2836 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2837 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2838 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2839 ret_val = hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2840 (u16)(mac_reg & 0xFFFF));
2841 if (ret_val)
2842 goto restore;
2843 ret_val = hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2844 (u16)((mac_reg >> 16) & 0xFFFF));
2845 if (ret_val)
2846 goto restore;
2847
2848 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2849 ret_val = hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2850 (u16)(mac_reg & 0xFFFF));
2851 if (ret_val)
2852 goto restore;
2853 ret_val = hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2854 (u16)((mac_reg & E1000_RAH_AV) >> 16));
2855 if (ret_val)
2856 goto restore;
2857 }
2858
2859 restore:
2860 restore_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2861 if (ret_val == E1000_SUCCESS)
2862 ret_val = restore_val;
2863
2864 release:
2865 hw->phy.ops.release(hw);
2866 return ret_val;
2867 }
2868
e1000_calc_rx_da_crc(u8 mac[])2869 static u32 e1000_calc_rx_da_crc(u8 mac[])
2870 {
2871 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2872 u32 i, j, mask, crc;
2873
2874 DEBUGFUNC("e1000_calc_rx_da_crc");
2875
2876 crc = 0xffffffff;
2877 for (i = 0; i < 6; i++) {
2878 crc = crc ^ mac[i];
2879 for (j = 8; j > 0; j--) {
2880 mask = (crc & 1) * (-1);
2881 crc = (crc >> 1) ^ (poly & mask);
2882 }
2883 }
2884 return ~crc;
2885 }
2886
2887 /**
2888 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2889 * with 82579 PHY
2890 * @hw: pointer to the HW structure
2891 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2892 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2893 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2894 {
2895 s32 ret_val = E1000_SUCCESS;
2896 u16 phy_reg, data;
2897 u32 mac_reg;
2898 u16 i;
2899
2900 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2901
2902 if (hw->mac.type < e1000_pch2lan)
2903 return E1000_SUCCESS;
2904
2905 /* disable Rx path while enabling/disabling workaround */
2906 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2907 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2908 phy_reg | (1 << 14));
2909 if (ret_val)
2910 return ret_val;
2911
2912 if (enable) {
2913 /* Write Rx addresses (rar_entry_count for RAL/H, and
2914 * SHRAL/H) and initial CRC values to the MAC
2915 */
2916 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2917 u8 mac_addr[ETHER_ADDR_LEN] = {0};
2918 u32 addr_high, addr_low;
2919
2920 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2921 if (!(addr_high & E1000_RAH_AV))
2922 continue;
2923 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2924 mac_addr[0] = (addr_low & 0xFF);
2925 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2926 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2927 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2928 mac_addr[4] = (addr_high & 0xFF);
2929 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2930
2931 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2932 e1000_calc_rx_da_crc(mac_addr));
2933 }
2934
2935 /* Write Rx addresses to the PHY */
2936 (void)e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2937
2938 /* Enable jumbo frame workaround in the MAC */
2939 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2940 mac_reg &= ~(1 << 14);
2941 mac_reg |= (7 << 15);
2942 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2943
2944 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2945 mac_reg |= E1000_RCTL_SECRC;
2946 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2947
2948 ret_val = e1000_read_kmrn_reg_generic(hw,
2949 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2950 &data);
2951 if (ret_val)
2952 return ret_val;
2953 ret_val = e1000_write_kmrn_reg_generic(hw,
2954 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2955 data | (1 << 0));
2956 if (ret_val)
2957 return ret_val;
2958 ret_val = e1000_read_kmrn_reg_generic(hw,
2959 E1000_KMRNCTRLSTA_HD_CTRL,
2960 &data);
2961 if (ret_val)
2962 return ret_val;
2963 data &= ~(0xF << 8);
2964 data |= (0xB << 8);
2965 ret_val = e1000_write_kmrn_reg_generic(hw,
2966 E1000_KMRNCTRLSTA_HD_CTRL,
2967 data);
2968 if (ret_val)
2969 return ret_val;
2970
2971 /* Enable jumbo frame workaround in the PHY */
2972 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2973 data &= ~(0x7F << 5);
2974 data |= (0x37 << 5);
2975 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2976 if (ret_val)
2977 return ret_val;
2978 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2979 data &= ~(1 << 13);
2980 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2981 if (ret_val)
2982 return ret_val;
2983 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2984 data &= ~(0x3FF << 2);
2985 data |= (E1000_TX_PTR_GAP << 2);
2986 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2987 if (ret_val)
2988 return ret_val;
2989 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2990 if (ret_val)
2991 return ret_val;
2992 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2993 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2994 (1 << 10));
2995 if (ret_val)
2996 return ret_val;
2997 } else {
2998 /* Write MAC register values back to h/w defaults */
2999 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
3000 mac_reg &= ~(0xF << 14);
3001 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
3002
3003 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
3004 mac_reg &= ~E1000_RCTL_SECRC;
3005 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
3006
3007 ret_val = e1000_read_kmrn_reg_generic(hw,
3008 E1000_KMRNCTRLSTA_CTRL_OFFSET,
3009 &data);
3010 if (ret_val)
3011 return ret_val;
3012 ret_val = e1000_write_kmrn_reg_generic(hw,
3013 E1000_KMRNCTRLSTA_CTRL_OFFSET,
3014 data & ~(1 << 0));
3015 if (ret_val)
3016 return ret_val;
3017 ret_val = e1000_read_kmrn_reg_generic(hw,
3018 E1000_KMRNCTRLSTA_HD_CTRL,
3019 &data);
3020 if (ret_val)
3021 return ret_val;
3022 data &= ~(0xF << 8);
3023 data |= (0xB << 8);
3024 ret_val = e1000_write_kmrn_reg_generic(hw,
3025 E1000_KMRNCTRLSTA_HD_CTRL,
3026 data);
3027 if (ret_val)
3028 return ret_val;
3029
3030 /* Write PHY register values back to h/w defaults */
3031 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
3032 data &= ~(0x7F << 5);
3033 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
3034 if (ret_val)
3035 return ret_val;
3036 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
3037 data |= (1 << 13);
3038 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
3039 if (ret_val)
3040 return ret_val;
3041 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
3042 data &= ~(0x3FF << 2);
3043 data |= (0x8 << 2);
3044 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
3045 if (ret_val)
3046 return ret_val;
3047 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
3048 if (ret_val)
3049 return ret_val;
3050 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
3051 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
3052 ~(1 << 10));
3053 if (ret_val)
3054 return ret_val;
3055 }
3056
3057 /* re-enable Rx path after enabling/disabling workaround */
3058 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
3059 ~(1 << 14));
3060 }
3061
3062 /**
3063 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
3064 * done after every PHY reset.
3065 * @hw: pointer to the HW structure
3066 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)3067 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
3068 {
3069 s32 ret_val = E1000_SUCCESS;
3070
3071 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
3072
3073 if (hw->mac.type != e1000_pch2lan)
3074 return E1000_SUCCESS;
3075
3076 /* Set MDIO slow mode before any other MDIO access */
3077 ret_val = e1000_set_mdio_slow_mode_hv(hw);
3078 if (ret_val)
3079 return ret_val;
3080
3081 ret_val = hw->phy.ops.acquire(hw);
3082 if (ret_val)
3083 return ret_val;
3084 /* set MSE higher to enable link to stay up when noise is high */
3085 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
3086 if (ret_val)
3087 goto release;
3088 /* drop link after 5 times MSE threshold was reached */
3089 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
3090 release:
3091 hw->phy.ops.release(hw);
3092
3093 return ret_val;
3094 }
3095
3096 /**
3097 * e1000_k1_gig_workaround_lv - K1 Si workaround
3098 * @hw: pointer to the HW structure
3099 *
3100 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
3101 * Disable K1 for 1000 and 100 speeds
3102 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)3103 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
3104 {
3105 s32 ret_val = E1000_SUCCESS;
3106 u16 status_reg = 0;
3107
3108 DEBUGFUNC("e1000_k1_workaround_lv");
3109
3110 if (hw->mac.type != e1000_pch2lan)
3111 return E1000_SUCCESS;
3112
3113 /* Set K1 beacon duration based on 10Mbs speed */
3114 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
3115 if (ret_val)
3116 return ret_val;
3117
3118 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
3119 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
3120 if (status_reg &
3121 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
3122 u16 pm_phy_reg;
3123
3124 /* LV 1G/100 Packet drop issue wa */
3125 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3126 &pm_phy_reg);
3127 if (ret_val)
3128 return ret_val;
3129 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
3130 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3131 pm_phy_reg);
3132 if (ret_val)
3133 return ret_val;
3134 } else {
3135 u32 mac_reg;
3136 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3137 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3138 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3139 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3140 }
3141 }
3142
3143 return ret_val;
3144 }
3145
3146 /**
3147 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3148 * @hw: pointer to the HW structure
3149 * @gate: boolean set to true to gate, false to ungate
3150 *
3151 * Gate/ungate the automatic PHY configuration via hardware; perform
3152 * the configuration via software instead.
3153 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)3154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3155 {
3156 u32 extcnf_ctrl;
3157
3158 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3159
3160 if (hw->mac.type < e1000_pch2lan)
3161 return;
3162
3163 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3164
3165 if (gate)
3166 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3167 else
3168 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3169
3170 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3171 }
3172
3173 /**
3174 * e1000_lan_init_done_ich8lan - Check for PHY config completion
3175 * @hw: pointer to the HW structure
3176 *
3177 * Check the appropriate indication the MAC has finished configuring the
3178 * PHY after a software reset.
3179 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)3180 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3181 {
3182 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3183
3184 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3185
3186 /* Wait for basic configuration completes before proceeding */
3187 do {
3188 data = E1000_READ_REG(hw, E1000_STATUS);
3189 data &= E1000_STATUS_LAN_INIT_DONE;
3190 usec_delay(100);
3191 } while ((!data) && --loop);
3192
3193 /* If basic configuration is incomplete before the above loop
3194 * count reaches 0, loading the configuration from NVM will
3195 * leave the PHY in a bad state possibly resulting in no link.
3196 */
3197 if (loop == 0)
3198 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3199
3200 /* Clear the Init Done bit for the next init event */
3201 data = E1000_READ_REG(hw, E1000_STATUS);
3202 data &= ~E1000_STATUS_LAN_INIT_DONE;
3203 E1000_WRITE_REG(hw, E1000_STATUS, data);
3204 }
3205
3206 /**
3207 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3208 * @hw: pointer to the HW structure
3209 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)3210 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3211 {
3212 s32 ret_val = E1000_SUCCESS;
3213 u16 reg;
3214
3215 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3216
3217 if (hw->phy.ops.check_reset_block(hw))
3218 return E1000_SUCCESS;
3219
3220 /* Allow time for h/w to get to quiescent state after reset */
3221 msec_delay(10);
3222
3223 /* Perform any necessary post-reset workarounds */
3224 switch (hw->mac.type) {
3225 case e1000_pchlan:
3226 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3227 if (ret_val)
3228 return ret_val;
3229 break;
3230 case e1000_pch2lan:
3231 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3232 if (ret_val)
3233 return ret_val;
3234 break;
3235 default:
3236 break;
3237 }
3238
3239 /* Clear the host wakeup bit after lcd reset */
3240 if (hw->mac.type >= e1000_pchlan) {
3241 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3242 reg &= ~BM_WUC_HOST_WU_BIT;
3243 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3244 }
3245
3246 /* Configure the LCD with the extended configuration region in NVM */
3247 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3248 if (ret_val)
3249 return ret_val;
3250
3251 /* Configure the LCD with the OEM bits in NVM */
3252 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3253
3254 if (hw->mac.type == e1000_pch2lan) {
3255 /* Ungate automatic PHY configuration on non-managed 82579 */
3256 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3257 E1000_ICH_FWSM_FW_VALID)) {
3258 msec_delay(10);
3259 e1000_gate_hw_phy_config_ich8lan(hw, false);
3260 }
3261
3262 /* Set EEE LPI Update Timer to 200usec */
3263 ret_val = hw->phy.ops.acquire(hw);
3264 if (ret_val)
3265 return ret_val;
3266 ret_val = e1000_write_emi_reg_locked(hw,
3267 I82579_LPI_UPDATE_TIMER,
3268 0x1387);
3269 hw->phy.ops.release(hw);
3270 }
3271
3272 return ret_val;
3273 }
3274
3275 /**
3276 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3277 * @hw: pointer to the HW structure
3278 *
3279 * Resets the PHY
3280 * This is a function pointer entry point called by drivers
3281 * or other shared routines.
3282 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)3283 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3284 {
3285 s32 ret_val = E1000_SUCCESS;
3286
3287 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3288
3289 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3290 if ((hw->mac.type == e1000_pch2lan) &&
3291 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3292 e1000_gate_hw_phy_config_ich8lan(hw, true);
3293
3294 ret_val = e1000_phy_hw_reset_generic(hw);
3295 if (ret_val)
3296 return ret_val;
3297
3298 return e1000_post_phy_reset_ich8lan(hw);
3299 }
3300
3301 /**
3302 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3303 * @hw: pointer to the HW structure
3304 * @active: true to enable LPLU, false to disable
3305 *
3306 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3307 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3308 * the phy speed. This function will manually set the LPLU bit and restart
3309 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3310 * since it configures the same bit.
3311 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)3312 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3313 {
3314 s32 ret_val;
3315 u16 oem_reg;
3316
3317 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3318 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3319 if (ret_val)
3320 return ret_val;
3321
3322 if (active)
3323 oem_reg |= HV_OEM_BITS_LPLU;
3324 else
3325 oem_reg &= ~HV_OEM_BITS_LPLU;
3326
3327 if (!hw->phy.ops.check_reset_block(hw))
3328 oem_reg |= HV_OEM_BITS_RESTART_AN;
3329
3330 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3331 }
3332
3333 /**
3334 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3335 * @hw: pointer to the HW structure
3336 * @active: true to enable LPLU, false to disable
3337 *
3338 * Sets the LPLU D0 state according to the active flag. When
3339 * activating LPLU this function also disables smart speed
3340 * and vice versa. LPLU will not be activated unless the
3341 * device autonegotiation advertisement meets standards of
3342 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3343 * This is a function pointer entry point only called by
3344 * PHY setup routines.
3345 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3346 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3347 {
3348 struct e1000_phy_info *phy = &hw->phy;
3349 u32 phy_ctrl;
3350 s32 ret_val = E1000_SUCCESS;
3351 u16 data;
3352
3353 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3354
3355 if (phy->type == e1000_phy_ife)
3356 return E1000_SUCCESS;
3357
3358 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3359
3360 if (active) {
3361 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3362 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3363
3364 if (phy->type != e1000_phy_igp_3)
3365 return E1000_SUCCESS;
3366
3367 /* Call gig speed drop workaround on LPLU before accessing
3368 * any PHY registers
3369 */
3370 if (hw->mac.type == e1000_ich8lan)
3371 e1000_gig_downshift_workaround_ich8lan(hw);
3372
3373 /* When LPLU is enabled, we should disable SmartSpeed */
3374 ret_val = phy->ops.read_reg(hw,
3375 IGP01E1000_PHY_PORT_CONFIG,
3376 &data);
3377 if (ret_val)
3378 return ret_val;
3379 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3380 ret_val = phy->ops.write_reg(hw,
3381 IGP01E1000_PHY_PORT_CONFIG,
3382 data);
3383 if (ret_val)
3384 return ret_val;
3385 } else {
3386 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3387 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3388
3389 if (phy->type != e1000_phy_igp_3)
3390 return E1000_SUCCESS;
3391
3392 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3393 * during Dx states where the power conservation is most
3394 * important. During driver activity we should enable
3395 * SmartSpeed, so performance is maintained.
3396 */
3397 if (phy->smart_speed == e1000_smart_speed_on) {
3398 ret_val = phy->ops.read_reg(hw,
3399 IGP01E1000_PHY_PORT_CONFIG,
3400 &data);
3401 if (ret_val)
3402 return ret_val;
3403
3404 data |= IGP01E1000_PSCFR_SMART_SPEED;
3405 ret_val = phy->ops.write_reg(hw,
3406 IGP01E1000_PHY_PORT_CONFIG,
3407 data);
3408 if (ret_val)
3409 return ret_val;
3410 } else if (phy->smart_speed == e1000_smart_speed_off) {
3411 ret_val = phy->ops.read_reg(hw,
3412 IGP01E1000_PHY_PORT_CONFIG,
3413 &data);
3414 if (ret_val)
3415 return ret_val;
3416
3417 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3418 ret_val = phy->ops.write_reg(hw,
3419 IGP01E1000_PHY_PORT_CONFIG,
3420 data);
3421 if (ret_val)
3422 return ret_val;
3423 }
3424 }
3425
3426 return E1000_SUCCESS;
3427 }
3428
3429 /**
3430 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3431 * @hw: pointer to the HW structure
3432 * @active: true to enable LPLU, false to disable
3433 *
3434 * Sets the LPLU D3 state according to the active flag. When
3435 * activating LPLU this function also disables smart speed
3436 * and vice versa. LPLU will not be activated unless the
3437 * device autonegotiation advertisement meets standards of
3438 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3439 * This is a function pointer entry point only called by
3440 * PHY setup routines.
3441 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3442 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3443 {
3444 struct e1000_phy_info *phy = &hw->phy;
3445 u32 phy_ctrl;
3446 s32 ret_val = E1000_SUCCESS;
3447 u16 data;
3448
3449 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3450
3451 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3452
3453 if (!active) {
3454 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3455 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3456
3457 if (phy->type != e1000_phy_igp_3)
3458 return E1000_SUCCESS;
3459
3460 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3461 * during Dx states where the power conservation is most
3462 * important. During driver activity we should enable
3463 * SmartSpeed, so performance is maintained.
3464 */
3465 if (phy->smart_speed == e1000_smart_speed_on) {
3466 ret_val = phy->ops.read_reg(hw,
3467 IGP01E1000_PHY_PORT_CONFIG,
3468 &data);
3469 if (ret_val)
3470 return ret_val;
3471
3472 data |= IGP01E1000_PSCFR_SMART_SPEED;
3473 ret_val = phy->ops.write_reg(hw,
3474 IGP01E1000_PHY_PORT_CONFIG,
3475 data);
3476 if (ret_val)
3477 return ret_val;
3478 } else if (phy->smart_speed == e1000_smart_speed_off) {
3479 ret_val = phy->ops.read_reg(hw,
3480 IGP01E1000_PHY_PORT_CONFIG,
3481 &data);
3482 if (ret_val)
3483 return ret_val;
3484
3485 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3486 ret_val = phy->ops.write_reg(hw,
3487 IGP01E1000_PHY_PORT_CONFIG,
3488 data);
3489 if (ret_val)
3490 return ret_val;
3491 }
3492 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3493 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3494 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3495 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3496 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3497
3498 if (phy->type != e1000_phy_igp_3)
3499 return E1000_SUCCESS;
3500
3501 /* Call gig speed drop workaround on LPLU before accessing
3502 * any PHY registers
3503 */
3504 if (hw->mac.type == e1000_ich8lan)
3505 e1000_gig_downshift_workaround_ich8lan(hw);
3506
3507 /* When LPLU is enabled, we should disable SmartSpeed */
3508 ret_val = phy->ops.read_reg(hw,
3509 IGP01E1000_PHY_PORT_CONFIG,
3510 &data);
3511 if (ret_val)
3512 return ret_val;
3513
3514 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3515 ret_val = phy->ops.write_reg(hw,
3516 IGP01E1000_PHY_PORT_CONFIG,
3517 data);
3518 }
3519
3520 return ret_val;
3521 }
3522
3523 /**
3524 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3525 * @hw: pointer to the HW structure
3526 * @bank: pointer to the variable that returns the active bank
3527 *
3528 * Reads signature byte from the NVM using the flash access registers.
3529 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3530 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)3531 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3532 {
3533 u32 eecd;
3534 struct e1000_nvm_info *nvm = &hw->nvm;
3535 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3536 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3537 u32 nvm_dword = 0;
3538 u8 sig_byte = 0;
3539 s32 ret_val;
3540
3541 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3542
3543 switch (hw->mac.type) {
3544 case e1000_pch_spt:
3545 case e1000_pch_cnp:
3546 case e1000_pch_tgp:
3547 case e1000_pch_adp:
3548 case e1000_pch_mtp:
3549 case e1000_pch_ptp:
3550 case e1000_pch_nvp:
3551 bank1_offset = nvm->flash_bank_size;
3552 act_offset = E1000_ICH_NVM_SIG_WORD;
3553
3554 /* set bank to 0 in case flash read fails */
3555 *bank = 0;
3556
3557 /* Check bank 0 */
3558 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3559 &nvm_dword);
3560 if (ret_val)
3561 return ret_val;
3562 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3563 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3564 E1000_ICH_NVM_SIG_VALUE) {
3565 *bank = 0;
3566 return E1000_SUCCESS;
3567 }
3568
3569 /* Check bank 1 */
3570 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3571 bank1_offset,
3572 &nvm_dword);
3573 if (ret_val)
3574 return ret_val;
3575 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3576 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3577 E1000_ICH_NVM_SIG_VALUE) {
3578 *bank = 1;
3579 return E1000_SUCCESS;
3580 }
3581
3582 DEBUGOUT("ERROR: No valid NVM bank present\n");
3583 return -E1000_ERR_NVM;
3584 case e1000_ich8lan:
3585 case e1000_ich9lan:
3586 eecd = E1000_READ_REG(hw, E1000_EECD);
3587 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3588 E1000_EECD_SEC1VAL_VALID_MASK) {
3589 if (eecd & E1000_EECD_SEC1VAL)
3590 *bank = 1;
3591 else
3592 *bank = 0;
3593
3594 return E1000_SUCCESS;
3595 }
3596 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3597 /* FALLTHROUGH */
3598 default:
3599 /* set bank to 0 in case flash read fails */
3600 *bank = 0;
3601
3602 /* Check bank 0 */
3603 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3604 &sig_byte);
3605 if (ret_val)
3606 return ret_val;
3607 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3608 E1000_ICH_NVM_SIG_VALUE) {
3609 *bank = 0;
3610 return E1000_SUCCESS;
3611 }
3612
3613 /* Check bank 1 */
3614 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3615 bank1_offset,
3616 &sig_byte);
3617 if (ret_val)
3618 return ret_val;
3619 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3620 E1000_ICH_NVM_SIG_VALUE) {
3621 *bank = 1;
3622 return E1000_SUCCESS;
3623 }
3624
3625 DEBUGOUT("ERROR: No valid NVM bank present\n");
3626 return -E1000_ERR_NVM;
3627 }
3628 }
3629
3630 /**
3631 * e1000_read_nvm_spt - NVM access for SPT
3632 * @hw: pointer to the HW structure
3633 * @offset: The offset (in bytes) of the word(s) to read.
3634 * @words: Size of data to read in words.
3635 * @data: pointer to the word(s) to read at offset.
3636 *
3637 * Reads a word(s) from the NVM
3638 **/
e1000_read_nvm_spt(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3639 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3640 u16 *data)
3641 {
3642 struct e1000_nvm_info *nvm = &hw->nvm;
3643 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3644 u32 act_offset;
3645 s32 ret_val = E1000_SUCCESS;
3646 u32 bank = 0;
3647 u32 dword = 0;
3648 u16 offset_to_read;
3649 u16 i;
3650
3651 DEBUGFUNC("e1000_read_nvm_spt");
3652
3653 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3654 (words == 0)) {
3655 DEBUGOUT("nvm parameter(s) out of bounds\n");
3656 ret_val = -E1000_ERR_NVM;
3657 goto out;
3658 }
3659
3660 nvm->ops.acquire(hw);
3661
3662 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3663 if (ret_val != E1000_SUCCESS) {
3664 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3665 bank = 0;
3666 }
3667
3668 act_offset = (bank) ? nvm->flash_bank_size : 0;
3669 act_offset += offset;
3670
3671 ret_val = E1000_SUCCESS;
3672
3673 for (i = 0; i < words; i += 2) {
3674 if (words - i == 1) {
3675 if (dev_spec->shadow_ram[offset + i].modified) {
3676 data[i] =
3677 dev_spec->shadow_ram[offset + i].value;
3678 } else {
3679 offset_to_read = act_offset + i -
3680 ((act_offset + i) % 2);
3681 ret_val =
3682 e1000_read_flash_dword_ich8lan(hw,
3683 offset_to_read,
3684 &dword);
3685 if (ret_val)
3686 break;
3687 if ((act_offset + i) % 2 == 0)
3688 data[i] = (u16)(dword & 0xFFFF);
3689 else
3690 data[i] = (u16)((dword >> 16) & 0xFFFF);
3691 }
3692 } else {
3693 offset_to_read = act_offset + i;
3694 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3695 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3696 ret_val =
3697 e1000_read_flash_dword_ich8lan(hw,
3698 offset_to_read,
3699 &dword);
3700 if (ret_val)
3701 break;
3702 }
3703 if (dev_spec->shadow_ram[offset + i].modified)
3704 data[i] =
3705 dev_spec->shadow_ram[offset + i].value;
3706 else
3707 data[i] = (u16)(dword & 0xFFFF);
3708 if (dev_spec->shadow_ram[offset + i + 1].modified)
3709 data[i + 1] =
3710 dev_spec->shadow_ram[offset + i + 1].value;
3711 else
3712 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3713 }
3714 }
3715
3716 nvm->ops.release(hw);
3717
3718 out:
3719 if (ret_val)
3720 DEBUGOUT1("NVM read error: %d\n", ret_val);
3721
3722 return ret_val;
3723 }
3724
3725 /**
3726 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3727 * @hw: pointer to the HW structure
3728 * @offset: The offset (in bytes) of the word(s) to read.
3729 * @words: Size of data to read in words
3730 * @data: Pointer to the word(s) to read at offset.
3731 *
3732 * Reads a word(s) from the NVM using the flash access registers.
3733 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3734 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3735 u16 *data)
3736 {
3737 struct e1000_nvm_info *nvm = &hw->nvm;
3738 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3739 u32 act_offset;
3740 s32 ret_val = E1000_SUCCESS;
3741 u32 bank = 0;
3742 u16 i, word;
3743
3744 DEBUGFUNC("e1000_read_nvm_ich8lan");
3745
3746 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3747 (words == 0)) {
3748 DEBUGOUT("nvm parameter(s) out of bounds\n");
3749 ret_val = -E1000_ERR_NVM;
3750 goto out;
3751 }
3752
3753 nvm->ops.acquire(hw);
3754
3755 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3756 if (ret_val != E1000_SUCCESS) {
3757 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3758 bank = 0;
3759 }
3760
3761 act_offset = (bank) ? nvm->flash_bank_size : 0;
3762 act_offset += offset;
3763
3764 ret_val = E1000_SUCCESS;
3765 for (i = 0; i < words; i++) {
3766 if (dev_spec->shadow_ram[offset + i].modified) {
3767 data[i] = dev_spec->shadow_ram[offset + i].value;
3768 } else {
3769 ret_val = e1000_read_flash_word_ich8lan(hw,
3770 act_offset + i,
3771 &word);
3772 if (ret_val)
3773 break;
3774 data[i] = word;
3775 }
3776 }
3777
3778 nvm->ops.release(hw);
3779
3780 out:
3781 if (ret_val)
3782 DEBUGOUT1("NVM read error: %d\n", ret_val);
3783
3784 return ret_val;
3785 }
3786
3787 /**
3788 * e1000_flash_cycle_init_ich8lan - Initialize flash
3789 * @hw: pointer to the HW structure
3790 *
3791 * This function does initial flash setup so that a new read/write/erase cycle
3792 * can be started.
3793 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3794 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3795 {
3796 union ich8_hws_flash_status hsfsts;
3797 s32 ret_val = -E1000_ERR_NVM;
3798
3799 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3800
3801 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3802
3803 /* Check if the flash descriptor is valid */
3804 if (!hsfsts.hsf_status.fldesvalid) {
3805 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3806 return -E1000_ERR_NVM;
3807 }
3808
3809 /* Clear FCERR and DAEL in hw status by writing 1 */
3810 hsfsts.hsf_status.flcerr = 1;
3811 hsfsts.hsf_status.dael = 1;
3812 if (hw->mac.type >= e1000_pch_spt)
3813 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3814 hsfsts.regval & 0xFFFF);
3815 else
3816 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3817
3818 /* Either we should have a hardware SPI cycle in progress
3819 * bit to check against, in order to start a new cycle or
3820 * FDONE bit should be changed in the hardware so that it
3821 * is 1 after hardware reset, which can then be used as an
3822 * indication whether a cycle is in progress or has been
3823 * completed.
3824 */
3825
3826 if (!hsfsts.hsf_status.flcinprog) {
3827 /* There is no cycle running at present,
3828 * so we can start a cycle.
3829 * Begin by setting Flash Cycle Done.
3830 */
3831 hsfsts.hsf_status.flcdone = 1;
3832 if (hw->mac.type >= e1000_pch_spt)
3833 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3834 hsfsts.regval & 0xFFFF);
3835 else
3836 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3837 hsfsts.regval);
3838 ret_val = E1000_SUCCESS;
3839 } else {
3840 s32 i;
3841
3842 /* Otherwise poll for sometime so the current
3843 * cycle has a chance to end before giving up.
3844 */
3845 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3846 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3847 ICH_FLASH_HSFSTS);
3848 if (!hsfsts.hsf_status.flcinprog) {
3849 ret_val = E1000_SUCCESS;
3850 break;
3851 }
3852 usec_delay(1);
3853 }
3854 if (ret_val == E1000_SUCCESS) {
3855 /* Successful in waiting for previous cycle to timeout,
3856 * now set the Flash Cycle Done.
3857 */
3858 hsfsts.hsf_status.flcdone = 1;
3859 if (hw->mac.type >= e1000_pch_spt)
3860 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3861 hsfsts.regval & 0xFFFF);
3862 else
3863 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3864 hsfsts.regval);
3865 } else {
3866 DEBUGOUT("Flash controller busy, cannot get access\n");
3867 }
3868 }
3869
3870 return ret_val;
3871 }
3872
3873 /**
3874 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3875 * @hw: pointer to the HW structure
3876 * @timeout: maximum time to wait for completion
3877 *
3878 * This function starts a flash cycle and waits for its completion.
3879 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3880 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3881 {
3882 union ich8_hws_flash_ctrl hsflctl;
3883 union ich8_hws_flash_status hsfsts;
3884 u32 i = 0;
3885
3886 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3887
3888 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3889 if (hw->mac.type >= e1000_pch_spt)
3890 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3891 else
3892 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3893 hsflctl.hsf_ctrl.flcgo = 1;
3894
3895 if (hw->mac.type >= e1000_pch_spt)
3896 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3897 hsflctl.regval << 16);
3898 else
3899 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3900
3901 /* wait till FDONE bit is set to 1 */
3902 do {
3903 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3904 if (hsfsts.hsf_status.flcdone)
3905 break;
3906 usec_delay(1);
3907 } while (i++ < timeout);
3908
3909 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3910 return E1000_SUCCESS;
3911
3912 return -E1000_ERR_NVM;
3913 }
3914
3915 /**
3916 * e1000_read_flash_dword_ich8lan - Read dword from flash
3917 * @hw: pointer to the HW structure
3918 * @offset: offset to data location
3919 * @data: pointer to the location for storing the data
3920 *
3921 * Reads the flash dword at offset into data. Offset is converted
3922 * to bytes before read.
3923 **/
e1000_read_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3924 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3925 u32 *data)
3926 {
3927 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3928
3929 if (!data)
3930 return -E1000_ERR_NVM;
3931
3932 /* Must convert word offset into bytes. */
3933 offset <<= 1;
3934
3935 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3936 }
3937
3938 /**
3939 * e1000_read_flash_word_ich8lan - Read word from flash
3940 * @hw: pointer to the HW structure
3941 * @offset: offset to data location
3942 * @data: pointer to the location for storing the data
3943 *
3944 * Reads the flash word at offset into data. Offset is converted
3945 * to bytes before read.
3946 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3947 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3948 u16 *data)
3949 {
3950 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3951
3952 if (!data)
3953 return -E1000_ERR_NVM;
3954
3955 /* Must convert offset into bytes. */
3956 offset <<= 1;
3957
3958 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3959 }
3960
3961 /**
3962 * e1000_read_flash_byte_ich8lan - Read byte from flash
3963 * @hw: pointer to the HW structure
3964 * @offset: The offset of the byte to read.
3965 * @data: Pointer to a byte to store the value read.
3966 *
3967 * Reads a single byte from the NVM using the flash access registers.
3968 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3969 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3970 u8 *data)
3971 {
3972 s32 ret_val;
3973 u16 word = 0;
3974
3975 /* In SPT, only 32 bits access is supported,
3976 * so this function should not be called.
3977 */
3978 if (hw->mac.type >= e1000_pch_spt)
3979 return -E1000_ERR_NVM;
3980 else
3981 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3982
3983 if (ret_val)
3984 return ret_val;
3985
3986 *data = (u8)word;
3987
3988 return E1000_SUCCESS;
3989 }
3990
3991 /**
3992 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3993 * @hw: pointer to the HW structure
3994 * @offset: The offset (in bytes) of the byte or word to read.
3995 * @size: Size of data to read, 1=byte 2=word
3996 * @data: Pointer to the word to store the value read.
3997 *
3998 * Reads a byte or word from the NVM using the flash access registers.
3999 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)4000 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4001 u8 size, u16 *data)
4002 {
4003 union ich8_hws_flash_status hsfsts;
4004 union ich8_hws_flash_ctrl hsflctl;
4005 u32 flash_linear_addr;
4006 u32 flash_data = 0;
4007 s32 ret_val = -E1000_ERR_NVM;
4008 u8 count = 0;
4009
4010 DEBUGFUNC("e1000_read_flash_data_ich8lan");
4011
4012 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4013 return -E1000_ERR_NVM;
4014 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4015 hw->nvm.flash_base_addr);
4016
4017 do {
4018 usec_delay(1);
4019 /* Steps */
4020 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4021 if (ret_val != E1000_SUCCESS)
4022 break;
4023 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4024
4025 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4026 hsflctl.hsf_ctrl.fldbcount = size - 1;
4027 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
4028 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
4029 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4030
4031 ret_val = e1000_flash_cycle_ich8lan(hw,
4032 ICH_FLASH_READ_COMMAND_TIMEOUT);
4033
4034 /* Check if FCERR is set to 1, if set to 1, clear it
4035 * and try the whole sequence a few more times, else
4036 * read in (shift in) the Flash Data0, the order is
4037 * least significant byte first msb to lsb
4038 */
4039 if (ret_val == E1000_SUCCESS) {
4040 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
4041 if (size == 1)
4042 *data = (u8)(flash_data & 0x000000FF);
4043 else if (size == 2)
4044 *data = (u16)(flash_data & 0x0000FFFF);
4045 break;
4046 } else {
4047 /* If we've gotten here, then things are probably
4048 * completely hosed, but if the error condition is
4049 * detected, it won't hurt to give it another try...
4050 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
4051 */
4052 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4053 ICH_FLASH_HSFSTS);
4054 if (hsfsts.hsf_status.flcerr) {
4055 /* Repeat for some time before giving up. */
4056 continue;
4057 } else if (!hsfsts.hsf_status.flcdone) {
4058 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4059 break;
4060 }
4061 }
4062 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4063
4064 return ret_val;
4065 }
4066
4067 /**
4068 * e1000_read_flash_data32_ich8lan - Read dword from NVM
4069 * @hw: pointer to the HW structure
4070 * @offset: The offset (in bytes) of the dword to read.
4071 * @data: Pointer to the dword to store the value read.
4072 *
4073 * Reads a byte or word from the NVM using the flash access registers.
4074 **/
e1000_read_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)4075 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4076 u32 *data)
4077 {
4078 union ich8_hws_flash_status hsfsts;
4079 union ich8_hws_flash_ctrl hsflctl;
4080 u32 flash_linear_addr;
4081 s32 ret_val = -E1000_ERR_NVM;
4082 u8 count = 0;
4083
4084 DEBUGFUNC("e1000_read_flash_data_ich8lan");
4085
4086 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
4087 hw->mac.type < e1000_pch_spt)
4088 return -E1000_ERR_NVM;
4089 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4090 hw->nvm.flash_base_addr);
4091
4092 do {
4093 usec_delay(1);
4094 /* Steps */
4095 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4096 if (ret_val != E1000_SUCCESS)
4097 break;
4098 /* In SPT, This register is in Lan memory space, not flash.
4099 * Therefore, only 32 bit access is supported
4100 */
4101 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4102
4103 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4104 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4105 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
4106 /* In SPT, This register is in Lan memory space, not flash.
4107 * Therefore, only 32 bit access is supported
4108 */
4109 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4110 (u32)hsflctl.regval << 16);
4111 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4112
4113 ret_val = e1000_flash_cycle_ich8lan(hw,
4114 ICH_FLASH_READ_COMMAND_TIMEOUT);
4115
4116 /* Check if FCERR is set to 1, if set to 1, clear it
4117 * and try the whole sequence a few more times, else
4118 * read in (shift in) the Flash Data0, the order is
4119 * least significant byte first msb to lsb
4120 */
4121 if (ret_val == E1000_SUCCESS) {
4122 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
4123 break;
4124 } else {
4125 /* If we've gotten here, then things are probably
4126 * completely hosed, but if the error condition is
4127 * detected, it won't hurt to give it another try...
4128 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
4129 */
4130 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4131 ICH_FLASH_HSFSTS);
4132 if (hsfsts.hsf_status.flcerr) {
4133 /* Repeat for some time before giving up. */
4134 continue;
4135 } else if (!hsfsts.hsf_status.flcdone) {
4136 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4137 break;
4138 }
4139 }
4140 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4141
4142 return ret_val;
4143 }
4144
4145 /**
4146 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
4147 * @hw: pointer to the HW structure
4148 * @offset: The offset (in bytes) of the word(s) to write.
4149 * @words: Size of data to write in words
4150 * @data: Pointer to the word(s) to write at offset.
4151 *
4152 * Writes a byte or word to the NVM using the flash access registers.
4153 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4154 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4155 u16 *data)
4156 {
4157 struct e1000_nvm_info *nvm = &hw->nvm;
4158 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4159 u16 i;
4160
4161 DEBUGFUNC("e1000_write_nvm_ich8lan");
4162
4163 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4164 (words == 0)) {
4165 DEBUGOUT("nvm parameter(s) out of bounds\n");
4166 return -E1000_ERR_NVM;
4167 }
4168
4169 nvm->ops.acquire(hw);
4170
4171 for (i = 0; i < words; i++) {
4172 dev_spec->shadow_ram[offset + i].modified = true;
4173 dev_spec->shadow_ram[offset + i].value = data[i];
4174 }
4175
4176 nvm->ops.release(hw);
4177
4178 return E1000_SUCCESS;
4179 }
4180
4181 /**
4182 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4183 * @hw: pointer to the HW structure
4184 *
4185 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4186 * which writes the checksum to the shadow ram. The changes in the shadow
4187 * ram are then committed to the EEPROM by processing each bank at a time
4188 * checking for the modified bit and writing only the pending changes.
4189 * After a successful commit, the shadow ram is cleared and is ready for
4190 * future writes.
4191 **/
e1000_update_nvm_checksum_spt(struct e1000_hw * hw)4192 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4193 {
4194 struct e1000_nvm_info *nvm = &hw->nvm;
4195 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4196 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4197 s32 ret_val;
4198 u32 dword = 0;
4199
4200 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4201
4202 ret_val = e1000_update_nvm_checksum_generic(hw);
4203 if (ret_val)
4204 goto out;
4205
4206 if (nvm->type != e1000_nvm_flash_sw)
4207 goto out;
4208
4209 nvm->ops.acquire(hw);
4210
4211 /* We're writing to the opposite bank so if we're on bank 1,
4212 * write to bank 0 etc. We also need to erase the segment that
4213 * is going to be written
4214 */
4215 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4216 if (ret_val != E1000_SUCCESS) {
4217 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4218 bank = 0;
4219 }
4220
4221 if (bank == 0) {
4222 new_bank_offset = nvm->flash_bank_size;
4223 old_bank_offset = 0;
4224 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4225 if (ret_val)
4226 goto release;
4227 } else {
4228 old_bank_offset = nvm->flash_bank_size;
4229 new_bank_offset = 0;
4230 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4231 if (ret_val)
4232 goto release;
4233 }
4234 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4235 /* Determine whether to write the value stored
4236 * in the other NVM bank or a modified value stored
4237 * in the shadow RAM
4238 */
4239 ret_val = e1000_read_flash_dword_ich8lan(hw,
4240 i + old_bank_offset,
4241 &dword);
4242
4243 if (dev_spec->shadow_ram[i].modified) {
4244 dword &= 0xffff0000;
4245 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4246 }
4247 if (dev_spec->shadow_ram[i + 1].modified) {
4248 dword &= 0x0000ffff;
4249 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4250 << 16);
4251 }
4252 if (ret_val)
4253 break;
4254
4255 /* If the word is 0x13, then make sure the signature bits
4256 * (15:14) are 11b until the commit has completed.
4257 * This will allow us to write 10b which indicates the
4258 * signature is valid. We want to do this after the write
4259 * has completed so that we don't mark the segment valid
4260 * while the write is still in progress
4261 */
4262 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4263 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4264
4265 /* Convert offset to bytes. */
4266 act_offset = (i + new_bank_offset) << 1;
4267
4268 usec_delay(100);
4269
4270 /* Write the data to the new bank. Offset in words*/
4271 act_offset = i + new_bank_offset;
4272 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4273 dword);
4274 if (ret_val)
4275 break;
4276 }
4277
4278 /* Don't bother writing the segment valid bits if sector
4279 * programming failed.
4280 */
4281 if (ret_val) {
4282 DEBUGOUT("Flash commit failed.\n");
4283 goto release;
4284 }
4285
4286 /* Finally validate the new segment by setting bit 15:14
4287 * to 10b in word 0x13 , this can be done without an
4288 * erase as well since these bits are 11 to start with
4289 * and we need to change bit 14 to 0b
4290 */
4291 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4292
4293 /*offset in words but we read dword*/
4294 --act_offset;
4295 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4296
4297 if (ret_val)
4298 goto release;
4299
4300 dword &= 0xBFFFFFFF;
4301 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4302
4303 if (ret_val)
4304 goto release;
4305
4306 /* offset in words but we read dword*/
4307 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4308 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4309
4310 if (ret_val)
4311 goto release;
4312
4313 dword &= 0x00FFFFFF;
4314 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4315
4316 if (ret_val)
4317 goto release;
4318
4319 /* Great! Everything worked, we can now clear the cached entries. */
4320 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4321 dev_spec->shadow_ram[i].modified = false;
4322 dev_spec->shadow_ram[i].value = 0xFFFF;
4323 }
4324
4325 release:
4326 nvm->ops.release(hw);
4327
4328 /* Reload the EEPROM, or else modifications will not appear
4329 * until after the next adapter reset.
4330 */
4331 if (!ret_val) {
4332 nvm->ops.reload(hw);
4333 msec_delay(10);
4334 }
4335
4336 out:
4337 if (ret_val)
4338 DEBUGOUT1("NVM update error: %d\n", ret_val);
4339
4340 return ret_val;
4341 }
4342
4343 /**
4344 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4345 * @hw: pointer to the HW structure
4346 *
4347 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4348 * which writes the checksum to the shadow ram. The changes in the shadow
4349 * ram are then committed to the EEPROM by processing each bank at a time
4350 * checking for the modified bit and writing only the pending changes.
4351 * After a successful commit, the shadow ram is cleared and is ready for
4352 * future writes.
4353 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)4354 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4355 {
4356 struct e1000_nvm_info *nvm = &hw->nvm;
4357 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4358 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4359 s32 ret_val;
4360 u16 data = 0;
4361
4362 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4363
4364 ret_val = e1000_update_nvm_checksum_generic(hw);
4365 if (ret_val)
4366 goto out;
4367
4368 if (nvm->type != e1000_nvm_flash_sw)
4369 goto out;
4370
4371 nvm->ops.acquire(hw);
4372
4373 /* We're writing to the opposite bank so if we're on bank 1,
4374 * write to bank 0 etc. We also need to erase the segment that
4375 * is going to be written
4376 */
4377 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4378 if (ret_val != E1000_SUCCESS) {
4379 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4380 bank = 0;
4381 }
4382
4383 if (bank == 0) {
4384 new_bank_offset = nvm->flash_bank_size;
4385 old_bank_offset = 0;
4386 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4387 if (ret_val)
4388 goto release;
4389 } else {
4390 old_bank_offset = nvm->flash_bank_size;
4391 new_bank_offset = 0;
4392 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4393 if (ret_val)
4394 goto release;
4395 }
4396 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4397 if (dev_spec->shadow_ram[i].modified) {
4398 data = dev_spec->shadow_ram[i].value;
4399 } else {
4400 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4401 old_bank_offset,
4402 &data);
4403 if (ret_val)
4404 break;
4405 }
4406 /* If the word is 0x13, then make sure the signature bits
4407 * (15:14) are 11b until the commit has completed.
4408 * This will allow us to write 10b which indicates the
4409 * signature is valid. We want to do this after the write
4410 * has completed so that we don't mark the segment valid
4411 * while the write is still in progress
4412 */
4413 if (i == E1000_ICH_NVM_SIG_WORD)
4414 data |= E1000_ICH_NVM_SIG_MASK;
4415
4416 /* Convert offset to bytes. */
4417 act_offset = (i + new_bank_offset) << 1;
4418
4419 usec_delay(100);
4420
4421 /* Write the bytes to the new bank. */
4422 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4423 act_offset,
4424 (u8)data);
4425 if (ret_val)
4426 break;
4427
4428 usec_delay(100);
4429 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4430 act_offset + 1,
4431 (u8)(data >> 8));
4432 if (ret_val)
4433 break;
4434 }
4435
4436 /* Don't bother writing the segment valid bits if sector
4437 * programming failed.
4438 */
4439 if (ret_val) {
4440 DEBUGOUT("Flash commit failed.\n");
4441 goto release;
4442 }
4443
4444 /* Finally validate the new segment by setting bit 15:14
4445 * to 10b in word 0x13 , this can be done without an
4446 * erase as well since these bits are 11 to start with
4447 * and we need to change bit 14 to 0b
4448 */
4449 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4450 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4451 if (ret_val)
4452 goto release;
4453
4454 data &= 0xBFFF;
4455 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4456 (u8)(data >> 8));
4457 if (ret_val)
4458 goto release;
4459
4460 /* And invalidate the previously valid segment by setting
4461 * its signature word (0x13) high_byte to 0b. This can be
4462 * done without an erase because flash erase sets all bits
4463 * to 1's. We can write 1's to 0's without an erase
4464 */
4465 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4466
4467 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4468
4469 if (ret_val)
4470 goto release;
4471
4472 /* Great! Everything worked, we can now clear the cached entries. */
4473 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4474 dev_spec->shadow_ram[i].modified = false;
4475 dev_spec->shadow_ram[i].value = 0xFFFF;
4476 }
4477
4478 release:
4479 nvm->ops.release(hw);
4480
4481 /* Reload the EEPROM, or else modifications will not appear
4482 * until after the next adapter reset.
4483 */
4484 if (!ret_val) {
4485 nvm->ops.reload(hw);
4486 msec_delay(10);
4487 }
4488
4489 out:
4490 if (ret_val)
4491 DEBUGOUT1("NVM update error: %d\n", ret_val);
4492
4493 return ret_val;
4494 }
4495
4496 /**
4497 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4498 * @hw: pointer to the HW structure
4499 *
4500 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4501 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4502 * calculated, in which case we need to calculate the checksum and set bit 6.
4503 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)4504 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4505 {
4506 s32 ret_val;
4507 u16 data;
4508 u16 word;
4509 u16 valid_csum_mask;
4510
4511 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4512
4513 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4514 * the checksum needs to be fixed. This bit is an indication that
4515 * the NVM was prepared by OEM software and did not calculate
4516 * the checksum...a likely scenario.
4517 */
4518 switch (hw->mac.type) {
4519 case e1000_pch_lpt:
4520 case e1000_pch_spt:
4521 case e1000_pch_cnp:
4522 case e1000_pch_tgp:
4523 case e1000_pch_adp:
4524 case e1000_pch_mtp:
4525 case e1000_pch_ptp:
4526 case e1000_pch_nvp:
4527 word = NVM_COMPAT;
4528 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4529 break;
4530 default:
4531 word = NVM_FUTURE_INIT_WORD1;
4532 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4533 break;
4534 }
4535
4536 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4537 if (ret_val)
4538 return ret_val;
4539
4540 if (!(data & valid_csum_mask)) {
4541 DEBUGOUT("NVM checksum valid bit not set\n");
4542
4543 if (hw->mac.type < e1000_pch_tgp) {
4544 data |= valid_csum_mask;
4545 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4546 if (ret_val)
4547 return ret_val;
4548 ret_val = hw->nvm.ops.update(hw);
4549 if (ret_val)
4550 return ret_val;
4551 } else if (hw->mac.type == e1000_pch_tgp) {
4552 /* Transitional TGP images may omit the valid bit. */
4553 return E1000_SUCCESS;
4554 }
4555 }
4556
4557 return e1000_validate_nvm_checksum_generic(hw);
4558 }
4559
4560 /**
4561 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4562 * @hw: pointer to the HW structure
4563 * @offset: The offset (in bytes) of the byte/word to read.
4564 * @size: Size of data to read, 1=byte 2=word
4565 * @data: The byte(s) to write to the NVM.
4566 *
4567 * Writes one/two bytes to the NVM using the flash access registers.
4568 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)4569 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4570 u8 size, u16 data)
4571 {
4572 union ich8_hws_flash_status hsfsts;
4573 union ich8_hws_flash_ctrl hsflctl;
4574 u32 flash_linear_addr;
4575 u32 flash_data = 0;
4576 s32 ret_val;
4577 u8 count = 0;
4578
4579 DEBUGFUNC("e1000_write_ich8_data");
4580
4581 if (hw->mac.type >= e1000_pch_spt) {
4582 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4583 return -E1000_ERR_NVM;
4584 } else {
4585 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4586 return -E1000_ERR_NVM;
4587 }
4588
4589 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4590 hw->nvm.flash_base_addr);
4591
4592 do {
4593 usec_delay(1);
4594 /* Steps */
4595 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4596 if (ret_val != E1000_SUCCESS)
4597 break;
4598 /* In SPT, This register is in Lan memory space, not
4599 * flash. Therefore, only 32 bit access is supported
4600 */
4601 if (hw->mac.type >= e1000_pch_spt)
4602 hsflctl.regval =
4603 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4604 else
4605 hsflctl.regval =
4606 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4607
4608 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4609 hsflctl.hsf_ctrl.fldbcount = size - 1;
4610 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4611 /* In SPT, This register is in Lan memory space,
4612 * not flash. Therefore, only 32 bit access is
4613 * supported
4614 */
4615 if (hw->mac.type >= e1000_pch_spt)
4616 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4617 hsflctl.regval << 16);
4618 else
4619 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4620 hsflctl.regval);
4621
4622 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4623
4624 if (size == 1)
4625 flash_data = (u32)data & 0x00FF;
4626 else
4627 flash_data = (u32)data;
4628
4629 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4630
4631 /* check if FCERR is set to 1 , if set to 1, clear it
4632 * and try the whole sequence a few more times else done
4633 */
4634 ret_val =
4635 e1000_flash_cycle_ich8lan(hw,
4636 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4637 if (ret_val == E1000_SUCCESS)
4638 break;
4639
4640 /* If we're here, then things are most likely
4641 * completely hosed, but if the error condition
4642 * is detected, it won't hurt to give it another
4643 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4644 */
4645 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4646 if (hsfsts.hsf_status.flcerr)
4647 /* Repeat for some time before giving up. */
4648 continue;
4649 if (!hsfsts.hsf_status.flcdone) {
4650 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4651 break;
4652 }
4653 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4654
4655 return ret_val;
4656 }
4657
4658 /**
4659 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4660 * @hw: pointer to the HW structure
4661 * @offset: The offset (in bytes) of the dwords to read.
4662 * @data: The 4 bytes to write to the NVM.
4663 *
4664 * Writes one/two/four bytes to the NVM using the flash access registers.
4665 **/
e1000_write_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 data)4666 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4667 u32 data)
4668 {
4669 union ich8_hws_flash_status hsfsts;
4670 union ich8_hws_flash_ctrl hsflctl;
4671 u32 flash_linear_addr;
4672 s32 ret_val;
4673 u8 count = 0;
4674
4675 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4676
4677 if (hw->mac.type >= e1000_pch_spt) {
4678 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4679 return -E1000_ERR_NVM;
4680 }
4681 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4682 hw->nvm.flash_base_addr);
4683 do {
4684 usec_delay(1);
4685 /* Steps */
4686 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4687 if (ret_val != E1000_SUCCESS)
4688 break;
4689
4690 /* In SPT, This register is in Lan memory space, not
4691 * flash. Therefore, only 32 bit access is supported
4692 */
4693 if (hw->mac.type >= e1000_pch_spt)
4694 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4695 ICH_FLASH_HSFSTS)
4696 >> 16;
4697 else
4698 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4699 ICH_FLASH_HSFCTL);
4700
4701 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4702 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4703
4704 /* In SPT, This register is in Lan memory space,
4705 * not flash. Therefore, only 32 bit access is
4706 * supported
4707 */
4708 if (hw->mac.type >= e1000_pch_spt)
4709 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4710 hsflctl.regval << 16);
4711 else
4712 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4713 hsflctl.regval);
4714
4715 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4716
4717 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4718
4719 /* check if FCERR is set to 1 , if set to 1, clear it
4720 * and try the whole sequence a few more times else done
4721 */
4722 ret_val = e1000_flash_cycle_ich8lan(hw,
4723 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4724
4725 if (ret_val == E1000_SUCCESS)
4726 break;
4727
4728 /* If we're here, then things are most likely
4729 * completely hosed, but if the error condition
4730 * is detected, it won't hurt to give it another
4731 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4732 */
4733 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4734
4735 if (hsfsts.hsf_status.flcerr)
4736 /* Repeat for some time before giving up. */
4737 continue;
4738 if (!hsfsts.hsf_status.flcdone) {
4739 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4740 break;
4741 }
4742 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4743
4744 return ret_val;
4745 }
4746
4747 /**
4748 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4749 * @hw: pointer to the HW structure
4750 * @offset: The index of the byte to read.
4751 * @data: The byte to write to the NVM.
4752 *
4753 * Writes a single byte to the NVM using the flash access registers.
4754 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)4755 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4756 u8 data)
4757 {
4758 u16 word = (u16)data;
4759
4760 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4761
4762 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4763 }
4764
4765 /**
4766 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4767 * @hw: pointer to the HW structure
4768 * @offset: The offset of the word to write.
4769 * @dword: The dword to write to the NVM.
4770 *
4771 * Writes a single dword to the NVM using the flash access registers.
4772 * Goes through a retry algorithm before giving up.
4773 **/
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 dword)4774 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4775 u32 offset, u32 dword)
4776 {
4777 s32 ret_val;
4778 u16 program_retries;
4779
4780 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4781
4782 /* Must convert word offset into bytes. */
4783 offset <<= 1;
4784
4785 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4786
4787 if (!ret_val)
4788 return ret_val;
4789 for (program_retries = 0; program_retries < 100; program_retries++) {
4790 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4791 usec_delay(100);
4792 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4793 if (ret_val == E1000_SUCCESS)
4794 break;
4795 }
4796 if (program_retries == 100)
4797 return -E1000_ERR_NVM;
4798
4799 return E1000_SUCCESS;
4800 }
4801
4802 /**
4803 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4804 * @hw: pointer to the HW structure
4805 * @offset: The offset of the byte to write.
4806 * @byte: The byte to write to the NVM.
4807 *
4808 * Writes a single byte to the NVM using the flash access registers.
4809 * Goes through a retry algorithm before giving up.
4810 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)4811 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4812 u32 offset, u8 byte)
4813 {
4814 s32 ret_val;
4815 u16 program_retries;
4816
4817 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4818
4819 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4820 if (!ret_val)
4821 return ret_val;
4822
4823 for (program_retries = 0; program_retries < 100; program_retries++) {
4824 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4825 usec_delay(100);
4826 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4827 if (ret_val == E1000_SUCCESS)
4828 break;
4829 }
4830 if (program_retries == 100)
4831 return -E1000_ERR_NVM;
4832
4833 return E1000_SUCCESS;
4834 }
4835
4836 /**
4837 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4838 * @hw: pointer to the HW structure
4839 * @bank: 0 for first bank, 1 for second bank, etc.
4840 *
4841 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4842 * bank N is 4096 * N + flash_reg_addr.
4843 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)4844 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4845 {
4846 struct e1000_nvm_info *nvm = &hw->nvm;
4847 union ich8_hws_flash_status hsfsts;
4848 union ich8_hws_flash_ctrl hsflctl;
4849 u32 flash_linear_addr;
4850 /* bank size is in 16bit words - adjust to bytes */
4851 u32 flash_bank_size = nvm->flash_bank_size * 2;
4852 s32 ret_val;
4853 s32 count = 0;
4854 s32 j, iteration, sector_size;
4855
4856 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4857
4858 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4859
4860 /* Determine HW Sector size: Read BERASE bits of hw flash status
4861 * register
4862 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4863 * consecutive sectors. The start index for the nth Hw sector
4864 * can be calculated as = bank * 4096 + n * 256
4865 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4866 * The start index for the nth Hw sector can be calculated
4867 * as = bank * 4096
4868 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4869 * (ich9 only, otherwise error condition)
4870 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4871 */
4872 switch (hsfsts.hsf_status.berasesz) {
4873 case 0:
4874 /* Hw sector size 256 */
4875 sector_size = ICH_FLASH_SEG_SIZE_256;
4876 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4877 break;
4878 case 1:
4879 sector_size = ICH_FLASH_SEG_SIZE_4K;
4880 iteration = 1;
4881 break;
4882 case 2:
4883 sector_size = ICH_FLASH_SEG_SIZE_8K;
4884 iteration = 1;
4885 break;
4886 case 3:
4887 sector_size = ICH_FLASH_SEG_SIZE_64K;
4888 iteration = 1;
4889 break;
4890 default:
4891 return -E1000_ERR_NVM;
4892 }
4893
4894 /* Start with the base address, then add the sector offset. */
4895 flash_linear_addr = hw->nvm.flash_base_addr;
4896 flash_linear_addr += (bank) ? flash_bank_size : 0;
4897
4898 for (j = 0; j < iteration; j++) {
4899 do {
4900 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4901
4902 /* Steps */
4903 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4904 if (ret_val)
4905 return ret_val;
4906
4907 /* Write a value 11 (block Erase) in Flash
4908 * Cycle field in hw flash control
4909 */
4910 if (hw->mac.type >= e1000_pch_spt)
4911 hsflctl.regval =
4912 E1000_READ_FLASH_REG(hw,
4913 ICH_FLASH_HSFSTS)>>16;
4914 else
4915 hsflctl.regval =
4916 E1000_READ_FLASH_REG16(hw,
4917 ICH_FLASH_HSFCTL);
4918
4919 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4920 if (hw->mac.type >= e1000_pch_spt)
4921 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4922 hsflctl.regval << 16);
4923 else
4924 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4925 hsflctl.regval);
4926
4927 /* Write the last 24 bits of an index within the
4928 * block into Flash Linear address field in Flash
4929 * Address.
4930 */
4931 flash_linear_addr += (j * sector_size);
4932 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4933 flash_linear_addr);
4934
4935 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4936 if (ret_val == E1000_SUCCESS)
4937 break;
4938
4939 /* Check if FCERR is set to 1. If 1,
4940 * clear it and try the whole sequence
4941 * a few more times else Done
4942 */
4943 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4944 ICH_FLASH_HSFSTS);
4945 if (hsfsts.hsf_status.flcerr)
4946 /* repeat for some time before giving up */
4947 continue;
4948 else if (!hsfsts.hsf_status.flcdone)
4949 return ret_val;
4950 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4951 }
4952
4953 return E1000_SUCCESS;
4954 }
4955
4956 /**
4957 * e1000_valid_led_default_ich8lan - Set the default LED settings
4958 * @hw: pointer to the HW structure
4959 * @data: Pointer to the LED settings
4960 *
4961 * Reads the LED default settings from the NVM to data. If the NVM LED
4962 * settings is all 0's or F's, set the LED default to a valid LED default
4963 * setting.
4964 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)4965 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4966 {
4967 s32 ret_val;
4968
4969 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4970
4971 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4972 if (ret_val) {
4973 DEBUGOUT("NVM Read Error\n");
4974 return ret_val;
4975 }
4976
4977 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4978 *data = ID_LED_DEFAULT_ICH8LAN;
4979
4980 return E1000_SUCCESS;
4981 }
4982
4983 /**
4984 * e1000_id_led_init_pchlan - store LED configurations
4985 * @hw: pointer to the HW structure
4986 *
4987 * PCH does not control LEDs via the LEDCTL register, rather it uses
4988 * the PHY LED configuration register.
4989 *
4990 * PCH also does not have an "always on" or "always off" mode which
4991 * complicates the ID feature. Instead of using the "on" mode to indicate
4992 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4993 * use "link_up" mode. The LEDs will still ID on request if there is no
4994 * link based on logic in e1000_led_[on|off]_pchlan().
4995 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)4996 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4997 {
4998 struct e1000_mac_info *mac = &hw->mac;
4999 s32 ret_val;
5000 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
5001 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
5002 u16 data, i, temp, shift;
5003
5004 DEBUGFUNC("e1000_id_led_init_pchlan");
5005
5006 /* Get default ID LED modes */
5007 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
5008 if (ret_val)
5009 return ret_val;
5010
5011 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
5012 mac->ledctl_mode1 = mac->ledctl_default;
5013 mac->ledctl_mode2 = mac->ledctl_default;
5014
5015 for (i = 0; i < 4; i++) {
5016 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
5017 shift = (i * 5);
5018 switch (temp) {
5019 case ID_LED_ON1_DEF2:
5020 case ID_LED_ON1_ON2:
5021 case ID_LED_ON1_OFF2:
5022 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
5023 mac->ledctl_mode1 |= (ledctl_on << shift);
5024 break;
5025 case ID_LED_OFF1_DEF2:
5026 case ID_LED_OFF1_ON2:
5027 case ID_LED_OFF1_OFF2:
5028 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
5029 mac->ledctl_mode1 |= (ledctl_off << shift);
5030 break;
5031 default:
5032 /* Do nothing */
5033 break;
5034 }
5035 switch (temp) {
5036 case ID_LED_DEF1_ON2:
5037 case ID_LED_ON1_ON2:
5038 case ID_LED_OFF1_ON2:
5039 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
5040 mac->ledctl_mode2 |= (ledctl_on << shift);
5041 break;
5042 case ID_LED_DEF1_OFF2:
5043 case ID_LED_ON1_OFF2:
5044 case ID_LED_OFF1_OFF2:
5045 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
5046 mac->ledctl_mode2 |= (ledctl_off << shift);
5047 break;
5048 default:
5049 /* Do nothing */
5050 break;
5051 }
5052 }
5053
5054 return E1000_SUCCESS;
5055 }
5056
5057 /**
5058 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
5059 * @hw: pointer to the HW structure
5060 *
5061 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
5062 * register, so the bus width is hard coded.
5063 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)5064 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
5065 {
5066 struct e1000_bus_info *bus = &hw->bus;
5067 s32 ret_val;
5068
5069 DEBUGFUNC("e1000_get_bus_info_ich8lan");
5070
5071 ret_val = e1000_get_bus_info_pcie_generic(hw);
5072
5073 /* ICH devices are "PCI Express"-ish. They have
5074 * a configuration space, but do not contain
5075 * PCI Express Capability registers, so bus width
5076 * must be hardcoded.
5077 */
5078 if (bus->width == e1000_bus_width_unknown)
5079 bus->width = e1000_bus_width_pcie_x1;
5080
5081 return ret_val;
5082 }
5083
5084 /**
5085 * e1000_reset_hw_ich8lan - Reset the hardware
5086 * @hw: pointer to the HW structure
5087 *
5088 * Does a full reset of the hardware which includes a reset of the PHY and
5089 * MAC.
5090 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)5091 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
5092 {
5093 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5094 u16 kum_cfg;
5095 u32 ctrl, reg;
5096 s32 ret_val;
5097 u16 pci_cfg;
5098
5099 DEBUGFUNC("e1000_reset_hw_ich8lan");
5100
5101 /* Prevent the PCI-E bus from sticking if there is no TLP connection
5102 * on the last TLP read/write transaction when MAC is reset.
5103 */
5104 ret_val = e1000_disable_pcie_master_generic(hw);
5105 if (ret_val)
5106 DEBUGOUT("PCI-E Master disable polling has failed.\n");
5107
5108 DEBUGOUT("Masking off all interrupts\n");
5109 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5110
5111 /* Disable the Transmit and Receive units. Then delay to allow
5112 * any pending transactions to complete before we hit the MAC
5113 * with the global reset.
5114 */
5115 E1000_WRITE_REG(hw, E1000_RCTL, 0);
5116 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
5117 E1000_WRITE_FLUSH(hw);
5118
5119 msec_delay(10);
5120
5121 /* Workaround for ICH8 bit corruption issue in FIFO memory */
5122 if (hw->mac.type == e1000_ich8lan) {
5123 /* Set Tx and Rx buffer allocation to 8k apiece. */
5124 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
5125 /* Set Packet Buffer Size to 16k. */
5126 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
5127 }
5128
5129 if (hw->mac.type == e1000_pchlan) {
5130 /* Save the NVM K1 bit setting*/
5131 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
5132 if (ret_val)
5133 return ret_val;
5134
5135 if (kum_cfg & E1000_NVM_K1_ENABLE)
5136 dev_spec->nvm_k1_enabled = true;
5137 else
5138 dev_spec->nvm_k1_enabled = false;
5139 }
5140
5141 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5142
5143 if (!hw->phy.ops.check_reset_block(hw)) {
5144 /* Full-chip reset requires MAC and PHY reset at the same
5145 * time to make sure the interface between MAC and the
5146 * external PHY is reset.
5147 */
5148 ctrl |= E1000_CTRL_PHY_RST;
5149
5150 /* Gate automatic PHY configuration by hardware on
5151 * non-managed 82579
5152 */
5153 if ((hw->mac.type == e1000_pch2lan) &&
5154 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5155 e1000_gate_hw_phy_config_ich8lan(hw, true);
5156 }
5157 ret_val = e1000_acquire_swflag_ich8lan(hw);
5158
5159 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
5160 * may occur during global reset and cause system hang.
5161 * Configuration space access creates the needed delay.
5162 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
5163 * insures configuration space read is done before global reset.
5164 */
5165 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
5166 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
5167 DEBUGOUT("Issuing a global reset to ich8lan\n");
5168 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5169 /* cannot issue a flush here because it hangs the hardware */
5170 msec_delay(20);
5171
5172 /* Configuration space access improve HW level time sync mechanism.
5173 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
5174 * value to insure configuration space read is done
5175 * before any access to mac register.
5176 */
5177 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
5178 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
5179
5180 /* Set Phy Config Counter to 50msec */
5181 if (hw->mac.type == e1000_pch2lan) {
5182 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5183 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5184 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5185 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5186 }
5187
5188
5189 if (ctrl & E1000_CTRL_PHY_RST) {
5190 ret_val = hw->phy.ops.get_cfg_done(hw);
5191 if (ret_val)
5192 return ret_val;
5193
5194 ret_val = e1000_post_phy_reset_ich8lan(hw);
5195 if (ret_val)
5196 return ret_val;
5197 }
5198
5199 /* For PCH, this write will make sure that any noise
5200 * will be detected as a CRC error and be dropped rather than show up
5201 * as a bad packet to the DMA engine.
5202 */
5203 if (hw->mac.type == e1000_pchlan)
5204 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5205
5206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5207 E1000_READ_REG(hw, E1000_ICR);
5208
5209 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5210 reg |= E1000_KABGTXD_BGSQLBIAS;
5211 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5212
5213 /* Prevent autonomous power gating after the hardware reset. */
5214 if (hw->mac.type >= e1000_pch_ptp &&
5215 hw->mac.type < e1000_82575) {
5216 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5217 reg &= ~E1000_CTRL_EXT_DPG_EN;
5218 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5219 }
5220
5221 return E1000_SUCCESS;
5222 }
5223
5224 /**
5225 * e1000_init_hw_ich8lan - Initialize the hardware
5226 * @hw: pointer to the HW structure
5227 *
5228 * Prepares the hardware for transmit and receive by doing the following:
5229 * - initialize hardware bits
5230 * - initialize LED identification
5231 * - setup receive address registers
5232 * - setup flow control
5233 * - setup transmit descriptors
5234 * - clear statistics
5235 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)5236 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5237 {
5238 struct e1000_mac_info *mac = &hw->mac;
5239 u32 ctrl_ext, txdctl, snoop;
5240 s32 ret_val;
5241 u16 i;
5242
5243 DEBUGFUNC("e1000_init_hw_ich8lan");
5244
5245 e1000_initialize_hw_bits_ich8lan(hw);
5246
5247 if (hw->mac.type >= e1000_pch_mtp &&
5248 hw->mac.type < e1000_82575) {
5249 ret_val = hw->phy.ops.acquire(hw);
5250 if (ret_val)
5251 return ret_val;
5252
5253 ret_val = e1000_reconfigure_k1_exit_timeout(hw);
5254 hw->phy.ops.release(hw);
5255 if (ret_val) {
5256 DEBUGOUT("Failed to reconfigure K1 exit timeout\n");
5257 return ret_val;
5258 }
5259 }
5260
5261 /* Initialize identification LED */
5262 ret_val = mac->ops.id_led_init(hw);
5263 /* An error is not fatal and we should not stop init due to this */
5264 if (ret_val)
5265 DEBUGOUT("Error initializing identification LED\n");
5266
5267 /* Setup the receive address. */
5268 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5269
5270 /* Zero out the Multicast HASH table */
5271 DEBUGOUT("Zeroing the MTA\n");
5272 for (i = 0; i < mac->mta_reg_count; i++)
5273 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5274
5275 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5276 * the ME. Disable wakeup by clearing the host wakeup bit.
5277 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5278 */
5279 if (hw->phy.type == e1000_phy_82578) {
5280 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5281 i &= ~BM_WUC_HOST_WU_BIT;
5282 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5283 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5284 if (ret_val)
5285 return ret_val;
5286 }
5287
5288 /* Setup link and flow control */
5289 ret_val = mac->ops.setup_link(hw);
5290
5291 /* Set the transmit descriptor write-back policy for both queues */
5292 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5293 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5294 E1000_TXDCTL_FULL_TX_DESC_WB);
5295 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5296 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5297 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5298 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5299 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5300 E1000_TXDCTL_FULL_TX_DESC_WB);
5301 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5302 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5303 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5304
5305 /* ICH8 has opposite polarity of no_snoop bits.
5306 * By default, we should use snoop behavior.
5307 */
5308 if (mac->type == e1000_ich8lan)
5309 snoop = PCIE_ICH8_SNOOP_ALL;
5310 else
5311 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5312 e1000_set_pcie_no_snoop_generic(hw, snoop);
5313
5314 /* ungate DMA clock to avoid packet loss */
5315 if (mac->type >= e1000_pch_tgp) {
5316 uint32_t fflt_dbg = E1000_READ_REG(hw, E1000_FFLT_DBG);
5317 fflt_dbg |= (1 << 12);
5318 E1000_WRITE_REG(hw, E1000_FFLT_DBG, fflt_dbg);
5319 }
5320
5321 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5322 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5323 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5324
5325 /* Clear all of the statistics registers (clear on read). It is
5326 * important that we do this after we have tried to establish link
5327 * because the symbol error count will increment wildly if there
5328 * is no link.
5329 */
5330 e1000_clear_hw_cntrs_ich8lan(hw);
5331
5332 return ret_val;
5333 }
5334
5335 /**
5336 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5337 * @hw: pointer to the HW structure
5338 *
5339 * Sets/Clears required hardware bits necessary for correctly setting up the
5340 * hardware for transmit and receive.
5341 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)5342 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5343 {
5344 u32 reg;
5345
5346 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5347
5348 /* Extended Device Control */
5349 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5350 reg |= (1 << 22);
5351 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5352 if (hw->mac.type >= e1000_pchlan)
5353 reg |= E1000_CTRL_EXT_PHYPDEN;
5354 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5355
5356 /* Transmit Descriptor Control 0 */
5357 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5358 reg |= (1 << 22);
5359 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5360
5361 /* Transmit Descriptor Control 1 */
5362 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5363 reg |= (1 << 22);
5364 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5365
5366 /* Transmit Arbitration Control 0 */
5367 reg = E1000_READ_REG(hw, E1000_TARC(0));
5368 if (hw->mac.type == e1000_ich8lan)
5369 reg |= (1 << 28) | (1 << 29);
5370 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5371 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5372
5373 /* Transmit Arbitration Control 1 */
5374 reg = E1000_READ_REG(hw, E1000_TARC(1));
5375 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5376 reg &= ~(1 << 28);
5377 else
5378 reg |= (1 << 28);
5379 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5380 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5381
5382 /* Device Status */
5383 if (hw->mac.type == e1000_ich8lan) {
5384 reg = E1000_READ_REG(hw, E1000_STATUS);
5385 reg &= ~(1U << 31);
5386 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5387 }
5388
5389 /* work-around descriptor data corruption issue during nfs v2 udp
5390 * traffic, just disable the nfs filtering capability
5391 */
5392 reg = E1000_READ_REG(hw, E1000_RFCTL);
5393 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5394
5395 /* Disable IPv6 extension header parsing because some malformed
5396 * IPv6 headers can hang the Rx.
5397 */
5398 if (hw->mac.type == e1000_ich8lan)
5399 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5400 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5401
5402 /* Enable ECC on Lynxpoint */
5403 if (hw->mac.type >= e1000_pch_lpt) {
5404 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5405 reg |= E1000_PBECCSTS_ECC_ENABLE;
5406 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5407
5408 reg = E1000_READ_REG(hw, E1000_CTRL);
5409 reg |= E1000_CTRL_MEHE;
5410 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5411 }
5412
5413 return;
5414 }
5415
5416 /**
5417 * e1000_setup_link_ich8lan - Setup flow control and link settings
5418 * @hw: pointer to the HW structure
5419 *
5420 * Determines which flow control settings to use, then configures flow
5421 * control. Calls the appropriate media-specific link configuration
5422 * function. Assuming the adapter has a valid link partner, a valid link
5423 * should be established. Assumes the hardware has previously been reset
5424 * and the transmitter and receiver are not enabled.
5425 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)5426 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5427 {
5428 s32 ret_val;
5429
5430 DEBUGFUNC("e1000_setup_link_ich8lan");
5431
5432 /* ICH parts do not have a word in the NVM to determine
5433 * the default flow control setting, so we explicitly
5434 * set it to full.
5435 */
5436 if (hw->fc.requested_mode == e1000_fc_default)
5437 hw->fc.requested_mode = e1000_fc_full;
5438
5439 /* Save off the requested flow control mode for use later. Depending
5440 * on the link partner's capabilities, we may or may not use this mode.
5441 */
5442 hw->fc.current_mode = hw->fc.requested_mode;
5443
5444 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5445 hw->fc.current_mode);
5446
5447 if (!hw->phy.ops.check_reset_block(hw)) {
5448 /* Continue to configure the copper link. */
5449 ret_val = hw->mac.ops.setup_physical_interface(hw);
5450 if (ret_val)
5451 return ret_val;
5452 }
5453
5454 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5455 if ((hw->phy.type == e1000_phy_82578) ||
5456 (hw->phy.type == e1000_phy_82579) ||
5457 (hw->phy.type == e1000_phy_i217) ||
5458 (hw->phy.type == e1000_phy_82577)) {
5459 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5460
5461 ret_val = hw->phy.ops.write_reg(hw,
5462 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5463 hw->fc.pause_time);
5464 if (ret_val)
5465 return ret_val;
5466 }
5467
5468 return e1000_set_fc_watermarks_generic(hw);
5469 }
5470
5471 /**
5472 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5473 * @hw: pointer to the HW structure
5474 *
5475 * Configures the kumeran interface to the PHY to wait the appropriate time
5476 * when polling the PHY, then call the generic setup_copper_link to finish
5477 * configuring the copper link.
5478 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)5479 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5480 {
5481 u32 ctrl;
5482 s32 ret_val;
5483 u16 reg_data;
5484
5485 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5486
5487 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5488 ctrl |= E1000_CTRL_SLU;
5489 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5490 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5491
5492 /* Set the mac to wait the maximum time between each iteration
5493 * and increase the max iterations when polling the phy;
5494 * this fixes erroneous timeouts at 10Mbps.
5495 */
5496 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5497 0xFFFF);
5498 if (ret_val)
5499 return ret_val;
5500 ret_val = e1000_read_kmrn_reg_generic(hw,
5501 E1000_KMRNCTRLSTA_INBAND_PARAM,
5502 ®_data);
5503 if (ret_val)
5504 return ret_val;
5505 reg_data |= 0x3F;
5506 ret_val = e1000_write_kmrn_reg_generic(hw,
5507 E1000_KMRNCTRLSTA_INBAND_PARAM,
5508 reg_data);
5509 if (ret_val)
5510 return ret_val;
5511
5512 switch (hw->phy.type) {
5513 case e1000_phy_igp_3:
5514 ret_val = e1000_copper_link_setup_igp(hw);
5515 if (ret_val)
5516 return ret_val;
5517 break;
5518 case e1000_phy_bm:
5519 case e1000_phy_82578:
5520 ret_val = e1000_copper_link_setup_m88(hw);
5521 if (ret_val)
5522 return ret_val;
5523 break;
5524 case e1000_phy_82577:
5525 case e1000_phy_82579:
5526 ret_val = e1000_copper_link_setup_82577(hw);
5527 if (ret_val)
5528 return ret_val;
5529 break;
5530 case e1000_phy_ife:
5531 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5532 ®_data);
5533 if (ret_val)
5534 return ret_val;
5535
5536 reg_data &= ~IFE_PMC_AUTO_MDIX;
5537
5538 switch (hw->phy.mdix) {
5539 case 1:
5540 reg_data &= ~IFE_PMC_FORCE_MDIX;
5541 break;
5542 case 2:
5543 reg_data |= IFE_PMC_FORCE_MDIX;
5544 break;
5545 case 0:
5546 default:
5547 reg_data |= IFE_PMC_AUTO_MDIX;
5548 break;
5549 }
5550 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5551 reg_data);
5552 if (ret_val)
5553 return ret_val;
5554 break;
5555 default:
5556 break;
5557 }
5558
5559 return e1000_setup_copper_link_generic(hw);
5560 }
5561
5562 /**
5563 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5564 * @hw: pointer to the HW structure
5565 *
5566 * Calls the PHY specific link setup function and then calls the
5567 * generic setup_copper_link to finish configuring the link for
5568 * Lynxpoint PCH devices
5569 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)5570 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5571 {
5572 u32 ctrl;
5573 s32 ret_val;
5574
5575 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5576
5577 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5578 ctrl |= E1000_CTRL_SLU;
5579 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5580 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5581
5582 ret_val = e1000_copper_link_setup_82577(hw);
5583 if (ret_val)
5584 return ret_val;
5585
5586 return e1000_setup_copper_link_generic(hw);
5587 }
5588
5589 /**
5590 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5591 * @hw: pointer to the HW structure
5592 * @speed: pointer to store current link speed
5593 * @duplex: pointer to store the current link duplex
5594 *
5595 * Calls the generic get_speed_and_duplex to retrieve the current link
5596 * information and then calls the Kumeran lock loss workaround for links at
5597 * gigabit speeds.
5598 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)5599 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5600 u16 *duplex)
5601 {
5602 s32 ret_val;
5603
5604 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5605
5606 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5607 if (ret_val)
5608 return ret_val;
5609
5610 if ((hw->mac.type == e1000_ich8lan) &&
5611 (hw->phy.type == e1000_phy_igp_3) &&
5612 (*speed == SPEED_1000)) {
5613 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5614 }
5615
5616 return ret_val;
5617 }
5618
5619 /**
5620 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5621 * @hw: pointer to the HW structure
5622 *
5623 * Work-around for 82566 Kumeran PCS lock loss:
5624 * On link status change (i.e. PCI reset, speed change) and link is up and
5625 * speed is gigabit-
5626 * 0) if workaround is optionally disabled do nothing
5627 * 1) wait 1ms for Kumeran link to come up
5628 * 2) check Kumeran Diagnostic register PCS lock loss bit
5629 * 3) if not set the link is locked (all is good), otherwise...
5630 * 4) reset the PHY
5631 * 5) repeat up to 10 times
5632 * Note: this is only called for IGP3 copper when speed is 1gb.
5633 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)5634 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5635 {
5636 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5637 u32 phy_ctrl;
5638 s32 ret_val;
5639 u16 i, data;
5640 bool link;
5641
5642 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5643
5644 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5645 return E1000_SUCCESS;
5646
5647 /* Make sure link is up before proceeding. If not just return.
5648 * Attempting this while link is negotiating fouled up link
5649 * stability
5650 */
5651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5652 if (!link)
5653 return E1000_SUCCESS;
5654
5655 for (i = 0; i < 10; i++) {
5656 /* read once to clear */
5657 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5658 if (ret_val)
5659 return ret_val;
5660 /* and again to get new status */
5661 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5662 if (ret_val)
5663 return ret_val;
5664
5665 /* check for PCS lock */
5666 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5667 return E1000_SUCCESS;
5668
5669 /* Issue PHY reset */
5670 hw->phy.ops.reset(hw);
5671 msec_delay_irq(5);
5672 }
5673 /* Disable GigE link negotiation */
5674 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5675 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5676 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5677 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5678
5679 /* Call gig speed drop workaround on Gig disable before accessing
5680 * any PHY registers
5681 */
5682 e1000_gig_downshift_workaround_ich8lan(hw);
5683
5684 /* unable to acquire PCS lock */
5685 return -E1000_ERR_PHY;
5686 }
5687
5688 /**
5689 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5690 * @hw: pointer to the HW structure
5691 * @state: boolean value used to set the current Kumeran workaround state
5692 *
5693 * If ICH8, set the current Kumeran workaround state (enabled - true
5694 * /disabled - false).
5695 **/
e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)5696 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5697 bool state)
5698 {
5699 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5700
5701 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5702
5703 if (hw->mac.type != e1000_ich8lan) {
5704 DEBUGOUT("Workaround applies to ICH8 only.\n");
5705 return;
5706 }
5707
5708 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5709
5710 return;
5711 }
5712
5713 /**
5714 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5715 * @hw: pointer to the HW structure
5716 *
5717 * Workaround for 82566 power-down on D3 entry:
5718 * 1) disable gigabit link
5719 * 2) write VR power-down enable
5720 * 3) read it back
5721 * Continue if successful, else issue LCD reset and repeat
5722 **/
e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)5723 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5724 {
5725 u32 reg;
5726 u16 data;
5727 u8 retry = 0;
5728
5729 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5730
5731 if (hw->phy.type != e1000_phy_igp_3)
5732 return;
5733
5734 /* Try the workaround twice (if needed) */
5735 do {
5736 /* Disable link */
5737 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5738 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5739 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5740 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5741
5742 /* Call gig speed drop workaround on Gig disable before
5743 * accessing any PHY registers
5744 */
5745 if (hw->mac.type == e1000_ich8lan)
5746 e1000_gig_downshift_workaround_ich8lan(hw);
5747
5748 /* Write VR power-down enable */
5749 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5750 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5751 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5752 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5753
5754 /* Read it back and test */
5755 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5756 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5757 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5758 break;
5759
5760 /* Issue PHY reset and repeat at most one more time */
5761 reg = E1000_READ_REG(hw, E1000_CTRL);
5762 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5763 retry++;
5764 } while (retry);
5765 }
5766
5767 /**
5768 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5769 * @hw: pointer to the HW structure
5770 *
5771 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5772 * LPLU, Gig disable, MDIC PHY reset):
5773 * 1) Set Kumeran Near-end loopback
5774 * 2) Clear Kumeran Near-end loopback
5775 * Should only be called for ICH8[m] devices with any 1G Phy.
5776 **/
e1000_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)5777 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5778 {
5779 s32 ret_val;
5780 u16 reg_data = 0;
5781
5782 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5783
5784 if ((hw->mac.type != e1000_ich8lan) ||
5785 (hw->phy.type == e1000_phy_ife))
5786 return;
5787
5788 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5789 ®_data);
5790 if (ret_val)
5791 return;
5792 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5793 ret_val = e1000_write_kmrn_reg_generic(hw,
5794 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5795 reg_data);
5796 if (ret_val)
5797 return;
5798 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5799 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5800 reg_data);
5801 }
5802
5803 /**
5804 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5805 * @hw: pointer to the HW structure
5806 *
5807 * During S0 to Sx transition, it is possible the link remains at gig
5808 * instead of negotiating to a lower speed. Before going to Sx, set
5809 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5810 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5811 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5812 * needs to be written.
5813 * Parts that support (and are linked to a partner which support) EEE in
5814 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5815 * than 10Mbps w/o EEE.
5816 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)5817 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5818 {
5819 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5820 u32 phy_ctrl;
5821 s32 ret_val;
5822
5823 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5824
5825 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5826 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5827
5828 if (hw->phy.type == e1000_phy_i217) {
5829 u16 phy_reg, device_id = hw->device_id;
5830
5831 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5832 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5833 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5834 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5835 (hw->mac.type >= e1000_pch_spt)) {
5836 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5837
5838 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5839 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5840 }
5841
5842 ret_val = hw->phy.ops.acquire(hw);
5843 if (ret_val)
5844 goto out;
5845
5846 if (!dev_spec->eee_disable) {
5847 u16 eee_advert;
5848
5849 ret_val =
5850 e1000_read_emi_reg_locked(hw,
5851 I217_EEE_ADVERTISEMENT,
5852 &eee_advert);
5853 if (ret_val)
5854 goto release;
5855
5856 /* Disable LPLU if both link partners support 100BaseT
5857 * EEE and 100Full is advertised on both ends of the
5858 * link, and enable Auto Enable LPI since there will
5859 * be no driver to enable LPI while in Sx.
5860 */
5861 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5862 (dev_spec->eee_lp_ability &
5863 I82579_EEE_100_SUPPORTED) &&
5864 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5865 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5866 E1000_PHY_CTRL_NOND0A_LPLU);
5867
5868 /* Set Auto Enable LPI after link up */
5869 hw->phy.ops.read_reg_locked(hw,
5870 I217_LPI_GPIO_CTRL,
5871 &phy_reg);
5872 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5873 hw->phy.ops.write_reg_locked(hw,
5874 I217_LPI_GPIO_CTRL,
5875 phy_reg);
5876 }
5877 }
5878
5879 /* For i217 Intel Rapid Start Technology support,
5880 * when the system is going into Sx and no manageability engine
5881 * is present, the driver must configure proxy to reset only on
5882 * power good. LPI (Low Power Idle) state must also reset only
5883 * on power good, as well as the MTA (Multicast table array).
5884 * The SMBus release must also be disabled on LCD reset.
5885 */
5886 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5887 E1000_ICH_FWSM_FW_VALID)) {
5888 /* Enable proxy to reset only on power good. */
5889 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5890 &phy_reg);
5891 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5892 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5893 phy_reg);
5894
5895 /* Set bit enable LPI (EEE) to reset only on
5896 * power good.
5897 */
5898 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5899 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5900 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5901
5902 /* Disable the SMB release on LCD reset. */
5903 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5904 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5905 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5906 }
5907
5908 /* Enable MTA to reset for Intel Rapid Start Technology
5909 * Support
5910 */
5911 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5912 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5913 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5914
5915 release:
5916 hw->phy.ops.release(hw);
5917 }
5918 out:
5919 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5920
5921 if (hw->mac.type == e1000_ich8lan)
5922 e1000_gig_downshift_workaround_ich8lan(hw);
5923
5924 if (hw->mac.type >= e1000_pchlan) {
5925 e1000_oem_bits_config_ich8lan(hw, false);
5926
5927 /* Reset PHY to activate OEM bits on 82577/8 */
5928 if (hw->mac.type == e1000_pchlan)
5929 e1000_phy_hw_reset_generic(hw);
5930
5931 ret_val = hw->phy.ops.acquire(hw);
5932 if (ret_val)
5933 return;
5934 e1000_write_smbus_addr(hw);
5935 hw->phy.ops.release(hw);
5936 }
5937
5938 return;
5939 }
5940
5941 /**
5942 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5943 * @hw: pointer to the HW structure
5944 *
5945 * During Sx to S0 transitions on non-managed devices or managed devices
5946 * on which PHY resets are not blocked, if the PHY registers cannot be
5947 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5948 * the PHY.
5949 * On i217, setup Intel Rapid Start Technology.
5950 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)5951 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5952 {
5953 s32 ret_val;
5954
5955 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5956 if (hw->mac.type < e1000_pch2lan)
5957 return E1000_SUCCESS;
5958
5959 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5960 if (ret_val) {
5961 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5962 return ret_val;
5963 }
5964
5965 /* For i217 Intel Rapid Start Technology support when the system
5966 * is transitioning from Sx and no manageability engine is present
5967 * configure SMBus to restore on reset, disable proxy, and enable
5968 * the reset on MTA (Multicast table array).
5969 */
5970 if (hw->phy.type == e1000_phy_i217) {
5971 u16 phy_reg;
5972
5973 ret_val = hw->phy.ops.acquire(hw);
5974 if (ret_val) {
5975 DEBUGOUT("Failed to setup iRST\n");
5976 return ret_val;
5977 }
5978
5979 /* Clear Auto Enable LPI after link up */
5980 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5981 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5982 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5983
5984 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5985 E1000_ICH_FWSM_FW_VALID)) {
5986 /* Restore clear on SMB if no manageability engine
5987 * is present
5988 */
5989 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5990 &phy_reg);
5991 if (ret_val)
5992 goto release;
5993 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5994 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5995
5996 /* Disable Proxy */
5997 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5998 }
5999 /* Enable reset on MTA */
6000 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
6001 &phy_reg);
6002 if (ret_val)
6003 goto release;
6004 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
6005 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
6006 release:
6007 if (ret_val)
6008 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
6009 hw->phy.ops.release(hw);
6010 return ret_val;
6011 }
6012 return E1000_SUCCESS;
6013 }
6014
6015 /**
6016 * e1000_cleanup_led_ich8lan - Restore the default LED operation
6017 * @hw: pointer to the HW structure
6018 *
6019 * Return the LED back to the default configuration.
6020 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)6021 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
6022 {
6023 DEBUGFUNC("e1000_cleanup_led_ich8lan");
6024
6025 if (hw->phy.type == e1000_phy_ife)
6026 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6027 0);
6028
6029 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
6030 return E1000_SUCCESS;
6031 }
6032
6033 /**
6034 * e1000_led_on_ich8lan - Turn LEDs on
6035 * @hw: pointer to the HW structure
6036 *
6037 * Turn on the LEDs.
6038 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)6039 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
6040 {
6041 DEBUGFUNC("e1000_led_on_ich8lan");
6042
6043 if (hw->phy.type == e1000_phy_ife)
6044 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6045 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6046
6047 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
6048 return E1000_SUCCESS;
6049 }
6050
6051 /**
6052 * e1000_led_off_ich8lan - Turn LEDs off
6053 * @hw: pointer to the HW structure
6054 *
6055 * Turn off the LEDs.
6056 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)6057 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
6058 {
6059 DEBUGFUNC("e1000_led_off_ich8lan");
6060
6061 if (hw->phy.type == e1000_phy_ife)
6062 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6063 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6064
6065 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
6066 return E1000_SUCCESS;
6067 }
6068
6069 /**
6070 * e1000_setup_led_pchlan - Configures SW controllable LED
6071 * @hw: pointer to the HW structure
6072 *
6073 * This prepares the SW controllable LED for use.
6074 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)6075 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
6076 {
6077 DEBUGFUNC("e1000_setup_led_pchlan");
6078
6079 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
6080 (u16)hw->mac.ledctl_mode1);
6081 }
6082
6083 /**
6084 * e1000_cleanup_led_pchlan - Restore the default LED operation
6085 * @hw: pointer to the HW structure
6086 *
6087 * Return the LED back to the default configuration.
6088 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)6089 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
6090 {
6091 DEBUGFUNC("e1000_cleanup_led_pchlan");
6092
6093 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
6094 (u16)hw->mac.ledctl_default);
6095 }
6096
6097 /**
6098 * e1000_led_on_pchlan - Turn LEDs on
6099 * @hw: pointer to the HW structure
6100 *
6101 * Turn on the LEDs.
6102 **/
e1000_led_on_pchlan(struct e1000_hw * hw)6103 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
6104 {
6105 u16 data = (u16)hw->mac.ledctl_mode2;
6106 u32 i, led;
6107
6108 DEBUGFUNC("e1000_led_on_pchlan");
6109
6110 /* If no link, then turn LED on by setting the invert bit
6111 * for each LED that's mode is "link_up" in ledctl_mode2.
6112 */
6113 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
6114 for (i = 0; i < 3; i++) {
6115 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
6116 if ((led & E1000_PHY_LED0_MODE_MASK) !=
6117 E1000_LEDCTL_MODE_LINK_UP)
6118 continue;
6119 if (led & E1000_PHY_LED0_IVRT)
6120 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
6121 else
6122 data |= (E1000_PHY_LED0_IVRT << (i * 5));
6123 }
6124 }
6125
6126 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
6127 }
6128
6129 /**
6130 * e1000_led_off_pchlan - Turn LEDs off
6131 * @hw: pointer to the HW structure
6132 *
6133 * Turn off the LEDs.
6134 **/
e1000_led_off_pchlan(struct e1000_hw * hw)6135 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
6136 {
6137 u16 data = (u16)hw->mac.ledctl_mode1;
6138 u32 i, led;
6139
6140 DEBUGFUNC("e1000_led_off_pchlan");
6141
6142 /* If no link, then turn LED off by clearing the invert bit
6143 * for each LED that's mode is "link_up" in ledctl_mode1.
6144 */
6145 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
6146 for (i = 0; i < 3; i++) {
6147 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
6148 if ((led & E1000_PHY_LED0_MODE_MASK) !=
6149 E1000_LEDCTL_MODE_LINK_UP)
6150 continue;
6151 if (led & E1000_PHY_LED0_IVRT)
6152 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
6153 else
6154 data |= (E1000_PHY_LED0_IVRT << (i * 5));
6155 }
6156 }
6157
6158 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
6159 }
6160
6161 /**
6162 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
6163 * @hw: pointer to the HW structure
6164 *
6165 * Read appropriate register for the config done bit for completion status
6166 * and configure the PHY through s/w for EEPROM-less parts.
6167 *
6168 * NOTE: some silicon which is EEPROM-less will fail trying to read the
6169 * config done bit, so only an error is logged and continues. If we were
6170 * to return with error, EEPROM-less silicon would not be able to be reset
6171 * or change link.
6172 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)6173 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
6174 {
6175 s32 ret_val = E1000_SUCCESS;
6176 u32 bank = 0;
6177 u32 status;
6178
6179 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
6180
6181 e1000_get_cfg_done_generic(hw);
6182
6183 /* Wait for indication from h/w that it has completed basic config */
6184 if (hw->mac.type >= e1000_ich10lan) {
6185 e1000_lan_init_done_ich8lan(hw);
6186 } else {
6187 ret_val = e1000_get_auto_rd_done_generic(hw);
6188 if (ret_val) {
6189 /* When auto config read does not complete, do not
6190 * return with an error. This can happen in situations
6191 * where there is no eeprom and prevents getting link.
6192 */
6193 DEBUGOUT("Auto Read Done did not complete\n");
6194 ret_val = E1000_SUCCESS;
6195 }
6196 }
6197
6198 /* Clear PHY Reset Asserted bit */
6199 status = E1000_READ_REG(hw, E1000_STATUS);
6200 if (status & E1000_STATUS_PHYRA)
6201 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6202 else
6203 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6204
6205 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6206 if (hw->mac.type <= e1000_ich9lan) {
6207 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6208 (hw->phy.type == e1000_phy_igp_3)) {
6209 e1000_phy_init_script_igp3(hw);
6210 }
6211 } else {
6212 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6213 /* Maybe we should do a basic PHY config */
6214 DEBUGOUT("EEPROM not present\n");
6215 ret_val = -E1000_ERR_CONFIG;
6216 }
6217 }
6218
6219 return ret_val;
6220 }
6221
6222 /**
6223 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6224 * @hw: pointer to the HW structure
6225 *
6226 * In the case of a PHY power down to save power, or to turn off link during a
6227 * driver unload, or wake on lan is not enabled, remove the link.
6228 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)6229 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6230 {
6231 /* If the management interface is not enabled, then power down */
6232 if (!(hw->mac.ops.check_mng_mode(hw) ||
6233 hw->phy.ops.check_reset_block(hw)))
6234 e1000_power_down_phy_copper(hw);
6235
6236 return;
6237 }
6238
6239 /**
6240 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6241 * @hw: pointer to the HW structure
6242 *
6243 * Clears hardware counters specific to the silicon family and calls
6244 * clear_hw_cntrs_generic to clear all general purpose counters.
6245 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)6246 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6247 {
6248 u16 phy_data;
6249 s32 ret_val;
6250
6251 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6252
6253 e1000_clear_hw_cntrs_base_generic(hw);
6254
6255 E1000_READ_REG(hw, E1000_ALGNERRC);
6256 E1000_READ_REG(hw, E1000_RXERRC);
6257 E1000_READ_REG(hw, E1000_TNCRS);
6258 E1000_READ_REG(hw, E1000_CEXTERR);
6259 E1000_READ_REG(hw, E1000_TSCTC);
6260 E1000_READ_REG(hw, E1000_TSCTFC);
6261
6262 E1000_READ_REG(hw, E1000_MGTPRC);
6263 E1000_READ_REG(hw, E1000_MGTPDC);
6264 E1000_READ_REG(hw, E1000_MGTPTC);
6265
6266 E1000_READ_REG(hw, E1000_IAC);
6267 E1000_READ_REG(hw, E1000_ICRXOC);
6268
6269 /* Clear PHY statistics registers */
6270 if ((hw->phy.type == e1000_phy_82578) ||
6271 (hw->phy.type == e1000_phy_82579) ||
6272 (hw->phy.type == e1000_phy_i217) ||
6273 (hw->phy.type == e1000_phy_82577)) {
6274 ret_val = hw->phy.ops.acquire(hw);
6275 if (ret_val)
6276 return;
6277 ret_val = hw->phy.ops.set_page(hw,
6278 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6279 if (ret_val)
6280 goto release;
6281 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6282 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6283 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6284 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6285 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6286 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6287 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6288 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6289 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6290 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6291 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6292 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6293 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6294 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6295 release:
6296 hw->phy.ops.release(hw);
6297 }
6298 }
6299
6300 /**
6301 * e1000_configure_k0s_lpt - Configure K0s power state
6302 * @hw: pointer to the HW structure
6303 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6304 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6305 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6306 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6307 *
6308 * Configure the K1 power state based on the provided parameter.
6309 * Assumes semaphore already acquired.
6310 *
6311 * Success returns 0, Failure returns:
6312 * -E1000_ERR_PHY (-2) in case of access error
6313 * -E1000_ERR_PARAM (-4) in case of parameters error
6314 **/
e1000_configure_k0s_lpt(struct e1000_hw * hw,u8 entry_latency,u8 min_time)6315 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6316 {
6317 s32 ret_val;
6318 u16 kmrn_reg = 0;
6319
6320 DEBUGFUNC("e1000_configure_k0s_lpt");
6321
6322 if (entry_latency > 3 || min_time > 4)
6323 return -E1000_ERR_PARAM;
6324
6325 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6326 &kmrn_reg);
6327 if (ret_val)
6328 return ret_val;
6329
6330 /* for now don't touch the latency */
6331 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6332 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6333
6334 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6335 kmrn_reg);
6336 if (ret_val)
6337 return ret_val;
6338
6339 return E1000_SUCCESS;
6340 }
6341