1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Texas Instruments ADS1018 ADC driver
4 *
5 * Copyright (C) 2025 Kurt Borja <kuurtb@gmail.com>
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/dev_printk.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/math.h>
15 #include <linux/module.h>
16 #include <linux/spi/spi.h>
17 #include <linux/types.h>
18 #include <linux/units.h>
19
20 #include <asm/byteorder.h>
21
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27
28 #define ADS1018_CFG_OS_TRIG BIT(15)
29 #define ADS1018_CFG_TS_MODE_EN BIT(4)
30 #define ADS1018_CFG_PULL_UP BIT(3)
31 #define ADS1018_CFG_NOP BIT(1)
32 #define ADS1018_CFG_VALID (ADS1018_CFG_PULL_UP | ADS1018_CFG_NOP)
33
34 #define ADS1018_CFG_MUX_MASK GENMASK(14, 12)
35
36 #define ADS1018_CFG_PGA_MASK GENMASK(11, 9)
37 #define ADS1018_PGA_DEFAULT 2
38
39 #define ADS1018_CFG_MODE_MASK BIT(8)
40 #define ADS1018_MODE_CONTINUOUS 0
41 #define ADS1018_MODE_ONESHOT 1
42
43 #define ADS1018_CFG_DRATE_MASK GENMASK(7, 5)
44 #define ADS1018_DRATE_DEFAULT 4
45
46 #define ADS1018_NUM_PGA_MODES 6
47 #define ADS1018_CHANNELS_MAX 10
48
49 struct ads1018_chan_data {
50 u8 pga_mode;
51 u8 data_rate_mode;
52 };
53
54 struct ads1018_chip_info {
55 const char *name;
56 const struct iio_chan_spec *channels;
57 unsigned long num_channels;
58
59 /* IIO_VAL_INT */
60 const u32 *data_rate_mode_to_hz;
61 unsigned long num_data_rate_mode_to_hz;
62
63 /*
64 * Let `res` be the chip's resolution and `fsr` (millivolts) be the
65 * full-scale range corresponding to the PGA mode given by the array
66 * index. Then, the gain is calculated using the following formula:
67 *
68 * gain = |fsr| / 2^(res - 1)
69 *
70 * This value then has to be represented in IIO_VAL_INT_PLUS_NANO
71 * format. For example if:
72 *
73 * gain = 6144 / 2^(16 - 1) = 0.1875
74 *
75 * ...then the formatted value is:
76 *
77 * { 0, 187500000 }
78 */
79 const u32 pga_mode_to_gain[ADS1018_NUM_PGA_MODES][2];
80
81 /* IIO_VAL_INT_PLUS_MICRO */
82 const u32 temp_scale[2];
83 };
84
85 struct ads1018 {
86 struct spi_device *spi;
87 struct iio_trigger *indio_trig;
88
89 struct gpio_desc *drdy_gpiod;
90 int drdy_irq;
91
92 struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX];
93 const struct ads1018_chip_info *chip_info;
94
95 struct spi_message msg_read;
96 struct spi_transfer xfer;
97 __be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
98 __be16 rx_buf[2];
99 };
100
101 #define ADS1018_VOLT_DIFF_CHAN(_index, _chan, _chan2, _realbits) { \
102 .type = IIO_VOLTAGE, \
103 .channel = _chan, \
104 .channel2 = _chan2, \
105 .scan_index = _index, \
106 .scan_type = { \
107 .sign = 's', \
108 .realbits = _realbits, \
109 .storagebits = 16, \
110 .shift = 16 - _realbits, \
111 .endianness = IIO_BE, \
112 }, \
113 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
114 BIT(IIO_CHAN_INFO_SCALE) | \
115 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
116 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
117 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
118 .indexed = true, \
119 .differential = true, \
120 }
121
122 #define ADS1018_VOLT_CHAN(_index, _chan, _realbits) { \
123 .type = IIO_VOLTAGE, \
124 .channel = _chan, \
125 .scan_index = _index, \
126 .scan_type = { \
127 .sign = 's', \
128 .realbits = _realbits, \
129 .storagebits = 16, \
130 .shift = 16 - _realbits, \
131 .endianness = IIO_BE, \
132 }, \
133 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
134 BIT(IIO_CHAN_INFO_SCALE) | \
135 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
136 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
137 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
138 .indexed = true, \
139 }
140
141 #define ADS1018_TEMP_CHAN(_index, _realbits) { \
142 .type = IIO_TEMP, \
143 .scan_index = _index, \
144 .scan_type = { \
145 .sign = 's', \
146 .realbits = _realbits, \
147 .storagebits = 16, \
148 .shift = 16 - _realbits, \
149 .endianness = IIO_BE, \
150 }, \
151 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
152 BIT(IIO_CHAN_INFO_SCALE) | \
153 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
154 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
155 }
156
157 static const struct iio_chan_spec ads1118_iio_channels[] = {
158 ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16),
159 ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16),
160 ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16),
161 ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 16),
162 ADS1018_VOLT_CHAN(4, 0, 16),
163 ADS1018_VOLT_CHAN(5, 1, 16),
164 ADS1018_VOLT_CHAN(6, 2, 16),
165 ADS1018_VOLT_CHAN(7, 3, 16),
166 ADS1018_TEMP_CHAN(8, 14),
167 IIO_CHAN_SOFT_TIMESTAMP(9),
168 };
169
170 static const struct iio_chan_spec ads1018_iio_channels[] = {
171 ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 12),
172 ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 12),
173 ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 12),
174 ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 12),
175 ADS1018_VOLT_CHAN(4, 0, 12),
176 ADS1018_VOLT_CHAN(5, 1, 12),
177 ADS1018_VOLT_CHAN(6, 2, 12),
178 ADS1018_VOLT_CHAN(7, 3, 12),
179 ADS1018_TEMP_CHAN(8, 12),
180 IIO_CHAN_SOFT_TIMESTAMP(9),
181 };
182
183 /**
184 * ads1018_calc_delay - Calculates a suitable delay for a single-shot reading
185 * @hz: Sampling frequency
186 *
187 * Calculates an appropriate delay for a single shot reading given a sampling
188 * frequency.
189 *
190 * Return: Delay in microseconds (Always greater than 0).
191 */
ads1018_calc_delay(unsigned int hz)192 static u32 ads1018_calc_delay(unsigned int hz)
193 {
194 /*
195 * Calculate the worst-case sampling rate by subtracting 10% error
196 * specified in the datasheet...
197 */
198 hz -= DIV_ROUND_UP(hz, 10);
199
200 /* ...Then calculate time per sample in microseconds. */
201 return DIV_ROUND_UP(HZ_PER_MHZ, hz);
202 }
203
204 /**
205 * ads1018_spi_read_exclusive - Reads a conversion value from the device
206 * @ads1018: Device data
207 * @cnv: ADC Conversion value (optional)
208 * @hold_cs: Keep CS line asserted after the SPI transfer
209 *
210 * Reads the most recent ADC conversion value, without updating the
211 * device's configuration.
212 *
213 * Context: Expects SPI bus *exclusive* use.
214 *
215 * Return: 0 on success, negative errno on error.
216 */
ads1018_spi_read_exclusive(struct ads1018 * ads1018,__be16 * cnv,bool hold_cs)217 static int ads1018_spi_read_exclusive(struct ads1018 *ads1018, __be16 *cnv,
218 bool hold_cs)
219 {
220 int ret;
221
222 ads1018->xfer.cs_change = hold_cs;
223
224 ret = spi_sync_locked(ads1018->spi, &ads1018->msg_read);
225 if (ret)
226 return ret;
227
228 if (cnv)
229 *cnv = ads1018->rx_buf[0];
230
231 return 0;
232 }
233
234 /**
235 * ads1018_single_shot - Performs a one-shot reading sequence
236 * @ads1018: Device data
237 * @chan: Channel specification
238 * @cnv: Conversion value
239 *
240 * Writes a new configuration, waits an appropriate delay, then reads the most
241 * recent conversion.
242 *
243 * Context: Expects iio_device_claim_direct() is held.
244 *
245 * Return: 0 on success, negative errno on error.
246 */
ads1018_single_shot(struct ads1018 * ads1018,struct iio_chan_spec const * chan,u16 * cnv)247 static int ads1018_single_shot(struct ads1018 *ads1018,
248 struct iio_chan_spec const *chan, u16 *cnv)
249 {
250 u8 max_drate_mode = ads1018->chip_info->num_data_rate_mode_to_hz - 1;
251 u32 drate = ads1018->chip_info->data_rate_mode_to_hz[max_drate_mode];
252 u8 pga_mode = ads1018->chan_data[chan->scan_index].pga_mode;
253 struct spi_transfer xfer[2] = {
254 {
255 .tx_buf = ads1018->tx_buf,
256 .len = sizeof(ads1018->tx_buf[0]),
257 .delay = {
258 .value = ads1018_calc_delay(drate),
259 .unit = SPI_DELAY_UNIT_USECS,
260 },
261 .cs_change = 1, /* 16-bit mode requires CS de-assert */
262 },
263 {
264 .rx_buf = ads1018->rx_buf,
265 .len = sizeof(ads1018->rx_buf[0]),
266 },
267 };
268 u16 cfg;
269 int ret;
270
271 cfg = ADS1018_CFG_VALID | ADS1018_CFG_OS_TRIG;
272 cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, chan->scan_index);
273 cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga_mode);
274 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
275 cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, max_drate_mode);
276
277 if (chan->type == IIO_TEMP)
278 cfg |= ADS1018_CFG_TS_MODE_EN;
279
280 ads1018->tx_buf[0] = cpu_to_be16(cfg);
281 ret = spi_sync_transfer(ads1018->spi, xfer, ARRAY_SIZE(xfer));
282 if (ret)
283 return ret;
284
285 *cnv = be16_to_cpu(ads1018->rx_buf[0]);
286
287 return 0;
288 }
289
290 static int
ads1018_read_raw_direct_mode(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)291 ads1018_read_raw_direct_mode(struct iio_dev *indio_dev,
292 struct iio_chan_spec const *chan, int *val, int *val2,
293 long mask)
294 {
295 struct ads1018 *ads1018 = iio_priv(indio_dev);
296 const struct ads1018_chip_info *chip_info = ads1018->chip_info;
297 u8 addr = chan->scan_index;
298 u8 pga_mode, drate_mode;
299 u16 cnv;
300 int ret;
301
302 switch (mask) {
303 case IIO_CHAN_INFO_RAW:
304 ret = ads1018_single_shot(ads1018, chan, &cnv);
305 if (ret)
306 return ret;
307
308 cnv >>= chan->scan_type.shift;
309 *val = sign_extend32(cnv, chan->scan_type.realbits - 1);
310
311 return IIO_VAL_INT;
312
313 case IIO_CHAN_INFO_SCALE:
314 switch (chan->type) {
315 case IIO_VOLTAGE:
316 pga_mode = ads1018->chan_data[addr].pga_mode;
317 *val = chip_info->pga_mode_to_gain[pga_mode][0];
318 *val2 = chip_info->pga_mode_to_gain[pga_mode][1];
319 return IIO_VAL_INT_PLUS_NANO;
320
321 case IIO_TEMP:
322 *val = chip_info->temp_scale[0];
323 *val2 = chip_info->temp_scale[1];
324 return IIO_VAL_INT_PLUS_MICRO;
325
326 default:
327 return -EOPNOTSUPP;
328 }
329
330 case IIO_CHAN_INFO_SAMP_FREQ:
331 drate_mode = ads1018->chan_data[addr].data_rate_mode;
332 *val = chip_info->data_rate_mode_to_hz[drate_mode];
333 return IIO_VAL_INT;
334
335 default:
336 return -EOPNOTSUPP;
337 }
338 }
339
340 static int
ads1018_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)341 ads1018_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
342 int *val, int *val2, long mask)
343 {
344 int ret;
345
346 if (!iio_device_claim_direct(indio_dev))
347 return -EBUSY;
348 ret = ads1018_read_raw_direct_mode(indio_dev, chan, val, val2, mask);
349 iio_device_release_direct(indio_dev);
350
351 return ret;
352 }
353
354 static int
ads1018_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)355 ads1018_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
356 const int **vals, int *type, int *length, long mask)
357 {
358 struct ads1018 *ads1018 = iio_priv(indio_dev);
359
360 switch (mask) {
361 case IIO_CHAN_INFO_SCALE:
362 *type = IIO_VAL_INT_PLUS_NANO;
363 *vals = (const int *)ads1018->chip_info->pga_mode_to_gain;
364 *length = ADS1018_NUM_PGA_MODES * 2;
365 return IIO_AVAIL_LIST;
366
367 case IIO_CHAN_INFO_SAMP_FREQ:
368 *type = IIO_VAL_INT;
369 *vals = ads1018->chip_info->data_rate_mode_to_hz;
370 *length = ads1018->chip_info->num_data_rate_mode_to_hz;
371 return IIO_AVAIL_LIST;
372
373 default:
374 return -EOPNOTSUPP;
375 }
376 }
377
378 static int
ads1018_write_raw_direct_mode(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)379 ads1018_write_raw_direct_mode(struct iio_dev *indio_dev,
380 struct iio_chan_spec const *chan, int val, int val2,
381 long mask)
382 {
383 struct ads1018 *ads1018 = iio_priv(indio_dev);
384 const struct ads1018_chip_info *info = ads1018->chip_info;
385 unsigned int i;
386
387 switch (mask) {
388 case IIO_CHAN_INFO_SCALE:
389 for (i = 0; i < ADS1018_NUM_PGA_MODES; i++) {
390 if (val == info->pga_mode_to_gain[i][0] &&
391 val2 == info->pga_mode_to_gain[i][1])
392 break;
393 }
394 if (i == ADS1018_NUM_PGA_MODES)
395 return -EINVAL;
396
397 ads1018->chan_data[chan->scan_index].pga_mode = i;
398 return 0;
399
400 case IIO_CHAN_INFO_SAMP_FREQ:
401 for (i = 0; i < info->num_data_rate_mode_to_hz; i++) {
402 if (val == info->data_rate_mode_to_hz[i])
403 break;
404 }
405 if (i == info->num_data_rate_mode_to_hz)
406 return -EINVAL;
407
408 ads1018->chan_data[chan->scan_index].data_rate_mode = i;
409 return 0;
410
411 default:
412 return -EOPNOTSUPP;
413 }
414 }
415
416 static int
ads1018_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)417 ads1018_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
418 int val, int val2, long mask)
419 {
420 int ret;
421
422 if (!iio_device_claim_direct(indio_dev))
423 return -EBUSY;
424 ret = ads1018_write_raw_direct_mode(indio_dev, chan, val, val2, mask);
425 iio_device_release_direct(indio_dev);
426
427 return ret;
428 }
429
430 static int
ads1018_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)431 ads1018_write_raw_get_fmt(struct iio_dev *indio_dev,
432 struct iio_chan_spec const *chan, long mask)
433 {
434 switch (mask) {
435 case IIO_CHAN_INFO_SCALE:
436 return IIO_VAL_INT_PLUS_NANO;
437 default:
438 return IIO_VAL_INT_PLUS_MICRO;
439 }
440 }
441
442 static const struct iio_info ads1018_iio_info = {
443 .read_raw = ads1018_read_raw,
444 .read_avail = ads1018_read_avail,
445 .write_raw = ads1018_write_raw,
446 .write_raw_get_fmt = ads1018_write_raw_get_fmt,
447 };
448
ads1018_set_trigger_enable(struct ads1018 * ads1018)449 static void ads1018_set_trigger_enable(struct ads1018 *ads1018)
450 {
451 spi_bus_lock(ads1018->spi->controller);
452 ads1018_spi_read_exclusive(ads1018, NULL, true);
453 enable_irq(ads1018->drdy_irq);
454 }
455
ads1018_set_trigger_disable(struct ads1018 * ads1018)456 static void ads1018_set_trigger_disable(struct ads1018 *ads1018)
457 {
458 disable_irq(ads1018->drdy_irq);
459 ads1018_spi_read_exclusive(ads1018, NULL, false);
460 spi_bus_unlock(ads1018->spi->controller);
461 }
462
ads1018_set_trigger_state(struct iio_trigger * trig,bool state)463 static int ads1018_set_trigger_state(struct iio_trigger *trig, bool state)
464 {
465 struct ads1018 *ads1018 = iio_trigger_get_drvdata(trig);
466
467 /*
468 * We need to lock the SPI bus and tie CS low (hold_cs) to catch
469 * data-ready interrupts, otherwise the MISO line enters a Hi-Z state.
470 */
471
472 if (state)
473 ads1018_set_trigger_enable(ads1018);
474 else
475 ads1018_set_trigger_disable(ads1018);
476
477 return 0;
478 }
479
480 static const struct iio_trigger_ops ads1018_trigger_ops = {
481 .set_trigger_state = ads1018_set_trigger_state,
482 .validate_device = iio_trigger_validate_own_device,
483 };
484
ads1018_buffer_preenable(struct iio_dev * indio_dev)485 static int ads1018_buffer_preenable(struct iio_dev *indio_dev)
486 {
487 struct ads1018 *ads1018 = iio_priv(indio_dev);
488 const struct ads1018_chip_info *chip_info = ads1018->chip_info;
489 unsigned int pga, drate, addr;
490 u16 cfg;
491
492 addr = find_first_bit(indio_dev->active_scan_mask,
493 iio_get_masklength(indio_dev));
494 pga = ads1018->chan_data[addr].pga_mode;
495 drate = ads1018->chan_data[addr].data_rate_mode;
496
497 cfg = ADS1018_CFG_VALID;
498 cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, addr);
499 cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga);
500 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS);
501 cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate);
502
503 if (chip_info->channels[addr].type == IIO_TEMP)
504 cfg |= ADS1018_CFG_TS_MODE_EN;
505
506 ads1018->tx_buf[0] = cpu_to_be16(cfg);
507 ads1018->tx_buf[1] = 0;
508
509 return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
510 }
511
ads1018_buffer_postdisable(struct iio_dev * indio_dev)512 static int ads1018_buffer_postdisable(struct iio_dev *indio_dev)
513 {
514 struct ads1018 *ads1018 = iio_priv(indio_dev);
515 u16 cfg;
516
517 cfg = ADS1018_CFG_VALID;
518 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
519
520 ads1018->tx_buf[0] = cpu_to_be16(cfg);
521 ads1018->tx_buf[1] = 0;
522
523 return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
524 }
525
526 static const struct iio_buffer_setup_ops ads1018_buffer_ops = {
527 .preenable = ads1018_buffer_preenable,
528 .postdisable = ads1018_buffer_postdisable,
529 .validate_scan_mask = iio_validate_scan_mask_onehot,
530 };
531
ads1018_irq_handler(int irq,void * dev_id)532 static irqreturn_t ads1018_irq_handler(int irq, void *dev_id)
533 {
534 struct ads1018 *ads1018 = dev_id;
535
536 /*
537 * We need to check if the "drdy" pin is actually active or if it's a
538 * pending interrupt triggered by the SPI transfer.
539 */
540 if (!gpiod_get_value(ads1018->drdy_gpiod))
541 return IRQ_HANDLED;
542
543 iio_trigger_poll(ads1018->indio_trig);
544
545 return IRQ_HANDLED;
546 }
547
ads1018_trigger_handler(int irq,void * p)548 static irqreturn_t ads1018_trigger_handler(int irq, void *p)
549 {
550 struct iio_poll_func *pf = p;
551 struct iio_dev *indio_dev = pf->indio_dev;
552 struct ads1018 *ads1018 = iio_priv(indio_dev);
553 struct {
554 __be16 conv;
555 aligned_s64 ts;
556 } scan = {};
557 int ret;
558
559 if (iio_trigger_using_own(indio_dev)) {
560 disable_irq(ads1018->drdy_irq);
561 ret = ads1018_spi_read_exclusive(ads1018, &scan.conv, true);
562 enable_irq(ads1018->drdy_irq);
563 } else {
564 ret = spi_read(ads1018->spi, ads1018->rx_buf, sizeof(ads1018->rx_buf));
565 scan.conv = ads1018->rx_buf[0];
566 }
567
568 if (!ret)
569 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan),
570 pf->timestamp);
571
572 iio_trigger_notify_done(indio_dev->trig);
573
574 return IRQ_HANDLED;
575 }
576
ads1018_trigger_setup(struct iio_dev * indio_dev)577 static int ads1018_trigger_setup(struct iio_dev *indio_dev)
578 {
579 struct ads1018 *ads1018 = iio_priv(indio_dev);
580 struct spi_device *spi = ads1018->spi;
581 struct device *dev = &spi->dev;
582 const char *con_id = "drdy";
583 int ret;
584
585 ads1018->drdy_gpiod = devm_gpiod_get_optional(dev, con_id, GPIOD_IN);
586 if (IS_ERR(ads1018->drdy_gpiod))
587 return dev_err_probe(dev, PTR_ERR(ads1018->drdy_gpiod),
588 "Failed to get %s GPIO.\n", con_id);
589
590 /* First try to get IRQ from SPI core, then from GPIO */
591 if (spi->irq > 0)
592 ads1018->drdy_irq = spi->irq;
593 else if (ads1018->drdy_gpiod)
594 ads1018->drdy_irq = gpiod_to_irq(ads1018->drdy_gpiod);
595 if (ads1018->drdy_irq < 0)
596 return dev_err_probe(dev, ads1018->drdy_irq,
597 "Failed to get IRQ from %s GPIO.\n", con_id);
598
599 /* An IRQ line is only an optional requirement for the IIO trigger */
600 if (ads1018->drdy_irq == 0)
601 return 0;
602
603 ads1018->indio_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-%s",
604 indio_dev->name,
605 iio_device_id(indio_dev),
606 con_id);
607 if (!ads1018->indio_trig)
608 return -ENOMEM;
609
610 iio_trigger_set_drvdata(ads1018->indio_trig, ads1018);
611 ads1018->indio_trig->ops = &ads1018_trigger_ops;
612
613 ret = devm_iio_trigger_register(dev, ads1018->indio_trig);
614 if (ret)
615 return ret;
616
617 /*
618 * The "data-ready" IRQ line is shared with the MOSI pin, thus we need
619 * to keep it disabled until we actually request data.
620 */
621 return devm_request_irq(dev, ads1018->drdy_irq, ads1018_irq_handler,
622 IRQF_NO_AUTOEN, ads1018->chip_info->name, ads1018);
623 }
624
ads1018_spi_probe(struct spi_device * spi)625 static int ads1018_spi_probe(struct spi_device *spi)
626 {
627 const struct ads1018_chip_info *info = spi_get_device_match_data(spi);
628 struct device *dev = &spi->dev;
629 struct iio_dev *indio_dev;
630 struct ads1018 *ads1018;
631 int ret;
632
633 indio_dev = devm_iio_device_alloc(dev, sizeof(*ads1018));
634 if (!indio_dev)
635 return -ENOMEM;
636
637 ads1018 = iio_priv(indio_dev);
638 ads1018->spi = spi;
639 ads1018->chip_info = info;
640
641 indio_dev->modes = INDIO_DIRECT_MODE;
642 indio_dev->name = info->name;
643 indio_dev->info = &ads1018_iio_info;
644 indio_dev->channels = info->channels;
645 indio_dev->num_channels = info->num_channels;
646
647 for (unsigned int i = 0; i < ADS1018_CHANNELS_MAX; i++) {
648 ads1018->chan_data[i].data_rate_mode = ADS1018_DRATE_DEFAULT;
649 ads1018->chan_data[i].pga_mode = ADS1018_PGA_DEFAULT;
650 }
651
652 ads1018->xfer.rx_buf = ads1018->rx_buf;
653 ads1018->xfer.len = sizeof(ads1018->rx_buf);
654 spi_message_init_with_transfers(&ads1018->msg_read, &ads1018->xfer, 1);
655
656 ret = ads1018_trigger_setup(indio_dev);
657 if (ret)
658 return ret;
659
660 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
661 iio_pollfunc_store_time,
662 ads1018_trigger_handler,
663 &ads1018_buffer_ops);
664 if (ret)
665 return ret;
666
667 return devm_iio_device_register(&spi->dev, indio_dev);
668 }
669
670 static const unsigned int ads1018_data_rate_table[] = {
671 128, 250, 490, 920, 1600, 2400, 3300,
672 };
673
674 static const unsigned int ads1118_data_rate_table[] = {
675 8, 16, 32, 64, 128, 250, 475, 860,
676 };
677
678 static const struct ads1018_chip_info ads1018_chip_info = {
679 .name = "ads1018",
680 .channels = ads1018_iio_channels,
681 .num_channels = ARRAY_SIZE(ads1018_iio_channels),
682 .data_rate_mode_to_hz = ads1018_data_rate_table,
683 .num_data_rate_mode_to_hz = ARRAY_SIZE(ads1018_data_rate_table),
684 .pga_mode_to_gain = {
685 { 3, 0 }, /* fsr = 6144 mV */
686 { 2, 0 }, /* fsr = 4096 mV */
687 { 1, 0 }, /* fsr = 2048 mV */
688 { 0, 500000000 }, /* fsr = 1024 mV */
689 { 0, 250000000 }, /* fsr = 512 mV */
690 { 0, 125000000 }, /* fsr = 256 mV */
691 },
692 .temp_scale = { 125, 0 },
693 };
694
695 static const struct ads1018_chip_info ads1118_chip_info = {
696 .name = "ads1118",
697 .channels = ads1118_iio_channels,
698 .num_channels = ARRAY_SIZE(ads1118_iio_channels),
699 .data_rate_mode_to_hz = ads1118_data_rate_table,
700 .num_data_rate_mode_to_hz = ARRAY_SIZE(ads1118_data_rate_table),
701 .pga_mode_to_gain = {
702 { 0, 187500000 }, /* fsr = 6144 mV */
703 { 0, 125000000 }, /* fsr = 4096 mV */
704 { 0, 62500000 }, /* fsr = 2048 mV */
705 { 0, 31250000 }, /* fsr = 1024 mV */
706 { 0, 15625000 }, /* fsr = 512 mV */
707 { 0, 7812500 }, /* fsr = 256 mV */
708 },
709 .temp_scale = { 31, 250000 },
710 };
711
712 static const struct of_device_id ads1018_of_match[] = {
713 { .compatible = "ti,ads1018", .data = &ads1018_chip_info },
714 { .compatible = "ti,ads1118", .data = &ads1118_chip_info },
715 { }
716 };
717 MODULE_DEVICE_TABLE(of, ads1018_of_match);
718
719 static const struct spi_device_id ads1018_spi_match[] = {
720 { .name = "ads1018", .driver_data = (kernel_ulong_t)&ads1018_chip_info },
721 { .name = "ads1118", .driver_data = (kernel_ulong_t)&ads1118_chip_info },
722 { }
723 };
724 MODULE_DEVICE_TABLE(spi, ads1018_spi_match);
725
726 static struct spi_driver ads1018_spi_driver = {
727 .driver = {
728 .name = "ads1018",
729 .of_match_table = ads1018_of_match,
730 },
731 .probe = ads1018_spi_probe,
732 .id_table = ads1018_spi_match,
733 };
734 module_spi_driver(ads1018_spi_driver);
735
736 MODULE_DESCRIPTION("Texas Instruments ADS1018 ADC Driver");
737 MODULE_LICENSE("GPL");
738 MODULE_AUTHOR("Kurt Borja <kuurtb@gmail.com>");
739