1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/iommu.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/page_pool/helpers.h>
23 #include <net/pkt_cls.h>
24 #include <net/pkt_sched.h>
25 #include <net/tcp.h>
26 #include <net/vxlan.h>
27 #include <net/geneve.h>
28
29 #include "hnae3.h"
30 #include "hns3_enet.h"
31 /* All hns3 tracepoints are defined by the include below, which
32 * must be included exactly once across the whole kernel with
33 * CREATE_TRACE_POINTS defined
34 */
35 #define CREATE_TRACE_POINTS
36 #include "hns3_trace.h"
37
38 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
39 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
40
41 #define hns3_rl_err(fmt, ...) \
42 do { \
43 if (net_ratelimit()) \
44 netdev_err(fmt, ##__VA_ARGS__); \
45 } while (0)
46
47 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
48
49 static const char hns3_driver_name[] = "hns3";
50 static const char hns3_driver_string[] =
51 "Hisilicon Ethernet Network Driver for Hip08 Family";
52 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
53 static struct hnae3_client client;
54
55 static int debug = -1;
56 module_param(debug, int, 0);
57 MODULE_PARM_DESC(debug, " Network interface message level setting");
58
59 static unsigned int tx_sgl = 1;
60 module_param(tx_sgl, uint, 0600);
61 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
62
63 static bool page_pool_enabled = true;
64 module_param(page_pool_enabled, bool, 0400);
65
66 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
67 sizeof(struct sg_table))
68 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
69 dma_get_cache_alignment())
70
71 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
72 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
73
74 #define HNS3_INNER_VLAN_TAG 1
75 #define HNS3_OUTER_VLAN_TAG 2
76
77 #define HNS3_MIN_TX_LEN 33U
78 #define HNS3_MIN_TUN_PKT_LEN 65U
79
80 /* hns3_pci_tbl - PCI Device ID Table
81 *
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id hns3_pci_tbl[] = {
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
104 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
105 /* required last entry */
106 {0,}
107 };
108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
109
110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
111 { ptype, \
112 l, \
113 CHECKSUM_##s, \
114 HNS3_L3_TYPE_##t, \
115 1, \
116 h}
117
118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
120 PKT_HASH_TYPE_NONE }
121
122 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
123 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
124 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
138 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
139 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
142 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
144 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
145 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
146 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
148 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
151 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
152 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
154 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
156 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
159 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
161 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
162 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
164 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
167 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
233 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
234 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
236 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
238 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
239 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
240 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
242 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
245 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
246 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
248 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
250 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
253 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
255 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
256 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
258 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
261 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
378 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
379 };
380
381 #define HNS3_INVALID_PTYPE \
382 ARRAY_SIZE(hns3_rx_ptype_tbl)
383
hns3_irq_handle(int irq,void * vector)384 static irqreturn_t hns3_irq_handle(int irq, void *vector)
385 {
386 struct hns3_enet_tqp_vector *tqp_vector = vector;
387
388 napi_schedule_irqoff(&tqp_vector->napi);
389 tqp_vector->event_cnt++;
390
391 return IRQ_HANDLED;
392 }
393
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)394 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
395 {
396 struct hns3_enet_tqp_vector *tqp_vectors;
397 unsigned int i;
398
399 for (i = 0; i < priv->vector_num; i++) {
400 tqp_vectors = &priv->tqp_vector[i];
401
402 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
403 continue;
404
405 /* clear the affinity mask */
406 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
407
408 /* release the irq resource */
409 free_irq(tqp_vectors->vector_irq, tqp_vectors);
410 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
411 }
412 }
413
hns3_nic_init_irq(struct hns3_nic_priv * priv)414 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
415 {
416 struct hns3_enet_tqp_vector *tqp_vectors;
417 int txrx_int_idx = 0;
418 int rx_int_idx = 0;
419 int tx_int_idx = 0;
420 unsigned int i;
421 int ret;
422
423 for (i = 0; i < priv->vector_num; i++) {
424 tqp_vectors = &priv->tqp_vector[i];
425
426 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
427 continue;
428
429 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
430 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
431 "%s-%s-%s-%d", hns3_driver_name,
432 pci_name(priv->ae_handle->pdev),
433 "TxRx", txrx_int_idx++);
434 txrx_int_idx++;
435 } else if (tqp_vectors->rx_group.ring) {
436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
437 "%s-%s-%s-%d", hns3_driver_name,
438 pci_name(priv->ae_handle->pdev),
439 "Rx", rx_int_idx++);
440 } else if (tqp_vectors->tx_group.ring) {
441 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
442 "%s-%s-%s-%d", hns3_driver_name,
443 pci_name(priv->ae_handle->pdev),
444 "Tx", tx_int_idx++);
445 } else {
446 /* Skip this unused q_vector */
447 continue;
448 }
449
450 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
451
452 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
453 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
454 tqp_vectors->name, tqp_vectors);
455 if (ret) {
456 netdev_err(priv->netdev, "request irq(%d) fail\n",
457 tqp_vectors->vector_irq);
458 hns3_nic_uninit_irq(priv);
459 return ret;
460 }
461
462 irq_set_affinity_hint(tqp_vectors->vector_irq,
463 &tqp_vectors->affinity_mask);
464
465 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
466 }
467
468 return 0;
469 }
470
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)471 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
472 u32 mask_en)
473 {
474 writel(mask_en, tqp_vector->mask_addr);
475 }
476
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)477 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
478 {
479 napi_enable(&tqp_vector->napi);
480 enable_irq(tqp_vector->vector_irq);
481 }
482
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)483 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
484 {
485 disable_irq(tqp_vector->vector_irq);
486 napi_disable(&tqp_vector->napi);
487 cancel_work_sync(&tqp_vector->rx_group.dim.work);
488 cancel_work_sync(&tqp_vector->tx_group.dim.work);
489 }
490
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)491 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
492 u32 rl_value)
493 {
494 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
495
496 /* this defines the configuration for RL (Interrupt Rate Limiter).
497 * Rl defines rate of interrupts i.e. number of interrupts-per-second
498 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
499 */
500 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
501 !tqp_vector->rx_group.coal.adapt_enable)
502 /* According to the hardware, the range of rl_reg is
503 * 0-59 and the unit is 4.
504 */
505 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
506
507 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
508 }
509
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)510 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
511 u32 gl_value)
512 {
513 u32 new_val;
514
515 if (tqp_vector->rx_group.coal.unit_1us)
516 new_val = gl_value | HNS3_INT_GL_1US;
517 else
518 new_val = hns3_gl_usec_to_reg(gl_value);
519
520 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
521 }
522
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)523 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
524 u32 gl_value)
525 {
526 u32 new_val;
527
528 if (tqp_vector->tx_group.coal.unit_1us)
529 new_val = gl_value | HNS3_INT_GL_1US;
530 else
531 new_val = hns3_gl_usec_to_reg(gl_value);
532
533 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
534 }
535
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)536 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
537 u32 ql_value)
538 {
539 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
540 }
541
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)542 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
543 u32 ql_value)
544 {
545 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
546 }
547
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)548 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
549 struct hns3_nic_priv *priv)
550 {
551 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
552 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
553 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
554 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
555 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
556
557 tx_coal->adapt_enable = ptx_coal->adapt_enable;
558 rx_coal->adapt_enable = prx_coal->adapt_enable;
559
560 tx_coal->int_gl = ptx_coal->int_gl;
561 rx_coal->int_gl = prx_coal->int_gl;
562
563 rx_coal->flow_level = prx_coal->flow_level;
564 tx_coal->flow_level = ptx_coal->flow_level;
565
566 /* device version above V3(include V3), GL can configure 1us
567 * unit, so uses 1us unit.
568 */
569 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
570 tx_coal->unit_1us = 1;
571 rx_coal->unit_1us = 1;
572 }
573
574 if (ae_dev->dev_specs.int_ql_max) {
575 tx_coal->ql_enable = 1;
576 rx_coal->ql_enable = 1;
577 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
578 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
579 tx_coal->int_ql = ptx_coal->int_ql;
580 rx_coal->int_ql = prx_coal->int_ql;
581 }
582 }
583
584 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)585 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
586 struct hns3_nic_priv *priv)
587 {
588 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
589 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
590 struct hnae3_handle *h = priv->ae_handle;
591
592 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
593 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
594 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
595
596 if (tx_coal->ql_enable)
597 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
598
599 if (rx_coal->ql_enable)
600 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
601 }
602
hns3_nic_set_real_num_queue(struct net_device * netdev)603 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
604 {
605 struct hnae3_handle *h = hns3_get_handle(netdev);
606 struct hnae3_knic_private_info *kinfo = &h->kinfo;
607 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
608 unsigned int queue_size = kinfo->num_tqps;
609 int i, ret;
610
611 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
612 netdev_reset_tc(netdev);
613 } else {
614 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
615 if (ret) {
616 netdev_err(netdev,
617 "netdev_set_num_tc fail, ret=%d!\n", ret);
618 return ret;
619 }
620
621 for (i = 0; i < tc_info->num_tc; i++)
622 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
623 tc_info->tqp_offset[i]);
624 }
625
626 ret = netif_set_real_num_tx_queues(netdev, queue_size);
627 if (ret) {
628 netdev_err(netdev,
629 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
630 return ret;
631 }
632
633 ret = netif_set_real_num_rx_queues(netdev, queue_size);
634 if (ret) {
635 netdev_err(netdev,
636 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
637 return ret;
638 }
639
640 return 0;
641 }
642
hns3_get_max_available_channels(struct hnae3_handle * h)643 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
644 {
645 u16 alloc_tqps, max_rss_size, rss_size;
646
647 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
648 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
649
650 return min_t(u16, rss_size, max_rss_size);
651 }
652
hns3_tqp_enable(struct hnae3_queue * tqp)653 static void hns3_tqp_enable(struct hnae3_queue *tqp)
654 {
655 u32 rcb_reg;
656
657 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
658 rcb_reg |= BIT(HNS3_RING_EN_B);
659 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
660 }
661
hns3_tqp_disable(struct hnae3_queue * tqp)662 static void hns3_tqp_disable(struct hnae3_queue *tqp)
663 {
664 u32 rcb_reg;
665
666 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
667 rcb_reg &= ~BIT(HNS3_RING_EN_B);
668 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
669 }
670
hns3_free_rx_cpu_rmap(struct net_device * netdev)671 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
672 {
673 #ifdef CONFIG_RFS_ACCEL
674 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
675 netdev->rx_cpu_rmap = NULL;
676 #endif
677 }
678
hns3_set_rx_cpu_rmap(struct net_device * netdev)679 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
680 {
681 #ifdef CONFIG_RFS_ACCEL
682 struct hns3_nic_priv *priv = netdev_priv(netdev);
683 struct hns3_enet_tqp_vector *tqp_vector;
684 int i, ret;
685
686 if (!netdev->rx_cpu_rmap) {
687 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
688 if (!netdev->rx_cpu_rmap)
689 return -ENOMEM;
690 }
691
692 for (i = 0; i < priv->vector_num; i++) {
693 tqp_vector = &priv->tqp_vector[i];
694 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
695 tqp_vector->vector_irq);
696 if (ret) {
697 hns3_free_rx_cpu_rmap(netdev);
698 return ret;
699 }
700 }
701 #endif
702 return 0;
703 }
704
hns3_enable_irqs_and_tqps(struct net_device * netdev)705 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
706 {
707 struct hns3_nic_priv *priv = netdev_priv(netdev);
708 struct hnae3_handle *h = priv->ae_handle;
709 u16 i;
710
711 for (i = 0; i < priv->vector_num; i++)
712 hns3_irq_enable(&priv->tqp_vector[i]);
713
714 for (i = 0; i < priv->vector_num; i++)
715 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
716
717 for (i = 0; i < h->kinfo.num_tqps; i++)
718 hns3_tqp_enable(h->kinfo.tqp[i]);
719 }
720
hns3_disable_irqs_and_tqps(struct net_device * netdev)721 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
722 {
723 struct hns3_nic_priv *priv = netdev_priv(netdev);
724 struct hnae3_handle *h = priv->ae_handle;
725 u16 i;
726
727 for (i = 0; i < h->kinfo.num_tqps; i++)
728 hns3_tqp_disable(h->kinfo.tqp[i]);
729
730 for (i = 0; i < priv->vector_num; i++)
731 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
732
733 for (i = 0; i < priv->vector_num; i++)
734 hns3_irq_disable(&priv->tqp_vector[i]);
735 }
736
hns3_nic_net_up(struct net_device * netdev)737 static int hns3_nic_net_up(struct net_device *netdev)
738 {
739 struct hns3_nic_priv *priv = netdev_priv(netdev);
740 struct hnae3_handle *h = priv->ae_handle;
741 int ret;
742
743 ret = hns3_nic_reset_all_ring(h);
744 if (ret)
745 return ret;
746
747 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
748
749 hns3_enable_irqs_and_tqps(netdev);
750
751 /* start the ae_dev */
752 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
753 if (ret) {
754 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
755 hns3_disable_irqs_and_tqps(netdev);
756 }
757
758 return ret;
759 }
760
hns3_config_xps(struct hns3_nic_priv * priv)761 static void hns3_config_xps(struct hns3_nic_priv *priv)
762 {
763 int i;
764
765 for (i = 0; i < priv->vector_num; i++) {
766 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
767 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
768
769 while (ring) {
770 int ret;
771
772 ret = netif_set_xps_queue(priv->netdev,
773 &tqp_vector->affinity_mask,
774 ring->tqp->tqp_index);
775 if (ret)
776 netdev_warn(priv->netdev,
777 "set xps queue failed: %d", ret);
778
779 ring = ring->next;
780 }
781 }
782 }
783
hns3_nic_net_open(struct net_device * netdev)784 static int hns3_nic_net_open(struct net_device *netdev)
785 {
786 struct hns3_nic_priv *priv = netdev_priv(netdev);
787 struct hnae3_handle *h = hns3_get_handle(netdev);
788 struct hnae3_knic_private_info *kinfo;
789 int i, ret;
790
791 if (hns3_nic_resetting(netdev))
792 return -EBUSY;
793
794 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
795 netdev_warn(netdev, "net open repeatedly!\n");
796 return 0;
797 }
798
799 netif_carrier_off(netdev);
800
801 ret = hns3_nic_set_real_num_queue(netdev);
802 if (ret)
803 return ret;
804
805 ret = hns3_nic_net_up(netdev);
806 if (ret) {
807 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
808 return ret;
809 }
810
811 kinfo = &h->kinfo;
812 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
813 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
814
815 if (h->ae_algo->ops->set_timer_task)
816 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
817
818 hns3_config_xps(priv);
819
820 netif_dbg(h, drv, netdev, "net open\n");
821
822 return 0;
823 }
824
hns3_reset_tx_queue(struct hnae3_handle * h)825 static void hns3_reset_tx_queue(struct hnae3_handle *h)
826 {
827 struct net_device *ndev = h->kinfo.netdev;
828 struct hns3_nic_priv *priv = netdev_priv(ndev);
829 struct netdev_queue *dev_queue;
830 u32 i;
831
832 for (i = 0; i < h->kinfo.num_tqps; i++) {
833 dev_queue = netdev_get_tx_queue(ndev,
834 priv->ring[i].queue_index);
835 netdev_tx_reset_queue(dev_queue);
836 }
837 }
838
hns3_nic_net_down(struct net_device * netdev)839 static void hns3_nic_net_down(struct net_device *netdev)
840 {
841 struct hns3_nic_priv *priv = netdev_priv(netdev);
842 const struct hnae3_ae_ops *ops;
843
844 hns3_disable_irqs_and_tqps(netdev);
845
846 /* stop ae_dev */
847 ops = priv->ae_handle->ae_algo->ops;
848 if (ops->stop)
849 ops->stop(priv->ae_handle);
850
851 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
852 * during reset process, because driver may not be able
853 * to disable the ring through firmware when downing the netdev.
854 */
855 if (!hns3_nic_resetting(netdev))
856 hns3_clear_all_ring(priv->ae_handle, false);
857
858 hns3_reset_tx_queue(priv->ae_handle);
859 }
860
hns3_nic_net_stop(struct net_device * netdev)861 static int hns3_nic_net_stop(struct net_device *netdev)
862 {
863 struct hns3_nic_priv *priv = netdev_priv(netdev);
864 struct hnae3_handle *h = hns3_get_handle(netdev);
865
866 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
867 return 0;
868
869 netif_dbg(h, drv, netdev, "net stop\n");
870
871 if (h->ae_algo->ops->set_timer_task)
872 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
873
874 netif_carrier_off(netdev);
875 netif_tx_disable(netdev);
876
877 hns3_nic_net_down(netdev);
878
879 return 0;
880 }
881
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)882 static int hns3_nic_uc_sync(struct net_device *netdev,
883 const unsigned char *addr)
884 {
885 struct hnae3_handle *h = hns3_get_handle(netdev);
886
887 if (h->ae_algo->ops->add_uc_addr)
888 return h->ae_algo->ops->add_uc_addr(h, addr);
889
890 return 0;
891 }
892
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)893 static int hns3_nic_uc_unsync(struct net_device *netdev,
894 const unsigned char *addr)
895 {
896 struct hnae3_handle *h = hns3_get_handle(netdev);
897
898 /* need ignore the request of removing device address, because
899 * we store the device address and other addresses of uc list
900 * in the function's mac filter list.
901 */
902 if (ether_addr_equal(addr, netdev->dev_addr))
903 return 0;
904
905 if (h->ae_algo->ops->rm_uc_addr)
906 return h->ae_algo->ops->rm_uc_addr(h, addr);
907
908 return 0;
909 }
910
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)911 static int hns3_nic_mc_sync(struct net_device *netdev,
912 const unsigned char *addr)
913 {
914 struct hnae3_handle *h = hns3_get_handle(netdev);
915
916 if (h->ae_algo->ops->add_mc_addr)
917 return h->ae_algo->ops->add_mc_addr(h, addr);
918
919 return 0;
920 }
921
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)922 static int hns3_nic_mc_unsync(struct net_device *netdev,
923 const unsigned char *addr)
924 {
925 struct hnae3_handle *h = hns3_get_handle(netdev);
926
927 if (h->ae_algo->ops->rm_mc_addr)
928 return h->ae_algo->ops->rm_mc_addr(h, addr);
929
930 return 0;
931 }
932
hns3_get_netdev_flags(struct net_device * netdev)933 static u8 hns3_get_netdev_flags(struct net_device *netdev)
934 {
935 u8 flags = 0;
936
937 if (netdev->flags & IFF_PROMISC)
938 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
939 else if (netdev->flags & IFF_ALLMULTI)
940 flags = HNAE3_USER_MPE;
941
942 return flags;
943 }
944
hns3_nic_set_rx_mode(struct net_device * netdev)945 static void hns3_nic_set_rx_mode(struct net_device *netdev)
946 {
947 struct hnae3_handle *h = hns3_get_handle(netdev);
948 u8 new_flags;
949
950 new_flags = hns3_get_netdev_flags(netdev);
951
952 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
953 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
954
955 /* User mode Promisc mode enable and vlan filtering is disabled to
956 * let all packets in.
957 */
958 h->netdev_flags = new_flags;
959 hns3_request_update_promisc_mode(h);
960 }
961
hns3_request_update_promisc_mode(struct hnae3_handle * handle)962 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
963 {
964 const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
965
966 if (ops->request_update_promisc_mode)
967 ops->request_update_promisc_mode(handle);
968 }
969
hns3_tx_spare_space(struct hns3_enet_ring * ring)970 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
971 {
972 struct hns3_tx_spare *tx_spare = ring->tx_spare;
973 u32 ntc, ntu;
974
975 /* This smp_load_acquire() pairs with smp_store_release() in
976 * hns3_tx_spare_update() called in tx desc cleaning process.
977 */
978 ntc = smp_load_acquire(&tx_spare->last_to_clean);
979 ntu = tx_spare->next_to_use;
980
981 if (ntc > ntu)
982 return ntc - ntu - 1;
983
984 /* The free tx buffer is divided into two part, so pick the
985 * larger one.
986 */
987 return max(ntc, tx_spare->len - ntu) - 1;
988 }
989
hns3_tx_spare_update(struct hns3_enet_ring * ring)990 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
991 {
992 struct hns3_tx_spare *tx_spare = ring->tx_spare;
993
994 if (!tx_spare ||
995 tx_spare->last_to_clean == tx_spare->next_to_clean)
996 return;
997
998 /* This smp_store_release() pairs with smp_load_acquire() in
999 * hns3_tx_spare_space() called in xmit process.
1000 */
1001 smp_store_release(&tx_spare->last_to_clean,
1002 tx_spare->next_to_clean);
1003 }
1004
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1005 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1006 struct sk_buff *skb,
1007 u32 space)
1008 {
1009 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1010 skb_headlen(skb);
1011
1012 if (len > ring->tx_copybreak)
1013 return false;
1014
1015 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1016 hns3_ring_stats_update(ring, tx_spare_full);
1017 return false;
1018 }
1019
1020 return true;
1021 }
1022
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1023 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1024 struct sk_buff *skb,
1025 u32 space)
1026 {
1027 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1028 (!skb_has_frag_list(skb) &&
1029 skb_shinfo(skb)->nr_frags < tx_sgl))
1030 return false;
1031
1032 if (space < HNS3_MAX_SGL_SIZE) {
1033 hns3_ring_stats_update(ring, tx_spare_full);
1034 return false;
1035 }
1036
1037 return true;
1038 }
1039
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1040 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1041 {
1042 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1043 struct net_device *netdev = ring_to_netdev(ring);
1044 struct hns3_nic_priv *priv = netdev_priv(netdev);
1045 struct hns3_tx_spare *tx_spare;
1046 struct page *page;
1047 dma_addr_t dma;
1048 int order;
1049
1050 if (!alloc_size)
1051 return;
1052
1053 order = get_order(alloc_size);
1054 if (order > MAX_PAGE_ORDER) {
1055 if (net_ratelimit())
1056 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1057 return;
1058 }
1059
1060 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1061 GFP_KERNEL);
1062 if (!tx_spare) {
1063 /* The driver still work without the tx spare buffer */
1064 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1065 goto devm_kzalloc_error;
1066 }
1067
1068 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1069 GFP_KERNEL, order);
1070 if (!page) {
1071 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1072 goto alloc_pages_error;
1073 }
1074
1075 dma = dma_map_page(ring_to_dev(ring), page, 0,
1076 PAGE_SIZE << order, DMA_TO_DEVICE);
1077 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1078 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1079 goto dma_mapping_error;
1080 }
1081
1082 tx_spare->dma = dma;
1083 tx_spare->buf = page_address(page);
1084 tx_spare->len = PAGE_SIZE << order;
1085 ring->tx_spare = tx_spare;
1086 ring->tx_copybreak = priv->tx_copybreak;
1087 return;
1088
1089 dma_mapping_error:
1090 put_page(page);
1091 alloc_pages_error:
1092 devm_kfree(ring_to_dev(ring), tx_spare);
1093 devm_kzalloc_error:
1094 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1095 }
1096
1097 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1098 * before calling below function to allocate tx buffer.
1099 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1100 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1101 unsigned int size, dma_addr_t *dma,
1102 u32 *cb_len)
1103 {
1104 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1105 u32 ntu = tx_spare->next_to_use;
1106
1107 size = ALIGN(size, dma_get_cache_alignment());
1108 *cb_len = size;
1109
1110 /* Tx spare buffer wraps back here because the end of
1111 * freed tx buffer is not enough.
1112 */
1113 if (ntu + size > tx_spare->len) {
1114 *cb_len += (tx_spare->len - ntu);
1115 ntu = 0;
1116 }
1117
1118 tx_spare->next_to_use = ntu + size;
1119 if (tx_spare->next_to_use == tx_spare->len)
1120 tx_spare->next_to_use = 0;
1121
1122 *dma = tx_spare->dma + ntu;
1123
1124 return tx_spare->buf + ntu;
1125 }
1126
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1127 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1128 {
1129 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1130
1131 if (len > tx_spare->next_to_use) {
1132 len -= tx_spare->next_to_use;
1133 tx_spare->next_to_use = tx_spare->len - len;
1134 } else {
1135 tx_spare->next_to_use -= len;
1136 }
1137 }
1138
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1139 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1140 struct hns3_desc_cb *cb)
1141 {
1142 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1143 u32 ntc = tx_spare->next_to_clean;
1144 u32 len = cb->length;
1145
1146 tx_spare->next_to_clean += len;
1147
1148 if (tx_spare->next_to_clean >= tx_spare->len) {
1149 tx_spare->next_to_clean -= tx_spare->len;
1150
1151 if (tx_spare->next_to_clean) {
1152 ntc = 0;
1153 len = tx_spare->next_to_clean;
1154 }
1155 }
1156
1157 /* This tx spare buffer is only really reclaimed after calling
1158 * hns3_tx_spare_update(), so it is still safe to use the info in
1159 * the tx buffer to do the dma sync or sg unmapping after
1160 * tx_spare->next_to_clean is moved forword.
1161 */
1162 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1163 dma_addr_t dma = tx_spare->dma + ntc;
1164
1165 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1166 DMA_TO_DEVICE);
1167 } else {
1168 struct sg_table *sgt = tx_spare->buf + ntc;
1169
1170 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1171 DMA_TO_DEVICE);
1172 }
1173 }
1174
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1175 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1176 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1177 {
1178 u32 l4_offset, hdr_len;
1179 union l3_hdr_info l3;
1180 union l4_hdr_info l4;
1181 u32 l4_paylen;
1182 int ret;
1183
1184 if (!skb_is_gso(skb))
1185 return 0;
1186
1187 ret = skb_cow_head(skb, 0);
1188 if (unlikely(ret < 0))
1189 return ret;
1190
1191 l3.hdr = skb_network_header(skb);
1192 l4.hdr = skb_transport_header(skb);
1193
1194 /* Software should clear the IPv4's checksum field when tso is
1195 * needed.
1196 */
1197 if (l3.v4->version == 4)
1198 l3.v4->check = 0;
1199
1200 /* tunnel packet */
1201 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1202 SKB_GSO_GRE_CSUM |
1203 SKB_GSO_UDP_TUNNEL |
1204 SKB_GSO_UDP_TUNNEL_CSUM)) {
1205 /* reset l3&l4 pointers from outer to inner headers */
1206 l3.hdr = skb_inner_network_header(skb);
1207 l4.hdr = skb_inner_transport_header(skb);
1208
1209 /* Software should clear the IPv4's checksum field when
1210 * tso is needed.
1211 */
1212 if (l3.v4->version == 4)
1213 l3.v4->check = 0;
1214 }
1215
1216 /* normal or tunnel packet */
1217 l4_offset = l4.hdr - skb->data;
1218
1219 /* remove payload length from inner pseudo checksum when tso */
1220 l4_paylen = skb->len - l4_offset;
1221
1222 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1223 hdr_len = sizeof(*l4.udp) + l4_offset;
1224 csum_replace_by_diff(&l4.udp->check,
1225 (__force __wsum)htonl(l4_paylen));
1226 } else {
1227 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1228 csum_replace_by_diff(&l4.tcp->check,
1229 (__force __wsum)htonl(l4_paylen));
1230 }
1231
1232 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1233
1234 /* find the txbd field values */
1235 *paylen_fdop_ol4cs = skb->len - hdr_len;
1236 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1237
1238 /* offload outer UDP header checksum */
1239 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1240 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1241
1242 /* get MSS for TSO */
1243 *mss = skb_shinfo(skb)->gso_size;
1244
1245 trace_hns3_tso(skb);
1246
1247 return 0;
1248 }
1249
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1250 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1251 u8 *il4_proto)
1252 {
1253 union l3_hdr_info l3;
1254 unsigned char *l4_hdr;
1255 unsigned char *exthdr;
1256 u8 l4_proto_tmp;
1257 __be16 frag_off;
1258
1259 /* find outer header point */
1260 l3.hdr = skb_network_header(skb);
1261 l4_hdr = skb_transport_header(skb);
1262
1263 if (skb->protocol == htons(ETH_P_IPV6)) {
1264 exthdr = l3.hdr + sizeof(*l3.v6);
1265 l4_proto_tmp = l3.v6->nexthdr;
1266 if (l4_hdr != exthdr)
1267 ipv6_skip_exthdr(skb, exthdr - skb->data,
1268 &l4_proto_tmp, &frag_off);
1269 } else if (skb->protocol == htons(ETH_P_IP)) {
1270 l4_proto_tmp = l3.v4->protocol;
1271 } else {
1272 return -EINVAL;
1273 }
1274
1275 *ol4_proto = l4_proto_tmp;
1276
1277 /* tunnel packet */
1278 if (!skb->encapsulation) {
1279 *il4_proto = 0;
1280 return 0;
1281 }
1282
1283 /* find inner header point */
1284 l3.hdr = skb_inner_network_header(skb);
1285 l4_hdr = skb_inner_transport_header(skb);
1286
1287 if (l3.v6->version == 6) {
1288 exthdr = l3.hdr + sizeof(*l3.v6);
1289 l4_proto_tmp = l3.v6->nexthdr;
1290 if (l4_hdr != exthdr)
1291 ipv6_skip_exthdr(skb, exthdr - skb->data,
1292 &l4_proto_tmp, &frag_off);
1293 } else if (l3.v4->version == 4) {
1294 l4_proto_tmp = l3.v4->protocol;
1295 }
1296
1297 *il4_proto = l4_proto_tmp;
1298
1299 return 0;
1300 }
1301
1302 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1303 * and it is udp packet, which has a dest port as the IANA assigned.
1304 * the hardware is expected to do the checksum offload, but the
1305 * hardware will not do the checksum offload when udp dest port is
1306 * 4789, 4790 or 6081.
1307 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1308 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1309 {
1310 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1311 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
1312 union l4_hdr_info l4;
1313
1314 /* device version above V3(include V3), the hardware can
1315 * do this checksum offload.
1316 */
1317 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1318 return false;
1319
1320 l4.hdr = skb_transport_header(skb);
1321
1322 if (!(!skb->encapsulation &&
1323 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1324 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1325 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1326 return false;
1327
1328 return true;
1329 }
1330
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1331 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1332 u32 *ol_type_vlan_len_msec)
1333 {
1334 u32 l2_len, l3_len, l4_len;
1335 unsigned char *il2_hdr;
1336 union l3_hdr_info l3;
1337 union l4_hdr_info l4;
1338
1339 l3.hdr = skb_network_header(skb);
1340 l4.hdr = skb_transport_header(skb);
1341
1342 /* compute OL2 header size, defined in 2 Bytes */
1343 l2_len = l3.hdr - skb->data;
1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1345
1346 /* compute OL3 header size, defined in 4 Bytes */
1347 l3_len = l4.hdr - l3.hdr;
1348 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1349
1350 il2_hdr = skb_inner_mac_header(skb);
1351 /* compute OL4 header size, defined in 4 Bytes */
1352 l4_len = il2_hdr - l4.hdr;
1353 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1354
1355 /* define outer network header type */
1356 if (skb->protocol == htons(ETH_P_IP)) {
1357 if (skb_is_gso(skb))
1358 hns3_set_field(*ol_type_vlan_len_msec,
1359 HNS3_TXD_OL3T_S,
1360 HNS3_OL3T_IPV4_CSUM);
1361 else
1362 hns3_set_field(*ol_type_vlan_len_msec,
1363 HNS3_TXD_OL3T_S,
1364 HNS3_OL3T_IPV4_NO_CSUM);
1365 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1366 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1367 HNS3_OL3T_IPV6);
1368 }
1369
1370 if (ol4_proto == IPPROTO_UDP)
1371 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1372 HNS3_TUN_MAC_IN_UDP);
1373 else if (ol4_proto == IPPROTO_GRE)
1374 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1375 HNS3_TUN_NVGRE);
1376 }
1377
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1378 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1379 u32 *type_cs_vlan_tso)
1380 {
1381 if (l3.v4->version == 4) {
1382 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1383 HNS3_L3T_IPV4);
1384
1385 /* the stack computes the IP header already, the only time we
1386 * need the hardware to recompute it is in the case of TSO.
1387 */
1388 if (skb_is_gso(skb))
1389 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1390 } else if (l3.v6->version == 6) {
1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1392 HNS3_L3T_IPV6);
1393 }
1394 }
1395
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1396 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1397 u32 l4_proto, u32 *type_cs_vlan_tso)
1398 {
1399 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1400 switch (l4_proto) {
1401 case IPPROTO_TCP:
1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1403 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1404 HNS3_L4T_TCP);
1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1406 l4.tcp->doff);
1407 break;
1408 case IPPROTO_UDP:
1409 if (hns3_tunnel_csum_bug(skb)) {
1410 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1411
1412 return ret ? ret : skb_checksum_help(skb);
1413 }
1414
1415 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1417 HNS3_L4T_UDP);
1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1419 (sizeof(struct udphdr) >> 2));
1420 break;
1421 case IPPROTO_SCTP:
1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1423 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1424 HNS3_L4T_SCTP);
1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1426 (sizeof(struct sctphdr) >> 2));
1427 break;
1428 default:
1429 /* drop the skb tunnel packet if hardware don't support,
1430 * because hardware can't calculate csum when TSO.
1431 */
1432 if (skb_is_gso(skb))
1433 return -EDOM;
1434
1435 /* the stack computes the IP header already,
1436 * driver calculate l4 checksum when not TSO.
1437 */
1438 return skb_checksum_help(skb);
1439 }
1440
1441 return 0;
1442 }
1443
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1444 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1445 u8 il4_proto, u32 *type_cs_vlan_tso,
1446 u32 *ol_type_vlan_len_msec)
1447 {
1448 unsigned char *l2_hdr = skb->data;
1449 u32 l4_proto = ol4_proto;
1450 union l4_hdr_info l4;
1451 union l3_hdr_info l3;
1452 u32 l2_len, l3_len;
1453
1454 l4.hdr = skb_transport_header(skb);
1455 l3.hdr = skb_network_header(skb);
1456
1457 /* handle encapsulation skb */
1458 if (skb->encapsulation) {
1459 /* If this is a not UDP/GRE encapsulation skb */
1460 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1461 /* drop the skb tunnel packet if hardware don't support,
1462 * because hardware can't calculate csum when TSO.
1463 */
1464 if (skb_is_gso(skb))
1465 return -EDOM;
1466
1467 /* the stack computes the IP header already,
1468 * driver calculate l4 checksum when not TSO.
1469 */
1470 return skb_checksum_help(skb);
1471 }
1472
1473 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1474
1475 /* switch to inner header */
1476 l2_hdr = skb_inner_mac_header(skb);
1477 l3.hdr = skb_inner_network_header(skb);
1478 l4.hdr = skb_inner_transport_header(skb);
1479 l4_proto = il4_proto;
1480 }
1481
1482 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1483
1484 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1485 l2_len = l3.hdr - l2_hdr;
1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1487
1488 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1489 l3_len = l4.hdr - l3.hdr;
1490 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1491
1492 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1493 }
1494
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1495 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1496 struct sk_buff *skb)
1497 {
1498 struct hnae3_handle *handle = tx_ring->tqp->handle;
1499 struct hnae3_ae_dev *ae_dev;
1500 struct vlan_ethhdr *vhdr;
1501 int rc;
1502
1503 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1504 skb_vlan_tag_present(skb)))
1505 return 0;
1506
1507 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1508 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1509 * will cause RAS error.
1510 */
1511 ae_dev = hns3_get_ae_dev(handle);
1512 if (unlikely(skb_vlan_tagged_multi(skb) &&
1513 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1514 handle->port_base_vlan_state ==
1515 HNAE3_PORT_BASE_VLAN_ENABLE))
1516 return -EINVAL;
1517
1518 if (skb->protocol == htons(ETH_P_8021Q) &&
1519 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1520 /* When HW VLAN acceleration is turned off, and the stack
1521 * sets the protocol to 802.1q, the driver just need to
1522 * set the protocol to the encapsulated ethertype.
1523 */
1524 skb->protocol = vlan_get_protocol(skb);
1525 return 0;
1526 }
1527
1528 if (skb_vlan_tag_present(skb)) {
1529 /* Based on hw strategy, use out_vtag in two layer tag case,
1530 * and use inner_vtag in one tag case.
1531 */
1532 if (skb->protocol == htons(ETH_P_8021Q) &&
1533 handle->port_base_vlan_state ==
1534 HNAE3_PORT_BASE_VLAN_DISABLE)
1535 rc = HNS3_OUTER_VLAN_TAG;
1536 else
1537 rc = HNS3_INNER_VLAN_TAG;
1538
1539 skb->protocol = vlan_get_protocol(skb);
1540 return rc;
1541 }
1542
1543 rc = skb_cow_head(skb, 0);
1544 if (unlikely(rc < 0))
1545 return rc;
1546
1547 vhdr = skb_vlan_eth_hdr(skb);
1548 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1549 & VLAN_PRIO_MASK);
1550
1551 skb->protocol = vlan_get_protocol(skb);
1552 return 0;
1553 }
1554
1555 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1556 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1557 {
1558 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1559
1560 /* Kindly note, due to backward compatibility of the TX descriptor,
1561 * HW checksum of the non-IP packets and GSO packets is handled at
1562 * different place in the following code
1563 */
1564 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1565 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1566 return false;
1567
1568 return true;
1569 }
1570
1571 struct hns3_desc_param {
1572 u32 paylen_ol4cs;
1573 u32 ol_type_vlan_len_msec;
1574 u32 type_cs_vlan_tso;
1575 u16 mss_hw_csum;
1576 u16 inner_vtag;
1577 u16 out_vtag;
1578 };
1579
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1580 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1581 {
1582 pa->paylen_ol4cs = skb->len;
1583 pa->ol_type_vlan_len_msec = 0;
1584 pa->type_cs_vlan_tso = 0;
1585 pa->mss_hw_csum = 0;
1586 pa->inner_vtag = 0;
1587 pa->out_vtag = 0;
1588 }
1589
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1590 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1591 struct sk_buff *skb,
1592 struct hns3_desc_param *param)
1593 {
1594 int ret;
1595
1596 ret = hns3_handle_vtags(ring, skb);
1597 if (unlikely(ret < 0)) {
1598 hns3_ring_stats_update(ring, tx_vlan_err);
1599 return ret;
1600 } else if (ret == HNS3_INNER_VLAN_TAG) {
1601 param->inner_vtag = skb_vlan_tag_get(skb);
1602 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1603 VLAN_PRIO_MASK;
1604 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1605 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1606 param->out_vtag = skb_vlan_tag_get(skb);
1607 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1608 VLAN_PRIO_MASK;
1609 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1610 1);
1611 }
1612 return 0;
1613 }
1614
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1615 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1616 struct sk_buff *skb,
1617 struct hns3_desc_cb *desc_cb,
1618 struct hns3_desc_param *param)
1619 {
1620 u8 ol4_proto, il4_proto;
1621 int ret;
1622
1623 if (hns3_check_hw_tx_csum(skb)) {
1624 /* set checksum start and offset, defined in 2 Bytes */
1625 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1626 skb_checksum_start_offset(skb) >> 1);
1627 hns3_set_field(param->ol_type_vlan_len_msec,
1628 HNS3_TXD_CSUM_OFFSET_S,
1629 skb->csum_offset >> 1);
1630 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1631 return 0;
1632 }
1633
1634 skb_reset_mac_len(skb);
1635
1636 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1637 if (unlikely(ret < 0)) {
1638 hns3_ring_stats_update(ring, tx_l4_proto_err);
1639 return ret;
1640 }
1641
1642 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1643 ¶m->type_cs_vlan_tso,
1644 ¶m->ol_type_vlan_len_msec);
1645 if (unlikely(ret < 0)) {
1646 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1647 return ret;
1648 }
1649
1650 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1651 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1652 if (unlikely(ret < 0)) {
1653 hns3_ring_stats_update(ring, tx_tso_err);
1654 return ret;
1655 }
1656 return 0;
1657 }
1658
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1659 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1660 struct sk_buff *skb, struct hns3_desc *desc,
1661 struct hns3_desc_cb *desc_cb)
1662 {
1663 struct hns3_desc_param param;
1664 int ret;
1665
1666 hns3_init_desc_data(skb, ¶m);
1667 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1668 if (unlikely(ret < 0))
1669 return ret;
1670
1671 desc_cb->send_bytes = skb->len;
1672
1673 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1674 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1675 if (ret)
1676 return ret;
1677 }
1678
1679 /* Set txbd */
1680 desc->tx.ol_type_vlan_len_msec =
1681 cpu_to_le32(param.ol_type_vlan_len_msec);
1682 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1683 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1684 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1685 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1686 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1687
1688 return 0;
1689 }
1690
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1691 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1692 unsigned int size)
1693 {
1694 #define HNS3_LIKELY_BD_NUM 1
1695
1696 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1697 unsigned int frag_buf_num, k;
1698 int sizeoflast;
1699
1700 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1701 desc->addr = cpu_to_le64(dma);
1702 desc->tx.send_size = cpu_to_le16(size);
1703 desc->tx.bdtp_fe_sc_vld_ra_ri =
1704 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1705
1706 trace_hns3_tx_desc(ring, ring->next_to_use);
1707 ring_ptr_move_fw(ring, next_to_use);
1708 return HNS3_LIKELY_BD_NUM;
1709 }
1710
1711 frag_buf_num = hns3_tx_bd_count(size);
1712 sizeoflast = size % HNS3_MAX_BD_SIZE;
1713 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1714
1715 /* When frag size is bigger than hardware limit, split this frag */
1716 for (k = 0; k < frag_buf_num; k++) {
1717 /* now, fill the descriptor */
1718 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1719 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1720 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1721 desc->tx.bdtp_fe_sc_vld_ra_ri =
1722 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1723
1724 trace_hns3_tx_desc(ring, ring->next_to_use);
1725 /* move ring pointer to next */
1726 ring_ptr_move_fw(ring, next_to_use);
1727
1728 desc = &ring->desc[ring->next_to_use];
1729 }
1730
1731 return frag_buf_num;
1732 }
1733
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1734 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1735 unsigned int type)
1736 {
1737 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1738 struct device *dev = ring_to_dev(ring);
1739 unsigned int size;
1740 dma_addr_t dma;
1741
1742 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1743 struct sk_buff *skb = (struct sk_buff *)priv;
1744
1745 size = skb_headlen(skb);
1746 if (!size)
1747 return 0;
1748
1749 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1750 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1751 /* Head data has been filled in hns3_handle_tx_bounce(),
1752 * just return 0 here.
1753 */
1754 return 0;
1755 } else {
1756 skb_frag_t *frag = (skb_frag_t *)priv;
1757
1758 size = skb_frag_size(frag);
1759 if (!size)
1760 return 0;
1761
1762 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1763 }
1764
1765 if (unlikely(dma_mapping_error(dev, dma))) {
1766 hns3_ring_stats_update(ring, sw_err_cnt);
1767 return -ENOMEM;
1768 }
1769
1770 desc_cb->priv = priv;
1771 desc_cb->length = size;
1772 desc_cb->dma = dma;
1773 desc_cb->type = type;
1774
1775 return hns3_fill_desc(ring, dma, size);
1776 }
1777
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1778 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1779 unsigned int bd_num)
1780 {
1781 unsigned int size;
1782 int i;
1783
1784 size = skb_headlen(skb);
1785 while (size > HNS3_MAX_BD_SIZE) {
1786 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1787 size -= HNS3_MAX_BD_SIZE;
1788
1789 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1790 return bd_num;
1791 }
1792
1793 if (size) {
1794 bd_size[bd_num++] = size;
1795 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1796 return bd_num;
1797 }
1798
1799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1801 size = skb_frag_size(frag);
1802 if (!size)
1803 continue;
1804
1805 while (size > HNS3_MAX_BD_SIZE) {
1806 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1807 size -= HNS3_MAX_BD_SIZE;
1808
1809 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1810 return bd_num;
1811 }
1812
1813 bd_size[bd_num++] = size;
1814 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1815 return bd_num;
1816 }
1817
1818 return bd_num;
1819 }
1820
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1821 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1822 u8 max_non_tso_bd_num, unsigned int bd_num,
1823 unsigned int recursion_level)
1824 {
1825 #define HNS3_MAX_RECURSION_LEVEL 24
1826
1827 struct sk_buff *frag_skb;
1828
1829 /* If the total len is within the max bd limit */
1830 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1831 !skb_has_frag_list(skb) &&
1832 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1833 return skb_shinfo(skb)->nr_frags + 1U;
1834
1835 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1836 return UINT_MAX;
1837
1838 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1839 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1840 return bd_num;
1841
1842 skb_walk_frags(skb, frag_skb) {
1843 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1844 bd_num, recursion_level + 1);
1845 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1846 return bd_num;
1847 }
1848
1849 return bd_num;
1850 }
1851
hns3_gso_hdr_len(struct sk_buff * skb)1852 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1853 {
1854 if (!skb->encapsulation)
1855 return skb_tcp_all_headers(skb);
1856
1857 return skb_inner_tcp_all_headers(skb);
1858 }
1859
1860 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1861 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1862 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1863 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1864 * than MSS except the last max_non_tso_bd_num - 1 frags.
1865 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1866 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1867 unsigned int bd_num, u8 max_non_tso_bd_num)
1868 {
1869 unsigned int tot_len = 0;
1870 unsigned int i;
1871
1872 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1873 tot_len += bd_size[i];
1874
1875 /* ensure the first max_non_tso_bd_num frags is greater than
1876 * mss + header
1877 */
1878 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1879 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1880 return true;
1881
1882 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1883 * than mss except the last one.
1884 */
1885 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1886 tot_len -= bd_size[i];
1887 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1888
1889 if (tot_len < skb_shinfo(skb)->gso_size)
1890 return true;
1891 }
1892
1893 return false;
1894 }
1895
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1896 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1897 {
1898 u32 i;
1899
1900 for (i = 0; i < MAX_SKB_FRAGS; i++)
1901 size[i] = skb_frag_size(&shinfo->frags[i]);
1902 }
1903
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1904 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1905 struct sk_buff *skb,
1906 unsigned int bd_num)
1907 {
1908 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1909 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1910 */
1911 if (bd_num == UINT_MAX) {
1912 hns3_ring_stats_update(ring, over_max_recursion);
1913 return -ENOMEM;
1914 }
1915
1916 /* The skb->len has exceeded the hw limitation, linearization
1917 * will not help.
1918 */
1919 if (skb->len > HNS3_MAX_TSO_SIZE ||
1920 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1921 hns3_ring_stats_update(ring, hw_limitation);
1922 return -ENOMEM;
1923 }
1924
1925 if (__skb_linearize(skb)) {
1926 hns3_ring_stats_update(ring, sw_err_cnt);
1927 return -ENOMEM;
1928 }
1929
1930 return 0;
1931 }
1932
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1933 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1934 struct net_device *netdev,
1935 struct sk_buff *skb)
1936 {
1937 struct hns3_nic_priv *priv = netdev_priv(netdev);
1938 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1939 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1940 unsigned int bd_num;
1941
1942 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1943 if (unlikely(bd_num > max_non_tso_bd_num)) {
1944 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1945 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1946 max_non_tso_bd_num)) {
1947 trace_hns3_over_max_bd(skb);
1948 goto out;
1949 }
1950
1951 if (hns3_skb_linearize(ring, skb, bd_num))
1952 return -ENOMEM;
1953
1954 bd_num = hns3_tx_bd_count(skb->len);
1955
1956 hns3_ring_stats_update(ring, tx_copy);
1957 }
1958
1959 out:
1960 if (likely(ring_space(ring) >= bd_num))
1961 return bd_num;
1962
1963 netif_stop_subqueue(netdev, ring->queue_index);
1964 smp_mb(); /* Memory barrier before checking ring_space */
1965
1966 /* Start queue in case hns3_clean_tx_ring has just made room
1967 * available and has not seen the queue stopped state performed
1968 * by netif_stop_subqueue above.
1969 */
1970 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1971 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1972 netif_start_subqueue(netdev, ring->queue_index);
1973 return bd_num;
1974 }
1975
1976 hns3_ring_stats_update(ring, tx_busy);
1977
1978 return -EBUSY;
1979 }
1980
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1981 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1982 {
1983 struct device *dev = ring_to_dev(ring);
1984 unsigned int i;
1985
1986 for (i = 0; i < ring->desc_num; i++) {
1987 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1988 struct hns3_desc_cb *desc_cb;
1989
1990 memset(desc, 0, sizeof(*desc));
1991
1992 /* check if this is where we started */
1993 if (ring->next_to_use == next_to_use_orig)
1994 break;
1995
1996 /* rollback one */
1997 ring_ptr_move_bw(ring, next_to_use);
1998
1999 desc_cb = &ring->desc_cb[ring->next_to_use];
2000
2001 if (!desc_cb->dma)
2002 continue;
2003
2004 /* unmap the descriptor dma address */
2005 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2006 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2007 DMA_TO_DEVICE);
2008 else if (desc_cb->type &
2009 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2010 hns3_tx_spare_rollback(ring, desc_cb->length);
2011 else if (desc_cb->length)
2012 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2013 DMA_TO_DEVICE);
2014
2015 desc_cb->length = 0;
2016 desc_cb->dma = 0;
2017 desc_cb->type = DESC_TYPE_UNKNOWN;
2018 }
2019 }
2020
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2021 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2022 struct sk_buff *skb, unsigned int type)
2023 {
2024 struct sk_buff *frag_skb;
2025 int i, ret, bd_num = 0;
2026
2027 ret = hns3_map_and_fill_desc(ring, skb, type);
2028 if (unlikely(ret < 0))
2029 return ret;
2030
2031 bd_num += ret;
2032
2033 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2035
2036 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2037 if (unlikely(ret < 0))
2038 return ret;
2039
2040 bd_num += ret;
2041 }
2042
2043 skb_walk_frags(skb, frag_skb) {
2044 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2045 DESC_TYPE_FRAGLIST_SKB);
2046 if (unlikely(ret < 0))
2047 return ret;
2048
2049 bd_num += ret;
2050 }
2051
2052 return bd_num;
2053 }
2054
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2055 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2056 {
2057 #define HNS3_BYTES_PER_64BIT 8
2058
2059 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2060 int offset = 0;
2061
2062 /* make sure everything is visible to device before
2063 * excuting tx push or updating doorbell
2064 */
2065 dma_wmb();
2066
2067 do {
2068 int idx = (ring->next_to_use - num + ring->desc_num) %
2069 ring->desc_num;
2070
2071 u64_stats_update_begin(&ring->syncp);
2072 ring->stats.tx_push++;
2073 u64_stats_update_end(&ring->syncp);
2074 memcpy(&desc[offset], &ring->desc[idx],
2075 sizeof(struct hns3_desc));
2076 offset++;
2077 } while (--num);
2078
2079 __iowrite64_copy(ring->tqp->mem_base, desc,
2080 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2081 HNS3_BYTES_PER_64BIT);
2082 }
2083
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2084 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2085 {
2086 #define HNS3_MEM_DOORBELL_OFFSET 64
2087
2088 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2089
2090 /* make sure everything is visible to device before
2091 * excuting tx push or updating doorbell
2092 */
2093 dma_wmb();
2094
2095 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2096 &bd_num, 1);
2097 u64_stats_update_begin(&ring->syncp);
2098 ring->stats.tx_mem_doorbell += ring->pending_buf;
2099 u64_stats_update_end(&ring->syncp);
2100 }
2101
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2102 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2103 bool doorbell)
2104 {
2105 struct net_device *netdev = ring_to_netdev(ring);
2106 struct hns3_nic_priv *priv = netdev_priv(netdev);
2107
2108 /* when tx push is enabled, the packet whose number of BD below
2109 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2110 */
2111 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2112 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2113 /* This smp_store_release() pairs with smp_load_acquire() in
2114 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2115 * is updated.
2116 */
2117 smp_store_release(&ring->last_to_use, ring->next_to_use);
2118 hns3_tx_push_bd(ring, num);
2119 return;
2120 }
2121
2122 ring->pending_buf += num;
2123
2124 if (!doorbell) {
2125 hns3_ring_stats_update(ring, tx_more);
2126 return;
2127 }
2128
2129 /* This smp_store_release() pairs with smp_load_acquire() in
2130 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2131 */
2132 smp_store_release(&ring->last_to_use, ring->next_to_use);
2133
2134 if (ring->tqp->mem_base)
2135 hns3_tx_mem_doorbell(ring);
2136 else
2137 writel(ring->pending_buf,
2138 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2139
2140 ring->pending_buf = 0;
2141 }
2142
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2143 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2144 struct hns3_desc *desc)
2145 {
2146 struct hnae3_handle *h = hns3_get_handle(netdev);
2147
2148 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2149 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2150 return;
2151
2152 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2153 }
2154
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2155 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2156 struct sk_buff *skb)
2157 {
2158 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2159 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2160 unsigned int size = skb_headlen(skb);
2161 dma_addr_t dma;
2162 int bd_num = 0;
2163 u32 cb_len;
2164 void *buf;
2165 int ret;
2166
2167 if (skb->len <= ring->tx_copybreak) {
2168 size = skb->len;
2169 type = DESC_TYPE_BOUNCE_ALL;
2170 }
2171
2172 /* hns3_can_use_tx_bounce() is called to ensure the below
2173 * function can always return the tx buffer.
2174 */
2175 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2176
2177 ret = skb_copy_bits(skb, 0, buf, size);
2178 if (unlikely(ret < 0)) {
2179 hns3_tx_spare_rollback(ring, cb_len);
2180 hns3_ring_stats_update(ring, copy_bits_err);
2181 return ret;
2182 }
2183
2184 desc_cb->priv = skb;
2185 desc_cb->length = cb_len;
2186 desc_cb->dma = dma;
2187 desc_cb->type = type;
2188
2189 bd_num += hns3_fill_desc(ring, dma, size);
2190
2191 if (type == DESC_TYPE_BOUNCE_HEAD) {
2192 ret = hns3_fill_skb_to_desc(ring, skb,
2193 DESC_TYPE_BOUNCE_HEAD);
2194 if (unlikely(ret < 0))
2195 return ret;
2196
2197 bd_num += ret;
2198 }
2199
2200 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2201 DMA_TO_DEVICE);
2202
2203 hns3_ring_stats_update(ring, tx_bounce);
2204
2205 return bd_num;
2206 }
2207
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2208 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2209 struct sk_buff *skb)
2210 {
2211 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2212 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2213 struct sg_table *sgt;
2214 int bd_num = 0;
2215 dma_addr_t dma;
2216 u32 cb_len, i;
2217 int nents;
2218
2219 if (skb_has_frag_list(skb))
2220 nfrag = HNS3_MAX_TSO_BD_NUM;
2221
2222 /* hns3_can_use_tx_sgl() is called to ensure the below
2223 * function can always return the tx buffer.
2224 */
2225 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2226 &dma, &cb_len);
2227
2228 /* scatterlist follows by the sg table */
2229 sgt->sgl = (struct scatterlist *)(sgt + 1);
2230 sg_init_table(sgt->sgl, nfrag);
2231 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2232 if (unlikely(nents < 0)) {
2233 hns3_tx_spare_rollback(ring, cb_len);
2234 hns3_ring_stats_update(ring, skb2sgl_err);
2235 return -ENOMEM;
2236 }
2237
2238 sgt->orig_nents = nents;
2239 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2240 DMA_TO_DEVICE);
2241 if (unlikely(!sgt->nents)) {
2242 hns3_tx_spare_rollback(ring, cb_len);
2243 hns3_ring_stats_update(ring, map_sg_err);
2244 return -ENOMEM;
2245 }
2246
2247 desc_cb->priv = skb;
2248 desc_cb->length = cb_len;
2249 desc_cb->dma = dma;
2250 desc_cb->type = DESC_TYPE_SGL_SKB;
2251
2252 for (i = 0; i < sgt->nents; i++)
2253 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2254 sg_dma_len(sgt->sgl + i));
2255 hns3_ring_stats_update(ring, tx_sgl);
2256
2257 return bd_num;
2258 }
2259
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2260 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2261 struct sk_buff *skb)
2262 {
2263 u32 space;
2264
2265 if (!ring->tx_spare)
2266 goto out;
2267
2268 space = hns3_tx_spare_space(ring);
2269
2270 if (hns3_can_use_tx_sgl(ring, skb, space))
2271 return hns3_handle_tx_sgl(ring, skb);
2272
2273 if (hns3_can_use_tx_bounce(ring, skb, space))
2274 return hns3_handle_tx_bounce(ring, skb);
2275
2276 out:
2277 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2278 }
2279
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2280 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2281 struct sk_buff *skb,
2282 struct hns3_desc_cb *desc_cb,
2283 int next_to_use_head)
2284 {
2285 int ret;
2286
2287 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2288 desc_cb);
2289 if (unlikely(ret < 0))
2290 goto fill_err;
2291
2292 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2293 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2294 * need to be notified to the hw.
2295 */
2296 ret = hns3_handle_desc_filling(ring, skb);
2297 if (likely(ret > 0))
2298 return ret;
2299
2300 fill_err:
2301 hns3_clear_desc(ring, next_to_use_head);
2302 return ret;
2303 }
2304
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2305 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2306 {
2307 struct hns3_nic_priv *priv = netdev_priv(netdev);
2308 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2309 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2310 struct netdev_queue *dev_queue;
2311 int pre_ntu, ret;
2312 bool doorbell;
2313
2314 /* Hardware can only handle short frames above 32 bytes */
2315 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2316 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2317
2318 hns3_ring_stats_update(ring, sw_err_cnt);
2319
2320 return NETDEV_TX_OK;
2321 }
2322
2323 /* Prefetch the data used later */
2324 prefetch(skb->data);
2325
2326 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2327 if (unlikely(ret <= 0)) {
2328 if (ret == -EBUSY) {
2329 hns3_tx_doorbell(ring, 0, true);
2330 return NETDEV_TX_BUSY;
2331 }
2332
2333 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2334 goto out_err_tx_ok;
2335 }
2336
2337 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2338 if (unlikely(ret <= 0))
2339 goto out_err_tx_ok;
2340
2341 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2342 (ring->desc_num - 1);
2343
2344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2345 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2346
2347 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2348 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2349 trace_hns3_tx_desc(ring, pre_ntu);
2350
2351 skb_tx_timestamp(skb);
2352
2353 /* Complete translate all packets */
2354 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2355 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2356 netdev_xmit_more());
2357 hns3_tx_doorbell(ring, ret, doorbell);
2358
2359 return NETDEV_TX_OK;
2360
2361 out_err_tx_ok:
2362 dev_kfree_skb_any(skb);
2363 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2364 return NETDEV_TX_OK;
2365 }
2366
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2367 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2368 {
2369 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2370 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2371 struct hnae3_handle *h = hns3_get_handle(netdev);
2372 struct sockaddr *mac_addr = p;
2373 int ret;
2374
2375 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2376 return -EADDRNOTAVAIL;
2377
2378 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2379 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2380 netdev_info(netdev, "already using mac address %s\n",
2381 format_mac_addr_sa);
2382 return 0;
2383 }
2384
2385 /* For VF device, if there is a perm_addr, then the user will not
2386 * be allowed to change the address.
2387 */
2388 if (!hns3_is_phys_func(h->pdev) &&
2389 !is_zero_ether_addr(netdev->perm_addr)) {
2390 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2391 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2392 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2393 format_mac_addr_perm, format_mac_addr_sa);
2394 return -EPERM;
2395 }
2396
2397 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2398 if (ret) {
2399 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2400 return ret;
2401 }
2402
2403 eth_hw_addr_set(netdev, mac_addr->sa_data);
2404
2405 return 0;
2406 }
2407
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2408 static int hns3_nic_do_ioctl(struct net_device *netdev,
2409 struct ifreq *ifr, int cmd)
2410 {
2411 struct hnae3_handle *h = hns3_get_handle(netdev);
2412
2413 if (!netif_running(netdev))
2414 return -EINVAL;
2415
2416 if (!h->ae_algo->ops->do_ioctl)
2417 return -EOPNOTSUPP;
2418
2419 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2420 }
2421
hns3_nic_hwtstamp_get(struct net_device * netdev,struct kernel_hwtstamp_config * config)2422 static int hns3_nic_hwtstamp_get(struct net_device *netdev,
2423 struct kernel_hwtstamp_config *config)
2424 {
2425 struct hnae3_handle *h = hns3_get_handle(netdev);
2426
2427 if (!netif_running(netdev))
2428 return -EINVAL;
2429
2430 if (!h->ae_algo->ops->hwtstamp_get)
2431 return -EOPNOTSUPP;
2432
2433 return h->ae_algo->ops->hwtstamp_get(h, config);
2434 }
2435
hns3_nic_hwtstamp_set(struct net_device * netdev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)2436 static int hns3_nic_hwtstamp_set(struct net_device *netdev,
2437 struct kernel_hwtstamp_config *config,
2438 struct netlink_ext_ack *extack)
2439 {
2440 struct hnae3_handle *h = hns3_get_handle(netdev);
2441
2442 if (!netif_running(netdev))
2443 return -EINVAL;
2444
2445 if (!h->ae_algo->ops->hwtstamp_set)
2446 return -EOPNOTSUPP;
2447
2448 return h->ae_algo->ops->hwtstamp_set(h, config, extack);
2449 }
2450
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2451 static int hns3_nic_set_features(struct net_device *netdev,
2452 netdev_features_t features)
2453 {
2454 netdev_features_t changed = netdev->features ^ features;
2455 struct hns3_nic_priv *priv = netdev_priv(netdev);
2456 struct hnae3_handle *h = priv->ae_handle;
2457 bool enable;
2458 int ret;
2459
2460 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2461 enable = !!(features & NETIF_F_GRO_HW);
2462 ret = h->ae_algo->ops->set_gro_en(h, enable);
2463 if (ret)
2464 return ret;
2465 }
2466
2467 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2468 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2469 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2470 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2471 if (ret)
2472 return ret;
2473 }
2474
2475 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2476 enable = !!(features & NETIF_F_NTUPLE);
2477 h->ae_algo->ops->enable_fd(h, enable);
2478 }
2479
2480 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2481 h->ae_algo->ops->cls_flower_active(h)) {
2482 netdev_err(netdev,
2483 "there are offloaded TC filters active, cannot disable HW TC offload\n");
2484 return -EINVAL;
2485 }
2486
2487 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2488 h->ae_algo->ops->enable_vlan_filter) {
2489 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2490 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2491 if (ret)
2492 return ret;
2493 }
2494
2495 return 0;
2496 }
2497
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2498 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2499 struct net_device *dev,
2500 netdev_features_t features)
2501 {
2502 #define HNS3_MAX_HDR_LEN 480U
2503 #define HNS3_MAX_L4_HDR_LEN 60U
2504
2505 size_t len;
2506
2507 if (skb->ip_summed != CHECKSUM_PARTIAL)
2508 return features;
2509
2510 if (skb->encapsulation)
2511 len = skb_inner_transport_offset(skb);
2512 else
2513 len = skb_transport_offset(skb);
2514
2515 /* Assume L4 is 60 byte as TCP is the only protocol with a
2516 * a flexible value, and it's max len is 60 bytes.
2517 */
2518 len += HNS3_MAX_L4_HDR_LEN;
2519
2520 /* Hardware only supports checksum on the skb with a max header
2521 * len of 480 bytes.
2522 */
2523 if (len > HNS3_MAX_HDR_LEN)
2524 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2525
2526 return features;
2527 }
2528
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2529 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2530 struct hns3_enet_ring *ring, bool is_tx)
2531 {
2532 struct ring_stats ring_stats;
2533 unsigned int start;
2534
2535 do {
2536 start = u64_stats_fetch_begin(&ring->syncp);
2537 ring_stats = ring->stats;
2538 } while (u64_stats_fetch_retry(&ring->syncp, start));
2539
2540 if (is_tx) {
2541 stats->tx_bytes += ring_stats.tx_bytes;
2542 stats->tx_packets += ring_stats.tx_pkts;
2543 stats->tx_dropped += ring_stats.sw_err_cnt;
2544 stats->tx_dropped += ring_stats.tx_vlan_err;
2545 stats->tx_dropped += ring_stats.tx_l4_proto_err;
2546 stats->tx_dropped += ring_stats.tx_l2l3l4_err;
2547 stats->tx_dropped += ring_stats.tx_tso_err;
2548 stats->tx_dropped += ring_stats.over_max_recursion;
2549 stats->tx_dropped += ring_stats.hw_limitation;
2550 stats->tx_dropped += ring_stats.copy_bits_err;
2551 stats->tx_dropped += ring_stats.skb2sgl_err;
2552 stats->tx_dropped += ring_stats.map_sg_err;
2553 stats->tx_errors += ring_stats.sw_err_cnt;
2554 stats->tx_errors += ring_stats.tx_vlan_err;
2555 stats->tx_errors += ring_stats.tx_l4_proto_err;
2556 stats->tx_errors += ring_stats.tx_l2l3l4_err;
2557 stats->tx_errors += ring_stats.tx_tso_err;
2558 stats->tx_errors += ring_stats.over_max_recursion;
2559 stats->tx_errors += ring_stats.hw_limitation;
2560 stats->tx_errors += ring_stats.copy_bits_err;
2561 stats->tx_errors += ring_stats.skb2sgl_err;
2562 stats->tx_errors += ring_stats.map_sg_err;
2563 } else {
2564 stats->rx_bytes += ring_stats.rx_bytes;
2565 stats->rx_packets += ring_stats.rx_pkts;
2566 stats->rx_dropped += ring_stats.l2_err;
2567 stats->rx_errors += ring_stats.l2_err;
2568 stats->rx_errors += ring_stats.l3l4_csum_err;
2569 stats->rx_crc_errors += ring_stats.l2_err;
2570 stats->multicast += ring_stats.rx_multicast;
2571 stats->rx_length_errors += ring_stats.err_pkt_len;
2572 }
2573 }
2574
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2575 static void hns3_nic_get_stats64(struct net_device *netdev,
2576 struct rtnl_link_stats64 *stats)
2577 {
2578 struct hns3_nic_priv *priv = netdev_priv(netdev);
2579 int queue_num = priv->ae_handle->kinfo.num_tqps;
2580 struct hnae3_handle *handle = priv->ae_handle;
2581 struct rtnl_link_stats64 ring_total_stats;
2582 struct hns3_enet_ring *ring;
2583 int idx;
2584
2585 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2586 return;
2587
2588 handle->ae_algo->ops->update_stats(handle);
2589
2590 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2591 for (idx = 0; idx < queue_num; idx++) {
2592 /* fetch the tx stats */
2593 ring = &priv->ring[idx];
2594 hns3_fetch_stats(&ring_total_stats, ring, true);
2595
2596 /* fetch the rx stats */
2597 ring = &priv->ring[idx + queue_num];
2598 hns3_fetch_stats(&ring_total_stats, ring, false);
2599 }
2600
2601 stats->tx_bytes = ring_total_stats.tx_bytes;
2602 stats->tx_packets = ring_total_stats.tx_packets;
2603 stats->rx_bytes = ring_total_stats.rx_bytes;
2604 stats->rx_packets = ring_total_stats.rx_packets;
2605
2606 stats->rx_errors = ring_total_stats.rx_errors;
2607 stats->multicast = ring_total_stats.multicast;
2608 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2609 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2610 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2611
2612 stats->tx_errors = ring_total_stats.tx_errors;
2613 stats->rx_dropped = ring_total_stats.rx_dropped;
2614 stats->tx_dropped = ring_total_stats.tx_dropped;
2615 stats->collisions = netdev->stats.collisions;
2616 stats->rx_over_errors = netdev->stats.rx_over_errors;
2617 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2618 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2619 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2620 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2621 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2622 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2623 stats->tx_window_errors = netdev->stats.tx_window_errors;
2624 stats->rx_compressed = netdev->stats.rx_compressed;
2625 stats->tx_compressed = netdev->stats.tx_compressed;
2626 }
2627
hns3_setup_tc(struct net_device * netdev,void * type_data)2628 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2629 {
2630 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2631 struct hnae3_knic_private_info *kinfo;
2632 u8 tc = mqprio_qopt->qopt.num_tc;
2633 u16 mode = mqprio_qopt->mode;
2634 u8 hw = mqprio_qopt->qopt.hw;
2635 struct hnae3_handle *h;
2636
2637 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2638 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2639 return -EOPNOTSUPP;
2640
2641 if (tc > HNAE3_MAX_TC)
2642 return -EINVAL;
2643
2644 if (!netdev)
2645 return -EINVAL;
2646
2647 h = hns3_get_handle(netdev);
2648 kinfo = &h->kinfo;
2649
2650 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2651
2652 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2653 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2654 }
2655
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2656 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2657 struct flow_cls_offload *flow)
2658 {
2659 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2660 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2661
2662 switch (flow->command) {
2663 case FLOW_CLS_REPLACE:
2664 if (h->ae_algo->ops->add_cls_flower)
2665 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2666 break;
2667 case FLOW_CLS_DESTROY:
2668 if (h->ae_algo->ops->del_cls_flower)
2669 return h->ae_algo->ops->del_cls_flower(h, flow);
2670 break;
2671 default:
2672 break;
2673 }
2674
2675 return -EOPNOTSUPP;
2676 }
2677
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2678 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2679 void *cb_priv)
2680 {
2681 struct hns3_nic_priv *priv = cb_priv;
2682
2683 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2684 return -EOPNOTSUPP;
2685
2686 switch (type) {
2687 case TC_SETUP_CLSFLOWER:
2688 return hns3_setup_tc_cls_flower(priv, type_data);
2689 default:
2690 return -EOPNOTSUPP;
2691 }
2692 }
2693
2694 static LIST_HEAD(hns3_block_cb_list);
2695
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2696 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2697 void *type_data)
2698 {
2699 struct hns3_nic_priv *priv = netdev_priv(dev);
2700 int ret;
2701
2702 switch (type) {
2703 case TC_SETUP_QDISC_MQPRIO:
2704 ret = hns3_setup_tc(dev, type_data);
2705 break;
2706 case TC_SETUP_BLOCK:
2707 ret = flow_block_cb_setup_simple(type_data,
2708 &hns3_block_cb_list,
2709 hns3_setup_tc_block_cb,
2710 priv, priv, true);
2711 break;
2712 default:
2713 return -EOPNOTSUPP;
2714 }
2715
2716 return ret;
2717 }
2718
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2719 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2720 __be16 proto, u16 vid)
2721 {
2722 struct hnae3_handle *h = hns3_get_handle(netdev);
2723 int ret = -EIO;
2724
2725 if (h->ae_algo->ops->set_vlan_filter)
2726 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2727
2728 return ret;
2729 }
2730
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2731 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2732 __be16 proto, u16 vid)
2733 {
2734 struct hnae3_handle *h = hns3_get_handle(netdev);
2735 int ret = -EIO;
2736
2737 if (h->ae_algo->ops->set_vlan_filter)
2738 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2739
2740 return ret;
2741 }
2742
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2743 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2744 u8 qos, __be16 vlan_proto)
2745 {
2746 struct hnae3_handle *h = hns3_get_handle(netdev);
2747 int ret = -EIO;
2748
2749 netif_dbg(h, drv, netdev,
2750 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2751 vf, vlan, qos, ntohs(vlan_proto));
2752
2753 if (h->ae_algo->ops->set_vf_vlan_filter)
2754 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2755 qos, vlan_proto);
2756
2757 return ret;
2758 }
2759
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2760 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2761 {
2762 struct hnae3_handle *handle = hns3_get_handle(netdev);
2763
2764 if (hns3_nic_resetting(netdev))
2765 return -EBUSY;
2766
2767 if (!handle->ae_algo->ops->set_vf_spoofchk)
2768 return -EOPNOTSUPP;
2769
2770 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2771 }
2772
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2773 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2774 {
2775 struct hnae3_handle *handle = hns3_get_handle(netdev);
2776
2777 if (!handle->ae_algo->ops->set_vf_trust)
2778 return -EOPNOTSUPP;
2779
2780 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2781 }
2782
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2783 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2784 {
2785 struct hnae3_handle *h = hns3_get_handle(netdev);
2786 int ret;
2787
2788 if (hns3_nic_resetting(netdev))
2789 return -EBUSY;
2790
2791 if (!h->ae_algo->ops->set_mtu)
2792 return -EOPNOTSUPP;
2793
2794 netif_dbg(h, drv, netdev,
2795 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2796
2797 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2798 if (ret)
2799 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2800 ret);
2801 else
2802 WRITE_ONCE(netdev->mtu, new_mtu);
2803
2804 return ret;
2805 }
2806
hns3_get_timeout_queue(struct net_device * ndev)2807 static int hns3_get_timeout_queue(struct net_device *ndev)
2808 {
2809 unsigned int i;
2810
2811 /* Find the stopped queue the same way the stack does */
2812 for (i = 0; i < ndev->num_tx_queues; i++) {
2813 struct netdev_queue *q;
2814 unsigned long trans_start;
2815
2816 q = netdev_get_tx_queue(ndev, i);
2817 trans_start = READ_ONCE(q->trans_start);
2818 if (netif_xmit_stopped(q) &&
2819 time_after(jiffies,
2820 (trans_start + ndev->watchdog_timeo))) {
2821 #ifdef CONFIG_BQL
2822 struct dql *dql = &q->dql;
2823
2824 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2825 dql->last_obj_cnt, dql->num_queued,
2826 dql->adj_limit, dql->num_completed);
2827 #endif
2828 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2829 q->state,
2830 jiffies_to_msecs(jiffies - trans_start));
2831 break;
2832 }
2833 }
2834
2835 return i;
2836 }
2837
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2838 static void hns3_dump_queue_stats(struct net_device *ndev,
2839 struct hns3_enet_ring *tx_ring,
2840 int timeout_queue)
2841 {
2842 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2843 struct hns3_nic_priv *priv = netdev_priv(ndev);
2844
2845 netdev_info(ndev,
2846 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2847 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2848 tx_ring->next_to_clean, napi->state);
2849
2850 netdev_info(ndev,
2851 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2852 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2853 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2854
2855 netdev_info(ndev,
2856 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2857 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2858 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2859
2860 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2861 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2862 }
2863
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2864 static void hns3_dump_queue_reg(struct net_device *ndev,
2865 struct hns3_enet_ring *tx_ring)
2866 {
2867 netdev_info(ndev,
2868 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2869 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2870 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2871 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2872 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2873 readl(tx_ring->tqp_vector->mask_addr));
2874 netdev_info(ndev,
2875 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2876 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2877 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2878 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2879 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2880 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2881 hns3_tqp_read_reg(tx_ring,
2882 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2883 }
2884
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2885 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2886 {
2887 struct hns3_nic_priv *priv = netdev_priv(ndev);
2888 struct hnae3_handle *h = hns3_get_handle(ndev);
2889 struct hns3_enet_ring *tx_ring;
2890 u32 timeout_queue;
2891
2892 timeout_queue = hns3_get_timeout_queue(ndev);
2893 if (timeout_queue >= ndev->num_tx_queues) {
2894 netdev_info(ndev,
2895 "no netdev TX timeout queue found, timeout count: %llu\n",
2896 priv->tx_timeout_count);
2897 return false;
2898 }
2899
2900 priv->tx_timeout_count++;
2901
2902 tx_ring = &priv->ring[timeout_queue];
2903 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2904
2905 /* When mac received many pause frames continuous, it's unable to send
2906 * packets, which may cause tx timeout
2907 */
2908 if (h->ae_algo->ops->get_mac_stats) {
2909 struct hns3_mac_stats mac_stats;
2910
2911 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2912 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2913 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2914 }
2915
2916 hns3_dump_queue_reg(ndev, tx_ring);
2917
2918 return true;
2919 }
2920
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2921 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2922 {
2923 struct hns3_nic_priv *priv = netdev_priv(ndev);
2924 struct hnae3_handle *h = priv->ae_handle;
2925
2926 if (!hns3_get_tx_timeo_queue_info(ndev))
2927 return;
2928
2929 /* request the reset, and let the hclge to determine
2930 * which reset level should be done
2931 */
2932 if (h->ae_algo->ops->reset_event)
2933 h->ae_algo->ops->reset_event(h->pdev, h);
2934 }
2935
2936 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2937 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2938 u16 rxq_index, u32 flow_id)
2939 {
2940 struct hnae3_handle *h = hns3_get_handle(dev);
2941 struct flow_keys fkeys;
2942
2943 if (!h->ae_algo->ops->add_arfs_entry)
2944 return -EOPNOTSUPP;
2945
2946 if (skb->encapsulation)
2947 return -EPROTONOSUPPORT;
2948
2949 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2950 return -EPROTONOSUPPORT;
2951
2952 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2953 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2954 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2955 fkeys.basic.ip_proto != IPPROTO_UDP))
2956 return -EPROTONOSUPPORT;
2957
2958 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2959 }
2960 #endif
2961
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2962 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2963 struct ifla_vf_info *ivf)
2964 {
2965 struct hnae3_handle *h = hns3_get_handle(ndev);
2966
2967 if (!h->ae_algo->ops->get_vf_config)
2968 return -EOPNOTSUPP;
2969
2970 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2971 }
2972
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2973 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2974 int link_state)
2975 {
2976 struct hnae3_handle *h = hns3_get_handle(ndev);
2977
2978 if (!h->ae_algo->ops->set_vf_link_state)
2979 return -EOPNOTSUPP;
2980
2981 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2982 }
2983
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2984 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2985 int min_tx_rate, int max_tx_rate)
2986 {
2987 struct hnae3_handle *h = hns3_get_handle(ndev);
2988
2989 if (!h->ae_algo->ops->set_vf_rate)
2990 return -EOPNOTSUPP;
2991
2992 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2993 false);
2994 }
2995
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2996 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2997 {
2998 struct hnae3_handle *h = hns3_get_handle(netdev);
2999 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
3000
3001 if (!h->ae_algo->ops->set_vf_mac)
3002 return -EOPNOTSUPP;
3003
3004 if (is_multicast_ether_addr(mac)) {
3005 hnae3_format_mac_addr(format_mac_addr, mac);
3006 netdev_err(netdev,
3007 "Invalid MAC:%s specified. Could not set MAC\n",
3008 format_mac_addr);
3009 return -EINVAL;
3010 }
3011
3012 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
3013 }
3014
3015 #define HNS3_INVALID_DSCP 0xff
3016 #define HNS3_DSCP_SHIFT 2
3017
hns3_get_skb_dscp(struct sk_buff * skb)3018 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
3019 {
3020 __be16 protocol = skb->protocol;
3021 u8 dscp = HNS3_INVALID_DSCP;
3022
3023 if (protocol == htons(ETH_P_8021Q))
3024 protocol = vlan_get_protocol(skb);
3025
3026 if (protocol == htons(ETH_P_IP))
3027 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
3028 else if (protocol == htons(ETH_P_IPV6))
3029 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
3030
3031 return dscp;
3032 }
3033
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3034 static u16 hns3_nic_select_queue(struct net_device *netdev,
3035 struct sk_buff *skb,
3036 struct net_device *sb_dev)
3037 {
3038 struct hnae3_handle *h = hns3_get_handle(netdev);
3039 u8 dscp;
3040
3041 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3042 !h->ae_algo->ops->get_dscp_prio)
3043 goto out;
3044
3045 dscp = hns3_get_skb_dscp(skb);
3046 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3047 goto out;
3048
3049 skb->priority = h->kinfo.dscp_prio[dscp];
3050 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3051 skb->priority = 0;
3052
3053 out:
3054 return netdev_pick_tx(netdev, skb, sb_dev);
3055 }
3056
3057 static const struct net_device_ops hns3_nic_netdev_ops = {
3058 .ndo_open = hns3_nic_net_open,
3059 .ndo_stop = hns3_nic_net_stop,
3060 .ndo_start_xmit = hns3_nic_net_xmit,
3061 .ndo_tx_timeout = hns3_nic_net_timeout,
3062 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3063 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3064 .ndo_change_mtu = hns3_nic_change_mtu,
3065 .ndo_set_features = hns3_nic_set_features,
3066 .ndo_features_check = hns3_features_check,
3067 .ndo_get_stats64 = hns3_nic_get_stats64,
3068 .ndo_setup_tc = hns3_nic_setup_tc,
3069 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3070 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3071 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3072 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3073 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3074 .ndo_set_vf_trust = hns3_set_vf_trust,
3075 #ifdef CONFIG_RFS_ACCEL
3076 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3077 #endif
3078 .ndo_get_vf_config = hns3_nic_get_vf_config,
3079 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3080 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3081 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3082 .ndo_select_queue = hns3_nic_select_queue,
3083 .ndo_hwtstamp_get = hns3_nic_hwtstamp_get,
3084 .ndo_hwtstamp_set = hns3_nic_hwtstamp_set,
3085 };
3086
hns3_is_phys_func(struct pci_dev * pdev)3087 bool hns3_is_phys_func(struct pci_dev *pdev)
3088 {
3089 u32 dev_id = pdev->device;
3090
3091 switch (dev_id) {
3092 case HNAE3_DEV_ID_GE:
3093 case HNAE3_DEV_ID_25GE:
3094 case HNAE3_DEV_ID_25GE_RDMA:
3095 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3096 case HNAE3_DEV_ID_50GE_RDMA:
3097 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3098 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3099 case HNAE3_DEV_ID_200G_RDMA:
3100 return true;
3101 case HNAE3_DEV_ID_VF:
3102 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3103 return false;
3104 default:
3105 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3106 dev_id);
3107 }
3108
3109 return false;
3110 }
3111
hns3_disable_sriov(struct pci_dev * pdev)3112 static void hns3_disable_sriov(struct pci_dev *pdev)
3113 {
3114 /* If our VFs are assigned we cannot shut down SR-IOV
3115 * without causing issues, so just leave the hardware
3116 * available but disabled
3117 */
3118 if (pci_vfs_assigned(pdev)) {
3119 dev_warn(&pdev->dev,
3120 "disabling driver while VFs are assigned\n");
3121 return;
3122 }
3123
3124 pci_disable_sriov(pdev);
3125 }
3126
3127 /* hns3_probe - Device initialization routine
3128 * @pdev: PCI device information struct
3129 * @ent: entry in hns3_pci_tbl
3130 *
3131 * hns3_probe initializes a PF identified by a pci_dev structure.
3132 * The OS initialization, configuring of the PF private structure,
3133 * and a hardware reset occur.
3134 *
3135 * Returns 0 on success, negative on failure
3136 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3137 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3138 {
3139 struct hnae3_ae_dev *ae_dev;
3140 int ret;
3141
3142 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3143 if (!ae_dev)
3144 return -ENOMEM;
3145
3146 ae_dev->pdev = pdev;
3147 ae_dev->flag = ent->driver_data;
3148 pci_set_drvdata(pdev, ae_dev);
3149
3150 ret = hnae3_register_ae_dev(ae_dev);
3151 if (ret)
3152 pci_set_drvdata(pdev, NULL);
3153
3154 return ret;
3155 }
3156
3157 /**
3158 * hns3_clean_vf_config
3159 * @pdev: pointer to a pci_dev structure
3160 * @num_vfs: number of VFs allocated
3161 *
3162 * Clean residual vf config after disable sriov
3163 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3164 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3165 {
3166 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3167
3168 if (ae_dev->ops->clean_vf_config)
3169 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3170 }
3171
3172 /* hns3_remove - Device removal routine
3173 * @pdev: PCI device information struct
3174 */
hns3_remove(struct pci_dev * pdev)3175 static void hns3_remove(struct pci_dev *pdev)
3176 {
3177 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3178
3179 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3180 hns3_disable_sriov(pdev);
3181
3182 hnae3_unregister_ae_dev(ae_dev);
3183 pci_set_drvdata(pdev, NULL);
3184 }
3185
3186 /**
3187 * hns3_pci_sriov_configure
3188 * @pdev: pointer to a pci_dev structure
3189 * @num_vfs: number of VFs to allocate
3190 *
3191 * Enable or change the number of VFs. Called when the user updates the number
3192 * of VFs in sysfs.
3193 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3194 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3195 {
3196 int ret;
3197
3198 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3199 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3200 return -EINVAL;
3201 }
3202
3203 if (num_vfs) {
3204 ret = pci_enable_sriov(pdev, num_vfs);
3205 if (ret)
3206 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3207 else
3208 return num_vfs;
3209 } else if (!pci_vfs_assigned(pdev)) {
3210 int num_vfs_pre = pci_num_vf(pdev);
3211
3212 pci_disable_sriov(pdev);
3213 hns3_clean_vf_config(pdev, num_vfs_pre);
3214 } else {
3215 dev_warn(&pdev->dev,
3216 "Unable to free VFs because some are assigned to VMs.\n");
3217 }
3218
3219 return 0;
3220 }
3221
hns3_shutdown(struct pci_dev * pdev)3222 static void hns3_shutdown(struct pci_dev *pdev)
3223 {
3224 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3225
3226 hnae3_unregister_ae_dev(ae_dev);
3227 pci_set_drvdata(pdev, NULL);
3228
3229 if (system_state == SYSTEM_POWER_OFF)
3230 pci_set_power_state(pdev, PCI_D3hot);
3231 }
3232
hns3_suspend(struct device * dev)3233 static int __maybe_unused hns3_suspend(struct device *dev)
3234 {
3235 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3236
3237 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3238 dev_info(dev, "Begin to suspend.\n");
3239 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3240 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3241 }
3242
3243 return 0;
3244 }
3245
hns3_resume(struct device * dev)3246 static int __maybe_unused hns3_resume(struct device *dev)
3247 {
3248 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3249
3250 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3251 dev_info(dev, "Begin to resume.\n");
3252 if (ae_dev->ops && ae_dev->ops->reset_done)
3253 ae_dev->ops->reset_done(ae_dev);
3254 }
3255
3256 return 0;
3257 }
3258
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3259 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3260 pci_channel_state_t state)
3261 {
3262 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3263 pci_ers_result_t ret;
3264
3265 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3266
3267 if (state == pci_channel_io_perm_failure)
3268 return PCI_ERS_RESULT_DISCONNECT;
3269
3270 if (!ae_dev || !ae_dev->ops) {
3271 dev_err(&pdev->dev,
3272 "Can't recover - error happened before device initialized\n");
3273 return PCI_ERS_RESULT_NONE;
3274 }
3275
3276 if (ae_dev->ops->handle_hw_ras_error)
3277 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3278 else
3279 return PCI_ERS_RESULT_NONE;
3280
3281 return ret;
3282 }
3283
hns3_slot_reset(struct pci_dev * pdev)3284 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3285 {
3286 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3287 const struct hnae3_ae_ops *ops;
3288 enum hnae3_reset_type reset_type;
3289 struct device *dev = &pdev->dev;
3290
3291 if (!ae_dev || !ae_dev->ops)
3292 return PCI_ERS_RESULT_NONE;
3293
3294 ops = ae_dev->ops;
3295 /* request the reset */
3296 if (ops->reset_event && ops->get_reset_level &&
3297 ops->set_default_reset_request) {
3298 if (ae_dev->hw_err_reset_req) {
3299 reset_type = ops->get_reset_level(ae_dev,
3300 &ae_dev->hw_err_reset_req);
3301 ops->set_default_reset_request(ae_dev, reset_type);
3302 dev_info(dev, "requesting reset due to PCI error\n");
3303 ops->reset_event(pdev, NULL);
3304 }
3305
3306 return PCI_ERS_RESULT_RECOVERED;
3307 }
3308
3309 return PCI_ERS_RESULT_DISCONNECT;
3310 }
3311
hns3_reset_prepare(struct pci_dev * pdev)3312 static void hns3_reset_prepare(struct pci_dev *pdev)
3313 {
3314 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3315
3316 dev_info(&pdev->dev, "FLR prepare\n");
3317 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3318 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3319 }
3320
hns3_reset_done(struct pci_dev * pdev)3321 static void hns3_reset_done(struct pci_dev *pdev)
3322 {
3323 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3324
3325 dev_info(&pdev->dev, "FLR done\n");
3326 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3327 ae_dev->ops->reset_done(ae_dev);
3328 }
3329
3330 static const struct pci_error_handlers hns3_err_handler = {
3331 .error_detected = hns3_error_detected,
3332 .slot_reset = hns3_slot_reset,
3333 .reset_prepare = hns3_reset_prepare,
3334 .reset_done = hns3_reset_done,
3335 };
3336
3337 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3338
3339 static struct pci_driver hns3_driver = {
3340 .name = hns3_driver_name,
3341 .id_table = hns3_pci_tbl,
3342 .probe = hns3_probe,
3343 .remove = hns3_remove,
3344 .shutdown = hns3_shutdown,
3345 .driver.pm = &hns3_pm_ops,
3346 .sriov_configure = hns3_pci_sriov_configure,
3347 .err_handler = &hns3_err_handler,
3348 };
3349
3350 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3351 static void hns3_set_default_feature(struct net_device *netdev)
3352 {
3353 struct hnae3_handle *h = hns3_get_handle(netdev);
3354 struct pci_dev *pdev = h->pdev;
3355 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3356
3357 netdev->priv_flags |= IFF_UNICAST_FLT;
3358
3359 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3360 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3361 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3362 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3363 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3364 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3365
3366 if (hnae3_ae_dev_gro_supported(ae_dev))
3367 netdev->features |= NETIF_F_GRO_HW;
3368
3369 if (hnae3_ae_dev_fd_supported(ae_dev))
3370 netdev->features |= NETIF_F_NTUPLE;
3371
3372 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3373 netdev->features |= NETIF_F_GSO_UDP_L4;
3374
3375 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3376 netdev->features |= NETIF_F_HW_CSUM;
3377 else
3378 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3379
3380 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3381 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3382
3383 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3384 netdev->features |= NETIF_F_HW_TC;
3385
3386 netdev->hw_features |= netdev->features;
3387 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3388 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3389
3390 netdev->vlan_features |= netdev->features &
3391 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3392 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3393 NETIF_F_HW_TC);
3394
3395 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3396
3397 /* The device_version V3 hardware can't offload the checksum for IP in
3398 * GRE packets, but can do it for NvGRE. So default to disable the
3399 * checksum and GSO offload for GRE.
3400 */
3401 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3402 netdev->features &= ~NETIF_F_GSO_GRE;
3403 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3404 }
3405 }
3406
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3407 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3408 struct hns3_desc_cb *cb)
3409 {
3410 unsigned int order = hns3_page_order(ring);
3411 struct page *p;
3412
3413 if (ring->page_pool) {
3414 p = page_pool_dev_alloc_frag(ring->page_pool,
3415 &cb->page_offset,
3416 hns3_buf_size(ring));
3417 if (unlikely(!p))
3418 return -ENOMEM;
3419
3420 cb->priv = p;
3421 cb->buf = page_address(p);
3422 cb->dma = page_pool_get_dma_addr(p);
3423 cb->type = DESC_TYPE_PP_FRAG;
3424 cb->reuse_flag = 0;
3425 return 0;
3426 }
3427
3428 p = dev_alloc_pages(order);
3429 if (!p)
3430 return -ENOMEM;
3431
3432 cb->priv = p;
3433 cb->page_offset = 0;
3434 cb->reuse_flag = 0;
3435 cb->buf = page_address(p);
3436 cb->length = hns3_page_size(ring);
3437 cb->type = DESC_TYPE_PAGE;
3438 page_ref_add(p, USHRT_MAX - 1);
3439 cb->pagecnt_bias = USHRT_MAX;
3440
3441 return 0;
3442 }
3443
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3444 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3445 struct hns3_desc_cb *cb, int budget)
3446 {
3447 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3448 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3449 napi_consume_skb(cb->priv, budget);
3450 else if (!HNAE3_IS_TX_RING(ring)) {
3451 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3452 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3453 else if (cb->type & DESC_TYPE_PP_FRAG)
3454 page_pool_put_full_page(ring->page_pool, cb->priv,
3455 false);
3456 }
3457 memset(cb, 0, sizeof(*cb));
3458 }
3459
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3460 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3461 {
3462 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3463 cb->length, ring_to_dma_dir(ring));
3464
3465 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3466 return -EIO;
3467
3468 return 0;
3469 }
3470
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3471 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3472 struct hns3_desc_cb *cb)
3473 {
3474 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3475 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3476 ring_to_dma_dir(ring));
3477 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3478 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3479 ring_to_dma_dir(ring));
3480 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3481 DESC_TYPE_SGL_SKB))
3482 hns3_tx_spare_reclaim_cb(ring, cb);
3483 }
3484
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3485 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3486 {
3487 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3488 ring->desc[i].addr = 0;
3489 ring->desc_cb[i].refill = 0;
3490 }
3491
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3492 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3493 int budget)
3494 {
3495 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3496
3497 if (!ring->desc_cb[i].dma)
3498 return;
3499
3500 hns3_buffer_detach(ring, i);
3501 hns3_free_buffer(ring, cb, budget);
3502 }
3503
hns3_free_buffers(struct hns3_enet_ring * ring)3504 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3505 {
3506 int i;
3507
3508 for (i = 0; i < ring->desc_num; i++)
3509 hns3_free_buffer_detach(ring, i, 0);
3510 }
3511
3512 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3513 static void hns3_free_desc(struct hns3_enet_ring *ring)
3514 {
3515 int size = ring->desc_num * sizeof(ring->desc[0]);
3516
3517 hns3_free_buffers(ring);
3518
3519 if (ring->desc) {
3520 dma_free_coherent(ring_to_dev(ring), size,
3521 ring->desc, ring->desc_dma_addr);
3522 ring->desc = NULL;
3523 }
3524 }
3525
hns3_alloc_desc(struct hns3_enet_ring * ring)3526 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3527 {
3528 int size = ring->desc_num * sizeof(ring->desc[0]);
3529
3530 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3531 &ring->desc_dma_addr, GFP_KERNEL);
3532 if (!ring->desc)
3533 return -ENOMEM;
3534
3535 return 0;
3536 }
3537
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3538 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3539 struct hns3_desc_cb *cb)
3540 {
3541 int ret;
3542
3543 ret = hns3_alloc_buffer(ring, cb);
3544 if (ret || ring->page_pool)
3545 goto out;
3546
3547 ret = hns3_map_buffer(ring, cb);
3548 if (ret)
3549 goto out_with_buf;
3550
3551 return 0;
3552
3553 out_with_buf:
3554 hns3_free_buffer(ring, cb, 0);
3555 out:
3556 return ret;
3557 }
3558
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3559 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3560 {
3561 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3562
3563 if (ret)
3564 return ret;
3565
3566 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3567 ring->desc_cb[i].page_offset);
3568 ring->desc_cb[i].refill = 1;
3569
3570 return 0;
3571 }
3572
3573 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3574 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3575 {
3576 int i, j, ret;
3577
3578 for (i = 0; i < ring->desc_num; i++) {
3579 ret = hns3_alloc_and_attach_buffer(ring, i);
3580 if (ret)
3581 goto out_buffer_fail;
3582
3583 if (!(i % HNS3_RESCHED_BD_NUM))
3584 cond_resched();
3585 }
3586
3587 return 0;
3588
3589 out_buffer_fail:
3590 for (j = i - 1; j >= 0; j--)
3591 hns3_free_buffer_detach(ring, j, 0);
3592 return ret;
3593 }
3594
3595 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3596 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3597 struct hns3_desc_cb *res_cb)
3598 {
3599 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3600 ring->desc_cb[i] = *res_cb;
3601 ring->desc_cb[i].refill = 1;
3602 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3603 ring->desc_cb[i].page_offset);
3604 ring->desc[i].rx.bd_base_info = 0;
3605 }
3606
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3607 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3608 {
3609 ring->desc_cb[i].reuse_flag = 0;
3610 ring->desc_cb[i].refill = 1;
3611 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3612 ring->desc_cb[i].page_offset);
3613 ring->desc[i].rx.bd_base_info = 0;
3614
3615 dma_sync_single_for_device(ring_to_dev(ring),
3616 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3617 hns3_buf_size(ring),
3618 DMA_FROM_DEVICE);
3619 }
3620
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3621 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3622 int *bytes, int *pkts, int budget)
3623 {
3624 /* This smp_load_acquire() pairs with smp_store_release() in
3625 * hns3_tx_doorbell().
3626 */
3627 int ltu = smp_load_acquire(&ring->last_to_use);
3628 int ntc = ring->next_to_clean;
3629 struct hns3_desc_cb *desc_cb;
3630 bool reclaimed = false;
3631 struct hns3_desc *desc;
3632
3633 while (ltu != ntc) {
3634 desc = &ring->desc[ntc];
3635
3636 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3637 BIT(HNS3_TXD_VLD_B))
3638 break;
3639
3640 desc_cb = &ring->desc_cb[ntc];
3641
3642 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3643 DESC_TYPE_BOUNCE_HEAD |
3644 DESC_TYPE_SGL_SKB)) {
3645 (*pkts)++;
3646 (*bytes) += desc_cb->send_bytes;
3647 }
3648
3649 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3650 hns3_free_buffer_detach(ring, ntc, budget);
3651
3652 if (++ntc == ring->desc_num)
3653 ntc = 0;
3654
3655 /* Issue prefetch for next Tx descriptor */
3656 prefetch(&ring->desc_cb[ntc]);
3657 reclaimed = true;
3658 }
3659
3660 if (unlikely(!reclaimed))
3661 return false;
3662
3663 /* This smp_store_release() pairs with smp_load_acquire() in
3664 * ring_space called by hns3_nic_net_xmit.
3665 */
3666 smp_store_release(&ring->next_to_clean, ntc);
3667
3668 hns3_tx_spare_update(ring);
3669
3670 return true;
3671 }
3672
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3673 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3674 {
3675 struct net_device *netdev = ring_to_netdev(ring);
3676 struct hns3_nic_priv *priv = netdev_priv(netdev);
3677 struct netdev_queue *dev_queue;
3678 int bytes, pkts;
3679
3680 bytes = 0;
3681 pkts = 0;
3682
3683 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3684 return;
3685
3686 ring->tqp_vector->tx_group.total_bytes += bytes;
3687 ring->tqp_vector->tx_group.total_packets += pkts;
3688
3689 u64_stats_update_begin(&ring->syncp);
3690 ring->stats.tx_bytes += bytes;
3691 ring->stats.tx_pkts += pkts;
3692 u64_stats_update_end(&ring->syncp);
3693
3694 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3695 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3696
3697 if (unlikely(netif_carrier_ok(netdev) &&
3698 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3699 /* Make sure that anybody stopping the queue after this
3700 * sees the new next_to_clean.
3701 */
3702 smp_mb();
3703 if (netif_tx_queue_stopped(dev_queue) &&
3704 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3705 netif_tx_wake_queue(dev_queue);
3706 ring->stats.restart_queue++;
3707 }
3708 }
3709 }
3710
hns3_desc_unused(struct hns3_enet_ring * ring)3711 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3712 {
3713 int ntc = ring->next_to_clean;
3714 int ntu = ring->next_to_use;
3715
3716 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3717 return ring->desc_num;
3718
3719 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3720 }
3721
3722 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3723 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3724 int cleand_count)
3725 {
3726 struct hns3_desc_cb *desc_cb;
3727 struct hns3_desc_cb res_cbs;
3728 int i, ret;
3729
3730 for (i = 0; i < cleand_count; i++) {
3731 desc_cb = &ring->desc_cb[ring->next_to_use];
3732 if (desc_cb->reuse_flag) {
3733 hns3_ring_stats_update(ring, reuse_pg_cnt);
3734
3735 hns3_reuse_buffer(ring, ring->next_to_use);
3736 } else {
3737 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3738 if (ret) {
3739 hns3_ring_stats_update(ring, sw_err_cnt);
3740
3741 hns3_rl_err(ring_to_netdev(ring),
3742 "alloc rx buffer failed: %d\n",
3743 ret);
3744
3745 writel(i, ring->tqp->io_base +
3746 HNS3_RING_RX_RING_HEAD_REG);
3747 return true;
3748 }
3749 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3750
3751 hns3_ring_stats_update(ring, non_reuse_pg);
3752 }
3753
3754 ring_ptr_move_fw(ring, next_to_use);
3755 }
3756
3757 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3758 return false;
3759 }
3760
hns3_can_reuse_page(struct hns3_desc_cb * cb)3761 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3762 {
3763 return page_count(cb->priv) == cb->pagecnt_bias;
3764 }
3765
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3766 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3767 struct hns3_enet_ring *ring,
3768 int pull_len,
3769 struct hns3_desc_cb *desc_cb)
3770 {
3771 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3772 u32 frag_offset = desc_cb->page_offset + pull_len;
3773 int size = le16_to_cpu(desc->rx.size);
3774 u32 frag_size = size - pull_len;
3775 void *frag = napi_alloc_frag(frag_size);
3776
3777 if (unlikely(!frag)) {
3778 hns3_ring_stats_update(ring, frag_alloc_err);
3779
3780 hns3_rl_err(ring_to_netdev(ring),
3781 "failed to allocate rx frag\n");
3782 return -ENOMEM;
3783 }
3784
3785 desc_cb->reuse_flag = 1;
3786 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3787 skb_add_rx_frag(skb, i, virt_to_page(frag),
3788 offset_in_page(frag), frag_size, frag_size);
3789
3790 hns3_ring_stats_update(ring, frag_alloc);
3791 return 0;
3792 }
3793
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3794 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3795 struct hns3_enet_ring *ring, int pull_len,
3796 struct hns3_desc_cb *desc_cb)
3797 {
3798 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3799 u32 frag_offset = desc_cb->page_offset + pull_len;
3800 int size = le16_to_cpu(desc->rx.size);
3801 u32 truesize = hns3_buf_size(ring);
3802 u32 frag_size = size - pull_len;
3803 int ret = 0;
3804 bool reused;
3805
3806 if (ring->page_pool) {
3807 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3808 frag_size, truesize);
3809 return;
3810 }
3811
3812 /* Avoid re-using remote or pfmem page */
3813 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3814 goto out;
3815
3816 reused = hns3_can_reuse_page(desc_cb);
3817
3818 /* Rx page can be reused when:
3819 * 1. Rx page is only owned by the driver when page_offset
3820 * is zero, which means 0 @ truesize will be used by
3821 * stack after skb_add_rx_frag() is called, and the rest
3822 * of rx page can be reused by driver.
3823 * Or
3824 * 2. Rx page is only owned by the driver when page_offset
3825 * is non-zero, which means page_offset @ truesize will
3826 * be used by stack after skb_add_rx_frag() is called,
3827 * and 0 @ truesize can be reused by driver.
3828 */
3829 if ((!desc_cb->page_offset && reused) ||
3830 ((desc_cb->page_offset + truesize + truesize) <=
3831 hns3_page_size(ring) && desc_cb->page_offset)) {
3832 desc_cb->page_offset += truesize;
3833 desc_cb->reuse_flag = 1;
3834 } else if (desc_cb->page_offset && reused) {
3835 desc_cb->page_offset = 0;
3836 desc_cb->reuse_flag = 1;
3837 } else if (frag_size <= ring->rx_copybreak) {
3838 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3839 if (!ret)
3840 return;
3841 }
3842
3843 out:
3844 desc_cb->pagecnt_bias--;
3845
3846 if (unlikely(!desc_cb->pagecnt_bias)) {
3847 page_ref_add(desc_cb->priv, USHRT_MAX);
3848 desc_cb->pagecnt_bias = USHRT_MAX;
3849 }
3850
3851 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3852 frag_size, truesize);
3853
3854 if (unlikely(!desc_cb->reuse_flag))
3855 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3856 }
3857
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3858 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3859 {
3860 __be16 type = skb->protocol;
3861 struct tcphdr *th;
3862 u32 depth = 0;
3863
3864 while (eth_type_vlan(type)) {
3865 struct vlan_hdr *vh;
3866
3867 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3868 return -EFAULT;
3869
3870 vh = (struct vlan_hdr *)(skb->data + depth);
3871 type = vh->h_vlan_encapsulated_proto;
3872 depth += VLAN_HLEN;
3873 }
3874
3875 skb_set_network_header(skb, depth);
3876
3877 if (type == htons(ETH_P_IP)) {
3878 const struct iphdr *iph = ip_hdr(skb);
3879
3880 depth += sizeof(struct iphdr);
3881 skb_set_transport_header(skb, depth);
3882 th = tcp_hdr(skb);
3883 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3884 iph->daddr, 0);
3885 } else if (type == htons(ETH_P_IPV6)) {
3886 const struct ipv6hdr *iph = ipv6_hdr(skb);
3887
3888 depth += sizeof(struct ipv6hdr);
3889 skb_set_transport_header(skb, depth);
3890 th = tcp_hdr(skb);
3891 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3892 &iph->daddr, 0);
3893 } else {
3894 hns3_rl_err(skb->dev,
3895 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3896 be16_to_cpu(type), depth);
3897 return -EFAULT;
3898 }
3899
3900 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3901 if (th->cwr)
3902 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3903
3904 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3905 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3906
3907 skb->csum_start = (unsigned char *)th - skb->head;
3908 skb->csum_offset = offsetof(struct tcphdr, check);
3909 skb->ip_summed = CHECKSUM_PARTIAL;
3910
3911 trace_hns3_gro(skb);
3912
3913 return 0;
3914 }
3915
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3916 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3917 struct sk_buff *skb, u32 ptype, u16 csum)
3918 {
3919 if (ptype == HNS3_INVALID_PTYPE ||
3920 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3921 return;
3922
3923 hns3_ring_stats_update(ring, csum_complete);
3924 skb->ip_summed = CHECKSUM_COMPLETE;
3925 skb->csum = csum_unfold((__force __sum16)csum);
3926 }
3927
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3928 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3929 u32 ol_info, u32 ptype)
3930 {
3931 int l3_type, l4_type;
3932 int ol4_type;
3933
3934 if (ptype != HNS3_INVALID_PTYPE) {
3935 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3936 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3937
3938 return;
3939 }
3940
3941 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3942 HNS3_RXD_OL4ID_S);
3943 switch (ol4_type) {
3944 case HNS3_OL4_TYPE_MAC_IN_UDP:
3945 case HNS3_OL4_TYPE_NVGRE:
3946 skb->csum_level = 1;
3947 fallthrough;
3948 case HNS3_OL4_TYPE_NO_TUN:
3949 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3950 HNS3_RXD_L3ID_S);
3951 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3952 HNS3_RXD_L4ID_S);
3953 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3954 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3955 l3_type == HNS3_L3_TYPE_IPV6) &&
3956 (l4_type == HNS3_L4_TYPE_UDP ||
3957 l4_type == HNS3_L4_TYPE_TCP ||
3958 l4_type == HNS3_L4_TYPE_SCTP))
3959 skb->ip_summed = CHECKSUM_UNNECESSARY;
3960 break;
3961 default:
3962 break;
3963 }
3964 }
3965
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3966 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3967 u32 l234info, u32 bd_base_info, u32 ol_info,
3968 u16 csum)
3969 {
3970 struct net_device *netdev = ring_to_netdev(ring);
3971 struct hns3_nic_priv *priv = netdev_priv(netdev);
3972 u32 ptype = HNS3_INVALID_PTYPE;
3973
3974 skb->ip_summed = CHECKSUM_NONE;
3975
3976 skb_checksum_none_assert(skb);
3977
3978 if (!(netdev->features & NETIF_F_RXCSUM))
3979 return;
3980
3981 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3982 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3983 HNS3_RXD_PTYPE_S);
3984
3985 hns3_checksum_complete(ring, skb, ptype, csum);
3986
3987 /* check if hardware has done checksum */
3988 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3989 return;
3990
3991 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3992 BIT(HNS3_RXD_OL3E_B) |
3993 BIT(HNS3_RXD_OL4E_B)))) {
3994 skb->ip_summed = CHECKSUM_NONE;
3995 hns3_ring_stats_update(ring, l3l4_csum_err);
3996
3997 return;
3998 }
3999
4000 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
4001 }
4002
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)4003 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
4004 {
4005 if (skb_has_frag_list(skb))
4006 napi_gro_flush(&ring->tqp_vector->napi, false);
4007
4008 napi_gro_receive(&ring->tqp_vector->napi, skb);
4009 }
4010
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)4011 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
4012 struct hns3_desc *desc, u32 l234info,
4013 u16 *vlan_tag)
4014 {
4015 struct hnae3_handle *handle = ring->tqp->handle;
4016 struct pci_dev *pdev = ring->tqp->handle->pdev;
4017 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4018
4019 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
4020 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4021 if (!(*vlan_tag & VLAN_VID_MASK))
4022 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4023
4024 return (*vlan_tag != 0);
4025 }
4026
4027 #define HNS3_STRP_OUTER_VLAN 0x1
4028 #define HNS3_STRP_INNER_VLAN 0x2
4029 #define HNS3_STRP_BOTH 0x3
4030
4031 /* Hardware always insert VLAN tag into RX descriptor when
4032 * remove the tag from packet, driver needs to determine
4033 * reporting which tag to stack.
4034 */
4035 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4036 HNS3_RXD_STRP_TAGP_S)) {
4037 case HNS3_STRP_OUTER_VLAN:
4038 if (handle->port_base_vlan_state !=
4039 HNAE3_PORT_BASE_VLAN_DISABLE)
4040 return false;
4041
4042 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4043 return true;
4044 case HNS3_STRP_INNER_VLAN:
4045 if (handle->port_base_vlan_state !=
4046 HNAE3_PORT_BASE_VLAN_DISABLE)
4047 return false;
4048
4049 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4050 return true;
4051 case HNS3_STRP_BOTH:
4052 if (handle->port_base_vlan_state ==
4053 HNAE3_PORT_BASE_VLAN_DISABLE)
4054 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4055 else
4056 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4057
4058 return true;
4059 default:
4060 return false;
4061 }
4062 }
4063
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4064 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4065 {
4066 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4067 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4068 ring->desc_cb[ring->next_to_clean].refill = 0;
4069 ring->next_to_clean += 1;
4070
4071 if (unlikely(ring->next_to_clean == ring->desc_num))
4072 ring->next_to_clean = 0;
4073 }
4074
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4075 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4076 unsigned char *va)
4077 {
4078 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4079 struct net_device *netdev = ring_to_netdev(ring);
4080 struct sk_buff *skb;
4081
4082 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4083 skb = ring->skb;
4084 if (unlikely(!skb)) {
4085 hns3_rl_err(netdev, "alloc rx skb fail\n");
4086 hns3_ring_stats_update(ring, sw_err_cnt);
4087
4088 return -ENOMEM;
4089 }
4090
4091 trace_hns3_rx_desc(ring);
4092 prefetchw(skb->data);
4093
4094 ring->pending_buf = 1;
4095 ring->frag_num = 0;
4096 ring->tail_skb = NULL;
4097 if (length <= HNS3_RX_HEAD_SIZE) {
4098 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4099
4100 /* We can reuse buffer as-is, just make sure it is reusable */
4101 if (dev_page_is_reusable(desc_cb->priv))
4102 desc_cb->reuse_flag = 1;
4103 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4104 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4105 false);
4106 else /* This page cannot be reused so discard it */
4107 __page_frag_cache_drain(desc_cb->priv,
4108 desc_cb->pagecnt_bias);
4109
4110 hns3_rx_ring_move_fw(ring);
4111 return 0;
4112 }
4113
4114 if (ring->page_pool)
4115 skb_mark_for_recycle(skb);
4116
4117 hns3_ring_stats_update(ring, seg_pkt_cnt);
4118
4119 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4120 __skb_put(skb, ring->pull_len);
4121 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4122 desc_cb);
4123 hns3_rx_ring_move_fw(ring);
4124
4125 return 0;
4126 }
4127
hns3_add_frag(struct hns3_enet_ring * ring)4128 static int hns3_add_frag(struct hns3_enet_ring *ring)
4129 {
4130 struct sk_buff *skb = ring->skb;
4131 struct sk_buff *head_skb = skb;
4132 struct sk_buff *new_skb;
4133 struct hns3_desc_cb *desc_cb;
4134 struct hns3_desc *desc;
4135 u32 bd_base_info;
4136
4137 do {
4138 desc = &ring->desc[ring->next_to_clean];
4139 desc_cb = &ring->desc_cb[ring->next_to_clean];
4140 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4141 /* make sure HW write desc complete */
4142 dma_rmb();
4143 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4144 return -ENXIO;
4145
4146 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4147 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4148 if (unlikely(!new_skb)) {
4149 hns3_rl_err(ring_to_netdev(ring),
4150 "alloc rx fraglist skb fail\n");
4151 return -ENXIO;
4152 }
4153
4154 if (ring->page_pool)
4155 skb_mark_for_recycle(new_skb);
4156
4157 ring->frag_num = 0;
4158
4159 if (ring->tail_skb) {
4160 ring->tail_skb->next = new_skb;
4161 ring->tail_skb = new_skb;
4162 } else {
4163 skb_shinfo(skb)->frag_list = new_skb;
4164 ring->tail_skb = new_skb;
4165 }
4166 }
4167
4168 if (ring->tail_skb) {
4169 head_skb->truesize += hns3_buf_size(ring);
4170 head_skb->data_len += le16_to_cpu(desc->rx.size);
4171 head_skb->len += le16_to_cpu(desc->rx.size);
4172 skb = ring->tail_skb;
4173 }
4174
4175 dma_sync_single_for_cpu(ring_to_dev(ring),
4176 desc_cb->dma + desc_cb->page_offset,
4177 hns3_buf_size(ring),
4178 DMA_FROM_DEVICE);
4179
4180 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4181 trace_hns3_rx_desc(ring);
4182 hns3_rx_ring_move_fw(ring);
4183 ring->pending_buf++;
4184 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4185
4186 return 0;
4187 }
4188
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4189 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4190 struct sk_buff *skb, u32 l234info,
4191 u32 bd_base_info, u32 ol_info, u16 csum)
4192 {
4193 struct net_device *netdev = ring_to_netdev(ring);
4194 struct hns3_nic_priv *priv = netdev_priv(netdev);
4195 u32 l3_type;
4196
4197 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4198 HNS3_RXD_GRO_SIZE_M,
4199 HNS3_RXD_GRO_SIZE_S);
4200 /* if there is no HW GRO, do not set gro params */
4201 if (!skb_shinfo(skb)->gso_size) {
4202 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4203 csum);
4204 return 0;
4205 }
4206
4207 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4208 HNS3_RXD_GRO_COUNT_M,
4209 HNS3_RXD_GRO_COUNT_S);
4210
4211 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4212 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4213 HNS3_RXD_PTYPE_S);
4214
4215 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4216 } else {
4217 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4218 HNS3_RXD_L3ID_S);
4219 }
4220
4221 if (l3_type == HNS3_L3_TYPE_IPV4)
4222 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4223 else if (l3_type == HNS3_L3_TYPE_IPV6)
4224 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4225 else
4226 return -EFAULT;
4227
4228 return hns3_gro_complete(skb, l234info);
4229 }
4230
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4231 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4232 struct sk_buff *skb, u32 rss_hash,
4233 u32 l234info, u32 ol_info)
4234 {
4235 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4236 struct net_device *netdev = ring_to_netdev(ring);
4237 struct hns3_nic_priv *priv = netdev_priv(netdev);
4238
4239 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4240 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4241 HNS3_RXD_PTYPE_S);
4242
4243 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4244 } else {
4245 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4246 HNS3_RXD_L3ID_S);
4247 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4248 HNS3_RXD_L4ID_S);
4249
4250 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4251 l3_type == HNS3_L3_TYPE_IPV6) {
4252 if (l4_type == HNS3_L4_TYPE_UDP ||
4253 l4_type == HNS3_L4_TYPE_TCP ||
4254 l4_type == HNS3_L4_TYPE_SCTP)
4255 rss_type = PKT_HASH_TYPE_L4;
4256 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4257 l4_type == HNS3_L4_TYPE_ICMP)
4258 rss_type = PKT_HASH_TYPE_L3;
4259 }
4260 }
4261
4262 skb_set_hash(skb, rss_hash, rss_type);
4263 }
4264
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4265 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4266 struct hns3_desc *desc, struct sk_buff *skb,
4267 u32 bd_base_info)
4268 {
4269 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4270 struct hnae3_handle *h = hns3_get_handle(netdev);
4271 u32 nsec = le32_to_cpu(desc->ts_nsec);
4272 u32 sec = le32_to_cpu(desc->ts_sec);
4273
4274 if (h->ae_algo->ops->get_rx_hwts)
4275 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4276 }
4277 }
4278
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4279 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4280 struct hns3_desc *desc, struct sk_buff *skb,
4281 u32 l234info)
4282 {
4283 struct net_device *netdev = ring_to_netdev(ring);
4284
4285 /* Based on hw strategy, the tag offloaded will be stored at
4286 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4287 * in one layer tag case.
4288 */
4289 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4290 u16 vlan_tag;
4291
4292 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4293 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4294 vlan_tag);
4295 }
4296 }
4297
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4298 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4299 {
4300 struct net_device *netdev = ring_to_netdev(ring);
4301 enum hns3_pkt_l2t_type l2_frame_type;
4302 u32 bd_base_info, l234info, ol_info;
4303 struct hns3_desc *desc;
4304 unsigned int len;
4305 int pre_ntc, ret;
4306 u16 csum;
4307
4308 /* bdinfo handled below is only valid on the last BD of the
4309 * current packet, and ring->next_to_clean indicates the first
4310 * descriptor of next packet, so need - 1 below.
4311 */
4312 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4313 (ring->desc_num - 1);
4314 desc = &ring->desc[pre_ntc];
4315 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4316 l234info = le32_to_cpu(desc->rx.l234_info);
4317 ol_info = le32_to_cpu(desc->rx.ol_info);
4318 csum = le16_to_cpu(desc->csum);
4319
4320 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4321
4322 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4323
4324 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4325 BIT(HNS3_RXD_L2E_B))))) {
4326 u64_stats_update_begin(&ring->syncp);
4327 if (l234info & BIT(HNS3_RXD_L2E_B))
4328 ring->stats.l2_err++;
4329 else
4330 ring->stats.err_pkt_len++;
4331 u64_stats_update_end(&ring->syncp);
4332
4333 return -EFAULT;
4334 }
4335
4336 len = skb->len;
4337
4338 /* Do update ip stack process */
4339 skb->protocol = eth_type_trans(skb, netdev);
4340
4341 /* This is needed in order to enable forwarding support */
4342 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4343 bd_base_info, ol_info, csum);
4344 if (unlikely(ret)) {
4345 hns3_ring_stats_update(ring, rx_err_cnt);
4346 return ret;
4347 }
4348
4349 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4350 HNS3_RXD_DMAC_S);
4351
4352 u64_stats_update_begin(&ring->syncp);
4353 ring->stats.rx_pkts++;
4354 ring->stats.rx_bytes += len;
4355
4356 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4357 ring->stats.rx_multicast++;
4358
4359 u64_stats_update_end(&ring->syncp);
4360
4361 ring->tqp_vector->rx_group.total_bytes += len;
4362
4363 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4364 l234info, ol_info);
4365 return 0;
4366 }
4367
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4368 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4369 {
4370 struct sk_buff *skb = ring->skb;
4371 struct hns3_desc_cb *desc_cb;
4372 struct hns3_desc *desc;
4373 unsigned int length;
4374 u32 bd_base_info;
4375 int ret;
4376
4377 desc = &ring->desc[ring->next_to_clean];
4378 desc_cb = &ring->desc_cb[ring->next_to_clean];
4379
4380 prefetch(desc);
4381
4382 if (!skb) {
4383 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4384 /* Check valid BD */
4385 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4386 return -ENXIO;
4387
4388 dma_rmb();
4389 length = le16_to_cpu(desc->rx.size);
4390
4391 ring->va = desc_cb->buf + desc_cb->page_offset;
4392
4393 dma_sync_single_for_cpu(ring_to_dev(ring),
4394 desc_cb->dma + desc_cb->page_offset,
4395 hns3_buf_size(ring),
4396 DMA_FROM_DEVICE);
4397
4398 /* Prefetch first cache line of first page.
4399 * Idea is to cache few bytes of the header of the packet.
4400 * Our L1 Cache line size is 64B so need to prefetch twice to make
4401 * it 128B. But in actual we can have greater size of caches with
4402 * 128B Level 1 cache lines. In such a case, single fetch would
4403 * suffice to cache in the relevant part of the header.
4404 */
4405 net_prefetch(ring->va);
4406
4407 ret = hns3_alloc_skb(ring, length, ring->va);
4408 skb = ring->skb;
4409
4410 if (ret < 0) /* alloc buffer fail */
4411 return ret;
4412 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4413 ret = hns3_add_frag(ring);
4414 if (ret)
4415 return ret;
4416 }
4417 } else {
4418 ret = hns3_add_frag(ring);
4419 if (ret)
4420 return ret;
4421 }
4422
4423 /* As the head data may be changed when GRO enable, copy
4424 * the head data in after other data rx completed
4425 */
4426 if (skb->len > HNS3_RX_HEAD_SIZE)
4427 memcpy(skb->data, ring->va,
4428 ALIGN(ring->pull_len, sizeof(long)));
4429
4430 ret = hns3_handle_bdinfo(ring, skb);
4431 if (unlikely(ret)) {
4432 dev_kfree_skb_any(skb);
4433 return ret;
4434 }
4435
4436 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4437 return 0;
4438 }
4439
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4440 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4441 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4442 {
4443 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4444 int unused_count = hns3_desc_unused(ring);
4445 bool failure = false;
4446 int recv_pkts = 0;
4447 int err;
4448
4449 unused_count -= ring->pending_buf;
4450
4451 while (recv_pkts < budget) {
4452 /* Reuse or realloc buffers */
4453 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4454 failure = failure ||
4455 hns3_nic_alloc_rx_buffers(ring, unused_count);
4456 unused_count = 0;
4457 }
4458
4459 /* Poll one pkt */
4460 err = hns3_handle_rx_bd(ring);
4461 /* Do not get FE for the packet or failed to alloc skb */
4462 if (unlikely(!ring->skb || err == -ENXIO)) {
4463 goto out;
4464 } else if (likely(!err)) {
4465 rx_fn(ring, ring->skb);
4466 recv_pkts++;
4467 }
4468
4469 unused_count += ring->pending_buf;
4470 ring->skb = NULL;
4471 ring->pending_buf = 0;
4472 }
4473
4474 out:
4475 /* sync head pointer before exiting, since hardware will calculate
4476 * FBD number with head pointer
4477 */
4478 if (unused_count > 0)
4479 failure = failure ||
4480 hns3_nic_alloc_rx_buffers(ring, unused_count);
4481
4482 return failure ? budget : recv_pkts;
4483 }
4484
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4485 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4486 {
4487 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4488 struct dim_sample sample = {};
4489
4490 if (!rx_group->coal.adapt_enable)
4491 return;
4492
4493 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4494 rx_group->total_bytes, &sample);
4495 net_dim(&rx_group->dim, &sample);
4496 }
4497
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4498 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4499 {
4500 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4501 struct dim_sample sample = {};
4502
4503 if (!tx_group->coal.adapt_enable)
4504 return;
4505
4506 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4507 tx_group->total_bytes, &sample);
4508 net_dim(&tx_group->dim, &sample);
4509 }
4510
hns3_nic_common_poll(struct napi_struct * napi,int budget)4511 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4512 {
4513 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4514 struct hns3_enet_ring *ring;
4515 int rx_pkt_total = 0;
4516
4517 struct hns3_enet_tqp_vector *tqp_vector =
4518 container_of(napi, struct hns3_enet_tqp_vector, napi);
4519 bool clean_complete = true;
4520 int rx_budget = budget;
4521
4522 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4523 napi_complete(napi);
4524 return 0;
4525 }
4526
4527 /* Since the actual Tx work is minimal, we can give the Tx a larger
4528 * budget and be more aggressive about cleaning up the Tx descriptors.
4529 */
4530 hns3_for_each_ring(ring, tqp_vector->tx_group)
4531 hns3_clean_tx_ring(ring, budget);
4532
4533 /* make sure rx ring budget not smaller than 1 */
4534 if (tqp_vector->num_tqps > 1)
4535 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4536
4537 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4538 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4539 hns3_rx_skb);
4540 if (rx_cleaned >= rx_budget)
4541 clean_complete = false;
4542
4543 rx_pkt_total += rx_cleaned;
4544 }
4545
4546 tqp_vector->rx_group.total_packets += rx_pkt_total;
4547
4548 if (!clean_complete)
4549 return budget;
4550
4551 if (napi_complete(napi) &&
4552 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4553 hns3_update_rx_int_coalesce(tqp_vector);
4554 hns3_update_tx_int_coalesce(tqp_vector);
4555
4556 hns3_mask_vector_irq(tqp_vector, 1);
4557 }
4558
4559 return rx_pkt_total;
4560 }
4561
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4562 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4563 struct hnae3_ring_chain_node **head,
4564 bool is_tx)
4565 {
4566 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4567 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4568 struct hnae3_ring_chain_node *cur_chain = *head;
4569 struct pci_dev *pdev = tqp_vector->handle->pdev;
4570 struct hnae3_ring_chain_node *chain;
4571 struct hns3_enet_ring *ring;
4572
4573 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4574
4575 if (cur_chain) {
4576 while (cur_chain->next)
4577 cur_chain = cur_chain->next;
4578 }
4579
4580 while (ring) {
4581 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4582 if (!chain)
4583 return -ENOMEM;
4584 if (cur_chain)
4585 cur_chain->next = chain;
4586 else
4587 *head = chain;
4588 chain->tqp_index = ring->tqp->tqp_index;
4589 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4590 bit_value);
4591 hnae3_set_field(chain->int_gl_idx,
4592 HNAE3_RING_GL_IDX_M,
4593 HNAE3_RING_GL_IDX_S, field_value);
4594
4595 cur_chain = chain;
4596
4597 ring = ring->next;
4598 }
4599
4600 return 0;
4601 }
4602
4603 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4604 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4605 {
4606 struct pci_dev *pdev = tqp_vector->handle->pdev;
4607 struct hnae3_ring_chain_node *cur_chain = NULL;
4608 struct hnae3_ring_chain_node *chain;
4609
4610 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4611 goto err_free_chain;
4612
4613 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4614 goto err_free_chain;
4615
4616 return cur_chain;
4617
4618 err_free_chain:
4619 while (cur_chain) {
4620 chain = cur_chain->next;
4621 devm_kfree(&pdev->dev, cur_chain);
4622 cur_chain = chain;
4623 }
4624
4625 return NULL;
4626 }
4627
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4628 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4629 struct hnae3_ring_chain_node *head)
4630 {
4631 struct pci_dev *pdev = tqp_vector->handle->pdev;
4632 struct hnae3_ring_chain_node *chain_tmp, *chain;
4633
4634 chain = head;
4635
4636 while (chain) {
4637 chain_tmp = chain->next;
4638 devm_kfree(&pdev->dev, chain);
4639 chain = chain_tmp;
4640 }
4641 }
4642
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4643 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4644 struct hns3_enet_ring *ring)
4645 {
4646 ring->next = group->ring;
4647 group->ring = ring;
4648
4649 group->count++;
4650 }
4651
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4652 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4653 {
4654 struct pci_dev *pdev = priv->ae_handle->pdev;
4655 struct hns3_enet_tqp_vector *tqp_vector;
4656 int num_vectors = priv->vector_num;
4657 int numa_node;
4658 int vector_i;
4659
4660 numa_node = dev_to_node(&pdev->dev);
4661
4662 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4663 tqp_vector = &priv->tqp_vector[vector_i];
4664 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4665 &tqp_vector->affinity_mask);
4666 }
4667 }
4668
hns3_rx_dim_work(struct work_struct * work)4669 static void hns3_rx_dim_work(struct work_struct *work)
4670 {
4671 struct dim *dim = container_of(work, struct dim, work);
4672 struct hns3_enet_ring_group *group = container_of(dim,
4673 struct hns3_enet_ring_group, dim);
4674 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4675 struct dim_cq_moder cur_moder =
4676 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4677
4678 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4679 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4680
4681 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4682 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4683 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4684 }
4685
4686 dim->state = DIM_START_MEASURE;
4687 }
4688
hns3_tx_dim_work(struct work_struct * work)4689 static void hns3_tx_dim_work(struct work_struct *work)
4690 {
4691 struct dim *dim = container_of(work, struct dim, work);
4692 struct hns3_enet_ring_group *group = container_of(dim,
4693 struct hns3_enet_ring_group, dim);
4694 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4695 struct dim_cq_moder cur_moder =
4696 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4697
4698 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4699 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4700
4701 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4702 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4703 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4704 }
4705
4706 dim->state = DIM_START_MEASURE;
4707 }
4708
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4709 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4710 {
4711 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4712 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4713 }
4714
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4715 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4716 {
4717 struct hnae3_handle *h = priv->ae_handle;
4718 struct hns3_enet_tqp_vector *tqp_vector;
4719 int ret;
4720 int i;
4721
4722 hns3_nic_set_cpumask(priv);
4723
4724 for (i = 0; i < priv->vector_num; i++) {
4725 tqp_vector = &priv->tqp_vector[i];
4726 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4727 tqp_vector->num_tqps = 0;
4728 hns3_nic_init_dim(tqp_vector);
4729 }
4730
4731 for (i = 0; i < h->kinfo.num_tqps; i++) {
4732 u16 vector_i = i % priv->vector_num;
4733 u16 tqp_num = h->kinfo.num_tqps;
4734
4735 tqp_vector = &priv->tqp_vector[vector_i];
4736
4737 hns3_add_ring_to_group(&tqp_vector->tx_group,
4738 &priv->ring[i]);
4739
4740 hns3_add_ring_to_group(&tqp_vector->rx_group,
4741 &priv->ring[i + tqp_num]);
4742
4743 priv->ring[i].tqp_vector = tqp_vector;
4744 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4745 tqp_vector->num_tqps++;
4746 }
4747
4748 for (i = 0; i < priv->vector_num; i++) {
4749 struct hnae3_ring_chain_node *vector_ring_chain;
4750
4751 tqp_vector = &priv->tqp_vector[i];
4752
4753 tqp_vector->rx_group.total_bytes = 0;
4754 tqp_vector->rx_group.total_packets = 0;
4755 tqp_vector->tx_group.total_bytes = 0;
4756 tqp_vector->tx_group.total_packets = 0;
4757 tqp_vector->handle = h;
4758
4759 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4760 if (!vector_ring_chain) {
4761 ret = -ENOMEM;
4762 goto map_ring_fail;
4763 }
4764
4765 ret = h->ae_algo->ops->map_ring_to_vector(h,
4766 tqp_vector->vector_irq, vector_ring_chain);
4767
4768 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4769
4770 if (ret)
4771 goto map_ring_fail;
4772
4773 netif_napi_add(priv->netdev, &tqp_vector->napi,
4774 hns3_nic_common_poll);
4775 }
4776
4777 return 0;
4778
4779 map_ring_fail:
4780 while (i--)
4781 netif_napi_del(&priv->tqp_vector[i].napi);
4782
4783 return ret;
4784 }
4785
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4786 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4787 {
4788 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4789 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4790 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4791
4792 /* initialize the configuration for interrupt coalescing.
4793 * 1. GL (Interrupt Gap Limiter)
4794 * 2. RL (Interrupt Rate Limiter)
4795 * 3. QL (Interrupt Quantity Limiter)
4796 *
4797 * Default: enable interrupt coalescing self-adaptive and GL
4798 */
4799 tx_coal->adapt_enable = 1;
4800 rx_coal->adapt_enable = 1;
4801
4802 tx_coal->int_gl = HNS3_INT_GL_50K;
4803 rx_coal->int_gl = HNS3_INT_GL_50K;
4804
4805 rx_coal->flow_level = HNS3_FLOW_LOW;
4806 tx_coal->flow_level = HNS3_FLOW_LOW;
4807
4808 if (ae_dev->dev_specs.int_ql_max) {
4809 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4810 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4811 }
4812 }
4813
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4814 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4815 {
4816 struct hnae3_handle *h = priv->ae_handle;
4817 struct hns3_enet_tqp_vector *tqp_vector;
4818 struct hnae3_vector_info *vector;
4819 struct pci_dev *pdev = h->pdev;
4820 u16 tqp_num = h->kinfo.num_tqps;
4821 u16 vector_num;
4822 int ret = 0;
4823 u16 i;
4824
4825 /* RSS size, cpu online and vector_num should be the same */
4826 /* Should consider 2p/4p later */
4827 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4828
4829 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4830 GFP_KERNEL);
4831 if (!vector)
4832 return -ENOMEM;
4833
4834 /* save the actual available vector number */
4835 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4836
4837 priv->vector_num = vector_num;
4838 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4839 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4840 GFP_KERNEL);
4841 if (!priv->tqp_vector) {
4842 ret = -ENOMEM;
4843 goto out;
4844 }
4845
4846 for (i = 0; i < priv->vector_num; i++) {
4847 tqp_vector = &priv->tqp_vector[i];
4848 tqp_vector->idx = i;
4849 tqp_vector->mask_addr = vector[i].io_addr;
4850 tqp_vector->vector_irq = vector[i].vector;
4851 hns3_vector_coalesce_init(tqp_vector, priv);
4852 }
4853
4854 out:
4855 devm_kfree(&pdev->dev, vector);
4856 return ret;
4857 }
4858
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4859 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4860 {
4861 group->ring = NULL;
4862 group->count = 0;
4863 }
4864
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4865 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4866 {
4867 struct hnae3_ring_chain_node *vector_ring_chain;
4868 struct hnae3_handle *h = priv->ae_handle;
4869 struct hns3_enet_tqp_vector *tqp_vector;
4870 int i;
4871
4872 for (i = 0; i < priv->vector_num; i++) {
4873 tqp_vector = &priv->tqp_vector[i];
4874
4875 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4876 continue;
4877
4878 /* Since the mapping can be overwritten, when fail to get the
4879 * chain between vector and ring, we should go on to deal with
4880 * the remaining options.
4881 */
4882 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4883 if (!vector_ring_chain)
4884 dev_warn(priv->dev, "failed to get ring chain\n");
4885
4886 h->ae_algo->ops->unmap_ring_from_vector(h,
4887 tqp_vector->vector_irq, vector_ring_chain);
4888
4889 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4890
4891 hns3_clear_ring_group(&tqp_vector->rx_group);
4892 hns3_clear_ring_group(&tqp_vector->tx_group);
4893 netif_napi_del(&priv->tqp_vector[i].napi);
4894 }
4895 }
4896
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4897 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4898 {
4899 struct hnae3_handle *h = priv->ae_handle;
4900 struct pci_dev *pdev = h->pdev;
4901 int i, ret;
4902
4903 for (i = 0; i < priv->vector_num; i++) {
4904 struct hns3_enet_tqp_vector *tqp_vector;
4905
4906 tqp_vector = &priv->tqp_vector[i];
4907 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4908 if (ret)
4909 return;
4910 }
4911
4912 devm_kfree(&pdev->dev, priv->tqp_vector);
4913 }
4914
hns3_update_tx_spare_buf_config(struct hns3_nic_priv * priv)4915 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv)
4916 {
4917 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024)
4918 #define HNS3_MAX_PACKET_SIZE (64 * 1024)
4919
4920 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev);
4921 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4922 struct hnae3_handle *handle = priv->ae_handle;
4923
4924 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
4925 return;
4926
4927 if (!(domain && iommu_is_dma_domain(domain)))
4928 return;
4929
4930 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE;
4931 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE;
4932
4933 if (priv->tx_copybreak < priv->min_tx_copybreak)
4934 priv->tx_copybreak = priv->min_tx_copybreak;
4935 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size)
4936 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size;
4937 }
4938
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4939 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4940 unsigned int ring_type)
4941 {
4942 int queue_num = priv->ae_handle->kinfo.num_tqps;
4943 struct hns3_enet_ring *ring;
4944 int desc_num;
4945
4946 if (ring_type == HNAE3_RING_TYPE_TX) {
4947 ring = &priv->ring[q->tqp_index];
4948 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4949 ring->queue_index = q->tqp_index;
4950 ring->tx_copybreak = priv->tx_copybreak;
4951 ring->last_to_use = 0;
4952 } else {
4953 ring = &priv->ring[q->tqp_index + queue_num];
4954 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4955 ring->queue_index = q->tqp_index;
4956 ring->rx_copybreak = priv->rx_copybreak;
4957 }
4958
4959 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4960
4961 ring->tqp = q;
4962 ring->desc = NULL;
4963 ring->desc_cb = NULL;
4964 ring->dev = priv->dev;
4965 ring->desc_dma_addr = 0;
4966 ring->buf_size = q->buf_size;
4967 ring->desc_num = desc_num;
4968 ring->next_to_use = 0;
4969 ring->next_to_clean = 0;
4970 }
4971
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4972 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4973 struct hns3_nic_priv *priv)
4974 {
4975 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4976 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4977 }
4978
hns3_get_ring_config(struct hns3_nic_priv * priv)4979 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4980 {
4981 struct hnae3_handle *h = priv->ae_handle;
4982 struct pci_dev *pdev = h->pdev;
4983 int i;
4984
4985 priv->ring = devm_kzalloc(&pdev->dev,
4986 array3_size(h->kinfo.num_tqps,
4987 sizeof(*priv->ring), 2),
4988 GFP_KERNEL);
4989 if (!priv->ring)
4990 return -ENOMEM;
4991
4992 for (i = 0; i < h->kinfo.num_tqps; i++)
4993 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4994
4995 return 0;
4996 }
4997
hns3_put_ring_config(struct hns3_nic_priv * priv)4998 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4999 {
5000 if (!priv->ring)
5001 return;
5002
5003 devm_kfree(priv->dev, priv->ring);
5004 priv->ring = NULL;
5005 }
5006
hns3_alloc_page_pool(struct hns3_enet_ring * ring)5007 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
5008 {
5009 struct page_pool_params pp_params = {
5010 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
5011 .order = hns3_page_order(ring),
5012 .pool_size = ring->desc_num * hns3_buf_size(ring) /
5013 (PAGE_SIZE << hns3_page_order(ring)),
5014 .nid = dev_to_node(ring_to_dev(ring)),
5015 .dev = ring_to_dev(ring),
5016 .dma_dir = DMA_FROM_DEVICE,
5017 .offset = 0,
5018 .max_len = PAGE_SIZE << hns3_page_order(ring),
5019 };
5020
5021 ring->page_pool = page_pool_create(&pp_params);
5022 if (IS_ERR(ring->page_pool)) {
5023 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
5024 PTR_ERR(ring->page_pool));
5025 ring->page_pool = NULL;
5026 }
5027 }
5028
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)5029 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
5030 {
5031 int ret;
5032
5033 if (ring->desc_num <= 0 || ring->buf_size <= 0)
5034 return -EINVAL;
5035
5036 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
5037 sizeof(ring->desc_cb[0]), GFP_KERNEL);
5038 if (!ring->desc_cb) {
5039 ret = -ENOMEM;
5040 goto out;
5041 }
5042
5043 ret = hns3_alloc_desc(ring);
5044 if (ret)
5045 goto out_with_desc_cb;
5046
5047 if (!HNAE3_IS_TX_RING(ring)) {
5048 if (page_pool_enabled)
5049 hns3_alloc_page_pool(ring);
5050
5051 ret = hns3_alloc_ring_buffers(ring);
5052 if (ret)
5053 goto out_with_desc;
5054 } else {
5055 hns3_init_tx_spare_buffer(ring);
5056 }
5057
5058 return 0;
5059
5060 out_with_desc:
5061 hns3_free_desc(ring);
5062 out_with_desc_cb:
5063 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5064 ring->desc_cb = NULL;
5065 out:
5066 return ret;
5067 }
5068
hns3_fini_ring(struct hns3_enet_ring * ring)5069 void hns3_fini_ring(struct hns3_enet_ring *ring)
5070 {
5071 hns3_free_desc(ring);
5072 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5073 ring->desc_cb = NULL;
5074 ring->next_to_clean = 0;
5075 ring->next_to_use = 0;
5076 ring->last_to_use = 0;
5077 ring->pending_buf = 0;
5078 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5079 dev_kfree_skb_any(ring->skb);
5080 ring->skb = NULL;
5081 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5082 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5083
5084 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5085 DMA_TO_DEVICE);
5086 free_pages((unsigned long)tx_spare->buf,
5087 get_order(tx_spare->len));
5088 devm_kfree(ring_to_dev(ring), tx_spare);
5089 ring->tx_spare = NULL;
5090 }
5091
5092 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5093 page_pool_destroy(ring->page_pool);
5094 ring->page_pool = NULL;
5095 }
5096 }
5097
hns3_buf_size2type(u32 buf_size)5098 static int hns3_buf_size2type(u32 buf_size)
5099 {
5100 int bd_size_type;
5101
5102 switch (buf_size) {
5103 case 512:
5104 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5105 break;
5106 case 1024:
5107 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5108 break;
5109 case 2048:
5110 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5111 break;
5112 case 4096:
5113 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5114 break;
5115 default:
5116 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5117 }
5118
5119 return bd_size_type;
5120 }
5121
hns3_init_ring_hw(struct hns3_enet_ring * ring)5122 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5123 {
5124 dma_addr_t dma = ring->desc_dma_addr;
5125 struct hnae3_queue *q = ring->tqp;
5126
5127 if (!HNAE3_IS_TX_RING(ring)) {
5128 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5129 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5130 (u32)((dma >> 31) >> 1));
5131
5132 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5133 hns3_buf_size2type(ring->buf_size));
5134 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5135 ring->desc_num / 8 - 1);
5136 } else {
5137 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5138 (u32)dma);
5139 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5140 (u32)((dma >> 31) >> 1));
5141
5142 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5143 ring->desc_num / 8 - 1);
5144 }
5145 }
5146
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5147 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5148 {
5149 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5150 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5151 int i;
5152
5153 for (i = 0; i < tc_info->num_tc; i++) {
5154 int j;
5155
5156 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5157 struct hnae3_queue *q;
5158
5159 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5160 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5161 }
5162 }
5163 }
5164
hns3_init_all_ring(struct hns3_nic_priv * priv)5165 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5166 {
5167 struct hnae3_handle *h = priv->ae_handle;
5168 int ring_num = h->kinfo.num_tqps * 2;
5169 int i, j;
5170 int ret;
5171
5172 hns3_update_tx_spare_buf_config(priv);
5173 for (i = 0; i < ring_num; i++) {
5174 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5175 if (ret) {
5176 dev_err(priv->dev,
5177 "Alloc ring memory fail! ret=%d\n", ret);
5178 goto out_when_alloc_ring_memory;
5179 }
5180
5181 u64_stats_init(&priv->ring[i].syncp);
5182 cond_resched();
5183 }
5184
5185 return 0;
5186
5187 out_when_alloc_ring_memory:
5188 for (j = i - 1; j >= 0; j--)
5189 hns3_fini_ring(&priv->ring[j]);
5190
5191 return -ENOMEM;
5192 }
5193
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5194 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5195 {
5196 struct hnae3_handle *h = priv->ae_handle;
5197 int i;
5198
5199 for (i = 0; i < h->kinfo.num_tqps; i++) {
5200 hns3_fini_ring(&priv->ring[i]);
5201 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5202 }
5203 }
5204
5205 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5206 static int hns3_init_mac_addr(struct net_device *netdev)
5207 {
5208 struct hns3_nic_priv *priv = netdev_priv(netdev);
5209 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5210 struct hnae3_handle *h = priv->ae_handle;
5211 u8 mac_addr_temp[ETH_ALEN] = {0};
5212 int ret = 0;
5213
5214 if (h->ae_algo->ops->get_mac_addr)
5215 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5216
5217 /* Check if the MAC address is valid, if not get a random one */
5218 if (!is_valid_ether_addr(mac_addr_temp)) {
5219 eth_hw_addr_random(netdev);
5220 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5221 dev_warn(priv->dev, "using random MAC address %s\n",
5222 format_mac_addr);
5223 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5224 eth_hw_addr_set(netdev, mac_addr_temp);
5225 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5226 } else {
5227 return 0;
5228 }
5229
5230 if (h->ae_algo->ops->set_mac_addr)
5231 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5232
5233 return ret;
5234 }
5235
hns3_init_phy(struct net_device * netdev)5236 static int hns3_init_phy(struct net_device *netdev)
5237 {
5238 struct hnae3_handle *h = hns3_get_handle(netdev);
5239 int ret = 0;
5240
5241 if (h->ae_algo->ops->mac_connect_phy)
5242 ret = h->ae_algo->ops->mac_connect_phy(h);
5243
5244 return ret;
5245 }
5246
hns3_uninit_phy(struct net_device * netdev)5247 static void hns3_uninit_phy(struct net_device *netdev)
5248 {
5249 struct hnae3_handle *h = hns3_get_handle(netdev);
5250
5251 if (h->ae_algo->ops->mac_disconnect_phy)
5252 h->ae_algo->ops->mac_disconnect_phy(h);
5253 }
5254
hns3_client_start(struct hnae3_handle * handle)5255 static int hns3_client_start(struct hnae3_handle *handle)
5256 {
5257 if (!handle->ae_algo->ops->client_start)
5258 return 0;
5259
5260 return handle->ae_algo->ops->client_start(handle);
5261 }
5262
hns3_client_stop(struct hnae3_handle * handle)5263 static void hns3_client_stop(struct hnae3_handle *handle)
5264 {
5265 if (!handle->ae_algo->ops->client_stop)
5266 return;
5267
5268 handle->ae_algo->ops->client_stop(handle);
5269 }
5270
hns3_info_show(struct hns3_nic_priv * priv)5271 static void hns3_info_show(struct hns3_nic_priv *priv)
5272 {
5273 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5274 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5275
5276 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5277 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5278 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5279 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5280 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5281 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5282 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5283 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5284 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5285 kinfo->tc_info.num_tc);
5286 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5287 }
5288
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5289 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5290 enum dim_cq_period_mode mode, bool is_tx)
5291 {
5292 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
5293 struct hnae3_handle *handle = priv->ae_handle;
5294 int i;
5295
5296 if (is_tx) {
5297 priv->tx_cqe_mode = mode;
5298
5299 for (i = 0; i < priv->vector_num; i++)
5300 priv->tqp_vector[i].tx_group.dim.mode = mode;
5301 } else {
5302 priv->rx_cqe_mode = mode;
5303
5304 for (i = 0; i < priv->vector_num; i++)
5305 priv->tqp_vector[i].rx_group.dim.mode = mode;
5306 }
5307
5308 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5309 u32 new_mode;
5310 u64 reg;
5311
5312 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5313 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5314 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5315
5316 writel(new_mode, handle->kinfo.io_base + reg);
5317 }
5318 }
5319
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5320 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5321 enum dim_cq_period_mode tx_mode,
5322 enum dim_cq_period_mode rx_mode)
5323 {
5324 hns3_set_cq_period_mode(priv, tx_mode, true);
5325 hns3_set_cq_period_mode(priv, rx_mode, false);
5326 }
5327
hns3_state_init(struct hnae3_handle * handle)5328 static void hns3_state_init(struct hnae3_handle *handle)
5329 {
5330 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
5331 struct net_device *netdev = handle->kinfo.netdev;
5332 struct hns3_nic_priv *priv = netdev_priv(netdev);
5333
5334 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5335
5336 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5337 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5338
5339 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5340 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5341
5342 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5343 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5344
5345 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5346 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5347 }
5348
hns3_state_uninit(struct hnae3_handle * handle)5349 static void hns3_state_uninit(struct hnae3_handle *handle)
5350 {
5351 struct hns3_nic_priv *priv = handle->priv;
5352
5353 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5354 }
5355
hns3_client_init(struct hnae3_handle * handle)5356 static int hns3_client_init(struct hnae3_handle *handle)
5357 {
5358 struct pci_dev *pdev = handle->pdev;
5359 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5360 u16 alloc_tqps, max_rss_size;
5361 struct hns3_nic_priv *priv;
5362 struct net_device *netdev;
5363 int ret;
5364
5365 ae_dev->handle = handle;
5366
5367 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5368 &max_rss_size);
5369 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5370 if (!netdev)
5371 return -ENOMEM;
5372
5373 priv = netdev_priv(netdev);
5374 priv->dev = &pdev->dev;
5375 priv->netdev = netdev;
5376 priv->ae_handle = handle;
5377 priv->tx_timeout_count = 0;
5378 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5379 priv->min_tx_copybreak = 0;
5380 priv->min_tx_spare_buf_size = 0;
5381 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5382
5383 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5384
5385 handle->kinfo.netdev = netdev;
5386 handle->priv = (void *)priv;
5387
5388 hns3_init_mac_addr(netdev);
5389
5390 hns3_set_default_feature(netdev);
5391
5392 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5393 netdev->priv_flags |= IFF_UNICAST_FLT;
5394 netdev->netdev_ops = &hns3_nic_netdev_ops;
5395 SET_NETDEV_DEV(netdev, &pdev->dev);
5396 hns3_ethtool_set_ops(netdev);
5397
5398 /* Carrier off reporting is important to ethtool even BEFORE open */
5399 netif_carrier_off(netdev);
5400
5401 ret = hns3_get_ring_config(priv);
5402 if (ret) {
5403 ret = -ENOMEM;
5404 goto out_get_ring_cfg;
5405 }
5406
5407 hns3_nic_init_coal_cfg(priv);
5408
5409 ret = hns3_nic_alloc_vector_data(priv);
5410 if (ret) {
5411 ret = -ENOMEM;
5412 goto out_alloc_vector_data;
5413 }
5414
5415 ret = hns3_nic_init_vector_data(priv);
5416 if (ret) {
5417 ret = -ENOMEM;
5418 goto out_init_vector_data;
5419 }
5420
5421 ret = hns3_init_all_ring(priv);
5422 if (ret) {
5423 ret = -ENOMEM;
5424 goto out_init_ring;
5425 }
5426
5427 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5428 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5429
5430 ret = hns3_init_phy(netdev);
5431 if (ret)
5432 goto out_init_phy;
5433
5434 /* the device can work without cpu rmap, only aRFS needs it */
5435 ret = hns3_set_rx_cpu_rmap(netdev);
5436 if (ret)
5437 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5438
5439 ret = hns3_nic_init_irq(priv);
5440 if (ret) {
5441 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5442 hns3_free_rx_cpu_rmap(netdev);
5443 goto out_init_irq_fail;
5444 }
5445
5446 ret = hns3_client_start(handle);
5447 if (ret) {
5448 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5449 goto out_client_start;
5450 }
5451
5452 hns3_dcbnl_setup(handle);
5453
5454 ret = hns3_dbg_init(handle);
5455 if (ret) {
5456 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5457 ret);
5458 goto out_client_start;
5459 }
5460
5461 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5462
5463 hns3_state_init(handle);
5464
5465 ret = register_netdev(netdev);
5466 if (ret) {
5467 dev_err(priv->dev, "probe register netdev fail!\n");
5468 goto out_reg_netdev_fail;
5469 }
5470
5471 if (netif_msg_drv(handle))
5472 hns3_info_show(priv);
5473
5474 return ret;
5475
5476 out_reg_netdev_fail:
5477 hns3_state_uninit(handle);
5478 hns3_dbg_uninit(handle);
5479 hns3_client_stop(handle);
5480 out_client_start:
5481 hns3_free_rx_cpu_rmap(netdev);
5482 hns3_nic_uninit_irq(priv);
5483 out_init_irq_fail:
5484 hns3_uninit_phy(netdev);
5485 out_init_phy:
5486 hns3_uninit_all_ring(priv);
5487 out_init_ring:
5488 hns3_nic_uninit_vector_data(priv);
5489 out_init_vector_data:
5490 hns3_nic_dealloc_vector_data(priv);
5491 out_alloc_vector_data:
5492 priv->ring = NULL;
5493 out_get_ring_cfg:
5494 priv->ae_handle = NULL;
5495 free_netdev(netdev);
5496 return ret;
5497 }
5498
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5499 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5500 {
5501 struct net_device *netdev = handle->kinfo.netdev;
5502 struct hns3_nic_priv *priv = netdev_priv(netdev);
5503
5504 if (netdev->reg_state != NETREG_UNINITIALIZED)
5505 unregister_netdev(netdev);
5506
5507 hns3_client_stop(handle);
5508
5509 hns3_uninit_phy(netdev);
5510
5511 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5512 netdev_warn(netdev, "already uninitialized\n");
5513 goto out_netdev_free;
5514 }
5515
5516 hns3_free_rx_cpu_rmap(netdev);
5517
5518 hns3_nic_uninit_irq(priv);
5519
5520 hns3_clear_all_ring(handle, true);
5521
5522 hns3_nic_uninit_vector_data(priv);
5523
5524 hns3_nic_dealloc_vector_data(priv);
5525
5526 hns3_uninit_all_ring(priv);
5527
5528 hns3_put_ring_config(priv);
5529
5530 out_netdev_free:
5531 hns3_dbg_uninit(handle);
5532 free_netdev(netdev);
5533 }
5534
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5535 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5536 {
5537 struct net_device *netdev = handle->kinfo.netdev;
5538
5539 if (!netdev)
5540 return;
5541
5542 if (linkup) {
5543 netif_tx_wake_all_queues(netdev);
5544 netif_carrier_on(netdev);
5545 if (netif_msg_link(handle))
5546 netdev_info(netdev, "link up\n");
5547 } else {
5548 netif_carrier_off(netdev);
5549 netif_tx_stop_all_queues(netdev);
5550 if (netif_msg_link(handle))
5551 netdev_info(netdev, "link down\n");
5552 }
5553 }
5554
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5555 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5556 {
5557 while (ring->next_to_clean != ring->next_to_use) {
5558 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5559 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5560 ring_ptr_move_fw(ring, next_to_clean);
5561 }
5562
5563 ring->pending_buf = 0;
5564 }
5565
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5566 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5567 {
5568 struct hns3_desc_cb res_cbs;
5569 int ret;
5570
5571 while (ring->next_to_use != ring->next_to_clean) {
5572 /* When a buffer is not reused, it's memory has been
5573 * freed in hns3_handle_rx_bd or will be freed by
5574 * stack, so we need to replace the buffer here.
5575 */
5576 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5577 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5578 if (ret) {
5579 hns3_ring_stats_update(ring, sw_err_cnt);
5580 /* if alloc new buffer fail, exit directly
5581 * and reclear in up flow.
5582 */
5583 netdev_warn(ring_to_netdev(ring),
5584 "reserve buffer map failed, ret = %d\n",
5585 ret);
5586 return ret;
5587 }
5588 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5589 }
5590 ring_ptr_move_fw(ring, next_to_use);
5591 }
5592
5593 /* Free the pending skb in rx ring */
5594 if (ring->skb) {
5595 dev_kfree_skb_any(ring->skb);
5596 ring->skb = NULL;
5597 ring->pending_buf = 0;
5598 }
5599
5600 return 0;
5601 }
5602
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5603 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5604 {
5605 while (ring->next_to_use != ring->next_to_clean) {
5606 /* When a buffer is not reused, it's memory has been
5607 * freed in hns3_handle_rx_bd or will be freed by
5608 * stack, so only need to unmap the buffer here.
5609 */
5610 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5611 hns3_unmap_buffer(ring,
5612 &ring->desc_cb[ring->next_to_use]);
5613 ring->desc_cb[ring->next_to_use].dma = 0;
5614 }
5615
5616 ring_ptr_move_fw(ring, next_to_use);
5617 }
5618 }
5619
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5620 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5621 {
5622 struct net_device *ndev = h->kinfo.netdev;
5623 struct hns3_nic_priv *priv = netdev_priv(ndev);
5624 u32 i;
5625
5626 for (i = 0; i < h->kinfo.num_tqps; i++) {
5627 struct hns3_enet_ring *ring;
5628
5629 ring = &priv->ring[i];
5630 hns3_clear_tx_ring(ring);
5631
5632 ring = &priv->ring[i + h->kinfo.num_tqps];
5633 /* Continue to clear other rings even if clearing some
5634 * rings failed.
5635 */
5636 if (force)
5637 hns3_force_clear_rx_ring(ring);
5638 else
5639 hns3_clear_rx_ring(ring);
5640 }
5641 }
5642
hns3_nic_reset_all_ring(struct hnae3_handle * h)5643 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5644 {
5645 struct net_device *ndev = h->kinfo.netdev;
5646 struct hns3_nic_priv *priv = netdev_priv(ndev);
5647 struct hns3_enet_ring *rx_ring;
5648 int i, j;
5649 int ret;
5650
5651 ret = h->ae_algo->ops->reset_queue(h);
5652 if (ret)
5653 return ret;
5654
5655 for (i = 0; i < h->kinfo.num_tqps; i++) {
5656 hns3_init_ring_hw(&priv->ring[i]);
5657
5658 /* We need to clear tx ring here because self test will
5659 * use the ring and will not run down before up
5660 */
5661 hns3_clear_tx_ring(&priv->ring[i]);
5662 priv->ring[i].next_to_clean = 0;
5663 priv->ring[i].next_to_use = 0;
5664 priv->ring[i].last_to_use = 0;
5665
5666 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5667 hns3_init_ring_hw(rx_ring);
5668 ret = hns3_clear_rx_ring(rx_ring);
5669 if (ret)
5670 return ret;
5671
5672 /* We can not know the hardware head and tail when this
5673 * function is called in reset flow, so we reuse all desc.
5674 */
5675 for (j = 0; j < rx_ring->desc_num; j++)
5676 hns3_reuse_buffer(rx_ring, j);
5677
5678 rx_ring->next_to_clean = 0;
5679 rx_ring->next_to_use = 0;
5680 }
5681
5682 hns3_init_tx_ring_tc(priv);
5683
5684 return 0;
5685 }
5686
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5687 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5688 {
5689 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5690 struct net_device *ndev = kinfo->netdev;
5691 struct hns3_nic_priv *priv = netdev_priv(ndev);
5692
5693 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5694 return 0;
5695
5696 if (!netif_running(ndev))
5697 return 0;
5698
5699 return hns3_nic_net_stop(ndev);
5700 }
5701
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5702 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5703 {
5704 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5705 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5706 int ret = 0;
5707
5708 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5709 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5710 return -EFAULT;
5711 }
5712
5713 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5714
5715 if (netif_running(kinfo->netdev)) {
5716 ret = hns3_nic_net_open(kinfo->netdev);
5717 if (ret) {
5718 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5719 netdev_err(kinfo->netdev,
5720 "net up fail, ret=%d!\n", ret);
5721 return ret;
5722 }
5723 }
5724
5725 return ret;
5726 }
5727
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5728 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5729 {
5730 struct net_device *netdev = handle->kinfo.netdev;
5731 struct hns3_nic_priv *priv = netdev_priv(netdev);
5732 int ret;
5733
5734 /* Carrier off reporting is important to ethtool even BEFORE open */
5735 netif_carrier_off(netdev);
5736
5737 ret = hns3_get_ring_config(priv);
5738 if (ret)
5739 return ret;
5740
5741 ret = hns3_nic_alloc_vector_data(priv);
5742 if (ret)
5743 goto err_put_ring;
5744
5745 ret = hns3_nic_init_vector_data(priv);
5746 if (ret)
5747 goto err_dealloc_vector;
5748
5749 ret = hns3_init_all_ring(priv);
5750 if (ret)
5751 goto err_uninit_vector;
5752
5753 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5754
5755 /* the device can work without cpu rmap, only aRFS needs it */
5756 ret = hns3_set_rx_cpu_rmap(netdev);
5757 if (ret)
5758 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5759
5760 ret = hns3_nic_init_irq(priv);
5761 if (ret) {
5762 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5763 hns3_free_rx_cpu_rmap(netdev);
5764 goto err_init_irq_fail;
5765 }
5766
5767 if (!hns3_is_phys_func(handle->pdev))
5768 hns3_init_mac_addr(netdev);
5769
5770 ret = hns3_client_start(handle);
5771 if (ret) {
5772 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5773 goto err_client_start_fail;
5774 }
5775
5776 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5777
5778 return ret;
5779
5780 err_client_start_fail:
5781 hns3_free_rx_cpu_rmap(netdev);
5782 hns3_nic_uninit_irq(priv);
5783 err_init_irq_fail:
5784 hns3_uninit_all_ring(priv);
5785 err_uninit_vector:
5786 hns3_nic_uninit_vector_data(priv);
5787 err_dealloc_vector:
5788 hns3_nic_dealloc_vector_data(priv);
5789 err_put_ring:
5790 hns3_put_ring_config(priv);
5791
5792 return ret;
5793 }
5794
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5795 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5796 {
5797 struct net_device *netdev = handle->kinfo.netdev;
5798 struct hns3_nic_priv *priv = netdev_priv(netdev);
5799
5800 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5801 hns3_nic_net_stop(netdev);
5802
5803 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5804 netdev_warn(netdev, "already uninitialized\n");
5805 return 0;
5806 }
5807
5808 hns3_free_rx_cpu_rmap(netdev);
5809 hns3_nic_uninit_irq(priv);
5810 hns3_clear_all_ring(handle, true);
5811 hns3_reset_tx_queue(priv->ae_handle);
5812
5813 hns3_nic_uninit_vector_data(priv);
5814
5815 hns3_nic_dealloc_vector_data(priv);
5816
5817 hns3_uninit_all_ring(priv);
5818
5819 hns3_put_ring_config(priv);
5820
5821 return 0;
5822 }
5823
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5824 int hns3_reset_notify(struct hnae3_handle *handle,
5825 enum hnae3_reset_notify_type type)
5826 {
5827 int ret = 0;
5828
5829 switch (type) {
5830 case HNAE3_UP_CLIENT:
5831 ret = hns3_reset_notify_up_enet(handle);
5832 break;
5833 case HNAE3_DOWN_CLIENT:
5834 ret = hns3_reset_notify_down_enet(handle);
5835 break;
5836 case HNAE3_INIT_CLIENT:
5837 ret = hns3_reset_notify_init_enet(handle);
5838 break;
5839 case HNAE3_UNINIT_CLIENT:
5840 ret = hns3_reset_notify_uninit_enet(handle);
5841 break;
5842 default:
5843 break;
5844 }
5845
5846 return ret;
5847 }
5848
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5849 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5850 bool rxfh_configured)
5851 {
5852 int ret;
5853
5854 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5855 rxfh_configured);
5856 if (ret) {
5857 dev_err(&handle->pdev->dev,
5858 "Change tqp num(%u) fail.\n", new_tqp_num);
5859 return ret;
5860 }
5861
5862 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5863 if (ret)
5864 return ret;
5865
5866 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5867 if (ret)
5868 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5869
5870 return ret;
5871 }
5872
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5873 int hns3_set_channels(struct net_device *netdev,
5874 struct ethtool_channels *ch)
5875 {
5876 struct hnae3_handle *h = hns3_get_handle(netdev);
5877 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5878 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5879 u32 new_tqp_num = ch->combined_count;
5880 u16 org_tqp_num;
5881 int ret;
5882
5883 if (hns3_nic_resetting(netdev))
5884 return -EBUSY;
5885
5886 if (ch->rx_count || ch->tx_count)
5887 return -EINVAL;
5888
5889 if (kinfo->tc_info.mqprio_active) {
5890 dev_err(&netdev->dev,
5891 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5892 return -EINVAL;
5893 }
5894
5895 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5896 new_tqp_num < 1) {
5897 dev_err(&netdev->dev,
5898 "Change tqps fail, the tqp range is from 1 to %u",
5899 hns3_get_max_available_channels(h));
5900 return -EINVAL;
5901 }
5902
5903 if (kinfo->rss_size == new_tqp_num)
5904 return 0;
5905
5906 netif_dbg(h, drv, netdev,
5907 "set channels: tqp_num=%u, rxfh=%d\n",
5908 new_tqp_num, rxfh_configured);
5909
5910 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5911 if (ret)
5912 return ret;
5913
5914 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5915 if (ret)
5916 return ret;
5917
5918 org_tqp_num = h->kinfo.num_tqps;
5919 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5920 if (ret) {
5921 int ret1;
5922
5923 netdev_warn(netdev,
5924 "Change channels fail, revert to old value\n");
5925 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5926 if (ret1) {
5927 netdev_err(netdev,
5928 "revert to old channel fail\n");
5929 return ret1;
5930 }
5931
5932 return ret;
5933 }
5934
5935 return 0;
5936 }
5937
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5938 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5939 {
5940 struct hns3_nic_priv *priv = netdev_priv(ndev);
5941
5942 if (!if_running)
5943 return;
5944
5945 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5946 return;
5947
5948 netif_carrier_off(ndev);
5949 netif_tx_disable(ndev);
5950
5951 hns3_disable_irqs_and_tqps(ndev);
5952
5953 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5954 * during reset process, because driver may not be able
5955 * to disable the ring through firmware when downing the netdev.
5956 */
5957 if (!hns3_nic_resetting(ndev))
5958 hns3_nic_reset_all_ring(priv->ae_handle);
5959
5960 hns3_reset_tx_queue(priv->ae_handle);
5961 }
5962
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5963 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5964 {
5965 struct hns3_nic_priv *priv = netdev_priv(ndev);
5966 struct hnae3_handle *h = priv->ae_handle;
5967
5968 if (!if_running)
5969 return;
5970
5971 if (hns3_nic_resetting(ndev))
5972 return;
5973
5974 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5975 return;
5976
5977 if (hns3_nic_reset_all_ring(priv->ae_handle))
5978 return;
5979
5980 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5981
5982 hns3_enable_irqs_and_tqps(ndev);
5983
5984 netif_tx_wake_all_queues(ndev);
5985
5986 if (h->ae_algo->ops->get_status(h))
5987 netif_carrier_on(ndev);
5988 }
5989
5990 static const struct hns3_hw_error_info hns3_hw_err[] = {
5991 { .type = HNAE3_PPU_POISON_ERROR,
5992 .msg = "PPU poison" },
5993 { .type = HNAE3_CMDQ_ECC_ERROR,
5994 .msg = "IMP CMDQ error" },
5995 { .type = HNAE3_IMP_RD_POISON_ERROR,
5996 .msg = "IMP RD poison" },
5997 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5998 .msg = "ROCEE AXI RESP error" },
5999 };
6000
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)6001 static void hns3_process_hw_error(struct hnae3_handle *handle,
6002 enum hnae3_hw_error_type type)
6003 {
6004 u32 i;
6005
6006 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
6007 if (hns3_hw_err[i].type == type) {
6008 dev_err(&handle->pdev->dev, "Detected %s!\n",
6009 hns3_hw_err[i].msg);
6010 break;
6011 }
6012 }
6013 }
6014
6015 static const struct hnae3_client_ops client_ops = {
6016 .init_instance = hns3_client_init,
6017 .uninit_instance = hns3_client_uninit,
6018 .link_status_change = hns3_link_status_change,
6019 .reset_notify = hns3_reset_notify,
6020 .process_hw_error = hns3_process_hw_error,
6021 };
6022
6023 /* hns3_init_module - Driver registration routine
6024 * hns3_init_module is the first routine called when the driver is
6025 * loaded. All it does is register with the PCI subsystem.
6026 */
hns3_init_module(void)6027 static int __init hns3_init_module(void)
6028 {
6029 int ret;
6030
6031 pr_debug("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
6032 pr_debug("%s: %s\n", hns3_driver_name, hns3_copyright);
6033
6034 client.type = HNAE3_CLIENT_KNIC;
6035 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
6036 hns3_driver_name);
6037
6038 client.ops = &client_ops;
6039
6040 INIT_LIST_HEAD(&client.node);
6041
6042 hns3_dbg_register_debugfs(hns3_driver_name);
6043
6044 ret = hnae3_register_client(&client);
6045 if (ret)
6046 goto err_reg_client;
6047
6048 ret = pci_register_driver(&hns3_driver);
6049 if (ret)
6050 goto err_reg_driver;
6051
6052 return ret;
6053
6054 err_reg_driver:
6055 hnae3_unregister_client(&client);
6056 err_reg_client:
6057 hns3_dbg_unregister_debugfs();
6058 return ret;
6059 }
6060 module_init(hns3_init_module);
6061
6062 /* hns3_exit_module - Driver exit cleanup routine
6063 * hns3_exit_module is called just before the driver is removed
6064 * from memory.
6065 */
hns3_exit_module(void)6066 static void __exit hns3_exit_module(void)
6067 {
6068 hnae3_acquire_unload_lock();
6069 pci_unregister_driver(&hns3_driver);
6070 hnae3_unregister_client(&client);
6071 hns3_dbg_unregister_debugfs();
6072 hnae3_release_unload_lock();
6073 }
6074 module_exit(hns3_exit_module);
6075
6076 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6077 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6078 MODULE_LICENSE("GPL");
6079 MODULE_ALIAS("pci:hns-nic");
6080