1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Keem Bay PWM driver
4 *
5 * Copyright (C) 2020 Intel Corporation
6 * Authors: Lai Poey Seng <poey.seng.lai@intel.com>
7 * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
8 *
9 * Limitations:
10 * - Upon disabling a channel, the currently running
11 * period will not be completed. However, upon
12 * reconfiguration of the duty cycle/period, the
13 * currently running period will be completed first.
14 */
15
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pwm.h>
22 #include <linux/regmap.h>
23
24 #define KMB_TOTAL_PWM_CHANNELS 6
25 #define KMB_PWM_COUNT_MAX U16_MAX
26 #define KMB_PWM_EN_BIT BIT(31)
27
28 /* Mask */
29 #define KMB_PWM_HIGH_MASK GENMASK(31, 16)
30 #define KMB_PWM_LOW_MASK GENMASK(15, 0)
31 #define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
32
33 /* PWM Register offset */
34 #define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
35 #define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
36
37 struct keembay_pwm {
38 struct device *dev;
39 struct clk *clk;
40 void __iomem *base;
41 };
42
to_keembay_pwm_dev(struct pwm_chip * chip)43 static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
44 {
45 return pwmchip_get_drvdata(chip);
46 }
47
keembay_clk_unprepare(void * data)48 static void keembay_clk_unprepare(void *data)
49 {
50 clk_disable_unprepare(data);
51 }
52
keembay_clk_enable(struct device * dev,struct clk * clk)53 static int keembay_clk_enable(struct device *dev, struct clk *clk)
54 {
55 int ret;
56
57 ret = clk_prepare_enable(clk);
58 if (ret)
59 return ret;
60
61 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
62 }
63
64 /*
65 * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
66 * "__always_inline" this fails to compile because the compiler doesn't notice
67 * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
68 */
keembay_pwm_update_bits(struct keembay_pwm * priv,u32 mask,u32 val,u32 offset)69 static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
70 u32 val, u32 offset)
71 {
72 u32 buff = readl(priv->base + offset);
73
74 buff = u32_replace_bits(buff, val, mask);
75 writel(buff, priv->base + offset);
76 }
77
keembay_pwm_enable(struct keembay_pwm * priv,int ch)78 static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
79 {
80 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
81 KMB_PWM_LEADIN_OFFSET(ch));
82 }
83
keembay_pwm_disable(struct keembay_pwm * priv,int ch)84 static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
85 {
86 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
87 KMB_PWM_LEADIN_OFFSET(ch));
88 }
89
keembay_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)90 static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
91 struct pwm_state *state)
92 {
93 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
94 unsigned long long high, low;
95 unsigned long clk_rate;
96 u32 highlow;
97
98 clk_rate = clk_get_rate(priv->clk);
99
100 /* Read channel enabled status */
101 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
102 if (highlow & KMB_PWM_EN_BIT)
103 state->enabled = true;
104 else
105 state->enabled = false;
106
107 /* Read period and duty cycle */
108 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
109 low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
110 high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
111 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
112 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
113 state->polarity = PWM_POLARITY_NORMAL;
114
115 return 0;
116 }
117
keembay_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)118 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
119 const struct pwm_state *state)
120 {
121 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
122 struct pwm_state current_state;
123 unsigned long long div;
124 unsigned long clk_rate;
125 u32 pwm_count = 0;
126 u16 high, low;
127
128 if (state->polarity != PWM_POLARITY_NORMAL)
129 return -EINVAL;
130
131 /*
132 * Configure the pwm repeat count as infinite at (15:0) and leadin
133 * low time as 0 at (30:16), which is in terms of clock cycles.
134 */
135 keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
136 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
137
138 keembay_pwm_get_state(chip, pwm, ¤t_state);
139
140 if (!state->enabled) {
141 if (current_state.enabled)
142 keembay_pwm_disable(priv, pwm->hwpwm);
143 return 0;
144 }
145
146 /*
147 * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
148 * register contain the high time and low time of waveform accordingly.
149 * All the values are in terms of clock cycles.
150 */
151
152 clk_rate = clk_get_rate(priv->clk);
153 div = clk_rate * state->duty_cycle;
154 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
155 if (div > KMB_PWM_COUNT_MAX)
156 return -ERANGE;
157
158 high = div;
159 div = clk_rate * state->period;
160 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
161 div = div - high;
162 if (div > KMB_PWM_COUNT_MAX)
163 return -ERANGE;
164
165 low = div;
166
167 pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
168 FIELD_PREP(KMB_PWM_LOW_MASK, low);
169
170 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
171
172 if (state->enabled && !current_state.enabled)
173 keembay_pwm_enable(priv, pwm->hwpwm);
174
175 return 0;
176 }
177
178 static const struct pwm_ops keembay_pwm_ops = {
179 .apply = keembay_pwm_apply,
180 .get_state = keembay_pwm_get_state,
181 };
182
keembay_pwm_probe(struct platform_device * pdev)183 static int keembay_pwm_probe(struct platform_device *pdev)
184 {
185 struct device *dev = &pdev->dev;
186 struct pwm_chip *chip;
187 struct keembay_pwm *priv;
188 int ret;
189
190 chip = devm_pwmchip_alloc(dev, KMB_TOTAL_PWM_CHANNELS, sizeof(*priv));
191 if (IS_ERR(chip))
192 return PTR_ERR(chip);
193 priv = to_keembay_pwm_dev(chip);
194
195 priv->clk = devm_clk_get(dev, NULL);
196 if (IS_ERR(priv->clk))
197 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
198
199 priv->base = devm_platform_ioremap_resource(pdev, 0);
200 if (IS_ERR(priv->base))
201 return PTR_ERR(priv->base);
202
203 ret = keembay_clk_enable(dev, priv->clk);
204 if (ret)
205 return ret;
206
207 chip->ops = &keembay_pwm_ops;
208
209 ret = devm_pwmchip_add(dev, chip);
210 if (ret)
211 return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
212
213 return 0;
214 }
215
216 static const struct of_device_id keembay_pwm_of_match[] = {
217 { .compatible = "intel,keembay-pwm" },
218 { }
219 };
220 MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
221
222 static struct platform_driver keembay_pwm_driver = {
223 .probe = keembay_pwm_probe,
224 .driver = {
225 .name = "pwm-keembay",
226 .of_match_table = keembay_pwm_of_match,
227 },
228 };
229 module_platform_driver(keembay_pwm_driver);
230
231 MODULE_ALIAS("platform:pwm-keembay");
232 MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
233 MODULE_LICENSE("GPL v2");
234