1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Xudong Chen <xudong.chen@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/scatterlist.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/units.h>
29
30 #define I2C_RS_TRANSFER (1 << 4)
31 #define I2C_ARB_LOST (1 << 3)
32 #define I2C_HS_NACKERR (1 << 2)
33 #define I2C_ACKERR (1 << 1)
34 #define I2C_TRANSAC_COMP (1 << 0)
35 #define I2C_TRANSAC_START (1 << 0)
36 #define I2C_RS_MUL_CNFG (1 << 15)
37 #define I2C_RS_MUL_TRIG (1 << 14)
38 #define I2C_DCM_DISABLE 0x0000
39 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
40 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
41 #define I2C_SOFT_RST 0x0001
42 #define I2C_HANDSHAKE_RST 0x0020
43 #define I2C_FIFO_ADDR_CLR 0x0001
44 #define I2C_DELAY_LEN 0x0002
45 #define I2C_ST_START_CON 0x8001
46 #define I2C_FS_START_CON 0x1800
47 #define I2C_TIME_CLR_VALUE 0x0000
48 #define I2C_TIME_DEFAULT_VALUE 0x0003
49 #define I2C_WRRD_TRANAC_VALUE 0x0002
50 #define I2C_RD_TRANAC_VALUE 0x0001
51 #define I2C_SCL_MIS_COMP_VALUE 0x0000
52 #define I2C_CHN_CLR_FLAG 0x0000
53 #define I2C_RELIABILITY 0x0010
54 #define I2C_DMAACK_ENABLE 0x0008
55
56 #define I2C_DMA_CON_TX 0x0000
57 #define I2C_DMA_CON_RX 0x0001
58 #define I2C_DMA_ASYNC_MODE 0x0004
59 #define I2C_DMA_SKIP_CONFIG 0x0010
60 #define I2C_DMA_DIR_CHANGE 0x0200
61 #define I2C_DMA_START_EN 0x0001
62 #define I2C_DMA_INT_FLAG_NONE 0x0000
63 #define I2C_DMA_CLR_FLAG 0x0000
64 #define I2C_DMA_WARM_RST 0x0001
65 #define I2C_DMA_HARD_RST 0x0002
66 #define I2C_DMA_HANDSHAKE_RST 0x0004
67
68 #define MAX_SAMPLE_CNT_DIV 8
69 #define MAX_STEP_CNT_DIV 64
70 #define MAX_CLOCK_DIV_8BITS 256
71 #define MAX_CLOCK_DIV_5BITS 32
72 #define MAX_HS_STEP_CNT_DIV 8
73 #define I2C_STANDARD_MODE_BUFFER (1000 / 3)
74 #define I2C_FAST_MODE_BUFFER (300 / 3)
75 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3)
76
77 #define I2C_CONTROL_RS (0x1 << 1)
78 #define I2C_CONTROL_DMA_EN (0x1 << 2)
79 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
80 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
81 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
82 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
83 #define I2C_CONTROL_DMAACK_EN (0x1 << 8)
84 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
85 #define I2C_CONTROL_WRAPPER (0x1 << 0)
86
87 #define I2C_DRV_NAME "i2c-mt65xx"
88
89 /**
90 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
91 *
92 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
93 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
94 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
95 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
96 * @I2C_MT65XX_CLK_MAX: Number of supported clocks
97 */
98 enum i2c_mt65xx_clks {
99 I2C_MT65XX_CLK_MAIN = 0,
100 I2C_MT65XX_CLK_DMA,
101 I2C_MT65XX_CLK_PMIC,
102 I2C_MT65XX_CLK_ARB,
103 I2C_MT65XX_CLK_MAX
104 };
105
106 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
107 "main", "dma", "pmic", "arb"
108 };
109
110 enum DMA_REGS_OFFSET {
111 OFFSET_INT_FLAG = 0x0,
112 OFFSET_INT_EN = 0x04,
113 OFFSET_EN = 0x08,
114 OFFSET_RST = 0x0c,
115 OFFSET_CON = 0x18,
116 OFFSET_TX_MEM_ADDR = 0x1c,
117 OFFSET_RX_MEM_ADDR = 0x20,
118 OFFSET_TX_LEN = 0x24,
119 OFFSET_RX_LEN = 0x28,
120 OFFSET_TX_4G_MODE = 0x54,
121 OFFSET_RX_4G_MODE = 0x58,
122 };
123
124 enum i2c_trans_st_rs {
125 I2C_TRANS_STOP = 0,
126 I2C_TRANS_REPEATED_START,
127 };
128
129 enum mtk_trans_op {
130 I2C_MASTER_WR = 1,
131 I2C_MASTER_RD,
132 I2C_MASTER_WRRD,
133 };
134
135 enum I2C_REGS_OFFSET {
136 OFFSET_DATA_PORT,
137 OFFSET_SLAVE_ADDR,
138 OFFSET_INTR_MASK,
139 OFFSET_INTR_STAT,
140 OFFSET_CONTROL,
141 OFFSET_TRANSFER_LEN,
142 OFFSET_TRANSAC_LEN,
143 OFFSET_DELAY_LEN,
144 OFFSET_TIMING,
145 OFFSET_START,
146 OFFSET_EXT_CONF,
147 OFFSET_FIFO_STAT,
148 OFFSET_FIFO_THRESH,
149 OFFSET_FIFO_ADDR_CLR,
150 OFFSET_IO_CONFIG,
151 OFFSET_RSV_DEBUG,
152 OFFSET_HS,
153 OFFSET_SOFTRESET,
154 OFFSET_DCM_EN,
155 OFFSET_MULTI_DMA,
156 OFFSET_PATH_DIR,
157 OFFSET_DEBUGSTAT,
158 OFFSET_DEBUGCTRL,
159 OFFSET_TRANSFER_LEN_AUX,
160 OFFSET_CLOCK_DIV,
161 OFFSET_LTIMING,
162 OFFSET_SCL_HIGH_LOW_RATIO,
163 OFFSET_HS_SCL_HIGH_LOW_RATIO,
164 OFFSET_SCL_MIS_COMP_POINT,
165 OFFSET_STA_STO_AC_TIMING,
166 OFFSET_HS_STA_STO_AC_TIMING,
167 OFFSET_SDA_TIMING,
168 };
169
170 static const u16 mt_i2c_regs_v1[] = {
171 [OFFSET_DATA_PORT] = 0x0,
172 [OFFSET_SLAVE_ADDR] = 0x4,
173 [OFFSET_INTR_MASK] = 0x8,
174 [OFFSET_INTR_STAT] = 0xc,
175 [OFFSET_CONTROL] = 0x10,
176 [OFFSET_TRANSFER_LEN] = 0x14,
177 [OFFSET_TRANSAC_LEN] = 0x18,
178 [OFFSET_DELAY_LEN] = 0x1c,
179 [OFFSET_TIMING] = 0x20,
180 [OFFSET_START] = 0x24,
181 [OFFSET_EXT_CONF] = 0x28,
182 [OFFSET_FIFO_STAT] = 0x30,
183 [OFFSET_FIFO_THRESH] = 0x34,
184 [OFFSET_FIFO_ADDR_CLR] = 0x38,
185 [OFFSET_IO_CONFIG] = 0x40,
186 [OFFSET_RSV_DEBUG] = 0x44,
187 [OFFSET_HS] = 0x48,
188 [OFFSET_SOFTRESET] = 0x50,
189 [OFFSET_DCM_EN] = 0x54,
190 [OFFSET_PATH_DIR] = 0x60,
191 [OFFSET_DEBUGSTAT] = 0x64,
192 [OFFSET_DEBUGCTRL] = 0x68,
193 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
194 [OFFSET_CLOCK_DIV] = 0x70,
195 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
196 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
197 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
198 [OFFSET_STA_STO_AC_TIMING] = 0x80,
199 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
200 [OFFSET_SDA_TIMING] = 0x88,
201 };
202
203 static const u16 mt_i2c_regs_v2[] = {
204 [OFFSET_DATA_PORT] = 0x0,
205 [OFFSET_SLAVE_ADDR] = 0x4,
206 [OFFSET_INTR_MASK] = 0x8,
207 [OFFSET_INTR_STAT] = 0xc,
208 [OFFSET_CONTROL] = 0x10,
209 [OFFSET_TRANSFER_LEN] = 0x14,
210 [OFFSET_TRANSAC_LEN] = 0x18,
211 [OFFSET_DELAY_LEN] = 0x1c,
212 [OFFSET_TIMING] = 0x20,
213 [OFFSET_START] = 0x24,
214 [OFFSET_EXT_CONF] = 0x28,
215 [OFFSET_LTIMING] = 0x2c,
216 [OFFSET_HS] = 0x30,
217 [OFFSET_IO_CONFIG] = 0x34,
218 [OFFSET_FIFO_ADDR_CLR] = 0x38,
219 [OFFSET_SDA_TIMING] = 0x3c,
220 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
221 [OFFSET_CLOCK_DIV] = 0x48,
222 [OFFSET_SOFTRESET] = 0x50,
223 [OFFSET_MULTI_DMA] = 0x8c,
224 [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
225 [OFFSET_DEBUGSTAT] = 0xe4,
226 [OFFSET_DEBUGCTRL] = 0xe8,
227 [OFFSET_FIFO_STAT] = 0xf4,
228 [OFFSET_FIFO_THRESH] = 0xf8,
229 [OFFSET_DCM_EN] = 0xf88,
230 };
231
232 static const u16 mt_i2c_regs_v3[] = {
233 [OFFSET_DATA_PORT] = 0x0,
234 [OFFSET_INTR_MASK] = 0x8,
235 [OFFSET_INTR_STAT] = 0xc,
236 [OFFSET_CONTROL] = 0x10,
237 [OFFSET_TRANSFER_LEN] = 0x14,
238 [OFFSET_TRANSAC_LEN] = 0x18,
239 [OFFSET_DELAY_LEN] = 0x1c,
240 [OFFSET_TIMING] = 0x20,
241 [OFFSET_START] = 0x24,
242 [OFFSET_EXT_CONF] = 0x28,
243 [OFFSET_LTIMING] = 0x2c,
244 [OFFSET_HS] = 0x30,
245 [OFFSET_IO_CONFIG] = 0x34,
246 [OFFSET_FIFO_ADDR_CLR] = 0x38,
247 [OFFSET_SDA_TIMING] = 0x3c,
248 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
249 [OFFSET_CLOCK_DIV] = 0x48,
250 [OFFSET_SOFTRESET] = 0x50,
251 [OFFSET_MULTI_DMA] = 0x8c,
252 [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
253 [OFFSET_SLAVE_ADDR] = 0x94,
254 [OFFSET_DEBUGSTAT] = 0xe4,
255 [OFFSET_DEBUGCTRL] = 0xe8,
256 [OFFSET_FIFO_STAT] = 0xf4,
257 [OFFSET_FIFO_THRESH] = 0xf8,
258 [OFFSET_DCM_EN] = 0xf88,
259 };
260
261 struct mtk_i2c_compatible {
262 const struct i2c_adapter_quirks *quirks;
263 const u16 *regs;
264 unsigned char pmic_i2c: 1;
265 unsigned char dcm: 1;
266 unsigned char auto_restart: 1;
267 unsigned char aux_len_reg: 1;
268 unsigned char timing_adjust: 1;
269 unsigned char dma_sync: 1;
270 unsigned char ltiming_adjust: 1;
271 unsigned char apdma_sync: 1;
272 unsigned char max_dma_support;
273 };
274
275 struct mtk_i2c_ac_timing {
276 u16 htiming;
277 u16 ltiming;
278 u16 hs;
279 u16 ext;
280 u16 inter_clk_div;
281 u16 scl_hl_ratio;
282 u16 hs_scl_hl_ratio;
283 u16 sta_stop;
284 u16 hs_sta_stop;
285 u16 sda_timing;
286 };
287
288 struct mtk_i2c {
289 struct i2c_adapter adap; /* i2c host adapter */
290 struct device *dev;
291 struct completion msg_complete;
292 struct i2c_timings timing_info;
293
294 /* set in i2c probe */
295 void __iomem *base; /* i2c base addr */
296 void __iomem *pdmabase; /* dma base address*/
297 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
298 bool have_pmic; /* can use i2c pins from PMIC */
299 bool use_push_pull; /* IO config push-pull mode */
300
301 u16 irq_stat; /* interrupt status */
302 unsigned int clk_src_div;
303 unsigned int speed_hz; /* The speed in transfer */
304 enum mtk_trans_op op;
305 u16 timing_reg;
306 u16 high_speed_reg;
307 u16 ltiming_reg;
308 unsigned char auto_restart;
309 bool ignore_restart_irq;
310 struct mtk_i2c_ac_timing ac_timing;
311 const struct mtk_i2c_compatible *dev_comp;
312 };
313
314 /**
315 * struct i2c_spec_values:
316 * @min_low_ns: min LOW period of the SCL clock
317 * @min_su_sta_ns: min set-up time for a repeated START condition
318 * @max_hd_dat_ns: max data hold time
319 * @min_su_dat_ns: min data set-up time
320 */
321 struct i2c_spec_values {
322 unsigned int min_low_ns;
323 unsigned int min_su_sta_ns;
324 unsigned int max_hd_dat_ns;
325 unsigned int min_su_dat_ns;
326 };
327
328 static const struct i2c_spec_values standard_mode_spec = {
329 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
330 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
331 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
332 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
333 };
334
335 static const struct i2c_spec_values fast_mode_spec = {
336 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
337 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
338 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
339 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
340 };
341
342 static const struct i2c_spec_values fast_mode_plus_spec = {
343 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
344 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
345 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
346 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
347 };
348
349 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
350 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
351 .max_num_msgs = 1,
352 .max_write_len = 255,
353 .max_read_len = 255,
354 .max_comb_1st_msg_len = 255,
355 .max_comb_2nd_msg_len = 31,
356 };
357
358 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
359 .max_num_msgs = 255,
360 };
361
362 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
363 .flags = I2C_AQ_NO_ZERO_LEN,
364 };
365
366 static const struct mtk_i2c_compatible mt2712_compat = {
367 .regs = mt_i2c_regs_v1,
368 .pmic_i2c = 0,
369 .dcm = 1,
370 .auto_restart = 1,
371 .aux_len_reg = 1,
372 .timing_adjust = 1,
373 .dma_sync = 0,
374 .ltiming_adjust = 0,
375 .apdma_sync = 0,
376 .max_dma_support = 33,
377 };
378
379 static const struct mtk_i2c_compatible mt6577_compat = {
380 .quirks = &mt6577_i2c_quirks,
381 .regs = mt_i2c_regs_v1,
382 .pmic_i2c = 0,
383 .dcm = 1,
384 .auto_restart = 0,
385 .aux_len_reg = 0,
386 .timing_adjust = 0,
387 .dma_sync = 0,
388 .ltiming_adjust = 0,
389 .apdma_sync = 0,
390 .max_dma_support = 32,
391 };
392
393 static const struct mtk_i2c_compatible mt6589_compat = {
394 .quirks = &mt6577_i2c_quirks,
395 .regs = mt_i2c_regs_v1,
396 .pmic_i2c = 1,
397 .dcm = 0,
398 .auto_restart = 0,
399 .aux_len_reg = 0,
400 .timing_adjust = 0,
401 .dma_sync = 0,
402 .ltiming_adjust = 0,
403 .apdma_sync = 0,
404 .max_dma_support = 32,
405 };
406
407 static const struct mtk_i2c_compatible mt7622_compat = {
408 .quirks = &mt7622_i2c_quirks,
409 .regs = mt_i2c_regs_v1,
410 .pmic_i2c = 0,
411 .dcm = 1,
412 .auto_restart = 1,
413 .aux_len_reg = 1,
414 .timing_adjust = 0,
415 .dma_sync = 0,
416 .ltiming_adjust = 0,
417 .apdma_sync = 0,
418 .max_dma_support = 32,
419 };
420
421 static const struct mtk_i2c_compatible mt8168_compat = {
422 .regs = mt_i2c_regs_v1,
423 .pmic_i2c = 0,
424 .dcm = 1,
425 .auto_restart = 1,
426 .aux_len_reg = 1,
427 .timing_adjust = 1,
428 .dma_sync = 1,
429 .ltiming_adjust = 0,
430 .apdma_sync = 0,
431 .max_dma_support = 33,
432 };
433
434 static const struct mtk_i2c_compatible mt7981_compat = {
435 .regs = mt_i2c_regs_v3,
436 .pmic_i2c = 0,
437 .dcm = 0,
438 .auto_restart = 1,
439 .aux_len_reg = 1,
440 .timing_adjust = 1,
441 .dma_sync = 1,
442 .ltiming_adjust = 1,
443 .max_dma_support = 33
444 };
445
446 static const struct mtk_i2c_compatible mt7986_compat = {
447 .quirks = &mt7622_i2c_quirks,
448 .regs = mt_i2c_regs_v1,
449 .pmic_i2c = 0,
450 .dcm = 1,
451 .auto_restart = 1,
452 .aux_len_reg = 1,
453 .timing_adjust = 0,
454 .dma_sync = 1,
455 .ltiming_adjust = 0,
456 .max_dma_support = 32,
457 };
458
459 static const struct mtk_i2c_compatible mt8173_compat = {
460 .regs = mt_i2c_regs_v1,
461 .pmic_i2c = 0,
462 .dcm = 1,
463 .auto_restart = 1,
464 .aux_len_reg = 1,
465 .timing_adjust = 0,
466 .dma_sync = 0,
467 .ltiming_adjust = 0,
468 .apdma_sync = 0,
469 .max_dma_support = 33,
470 };
471
472 static const struct mtk_i2c_compatible mt8183_compat = {
473 .quirks = &mt8183_i2c_quirks,
474 .regs = mt_i2c_regs_v2,
475 .pmic_i2c = 0,
476 .dcm = 0,
477 .auto_restart = 1,
478 .aux_len_reg = 1,
479 .timing_adjust = 1,
480 .dma_sync = 1,
481 .ltiming_adjust = 1,
482 .apdma_sync = 0,
483 .max_dma_support = 33,
484 };
485
486 static const struct mtk_i2c_compatible mt8186_compat = {
487 .regs = mt_i2c_regs_v2,
488 .pmic_i2c = 0,
489 .dcm = 0,
490 .auto_restart = 1,
491 .aux_len_reg = 1,
492 .timing_adjust = 1,
493 .dma_sync = 0,
494 .ltiming_adjust = 1,
495 .apdma_sync = 0,
496 .max_dma_support = 36,
497 };
498
499 static const struct mtk_i2c_compatible mt8188_compat = {
500 .regs = mt_i2c_regs_v3,
501 .pmic_i2c = 0,
502 .dcm = 0,
503 .auto_restart = 1,
504 .aux_len_reg = 1,
505 .timing_adjust = 1,
506 .dma_sync = 0,
507 .ltiming_adjust = 1,
508 .apdma_sync = 1,
509 .max_dma_support = 36,
510 };
511
512 static const struct mtk_i2c_compatible mt8192_compat = {
513 .quirks = &mt8183_i2c_quirks,
514 .regs = mt_i2c_regs_v2,
515 .pmic_i2c = 0,
516 .dcm = 0,
517 .auto_restart = 1,
518 .aux_len_reg = 1,
519 .timing_adjust = 1,
520 .dma_sync = 1,
521 .ltiming_adjust = 1,
522 .apdma_sync = 1,
523 .max_dma_support = 36,
524 };
525
526 static const struct of_device_id mtk_i2c_of_match[] = {
527 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
528 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
529 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
530 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
531 { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
532 { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
533 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
534 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
535 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
536 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
537 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
538 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
539 {}
540 };
541 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
542
mtk_i2c_readw(struct mtk_i2c * i2c,enum I2C_REGS_OFFSET reg)543 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
544 {
545 return readw(i2c->base + i2c->dev_comp->regs[reg]);
546 }
547
mtk_i2c_writew(struct mtk_i2c * i2c,u16 val,enum I2C_REGS_OFFSET reg)548 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
549 enum I2C_REGS_OFFSET reg)
550 {
551 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
552 }
553
mtk_i2c_init_hw(struct mtk_i2c * i2c)554 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
555 {
556 u16 control_reg;
557 u16 intr_stat_reg;
558 u16 ext_conf_val;
559
560 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
561 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
562 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
563
564 if (i2c->dev_comp->apdma_sync) {
565 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
566 udelay(10);
567 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
568 udelay(10);
569 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
570 i2c->pdmabase + OFFSET_RST);
571 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
572 OFFSET_SOFTRESET);
573 udelay(10);
574 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
575 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
576 } else {
577 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
578 udelay(50);
579 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
580 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
581 }
582
583 /* Set ioconfig */
584 if (i2c->use_push_pull)
585 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
586 else
587 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
588
589 if (i2c->dev_comp->dcm)
590 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
591
592 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
593 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
594 if (i2c->dev_comp->ltiming_adjust)
595 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
596
597 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
598 ext_conf_val = I2C_ST_START_CON;
599 else
600 ext_conf_val = I2C_FS_START_CON;
601
602 if (i2c->dev_comp->timing_adjust) {
603 ext_conf_val = i2c->ac_timing.ext;
604 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
605 OFFSET_CLOCK_DIV);
606 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
607 OFFSET_SCL_MIS_COMP_POINT);
608 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
609 OFFSET_SDA_TIMING);
610
611 if (i2c->dev_comp->ltiming_adjust) {
612 mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
613 OFFSET_TIMING);
614 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
615 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
616 OFFSET_LTIMING);
617 } else {
618 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
619 OFFSET_SCL_HIGH_LOW_RATIO);
620 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
621 OFFSET_HS_SCL_HIGH_LOW_RATIO);
622 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
623 OFFSET_STA_STO_AC_TIMING);
624 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
625 OFFSET_HS_STA_STO_AC_TIMING);
626 }
627 }
628 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
629
630 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
631 if (i2c->have_pmic)
632 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
633
634 control_reg = I2C_CONTROL_ACKERR_DET_EN |
635 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
636 if (i2c->dev_comp->dma_sync)
637 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
638
639 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
640 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
641 }
642
mtk_i2c_get_spec(unsigned int speed)643 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
644 {
645 if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
646 return &standard_mode_spec;
647 else if (speed <= I2C_MAX_FAST_MODE_FREQ)
648 return &fast_mode_spec;
649 else
650 return &fast_mode_plus_spec;
651 }
652
mtk_i2c_max_step_cnt(unsigned int target_speed)653 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
654 {
655 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
656 return MAX_HS_STEP_CNT_DIV;
657 else
658 return MAX_STEP_CNT_DIV;
659 }
660
mtk_i2c_get_clk_div_restri(struct mtk_i2c * i2c,unsigned int sample_cnt)661 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
662 unsigned int sample_cnt)
663 {
664 int clk_div_restri = 0;
665
666 if (i2c->dev_comp->ltiming_adjust == 0)
667 return 0;
668
669 if (sample_cnt == 1) {
670 if (i2c->ac_timing.inter_clk_div == 0)
671 clk_div_restri = 0;
672 else
673 clk_div_restri = 1;
674 } else {
675 if (i2c->ac_timing.inter_clk_div == 0)
676 clk_div_restri = -1;
677 else if (i2c->ac_timing.inter_clk_div == 1)
678 clk_div_restri = 0;
679 else
680 clk_div_restri = 1;
681 }
682
683 return clk_div_restri;
684 }
685
686 /*
687 * Check and Calculate i2c ac-timing
688 *
689 * Hardware design:
690 * sample_ns = (HZ_PER_GHZ * (sample_cnt + 1)) / clk_src
691 * xxx_cnt_div = spec->min_xxx_ns / sample_ns
692 *
693 * Sample_ns is rounded down for xxx_cnt_div would be greater
694 * than the smallest spec.
695 * The sda_timing is chosen as the middle value between
696 * the largest and smallest.
697 */
mtk_i2c_check_ac_timing(struct mtk_i2c * i2c,unsigned int clk_src,unsigned int check_speed,unsigned int step_cnt,unsigned int sample_cnt)698 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
699 unsigned int clk_src,
700 unsigned int check_speed,
701 unsigned int step_cnt,
702 unsigned int sample_cnt)
703 {
704 const struct i2c_spec_values *spec;
705 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
706 unsigned int sda_max, sda_min, max_sta_cnt = 0x3f;
707 unsigned int clk_ns, sample_ns;
708
709 if (!i2c->dev_comp->timing_adjust)
710 return 0;
711
712 if (i2c->dev_comp->ltiming_adjust)
713 max_sta_cnt = 0x100;
714
715 spec = mtk_i2c_get_spec(check_speed);
716
717 sample_ns = div_u64(1ULL * HZ_PER_GHZ * (sample_cnt + 1), clk_src);
718 if (i2c->dev_comp->ltiming_adjust)
719 clk_ns = HZ_PER_GHZ / clk_src;
720 else
721 clk_ns = sample_ns / 2;
722
723 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
724 i2c->timing_info.scl_int_delay_ns, clk_ns);
725 if (su_sta_cnt > max_sta_cnt)
726 return -1;
727
728 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
729 max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
730 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
731 if (low_cnt > step_cnt) {
732 high_cnt = 2 * step_cnt - low_cnt;
733 } else {
734 high_cnt = step_cnt;
735 low_cnt = step_cnt;
736 }
737 } else {
738 return -2;
739 }
740
741 sda_max = spec->max_hd_dat_ns / sample_ns;
742 if (sda_max > low_cnt)
743 sda_max = 0;
744
745 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
746 if (sda_min < low_cnt)
747 sda_min = 0;
748
749 if (sda_min > sda_max)
750 return -3;
751
752 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
753 if (i2c->dev_comp->ltiming_adjust) {
754 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
755 (sample_cnt << 12) | (high_cnt << 8);
756 i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
757 i2c->ac_timing.ltiming |= (sample_cnt << 12) |
758 (low_cnt << 9);
759 i2c->ac_timing.ext &= ~GENMASK(7, 1);
760 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
761 } else {
762 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
763 (high_cnt << 6) | low_cnt;
764 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
765 su_sta_cnt;
766 }
767 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
768 i2c->ac_timing.sda_timing |= (1 << 12) |
769 ((sda_max + sda_min) / 2) << 6;
770 } else {
771 if (i2c->dev_comp->ltiming_adjust) {
772 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
773 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
774 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
775 } else {
776 i2c->ac_timing.scl_hl_ratio = (1 << 12) |
777 (high_cnt << 6) | low_cnt;
778 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
779 su_sta_cnt;
780 }
781
782 i2c->ac_timing.sda_timing = (1 << 12) |
783 (sda_max + sda_min) / 2;
784 }
785
786 return 0;
787 }
788
789 /*
790 * Calculate i2c port speed
791 *
792 * Hardware design:
793 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
794 * clock_div: fixed in hardware, but may be various in different SoCs
795 *
796 * The calculation want to pick the highest bus frequency that is still
797 * less than or equal to i2c->speed_hz. The calculation try to get
798 * sample_cnt and step_cn
799 */
mtk_i2c_calculate_speed(struct mtk_i2c * i2c,unsigned int clk_src,unsigned int target_speed,unsigned int * timing_step_cnt,unsigned int * timing_sample_cnt)800 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
801 unsigned int target_speed,
802 unsigned int *timing_step_cnt,
803 unsigned int *timing_sample_cnt)
804 {
805 unsigned int step_cnt;
806 unsigned int sample_cnt;
807 unsigned int max_step_cnt;
808 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
809 unsigned int base_step_cnt;
810 unsigned int opt_div;
811 unsigned int best_mul;
812 unsigned int cnt_mul;
813 int ret = -EINVAL;
814 int clk_div_restri = 0;
815
816 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
817 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
818
819 max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
820 base_step_cnt = max_step_cnt;
821 /* Find the best combination */
822 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
823 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
824
825 /* Search for the best pair (sample_cnt, step_cnt) with
826 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
827 * 0 < step_cnt < max_step_cnt
828 * sample_cnt * step_cnt >= opt_div
829 * optimizing for sample_cnt * step_cnt being minimal
830 */
831 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
832 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
833 step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
834 cnt_mul = step_cnt * sample_cnt;
835 if (step_cnt > max_step_cnt)
836 continue;
837
838 if (cnt_mul < best_mul) {
839 ret = mtk_i2c_check_ac_timing(i2c, clk_src,
840 target_speed, step_cnt - 1, sample_cnt - 1);
841 if (ret)
842 continue;
843
844 best_mul = cnt_mul;
845 base_sample_cnt = sample_cnt;
846 base_step_cnt = step_cnt;
847 if (best_mul == (opt_div + clk_div_restri))
848 break;
849 }
850 }
851
852 if (ret)
853 return -EINVAL;
854
855 sample_cnt = base_sample_cnt;
856 step_cnt = base_step_cnt;
857
858 if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
859 target_speed) {
860 /* In this case, hardware can't support such
861 * low i2c_bus_freq
862 */
863 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
864 return -EINVAL;
865 }
866
867 *timing_step_cnt = step_cnt - 1;
868 *timing_sample_cnt = sample_cnt - 1;
869
870 return 0;
871 }
872
mtk_i2c_set_speed(struct mtk_i2c * i2c,unsigned int parent_clk)873 static void mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
874 {
875 unsigned int clk_src;
876 unsigned int step_cnt;
877 unsigned int sample_cnt;
878 unsigned int l_step_cnt;
879 unsigned int l_sample_cnt;
880 unsigned int target_speed;
881 unsigned int clk_div;
882 unsigned int max_clk_div;
883 int ret;
884
885 target_speed = i2c->speed_hz;
886 parent_clk /= i2c->clk_src_div;
887
888 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
889 max_clk_div = MAX_CLOCK_DIV_5BITS;
890 else if (i2c->dev_comp->timing_adjust)
891 max_clk_div = MAX_CLOCK_DIV_8BITS;
892 else
893 max_clk_div = 1;
894
895 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
896 clk_src = parent_clk / clk_div;
897 i2c->ac_timing.inter_clk_div = clk_div - 1;
898
899 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
900 /* Set master code speed register */
901 ret = mtk_i2c_calculate_speed(i2c, clk_src,
902 I2C_MAX_FAST_MODE_FREQ,
903 &l_step_cnt,
904 &l_sample_cnt);
905 if (ret < 0)
906 continue;
907
908 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
909
910 /* Set the high speed mode register */
911 ret = mtk_i2c_calculate_speed(i2c, clk_src,
912 target_speed, &step_cnt,
913 &sample_cnt);
914 if (ret < 0)
915 continue;
916
917 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
918 (sample_cnt << 12) | (step_cnt << 8);
919
920 if (i2c->dev_comp->ltiming_adjust)
921 i2c->ltiming_reg =
922 (l_sample_cnt << 6) | l_step_cnt |
923 (sample_cnt << 12) | (step_cnt << 9);
924 } else {
925 ret = mtk_i2c_calculate_speed(i2c, clk_src,
926 target_speed, &l_step_cnt,
927 &l_sample_cnt);
928 if (ret < 0)
929 continue;
930
931 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
932
933 /* Disable the high speed transaction */
934 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
935
936 if (i2c->dev_comp->ltiming_adjust)
937 i2c->ltiming_reg =
938 (l_sample_cnt << 6) | l_step_cnt;
939 }
940
941 break;
942 }
943 }
944
i2c_dump_register(struct mtk_i2c * i2c)945 static void i2c_dump_register(struct mtk_i2c *i2c)
946 {
947 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
948 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
949 mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
950 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
951 mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
952 mtk_i2c_readw(i2c, OFFSET_CONTROL));
953 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
954 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
955 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
956 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
957 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
958 mtk_i2c_readw(i2c, OFFSET_TIMING));
959 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
960 mtk_i2c_readw(i2c, OFFSET_START),
961 mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
962 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
963 mtk_i2c_readw(i2c, OFFSET_HS),
964 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
965 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
966 mtk_i2c_readw(i2c, OFFSET_DCM_EN),
967 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
968 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
969 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
970 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
971 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
972 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
973 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
974 if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
975 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
976 mtk_i2c_readw(i2c, OFFSET_LTIMING),
977 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
978 }
979 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
980 readl(i2c->pdmabase + OFFSET_INT_FLAG),
981 readl(i2c->pdmabase + OFFSET_INT_EN));
982 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
983 readl(i2c->pdmabase + OFFSET_EN),
984 readl(i2c->pdmabase + OFFSET_CON));
985 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
986 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
987 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
988 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
989 readl(i2c->pdmabase + OFFSET_TX_LEN),
990 readl(i2c->pdmabase + OFFSET_RX_LEN));
991 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
992 readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
993 readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
994 }
995
mtk_i2c_do_transfer(struct mtk_i2c * i2c,struct i2c_msg * msgs,int num,int left_num)996 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
997 int num, int left_num)
998 {
999 u16 addr_reg;
1000 u16 start_reg;
1001 u16 control_reg;
1002 u16 restart_flag = 0;
1003 u16 dma_sync = 0;
1004 u32 reg_4g_mode;
1005 u32 reg_dma_reset;
1006 u8 *dma_rd_buf = NULL;
1007 u8 *dma_wr_buf = NULL;
1008 dma_addr_t rpaddr = 0;
1009 dma_addr_t wpaddr = 0;
1010 int ret;
1011
1012 i2c->irq_stat = 0;
1013
1014 if (i2c->auto_restart)
1015 restart_flag = I2C_RS_TRANSFER;
1016
1017 reinit_completion(&i2c->msg_complete);
1018
1019 if (i2c->dev_comp->apdma_sync &&
1020 i2c->op != I2C_MASTER_WRRD && num > 1) {
1021 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
1022 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
1023 i2c->pdmabase + OFFSET_RST);
1024
1025 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
1026 reg_dma_reset,
1027 !(reg_dma_reset & I2C_DMA_WARM_RST),
1028 0, 100);
1029 if (ret) {
1030 dev_err(i2c->dev, "DMA warm reset timeout\n");
1031 return -ETIMEDOUT;
1032 }
1033
1034 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
1035 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
1036 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
1037 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
1038 OFFSET_DEBUGCTRL);
1039 }
1040
1041 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
1042 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
1043 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
1044 control_reg |= I2C_CONTROL_RS;
1045
1046 if (i2c->op == I2C_MASTER_WRRD)
1047 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
1048
1049 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
1050
1051 addr_reg = i2c_8bit_addr_from_msg(msgs);
1052 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
1053
1054 /* Clear interrupt status */
1055 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1056 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
1057
1058 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
1059
1060 /* Enable interrupt */
1061 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1062 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
1063
1064 /* Set transfer and transaction len */
1065 if (i2c->op == I2C_MASTER_WRRD) {
1066 if (i2c->dev_comp->aux_len_reg) {
1067 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1068 mtk_i2c_writew(i2c, (msgs + 1)->len,
1069 OFFSET_TRANSFER_LEN_AUX);
1070 } else {
1071 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
1072 OFFSET_TRANSFER_LEN);
1073 }
1074 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
1075 } else {
1076 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1077 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
1078 }
1079
1080 if (i2c->dev_comp->apdma_sync) {
1081 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
1082 if (i2c->op == I2C_MASTER_WRRD)
1083 dma_sync |= I2C_DMA_DIR_CHANGE;
1084 }
1085
1086 /* Prepare buffer data to start transfer */
1087 if (i2c->op == I2C_MASTER_RD) {
1088 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1089 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
1090
1091 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1092 if (!dma_rd_buf)
1093 return -ENOMEM;
1094
1095 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1096 msgs->len, DMA_FROM_DEVICE);
1097 if (dma_mapping_error(i2c->dev, rpaddr)) {
1098 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
1099
1100 return -ENOMEM;
1101 }
1102
1103 if (i2c->dev_comp->max_dma_support > 32) {
1104 reg_4g_mode = upper_32_bits(rpaddr);
1105 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1106 }
1107
1108 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1109 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
1110 } else if (i2c->op == I2C_MASTER_WR) {
1111 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1112 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
1113
1114 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1115 if (!dma_wr_buf)
1116 return -ENOMEM;
1117
1118 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1119 msgs->len, DMA_TO_DEVICE);
1120 if (dma_mapping_error(i2c->dev, wpaddr)) {
1121 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1122
1123 return -ENOMEM;
1124 }
1125
1126 if (i2c->dev_comp->max_dma_support > 32) {
1127 reg_4g_mode = upper_32_bits(wpaddr);
1128 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1129 }
1130
1131 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1132 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1133 } else {
1134 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
1135 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
1136
1137 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1138 if (!dma_wr_buf)
1139 return -ENOMEM;
1140
1141 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1142 msgs->len, DMA_TO_DEVICE);
1143 if (dma_mapping_error(i2c->dev, wpaddr)) {
1144 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1145
1146 return -ENOMEM;
1147 }
1148
1149 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
1150 if (!dma_rd_buf) {
1151 dma_unmap_single(i2c->dev, wpaddr,
1152 msgs->len, DMA_TO_DEVICE);
1153
1154 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1155
1156 return -ENOMEM;
1157 }
1158
1159 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1160 (msgs + 1)->len,
1161 DMA_FROM_DEVICE);
1162 if (dma_mapping_error(i2c->dev, rpaddr)) {
1163 dma_unmap_single(i2c->dev, wpaddr,
1164 msgs->len, DMA_TO_DEVICE);
1165
1166 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1167 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
1168
1169 return -ENOMEM;
1170 }
1171
1172 if (i2c->dev_comp->max_dma_support > 32) {
1173 reg_4g_mode = upper_32_bits(wpaddr);
1174 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1175
1176 reg_4g_mode = upper_32_bits(rpaddr);
1177 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1178 }
1179
1180 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1181 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1182 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1183 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1184 }
1185
1186 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1187
1188 if (!i2c->auto_restart) {
1189 start_reg = I2C_TRANSAC_START;
1190 } else {
1191 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1192 if (left_num >= 1)
1193 start_reg |= I2C_RS_MUL_CNFG;
1194 }
1195 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1196
1197 ret = wait_for_completion_timeout(&i2c->msg_complete,
1198 i2c->adap.timeout);
1199
1200 /* Clear interrupt mask */
1201 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1202 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1203
1204 if (i2c->op == I2C_MASTER_WR) {
1205 dma_unmap_single(i2c->dev, wpaddr,
1206 msgs->len, DMA_TO_DEVICE);
1207
1208 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1209 } else if (i2c->op == I2C_MASTER_RD) {
1210 dma_unmap_single(i2c->dev, rpaddr,
1211 msgs->len, DMA_FROM_DEVICE);
1212
1213 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1214 } else {
1215 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1216 DMA_TO_DEVICE);
1217 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1218 DMA_FROM_DEVICE);
1219
1220 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1221 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1222 }
1223
1224 if (ret == 0) {
1225 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1226 i2c_dump_register(i2c);
1227 mtk_i2c_init_hw(i2c);
1228 return -ETIMEDOUT;
1229 }
1230
1231 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1232 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1233 mtk_i2c_init_hw(i2c);
1234 return -ENXIO;
1235 }
1236
1237 return 0;
1238 }
1239
mtk_i2c_transfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1240 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1241 struct i2c_msg msgs[], int num)
1242 {
1243 int ret;
1244 int left_num = num;
1245 bool write_then_read_en = false;
1246 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1247
1248 if (i2c->adap.bus_regulator) {
1249 ret = regulator_enable(i2c->adap.bus_regulator);
1250 if (ret)
1251 return ret;
1252 }
1253
1254 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1255 if (ret)
1256 goto err_regulator;
1257
1258 i2c->auto_restart = i2c->dev_comp->auto_restart;
1259
1260 /* checking if we can skip restart and optimize using WRRD mode */
1261 if (num == 2) {
1262 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1263 msgs[0].addr == msgs[1].addr) {
1264 i2c->auto_restart = 0;
1265 write_then_read_en = true;
1266 }
1267 }
1268
1269 if (i2c->auto_restart && num >= 2 &&
1270 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1271 /* ignore the first restart irq after the master code,
1272 * otherwise the first transfer will be discarded.
1273 */
1274 i2c->ignore_restart_irq = true;
1275 else
1276 i2c->ignore_restart_irq = false;
1277
1278 while (left_num--) {
1279 if (!msgs->buf) {
1280 dev_dbg(i2c->dev, "data buffer is NULL.\n");
1281 ret = -EINVAL;
1282 goto err_exit;
1283 }
1284
1285 if (msgs->flags & I2C_M_RD)
1286 i2c->op = I2C_MASTER_RD;
1287 else
1288 i2c->op = I2C_MASTER_WR;
1289
1290 if (write_then_read_en) {
1291 /* combined two messages into one transaction */
1292 i2c->op = I2C_MASTER_WRRD;
1293 left_num--;
1294 }
1295
1296 /* always use DMA mode. */
1297 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1298 if (ret < 0)
1299 goto err_exit;
1300
1301 if (i2c->op == I2C_MASTER_WRRD)
1302 msgs += 2;
1303 else
1304 msgs++;
1305 }
1306 /* the return value is number of executed messages */
1307 ret = num;
1308
1309 err_exit:
1310 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1311 err_regulator:
1312 if (i2c->adap.bus_regulator)
1313 regulator_disable(i2c->adap.bus_regulator);
1314
1315 return ret;
1316 }
1317
mtk_i2c_irq(int irqno,void * dev_id)1318 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1319 {
1320 struct mtk_i2c *i2c = dev_id;
1321 u16 restart_flag = i2c->auto_restart ? I2C_RS_TRANSFER : 0;
1322 u16 intr_stat;
1323
1324 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1325 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1326
1327 /*
1328 * when occurs ack error, i2c controller generate two interrupts
1329 * first is the ack error interrupt, then the complete interrupt
1330 * i2c->irq_stat need keep the two interrupt value.
1331 */
1332 i2c->irq_stat |= intr_stat;
1333
1334 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1335 i2c->ignore_restart_irq = false;
1336 i2c->irq_stat = 0;
1337 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1338 I2C_TRANSAC_START, OFFSET_START);
1339 } else {
1340 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1341 complete(&i2c->msg_complete);
1342 }
1343
1344 return IRQ_HANDLED;
1345 }
1346
mtk_i2c_functionality(struct i2c_adapter * adap)1347 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1348 {
1349 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1350 return I2C_FUNC_I2C |
1351 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1352 else
1353 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1354 }
1355
1356 static const struct i2c_algorithm mtk_i2c_algorithm = {
1357 .xfer = mtk_i2c_transfer,
1358 .functionality = mtk_i2c_functionality,
1359 };
1360
mtk_i2c_parse_dt(struct device_node * np,struct mtk_i2c * i2c)1361 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1362 {
1363 int ret;
1364
1365 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1366 if (ret < 0)
1367 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1368
1369 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1370 if (ret < 0)
1371 return ret;
1372
1373 if (i2c->clk_src_div == 0)
1374 return -EINVAL;
1375
1376 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1377 i2c->use_push_pull =
1378 of_property_read_bool(np, "mediatek,use-push-pull");
1379
1380 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1381
1382 return 0;
1383 }
1384
mtk_i2c_probe(struct platform_device * pdev)1385 static int mtk_i2c_probe(struct platform_device *pdev)
1386 {
1387 int ret = 0;
1388 struct mtk_i2c *i2c;
1389 int i, irq, speed_clk;
1390
1391 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1392 if (!i2c)
1393 return -ENOMEM;
1394
1395 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1396 if (IS_ERR(i2c->base))
1397 return PTR_ERR(i2c->base);
1398
1399 i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
1400 if (IS_ERR(i2c->pdmabase))
1401 return PTR_ERR(i2c->pdmabase);
1402
1403 irq = platform_get_irq(pdev, 0);
1404 if (irq < 0)
1405 return irq;
1406
1407 init_completion(&i2c->msg_complete);
1408
1409 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1410 i2c->adap.dev.of_node = pdev->dev.of_node;
1411 i2c->dev = &pdev->dev;
1412 i2c->adap.dev.parent = &pdev->dev;
1413 i2c->adap.owner = THIS_MODULE;
1414 i2c->adap.algo = &mtk_i2c_algorithm;
1415 i2c->adap.quirks = i2c->dev_comp->quirks;
1416 i2c->adap.timeout = 2 * HZ;
1417 i2c->adap.retries = 1;
1418 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
1419 if (IS_ERR(i2c->adap.bus_regulator)) {
1420 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV)
1421 i2c->adap.bus_regulator = NULL;
1422 else
1423 return PTR_ERR(i2c->adap.bus_regulator);
1424 }
1425
1426 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1427 if (ret)
1428 return -EINVAL;
1429
1430 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1431 return -EINVAL;
1432
1433 /* Fill in clk-bulk IDs */
1434 for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
1435 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
1436
1437 /* Get clocks one by one, some may be optional */
1438 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
1439 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
1440 dev_err(&pdev->dev, "cannot get main clock\n");
1441 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
1442 }
1443
1444 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
1445 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
1446 dev_err(&pdev->dev, "cannot get dma clock\n");
1447 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
1448 }
1449
1450 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
1451 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
1452 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
1453
1454 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
1455 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
1456 dev_err(&pdev->dev, "cannot get pmic clock\n");
1457 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
1458 }
1459
1460 if (i2c->have_pmic) {
1461 if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
1462 dev_err(&pdev->dev, "cannot get pmic clock\n");
1463 return -ENODEV;
1464 }
1465 speed_clk = I2C_MT65XX_CLK_PMIC;
1466 } else {
1467 speed_clk = I2C_MT65XX_CLK_MAIN;
1468 }
1469
1470 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1471
1472 mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
1473
1474 if (i2c->dev_comp->max_dma_support > 32) {
1475 ret = dma_set_mask(&pdev->dev,
1476 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1477 if (ret) {
1478 dev_err(&pdev->dev, "dma_set_mask return error.\n");
1479 return ret;
1480 }
1481 }
1482
1483 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1484 if (ret) {
1485 dev_err(&pdev->dev, "clock enable failed!\n");
1486 return ret;
1487 }
1488 mtk_i2c_init_hw(i2c);
1489 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1490
1491 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1492 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1493 dev_name(&pdev->dev), i2c);
1494 if (ret < 0) {
1495 dev_err(&pdev->dev,
1496 "Request I2C IRQ %d fail\n", irq);
1497 goto err_bulk_unprepare;
1498 }
1499
1500 i2c_set_adapdata(&i2c->adap, i2c);
1501 ret = i2c_add_adapter(&i2c->adap);
1502 if (ret)
1503 goto err_bulk_unprepare;
1504
1505 platform_set_drvdata(pdev, i2c);
1506
1507 return 0;
1508
1509 err_bulk_unprepare:
1510 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1511
1512 return ret;
1513 }
1514
mtk_i2c_remove(struct platform_device * pdev)1515 static void mtk_i2c_remove(struct platform_device *pdev)
1516 {
1517 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1518
1519 i2c_del_adapter(&i2c->adap);
1520
1521 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1522 }
1523
mtk_i2c_suspend_noirq(struct device * dev)1524 static int mtk_i2c_suspend_noirq(struct device *dev)
1525 {
1526 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1527
1528 i2c_mark_adapter_suspended(&i2c->adap);
1529 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1530
1531 return 0;
1532 }
1533
mtk_i2c_resume_noirq(struct device * dev)1534 static int mtk_i2c_resume_noirq(struct device *dev)
1535 {
1536 int ret;
1537 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1538
1539 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1540 if (ret) {
1541 dev_err(dev, "clock enable failed!\n");
1542 return ret;
1543 }
1544
1545 mtk_i2c_init_hw(i2c);
1546
1547 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1548
1549 i2c_mark_adapter_resumed(&i2c->adap);
1550
1551 return 0;
1552 }
1553
1554 static const struct dev_pm_ops mtk_i2c_pm = {
1555 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1556 mtk_i2c_resume_noirq)
1557 };
1558
1559 static struct platform_driver mtk_i2c_driver = {
1560 .probe = mtk_i2c_probe,
1561 .remove = mtk_i2c_remove,
1562 .driver = {
1563 .name = I2C_DRV_NAME,
1564 .pm = pm_sleep_ptr(&mtk_i2c_pm),
1565 .of_match_table = mtk_i2c_of_match,
1566 },
1567 };
1568
1569 module_platform_driver(mtk_i2c_driver);
1570
1571 MODULE_LICENSE("GPL v2");
1572 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1573 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
1574