1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/module.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "fw.h"
9 #include "tx.h"
10 #include "rx.h"
11 #include "phy.h"
12 #include "rtw8822b.h"
13 #include "rtw8822b_table.h"
14 #include "mac.h"
15 #include "reg.h"
16 #include "debug.h"
17 #include "bf.h"
18 #include "regd.h"
19
20 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
21 u8 rx_path, bool is_tx2_path);
22
rtw8822be_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)23 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8822b_efuse *map)
25 {
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27 }
28
rtw8822bu_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)29 static void rtw8822bu_efuse_parsing(struct rtw_efuse *efuse,
30 struct rtw8822b_efuse *map)
31 {
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
33 }
34
rtw8822bs_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)35 static void rtw8822bs_efuse_parsing(struct rtw_efuse *efuse,
36 struct rtw8822b_efuse *map)
37 {
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
39 }
40
rtw8822b_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)41 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
42 {
43 struct rtw_efuse *efuse = &rtwdev->efuse;
44 struct rtw8822b_efuse *map;
45 int i;
46
47 map = (struct rtw8822b_efuse *)log_map;
48
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7));
50 efuse->rfe_option = map->rfe_option;
51 efuse->rf_board_option = map->rf_board_option;
52 efuse->crystal_cap = map->xtal_k;
53 efuse->pa_type_2g = map->pa_type;
54 efuse->pa_type_5g = map->pa_type;
55 efuse->lna_type_2g = map->lna_type_2g[0];
56 efuse->lna_type_5g = map->lna_type_5g[0];
57 efuse->channel_plan = map->channel_plan;
58 efuse->country_code[0] = map->country_code[0];
59 efuse->country_code[1] = map->country_code[1];
60 efuse->bt_setting = map->rf_bt_setting;
61 efuse->regd = map->rf_board_option & 0x7;
62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
63 efuse->thermal_meter_k = map->thermal_meter;
64
65 for (i = 0; i < 4; i++)
66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
67
68 switch (rtw_hci_type(rtwdev)) {
69 case RTW_HCI_TYPE_PCIE:
70 rtw8822be_efuse_parsing(efuse, map);
71 break;
72 case RTW_HCI_TYPE_USB:
73 rtw8822bu_efuse_parsing(efuse, map);
74 break;
75 case RTW_HCI_TYPE_SDIO:
76 rtw8822bs_efuse_parsing(efuse, map);
77 break;
78 default:
79 /* unsupported now */
80 return -ENOTSUPP;
81 }
82
83 return 0;
84 }
85
rtw8822b_phy_rfe_init(struct rtw_dev * rtwdev)86 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev)
87 {
88 /* chip top mux */
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
92
93 /* from s0 or s1 */
94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
96
97 /* input or output */
98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
100 }
101
102 #define RTW_TXSCALE_SIZE 37
103 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = {
104 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
105 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
106 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
107 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
108 };
109
rtw8822b_get_swing_index(struct rtw_dev * rtwdev)110 static u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev)
111 {
112 u8 i = 0;
113 u32 swing, table_value;
114
115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000);
116 for (i = 0; i < RTW_TXSCALE_SIZE; i++) {
117 table_value = rtw8822b_txscale_tbl[i];
118 if (swing == table_value)
119 break;
120 }
121
122 return i;
123 }
124
rtw8822b_pwrtrack_init(struct rtw_dev * rtwdev)125 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev)
126 {
127 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
128 u8 swing_idx = rtw8822b_get_swing_index(rtwdev);
129 u8 path;
130
131 if (swing_idx >= RTW_TXSCALE_SIZE)
132 dm_info->default_ofdm_index = 24;
133 else
134 dm_info->default_ofdm_index = swing_idx;
135
136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
137 ewma_thermal_init(&dm_info->avg_thermal[path]);
138 dm_info->delta_power_index[path] = 0;
139 }
140 dm_info->pwr_trk_triggered = false;
141 dm_info->pwr_trk_init_trigger = true;
142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
143 }
144
rtw8822b_phy_bf_init(struct rtw_dev * rtwdev)145 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev)
146 {
147 rtw_bf_phy_init(rtwdev);
148 /* Grouping bitmap parameters */
149 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
150 }
151
rtw8822b_phy_set_param(struct rtw_dev * rtwdev)152 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
153 {
154 struct rtw_hal *hal = &rtwdev->hal;
155 u8 crystal_cap;
156 bool is_tx2_path;
157
158 /* power on BB/RF domain */
159 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
160 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
161 rtw_write8_set(rtwdev, REG_RF_CTRL,
162 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
163 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
164
165 /* pre init before header files config */
166 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
167
168 rtw_phy_load_tables(rtwdev);
169
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
173
174 /* post init after header files config */
175 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
176
177 is_tx2_path = false;
178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
179 is_tx2_path);
180 rtw_phy_init(rtwdev);
181
182 rtw8822b_phy_rfe_init(rtwdev);
183 rtw8822b_pwrtrack_init(rtwdev);
184
185 rtw8822b_phy_bf_init(rtwdev);
186 }
187
188 #define WLAN_SLOT_TIME 0x09
189 #define WLAN_PIFS_TIME 0x19
190 #define WLAN_SIFS_CCK_CONT_TX 0xA
191 #define WLAN_SIFS_OFDM_CONT_TX 0xE
192 #define WLAN_SIFS_CCK_TRX 0x10
193 #define WLAN_SIFS_OFDM_TRX 0x10
194 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
195 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
196 #define WLAN_RDG_NAV 0x05
197 #define WLAN_TXOP_NAV 0x1B
198 #define WLAN_CCK_RX_TSF 0x30
199 #define WLAN_OFDM_RX_TSF 0x30
200 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
201 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
202 #define WLAN_DRV_EARLY_INT 0x04
203 #define WLAN_BCN_DMA_TIME 0x02
204
205 #define WLAN_RX_FILTER0 0xFFFF
206 #define WLAN_RX_FILTER1 0x0FFF
207 #define WLAN_RX_FILTER2 0xFFFF
208 #define WLAN_RCR_CFG 0xE400220E
209 #define WLAN_RXPKT_MAX_SZ 12288
210 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
211
212 #define WLAN_AMPDU_MAX_TIME 0x70
213 #define WLAN_RTS_LEN_TH 0xFF
214 #define WLAN_RTS_TX_TIME_TH 0x08
215 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
216 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
217 #define FAST_EDCA_VO_TH 0x06
218 #define FAST_EDCA_VI_TH 0x06
219 #define FAST_EDCA_BE_TH 0x06
220 #define FAST_EDCA_BK_TH 0x06
221 #define WLAN_BAR_RETRY_LIMIT 0x01
222 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
223
224 #define WLAN_TX_FUNC_CFG1 0x30
225 #define WLAN_TX_FUNC_CFG2 0x30
226 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
227 #define WLAN_MAC_OPT_LB_FUNC1 0x80
228 #define WLAN_MAC_OPT_FUNC2 0xb0810041
229
230 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
231 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
232 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
233 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
234
235 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
236 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
237
238 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
239 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
240
rtw8822b_mac_init(struct rtw_dev * rtwdev)241 static int rtw8822b_mac_init(struct rtw_dev *rtwdev)
242 {
243 u32 value32;
244
245 /* protocol configuration */
246 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD);
247 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
248 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
249 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
250 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
251 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
252 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
253 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
254 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
255 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
256 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
257 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
258 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
259 /* EDCA configuration */
260 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
261 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
262 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
263 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
264 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
265 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
266 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
267 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
268 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
269 /* Set beacon cotnrol - enable TSF and other related functions */
270 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
271 /* Set send beacon related registers */
272 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
273 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
274 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
275 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
276 /* WMAC configuration */
277 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
278 rtwdev->hal.rxfltmap1 = WLAN_RX_FILTER1;
279 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
280 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
281 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
282 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
283 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
284 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
285 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
286 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
287 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
288 BIT_DIS_CHK_VHTSIGB_CRC);
289
290 return 0;
291 }
292
rtw8822b_set_channel_rfe_efem(struct rtw_dev * rtwdev,u8 channel)293 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel)
294 {
295 struct rtw_hal *hal = &rtwdev->hal;
296
297 if (IS_CH_2G_BAND(channel)) {
298 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
299 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
300 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
301 } else {
302 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
303 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
304 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
305 }
306
307 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
308
309 if (hal->antenna_rx == BB_PATH_AB ||
310 hal->antenna_tx == BB_PATH_AB) {
311 /* 2TX or 2RX */
312 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
313 } else if (hal->antenna_rx == hal->antenna_tx) {
314 /* TXA+RXA or TXB+RXB */
315 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
316 } else {
317 /* TXB+RXA or TXA+RXB */
318 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
319 }
320 }
321
rtw8822b_set_channel_rfe_ifem(struct rtw_dev * rtwdev,u8 channel)322 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel)
323 {
324 struct rtw_hal *hal = &rtwdev->hal;
325
326 if (IS_CH_2G_BAND(channel)) {
327 /* signal source */
328 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
329 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
330 } else {
331 /* signal source */
332 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
333 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
334 }
335
336 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
337
338 if (IS_CH_2G_BAND(channel)) {
339 if (hal->antenna_rx == BB_PATH_AB ||
340 hal->antenna_tx == BB_PATH_AB) {
341 /* 2TX or 2RX */
342 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
343 } else if (hal->antenna_rx == hal->antenna_tx) {
344 /* TXA+RXA or TXB+RXB */
345 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
346 } else {
347 /* TXB+RXA or TXA+RXB */
348 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
349 }
350 } else {
351 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
352 }
353 }
354
355 enum {
356 CCUT_IDX_1R_2G,
357 CCUT_IDX_2R_2G,
358 CCUT_IDX_1R_5G,
359 CCUT_IDX_2R_5G,
360 CCUT_IDX_NR,
361 };
362
363 struct cca_ccut {
364 u32 reg82c[CCUT_IDX_NR];
365 u32 reg830[CCUT_IDX_NR];
366 u32 reg838[CCUT_IDX_NR];
367 };
368
369 static const struct cca_ccut cca_ifem_ccut = {
370 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
371 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
372 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
373 };
374
375 static const struct cca_ccut cca_efem_ccut = {
376 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
377 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
378 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
379 };
380
381 static const struct cca_ccut cca_ifem_ccut_ext = {
382 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
383 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
384 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
385 };
386
rtw8822b_get_cca_val(const struct cca_ccut * cca_ccut,u8 col,u32 * reg82c,u32 * reg830,u32 * reg838)387 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col,
388 u32 *reg82c, u32 *reg830, u32 *reg838)
389 {
390 *reg82c = cca_ccut->reg82c[col];
391 *reg830 = cca_ccut->reg830[col];
392 *reg838 = cca_ccut->reg838[col];
393 }
394
395 struct rtw8822b_rfe_info {
396 const struct cca_ccut *cca_ccut_2g;
397 const struct cca_ccut *cca_ccut_5g;
398 enum rtw_rfe_fem fem;
399 bool ifem_ext;
400 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel);
401 };
402
403 #define I2GE5G_CCUT(set_ch) { \
404 .cca_ccut_2g = &cca_ifem_ccut, \
405 .cca_ccut_5g = &cca_efem_ccut, \
406 .fem = RTW_RFE_IFEM2G_EFEM5G, \
407 .ifem_ext = false, \
408 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
409 }
410 #define IFEM_EXT_CCUT(set_ch) { \
411 .cca_ccut_2g = &cca_ifem_ccut_ext, \
412 .cca_ccut_5g = &cca_ifem_ccut_ext, \
413 .fem = RTW_RFE_IFEM, \
414 .ifem_ext = true, \
415 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
416 }
417
418 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = {
419 [2] = I2GE5G_CCUT(efem),
420 [3] = IFEM_EXT_CCUT(ifem),
421 [5] = IFEM_EXT_CCUT(ifem),
422 };
423
rtw8822b_set_channel_cca(struct rtw_dev * rtwdev,u8 channel,u8 bw,const struct rtw8822b_rfe_info * rfe_info)424 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw,
425 const struct rtw8822b_rfe_info *rfe_info)
426 {
427 struct rtw_hal *hal = &rtwdev->hal;
428 struct rtw_efuse *efuse = &rtwdev->efuse;
429 const struct cca_ccut *cca_ccut;
430 u8 col;
431 u32 reg82c, reg830, reg838;
432 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
433
434 if (IS_CH_2G_BAND(channel)) {
435 cca_ccut = rfe_info->cca_ccut_2g;
436
437 if (hal->antenna_rx == BB_PATH_A ||
438 hal->antenna_rx == BB_PATH_B)
439 col = CCUT_IDX_1R_2G;
440 else
441 col = CCUT_IDX_2R_2G;
442 } else {
443 cca_ccut = rfe_info->cca_ccut_5g;
444
445 if (hal->antenna_rx == BB_PATH_A ||
446 hal->antenna_rx == BB_PATH_B)
447 col = CCUT_IDX_1R_5G;
448 else
449 col = CCUT_IDX_2R_5G;
450 }
451
452 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838);
453
454 switch (rfe_info->fem) {
455 case RTW_RFE_IFEM:
456 default:
457 is_ifem_cca = true;
458 if (rfe_info->ifem_ext)
459 is_rfe_type = true;
460 break;
461 case RTW_RFE_EFEM:
462 is_efem_cca = true;
463 break;
464 case RTW_RFE_IFEM2G_EFEM5G:
465 if (IS_CH_2G_BAND(channel))
466 is_ifem_cca = true;
467 else
468 is_efem_cca = true;
469 break;
470 }
471
472 if (is_ifem_cca) {
473 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
474 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) &&
475 bw == RTW_CHANNEL_WIDTH_40) ||
476 (!is_rfe_type && col == CCUT_IDX_2R_5G &&
477 bw == RTW_CHANNEL_WIDTH_40) ||
478 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
479 reg830 = 0x79a0ea28;
480 }
481
482 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c);
483 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830);
484 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838);
485
486 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
487 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
488
489 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel))
490 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
491 }
492
493 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
494 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
495 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
496 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
497 0x6, 0x5, 0x0, 0x0, 0x7};
498 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
499 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
500
rtw8822b_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)501 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
502 {
503 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
504 #define RF18_BAND_2G (0)
505 #define RF18_BAND_5G (BIT(16) | BIT(8))
506 #define RF18_CHANNEL_MASK (MASKBYTE0)
507 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
508 #define RF18_RFSI_GE_CH80 (BIT(17))
509 #define RF18_RFSI_GT_CH144 (BIT(18))
510 #define RF18_BW_MASK (BIT(11) | BIT(10))
511 #define RF18_BW_20M (BIT(11) | BIT(10))
512 #define RF18_BW_40M (BIT(11))
513 #define RF18_BW_80M (BIT(10))
514 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
515
516 struct rtw_hal *hal = &rtwdev->hal;
517 u32 rf_reg18, rf_reg_be;
518
519 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
520
521 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
522 RF18_BW_MASK);
523
524 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
525 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
526 if (channel > 144)
527 rf_reg18 |= RF18_RFSI_GT_CH144;
528 else if (channel >= 80)
529 rf_reg18 |= RF18_RFSI_GE_CH80;
530
531 switch (bw) {
532 case RTW_CHANNEL_WIDTH_5:
533 case RTW_CHANNEL_WIDTH_10:
534 case RTW_CHANNEL_WIDTH_20:
535 default:
536 rf_reg18 |= RF18_BW_20M;
537 break;
538 case RTW_CHANNEL_WIDTH_40:
539 rf_reg18 |= RF18_BW_40M;
540 break;
541 case RTW_CHANNEL_WIDTH_80:
542 rf_reg18 |= RF18_BW_80M;
543 break;
544 }
545
546 if (IS_CH_2G_BAND(channel))
547 rf_reg_be = 0x0;
548 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel))
549 rf_reg_be = low_band[(channel - 36) >> 1];
550 else if (IS_CH_5G_BAND_3(channel))
551 rf_reg_be = middle_band[(channel - 100) >> 1];
552 else if (IS_CH_5G_BAND_4(channel))
553 rf_reg_be = high_band[(channel - 149) >> 1];
554 else
555 goto err;
556
557 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be);
558
559 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
560 if (channel == 144)
561 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
562 else
563 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
564
565 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
566 if (hal->rf_type > RF_1T1R)
567 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
568
569 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
570 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
571
572 return;
573
574 err:
575 WARN_ON(1);
576 }
577
rtw8822b_toggle_igi(struct rtw_dev * rtwdev)578 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev)
579 {
580 struct rtw_hal *hal = &rtwdev->hal;
581 u32 igi;
582
583 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
584 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
585 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
586 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
587 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
588
589 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
590 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0,
591 hal->antenna_rx | (hal->antenna_rx << 4));
592 }
593
rtw8822b_set_channel_rxdfir(struct rtw_dev * rtwdev,u8 bw)594 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
595 {
596 if (bw == RTW_CHANNEL_WIDTH_40) {
597 /* RX DFIR for BW40 */
598 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
599 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
600 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
601 } else if (bw == RTW_CHANNEL_WIDTH_80) {
602 /* RX DFIR for BW80 */
603 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
604 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
605 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
606 } else {
607 /* RX DFIR for BW20, BW10 and BW5*/
608 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
609 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
610 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
611 }
612 }
613
rtw8822b_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)614 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
615 u8 primary_ch_idx)
616 {
617 struct rtw_efuse *efuse = &rtwdev->efuse;
618 u8 rfe_option = efuse->rfe_option;
619 u32 val32;
620
621 if (IS_CH_2G_BAND(channel)) {
622 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
623 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
624 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
625 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
626
627 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
628 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
629 if (channel == 14) {
630 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
631 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
632 } else {
633 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
634 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
635 }
636
637 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
638 } else if (IS_CH_5G_BAND(channel)) {
639 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
640 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
641 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
642 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
643
644 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel))
645 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
646 else if (IS_CH_5G_BAND_3(channel))
647 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
648 else if (IS_CH_5G_BAND_4(channel))
649 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
650
651 if (IS_CH_5G_BAND_1(channel))
652 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
653 else if (IS_CH_5G_BAND_2(channel))
654 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
655 else if (channel >= 100 && channel <= 116)
656 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
657 else if (channel >= 118 && channel <= 177)
658 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
659
660 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
661 }
662
663 switch (bw) {
664 case RTW_CHANNEL_WIDTH_20:
665 default:
666 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
667 val32 &= 0xFFCFFC00;
668 val32 |= (RTW_CHANNEL_WIDTH_20);
669 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
670
671 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
672 break;
673 case RTW_CHANNEL_WIDTH_40:
674 if (primary_ch_idx == RTW_SC_20_UPPER)
675 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
676 else
677 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
678
679 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
680 val32 &= 0xFF3FF300;
681 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
682 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
683
684 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
685 break;
686 case RTW_CHANNEL_WIDTH_80:
687 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
688 val32 &= 0xFCEFCF00;
689 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
690 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
691
692 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
693
694 if (rfe_option == 2 || rfe_option == 3) {
695 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
696 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
697 }
698 break;
699 case RTW_CHANNEL_WIDTH_5:
700 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
701 val32 &= 0xEFEEFE00;
702 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
703 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
704
705 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
706 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
707 break;
708 case RTW_CHANNEL_WIDTH_10:
709 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
710 val32 &= 0xEFFEFF00;
711 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
712 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
713
714 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
715 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
716 break;
717 }
718 }
719
rtw8822b_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)720 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
721 u8 primary_chan_idx)
722 {
723 struct rtw_efuse *efuse = &rtwdev->efuse;
724 const struct rtw8822b_rfe_info *rfe_info;
725
726 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
727 "rfe_option %d is out of boundary\n", efuse->rfe_option))
728 return;
729
730 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
731
732 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
733 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
734 rtw8822b_set_channel_rf(rtwdev, channel, bw);
735 rtw8822b_set_channel_rxdfir(rtwdev, bw);
736 rtw8822b_toggle_igi(rtwdev);
737 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info);
738 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
739 }
740
rtw8822b_config_trx_mode(struct rtw_dev * rtwdev,u8 tx_path,u8 rx_path,bool is_tx2_path)741 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
742 u8 rx_path, bool is_tx2_path)
743 {
744 struct rtw_efuse *efuse = &rtwdev->efuse;
745 const struct rtw8822b_rfe_info *rfe_info;
746 u8 ch = rtwdev->hal.current_channel;
747 u8 tx_path_sel, rx_path_sel;
748 int counter;
749
750 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
751 "rfe_option %d is out of boundary\n", efuse->rfe_option))
752 return;
753
754 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
755
756 if ((tx_path | rx_path) & BB_PATH_A)
757 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
758 else
759 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
760
761 if ((tx_path | rx_path) & BB_PATH_B)
762 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
763 else
764 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
765
766 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
767 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
768 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
769
770 if (tx_path & BB_PATH_A) {
771 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
772 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
773 } else if (tx_path & BB_PATH_B) {
774 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
775 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
776 }
777
778 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
779 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
780 else
781 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
782
783 tx_path_sel = (tx_path << 4) | tx_path;
784 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel);
785
786 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) {
787 if (is_tx2_path || rtwdev->mp_mode) {
788 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
789 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
790 }
791 }
792
793 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
794 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
795
796 if (rx_path & BB_PATH_A)
797 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
798 else if (rx_path & BB_PATH_B)
799 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
800
801 rx_path_sel = (rx_path << 4) | rx_path;
802 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel);
803
804 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
805 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
806 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
807 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
808 } else {
809 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
810 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
811 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
812 }
813
814 for (counter = 100; counter > 0; counter--) {
815 u32 rf_reg33;
816
817 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
818 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
819
820 udelay(2);
821 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
822
823 if (rf_reg33 == 0x00001)
824 break;
825 }
826
827 if (WARN(counter <= 0, "write RF mode table fail\n"))
828 return;
829
830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
833 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
834 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
835 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
836
837 rtw8822b_toggle_igi(rtwdev);
838 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info);
839 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
840 }
841
query_phy_status_page0(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)842 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
843 struct rtw_rx_pkt_stat *pkt_stat)
844 {
845 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
846 s8 min_rx_power = -120;
847 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
848
849 /* 8822B uses only 1 antenna to RX CCK rates */
850 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
851 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
852 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
853 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
854 min_rx_power);
855 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
856 }
857
query_phy_status_page1(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)858 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
859 struct rtw_rx_pkt_stat *pkt_stat)
860 {
861 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
862 u8 rxsc, bw;
863 s8 min_rx_power = -120;
864 s8 rx_evm;
865 u8 evm_dbm = 0;
866 u8 rssi;
867 int path;
868
869 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
870 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
871 else
872 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
873
874 if (rxsc >= 1 && rxsc <= 8)
875 bw = RTW_CHANNEL_WIDTH_20;
876 else if (rxsc >= 9 && rxsc <= 12)
877 bw = RTW_CHANNEL_WIDTH_40;
878 else if (rxsc >= 13)
879 bw = RTW_CHANNEL_WIDTH_80;
880 else
881 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
882
883 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
884 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
885 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
886 pkt_stat->bw = bw;
887 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
888 pkt_stat->rx_power[RF_PATH_B],
889 min_rx_power);
890
891 dm_info->curr_rx_rate = pkt_stat->rate;
892
893 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
894 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
895
896 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
897 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
898
899 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
900 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
901
902 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
903 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
904 dm_info->rssi[path] = rssi;
905 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
906 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
907
908 rx_evm = pkt_stat->rx_evm[path];
909
910 if (rx_evm < 0) {
911 if (rx_evm == S8_MIN)
912 evm_dbm = 0;
913 else
914 evm_dbm = ((u8)-rx_evm >> 1);
915 }
916 dm_info->rx_evm_dbm[path] = evm_dbm;
917 }
918 }
919
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)920 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
921 struct rtw_rx_pkt_stat *pkt_stat)
922 {
923 u8 page;
924
925 page = *phy_status & 0xf;
926
927 switch (page) {
928 case 0:
929 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
930 break;
931 case 1:
932 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
933 break;
934 default:
935 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
936 return;
937 }
938 }
939
940 static void
rtw8822b_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs,u32 * phy_pwr_idx)941 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
942 u8 rs, u32 *phy_pwr_idx)
943 {
944 struct rtw_hal *hal = &rtwdev->hal;
945 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
946 u8 rate, rate_idx, pwr_index, shift;
947 int j;
948
949 for (j = 0; j < rtw_rate_size[rs]; j++) {
950 rate = rtw_rate_section[rs][j];
951 pwr_index = hal->tx_pwr_tbl[path][rate];
952 shift = rate & 0x3;
953 *phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
954 if (shift == 0x3) {
955 rate_idx = rate & 0xfc;
956 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
957 *phy_pwr_idx);
958 *phy_pwr_idx = 0;
959 }
960 }
961 }
962
rtw8822b_set_tx_power_index(struct rtw_dev * rtwdev)963 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev)
964 {
965 struct rtw_hal *hal = &rtwdev->hal;
966 u32 phy_pwr_idx = 0;
967 int rs, path;
968
969 for (path = 0; path < hal->rf_path_num; path++) {
970 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++)
971 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs,
972 &phy_pwr_idx);
973 }
974 }
975
rtw8822b_check_rf_path(u8 antenna)976 static bool rtw8822b_check_rf_path(u8 antenna)
977 {
978 switch (antenna) {
979 case BB_PATH_A:
980 case BB_PATH_B:
981 case BB_PATH_AB:
982 return true;
983 default:
984 return false;
985 }
986 }
987
rtw8822b_set_antenna(struct rtw_dev * rtwdev,int radio_idx,u32 antenna_tx,u32 antenna_rx)988 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev,
989 int radio_idx,
990 u32 antenna_tx,
991 u32 antenna_rx)
992 {
993 struct rtw_hal *hal = &rtwdev->hal;
994
995 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
996 antenna_tx, antenna_rx);
997
998 if (!rtw8822b_check_rf_path(antenna_tx)) {
999 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
1000 return -EINVAL;
1001 }
1002
1003 if (!rtw8822b_check_rf_path(antenna_rx)) {
1004 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
1005 return -EINVAL;
1006 }
1007
1008 hal->antenna_tx = antenna_tx;
1009 hal->antenna_rx = antenna_rx;
1010
1011 if (test_bit(RTW_FLAG_POWERON, rtwdev->flags))
1012 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
1013
1014 return 0;
1015 }
1016
rtw8822b_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)1017 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1018 {
1019 u8 ldo_pwr;
1020
1021 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
1022 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN;
1023 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
1024 }
1025
rtw8822b_false_alarm_statistics(struct rtw_dev * rtwdev)1026 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
1027 {
1028 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1029 u32 cck_enable;
1030 u32 cck_fa_cnt;
1031 u32 ofdm_fa_cnt;
1032 u32 crc32_cnt;
1033 u32 cca32_cnt;
1034
1035 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
1036 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
1037 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
1038
1039 dm_info->cck_fa_cnt = cck_fa_cnt;
1040 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1041 dm_info->total_fa_cnt = ofdm_fa_cnt;
1042 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1043
1044 crc32_cnt = rtw_read32(rtwdev, 0xf04);
1045 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1046 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1047 crc32_cnt = rtw_read32(rtwdev, 0xf14);
1048 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1049 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1050 crc32_cnt = rtw_read32(rtwdev, 0xf10);
1051 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1052 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1053 crc32_cnt = rtw_read32(rtwdev, 0xf0c);
1054 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1055 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1056
1057 cca32_cnt = rtw_read32(rtwdev, 0xf08);
1058 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1059 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1060 if (cck_enable) {
1061 cca32_cnt = rtw_read32(rtwdev, 0xfcc);
1062 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1063 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1064 }
1065
1066 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
1067 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
1068 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
1069 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
1070 rtw_write32_set(rtwdev, 0xb58, BIT(0));
1071 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
1072 }
1073
rtw8822b_do_iqk(struct rtw_dev * rtwdev)1074 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
1075 {
1076 static int do_iqk_cnt;
1077 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
1078 u32 rf_reg, iqk_fail_mask;
1079 int counter;
1080 bool reload;
1081
1082 rtw_fw_do_iqk(rtwdev, ¶);
1083
1084 for (counter = 0; counter < 300; counter++) {
1085 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
1086 if (rf_reg == 0xabcde)
1087 break;
1088 msleep(20);
1089 }
1090 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
1091
1092 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
1093 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
1094 rtw_dbg(rtwdev, RTW_DBG_PHY,
1095 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1096 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
1097 }
1098
rtw8822b_phy_calibration(struct rtw_dev * rtwdev)1099 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev)
1100 {
1101 rtw8822b_do_iqk(rtwdev);
1102 }
1103
rtw8822b_coex_cfg_init(struct rtw_dev * rtwdev)1104 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
1105 {
1106 /* enable TBTT nterrupt */
1107 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1108
1109 /* BT report packet sample rate */
1110 /* 0x790[5:0]=0x5 */
1111 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
1112
1113 /* enable BT counter statistics */
1114 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1115
1116 /* enable PTA (3-wire function form BT side) */
1117 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1118 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
1119
1120 /* enable PTA (tx/rx signal form WiFi side) */
1121 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1122 /* wl tx signal to PTA not case EDCCA */
1123 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1124 /* GNT_BT=1 while select both */
1125 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
1126 }
1127
rtw8822b_coex_cfg_ant_switch(struct rtw_dev * rtwdev,u8 ctrl_type,u8 pos_type)1128 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
1129 u8 ctrl_type, u8 pos_type)
1130 {
1131 struct rtw_coex *coex = &rtwdev->coex;
1132 struct rtw_coex_dm *coex_dm = &coex->dm;
1133 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1134 bool polarity_inverse;
1135 u8 regval = 0;
1136
1137 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1138 return;
1139
1140 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1141
1142 if (coex_rfe->ant_switch_diversity &&
1143 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
1144 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
1145
1146 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1147
1148 switch (ctrl_type) {
1149 default:
1150 case COEX_SWITCH_CTRL_BY_BBSW:
1151 /* 0x4c[23] = 0 */
1152 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1153 /* 0x4c[24] = 1 */
1154 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1155 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1156 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1157
1158 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
1159 if (coex_rfe->rfe_module_type != 0x4 &&
1160 coex_rfe->rfe_module_type != 0x2)
1161 regval = 0x3;
1162 else
1163 regval = (!polarity_inverse ? 0x2 : 0x1);
1164 } else if (pos_type == COEX_SWITCH_TO_WLG) {
1165 regval = (!polarity_inverse ? 0x2 : 0x1);
1166 } else {
1167 regval = (!polarity_inverse ? 0x1 : 0x2);
1168 }
1169
1170 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1171 break;
1172 case COEX_SWITCH_CTRL_BY_PTA:
1173 /* 0x4c[23] = 0 */
1174 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1175 /* 0x4c[24] = 1 */
1176 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1177 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1178 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1179
1180 regval = (!polarity_inverse ? 0x2 : 0x1);
1181 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1182 break;
1183 case COEX_SWITCH_CTRL_BY_ANTDIV:
1184 /* 0x4c[23] = 0 */
1185 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1186 /* 0x4c[24] = 1 */
1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1188 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
1189 break;
1190 case COEX_SWITCH_CTRL_BY_MAC:
1191 /* 0x4c[23] = 1 */
1192 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
1193
1194 regval = (!polarity_inverse ? 0x0 : 0x1);
1195 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
1196 break;
1197 case COEX_SWITCH_CTRL_BY_FW:
1198 /* 0x4c[23] = 0 */
1199 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1200 /* 0x4c[24] = 1 */
1201 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1202 break;
1203 case COEX_SWITCH_CTRL_BY_BT:
1204 /* 0x4c[23] = 0 */
1205 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1206 /* 0x4c[24] = 0 */
1207 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
1208 break;
1209 }
1210 }
1211
rtw8822b_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)1212 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1213 {
1214 }
1215
rtw8822b_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)1216 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1217 {
1218 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
1219 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
1220 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
1221 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
1222 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
1223 }
1224
rtw8822b_coex_cfg_rfe_type(struct rtw_dev * rtwdev)1225 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1226 {
1227 struct rtw_coex *coex = &rtwdev->coex;
1228 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1229 struct rtw_efuse *efuse = &rtwdev->efuse;
1230 bool is_ext_fem = false;
1231
1232 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1233 coex_rfe->ant_switch_polarity = 0;
1234 coex_rfe->ant_switch_diversity = false;
1235 if (coex_rfe->rfe_module_type == 0x12 ||
1236 coex_rfe->rfe_module_type == 0x15 ||
1237 coex_rfe->rfe_module_type == 0x16)
1238 coex_rfe->ant_switch_exist = false;
1239 else
1240 coex_rfe->ant_switch_exist = true;
1241
1242 if (coex_rfe->rfe_module_type == 2 ||
1243 coex_rfe->rfe_module_type == 4) {
1244 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
1245 is_ext_fem = true;
1246 } else {
1247 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
1248 }
1249
1250 coex_rfe->wlg_at_btg = false;
1251
1252 if (efuse->share_ant &&
1253 coex_rfe->ant_switch_exist && !is_ext_fem)
1254 coex_rfe->ant_switch_with_bt = true;
1255 else
1256 coex_rfe->ant_switch_with_bt = false;
1257
1258 /* Ext switch buffer mux */
1259 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
1260 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
1261 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
1262
1263 /* Disable LTE Coex Function in WiFi side */
1264 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
1265
1266 /* BTC_CTT_WL_VS_LTE */
1267 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1268
1269 /* BTC_CTT_BT_VS_LTE */
1270 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1271 }
1272
rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1273 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1274 {
1275 struct rtw_coex *coex = &rtwdev->coex;
1276 struct rtw_coex_dm *coex_dm = &coex->dm;
1277 static const u16 reg_addr[] = {0xc58, 0xe58};
1278 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
1279 u8 i, pwr;
1280
1281 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1282 return;
1283
1284 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1285
1286 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1287 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1288
1289 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1290
1291 for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
1292 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
1293 }
1294
rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1295 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1296 {
1297 struct rtw_coex *coex = &rtwdev->coex;
1298 struct rtw_coex_dm *coex_dm = &coex->dm;
1299 /* WL Rx Low gain on */
1300 static const u32 wl_rx_low_gain_on[] = {
1301 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
1302 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
1303 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
1304 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
1305 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
1306 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
1307 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
1308 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
1309 0x007e0403
1310 };
1311
1312 /* WL Rx Low gain off */
1313 static const u32 wl_rx_low_gain_off[] = {
1314 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
1315 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
1316 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
1317 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
1318 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
1319 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
1320 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
1321 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
1322 0x007e0403
1323 };
1324 u8 i;
1325
1326 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1327 return;
1328
1329 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1330
1331 if (coex_dm->cur_wl_rx_low_gain_en) {
1332 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
1333 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1334 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
1335
1336 /* set Rx filter corner RCK offset */
1337 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
1338 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
1339 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
1340 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
1341 } else {
1342 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
1343 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1344 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
1345
1346 /* set Rx filter corner RCK offset */
1347 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
1348 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
1349 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
1350 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
1351 }
1352 }
1353
rtw8822b_txagc_swing_offset(struct rtw_dev * rtwdev,u8 path,u8 tx_pwr_idx_offset,s8 * txagc_idx,u8 * swing_idx)1354 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path,
1355 u8 tx_pwr_idx_offset,
1356 s8 *txagc_idx, u8 *swing_idx)
1357 {
1358 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1359 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1360 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1361 u8 swing_lower_bound = 0;
1362 u8 max_tx_pwr_idx_offset = 0xf;
1363 s8 agc_index = 0;
1364 u8 swing_index = dm_info->default_ofdm_index;
1365
1366 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset);
1367
1368 if (delta_pwr_idx >= 0) {
1369 if (delta_pwr_idx <= tx_pwr_idx_offset) {
1370 agc_index = delta_pwr_idx;
1371 swing_index = dm_info->default_ofdm_index;
1372 } else if (delta_pwr_idx > tx_pwr_idx_offset) {
1373 agc_index = tx_pwr_idx_offset;
1374 swing_index = dm_info->default_ofdm_index +
1375 delta_pwr_idx - tx_pwr_idx_offset;
1376 swing_index = min_t(u8, swing_index, swing_upper_bound);
1377 }
1378 } else {
1379 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1380 swing_index =
1381 dm_info->default_ofdm_index + delta_pwr_idx;
1382 else
1383 swing_index = swing_lower_bound;
1384 swing_index = max_t(u8, swing_index, swing_lower_bound);
1385
1386 agc_index = 0;
1387 }
1388
1389 if (swing_index >= RTW_TXSCALE_SIZE) {
1390 rtw_warn(rtwdev, "swing index overflow\n");
1391 swing_index = RTW_TXSCALE_SIZE - 1;
1392 }
1393 *txagc_idx = agc_index;
1394 *swing_idx = swing_index;
1395 }
1396
rtw8822b_pwrtrack_set_pwr(struct rtw_dev * rtwdev,u8 path,u8 pwr_idx_offset)1397 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path,
1398 u8 pwr_idx_offset)
1399 {
1400 s8 txagc_idx;
1401 u8 swing_idx;
1402 u32 reg1, reg2;
1403
1404 if (path == RF_PATH_A) {
1405 reg1 = 0xc94;
1406 reg2 = 0xc1c;
1407 } else if (path == RF_PATH_B) {
1408 reg1 = 0xe94;
1409 reg2 = 0xe1c;
1410 } else {
1411 return;
1412 }
1413
1414 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset,
1415 &txagc_idx, &swing_idx);
1416 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx);
1417 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21),
1418 rtw8822b_txscale_tbl[swing_idx]);
1419 }
1420
rtw8822b_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1421 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1422 {
1423 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1424 u8 pwr_idx_offset, tx_pwr_idx;
1425 u8 channel = rtwdev->hal.current_channel;
1426 u8 band_width = rtwdev->hal.current_band_width;
1427 u8 regd = rtw_regd_get(rtwdev);
1428 u8 tx_rate = dm_info->tx_rate;
1429 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1430
1431 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate,
1432 band_width, channel, regd);
1433
1434 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1435
1436 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1437
1438 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset);
1439 }
1440
rtw8822b_phy_pwrtrack_path(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 path)1441 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev,
1442 struct rtw_swing_table *swing_table,
1443 u8 path)
1444 {
1445 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1446 u8 power_idx_cur, power_idx_last;
1447 u8 delta;
1448
1449 /* 8822B only has one thermal meter at PATH A */
1450 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1451
1452 power_idx_last = dm_info->delta_power_index[path];
1453 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table,
1454 path, RF_PATH_A, delta);
1455
1456 /* if delta of power indexes are the same, just skip */
1457 if (power_idx_cur == power_idx_last)
1458 return;
1459
1460 dm_info->delta_power_index[path] = power_idx_cur;
1461 rtw8822b_pwrtrack_set(rtwdev, path);
1462 }
1463
rtw8822b_phy_pwrtrack(struct rtw_dev * rtwdev)1464 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev)
1465 {
1466 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1467 struct rtw_swing_table swing_table;
1468 u8 thermal_value, path;
1469
1470 rtw_phy_config_swing_table(rtwdev, &swing_table);
1471
1472 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1473 return;
1474
1475 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1476
1477 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1478
1479 if (dm_info->pwr_trk_init_trigger)
1480 dm_info->pwr_trk_init_trigger = false;
1481 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1482 RF_PATH_A))
1483 goto iqk;
1484
1485 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1486 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path);
1487
1488 iqk:
1489 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1490 rtw8822b_do_iqk(rtwdev);
1491 }
1492
rtw8822b_pwr_track(struct rtw_dev * rtwdev)1493 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev)
1494 {
1495 struct rtw_efuse *efuse = &rtwdev->efuse;
1496 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1497
1498 if (efuse->power_track_type != 0)
1499 return;
1500
1501 if (!dm_info->pwr_trk_triggered) {
1502 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1503 GENMASK(17, 16), 0x03);
1504 dm_info->pwr_trk_triggered = true;
1505 return;
1506 }
1507
1508 rtw8822b_phy_pwrtrack(rtwdev);
1509 dm_info->pwr_trk_triggered = false;
1510 }
1511
rtw8822b_bf_config_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1512 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev,
1513 struct rtw_vif *vif,
1514 struct rtw_bfee *bfee, bool enable)
1515 {
1516 if (enable)
1517 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1518 else
1519 rtw_bf_remove_bfee_su(rtwdev, bfee);
1520 }
1521
rtw8822b_bf_config_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1522 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1523 struct rtw_vif *vif,
1524 struct rtw_bfee *bfee, bool enable)
1525 {
1526 if (enable)
1527 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1528 else
1529 rtw_bf_remove_bfee_mu(rtwdev, bfee);
1530 }
1531
rtw8822b_bf_config_bfee(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1532 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1533 struct rtw_bfee *bfee, bool enable)
1534 {
1535 if (bfee->role == RTW_BFEE_SU)
1536 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1537 else if (bfee->role == RTW_BFEE_MU)
1538 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1539 else
1540 rtw_warn(rtwdev, "wrong bfee role\n");
1541 }
1542
rtw8822b_adaptivity_init(struct rtw_dev * rtwdev)1543 static void rtw8822b_adaptivity_init(struct rtw_dev *rtwdev)
1544 {
1545 rtw_phy_set_edcca_th(rtwdev, RTW8822B_EDCCA_MAX, RTW8822B_EDCCA_MAX);
1546
1547 /* mac edcca state setting */
1548 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
1549 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
1550 rtw_write32_mask(rtwdev, REG_EDCCA_SOURCE, BIT_SOURCE_OPTION,
1551 RTW8822B_EDCCA_SRC_DEF);
1552 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0);
1553
1554 /* edcca decision opt */
1555 rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
1556 }
1557
rtw8822b_adaptivity(struct rtw_dev * rtwdev)1558 static void rtw8822b_adaptivity(struct rtw_dev *rtwdev)
1559 {
1560 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1561 s8 l2h, h2l;
1562 u8 igi;
1563
1564 igi = dm_info->igi_history[0];
1565 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
1566 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB);
1567 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
1568 } else {
1569 l2h = min_t(s8, igi, dm_info->l2h_th_ini);
1570 h2l = l2h - EDCCA_L2H_H2L_DIFF;
1571 }
1572
1573 rtw_phy_set_edcca_th(rtwdev, l2h, h2l);
1574 }
1575
rtw8822b_led_set(struct led_classdev * led,enum led_brightness brightness)1576 static void rtw8822b_led_set(struct led_classdev *led,
1577 enum led_brightness brightness)
1578 {
1579 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
1580 u32 ledcfg;
1581
1582 ledcfg = rtw_read32(rtwdev, REG_LED_CFG);
1583 u32p_replace_bits(&ledcfg, BIT_LED_MODE_SW_CTRL, BIT_LED2_CM);
1584 ledcfg &= ~BIT_GPIO13_14_WL_CTRL_EN;
1585
1586 if (brightness == LED_OFF)
1587 ledcfg |= BIT_LED2_SV;
1588 else
1589 ledcfg &= ~BIT_LED2_SV;
1590
1591 rtw_write32(rtwdev, REG_LED_CFG, ledcfg);
1592 }
1593
rtw8822b_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)1594 static void rtw8822b_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1595 struct rtw_tx_pkt_info *pkt_info,
1596 u8 *txdesc)
1597 {
1598 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
1599
1600 fill_txdesc_checksum_common(txdesc, words);
1601 }
1602
1603 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
1604 {0x0086,
1605 RTW_PWR_CUT_ALL_MSK,
1606 RTW_PWR_INTF_SDIO_MSK,
1607 RTW_PWR_ADDR_SDIO,
1608 RTW_PWR_CMD_WRITE, BIT(0), 0},
1609 {0x0086,
1610 RTW_PWR_CUT_ALL_MSK,
1611 RTW_PWR_INTF_SDIO_MSK,
1612 RTW_PWR_ADDR_SDIO,
1613 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1614 {0x004A,
1615 RTW_PWR_CUT_ALL_MSK,
1616 RTW_PWR_INTF_USB_MSK,
1617 RTW_PWR_ADDR_MAC,
1618 RTW_PWR_CMD_WRITE, BIT(0), 0},
1619 {0x0005,
1620 RTW_PWR_CUT_ALL_MSK,
1621 RTW_PWR_INTF_ALL_MSK,
1622 RTW_PWR_ADDR_MAC,
1623 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1624 {0x0300,
1625 RTW_PWR_CUT_ALL_MSK,
1626 RTW_PWR_INTF_PCI_MSK,
1627 RTW_PWR_ADDR_MAC,
1628 RTW_PWR_CMD_WRITE, 0xFF, 0},
1629 {0x0301,
1630 RTW_PWR_CUT_ALL_MSK,
1631 RTW_PWR_INTF_PCI_MSK,
1632 RTW_PWR_ADDR_MAC,
1633 RTW_PWR_CMD_WRITE, 0xFF, 0},
1634 {0xFFFF,
1635 RTW_PWR_CUT_ALL_MSK,
1636 RTW_PWR_INTF_ALL_MSK,
1637 0,
1638 RTW_PWR_CMD_END, 0, 0},
1639 };
1640
1641 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = {
1642 {0x0012,
1643 RTW_PWR_CUT_ALL_MSK,
1644 RTW_PWR_INTF_ALL_MSK,
1645 RTW_PWR_ADDR_MAC,
1646 RTW_PWR_CMD_WRITE, BIT(1), 0},
1647 {0x0012,
1648 RTW_PWR_CUT_ALL_MSK,
1649 RTW_PWR_INTF_ALL_MSK,
1650 RTW_PWR_ADDR_MAC,
1651 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1652 {0x0020,
1653 RTW_PWR_CUT_ALL_MSK,
1654 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1655 RTW_PWR_ADDR_MAC,
1656 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1657 {0x0001,
1658 RTW_PWR_CUT_ALL_MSK,
1659 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1660 RTW_PWR_ADDR_MAC,
1661 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1662 {0x0000,
1663 RTW_PWR_CUT_ALL_MSK,
1664 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1665 RTW_PWR_ADDR_MAC,
1666 RTW_PWR_CMD_WRITE, BIT(5), 0},
1667 {0x0005,
1668 RTW_PWR_CUT_ALL_MSK,
1669 RTW_PWR_INTF_ALL_MSK,
1670 RTW_PWR_ADDR_MAC,
1671 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1672 {0x0075,
1673 RTW_PWR_CUT_ALL_MSK,
1674 RTW_PWR_INTF_PCI_MSK,
1675 RTW_PWR_ADDR_MAC,
1676 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1677 {0x0006,
1678 RTW_PWR_CUT_ALL_MSK,
1679 RTW_PWR_INTF_ALL_MSK,
1680 RTW_PWR_ADDR_MAC,
1681 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1682 {0x0075,
1683 RTW_PWR_CUT_ALL_MSK,
1684 RTW_PWR_INTF_PCI_MSK,
1685 RTW_PWR_ADDR_MAC,
1686 RTW_PWR_CMD_WRITE, BIT(0), 0},
1687 {0xFF1A,
1688 RTW_PWR_CUT_ALL_MSK,
1689 RTW_PWR_INTF_USB_MSK,
1690 RTW_PWR_ADDR_MAC,
1691 RTW_PWR_CMD_WRITE, 0xFF, 0},
1692 {0x0006,
1693 RTW_PWR_CUT_ALL_MSK,
1694 RTW_PWR_INTF_ALL_MSK,
1695 RTW_PWR_ADDR_MAC,
1696 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1697 {0x0005,
1698 RTW_PWR_CUT_ALL_MSK,
1699 RTW_PWR_INTF_ALL_MSK,
1700 RTW_PWR_ADDR_MAC,
1701 RTW_PWR_CMD_WRITE, BIT(7), 0},
1702 {0x0005,
1703 RTW_PWR_CUT_ALL_MSK,
1704 RTW_PWR_INTF_ALL_MSK,
1705 RTW_PWR_ADDR_MAC,
1706 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1707 {0x10C3,
1708 RTW_PWR_CUT_ALL_MSK,
1709 RTW_PWR_INTF_USB_MSK,
1710 RTW_PWR_ADDR_MAC,
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1712 {0x0005,
1713 RTW_PWR_CUT_ALL_MSK,
1714 RTW_PWR_INTF_ALL_MSK,
1715 RTW_PWR_ADDR_MAC,
1716 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1717 {0x0005,
1718 RTW_PWR_CUT_ALL_MSK,
1719 RTW_PWR_INTF_ALL_MSK,
1720 RTW_PWR_ADDR_MAC,
1721 RTW_PWR_CMD_POLLING, BIT(0), 0},
1722 {0x0020,
1723 RTW_PWR_CUT_ALL_MSK,
1724 RTW_PWR_INTF_ALL_MSK,
1725 RTW_PWR_ADDR_MAC,
1726 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1727 {0x10A8,
1728 RTW_PWR_CUT_C_MSK,
1729 RTW_PWR_INTF_ALL_MSK,
1730 RTW_PWR_ADDR_MAC,
1731 RTW_PWR_CMD_WRITE, 0xFF, 0},
1732 {0x10A9,
1733 RTW_PWR_CUT_C_MSK,
1734 RTW_PWR_INTF_ALL_MSK,
1735 RTW_PWR_ADDR_MAC,
1736 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1737 {0x10AA,
1738 RTW_PWR_CUT_C_MSK,
1739 RTW_PWR_INTF_ALL_MSK,
1740 RTW_PWR_ADDR_MAC,
1741 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1742 {0x0068,
1743 RTW_PWR_CUT_C_MSK,
1744 RTW_PWR_INTF_SDIO_MSK,
1745 RTW_PWR_ADDR_MAC,
1746 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1747 {0x0029,
1748 RTW_PWR_CUT_ALL_MSK,
1749 RTW_PWR_INTF_ALL_MSK,
1750 RTW_PWR_ADDR_MAC,
1751 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1752 {0x0024,
1753 RTW_PWR_CUT_ALL_MSK,
1754 RTW_PWR_INTF_ALL_MSK,
1755 RTW_PWR_ADDR_MAC,
1756 RTW_PWR_CMD_WRITE, BIT(2), 0},
1757 {0x0074,
1758 RTW_PWR_CUT_ALL_MSK,
1759 RTW_PWR_INTF_PCI_MSK,
1760 RTW_PWR_ADDR_MAC,
1761 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1762 {0x00AF,
1763 RTW_PWR_CUT_ALL_MSK,
1764 RTW_PWR_INTF_ALL_MSK,
1765 RTW_PWR_ADDR_MAC,
1766 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1767 {0xFFFF,
1768 RTW_PWR_CUT_ALL_MSK,
1769 RTW_PWR_INTF_ALL_MSK,
1770 0,
1771 RTW_PWR_CMD_END, 0, 0},
1772 };
1773
1774 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = {
1775 {0x0003,
1776 RTW_PWR_CUT_ALL_MSK,
1777 RTW_PWR_INTF_SDIO_MSK,
1778 RTW_PWR_ADDR_MAC,
1779 RTW_PWR_CMD_WRITE, BIT(2), 0},
1780 {0x0093,
1781 RTW_PWR_CUT_ALL_MSK,
1782 RTW_PWR_INTF_ALL_MSK,
1783 RTW_PWR_ADDR_MAC,
1784 RTW_PWR_CMD_WRITE, BIT(3), 0},
1785 {0x001F,
1786 RTW_PWR_CUT_ALL_MSK,
1787 RTW_PWR_INTF_ALL_MSK,
1788 RTW_PWR_ADDR_MAC,
1789 RTW_PWR_CMD_WRITE, 0xFF, 0},
1790 {0x00EF,
1791 RTW_PWR_CUT_ALL_MSK,
1792 RTW_PWR_INTF_ALL_MSK,
1793 RTW_PWR_ADDR_MAC,
1794 RTW_PWR_CMD_WRITE, 0xFF, 0},
1795 {0xFF1A,
1796 RTW_PWR_CUT_ALL_MSK,
1797 RTW_PWR_INTF_USB_MSK,
1798 RTW_PWR_ADDR_MAC,
1799 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1800 {0x0049,
1801 RTW_PWR_CUT_ALL_MSK,
1802 RTW_PWR_INTF_ALL_MSK,
1803 RTW_PWR_ADDR_MAC,
1804 RTW_PWR_CMD_WRITE, BIT(1), 0},
1805 {0x0006,
1806 RTW_PWR_CUT_ALL_MSK,
1807 RTW_PWR_INTF_ALL_MSK,
1808 RTW_PWR_ADDR_MAC,
1809 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1810 {0x0002,
1811 RTW_PWR_CUT_ALL_MSK,
1812 RTW_PWR_INTF_ALL_MSK,
1813 RTW_PWR_ADDR_MAC,
1814 RTW_PWR_CMD_WRITE, BIT(1), 0},
1815 {0x10C3,
1816 RTW_PWR_CUT_ALL_MSK,
1817 RTW_PWR_INTF_USB_MSK,
1818 RTW_PWR_ADDR_MAC,
1819 RTW_PWR_CMD_WRITE, BIT(0), 0},
1820 {0x0005,
1821 RTW_PWR_CUT_ALL_MSK,
1822 RTW_PWR_INTF_ALL_MSK,
1823 RTW_PWR_ADDR_MAC,
1824 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1825 {0x0005,
1826 RTW_PWR_CUT_ALL_MSK,
1827 RTW_PWR_INTF_ALL_MSK,
1828 RTW_PWR_ADDR_MAC,
1829 RTW_PWR_CMD_POLLING, BIT(1), 0},
1830 {0x0020,
1831 RTW_PWR_CUT_ALL_MSK,
1832 RTW_PWR_INTF_ALL_MSK,
1833 RTW_PWR_ADDR_MAC,
1834 RTW_PWR_CMD_WRITE, BIT(3), 0},
1835 {0x0000,
1836 RTW_PWR_CUT_ALL_MSK,
1837 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1838 RTW_PWR_ADDR_MAC,
1839 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1840 {0xFFFF,
1841 RTW_PWR_CUT_ALL_MSK,
1842 RTW_PWR_INTF_ALL_MSK,
1843 0,
1844 RTW_PWR_CMD_END, 0, 0},
1845 };
1846
1847 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = {
1848 {0x0005,
1849 RTW_PWR_CUT_ALL_MSK,
1850 RTW_PWR_INTF_SDIO_MSK,
1851 RTW_PWR_ADDR_MAC,
1852 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1853 {0x0007,
1854 RTW_PWR_CUT_ALL_MSK,
1855 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1856 RTW_PWR_ADDR_MAC,
1857 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1858 {0x0067,
1859 RTW_PWR_CUT_ALL_MSK,
1860 RTW_PWR_INTF_ALL_MSK,
1861 RTW_PWR_ADDR_MAC,
1862 RTW_PWR_CMD_WRITE, BIT(5), 0},
1863 {0x0005,
1864 RTW_PWR_CUT_ALL_MSK,
1865 RTW_PWR_INTF_PCI_MSK,
1866 RTW_PWR_ADDR_MAC,
1867 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1868 {0x004A,
1869 RTW_PWR_CUT_ALL_MSK,
1870 RTW_PWR_INTF_USB_MSK,
1871 RTW_PWR_ADDR_MAC,
1872 RTW_PWR_CMD_WRITE, BIT(0), 0},
1873 {0x0067,
1874 RTW_PWR_CUT_ALL_MSK,
1875 RTW_PWR_INTF_SDIO_MSK,
1876 RTW_PWR_ADDR_MAC,
1877 RTW_PWR_CMD_WRITE, BIT(5), 0},
1878 {0x0067,
1879 RTW_PWR_CUT_ALL_MSK,
1880 RTW_PWR_INTF_SDIO_MSK,
1881 RTW_PWR_ADDR_MAC,
1882 RTW_PWR_CMD_WRITE, BIT(4), 0},
1883 {0x004F,
1884 RTW_PWR_CUT_ALL_MSK,
1885 RTW_PWR_INTF_SDIO_MSK,
1886 RTW_PWR_ADDR_MAC,
1887 RTW_PWR_CMD_WRITE, BIT(0), 0},
1888 {0x0067,
1889 RTW_PWR_CUT_ALL_MSK,
1890 RTW_PWR_INTF_SDIO_MSK,
1891 RTW_PWR_ADDR_MAC,
1892 RTW_PWR_CMD_WRITE, BIT(1), 0},
1893 {0x0046,
1894 RTW_PWR_CUT_ALL_MSK,
1895 RTW_PWR_INTF_SDIO_MSK,
1896 RTW_PWR_ADDR_MAC,
1897 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1898 {0x0067,
1899 RTW_PWR_CUT_ALL_MSK,
1900 RTW_PWR_INTF_SDIO_MSK,
1901 RTW_PWR_ADDR_MAC,
1902 RTW_PWR_CMD_WRITE, BIT(2), 0},
1903 {0x0046,
1904 RTW_PWR_CUT_ALL_MSK,
1905 RTW_PWR_INTF_SDIO_MSK,
1906 RTW_PWR_ADDR_MAC,
1907 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1908 {0x0062,
1909 RTW_PWR_CUT_ALL_MSK,
1910 RTW_PWR_INTF_SDIO_MSK,
1911 RTW_PWR_ADDR_MAC,
1912 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1913 {0x0081,
1914 RTW_PWR_CUT_ALL_MSK,
1915 RTW_PWR_INTF_ALL_MSK,
1916 RTW_PWR_ADDR_MAC,
1917 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1918 {0x0005,
1919 RTW_PWR_CUT_ALL_MSK,
1920 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1921 RTW_PWR_ADDR_MAC,
1922 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1923 {0x0086,
1924 RTW_PWR_CUT_ALL_MSK,
1925 RTW_PWR_INTF_SDIO_MSK,
1926 RTW_PWR_ADDR_SDIO,
1927 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1928 {0x0086,
1929 RTW_PWR_CUT_ALL_MSK,
1930 RTW_PWR_INTF_SDIO_MSK,
1931 RTW_PWR_ADDR_SDIO,
1932 RTW_PWR_CMD_POLLING, BIT(1), 0},
1933 {0x0090,
1934 RTW_PWR_CUT_ALL_MSK,
1935 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1936 RTW_PWR_ADDR_MAC,
1937 RTW_PWR_CMD_WRITE, BIT(1), 0},
1938 {0x0044,
1939 RTW_PWR_CUT_ALL_MSK,
1940 RTW_PWR_INTF_SDIO_MSK,
1941 RTW_PWR_ADDR_SDIO,
1942 RTW_PWR_CMD_WRITE, 0xFF, 0},
1943 {0x0040,
1944 RTW_PWR_CUT_ALL_MSK,
1945 RTW_PWR_INTF_SDIO_MSK,
1946 RTW_PWR_ADDR_SDIO,
1947 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1948 {0x0041,
1949 RTW_PWR_CUT_ALL_MSK,
1950 RTW_PWR_INTF_SDIO_MSK,
1951 RTW_PWR_ADDR_SDIO,
1952 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1953 {0x0042,
1954 RTW_PWR_CUT_ALL_MSK,
1955 RTW_PWR_INTF_SDIO_MSK,
1956 RTW_PWR_ADDR_SDIO,
1957 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1958 {0xFFFF,
1959 RTW_PWR_CUT_ALL_MSK,
1960 RTW_PWR_INTF_ALL_MSK,
1961 0,
1962 RTW_PWR_CMD_END, 0, 0},
1963 };
1964
1965 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8822b[] = {
1966 trans_carddis_to_cardemu_8822b,
1967 trans_cardemu_to_act_8822b,
1968 NULL
1969 };
1970
1971 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8822b[] = {
1972 trans_act_to_cardemu_8822b,
1973 trans_cardemu_to_carddis_8822b,
1974 NULL
1975 };
1976
1977 static const struct rtw_intf_phy_para usb2_param_8822b[] = {
1978 {0xFFFF, 0x00,
1979 RTW_IP_SEL_PHY,
1980 RTW_INTF_PHY_CUT_ALL,
1981 RTW_INTF_PHY_PLATFORM_ALL},
1982 };
1983
1984 static const struct rtw_intf_phy_para usb3_param_8822b[] = {
1985 {0x0001, 0xA841,
1986 RTW_IP_SEL_PHY,
1987 RTW_INTF_PHY_CUT_D,
1988 RTW_INTF_PHY_PLATFORM_ALL},
1989 {0xFFFF, 0x0000,
1990 RTW_IP_SEL_PHY,
1991 RTW_INTF_PHY_CUT_ALL,
1992 RTW_INTF_PHY_PLATFORM_ALL},
1993 };
1994
1995 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = {
1996 {0x0001, 0xA841,
1997 RTW_IP_SEL_PHY,
1998 RTW_INTF_PHY_CUT_C,
1999 RTW_INTF_PHY_PLATFORM_ALL},
2000 {0x0002, 0x60C6,
2001 RTW_IP_SEL_PHY,
2002 RTW_INTF_PHY_CUT_C,
2003 RTW_INTF_PHY_PLATFORM_ALL},
2004 {0x0008, 0x3596,
2005 RTW_IP_SEL_PHY,
2006 RTW_INTF_PHY_CUT_C,
2007 RTW_INTF_PHY_PLATFORM_ALL},
2008 {0x0009, 0x321C,
2009 RTW_IP_SEL_PHY,
2010 RTW_INTF_PHY_CUT_C,
2011 RTW_INTF_PHY_PLATFORM_ALL},
2012 {0x000A, 0x9623,
2013 RTW_IP_SEL_PHY,
2014 RTW_INTF_PHY_CUT_C,
2015 RTW_INTF_PHY_PLATFORM_ALL},
2016 {0x0020, 0x94FF,
2017 RTW_IP_SEL_PHY,
2018 RTW_INTF_PHY_CUT_C,
2019 RTW_INTF_PHY_PLATFORM_ALL},
2020 {0x0021, 0xFFCF,
2021 RTW_IP_SEL_PHY,
2022 RTW_INTF_PHY_CUT_C,
2023 RTW_INTF_PHY_PLATFORM_ALL},
2024 {0x0026, 0xC006,
2025 RTW_IP_SEL_PHY,
2026 RTW_INTF_PHY_CUT_C,
2027 RTW_INTF_PHY_PLATFORM_ALL},
2028 {0x0029, 0xFF0E,
2029 RTW_IP_SEL_PHY,
2030 RTW_INTF_PHY_CUT_C,
2031 RTW_INTF_PHY_PLATFORM_ALL},
2032 {0x002A, 0x1840,
2033 RTW_IP_SEL_PHY,
2034 RTW_INTF_PHY_CUT_C,
2035 RTW_INTF_PHY_PLATFORM_ALL},
2036 {0xFFFF, 0x0000,
2037 RTW_IP_SEL_PHY,
2038 RTW_INTF_PHY_CUT_ALL,
2039 RTW_INTF_PHY_PLATFORM_ALL},
2040 };
2041
2042 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = {
2043 {0x0001, 0xA841,
2044 RTW_IP_SEL_PHY,
2045 RTW_INTF_PHY_CUT_C,
2046 RTW_INTF_PHY_PLATFORM_ALL},
2047 {0x0002, 0x60C6,
2048 RTW_IP_SEL_PHY,
2049 RTW_INTF_PHY_CUT_C,
2050 RTW_INTF_PHY_PLATFORM_ALL},
2051 {0x0008, 0x3597,
2052 RTW_IP_SEL_PHY,
2053 RTW_INTF_PHY_CUT_C,
2054 RTW_INTF_PHY_PLATFORM_ALL},
2055 {0x0009, 0x321C,
2056 RTW_IP_SEL_PHY,
2057 RTW_INTF_PHY_CUT_C,
2058 RTW_INTF_PHY_PLATFORM_ALL},
2059 {0x000A, 0x9623,
2060 RTW_IP_SEL_PHY,
2061 RTW_INTF_PHY_CUT_C,
2062 RTW_INTF_PHY_PLATFORM_ALL},
2063 {0x0020, 0x94FF,
2064 RTW_IP_SEL_PHY,
2065 RTW_INTF_PHY_CUT_C,
2066 RTW_INTF_PHY_PLATFORM_ALL},
2067 {0x0021, 0xFFCF,
2068 RTW_IP_SEL_PHY,
2069 RTW_INTF_PHY_CUT_C,
2070 RTW_INTF_PHY_PLATFORM_ALL},
2071 {0x0026, 0xC006,
2072 RTW_IP_SEL_PHY,
2073 RTW_INTF_PHY_CUT_C,
2074 RTW_INTF_PHY_PLATFORM_ALL},
2075 {0x0029, 0xFF0E,
2076 RTW_IP_SEL_PHY,
2077 RTW_INTF_PHY_CUT_C,
2078 RTW_INTF_PHY_PLATFORM_ALL},
2079 {0x002A, 0x3040,
2080 RTW_IP_SEL_PHY,
2081 RTW_INTF_PHY_CUT_C,
2082 RTW_INTF_PHY_PLATFORM_ALL},
2083 {0xFFFF, 0x0000,
2084 RTW_IP_SEL_PHY,
2085 RTW_INTF_PHY_CUT_ALL,
2086 RTW_INTF_PHY_PLATFORM_ALL},
2087 };
2088
2089 static const struct rtw_intf_phy_para_table phy_para_table_8822b = {
2090 .usb2_para = usb2_param_8822b,
2091 .usb3_para = usb3_param_8822b,
2092 .gen1_para = pcie_gen1_param_8822b,
2093 .gen2_para = pcie_gen2_param_8822b,
2094 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b),
2095 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b),
2096 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b),
2097 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b),
2098 };
2099
2100 static const struct rtw_hw_reg rtw8822b_dig[] = {
2101 [0] = { .addr = 0xc50, .mask = 0x7f },
2102 [1] = { .addr = 0xe50, .mask = 0x7f },
2103 };
2104
2105 static const struct rtw_ltecoex_addr rtw8822b_ltecoex_addr = {
2106 .ctrl = LTECOEX_ACCESS_CTRL,
2107 .wdata = LTECOEX_WRITE_DATA,
2108 .rdata = LTECOEX_READ_DATA,
2109 };
2110
2111 static const struct rtw_page_table page_table_8822b[] = {
2112 {64, 64, 64, 64, 1},
2113 {64, 64, 64, 64, 1},
2114 {64, 64, 0, 0, 1},
2115 {64, 64, 64, 0, 1},
2116 {64, 64, 64, 64, 1},
2117 };
2118
2119 static const struct rtw_rqpn rqpn_table_8822b[] = {
2120 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2121 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2122 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2123 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2124 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2125 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2126 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2127 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
2128 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2129 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2130 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2131 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2132 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2133 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2134 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2135 };
2136
2137 static const struct rtw_prioq_addrs prioq_addrs_8822b = {
2138 .prio[RTW_DMA_MAPPING_EXTRA] = {
2139 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
2140 },
2141 .prio[RTW_DMA_MAPPING_LOW] = {
2142 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
2143 },
2144 .prio[RTW_DMA_MAPPING_NORMAL] = {
2145 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
2146 },
2147 .prio[RTW_DMA_MAPPING_HIGH] = {
2148 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
2149 },
2150 .wsize = true,
2151 };
2152
2153 static const struct rtw_chip_ops rtw8822b_ops = {
2154 .power_on = rtw_power_on,
2155 .power_off = rtw_power_off,
2156 .phy_set_param = rtw8822b_phy_set_param,
2157 .read_efuse = rtw8822b_read_efuse,
2158 .query_phy_status = query_phy_status,
2159 .set_channel = rtw8822b_set_channel,
2160 .mac_init = rtw8822b_mac_init,
2161 .mac_postinit = NULL,
2162 .read_rf = rtw_phy_read_rf,
2163 .write_rf = rtw_phy_write_rf_reg_sipi,
2164 .set_tx_power_index = rtw8822b_set_tx_power_index,
2165 .set_antenna = rtw8822b_set_antenna,
2166 .cfg_ldo25 = rtw8822b_cfg_ldo25,
2167 .set_ampdu_factor = NULL,
2168 .false_alarm_statistics = rtw8822b_false_alarm_statistics,
2169 .phy_calibration = rtw8822b_phy_calibration,
2170 .pwr_track = rtw8822b_pwr_track,
2171 .config_bfee = rtw8822b_bf_config_bfee,
2172 .set_gid_table = rtw_bf_set_gid_table,
2173 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
2174 .adaptivity_init = rtw8822b_adaptivity_init,
2175 .adaptivity = rtw8822b_adaptivity,
2176 .led_set = rtw8822b_led_set,
2177 .fill_txdesc_checksum = rtw8822b_fill_txdesc_checksum,
2178
2179 .coex_set_init = rtw8822b_coex_cfg_init,
2180 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
2181 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
2182 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
2183 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
2184 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
2185 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
2186 };
2187
2188 /* Shared-Antenna Coex Table */
2189 static const struct coex_table_para table_sant_8822b[] = {
2190 {0xffffffff, 0xffffffff}, /* case-0 */
2191 {0x55555555, 0x55555555},
2192 {0x66555555, 0x66555555},
2193 {0xaaaaaaaa, 0xaaaaaaaa},
2194 {0x5a5a5a5a, 0x5a5a5a5a},
2195 {0xfafafafa, 0xfafafafa}, /* case-5 */
2196 {0x6a5a5555, 0xaaaaaaaa},
2197 {0x6a5a56aa, 0x6a5a56aa},
2198 {0x6a5a5a5a, 0x6a5a5a5a},
2199 {0x66555555, 0x5a5a5a5a},
2200 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2201 {0x66555555, 0xfafafafa},
2202 {0x66555555, 0x5a5a5aaa},
2203 {0x66555555, 0x6aaa5aaa},
2204 {0x66555555, 0xaaaa5aaa},
2205 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2206 {0xffff55ff, 0xfafafafa},
2207 {0xffff55ff, 0x6afa5afa},
2208 {0xaaffffaa, 0xfafafafa},
2209 {0xaa5555aa, 0x5a5a5a5a},
2210 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2211 {0xaa5555aa, 0xaaaaaaaa},
2212 {0xffffffff, 0x5a5a5a5a},
2213 {0xffffffff, 0x5a5a5a5a},
2214 {0xffffffff, 0x55555555},
2215 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2216 {0x55555555, 0x5a5a5a5a},
2217 {0x55555555, 0xaaaaaaaa},
2218 {0x55555555, 0x6a5a6a5a},
2219 {0x66556655, 0x66556655},
2220 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2221 {0xffffffff, 0x5aaa5aaa},
2222 {0x56555555, 0x5a5a5aaa},
2223 {0xdaffdaff, 0xdaffdaff},
2224 {0xddffddff, 0xddffddff},
2225 {0xe5555555, 0xe5555555}, /* case-35 */
2226 {0xea5a5a5a, 0xea5a5a5a},
2227 {0xea6a6a6a, 0xea6a6a6a},
2228 };
2229
2230 /* Non-Shared-Antenna Coex Table */
2231 static const struct coex_table_para table_nsant_8822b[] = {
2232 {0xffffffff, 0xffffffff}, /* case-100 */
2233 {0x55555555, 0x55555555},
2234 {0x66555555, 0x66555555},
2235 {0xaaaaaaaa, 0xaaaaaaaa},
2236 {0x5a5a5a5a, 0x5a5a5a5a},
2237 {0xfafafafa, 0xfafafafa}, /* case-105 */
2238 {0x5afa5afa, 0x5afa5afa},
2239 {0x55555555, 0xfafafafa},
2240 {0x66555555, 0xfafafafa},
2241 {0x66555555, 0x5a5a5a5a},
2242 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2243 {0x66555555, 0xaaaaaaaa},
2244 {0xffff55ff, 0xfafafafa},
2245 {0xffff55ff, 0x5afa5afa},
2246 {0xffff55ff, 0xaaaaaaaa},
2247 {0xffff55ff, 0xffff55ff}, /* case-115 */
2248 {0xaaffffaa, 0x5afa5afa},
2249 {0xaaffffaa, 0xaaaaaaaa},
2250 {0xffffffff, 0xfafafafa},
2251 {0xffffffff, 0x5afa5afa},
2252 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2253 {0x55ff55ff, 0x5afa5afa},
2254 {0x55ff55ff, 0xaaaaaaaa},
2255 {0x55ff55ff, 0x55ff55ff}
2256 };
2257
2258 /* Shared-Antenna TDMA */
2259 static const struct coex_tdma_para tdma_sant_8822b[] = {
2260 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2261 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2262 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2263 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2264 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2265 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2266 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2267 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2268 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2269 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2270 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2271 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2272 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2273 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2274 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2275 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2276 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2277 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2278 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2279 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2280 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2281 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2282 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2283 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2284 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2285 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2286 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2287 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2288 };
2289
2290 /* Non-Shared-Antenna TDMA */
2291 static const struct coex_tdma_para tdma_nsant_8822b[] = {
2292 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2293 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2294 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2295 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2296 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2297 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2298 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2299 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2300 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2301 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2302 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2303 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2304 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2305 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2306 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2307 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2308 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2309 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2310 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2311 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2312 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2313 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2314 };
2315
2316 /* rssi in percentage % (dbm = % - 100) */
2317 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
2318 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
2319
2320 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
2321 static const struct coex_rf_para rf_para_tx_8822b[] = {
2322 {0, 0, false, 7}, /* for normal */
2323 {0, 16, false, 7}, /* for WL-CPT */
2324 {4, 0, true, 1},
2325 {3, 6, true, 1},
2326 {2, 9, true, 1},
2327 {1, 13, true, 1}
2328 };
2329
2330 static const struct coex_rf_para rf_para_rx_8822b[] = {
2331 {0, 0, false, 7}, /* for normal */
2332 {0, 16, false, 7}, /* for WL-CPT */
2333 {4, 0, true, 1},
2334 {3, 6, true, 1},
2335 {2, 9, true, 1},
2336 {1, 13, true, 1}
2337 };
2338
2339 static const struct coex_5g_afh_map afh_5g_8822b[] = {
2340 {120, 2, 4},
2341 {124, 8, 8},
2342 {128, 17, 8},
2343 {132, 26, 10},
2344 {136, 34, 8},
2345 {140, 42, 10},
2346 {144, 51, 8},
2347 {149, 62, 8},
2348 {153, 71, 10},
2349 {157, 77, 4},
2350 {118, 2, 4},
2351 {126, 12, 16},
2352 {134, 29, 16},
2353 {142, 46, 16},
2354 {151, 66, 16},
2355 {159, 76, 4},
2356 {122, 10, 20},
2357 {138, 37, 34},
2358 {155, 68, 20}
2359 };
2360 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
2361
2362 static const u8
2363 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2364 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2365 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2366 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2367 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2368 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2369 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2370 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2371 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2372 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2373 };
2374
2375 static const u8
2376 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2377 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2378 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2379 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2380 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2381 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2382 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2383 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2384 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2385 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2386 };
2387
2388 static const u8
2389 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2390 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2391 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2392 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2393 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2394 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2395 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2396 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2397 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2398 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2399 };
2400
2401 static const u8
2402 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2403 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2404 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2405 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2406 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2407 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2408 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2409 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2410 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2411 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2412 };
2413
2414 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = {
2415 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2416 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2417 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2418 };
2419
2420 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = {
2421 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2422 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2423 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2424 };
2425
2426 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = {
2427 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2428 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2429 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2430 };
2431
2432 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = {
2433 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2434 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2435 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2436 };
2437
2438 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = {
2439 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2440 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2441 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2442 };
2443
2444 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = {
2445 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2446 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2447 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2448 };
2449
2450 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = {
2451 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2452 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2453 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2454 };
2455
2456 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = {
2457 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2458 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2459 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2460 };
2461
2462 static const struct rtw_pwr_track_tbl rtw8822b_pwr_track_type0_tbl = {
2463 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1],
2464 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2],
2465 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3],
2466 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1],
2467 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2],
2468 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3],
2469 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1],
2470 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2],
2471 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3],
2472 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1],
2473 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2],
2474 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3],
2475 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n,
2476 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p,
2477 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n,
2478 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p,
2479 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n,
2480 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p,
2481 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n,
2482 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p,
2483 };
2484
2485 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = {
2486 [2] = RTW_DEF_RFE(8822b, 2, 2, 0),
2487 [3] = RTW_DEF_RFE(8822b, 3, 0, 0),
2488 [5] = RTW_DEF_RFE(8822b, 5, 5, 0),
2489 };
2490
2491 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = {
2492 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2493 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2494 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2495 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2496 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2497 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2498 {0, 0, RTW_REG_DOMAIN_NL},
2499 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2500 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2501 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2502 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2503 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2504 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2505 {0, 0, RTW_REG_DOMAIN_NL},
2506 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2507 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2508 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2509 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2510 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2511 {0, 0, RTW_REG_DOMAIN_NL},
2512 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2513 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2514 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2515 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2516 };
2517
2518 static const struct rtw_hw_reg_offset rtw8822b_edcca_th[] = {
2519 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2520 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2521 };
2522
2523 const struct rtw_chip_info rtw8822b_hw_spec = {
2524 .ops = &rtw8822b_ops,
2525 .id = RTW_CHIP_TYPE_8822B,
2526 .fw_name = "rtw88/rtw8822b_fw.bin",
2527 .wlan_cpu = RTW_WCPU_3081,
2528 .tx_pkt_desc_sz = 48,
2529 .tx_buf_desc_sz = 16,
2530 .rx_pkt_desc_sz = 24,
2531 .rx_buf_desc_sz = 8,
2532 .phy_efuse_size = 1024,
2533 .log_efuse_size = 768,
2534 .ptct_efuse_size = 96,
2535 .txff_size = 262144,
2536 .rxff_size = 24576,
2537 .fw_rxff_size = 12288,
2538 .rsvd_drv_pg_num = 8,
2539 .txgi_factor = 1,
2540 .is_pwr_by_rate_dec = true,
2541 .max_power_index = 0x3f,
2542 .csi_buf_pg_num = 0,
2543 .band = RTW_BAND_2G | RTW_BAND_5G,
2544 .page_size = TX_PAGE_SIZE,
2545 .dig_min = 0x1c,
2546 .amsdu_in_ampdu = true,
2547 .usb_tx_agg_desc_num = 3,
2548 .hw_feature_report = true,
2549 .c2h_ra_report_size = 7,
2550 .old_datarate_fb_limit = false,
2551 .ht_supported = true,
2552 .vht_supported = true,
2553 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2554 .sys_func_en = 0xDC,
2555 .pwr_on_seq = card_enable_flow_8822b,
2556 .pwr_off_seq = card_disable_flow_8822b,
2557 .page_table = page_table_8822b,
2558 .rqpn_table = rqpn_table_8822b,
2559 .prioq_addrs = &prioq_addrs_8822b,
2560 .intf_table = &phy_para_table_8822b,
2561 .dig = rtw8822b_dig,
2562 .dig_cck = NULL,
2563 .rf_base_addr = {0x2800, 0x2c00},
2564 .rf_sipi_addr = {0xc90, 0xe90},
2565 .ltecoex_addr = &rtw8822b_ltecoex_addr,
2566 .mac_tbl = &rtw8822b_mac_tbl,
2567 .agc_tbl = &rtw8822b_agc_tbl,
2568 .bb_tbl = &rtw8822b_bb_tbl,
2569 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
2570 .rfe_defs = rtw8822b_rfe_defs,
2571 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
2572 .iqk_threshold = 8,
2573 .bfer_su_max_num = 2,
2574 .bfer_mu_max_num = 1,
2575 .rx_ldpc = true,
2576 .edcca_th = rtw8822b_edcca_th,
2577 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE,
2578 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,
2579 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2580 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2581
2582 .coex_para_ver = 0x20070206,
2583 .bt_desired_ver = 0x6,
2584 .scbd_support = true,
2585 .new_scbd10_def = false,
2586 .ble_hid_profile_support = false,
2587 .wl_mimo_ps_support = false,
2588 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2589 .bt_rssi_type = COEX_BTRSSI_RATIO,
2590 .ant_isolation = 15,
2591 .rssi_tolerance = 2,
2592 .wl_rssi_step = wl_rssi_step_8822b,
2593 .bt_rssi_step = bt_rssi_step_8822b,
2594 .table_sant_num = ARRAY_SIZE(table_sant_8822b),
2595 .table_sant = table_sant_8822b,
2596 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
2597 .table_nsant = table_nsant_8822b,
2598 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
2599 .tdma_sant = tdma_sant_8822b,
2600 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
2601 .tdma_nsant = tdma_nsant_8822b,
2602 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
2603 .wl_rf_para_tx = rf_para_tx_8822b,
2604 .wl_rf_para_rx = rf_para_rx_8822b,
2605 .bt_afh_span_bw20 = 0x24,
2606 .bt_afh_span_bw40 = 0x36,
2607 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
2608 .afh_5g = afh_5g_8822b,
2609
2610 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b),
2611 .coex_info_hw_regs = coex_info_hw_regs_8822b,
2612
2613 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},
2614 };
2615 EXPORT_SYMBOL(rtw8822b_hw_spec);
2616
2617 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin");
2618
2619 MODULE_AUTHOR("Realtek Corporation");
2620 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822b driver");
2621 MODULE_LICENSE("Dual BSD/GPL");
2622