1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/aperture.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 18 #include <drm/clients/drm_client_setup.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_drv.h> 21 #include <drm/drm_fbdev_ttm.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_gem_vram_helper.h> 24 #include <drm/drm_managed.h> 25 #include <drm/drm_module.h> 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_probe_helper.h> 28 29 #include "hibmc_drm_drv.h" 30 #include "hibmc_drm_regs.h" 31 32 #include "dp/dp_reg.h" 33 34 DEFINE_DRM_GEM_FOPS(hibmc_fops); 35 36 static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] = { "hibmc-vblank", "hibmc-hpd" }; 37 38 static irqreturn_t hibmc_interrupt(int irq, void *arg) 39 { 40 struct drm_device *dev = (struct drm_device *)arg; 41 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 42 u32 status; 43 44 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); 45 46 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) { 47 writel(HIBMC_RAW_INTERRUPT_VBLANK(1), 48 priv->mmio + HIBMC_RAW_INTERRUPT); 49 drm_handle_vblank(dev, 0); 50 } 51 52 return IRQ_HANDLED; 53 } 54 55 static irqreturn_t hibmc_dp_interrupt(int irq, void *arg) 56 { 57 struct drm_device *dev = (struct drm_device *)arg; 58 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 59 u32 status; 60 61 status = readl(priv->mmio + HIBMC_DP_INTSTAT); 62 if (status) { 63 priv->dp.irq_status = status; 64 writel(status, priv->mmio + HIBMC_DP_INTCLR); 65 return IRQ_WAKE_THREAD; 66 } 67 68 return IRQ_HANDLED; 69 } 70 71 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev, 72 struct drm_mode_create_dumb *args) 73 { 74 return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args); 75 } 76 77 static const struct drm_driver hibmc_driver = { 78 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 79 .fops = &hibmc_fops, 80 .name = "hibmc", 81 .desc = "hibmc drm driver", 82 .major = 1, 83 .minor = 0, 84 .debugfs_init = drm_vram_mm_debugfs_init, 85 .dumb_create = hibmc_dumb_create, 86 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 87 DRM_FBDEV_TTM_DRIVER_OPS, 88 }; 89 90 static int __maybe_unused hibmc_pm_suspend(struct device *dev) 91 { 92 struct drm_device *drm_dev = dev_get_drvdata(dev); 93 94 return drm_mode_config_helper_suspend(drm_dev); 95 } 96 97 static int __maybe_unused hibmc_pm_resume(struct device *dev) 98 { 99 struct drm_device *drm_dev = dev_get_drvdata(dev); 100 101 return drm_mode_config_helper_resume(drm_dev); 102 } 103 104 static const struct dev_pm_ops hibmc_pm_ops = { 105 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend, 106 hibmc_pm_resume) 107 }; 108 109 static const struct drm_mode_config_funcs hibmc_mode_funcs = { 110 .mode_valid = drm_vram_helper_mode_valid, 111 .atomic_check = drm_atomic_helper_check, 112 .atomic_commit = drm_atomic_helper_commit, 113 .fb_create = drm_gem_fb_create, 114 }; 115 116 static int hibmc_kms_init(struct hibmc_drm_private *priv) 117 { 118 struct drm_device *dev = &priv->dev; 119 struct drm_encoder *encoder; 120 u32 clone_mask = 0; 121 int ret; 122 123 ret = drmm_mode_config_init(dev); 124 if (ret) 125 return ret; 126 127 dev->mode_config.min_width = 0; 128 dev->mode_config.min_height = 0; 129 dev->mode_config.max_width = 1920; 130 dev->mode_config.max_height = 1200; 131 132 dev->mode_config.preferred_depth = 24; 133 dev->mode_config.prefer_shadow = 1; 134 135 dev->mode_config.funcs = (void *)&hibmc_mode_funcs; 136 137 ret = hibmc_de_init(priv); 138 if (ret) { 139 drm_err(dev, "failed to init de: %d\n", ret); 140 return ret; 141 } 142 143 /* 144 * If the serdes reg is readable and is not equal to 0, 145 * DP block exists and initializes it. 146 */ 147 ret = readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL); 148 if (ret) { 149 ret = hibmc_dp_init(priv); 150 if (ret) 151 drm_err(dev, "failed to init dp: %d\n", ret); 152 } 153 154 ret = hibmc_vdac_init(priv); 155 if (ret) { 156 drm_err(dev, "failed to init vdac: %d\n", ret); 157 return ret; 158 } 159 160 drm_for_each_encoder(encoder, dev) 161 clone_mask |= drm_encoder_mask(encoder); 162 163 drm_for_each_encoder(encoder, dev) 164 encoder->possible_clones = clone_mask; 165 166 return 0; 167 } 168 169 /* 170 * It can operate in one of three modes: 0, 1 or Sleep. 171 */ 172 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode) 173 { 174 u32 control_value = 0; 175 void __iomem *mmio = priv->mmio; 176 u32 input = 1; 177 178 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP) 179 return; 180 181 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP) 182 input = 0; 183 184 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); 185 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | 186 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK); 187 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); 188 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); 189 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); 190 } 191 192 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) 193 { 194 u32 gate_reg; 195 u32 mode; 196 void __iomem *mmio = priv->mmio; 197 198 /* Get current power mode. */ 199 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) & 200 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT; 201 202 switch (mode) { 203 case HIBMC_PW_MODE_CTL_MODE_MODE0: 204 gate_reg = HIBMC_MODE0_GATE; 205 break; 206 207 case HIBMC_PW_MODE_CTL_MODE_MODE1: 208 gate_reg = HIBMC_MODE1_GATE; 209 break; 210 211 default: 212 gate_reg = HIBMC_MODE0_GATE; 213 break; 214 } 215 writel(gate, mmio + gate_reg); 216 } 217 218 static void hibmc_display_ctrl(struct hibmc_drm_private *priv) 219 { 220 u32 reg; 221 222 reg = readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); 223 reg |= HIBMC_DISPLAY_CONTROL_PANELDATE(1); 224 writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); 225 } 226 227 static void hibmc_hw_config(struct hibmc_drm_private *priv) 228 { 229 u32 reg; 230 231 /* On hardware reset, power mode 0 is default. */ 232 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 233 234 /* Enable display power gate & LOCALMEM power gate*/ 235 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 236 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 237 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 238 reg |= HIBMC_CURR_GATE_DISPLAY(1); 239 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 240 241 hibmc_set_current_gate(priv, reg); 242 243 /* 244 * Reset the memory controller. If the memory controller 245 * is not reset in chip,the system might hang when sw accesses 246 * the memory.The memory should be resetted after 247 * changing the MXCLK. 248 */ 249 reg = readl(priv->mmio + HIBMC_MISC_CTRL); 250 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 251 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); 252 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 253 254 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 255 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); 256 257 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 258 259 hibmc_display_ctrl(priv); 260 } 261 262 static int hibmc_hw_map(struct hibmc_drm_private *priv) 263 { 264 struct drm_device *dev = &priv->dev; 265 struct pci_dev *pdev = to_pci_dev(dev->dev); 266 resource_size_t ioaddr, iosize; 267 268 ioaddr = pci_resource_start(pdev, 1); 269 iosize = pci_resource_len(pdev, 1); 270 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize); 271 if (!priv->mmio) { 272 drm_err(dev, "Cannot map mmio region\n"); 273 return -ENOMEM; 274 } 275 276 return 0; 277 } 278 279 static int hibmc_hw_init(struct hibmc_drm_private *priv) 280 { 281 int ret; 282 283 ret = hibmc_hw_map(priv); 284 if (ret) 285 return ret; 286 287 hibmc_hw_config(priv); 288 289 return 0; 290 } 291 292 static void hibmc_unload(struct drm_device *dev) 293 { 294 drm_atomic_helper_shutdown(dev); 295 } 296 297 static int hibmc_msi_init(struct drm_device *dev) 298 { 299 struct pci_dev *pdev = to_pci_dev(dev->dev); 300 int valid_irq_num; 301 int irq; 302 int ret; 303 304 ret = pci_alloc_irq_vectors(pdev, HIBMC_MIN_VECTORS, 305 HIBMC_MAX_VECTORS, PCI_IRQ_MSI); 306 if (ret < 0) { 307 drm_err(dev, "enabling MSI failed: %d\n", ret); 308 return ret; 309 } 310 311 valid_irq_num = ret; 312 313 for (int i = 0; i < valid_irq_num; i++) { 314 irq = pci_irq_vector(pdev, i); 315 316 if (i) 317 /* PCI devices require shared interrupts. */ 318 ret = devm_request_threaded_irq(&pdev->dev, irq, 319 hibmc_dp_interrupt, 320 hibmc_dp_hpd_isr, 321 IRQF_SHARED, g_irqs_names_map[i], dev); 322 else 323 ret = devm_request_irq(&pdev->dev, irq, hibmc_interrupt, 324 IRQF_SHARED, g_irqs_names_map[i], dev); 325 if (ret) { 326 drm_err(dev, "install irq failed: %d\n", ret); 327 return ret; 328 } 329 } 330 331 return 0; 332 } 333 334 static int hibmc_load(struct drm_device *dev) 335 { 336 struct pci_dev *pdev = to_pci_dev(dev->dev); 337 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 338 int ret; 339 340 ret = hibmc_hw_init(priv); 341 if (ret) 342 return ret; 343 344 ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), 345 pci_resource_len(pdev, 0)); 346 if (ret) { 347 drm_err(dev, "Error initializing VRAM MM; %d\n", ret); 348 return ret; 349 } 350 351 ret = hibmc_kms_init(priv); 352 if (ret) 353 goto err; 354 355 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 356 if (ret) { 357 drm_err(dev, "failed to initialize vblank: %d\n", ret); 358 goto err; 359 } 360 361 ret = hibmc_msi_init(dev); 362 if (ret) { 363 drm_err(dev, "hibmc msi init failed, ret:%d\n", ret); 364 goto err; 365 } 366 367 /* reset all the states of crtc/plane/encoder/connector */ 368 drm_mode_config_reset(dev); 369 370 drmm_kms_helper_poll_init(dev); 371 372 return 0; 373 374 err: 375 hibmc_unload(dev); 376 drm_err(dev, "failed to initialize drm driver: %d\n", ret); 377 return ret; 378 } 379 380 static int hibmc_pci_probe(struct pci_dev *pdev, 381 const struct pci_device_id *ent) 382 { 383 struct hibmc_drm_private *priv; 384 struct drm_device *dev; 385 int ret; 386 387 ret = aperture_remove_conflicting_pci_devices(pdev, hibmc_driver.name); 388 if (ret) 389 return ret; 390 391 priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver, 392 struct hibmc_drm_private, dev); 393 if (IS_ERR(priv)) { 394 DRM_ERROR("failed to allocate drm_device\n"); 395 return PTR_ERR(priv); 396 } 397 398 dev = &priv->dev; 399 pci_set_drvdata(pdev, dev); 400 401 ret = pcim_enable_device(pdev); 402 if (ret) { 403 drm_err(dev, "failed to enable pci device: %d\n", ret); 404 goto err_return; 405 } 406 407 pci_set_master(pdev); 408 409 ret = hibmc_load(dev); 410 if (ret) { 411 drm_err(dev, "failed to load hibmc: %d\n", ret); 412 goto err_return; 413 } 414 415 ret = drm_dev_register(dev, 0); 416 if (ret) { 417 drm_err(dev, "failed to register drv for userspace access: %d\n", 418 ret); 419 goto err_unload; 420 } 421 422 drm_client_setup(dev, NULL); 423 424 return 0; 425 426 err_unload: 427 hibmc_unload(dev); 428 err_return: 429 return ret; 430 } 431 432 static void hibmc_pci_remove(struct pci_dev *pdev) 433 { 434 struct drm_device *dev = pci_get_drvdata(pdev); 435 436 drm_dev_unregister(dev); 437 hibmc_unload(dev); 438 } 439 440 static void hibmc_pci_shutdown(struct pci_dev *pdev) 441 { 442 hibmc_pci_remove(pdev); 443 } 444 445 static const struct pci_device_id hibmc_pci_table[] = { 446 { PCI_VDEVICE(HUAWEI, 0x1711) }, 447 {0,} 448 }; 449 450 static struct pci_driver hibmc_pci_driver = { 451 .name = "hibmc-drm", 452 .id_table = hibmc_pci_table, 453 .probe = hibmc_pci_probe, 454 .remove = hibmc_pci_remove, 455 .shutdown = hibmc_pci_shutdown, 456 .driver.pm = &hibmc_pm_ops, 457 }; 458 459 drm_module_pci_driver(hibmc_pci_driver); 460 461 MODULE_DEVICE_TABLE(pci, hibmc_pci_table); 462 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>"); 463 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc"); 464 MODULE_LICENSE("GPL v2"); 465