1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/drm_edid.h> 10 #include <drm/display/drm_hdmi_helper.h> 11 #include <drm/display/drm_hdmi_state_helper.h> 12 13 #include "msm_kms.h" 14 #include "hdmi.h" 15 16 static int msm_hdmi_power_on(struct drm_bridge *bridge) 17 { 18 struct drm_device *dev = bridge->dev; 19 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 20 struct hdmi *hdmi = hdmi_bridge->hdmi; 21 int ret; 22 23 ret = pm_runtime_resume_and_get(&hdmi->pdev->dev); 24 if (ret) 25 return ret; 26 27 if (hdmi->extp_clk) { 28 DBG("pixclock: %lu", hdmi->pixclock); 29 ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock); 30 if (ret) 31 DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); 32 33 ret = clk_prepare_enable(hdmi->extp_clk); 34 if (ret) { 35 DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); 36 pm_runtime_put(&hdmi->pdev->dev); 37 return ret; 38 } 39 } 40 41 return 0; 42 } 43 44 static void power_off(struct drm_bridge *bridge) 45 { 46 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 47 struct hdmi *hdmi = hdmi_bridge->hdmi; 48 49 /* TODO do we need to wait for final vblank somewhere before 50 * cutting the clocks? 51 */ 52 mdelay(16 + 4); 53 54 if (hdmi->extp_clk) 55 clk_disable_unprepare(hdmi->extp_clk); 56 57 pm_runtime_put(&hdmi->pdev->dev); 58 } 59 60 #define AVI_IFRAME_LINE_NUMBER 1 61 #define SPD_IFRAME_LINE_NUMBER 1 62 #define VENSPEC_IFRAME_LINE_NUMBER 3 63 64 static int msm_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 65 { 66 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 67 struct hdmi *hdmi = hdmi_bridge->hdmi; 68 69 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 70 HDMI_INFOFRAME_CTRL0_AVI_SEND | 71 HDMI_INFOFRAME_CTRL0_AVI_CONT); 72 73 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 74 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK); 75 76 return 0; 77 } 78 79 static int msm_hdmi_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 80 { 81 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 82 struct hdmi *hdmi = hdmi_bridge->hdmi; 83 84 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 85 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 86 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 87 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 88 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE); 89 90 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 91 HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK); 92 93 return 0; 94 } 95 96 static int msm_hdmi_bridge_clear_spd_infoframe(struct drm_bridge *bridge) 97 { 98 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 99 struct hdmi *hdmi = hdmi_bridge->hdmi; 100 101 hdmi_clear_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, 102 HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 103 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 104 HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK); 105 106 return 0; 107 } 108 109 static int msm_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 110 { 111 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 112 struct hdmi *hdmi = hdmi_bridge->hdmi; 113 114 hdmi_clear_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, 115 HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 116 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 117 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 118 HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK); 119 120 return 0; 121 } 122 123 static int msm_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, 124 const u8 *buffer, size_t len) 125 { 126 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 127 struct hdmi *hdmi = hdmi_bridge->hdmi; 128 u32 buf[4] = {}; 129 int i; 130 131 if (len != HDMI_INFOFRAME_SIZE(AVI) || len - 3 > sizeof(buf)) { 132 DRM_DEV_ERROR(&hdmi->pdev->dev, 133 "failed to configure avi infoframe\n"); 134 return -EINVAL; 135 } 136 137 msm_hdmi_bridge_clear_avi_infoframe(bridge); 138 139 /* 140 * the AVI_INFOx registers don't map exactly to how the AVI infoframes 141 * are packed according to the spec. The checksum from the header is 142 * written to the LSB byte of AVI_INFO0 and the version is written to 143 * the third byte from the LSB of AVI_INFO3 144 */ 145 memcpy(buf, &buffer[3], len - 3); 146 147 buf[3] |= buffer[1] << 24; 148 149 for (i = 0; i < ARRAY_SIZE(buf); i++) 150 hdmi_write(hdmi, REG_HDMI_AVI_INFO(i), buf[i]); 151 152 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 153 HDMI_INFOFRAME_CTRL0_AVI_SEND | HDMI_INFOFRAME_CTRL0_AVI_CONT, 154 HDMI_INFOFRAME_CTRL0_AVI_SEND | HDMI_INFOFRAME_CTRL0_AVI_CONT); 155 156 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 157 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK, 158 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER)); 159 160 return 0; 161 } 162 163 static int msm_hdmi_bridge_write_audio_infoframe(struct drm_bridge *bridge, 164 const u8 *buffer, size_t len) 165 { 166 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 167 struct hdmi *hdmi = hdmi_bridge->hdmi; 168 u32 val; 169 170 if (len != HDMI_INFOFRAME_SIZE(AUDIO)) { 171 DRM_DEV_ERROR(&hdmi->pdev->dev, 172 "failed to configure audio infoframe\n"); 173 return -EINVAL; 174 } 175 176 msm_hdmi_bridge_clear_audio_infoframe(bridge); 177 178 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0, 179 buffer[3] | 180 buffer[4] << 8 | 181 buffer[5] << 16 | 182 buffer[6] << 24); 183 184 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1, 185 buffer[7] | 186 buffer[8] << 8 | 187 buffer[9] << 16 | 188 buffer[10] << 24); 189 190 val = HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 191 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 192 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 193 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE; 194 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, val, val); 195 196 return 0; 197 } 198 199 static int msm_hdmi_bridge_write_spd_infoframe(struct drm_bridge *bridge, 200 const u8 *buffer, size_t len) 201 { 202 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 203 struct hdmi *hdmi = hdmi_bridge->hdmi; 204 u32 buf[7] = {}; 205 u32 val; 206 int i; 207 208 if (len != HDMI_INFOFRAME_SIZE(SPD) || len - 3 > sizeof(buf)) { 209 DRM_DEV_ERROR(&hdmi->pdev->dev, 210 "failed to configure SPD infoframe\n"); 211 return -EINVAL; 212 } 213 214 msm_hdmi_bridge_clear_spd_infoframe(bridge); 215 216 /* checksum gets written together with the body of the frame */ 217 hdmi_write(hdmi, REG_HDMI_GENERIC1_HDR, 218 buffer[0] | 219 buffer[1] << 8 | 220 buffer[2] << 16); 221 222 memcpy(buf, &buffer[3], len - 3); 223 224 for (i = 0; i < ARRAY_SIZE(buf); i++) 225 hdmi_write(hdmi, REG_HDMI_GENERIC1(i), buf[i]); 226 227 val = HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 228 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 229 HDMI_GEN_PKT_CTRL_GENERIC1_LINE(SPD_IFRAME_LINE_NUMBER); 230 hdmi_update_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, val, val); 231 232 return 0; 233 } 234 235 static int msm_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 236 const u8 *buffer, size_t len) 237 { 238 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 239 struct hdmi *hdmi = hdmi_bridge->hdmi; 240 u32 buf[7] = {}; 241 u32 val; 242 int i; 243 244 if (len < HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_SIZE || 245 len - 3 > sizeof(buf)) { 246 DRM_DEV_ERROR(&hdmi->pdev->dev, 247 "failed to configure HDMI infoframe\n"); 248 return -EINVAL; 249 } 250 251 msm_hdmi_bridge_clear_hdmi_infoframe(bridge); 252 253 /* checksum gets written together with the body of the frame */ 254 hdmi_write(hdmi, REG_HDMI_GENERIC0_HDR, 255 buffer[0] | 256 buffer[1] << 8 | 257 buffer[2] << 16); 258 259 memcpy(buf, &buffer[3], len - 3); 260 261 for (i = 0; i < ARRAY_SIZE(buf); i++) 262 hdmi_write(hdmi, REG_HDMI_GENERIC0(i), buf[i]); 263 264 val = HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 265 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 266 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 267 HDMI_GEN_PKT_CTRL_GENERIC0_LINE(VENSPEC_IFRAME_LINE_NUMBER); 268 hdmi_update_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, val, val); 269 270 return 0; 271 } 272 273 static void msm_hdmi_set_timings(struct hdmi *hdmi, 274 const struct drm_display_mode *mode); 275 276 static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 277 struct drm_atomic_commit *state) 278 { 279 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 280 struct hdmi *hdmi = hdmi_bridge->hdmi; 281 struct hdmi_phy *phy = hdmi->phy; 282 struct drm_encoder *encoder = bridge->encoder; 283 struct drm_connector *connector; 284 struct drm_connector_state *conn_state; 285 struct drm_crtc_state *crtc_state; 286 287 DBG("power up"); 288 289 connector = drm_atomic_get_new_connector_for_encoder(state, encoder); 290 conn_state = drm_atomic_get_new_connector_state(state, connector); 291 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 292 293 hdmi->pixclock = conn_state->hdmi.tmds_char_rate; 294 295 msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode); 296 297 scoped_guard(mutex, &hdmi->state_mutex) { 298 if (!hdmi->power_on) { 299 if (msm_hdmi_phy_resource_enable(phy)) 300 return; 301 302 if (msm_hdmi_power_on(bridge)) { 303 msm_hdmi_phy_resource_disable(phy); 304 return; 305 } 306 hdmi->power_on = true; 307 } 308 } 309 310 if (connector->display_info.is_hdmi) 311 msm_hdmi_audio_update(hdmi); 312 313 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 314 315 msm_hdmi_phy_powerup(phy, hdmi->pixclock); 316 317 msm_hdmi_set_mode(hdmi, true); 318 319 if (hdmi->hdcp_ctrl) 320 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl); 321 } 322 323 static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, 324 struct drm_atomic_commit *state) 325 { 326 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 327 struct hdmi *hdmi = hdmi_bridge->hdmi; 328 struct hdmi_phy *phy = hdmi->phy; 329 330 if (hdmi->hdcp_ctrl) 331 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl); 332 333 DBG("power down"); 334 335 /* Keep the HDMI enabled if the HPD is enabled */ 336 mutex_lock(&hdmi->state_mutex); 337 msm_hdmi_set_mode(hdmi, hdmi->hpd_enabled); 338 339 msm_hdmi_phy_powerdown(phy); 340 341 if (hdmi->power_on) { 342 hdmi->power_on = false; 343 if (hdmi->connector->display_info.is_hdmi) 344 msm_hdmi_audio_update(hdmi); 345 power_off(bridge); 346 msm_hdmi_phy_resource_disable(phy); 347 } 348 mutex_unlock(&hdmi->state_mutex); 349 } 350 351 static void msm_hdmi_set_timings(struct hdmi *hdmi, 352 const struct drm_display_mode *mode) 353 { 354 int hstart, hend, vstart, vend; 355 u32 frame_ctrl; 356 357 hstart = mode->htotal - mode->hsync_start; 358 hend = mode->htotal - mode->hsync_start + mode->hdisplay; 359 360 vstart = mode->vtotal - mode->vsync_start - 1; 361 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1; 362 363 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d", 364 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); 365 366 hdmi_write(hdmi, REG_HDMI_TOTAL, 367 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) | 368 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1)); 369 370 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC, 371 HDMI_ACTIVE_HSYNC_START(hstart) | 372 HDMI_ACTIVE_HSYNC_END(hend)); 373 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC, 374 HDMI_ACTIVE_VSYNC_START(vstart) | 375 HDMI_ACTIVE_VSYNC_END(vend)); 376 377 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 378 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 379 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal)); 380 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 381 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) | 382 HDMI_VSYNC_ACTIVE_F2_END(vend + 1)); 383 } else { 384 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 385 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0)); 386 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 387 HDMI_VSYNC_ACTIVE_F2_START(0) | 388 HDMI_VSYNC_ACTIVE_F2_END(0)); 389 } 390 391 frame_ctrl = 0; 392 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 393 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW; 394 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 395 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW; 396 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 397 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN; 398 DBG("frame_ctrl=%08x", frame_ctrl); 399 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl); 400 } 401 402 static const struct drm_edid *msm_hdmi_bridge_edid_read(struct drm_bridge *bridge, 403 struct drm_connector *connector) 404 { 405 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 406 struct hdmi *hdmi = hdmi_bridge->hdmi; 407 const struct drm_edid *drm_edid; 408 u32 hdmi_ctrl; 409 410 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); 411 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); 412 413 drm_edid = drm_edid_read_ddc(connector, hdmi->i2c); 414 415 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); 416 417 return drm_edid; 418 } 419 420 static enum drm_mode_status msm_hdmi_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 421 const struct drm_display_mode *mode, 422 unsigned long long tmds_rate) 423 { 424 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 425 struct hdmi *hdmi = hdmi_bridge->hdmi; 426 struct msm_drm_private *priv = bridge->dev->dev_private; 427 struct msm_kms *kms = priv->kms; 428 long actual; 429 430 /* for mdp5/apq8074, we manage our own pixel clk (as opposed to 431 * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder 432 * instead): 433 */ 434 if (kms->funcs->round_pixclk) 435 actual = kms->funcs->round_pixclk(kms, 436 tmds_rate, 437 hdmi_bridge->hdmi->encoder); 438 else if (hdmi->extp_clk) 439 actual = clk_round_rate(hdmi->extp_clk, tmds_rate); 440 else 441 actual = tmds_rate; 442 443 DBG("requested=%lld, actual=%ld", tmds_rate, actual); 444 445 if (actual != tmds_rate) 446 return MODE_CLOCK_RANGE; 447 448 return 0; 449 } 450 451 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { 452 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 453 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 454 .atomic_create_state = drm_atomic_helper_bridge_create_state, 455 .atomic_pre_enable = msm_hdmi_bridge_atomic_pre_enable, 456 .atomic_post_disable = msm_hdmi_bridge_atomic_post_disable, 457 .edid_read = msm_hdmi_bridge_edid_read, 458 .detect = msm_hdmi_bridge_detect, 459 .hpd_enable = msm_hdmi_hpd_enable, 460 .hpd_disable = msm_hdmi_hpd_disable, 461 .hdmi_tmds_char_rate_valid = msm_hdmi_bridge_tmds_char_rate_valid, 462 .hdmi_clear_audio_infoframe = msm_hdmi_bridge_clear_audio_infoframe, 463 .hdmi_write_audio_infoframe = msm_hdmi_bridge_write_audio_infoframe, 464 .hdmi_clear_avi_infoframe = msm_hdmi_bridge_clear_avi_infoframe, 465 .hdmi_write_avi_infoframe = msm_hdmi_bridge_write_avi_infoframe, 466 .hdmi_clear_spd_infoframe = msm_hdmi_bridge_clear_spd_infoframe, 467 .hdmi_write_spd_infoframe = msm_hdmi_bridge_write_spd_infoframe, 468 .hdmi_clear_hdmi_infoframe = msm_hdmi_bridge_clear_hdmi_infoframe, 469 .hdmi_write_hdmi_infoframe = msm_hdmi_bridge_write_hdmi_infoframe, 470 .hdmi_audio_prepare = msm_hdmi_bridge_audio_prepare, 471 .hdmi_audio_shutdown = msm_hdmi_bridge_audio_shutdown, 472 }; 473 474 static void 475 msm_hdmi_hotplug_work(struct work_struct *work) 476 { 477 struct hdmi_bridge *hdmi_bridge = 478 container_of(work, struct hdmi_bridge, hpd_work); 479 struct drm_bridge *bridge = &hdmi_bridge->base; 480 481 drm_bridge_hpd_notify(bridge, drm_bridge_detect(bridge, hdmi_bridge->hdmi->connector)); 482 } 483 484 /* initialize bridge */ 485 int msm_hdmi_bridge_init(struct hdmi *hdmi) 486 { 487 struct drm_bridge *bridge; 488 struct hdmi_bridge *hdmi_bridge; 489 int ret; 490 491 hdmi_bridge = devm_drm_bridge_alloc(hdmi->dev->dev, struct hdmi_bridge, base, 492 &msm_hdmi_bridge_funcs); 493 if (IS_ERR(hdmi_bridge)) 494 return PTR_ERR(hdmi_bridge); 495 496 hdmi_bridge->hdmi = hdmi; 497 INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work); 498 499 bridge = &hdmi_bridge->base; 500 bridge->ddc = hdmi->i2c; 501 bridge->type = DRM_MODE_CONNECTOR_HDMIA; 502 bridge->vendor = "Qualcomm"; 503 bridge->product = "Snapdragon"; 504 bridge->ops = DRM_BRIDGE_OP_HPD | 505 DRM_BRIDGE_OP_DETECT | 506 DRM_BRIDGE_OP_HDMI | 507 DRM_BRIDGE_OP_HDMI_AUDIO | 508 DRM_BRIDGE_OP_EDID; 509 bridge->hdmi_audio_max_i2s_playback_channels = 8; 510 bridge->hdmi_audio_dev = &hdmi->pdev->dev; 511 bridge->hdmi_audio_dai_port = -1; 512 513 ret = devm_drm_bridge_add(hdmi->dev->dev, bridge); 514 if (ret) 515 return ret; 516 517 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 518 if (ret) 519 return ret; 520 521 hdmi->bridge = bridge; 522 523 return 0; 524 } 525