1 /*- 2 * Copyright (c) 2025, Samsung Electronics Co., Ltd. 3 * Written by Jaeyoon Choi 4 * 5 * SPDX-License-Identifier: BSD-2-Clause 6 */ 7 #ifndef __UFSHCI_REG_H__ 8 #define __UFSHCI_REG_H__ 9 10 #include <sys/param.h> 11 #include <sys/endian.h> 12 13 /* UFSHCI 4.1, section 5.1 Register Map */ 14 struct ufshci_registers { 15 /* Host Capabilities (00h) */ 16 uint32_t cap; /* Host Controller Capabiities */ 17 uint32_t mcqcap; /* Multi-Circular Queue Capability Register */ 18 uint32_t ver; /* UFS Version */ 19 uint32_t ext_cap; /* Extended Controller Capabilities */ 20 uint32_t hcpid; /* Product ID */ 21 uint32_t hcmid; /* Manufacturer ID */ 22 uint32_t ahit; /* Auto-Hibernate Idle Timer */ 23 uint32_t reserved1; 24 /* Operation and Runtime (20h) */ 25 uint32_t is; /* Interrupt Status */ 26 uint32_t ie; /* Interrupt Enable */ 27 uint32_t reserved2; 28 uint32_t hcsext; /* Host Controller Status Extended */ 29 uint32_t hcs; /* Host Controller Status */ 30 uint32_t hce; /* Host Controller Enable */ 31 uint32_t uecpa; /* Host UIC Error Code PHY Adapter Layer */ 32 uint32_t uecdl; /* Host UIC Error Code Data Link Layer */ 33 uint32_t uecn; /* Host UIC Error Code Network Layer */ 34 uint32_t uect; /* Host UIC Error Code Transport Layer */ 35 uint32_t uecdme; /* Host UIC Error Code DME */ 36 uint32_t utriacr; /* Interrupt Aggregation Control */ 37 /* UTP Transfer (50h) */ 38 uint32_t utrlba; /* UTRL Base Address */ 39 uint32_t utrlbau; /* UTRL Base Address Upper 32-Bits */ 40 uint32_t utrldbr; /* UTRL DoorBell Register */ 41 uint32_t utrlclr; /* UTRL CLear Register */ 42 uint32_t utrlrsr; /* UTR Run-Stop Register */ 43 uint32_t utrlcnr; /* UTRL Completion Notification */ 44 uint64_t reserved3; 45 /* UTP Task Managemeng (70h) */ 46 uint32_t utmrlba; /* UTRL Base Address */ 47 uint32_t utmrlbau; /* UTMRL Base Address Upper 32-Bits */ 48 uint32_t utmrldbr; /* UTMRL DoorBell Register */ 49 uint32_t utmrlclr; /* UTMRL CLear Register */ 50 uint32_t utmrlrsr; /* UTM Run-Stop Register */ 51 uint8_t reserved4[12]; 52 /* UIC Command (90h) */ 53 uint32_t uiccmd; /* UIC Command Register */ 54 uint32_t ucmdarg1; /* UIC Command Argument 1 */ 55 uint32_t ucmdarg2; /* UIC Command Argument 2 */ 56 uint32_t ucmdarg3; /* UIC Command Argument 3 */ 57 uint8_t reserved5[16]; 58 /* UMA (B0h) */ 59 uint8_t reserved6[16]; /* Reserved for Unified Memory Extension */ 60 /* Vendor Specific (C0h) */ 61 uint8_t vendor[64]; /* Vendor Specific Registers */ 62 /* Crypto (100h) */ 63 uint32_t ccap; /* Crypto Capability */ 64 uint8_t reserved7[508]; 65 /* Config (300h) */ 66 uint32_t config; /* Global Configuration */ 67 uint8_t reserved9[124]; 68 /* MCQ Configuration (380h) */ 69 uint32_t mcqconfig; /* MCQ Config Register */ 70 /* Event Specific Interrupt Lower Base Address */ 71 uint32_t esilba; 72 /* Event Specific Interrupt Upper Base Address */ 73 uint32_t esiuba; 74 /* TODO: Need to define SQ/CQ registers */ 75 }; 76 77 _Static_assert(__offsetof(struct ufshci_registers, is) == 0x20, 78 "operation and runtime section must start at 20h"); 79 _Static_assert(__offsetof(struct ufshci_registers, utrlba) == 0x50, 80 "UTP transfer section must start at 50h"); 81 _Static_assert(__offsetof(struct ufshci_registers, utmrlba) == 0x70, 82 "UTP task management section must start at 70h"); 83 _Static_assert(__offsetof(struct ufshci_registers, uiccmd) == 0x90, 84 "UIC command section must start at 90h"); 85 _Static_assert(__offsetof(struct ufshci_registers, vendor) == 0xC0, 86 "vendor specific section must start at C0h"); 87 _Static_assert(__offsetof(struct ufshci_registers, ccap) == 0x100, 88 "crypto section must start at 100h"); 89 _Static_assert(__offsetof(struct ufshci_registers, config) == 0x300, 90 "config section must start at 300h"); 91 _Static_assert(__offsetof(struct ufshci_registers, mcqconfig) == 0x380, 92 "MCQ configuration section must start at 380h"); 93 94 /* Register field definitions */ 95 #define UFSHCI__REG__SHIFT (0) 96 #define UFSHCI__REG__MASK (0) 97 98 /* 99 * UFSHCI 4.1, section 5.2.1, Offset 00h: CAP 100 * Controller Capabilities 101 */ 102 #define UFSHCI_CAP_REG_NUTRS_SHIFT (0) 103 #define UFSHCI_CAP_REG_NUTRS_MASK (0xFF) 104 #define UFSHCI_CAP_REG_NORTT_SHIFT (8) 105 #define UFSHCI_CAP_REG_NORTT_MASK (0xFF) 106 #define UFSHCI_CAP_REG_NUTMRS_SHIFT (16) 107 #define UFSHCI_CAP_REG_NUTMRS_MASK (0x7) 108 #define UFSHCI_CAP_REG_EHSLUTRDS_SHIFT (22) 109 #define UFSHCI_CAP_REG_EHSLUTRDS_MASK (0x1) 110 #define UFSHCI_CAP_REG_AUTOH8_SHIFT (23) 111 #define UFSHCI_CAP_REG_AUTOH8_MASK (0x1) 112 #define UFSHCI_CAP_REG_64AS_SHIFT (24) 113 #define UFSHCI_CAP_REG_64AS_MASK (0x1) 114 #define UFSHCI_CAP_REG_OODDS_SHIFT (25) 115 #define UFSHCI_CAP_REG_OODDS_MASK (0x1) 116 #define UFSHCI_CAP_REG_UICDMETMS_SHIFT (26) 117 #define UFSHCI_CAP_REG_UICDMETMS_MASK (0x1) 118 #define UFSHCI_CAP_REG_CS_SHIFT (28) 119 #define UFSHCI_CAP_REG_CS_MASK (0x1) 120 #define UFSHCI_CAP_REG_LSDBS_SHIFT (29) 121 #define UFSHCI_CAP_REG_LSDBS_MASK (0x1) 122 #define UFSHCI_CAP_REG_MCQS_SHIFT (30) 123 #define UFSHCI_CAP_REG_MCQS_MASK (0x1) 124 #define UFSHCI_CAP_REG_EIS_SHIFT (31) 125 #define UFSHCI_CAP_REG_EIS_MASK (0x1) 126 127 /* 128 * UFSHCI 4.1, section 5.2.2, Offset 04h: MCQCAP 129 * Multi-Circular Queue Capability Register 130 */ 131 #define UFSHCI_MCQCAP_REG_MAXQ_SHIFT (0) 132 #define UFSHCI_MCQCAP_REG_MAXQ_MASK (0xFF) 133 #define UFSHCI_MCQCAP_REG_SP_SHIFT (8) 134 #define UFSHCI_MCQCAP_REG_SP_MASK (0x1) 135 #define UFSHCI_MCQCAP_REG_RRP_SHIFT (9) 136 #define UFSHCI_MCQCAP_REG_RRP_MASK (0x1) 137 #define UFSHCI_MCQCAP_REG_EIS_SHIFT (10) 138 #define UFSHCI_MCQCAP_REG_EIS_MASK (0x1) 139 #define UFSHCI_MCQCAP_REG_QCFGPTR_SHIFT (16) 140 #define UFSHCI_MCQCAP_REG_QCFGPTR_MASK (0xFF) 141 #define UFSHCI_MCQCAP_REG_MIAG_SHIFT (24) 142 #define UFSHCI_MCQCAP_REG_MIAG_MASK (0xFF) 143 144 /* 145 * UFSHCI 4.1, section 5.2.3, Offset 08h: VER 146 * UFS Version 147 */ 148 #define UFSHCI_VER_REG_VS_SHIFT (0) 149 #define UFSHCI_VER_REG_VS_MASK (0xF) 150 #define UFSHCI_VER_REG_MNR_SHIFT (4) 151 #define UFSHCI_VER_REG_MNR_MASK (0xF) 152 #define UFSHCI_VER_REG_MJR_SHIFT (8) 153 #define UFSHCI_VER_REG_MJR_MASK (0xFF) 154 155 /* 156 * UFSHCI 4.1, section 5.2.4, Offset 0Ch: EXT_CAP 157 * Extended Controller Capabilities 158 */ 159 #define UFSHCI_EXTCAP_REG_HOST_HINT_CACAHE_SIZE_SHIFT (0) 160 #define UFSHCI_EXTCAP_REG_HOST_HINT_CACAHE_SIZE_MASK (0xFFFF) 161 162 /* 163 * UFSHCI 4.1, section 5.2.5, Offset 10h: HCPID 164 * Host Controller Identification Descriptor – Product ID 165 */ 166 #define UFSHCI_HCPID_REG_PID_SHIFT (0) 167 #define UFSHCI_HCPID_REG_PID_MASK (0xFFFFFFFF) 168 169 /* 170 * UFSHCI 4.1, section 5.2.6, Offset 14h: HCMID 171 * Host Controller Identification Descriptor – Manufacturer ID 172 */ 173 #define UFSHCI_HCMID_REG_MIC_SHIFT (0) 174 #define UFSHCI_HCMID_REG_MIC_MASK (0xFFFF) 175 #define UFSHCI_HCMID_REG_BI_SHIFT (16) 176 #define UFSHCI_HCMID_REG_BI_MASK (0xFF) 177 178 /* 179 * UFSHCI 4.1, section 5.2.7, Offset 18h: AHIT 180 * Auto-Hibernate Idle Timer 181 */ 182 #define UFSHCI_AHIT_REG_AH8ITV_SHIFT (0) 183 #define UFSHCI_AHIT_REG_AH8ITV_MASK (0x3FF) 184 #define UFSHCI_AHIT_REG_TS_SHIFT (10) 185 #define UFSHCI_AHIT_REG_TS_MASK (0x7) 186 187 /* 188 * UFSHCI 4.1, section 5.3.1, Offset 20h: IS 189 * Interrupt Status 190 */ 191 #define UFSHCI_IS_REG_UTRCS_SHIFT (0) 192 #define UFSHCI_IS_REG_UTRCS_MASK (0x1) 193 #define UFSHCI_IS_REG_UDEPRI_SHIFT (1) 194 #define UFSHCI_IS_REG_UDEPRI_MASK (0x1) 195 #define UFSHCI_IS_REG_UE_SHIFT (2) 196 #define UFSHCI_IS_REG_UE_MASK (0x1) 197 #define UFSHCI_IS_REG_UTMS_SHIFT (3) 198 #define UFSHCI_IS_REG_UTMS_MASK (0x1) 199 #define UFSHCI_IS_REG_UPMS_SHIFT (4) 200 #define UFSHCI_IS_REG_UPMS_MASK (0x1) 201 #define UFSHCI_IS_REG_UHXS_SHIFT (5) 202 #define UFSHCI_IS_REG_UHXS_MASK (0x1) 203 #define UFSHCI_IS_REG_UHES_SHIFT (6) 204 #define UFSHCI_IS_REG_UHES_MASK (0x1) 205 #define UFSHCI_IS_REG_ULLS_SHIFT (7) 206 #define UFSHCI_IS_REG_ULLS_MASK (0x1) 207 #define UFSHCI_IS_REG_ULSS_SHIFT (8) 208 #define UFSHCI_IS_REG_ULSS_MASK (0x1) 209 #define UFSHCI_IS_REG_UTMRCS_SHIFT (9) 210 #define UFSHCI_IS_REG_UTMRCS_MASK (0x1) 211 #define UFSHCI_IS_REG_UCCS_SHIFT (10) 212 #define UFSHCI_IS_REG_UCCS_MASK (0x1) 213 #define UFSHCI_IS_REG_DFES_SHIFT (11) 214 #define UFSHCI_IS_REG_DFES_MASK (0x1) 215 #define UFSHCI_IS_REG_UTPES_SHIFT (12) 216 #define UFSHCI_IS_REG_UTPES_MASK (0x1) 217 #define UFSHCI_IS_REG_HCFES_SHIFT (16) 218 #define UFSHCI_IS_REG_HCFES_MASK (0x1) 219 #define UFSHCI_IS_REG_SBFES_SHIFT (17) 220 #define UFSHCI_IS_REG_SBFES_MASK (0x1) 221 #define UFSHCI_IS_REG_CEFES_SHIFT (18) 222 #define UFSHCI_IS_REG_CEFES_MASK (0x1) 223 #define UFSHCI_IS_REG_SQES_SHIFT (19) 224 #define UFSHCI_IS_REG_SQES_MASK (0x1) 225 #define UFSHCI_IS_REG_CQES_SHIFT (20) 226 #define UFSHCI_IS_REG_CQES_MASK (0x1) 227 #define UFSHCI_IS_REG_IAGES_SHIFT (21) 228 #define UFSHCI_IS_REG_IAGES_MASK (0x1) 229 230 /* 231 * UFSHCI 4.1, section 5.3.2, Offset 24h: IE 232 * Interrupt Enable 233 */ 234 #define UFSHCI_IE_REG_UTRCE_SHIFT (0) 235 #define UFSHCI_IE_REG_UTRCE_MASK (0x1) 236 #define UFSHCI_IE_REG_UDEPRIE_SHIFT (1) 237 #define UFSHCI_IE_REG_UDEPRIE_MASK (0x1) 238 #define UFSHCI_IE_REG_UEE_SHIFT (2) 239 #define UFSHCI_IE_REG_UEE_MASK (0x1) 240 #define UFSHCI_IE_REG_UTMSE_SHIFT (3) 241 #define UFSHCI_IE_REG_UTMSE_MASK (0x1) 242 #define UFSHCI_IE_REG_UPMSE_SHIFT (4) 243 #define UFSHCI_IE_REG_UPMSE_MASK (0x1) 244 #define UFSHCI_IE_REG_UHXSE_SHIFT (5) 245 #define UFSHCI_IE_REG_UHXSE_MASK (0x1) 246 #define UFSHCI_IE_REG_UHESE_SHIFT (6) 247 #define UFSHCI_IE_REG_UHESE_MASK (0x1) 248 #define UFSHCI_IE_REG_ULLSE_SHIFT (7) 249 #define UFSHCI_IE_REG_ULLSE_MASK (0x1) 250 #define UFSHCI_IE_REG_ULSSE_SHIFT (8) 251 #define UFSHCI_IE_REG_ULSSE_MASK (0x1) 252 #define UFSHCI_IE_REG_UTMRCE_SHIFT (9) 253 #define UFSHCI_IE_REG_UTMRCE_MASK (0x1) 254 #define UFSHCI_IE_REG_UCCE_SHIFT (10) 255 #define UFSHCI_IE_REG_UCCE_MASK (0x1) 256 #define UFSHCI_IE_REG_DFEE_SHIFT (11) 257 #define UFSHCI_IE_REG_DFEE_MASK (0x1) 258 #define UFSHCI_IE_REG_UTPEE_SHIFT (12) 259 #define UFSHCI_IE_REG_UTPEE_MASK (0x1) 260 #define UFSHCI_IE_REG_HCFEE_SHIFT (16) 261 #define UFSHCI_IE_REG_HCFEE_MASK (0x1) 262 #define UFSHCI_IE_REG_SBFEE_SHIFT (17) 263 #define UFSHCI_IE_REG_SBFEE_MASK (0x1) 264 #define UFSHCI_IE_REG_CEFEE_SHIFT (18) 265 #define UFSHCI_IE_REG_CEFEE_MASK (0x1) 266 #define UFSHCI_IE_REG_SQEE_SHIFT (19) 267 #define UFSHCI_IE_REG_SQEE_MASK (0x1) 268 #define UFSHCI_IE_REG_CQEE_SHIFT (20) 269 #define UFSHCI_IE_REG_CQEE_MASK (0x1) 270 #define UFSHCI_IE_REG_IAGEE_SHIFT (21) 271 #define UFSHCI_IE_REG_IAGEE_MASK (0x1) 272 273 /* 274 * UFSHCI 4.1, section 5.3.3, Offset 2Ch: HCSEXT 275 * Host Controller Status Extended 276 */ 277 #define UFSHCI_HCSEXT_IIDUTPE_SHIFT (0) 278 #define UFSHCI_HCSEXT_IIDUTPE_MASK (0xF) 279 #define UFSHCI_HCSEXT_EXT_IIDUTPE_SHIFT (4) 280 #define UFSHCI_HCSEXT_EXT_IIDUTPE_MASK (0xF) 281 282 /* 283 * UFSHCI 4.1, section 5.3.4, Offset 30h: HCS 284 * Host Controller Status 285 */ 286 #define UFSHCI_HCS_REG_DP_SHIFT (0) 287 #define UFSHCI_HCS_REG_DP_MASK (0x1) 288 #define UFSHCI_HCS_REG_UTRLRDY_SHIFT (1) 289 #define UFSHCI_HCS_REG_UTRLRDY_MASK (0x1) 290 #define UFSHCI_HCS_REG_UTMRLRDY_SHIFT (2) 291 #define UFSHCI_HCS_REG_UTMRLRDY_MASK (0x1) 292 #define UFSHCI_HCS_REG_UCRDY_SHIFT (3) 293 #define UFSHCI_HCS_REG_UCRDY_MASK (0x1) 294 #define UFSHCI_HCS_REG_UPMCRS_SHIFT (8) 295 #define UFSHCI_HCS_REG_UPMCRS_MASK (0x7) 296 #define UFSHCI_HCS_REG_UTPEC_SHIFT (12) 297 #define UFSHCI_HCS_REG_UTPEC_MASK (0xF) 298 #define UFSHCI_HCS_REG_TTAGUTPE_SHIFT (16) 299 #define UFSHCI_HCS_REG_TTAGUTPE_MASK (0xFF) 300 #define UFSHCI_HCS_REG_TLUNUTPE_SHIFT (24) 301 #define UFSHCI_HCS_REG_TLUNUTPE_MASK (0xFF) 302 303 /* 304 * UFSHCI 4.1, section 5.3.5, Offset 34h: HCE 305 * Host Controller Enable 306 */ 307 #define UFSHCI_HCE_REG_HCE_SHIFT (0) 308 #define UFSHCI_HCE_REG_HCE_MASK (0x1) 309 #define UFSHCI_HCE_REG_CGE_SHIFT (1) 310 #define UFSHCI_HCE_REG_CGE_MASK (0x1) 311 312 /* 313 * UFSHCI 4.1, section 5.3.6, Offset 38h: UECPA 314 * Host UIC Error Code PHY Adapter Layer 315 */ 316 #define UFSHCI_UECPA_REG_EC_SHIFT (0) 317 #define UFSHCI_UECPA_REG_EC_MASK (0xF) 318 #define UFSHCI_UECPA_REG_ERR_SHIFT (31) 319 #define UFSHCI_UECPA_REG_ERR_MASK (0x1) 320 321 /* 322 * UFSHCI 4.1, section 5.3.7, Offset 3Ch: UECDL 323 * Host UIC Error Code Data Link Layer 324 */ 325 #define UFSHCI_UECDL_REG_EC_SHIFT (0) 326 #define UFSHCI_UECDL_REG_EC_MASK (0xFFFF) 327 #define UFSHCI_UECDL_REG_ERR_SHIFT (31) 328 #define UFSHCI_UECDL_REG_ERR_MASK (0x1) 329 330 /* 331 * UFSHCI 4.1, section 5.3.8, Offset 40h: UECN 332 * Host UIC Error Code Network Layer 333 */ 334 #define UFSHCI_UECN_REG_EC_SHIFT (0) 335 #define UFSHCI_UECN_REG_EC_MASK (0x7) 336 #define UFSHCI_UECN_REG_ERR_SHIFT (31) 337 #define UFSHCI_UECN_REG_ERR_MASK (0x1) 338 339 /* 340 * UFSHCI 4.1, section 5.3.9, Offset 44h: UECT 341 * Host UIC Error Code Transport Layer 342 */ 343 #define UFSHCI_UECT_REG_EC_SHIFT (0) 344 #define UFSHCI_UECT_REG_EC_MASK (0x7F) 345 #define UFSHCI_UECT_REG_ERR_SHIFT (31) 346 #define UFSHCI_UECT_REG_ERR_MASK (0x1) 347 348 /* 349 * UFSHCI 4.1, section 5.3.10, Offset 48h: UECDME 350 * Host UIC Error Code 351 */ 352 #define UFSHCI_UECDME_REG_EC_SHIFT (0) 353 #define UFSHCI_UECDME_REG_EC_MASK (0xF) 354 #define UFSHCI_UECDME_REG_ERR_SHIFT (31) 355 #define UFSHCI_UECDME_REG_ERR_MASK (0x1) 356 357 /* 358 * UFSHCI 4.1, section 5.4.1, Offset 50h: UTRLBA 359 * UTP Transfer Request List Base Address 360 */ 361 #define UFSHCI_UTRLBA_REG_UTRLBA_SHIFT (0) 362 #define UFSHCI_UTRLBA_REG_UTRLBA_MASK (0xFFFFFFFF) 363 364 /* 365 * UFSHCI 4.1, section 5.4.2, Offset 54h: UTRLBAU 366 * UTP Transfer Request List Base Address Upper 32-bits 367 */ 368 #define UFSHCI_UTRLBAU_REG_UTRLBAU_SHIFT (0) 369 #define UFSHCI_UTRLBAU_REG_UTRLBAU_MASK (0xFFFFFFFF) 370 371 /* 372 * UFSHCI 4.1, section 5.4.3, Offset 58h: UTRLDBR 373 * UTP Transfer Request List Door Bell Register 374 */ 375 #define UFSHCI_UTRLDBR_REG_UTRLDBR_SHIFT (0) 376 #define UFSHCI_UTRLDBR_REG_UTRLDBR_MASK (0xFFFFFFFF) 377 378 /* 379 * UFSHCI 4.1, section 5.4.4, Offset 5Ch: UTRLCLR 380 * UTP Transfer Request List Clear Register 381 */ 382 #define UFSHCI_UTRLCLR_REG_UTRLCLR_SHIFT (0) 383 #define UFSHCI_UTRLCLR_REG_UTRLCLR_MASK (0xFFFFFFFF) 384 385 /* 386 * UFSHCI 4.1, section 5.4.5, Offset 60h: UTRLRSR 387 * UTP Transfer Request List Run Stop Register 388 */ 389 #define UFSHCI_UTRLRSR_REG_UTRLRSR_SHIFT (0) 390 #define UFSHCI_UTRLRSR_REG_UTRLRSR_MASK (0x1) 391 392 /* 393 * UFSHCI 4.1, section 5.4.6, Offset 64h: UTRLCNR 394 * UTP Transfer Request List Completion Notification Register 395 */ 396 #define UFSHCI_UTRLCNR_REG_UTRLCNR_SHIFT (0) 397 #define UFSHCI_UTRLCNR_REG_UTRLCNR_MASK (0xFFFFFFFF) 398 399 /* 400 * UFSHCI 4.1, section 5.5.1, Offset 70h: UTMRLBA 401 * UTP Task Management Request List Base Address 402 */ 403 #define UFSHCI_UTMRLBA_REG_UTMRLBA_SHIFT (0) 404 #define UFSHCI_UTMRLBA_REG_UTMRLBA_MASK (0xFFFFFFFF) 405 406 /* 407 * UFSHCI 4.1, section 5.5.2, Offset 74h: UTMRLBAU 408 * UTP Task Management Request List Base Address Upper 32-bits 409 */ 410 #define UFSHCI_UTMRLBAU_REG_UTMRLBAU_SHIFT (0) 411 #define UFSHCI_UTMRLBAU_REG_UTMRLBAU_MASK (0xFFFFFFFF) 412 413 /* 414 * UFSHCI 4.1, section 5.5.3, Offset 78h: UTMRLDBR 415 * UTP Task Management Request List Door Bell Register 416 */ 417 #define UFSHCI_UTMRLDBR_REG_UTMRLDBR_SHIFT (0) 418 #define UFSHCI_UTMRLDBR_REG_UTMRLDBR_MASK (0xFF) 419 420 /* 421 * UFSHCI 4.1, section 5.5.4, Offset 7Ch: UTMRLCLR 422 * UTP Task Management Request List CLear Register 423 */ 424 #define UFSHCI_UTMRLCLR_REG_UTMRLCLR_SHIFT (0) 425 #define UFSHCI_UTMRLCLR_REG_UTMRLCLR_MASK (0xFF) 426 427 /* 428 * UFSHCI 4.1, section 5.5.5, Offset 80h: UTMRLRSR 429 * UTP Task Management Request List Run Stop Register 430 */ 431 #define UFSHCI_UTMRLRSR_REG_UTMRLRSR_SHIFT (0) 432 #define UFSHCI_UTMRLRSR_REG_UTMRLRSR_MASK (0xFF) 433 434 /* 435 * UFSHCI 4.1, section 5.6.1 436 * Offset 90h: UICCMD – UIC Command 437 */ 438 #define UFSHCI_UICCMD_REG_CMDOP_SHIFT (0) 439 #define UFSHCI_UICCMD_REG_CMDOP_MASK (0xFF) 440 441 /* 442 * UFSHCI 4.1, section 5.6.2 443 * Offset 94h: UICCMDARG1 – UIC Command Argument 1 444 */ 445 #define UFSHCI_UICCMDARG1_REG_ARG1_SHIFT (0) 446 #define UFSHCI_UICCMDARG1_REG_ARG1_MASK (0xFFFFFFFF) 447 #define UFSHCI_UICCMDARG1_REG_GEN_SELECTOR_INDEX_SHIFT (0) 448 #define UFSHCI_UICCMDARG1_REG_GEN_SELECTOR_INDEX_MASK (0xFFFF) 449 #define UFSHCI_UICCMDARG1_REG_MIB_ATTR_SHIFT (16) 450 #define UFSHCI_UICCMDARG1_REG_MIB_ATTR_MASK (0xFFFF) 451 452 /* 453 * UFSHCI 4.1, section 5.6.3 454 * Offset 98h: UICCMDARG2 – UIC Command Argument 2 455 */ 456 #define UFSHCI_UICCMDARG2_REG_ARG2_SHIFT (0) 457 #define UFSHCI_UICCMDARG2_REG_ARG2_MASK (0xFFFFFFFF) 458 #define UFSHCI_UICCMDARG2_REG_ERROR_CODE_SHIFT (0) 459 #define UFSHCI_UICCMDARG2_REG_ERROR_CODE_MASK (0xFF) 460 #define UFSHCI_UICCMDARG2_REG_ATTR_SET_TYPE_SHIFT (16) 461 #define UFSHCI_UICCMDARG2_REG_ATTR_SET_TYPE_MASK (0xFF) 462 463 /* 464 * UFSHCI 4.1, section 5.6.4 465 * Offset 9Ch: UICCMDARG3 – UIC Command Argument 3 466 */ 467 #define UFSHCI_UICCMDARG3_REG_ARG3_SHIFT (0) 468 #define UFSHCI_UICCMDARG3_REG_ARG3_MASK (0xFFFFFFFF) 469 470 /* Helper macro to combine *_MASK and *_SHIFT defines */ 471 #define UFSHCIM(name) (name##_MASK << name##_SHIFT) 472 473 /* Helper macro to extract value from x */ 474 #define UFSHCIV(name, x) (((x) >> name##_SHIFT) & name##_MASK) 475 476 /* Helper macro to construct a field value */ 477 #define UFSHCIF(name, x) (((x)&name##_MASK) << name##_SHIFT) 478 479 #define UFSHCI_DUMP_REG(ctrlr, member) \ 480 do { \ 481 uint32_t _val = ufshci_mmio_read_4(ctrlr, member); \ 482 ufshci_printf(ctrlr, " %-15s (0x%03lx) : 0x%08x\n", #member, \ 483 ufshci_mmio_offsetof(member), _val); \ 484 } while (0) 485 486 #endif /* __UFSHCI_REG_H__ */ 487