1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 4 // with eint support. 5 // 6 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 7 // http://www.samsung.com 8 // Copyright (c) 2012 Linaro Ltd 9 // http://www.linaro.org 10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/slab.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 19 #include "pinctrl-samsung.h" 20 #include "pinctrl-exynos.h" 21 22 static const struct samsung_pin_bank_type bank_type_off = { 23 .fld_width = { 4, 1, 2, 2, 2, 2, }, 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 25 }; 26 27 static const struct samsung_pin_bank_type bank_type_alive = { 28 .fld_width = { 4, 1, 2, 2, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 30 }; 31 32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 34 .fld_width = { 4, 1, 2, 4, 2, 2, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 36 }; 37 38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 39 .fld_width = { 4, 1, 2, 4, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 41 }; 42 43 /* 44 * Bank type for alive type. Bit fields: 45 * CON: 4, DAT: 1, PUD: 2, DRV: 3 46 */ 47 static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { 48 .fld_width = { 4, 1, 2, 3, }, 49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 50 }; 51 52 /* 53 * Bank type for non-alive type. Bit fields: 54 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 55 */ 56 static const struct samsung_pin_bank_type exynos850_bank_type_off = { 57 .fld_width = { 4, 1, 4, 4, 2, 4, }, 58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 59 }; 60 61 /* 62 * Bank type for alive type. Bit fields: 63 * CON: 4, DAT: 1, PUD: 4, DRV: 4 64 */ 65 static const struct samsung_pin_bank_type exynos850_bank_type_alive = { 66 .fld_width = { 4, 1, 4, 4, }, 67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 68 }; 69 70 /* 71 * Bank type for non-alive type. Bit fields: 72 * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 73 */ 74 static const struct samsung_pin_bank_type exynos8895_bank_type_off = { 75 .fld_width = { 4, 1, 2, 3, 2, 2, }, 76 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 77 }; 78 79 /* 80 * Bank type for non-alive type. Bit fields: 81 * CON: 4, DAT: 1, PUD: 4, DRV: 4 82 */ 83 static const struct samsung_pin_bank_type artpec_bank_type_off = { 84 .fld_width = { 4, 1, 4, 4, }, 85 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 86 }; 87 88 /* Pad retention control code for accessing PMU regmap */ 89 static atomic_t exynos_shared_retention_refcnt; 90 91 /* pin banks of exynos2200 pin-controller - ALIVE */ 92 static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { 93 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), 94 EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), 95 EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), 96 EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), 97 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), 98 EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), 99 EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), 100 EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), 101 }; 102 103 /* pin banks of exynos2200 pin-controller - CMGP */ 104 static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { 105 EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00), 106 EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04), 107 EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08), 108 EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c), 109 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10), 110 EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14), 111 EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18), 112 EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c), 113 EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20), 114 EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24), 115 EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28), 116 EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c), 117 EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30), 118 EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34), 119 EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38), 120 EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c), 121 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), 122 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), 123 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48), 124 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c), 125 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50), 126 EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54), 127 EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58), 128 }; 129 130 /* pin banks of exynos2200 pin-controller - HSI1 */ 131 static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { 132 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00), 133 }; 134 135 /* pin banks of exynos2200 pin-controller - UFS */ 136 static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { 137 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00), 138 }; 139 140 /* pin banks of exynos2200 pin-controller - HSI1UFS */ 141 static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { 142 EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00), 143 }; 144 145 /* pin banks of exynos2200 pin-controller - PERIC0 */ 146 static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { 147 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00), 148 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04), 149 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08), 150 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c), 151 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), 152 EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14), 153 EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18), 154 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c), 155 EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20), 156 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24), 157 }; 158 159 /* pin banks of exynos2200 pin-controller - PERIC1 */ 160 static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { 161 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00), 162 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04), 163 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08), 164 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c), 165 }; 166 167 /* pin banks of exynos2200 pin-controller - PERIC2 */ 168 static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { 169 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00), 170 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), 171 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), 172 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c), 173 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10), 174 EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14), 175 EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18), 176 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c), 177 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20), 178 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24), 179 EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28), 180 EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c), 181 EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30), 182 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34), 183 EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38), 184 }; 185 186 /* pin banks of exynos2200 pin-controller - VTS */ 187 static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { 188 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00), 189 }; 190 191 static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { 192 { 193 /* pin-controller instance 0 ALIVE data */ 194 .pin_banks = exynos2200_pin_banks0, 195 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks0), 196 .eint_gpio_init = exynos_eint_gpio_init, 197 .eint_wkup_init = exynos_eint_wkup_init, 198 .suspend = exynos_pinctrl_suspend, 199 .resume = exynos_pinctrl_resume, 200 }, { 201 /* pin-controller instance 1 CMGP data */ 202 .pin_banks = exynos2200_pin_banks1, 203 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks1), 204 .eint_gpio_init = exynos_eint_gpio_init, 205 .eint_wkup_init = exynos_eint_wkup_init, 206 .suspend = exynos_pinctrl_suspend, 207 .resume = exynos_pinctrl_resume, 208 }, { 209 /* pin-controller instance 2 HSI1 data */ 210 .pin_banks = exynos2200_pin_banks2, 211 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks2), 212 }, { 213 /* pin-controller instance 3 UFS data */ 214 .pin_banks = exynos2200_pin_banks3, 215 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks3), 216 .eint_gpio_init = exynos_eint_gpio_init, 217 .suspend = exynos_pinctrl_suspend, 218 .resume = exynos_pinctrl_resume, 219 }, { 220 /* pin-controller instance 4 HSI1UFS data */ 221 .pin_banks = exynos2200_pin_banks4, 222 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks4), 223 .eint_gpio_init = exynos_eint_gpio_init, 224 .suspend = exynos_pinctrl_suspend, 225 .resume = exynos_pinctrl_resume, 226 }, { 227 /* pin-controller instance 5 PERIC0 data */ 228 .pin_banks = exynos2200_pin_banks5, 229 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks5), 230 .eint_gpio_init = exynos_eint_gpio_init, 231 .suspend = exynos_pinctrl_suspend, 232 .resume = exynos_pinctrl_resume, 233 }, { 234 /* pin-controller instance 6 PERIC1 data */ 235 .pin_banks = exynos2200_pin_banks6, 236 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks6), 237 .eint_gpio_init = exynos_eint_gpio_init, 238 .suspend = exynos_pinctrl_suspend, 239 .resume = exynos_pinctrl_resume, 240 }, { 241 /* pin-controller instance 7 PERIC2 data */ 242 .pin_banks = exynos2200_pin_banks7, 243 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks7), 244 .eint_gpio_init = exynos_eint_gpio_init, 245 .suspend = exynos_pinctrl_suspend, 246 .resume = exynos_pinctrl_resume, 247 }, { 248 /* pin-controller instance 8 VTS data */ 249 .pin_banks = exynos2200_pin_banks8, 250 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks8), 251 }, 252 }; 253 254 const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = { 255 .ctrl = exynos2200_pin_ctrl, 256 .num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl), 257 }; 258 259 /* pin banks of exynos5433 pin-controller - ALIVE */ 260 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 261 /* Must start with EINTG banks, ordered by EINT group number. */ 262 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 263 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 264 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 265 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 266 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 267 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 268 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 269 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 270 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 271 }; 272 273 /* pin banks of exynos5433 pin-controller - AUD */ 274 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 275 /* Must start with EINTG banks, ordered by EINT group number. */ 276 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 277 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 278 }; 279 280 /* pin banks of exynos5433 pin-controller - CPIF */ 281 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 282 /* Must start with EINTG banks, ordered by EINT group number. */ 283 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 284 }; 285 286 /* pin banks of exynos5433 pin-controller - eSE */ 287 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 288 /* Must start with EINTG banks, ordered by EINT group number. */ 289 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 290 }; 291 292 /* pin banks of exynos5433 pin-controller - FINGER */ 293 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 294 /* Must start with EINTG banks, ordered by EINT group number. */ 295 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 296 }; 297 298 /* pin banks of exynos5433 pin-controller - FSYS */ 299 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 300 /* Must start with EINTG banks, ordered by EINT group number. */ 301 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 302 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 303 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 304 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 305 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 306 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 307 }; 308 309 /* pin banks of exynos5433 pin-controller - IMEM */ 310 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 311 /* Must start with EINTG banks, ordered by EINT group number. */ 312 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 313 }; 314 315 /* pin banks of exynos5433 pin-controller - NFC */ 316 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 317 /* Must start with EINTG banks, ordered by EINT group number. */ 318 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 319 }; 320 321 /* pin banks of exynos5433 pin-controller - PERIC */ 322 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 323 /* Must start with EINTG banks, ordered by EINT group number. */ 324 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 325 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 326 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 327 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 328 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 329 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 330 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 331 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 332 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 333 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 334 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 335 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 336 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 337 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 338 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 339 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 340 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 341 }; 342 343 /* pin banks of exynos5433 pin-controller - TOUCH */ 344 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 345 /* Must start with EINTG banks, ordered by EINT group number. */ 346 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 347 }; 348 349 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 350 static const u32 exynos5433_retention_regs[] = { 351 EXYNOS5433_PAD_RETENTION_TOP_OPTION, 352 EXYNOS5433_PAD_RETENTION_UART_OPTION, 353 EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 354 EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 355 EXYNOS5433_PAD_RETENTION_SPI_OPTION, 356 EXYNOS5433_PAD_RETENTION_MIF_OPTION, 357 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 358 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 359 EXYNOS5433_PAD_RETENTION_UFS_OPTION, 360 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 361 }; 362 363 static const struct samsung_retention_data exynos5433_retention_data __initconst = { 364 .regs = exynos5433_retention_regs, 365 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 366 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 367 .refcnt = &exynos_shared_retention_refcnt, 368 .init = exynos_retention_init, 369 }; 370 371 /* PMU retention control for audio pins can be tied to audio pin bank */ 372 static const u32 exynos5433_audio_retention_regs[] = { 373 EXYNOS5433_PAD_RETENTION_AUD_OPTION, 374 }; 375 376 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 377 .regs = exynos5433_audio_retention_regs, 378 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 379 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 380 .init = exynos_retention_init, 381 }; 382 383 /* PMU retention control for mmc pins can be tied to fsys pin bank */ 384 static const u32 exynos5433_fsys_retention_regs[] = { 385 EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 386 EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 387 EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 388 }; 389 390 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 391 .regs = exynos5433_fsys_retention_regs, 392 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 393 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 394 .init = exynos_retention_init, 395 }; 396 397 /* 398 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 399 * ten gpio/pin-mux/pinconfig controllers. 400 */ 401 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 402 { 403 /* pin-controller instance 0 data */ 404 .pin_banks = exynos5433_pin_banks0, 405 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 406 .eint_wkup_init = exynos_eint_wkup_init, 407 .suspend = exynos_pinctrl_suspend, 408 .resume = exynos_pinctrl_resume, 409 .nr_ext_resources = 1, 410 .retention_data = &exynos5433_retention_data, 411 }, { 412 /* pin-controller instance 1 data */ 413 .pin_banks = exynos5433_pin_banks1, 414 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 415 .eint_gpio_init = exynos_eint_gpio_init, 416 .suspend = exynos_pinctrl_suspend, 417 .resume = exynos_pinctrl_resume, 418 .retention_data = &exynos5433_audio_retention_data, 419 }, { 420 /* pin-controller instance 2 data */ 421 .pin_banks = exynos5433_pin_banks2, 422 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 423 .eint_gpio_init = exynos_eint_gpio_init, 424 .suspend = exynos_pinctrl_suspend, 425 .resume = exynos_pinctrl_resume, 426 .retention_data = &exynos5433_retention_data, 427 }, { 428 /* pin-controller instance 3 data */ 429 .pin_banks = exynos5433_pin_banks3, 430 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 431 .eint_gpio_init = exynos_eint_gpio_init, 432 .suspend = exynos_pinctrl_suspend, 433 .resume = exynos_pinctrl_resume, 434 .retention_data = &exynos5433_retention_data, 435 }, { 436 /* pin-controller instance 4 data */ 437 .pin_banks = exynos5433_pin_banks4, 438 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 439 .eint_gpio_init = exynos_eint_gpio_init, 440 .suspend = exynos_pinctrl_suspend, 441 .resume = exynos_pinctrl_resume, 442 .retention_data = &exynos5433_retention_data, 443 }, { 444 /* pin-controller instance 5 data */ 445 .pin_banks = exynos5433_pin_banks5, 446 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 447 .eint_gpio_init = exynos_eint_gpio_init, 448 .suspend = exynos_pinctrl_suspend, 449 .resume = exynos_pinctrl_resume, 450 .retention_data = &exynos5433_fsys_retention_data, 451 }, { 452 /* pin-controller instance 6 data */ 453 .pin_banks = exynos5433_pin_banks6, 454 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 455 .eint_gpio_init = exynos_eint_gpio_init, 456 .suspend = exynos_pinctrl_suspend, 457 .resume = exynos_pinctrl_resume, 458 .retention_data = &exynos5433_retention_data, 459 }, { 460 /* pin-controller instance 7 data */ 461 .pin_banks = exynos5433_pin_banks7, 462 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 463 .eint_gpio_init = exynos_eint_gpio_init, 464 .suspend = exynos_pinctrl_suspend, 465 .resume = exynos_pinctrl_resume, 466 .retention_data = &exynos5433_retention_data, 467 }, { 468 /* pin-controller instance 8 data */ 469 .pin_banks = exynos5433_pin_banks8, 470 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 471 .eint_gpio_init = exynos_eint_gpio_init, 472 .suspend = exynos_pinctrl_suspend, 473 .resume = exynos_pinctrl_resume, 474 .retention_data = &exynos5433_retention_data, 475 }, { 476 /* pin-controller instance 9 data */ 477 .pin_banks = exynos5433_pin_banks9, 478 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 479 .eint_gpio_init = exynos_eint_gpio_init, 480 .suspend = exynos_pinctrl_suspend, 481 .resume = exynos_pinctrl_resume, 482 .retention_data = &exynos5433_retention_data, 483 }, 484 }; 485 486 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { 487 .ctrl = exynos5433_pin_ctrl, 488 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), 489 }; 490 491 /* pin banks of exynos7 pin-controller - ALIVE */ 492 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 493 /* Must start with EINTG banks, ordered by EINT group number. */ 494 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 495 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 496 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 497 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 498 }; 499 500 /* pin banks of exynos7 pin-controller - BUS0 */ 501 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 502 /* Must start with EINTG banks, ordered by EINT group number. */ 503 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 504 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 505 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 506 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 507 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 508 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 509 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 510 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 511 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 512 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 513 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 514 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 515 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 516 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 517 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 518 }; 519 520 /* pin banks of exynos7 pin-controller - NFC */ 521 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 522 /* Must start with EINTG banks, ordered by EINT group number. */ 523 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 524 }; 525 526 /* pin banks of exynos7 pin-controller - TOUCH */ 527 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 528 /* Must start with EINTG banks, ordered by EINT group number. */ 529 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 530 }; 531 532 /* pin banks of exynos7 pin-controller - FF */ 533 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 534 /* Must start with EINTG banks, ordered by EINT group number. */ 535 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 536 }; 537 538 /* pin banks of exynos7 pin-controller - ESE */ 539 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 540 /* Must start with EINTG banks, ordered by EINT group number. */ 541 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 542 }; 543 544 /* pin banks of exynos7 pin-controller - FSYS0 */ 545 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 546 /* Must start with EINTG banks, ordered by EINT group number. */ 547 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 548 }; 549 550 /* pin banks of exynos7 pin-controller - FSYS1 */ 551 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 552 /* Must start with EINTG banks, ordered by EINT group number. */ 553 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 554 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 555 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 556 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 557 }; 558 559 /* pin banks of exynos7 pin-controller - BUS1 */ 560 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 561 /* Must start with EINTG banks, ordered by EINT group number. */ 562 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 563 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 564 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 565 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 566 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 567 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 568 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 569 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 570 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 571 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 572 }; 573 574 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 575 /* Must start with EINTG banks, ordered by EINT group number. */ 576 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 577 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 578 }; 579 580 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 581 { 582 /* pin-controller instance 0 Alive data */ 583 .pin_banks = exynos7_pin_banks0, 584 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 585 .eint_wkup_init = exynos_eint_wkup_init, 586 }, { 587 /* pin-controller instance 1 BUS0 data */ 588 .pin_banks = exynos7_pin_banks1, 589 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 590 .eint_gpio_init = exynos_eint_gpio_init, 591 }, { 592 /* pin-controller instance 2 NFC data */ 593 .pin_banks = exynos7_pin_banks2, 594 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 595 .eint_gpio_init = exynos_eint_gpio_init, 596 }, { 597 /* pin-controller instance 3 TOUCH data */ 598 .pin_banks = exynos7_pin_banks3, 599 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 600 .eint_gpio_init = exynos_eint_gpio_init, 601 }, { 602 /* pin-controller instance 4 FF data */ 603 .pin_banks = exynos7_pin_banks4, 604 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 605 .eint_gpio_init = exynos_eint_gpio_init, 606 }, { 607 /* pin-controller instance 5 ESE data */ 608 .pin_banks = exynos7_pin_banks5, 609 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 610 .eint_gpio_init = exynos_eint_gpio_init, 611 }, { 612 /* pin-controller instance 6 FSYS0 data */ 613 .pin_banks = exynos7_pin_banks6, 614 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 615 .eint_gpio_init = exynos_eint_gpio_init, 616 }, { 617 /* pin-controller instance 7 FSYS1 data */ 618 .pin_banks = exynos7_pin_banks7, 619 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 620 .eint_gpio_init = exynos_eint_gpio_init, 621 }, { 622 /* pin-controller instance 8 BUS1 data */ 623 .pin_banks = exynos7_pin_banks8, 624 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 625 .eint_gpio_init = exynos_eint_gpio_init, 626 }, { 627 /* pin-controller instance 9 AUD data */ 628 .pin_banks = exynos7_pin_banks9, 629 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 630 .eint_gpio_init = exynos_eint_gpio_init, 631 }, 632 }; 633 634 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { 635 .ctrl = exynos7_pin_ctrl, 636 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), 637 }; 638 639 /* pin banks of exynos7870 pin-controller 0 (ALIVE) */ 640 static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { 641 EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"), 642 EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"), 643 EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 644 EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 645 EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 646 EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"), 647 }; 648 649 /* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ 650 static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { 651 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00), 652 EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04), 653 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08), 654 }; 655 656 /* pin banks of exynos7870 pin-controller 2 (ESE) */ 657 static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { 658 EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00), 659 }; 660 661 /* pin banks of exynos7870 pin-controller 3 (FSYS) */ 662 static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { 663 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00), 664 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 665 EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08), 666 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c), 667 EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10), 668 }; 669 670 /* pin banks of exynos7870 pin-controller 4 (MIF) */ 671 static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { 672 EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00), 673 }; 674 675 /* pin banks of exynos7870 pin-controller 5 (NFC) */ 676 static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { 677 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00), 678 }; 679 680 /* pin banks of exynos7870 pin-controller 6 (TOP) */ 681 static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { 682 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00), 683 EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04), 684 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08), 685 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c), 686 EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10), 687 EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14), 688 EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18), 689 EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c), 690 EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20), 691 EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24), 692 EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28), 693 EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c), 694 EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34), 695 EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 696 EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c), 697 EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40), 698 EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44), 699 EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48), 700 }; 701 702 /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ 703 static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { 704 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00), 705 }; 706 707 static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { 708 { 709 /* pin-controller instance 0 Alive data */ 710 .pin_banks = exynos7870_pin_banks0, 711 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks0), 712 .eint_wkup_init = exynos_eint_wkup_init, 713 .suspend = exynos_pinctrl_suspend, 714 .resume = exynos_pinctrl_resume, 715 }, { 716 /* pin-controller instance 1 DISPAUD data */ 717 .pin_banks = exynos7870_pin_banks1, 718 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks1), 719 }, { 720 /* pin-controller instance 2 ESE data */ 721 .pin_banks = exynos7870_pin_banks2, 722 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks2), 723 .eint_gpio_init = exynos_eint_gpio_init, 724 .suspend = exynos_pinctrl_suspend, 725 .resume = exynos_pinctrl_resume, 726 }, { 727 /* pin-controller instance 3 FSYS data */ 728 .pin_banks = exynos7870_pin_banks3, 729 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks3), 730 .eint_gpio_init = exynos_eint_gpio_init, 731 .suspend = exynos_pinctrl_suspend, 732 .resume = exynos_pinctrl_resume, 733 }, { 734 /* pin-controller instance 4 MIF data */ 735 .pin_banks = exynos7870_pin_banks4, 736 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks4), 737 .eint_gpio_init = exynos_eint_gpio_init, 738 .suspend = exynos_pinctrl_suspend, 739 .resume = exynos_pinctrl_resume, 740 }, { 741 /* pin-controller instance 5 NFC data */ 742 .pin_banks = exynos7870_pin_banks5, 743 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks5), 744 .eint_gpio_init = exynos_eint_gpio_init, 745 .suspend = exynos_pinctrl_suspend, 746 .resume = exynos_pinctrl_resume, 747 }, { 748 /* pin-controller instance 6 TOP data */ 749 .pin_banks = exynos7870_pin_banks6, 750 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks6), 751 .eint_gpio_init = exynos_eint_gpio_init, 752 .suspend = exynos_pinctrl_suspend, 753 .resume = exynos_pinctrl_resume, 754 }, { 755 /* pin-controller instance 7 TOUCH data */ 756 .pin_banks = exynos7870_pin_banks7, 757 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks7), 758 .eint_gpio_init = exynos_eint_gpio_init, 759 .suspend = exynos_pinctrl_suspend, 760 .resume = exynos_pinctrl_resume, 761 }, 762 }; 763 764 const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { 765 .ctrl = exynos7870_pin_ctrl, 766 .num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl), 767 }; 768 769 /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ 770 static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { 771 EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), 772 EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), 773 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 774 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 775 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 776 EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), 777 }; 778 779 /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ 780 static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { 781 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 782 EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), 783 EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), 784 }; 785 786 /* pin banks of exynos7885 pin-controller 2 (FSYS) */ 787 static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { 788 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 789 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), 790 EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), 791 EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), 792 }; 793 794 /* pin banks of exynos7885 pin-controller 3 (TOP) */ 795 static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { 796 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), 797 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), 798 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 799 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 800 EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), 801 EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), 802 EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), 803 EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), 804 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), 805 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), 806 EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), 807 EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), 808 EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), 809 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), 810 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), 811 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), 812 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), 813 }; 814 815 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { 816 { 817 /* pin-controller instance 0 Alive data */ 818 .pin_banks = exynos7885_pin_banks0, 819 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), 820 .eint_gpio_init = exynos_eint_gpio_init, 821 .eint_wkup_init = exynos_eint_wkup_init, 822 .suspend = exynos_pinctrl_suspend, 823 .resume = exynos_pinctrl_resume, 824 }, { 825 /* pin-controller instance 1 DISPAUD data */ 826 .pin_banks = exynos7885_pin_banks1, 827 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), 828 }, { 829 /* pin-controller instance 2 FSYS data */ 830 .pin_banks = exynos7885_pin_banks2, 831 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), 832 .eint_gpio_init = exynos_eint_gpio_init, 833 .suspend = exynos_pinctrl_suspend, 834 .resume = exynos_pinctrl_resume, 835 }, { 836 /* pin-controller instance 3 TOP data */ 837 .pin_banks = exynos7885_pin_banks3, 838 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), 839 .eint_gpio_init = exynos_eint_gpio_init, 840 .suspend = exynos_pinctrl_suspend, 841 .resume = exynos_pinctrl_resume, 842 }, 843 }; 844 845 const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { 846 .ctrl = exynos7885_pin_ctrl, 847 .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), 848 }; 849 850 /* pin banks of exynos850 pin-controller 0 (ALIVE) */ 851 static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { 852 /* Must start with EINTG banks, ordered by EINT group number. */ 853 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 854 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 855 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 856 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 857 EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), 858 EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), 859 }; 860 861 /* pin banks of exynos850 pin-controller 1 (CMGP) */ 862 static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { 863 /* Must start with EINTG banks, ordered by EINT group number. */ 864 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 865 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 866 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 867 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), 868 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 869 EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), 870 EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), 871 EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), 872 }; 873 874 /* pin banks of exynos850 pin-controller 2 (AUD) */ 875 static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { 876 /* Must start with EINTG banks, ordered by EINT group number. */ 877 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 878 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), 879 }; 880 881 /* pin banks of exynos850 pin-controller 3 (HSI) */ 882 static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { 883 /* Must start with EINTG banks, ordered by EINT group number. */ 884 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), 885 }; 886 887 /* pin banks of exynos850 pin-controller 4 (CORE) */ 888 static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { 889 /* Must start with EINTG banks, ordered by EINT group number. */ 890 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 891 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), 892 }; 893 894 /* pin banks of exynos850 pin-controller 5 (PERI) */ 895 static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { 896 /* Must start with EINTG banks, ordered by EINT group number. */ 897 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), 898 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), 899 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 900 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 901 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), 902 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), 903 EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), 904 EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), 905 EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), 906 }; 907 908 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { 909 { 910 /* pin-controller instance 0 ALIVE data */ 911 .pin_banks = exynos850_pin_banks0, 912 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), 913 .eint_wkup_init = exynos_eint_wkup_init, 914 }, { 915 /* pin-controller instance 1 CMGP data */ 916 .pin_banks = exynos850_pin_banks1, 917 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), 918 .eint_wkup_init = exynos_eint_wkup_init, 919 }, { 920 /* pin-controller instance 2 AUD data */ 921 .pin_banks = exynos850_pin_banks2, 922 .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), 923 }, { 924 /* pin-controller instance 3 HSI data */ 925 .pin_banks = exynos850_pin_banks3, 926 .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), 927 .eint_gpio_init = exynos_eint_gpio_init, 928 }, { 929 /* pin-controller instance 4 CORE data */ 930 .pin_banks = exynos850_pin_banks4, 931 .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), 932 .eint_gpio_init = exynos_eint_gpio_init, 933 }, { 934 /* pin-controller instance 5 PERI data */ 935 .pin_banks = exynos850_pin_banks5, 936 .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), 937 .eint_gpio_init = exynos_eint_gpio_init, 938 }, 939 }; 940 941 const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { 942 .ctrl = exynos850_pin_ctrl, 943 .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), 944 }; 945 946 /* pin banks of exynos8855 pin-controller 0 (ALIVE) */ 947 static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = { 948 GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00), 949 GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08), 950 EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"), 951 EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"), 952 GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10), 953 GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14), 954 GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18), 955 GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c), 956 GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20), 957 GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24), 958 GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28), 959 GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c), 960 GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30), 961 GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34), 962 GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38), 963 GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c), 964 GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40), 965 GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44), 966 GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48), 967 GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c), 968 GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50), 969 GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54), 970 }; 971 972 /* pin banks of exynos8855 pin-controller 1 (CMGP) */ 973 static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = { 974 GS101_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00, 0x00), 975 GS101_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04, 0x04), 976 GS101_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08, 0x08), 977 GS101_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c, 0x0c), 978 GS101_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10, 0x10), 979 GS101_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14, 0x14), 980 GS101_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18, 0x18), 981 GS101_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c, 0x1c), 982 GS101_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20, 0x20), 983 GS101_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24, 0x24), 984 GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28), 985 GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c), 986 GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30), 987 GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34), 988 GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38), 989 GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c), 990 GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40), 991 GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44), 992 GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48), 993 GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c), 994 GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50), 995 GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54), 996 }; 997 998 /* pin banks of exynos8855 pin-controller 2 (HSI UFS) */ 999 static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = { 1000 GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00), 1001 }; 1002 1003 /* pin banks of exynos8855 pin-controller 3 (PERIC) */ 1004 static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = { 1005 GS101_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00, 0x00), 1006 GS101_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04, 0x08), 1007 GS101_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08, 0x10), 1008 GS101_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c, 0x18), 1009 GS101_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10, 0x1c), 1010 GS101_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14, 0x20), 1011 GS101_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18, 0x28), 1012 }; 1013 1014 /* pin banks of exynos8855 pin-controller 4 (PERICMMC) */ 1015 static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = { 1016 GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00), 1017 }; 1018 1019 /* pin banks of exynos8855 pin-controller 5 (USI) */ 1020 static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = { 1021 GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00), 1022 GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08), 1023 GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c), 1024 GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10), 1025 }; 1026 1027 static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = { 1028 { 1029 /* pin-controller instance 0 ALIVE data */ 1030 .pin_banks = exynos8855_pin_banks0, 1031 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0), 1032 .eint_wkup_init = exynos_eint_wkup_init, 1033 .suspend = gs101_pinctrl_suspend, 1034 .resume = gs101_pinctrl_resume, 1035 }, { 1036 /* pin-controller instance 1 CMGP data */ 1037 .pin_banks = exynos8855_pin_banks1, 1038 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1), 1039 .eint_gpio_init = exynos_eint_gpio_init, 1040 .suspend = gs101_pinctrl_suspend, 1041 .resume = gs101_pinctrl_resume, 1042 }, { 1043 /* pin-controller instance 2 HSI UFS data */ 1044 .pin_banks = exynos8855_pin_banks2, 1045 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2), 1046 .eint_gpio_init = exynos_eint_gpio_init, 1047 .suspend = gs101_pinctrl_suspend, 1048 .resume = gs101_pinctrl_resume, 1049 }, { 1050 /* pin-controller instance 3 PERIC data */ 1051 .pin_banks = exynos8855_pin_banks3, 1052 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3), 1053 .eint_gpio_init = exynos_eint_gpio_init, 1054 .suspend = gs101_pinctrl_suspend, 1055 .resume = gs101_pinctrl_resume, 1056 }, { 1057 /* pin-controller instance 4 PERICMMC data */ 1058 .pin_banks = exynos8855_pin_banks4, 1059 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4), 1060 .eint_gpio_init = exynos_eint_gpio_init, 1061 .suspend = gs101_pinctrl_suspend, 1062 .resume = gs101_pinctrl_resume, 1063 }, { 1064 /* pin-controller instance 5 USI data */ 1065 .pin_banks = exynos8855_pin_banks5, 1066 .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5), 1067 .eint_gpio_init = exynos_eint_gpio_init, 1068 .suspend = gs101_pinctrl_suspend, 1069 .resume = gs101_pinctrl_resume, 1070 }, 1071 }; 1072 1073 const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = { 1074 .ctrl = exynos8855_pin_ctrl, 1075 .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl), 1076 }; 1077 1078 /* pin banks of exynos990 pin-controller 0 (ALIVE) */ 1079 static struct samsung_pin_bank_data exynos990_pin_banks0[] = { 1080 /* Must start with EINTG banks, ordered by EINT group number. */ 1081 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1082 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1083 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1084 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1085 EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), 1086 EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), 1087 }; 1088 1089 /* pin banks of exynos990 pin-controller 1 (CMGP) */ 1090 static struct samsung_pin_bank_data exynos990_pin_banks1[] = { 1091 /* Must start with EINTG banks, ordered by EINT group number. */ 1092 EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), 1093 EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), 1094 EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), 1095 EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), 1096 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), 1097 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), 1098 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), 1099 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), 1100 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), 1101 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), 1102 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), 1103 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), 1104 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), 1105 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), 1106 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), 1107 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), 1108 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), 1109 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), 1110 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), 1111 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), 1112 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), 1113 EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), 1114 EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), 1115 EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), 1116 EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), 1117 EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), 1118 EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), 1119 EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), 1120 EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), 1121 EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), 1122 EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), 1123 EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), 1124 EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), 1125 EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), 1126 1127 }; 1128 1129 /* pin banks of exynos990 pin-controller 2 (HSI1) */ 1130 static struct samsung_pin_bank_data exynos990_pin_banks2[] = { 1131 /* Must start with EINTG banks, ordered by EINT group number. */ 1132 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 1133 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 1134 EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), 1135 }; 1136 1137 /* pin banks of exynos990 pin-controller 3 (HSI2) */ 1138 static struct samsung_pin_bank_data exynos990_pin_banks3[] = { 1139 /* Must start with EINTG banks, ordered by EINT group number. */ 1140 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), 1141 }; 1142 1143 /* pin banks of exynos990 pin-controller 4 (PERIC0) */ 1144 static struct samsung_pin_bank_data exynos990_pin_banks4[] = { 1145 /* Must start with EINTG banks, ordered by EINT group number. */ 1146 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1147 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1148 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1149 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), 1150 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), 1151 EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), 1152 }; 1153 1154 /* pin banks of exynos990 pin-controller 5 (PERIC1) */ 1155 static struct samsung_pin_bank_data exynos990_pin_banks5[] = { 1156 /* Must start with EINTG banks, ordered by EINT group number. */ 1157 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), 1158 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), 1159 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), 1160 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), 1161 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), 1162 EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), 1163 EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), 1164 EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), 1165 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), 1166 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), 1167 }; 1168 1169 /* pin banks of exynos990 pin-controller 6 (VTS) */ 1170 static struct samsung_pin_bank_data exynos990_pin_banks6[] = { 1171 /* Must start with EINTG banks, ordered by EINT group number. */ 1172 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), 1173 }; 1174 1175 static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { 1176 { 1177 /* pin-controller instance 0 ALIVE data */ 1178 .pin_banks = exynos990_pin_banks0, 1179 .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), 1180 .eint_wkup_init = exynos_eint_wkup_init, 1181 }, { 1182 /* pin-controller instance 1 CMGP data */ 1183 .pin_banks = exynos990_pin_banks1, 1184 .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), 1185 .eint_wkup_init = exynos_eint_wkup_init, 1186 }, { 1187 /* pin-controller instance 2 HSI1 data */ 1188 .pin_banks = exynos990_pin_banks2, 1189 .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), 1190 .eint_gpio_init = exynos_eint_gpio_init, 1191 }, { 1192 /* pin-controller instance 3 HSI2 data */ 1193 .pin_banks = exynos990_pin_banks3, 1194 .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), 1195 .eint_gpio_init = exynos_eint_gpio_init, 1196 }, { 1197 /* pin-controller instance 4 PERIC0 data */ 1198 .pin_banks = exynos990_pin_banks4, 1199 .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), 1200 .eint_gpio_init = exynos_eint_gpio_init, 1201 }, { 1202 /* pin-controller instance 5 PERIC1 data */ 1203 .pin_banks = exynos990_pin_banks5, 1204 .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), 1205 .eint_gpio_init = exynos_eint_gpio_init, 1206 }, { 1207 /* pin-controller instance 6 VTS data */ 1208 .pin_banks = exynos990_pin_banks6, 1209 .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), 1210 }, 1211 }; 1212 1213 const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { 1214 .ctrl = exynos990_pin_ctrl, 1215 .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), 1216 }; 1217 1218 /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ 1219 static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { 1220 EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), 1221 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1222 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1223 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1224 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1225 EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), 1226 EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), 1227 }; 1228 1229 /* pin banks of exynos9810 pin-controller 1 (AUD) */ 1230 static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { 1231 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1232 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1233 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), 1234 }; 1235 1236 /* pin banks of exynos9810 pin-controller 2 (CHUB) */ 1237 static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { 1238 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1239 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), 1240 }; 1241 1242 /* pin banks of exynos9810 pin-controller 3 (CMGP) */ 1243 static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { 1244 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 1245 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 1246 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 1247 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), 1248 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 1249 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), 1250 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), 1251 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), 1252 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), 1253 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), 1254 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), 1255 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), 1256 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), 1257 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), 1258 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), 1259 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), 1260 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), 1261 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), 1262 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), 1263 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), 1264 }; 1265 1266 /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ 1267 static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { 1268 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), 1269 }; 1270 1271 /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ 1272 static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { 1273 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), 1274 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), 1275 }; 1276 1277 /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ 1278 static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { 1279 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1280 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1281 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1282 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), 1283 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1284 EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1285 EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), 1286 }; 1287 1288 /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ 1289 static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { 1290 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), 1291 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), 1292 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), 1293 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), 1294 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), 1295 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 1296 EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), 1297 }; 1298 1299 /* pin banks of exynos9810 pin-controller 8 (VTS) */ 1300 static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { 1301 EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), 1302 }; 1303 1304 static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { 1305 { 1306 /* pin-controller instance 0 ALIVE data */ 1307 .pin_banks = exynos9810_pin_banks0, 1308 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), 1309 .eint_wkup_init = exynos_eint_wkup_init, 1310 .eint_gpio_init = exynos_eint_gpio_init, 1311 .suspend = exynos_pinctrl_suspend, 1312 .resume = exynos_pinctrl_resume, 1313 }, { 1314 /* pin-controller instance 1 AUD data */ 1315 .pin_banks = exynos9810_pin_banks1, 1316 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), 1317 }, { 1318 /* pin-controller instance 2 CHUB data */ 1319 .pin_banks = exynos9810_pin_banks2, 1320 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), 1321 .eint_gpio_init = exynos_eint_gpio_init, 1322 .suspend = exynos_pinctrl_suspend, 1323 .resume = exynos_pinctrl_resume, 1324 }, { 1325 /* pin-controller instance 3 CMGP data */ 1326 .pin_banks = exynos9810_pin_banks3, 1327 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), 1328 .eint_wkup_init = exynos_eint_wkup_init, 1329 .eint_gpio_init = exynos_eint_gpio_init, 1330 .suspend = exynos_pinctrl_suspend, 1331 .resume = exynos_pinctrl_resume, 1332 }, { 1333 /* pin-controller instance 4 FSYS0 data */ 1334 .pin_banks = exynos9810_pin_banks4, 1335 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), 1336 .eint_gpio_init = exynos_eint_gpio_init, 1337 .suspend = exynos_pinctrl_suspend, 1338 .resume = exynos_pinctrl_resume, 1339 }, { 1340 /* pin-controller instance 5 FSYS1 data */ 1341 .pin_banks = exynos9810_pin_banks5, 1342 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), 1343 .eint_gpio_init = exynos_eint_gpio_init, 1344 .suspend = exynos_pinctrl_suspend, 1345 .resume = exynos_pinctrl_resume, 1346 }, { 1347 /* pin-controller instance 6 PERIC0 data */ 1348 .pin_banks = exynos9810_pin_banks6, 1349 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), 1350 .eint_gpio_init = exynos_eint_gpio_init, 1351 .suspend = exynos_pinctrl_suspend, 1352 .resume = exynos_pinctrl_resume, 1353 }, { 1354 /* pin-controller instance 7 PERIC1 data */ 1355 .pin_banks = exynos9810_pin_banks7, 1356 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), 1357 .eint_gpio_init = exynos_eint_gpio_init, 1358 .suspend = exynos_pinctrl_suspend, 1359 .resume = exynos_pinctrl_resume, 1360 }, { 1361 /* pin-controller instance 8 VTS data */ 1362 .pin_banks = exynos9810_pin_banks8, 1363 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), 1364 }, 1365 }; 1366 1367 const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { 1368 .ctrl = exynos9810_pin_ctrl, 1369 .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), 1370 }; 1371 1372 /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ 1373 static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { 1374 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1375 EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), 1376 EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), 1377 }; 1378 1379 /* pin banks of exynosautov9 pin-controller 1 (AUD) */ 1380 static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { 1381 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1382 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1383 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), 1384 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), 1385 }; 1386 1387 /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ 1388 static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { 1389 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), 1390 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 1391 }; 1392 1393 /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ 1394 static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { 1395 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), 1396 }; 1397 1398 /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ 1399 static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { 1400 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), 1401 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), 1402 EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), 1403 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), 1404 EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), 1405 }; 1406 1407 /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ 1408 static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { 1409 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1410 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1411 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1412 EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), 1413 }; 1414 1415 /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ 1416 static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { 1417 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), 1418 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), 1419 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), 1420 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), 1421 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), 1422 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), 1423 }; 1424 1425 static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { 1426 { 1427 /* pin-controller instance 0 ALIVE data */ 1428 .pin_banks = exynosautov9_pin_banks0, 1429 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), 1430 .eint_wkup_init = exynos_eint_wkup_init, 1431 .suspend = exynos_pinctrl_suspend, 1432 .resume = exynos_pinctrl_resume, 1433 }, { 1434 /* pin-controller instance 1 AUD data */ 1435 .pin_banks = exynosautov9_pin_banks1, 1436 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1), 1437 }, { 1438 /* pin-controller instance 2 FSYS0 data */ 1439 .pin_banks = exynosautov9_pin_banks2, 1440 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), 1441 .eint_gpio_init = exynos_eint_gpio_init, 1442 .suspend = exynos_pinctrl_suspend, 1443 .resume = exynos_pinctrl_resume, 1444 }, { 1445 /* pin-controller instance 3 FSYS1 data */ 1446 .pin_banks = exynosautov9_pin_banks3, 1447 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), 1448 .eint_gpio_init = exynos_eint_gpio_init, 1449 .suspend = exynos_pinctrl_suspend, 1450 .resume = exynos_pinctrl_resume, 1451 }, { 1452 /* pin-controller instance 4 FSYS2 data */ 1453 .pin_banks = exynosautov9_pin_banks4, 1454 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), 1455 .eint_gpio_init = exynos_eint_gpio_init, 1456 .suspend = exynos_pinctrl_suspend, 1457 .resume = exynos_pinctrl_resume, 1458 }, { 1459 /* pin-controller instance 5 PERIC0 data */ 1460 .pin_banks = exynosautov9_pin_banks5, 1461 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), 1462 .eint_gpio_init = exynos_eint_gpio_init, 1463 .suspend = exynos_pinctrl_suspend, 1464 .resume = exynos_pinctrl_resume, 1465 }, { 1466 /* pin-controller instance 6 PERIC1 data */ 1467 .pin_banks = exynosautov9_pin_banks6, 1468 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), 1469 .eint_gpio_init = exynos_eint_gpio_init, 1470 .suspend = exynos_pinctrl_suspend, 1471 .resume = exynos_pinctrl_resume, 1472 }, 1473 }; 1474 1475 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 1476 .ctrl = exynosautov9_pin_ctrl, 1477 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), 1478 }; 1479 1480 /* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ 1481 static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { 1482 EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), 1483 EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), 1484 EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), 1485 }; 1486 1487 /* pin banks of exynosautov920 pin-controller 1 (AUD) */ 1488 static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { 1489 EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), 1490 EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), 1491 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), 1492 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), 1493 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), 1494 EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), 1495 EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), 1496 }; 1497 1498 /* pin banks of exynosautov920 pin-controller 2 (HSI0) */ 1499 static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { 1500 EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), 1501 EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), 1502 }; 1503 1504 /* pin banks of exynosautov920 pin-controller 3 (HSI1) */ 1505 static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { 1506 EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), 1507 }; 1508 1509 /* pin banks of exynosautov920 pin-controller 4 (HSI2) */ 1510 static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { 1511 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), 1512 EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), 1513 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), 1514 EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), 1515 }; 1516 1517 /* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ 1518 static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { 1519 EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), 1520 }; 1521 1522 /* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ 1523 static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { 1524 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), 1525 EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), 1526 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), 1527 EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), 1528 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), 1529 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), 1530 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), 1531 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), 1532 EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), 1533 EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), 1534 }; 1535 1536 /* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ 1537 static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { 1538 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), 1539 EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), 1540 EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), 1541 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), 1542 EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), 1543 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), 1544 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), 1545 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), 1546 EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), 1547 }; 1548 1549 static const struct samsung_retention_data no_retention_data __initconst = { 1550 .regs = NULL, 1551 .nr_regs = 0, 1552 .value = 0, 1553 .refcnt = &exynos_shared_retention_refcnt, 1554 .init = exynos_retention_init, 1555 }; 1556 1557 static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { 1558 { 1559 /* pin-controller instance 0 ALIVE data */ 1560 .pin_banks = exynosautov920_pin_banks0, 1561 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), 1562 .eint_wkup_init = exynos_eint_wkup_init, 1563 .suspend = exynosautov920_pinctrl_suspend, 1564 .resume = exynosautov920_pinctrl_resume, 1565 .retention_data = &no_retention_data, 1566 }, { 1567 /* pin-controller instance 1 AUD data */ 1568 .pin_banks = exynosautov920_pin_banks1, 1569 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), 1570 }, { 1571 /* pin-controller instance 2 HSI0 data */ 1572 .pin_banks = exynosautov920_pin_banks2, 1573 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), 1574 .eint_gpio_init = exynos_eint_gpio_init, 1575 .suspend = exynosautov920_pinctrl_suspend, 1576 .resume = exynosautov920_pinctrl_resume, 1577 }, { 1578 /* pin-controller instance 3 HSI1 data */ 1579 .pin_banks = exynosautov920_pin_banks3, 1580 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), 1581 .eint_gpio_init = exynos_eint_gpio_init, 1582 .suspend = exynosautov920_pinctrl_suspend, 1583 .resume = exynosautov920_pinctrl_resume, 1584 }, { 1585 /* pin-controller instance 4 HSI2 data */ 1586 .pin_banks = exynosautov920_pin_banks4, 1587 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), 1588 .eint_gpio_init = exynos_eint_gpio_init, 1589 .suspend = exynosautov920_pinctrl_suspend, 1590 .resume = exynosautov920_pinctrl_resume, 1591 }, { 1592 /* pin-controller instance 5 HSI2UFS data */ 1593 .pin_banks = exynosautov920_pin_banks5, 1594 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), 1595 .eint_gpio_init = exynos_eint_gpio_init, 1596 .suspend = exynosautov920_pinctrl_suspend, 1597 .resume = exynosautov920_pinctrl_resume, 1598 }, { 1599 /* pin-controller instance 6 PERIC0 data */ 1600 .pin_banks = exynosautov920_pin_banks6, 1601 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), 1602 .eint_gpio_init = exynos_eint_gpio_init, 1603 .suspend = exynosautov920_pinctrl_suspend, 1604 .resume = exynosautov920_pinctrl_resume, 1605 }, { 1606 /* pin-controller instance 7 PERIC1 data */ 1607 .pin_banks = exynosautov920_pin_banks7, 1608 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), 1609 .eint_gpio_init = exynos_eint_gpio_init, 1610 .suspend = exynosautov920_pinctrl_suspend, 1611 .resume = exynosautov920_pinctrl_resume, 1612 }, 1613 }; 1614 1615 const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { 1616 .ctrl = exynosautov920_pin_ctrl, 1617 .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), 1618 }; 1619 1620 /* pin banks of exynos8890 pin-controller 0 (ALIVE) */ 1621 static const struct samsung_pin_bank_data exynos8890_pin_banks0[] __initconst = { 1622 /* Must start with EINTG banks, ordered by EINT group number. */ 1623 EXYNOS7870_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1624 EXYNOS7870_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1625 EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1626 EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1627 }; 1628 1629 /* pin banks of exynos8890 pin-controller 1 (AUD) */ 1630 static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = { 1631 /* Must start with EINTG banks, ordered by EINT group number. */ 1632 EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gph0", 0x00), 1633 }; 1634 1635 /* pin banks of exynos8890 pin-controller 2 (CCORE) */ 1636 static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = { 1637 /* Must start with EINTG banks, ordered by EINT group number. */ 1638 EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "etc0", 0x00), 1639 }; 1640 1641 /* pin banks of exynos8890 pin-controller 3 (ESE) */ 1642 static const struct samsung_pin_bank_data exynos8890_pin_banks3[] __initconst = { 1643 /* Must start with EINTG banks, ordered by EINT group number. */ 1644 EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpf3", 0x00), 1645 }; 1646 1647 /* pin banks of exynos8890 pin-controller 4 (FP) */ 1648 static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = { 1649 /* Must start with EINTG banks, ordered by EINT group number. */ 1650 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), 1651 }; 1652 1653 /* pin banks of exynos8890 pin-controller 5 (FSYS0) */ 1654 static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = { 1655 /* Must start with EINTG banks, ordered by EINT group number. */ 1656 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpi1", 0x00), 1657 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi2", 0x04), 1658 }; 1659 1660 /* pin banks of exynos8890 pin-controller 6 (FSYS1) */ 1661 static const struct samsung_pin_bank_data exynos8890_pin_banks6[] __initconst = { 1662 /* Must start with EINTG banks, ordered by EINT group number. */ 1663 EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gpj0", 0x00), 1664 }; 1665 1666 /* pin banks of exynos8890 pin-controller 7 (NFC) */ 1667 static const struct samsung_pin_bank_data exynos8890_pin_banks7[] __initconst = { 1668 /* Must start with EINTG banks, ordered by EINT group number. */ 1669 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf0", 0x00), 1670 }; 1671 1672 /* pin banks of exynos8890 pin-controller 8 (PERIC0) */ 1673 static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = { 1674 /* Must start with EINTG banks, ordered by EINT group number. */ 1675 EXYNOS8895_PIN_BANK_EINTG(6, 0x000, "gpi0", 0x00), 1676 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpd0", 0x04), 1677 EXYNOS8895_PIN_BANK_EINTG(6, 0x040, "gpd1", 0x08), 1678 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpd2", 0x0c), 1679 EXYNOS8895_PIN_BANK_EINTG(4, 0x080, "gpd3", 0x10), 1680 EXYNOS8895_PIN_BANK_EINTG(2, 0x0A0, "gpb1", 0x14), 1681 EXYNOS8895_PIN_BANK_EINTG(2, 0x0C0, "gpb2", 0x18), 1682 EXYNOS8895_PIN_BANK_EINTG(3, 0x0E0, "gpb0", 0x1c), 1683 EXYNOS8895_PIN_BANK_EINTG(5, 0x100, "gpc0", 0x20), 1684 EXYNOS8895_PIN_BANK_EINTG(5, 0x120, "gpc1", 0x24), 1685 EXYNOS8895_PIN_BANK_EINTG(6, 0x140, "gpc2", 0x28), 1686 EXYNOS8895_PIN_BANK_EINTG(8, 0x160, "gpc3", 0x2c), 1687 EXYNOS8895_PIN_BANK_EINTG(4, 0x180, "gpk0", 0x30), 1688 EXYNOS8895_PIN_BANK_EINTG(7, 0x1A0, "etc1", 0x34), 1689 }; 1690 1691 /* pin banks of exynos8890 pin-controller 9 (PERIC1) */ 1692 static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = { 1693 /* Must start with EINTG banks, ordered by EINT group number. */ 1694 EXYNOS8895_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1695 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpe5", 0x04), 1696 EXYNOS8895_PIN_BANK_EINTG(8, 0x040, "gpe6", 0x08), 1697 EXYNOS8895_PIN_BANK_EINTG(8, 0x060, "gpj1", 0x0c), 1698 EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpj2", 0x10), 1699 EXYNOS8895_PIN_BANK_EINTG(8, 0x0A0, "gpe2", 0x14), 1700 EXYNOS8895_PIN_BANK_EINTG(8, 0x0C0, "gpe3", 0x18), 1701 EXYNOS8895_PIN_BANK_EINTG(8, 0x0E0, "gpe4", 0x1c), 1702 EXYNOS8895_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 1703 EXYNOS8895_PIN_BANK_EINTG(4, 0x120, "gpe7", 0x24), 1704 EXYNOS8895_PIN_BANK_EINTG(3, 0x140, "gpg0", 0x28), 1705 }; 1706 1707 /* pin banks of exynos8890 pin-controller 10 (TOUCH) */ 1708 static const struct samsung_pin_bank_data exynos8890_pin_banks10[] __initconst = { 1709 /* Must start with EINTG banks, ordered by EINT group number. */ 1710 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf1", 0x00), 1711 }; 1712 1713 static const struct samsung_pin_ctrl exynos8890_pin_ctrl[] __initconst = { 1714 { 1715 /* pin-controller instance 0 Alive data */ 1716 .pin_banks = exynos8890_pin_banks0, 1717 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks0), 1718 .eint_wkup_init = exynos_eint_wkup_init, 1719 }, { 1720 /* pin-controller instance 1 AUD data */ 1721 .pin_banks = exynos8890_pin_banks1, 1722 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks1), 1723 .eint_gpio_init = exynos_eint_gpio_init, 1724 }, { 1725 /* pin-controller instance 2 CCORE data */ 1726 .pin_banks = exynos8890_pin_banks2, 1727 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks2), 1728 .eint_gpio_init = exynos_eint_gpio_init, 1729 }, { 1730 /* pin-controller instance 3 ESE data */ 1731 .pin_banks = exynos8890_pin_banks3, 1732 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks3), 1733 .eint_gpio_init = exynos_eint_gpio_init, 1734 }, { 1735 /* pin-controller instance 4 FP data */ 1736 .pin_banks = exynos8890_pin_banks4, 1737 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks4), 1738 .eint_gpio_init = exynos_eint_gpio_init, 1739 }, { 1740 /* pin-controller instance 5 FSYS0 data */ 1741 .pin_banks = exynos8890_pin_banks5, 1742 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks5), 1743 .eint_gpio_init = exynos_eint_gpio_init, 1744 }, { 1745 /* pin-controller instance 6 FSYS1 data */ 1746 .pin_banks = exynos8890_pin_banks6, 1747 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks6), 1748 .eint_gpio_init = exynos_eint_gpio_init, 1749 }, { 1750 /* pin-controller instance 7 NFC data */ 1751 .pin_banks = exynos8890_pin_banks7, 1752 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks7), 1753 .eint_gpio_init = exynos_eint_gpio_init, 1754 }, { 1755 /* pin-controller instance 8 PERIC0 data */ 1756 .pin_banks = exynos8890_pin_banks8, 1757 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks8), 1758 .eint_gpio_init = exynos_eint_gpio_init, 1759 }, { 1760 /* pin-controller instance 9 PERIC1 data */ 1761 .pin_banks = exynos8890_pin_banks9, 1762 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks9), 1763 .eint_gpio_init = exynos_eint_gpio_init, 1764 }, { 1765 /* pin-controller instance 10 TOUCH data */ 1766 .pin_banks = exynos8890_pin_banks10, 1767 .nr_banks = ARRAY_SIZE(exynos8890_pin_banks10), 1768 .eint_gpio_init = exynos_eint_gpio_init, 1769 }, 1770 }; 1771 1772 const struct samsung_pinctrl_of_match_data exynos8890_of_data __initconst = { 1773 .ctrl = exynos8890_pin_ctrl, 1774 .num_ctrl = ARRAY_SIZE(exynos8890_pin_ctrl), 1775 }; 1776 1777 /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ 1778 static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { 1779 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1780 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1781 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1782 EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1783 EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), 1784 }; 1785 1786 /* pin banks of exynos8895 pin-controller 1 (ABOX) */ 1787 static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { 1788 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1789 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), 1790 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), 1791 }; 1792 1793 /* pin banks of exynos8895 pin-controller 2 (VTS) */ 1794 static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { 1795 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), 1796 }; 1797 1798 /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ 1799 static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { 1800 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), 1801 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), 1802 }; 1803 1804 /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ 1805 static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { 1806 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), 1807 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), 1808 }; 1809 1810 /* pin banks of exynos8895 pin-controller 5 (BUSC) */ 1811 static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { 1812 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), 1813 }; 1814 1815 /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ 1816 static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { 1817 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), 1818 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), 1819 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), 1820 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), 1821 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1822 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), 1823 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), 1824 }; 1825 1826 /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ 1827 static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { 1828 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), 1829 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), 1830 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), 1831 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), 1832 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1833 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), 1834 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), 1835 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), 1836 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), 1837 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), 1838 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), 1839 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), 1840 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), 1841 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1842 }; 1843 1844 static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { 1845 { 1846 /* pin-controller instance 0 ALIVE data */ 1847 .pin_banks = exynos8895_pin_banks0, 1848 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), 1849 .eint_gpio_init = exynos_eint_gpio_init, 1850 .eint_wkup_init = exynos_eint_wkup_init, 1851 .suspend = exynos_pinctrl_suspend, 1852 .resume = exynos_pinctrl_resume, 1853 }, { 1854 /* pin-controller instance 1 ABOX data */ 1855 .pin_banks = exynos8895_pin_banks1, 1856 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), 1857 }, { 1858 /* pin-controller instance 2 VTS data */ 1859 .pin_banks = exynos8895_pin_banks2, 1860 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), 1861 .eint_gpio_init = exynos_eint_gpio_init, 1862 }, { 1863 /* pin-controller instance 3 FSYS0 data */ 1864 .pin_banks = exynos8895_pin_banks3, 1865 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), 1866 .eint_gpio_init = exynos_eint_gpio_init, 1867 .suspend = exynos_pinctrl_suspend, 1868 .resume = exynos_pinctrl_resume, 1869 }, { 1870 /* pin-controller instance 4 FSYS1 data */ 1871 .pin_banks = exynos8895_pin_banks4, 1872 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), 1873 .eint_gpio_init = exynos_eint_gpio_init, 1874 .suspend = exynos_pinctrl_suspend, 1875 .resume = exynos_pinctrl_resume, 1876 }, { 1877 /* pin-controller instance 5 BUSC data */ 1878 .pin_banks = exynos8895_pin_banks5, 1879 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), 1880 .eint_gpio_init = exynos_eint_gpio_init, 1881 .suspend = exynos_pinctrl_suspend, 1882 .resume = exynos_pinctrl_resume, 1883 }, { 1884 /* pin-controller instance 6 PERIC0 data */ 1885 .pin_banks = exynos8895_pin_banks6, 1886 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), 1887 .eint_gpio_init = exynos_eint_gpio_init, 1888 .suspend = exynos_pinctrl_suspend, 1889 .resume = exynos_pinctrl_resume, 1890 }, { 1891 /* pin-controller instance 7 PERIC1 data */ 1892 .pin_banks = exynos8895_pin_banks7, 1893 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), 1894 .eint_gpio_init = exynos_eint_gpio_init, 1895 .suspend = exynos_pinctrl_suspend, 1896 .resume = exynos_pinctrl_resume, 1897 }, 1898 }; 1899 1900 const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { 1901 .ctrl = exynos8895_pin_ctrl, 1902 .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), 1903 }; 1904 1905 /* pin banks of exynos9610 pin-controller 0 (ALIVE) */ 1906 static const struct samsung_pin_bank_data exynos9610_pin_banks0[] __initconst = { 1907 EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"), 1908 GS101_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00, 0x00), 1909 GS101_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04, 0x08), 1910 GS101_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08, 0x0c), 1911 EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"), 1912 }; 1913 1914 /* pin banks of exynos9610 pin-controller 1 (CMGP) */ 1915 static const struct samsung_pin_bank_data exynos9610_pin_banks1[] __initconst = { 1916 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 1917 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 1918 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 1919 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), 1920 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 1921 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), 1922 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), 1923 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), 1924 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20), 1925 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24), 1926 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28), 1927 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C), 1928 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30), 1929 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34), 1930 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38), 1931 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C), 1932 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), 1933 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), 1934 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48), 1935 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C), 1936 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50), 1937 EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54), 1938 EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58), 1939 EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C), 1940 EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60), 1941 EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64), 1942 }; 1943 1944 /* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ 1945 static const struct samsung_pin_bank_data exynos9610_pin_banks2[] __initconst = { 1946 GS101_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00, 0x00), 1947 GS101_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04, 0x08), 1948 GS101_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08, 0x0c), 1949 }; 1950 1951 /* pin banks of exynos9610 pin-controller 3 (FSYS) */ 1952 static const struct samsung_pin_bank_data exynos9610_pin_banks3[] __initconst = { 1953 GS101_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00, 0x00), 1954 GS101_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04, 0x04), 1955 GS101_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08, 0x0c), 1956 }; 1957 1958 /* pin banks of exynos9610 pin-controller 4 (TOP) */ 1959 static const struct samsung_pin_bank_data exynos9610_pin_banks4[] __initconst = { 1960 GS101_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00, 0x00), 1961 GS101_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04, 0x08), 1962 GS101_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08, 0x10), 1963 GS101_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C, 0x18), 1964 GS101_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10, 0x20), 1965 GS101_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14, 0x28), 1966 GS101_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18, 0x30), 1967 GS101_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C, 0x38), 1968 GS101_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20, 0x40), 1969 GS101_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24, 0x48), 1970 GS101_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28, 0x50), 1971 }; 1972 1973 /* pin banks of exynos9610 pin-controller 5 (SHUB) */ 1974 static const struct samsung_pin_bank_data exynos9610_pin_banks5[] __initconst = { 1975 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00), 1976 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04), 1977 }; 1978 1979 static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst = { 1980 { 1981 /* pin-controller instance 0 ALIVE data */ 1982 .pin_banks = exynos9610_pin_banks0, 1983 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks0), 1984 .eint_wkup_init = exynos_eint_wkup_init, 1985 .suspend = exynos_pinctrl_suspend, 1986 .resume = exynos_pinctrl_resume, 1987 }, { 1988 /* pin-controller instance 1 CMGP data */ 1989 .pin_banks = exynos9610_pin_banks1, 1990 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks1), 1991 .eint_wkup_init = exynos_eint_wkup_init, 1992 .suspend = exynos_pinctrl_suspend, 1993 .resume = exynos_pinctrl_resume, 1994 }, { 1995 /* pin-controller instance 2 DISPAUD data */ 1996 .pin_banks = exynos9610_pin_banks2, 1997 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks2), 1998 }, { 1999 /* pin-controller instance 3 FSYS data */ 2000 .pin_banks = exynos9610_pin_banks3, 2001 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks3), 2002 .suspend = exynos_pinctrl_suspend, 2003 .resume = exynos_pinctrl_resume, 2004 }, { 2005 /* pin-controller instance 4 TOP data */ 2006 .pin_banks = exynos9610_pin_banks4, 2007 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks4), 2008 .suspend = exynos_pinctrl_suspend, 2009 .resume = exynos_pinctrl_resume, 2010 }, { 2011 /* pin-controller instance 5 SHUB data */ 2012 .pin_banks = exynos9610_pin_banks5, 2013 .nr_banks = ARRAY_SIZE(exynos9610_pin_banks5), 2014 }, 2015 }; 2016 2017 const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = { 2018 .ctrl = exynos9610_pin_ctrl, 2019 .num_ctrl = ARRAY_SIZE(exynos9610_pin_ctrl), 2020 }; 2021 2022 /* 2023 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three 2024 * gpio/pin-mux/pinconfig controllers. 2025 */ 2026 2027 /* pin banks of FSD pin-controller 0 (FSYS) */ 2028 static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { 2029 EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), 2030 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), 2031 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), 2032 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), 2033 EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), 2034 }; 2035 2036 /* pin banks of FSD pin-controller 1 (PERIC) */ 2037 static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { 2038 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), 2039 EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), 2040 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), 2041 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), 2042 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), 2043 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), 2044 EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), 2045 EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), 2046 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), 2047 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), 2048 EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), 2049 EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 2050 EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), 2051 EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), 2052 EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), 2053 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), 2054 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 2055 EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), 2056 EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), 2057 EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), 2058 EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), 2059 }; 2060 2061 /* pin banks of FSD pin-controller 2 (PMU) */ 2062 static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { 2063 EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), 2064 }; 2065 2066 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { 2067 { 2068 /* pin-controller instance 0 FSYS0 data */ 2069 .pin_banks = fsd_pin_banks0, 2070 .nr_banks = ARRAY_SIZE(fsd_pin_banks0), 2071 .eint_gpio_init = exynos_eint_gpio_init, 2072 .suspend = exynos_pinctrl_suspend, 2073 .resume = exynos_pinctrl_resume, 2074 }, { 2075 /* pin-controller instance 1 PERIC data */ 2076 .pin_banks = fsd_pin_banks1, 2077 .nr_banks = ARRAY_SIZE(fsd_pin_banks1), 2078 .eint_gpio_init = exynos_eint_gpio_init, 2079 .suspend = exynos_pinctrl_suspend, 2080 .resume = exynos_pinctrl_resume, 2081 }, { 2082 /* pin-controller instance 2 PMU data */ 2083 .pin_banks = fsd_pin_banks2, 2084 .nr_banks = ARRAY_SIZE(fsd_pin_banks2), 2085 }, 2086 }; 2087 2088 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 2089 .ctrl = fsd_pin_ctrl, 2090 .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), 2091 }; 2092 2093 /* pin banks of gs101 pin-controller (ALIVE) */ 2094 static const struct samsung_pin_bank_data gs101_pin_alive[] = { 2095 GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), 2096 GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), 2097 GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), 2098 GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), 2099 GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), 2100 GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), 2101 GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), 2102 GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), 2103 }; 2104 2105 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 2106 static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { 2107 GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), 2108 GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), 2109 GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), 2110 GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), 2111 }; 2112 2113 /* pin banks of gs101 pin-controller (GSACORE) */ 2114 static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { 2115 GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), 2116 GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), 2117 GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), 2118 }; 2119 2120 /* pin banks of gs101 pin-controller (GSACTRL) */ 2121 static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { 2122 GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), 2123 }; 2124 2125 /* pin banks of gs101 pin-controller (PERIC0) */ 2126 static const struct samsung_pin_bank_data gs101_pin_peric0[] = { 2127 GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), 2128 GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), 2129 GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), 2130 GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), 2131 GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), 2132 GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), 2133 GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), 2134 GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), 2135 GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), 2136 GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), 2137 GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), 2138 GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), 2139 GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), 2140 GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), 2141 GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), 2142 GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), 2143 GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), 2144 GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), 2145 GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), 2146 GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), 2147 }; 2148 2149 /* pin banks of gs101 pin-controller (PERIC1) */ 2150 static const struct samsung_pin_bank_data gs101_pin_peric1[] = { 2151 GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), 2152 GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), 2153 GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), 2154 GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), 2155 GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), 2156 GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), 2157 GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), 2158 GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), 2159 }; 2160 2161 /* pin banks of gs101 pin-controller (HSI1) */ 2162 static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { 2163 GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), 2164 GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), 2165 }; 2166 2167 /* pin banks of gs101 pin-controller (HSI2) */ 2168 static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { 2169 GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), 2170 GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), 2171 GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), 2172 }; 2173 2174 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { 2175 { 2176 /* pin banks of gs101 pin-controller (ALIVE) */ 2177 .pin_banks = gs101_pin_alive, 2178 .nr_banks = ARRAY_SIZE(gs101_pin_alive), 2179 .eint_wkup_init = exynos_eint_wkup_init, 2180 .suspend = gs101_pinctrl_suspend, 2181 .resume = gs101_pinctrl_resume, 2182 .retention_data = &no_retention_data, 2183 }, { 2184 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 2185 .pin_banks = gs101_pin_far_alive, 2186 .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), 2187 .eint_wkup_init = exynos_eint_wkup_init, 2188 .suspend = gs101_pinctrl_suspend, 2189 .resume = gs101_pinctrl_resume, 2190 .retention_data = &no_retention_data, 2191 }, { 2192 /* pin banks of gs101 pin-controller (GSACORE) */ 2193 .pin_banks = gs101_pin_gsacore, 2194 .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), 2195 }, { 2196 /* pin banks of gs101 pin-controller (GSACTRL) */ 2197 .pin_banks = gs101_pin_gsactrl, 2198 .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), 2199 }, { 2200 /* pin banks of gs101 pin-controller (PERIC0) */ 2201 .pin_banks = gs101_pin_peric0, 2202 .nr_banks = ARRAY_SIZE(gs101_pin_peric0), 2203 .eint_gpio_init = exynos_eint_gpio_init, 2204 .suspend = gs101_pinctrl_suspend, 2205 .resume = gs101_pinctrl_resume, 2206 }, { 2207 /* pin banks of gs101 pin-controller (PERIC1) */ 2208 .pin_banks = gs101_pin_peric1, 2209 .nr_banks = ARRAY_SIZE(gs101_pin_peric1), 2210 .eint_gpio_init = exynos_eint_gpio_init, 2211 .suspend = gs101_pinctrl_suspend, 2212 .resume = gs101_pinctrl_resume, 2213 }, { 2214 /* pin banks of gs101 pin-controller (HSI1) */ 2215 .pin_banks = gs101_pin_hsi1, 2216 .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), 2217 .eint_gpio_init = exynos_eint_gpio_init, 2218 .suspend = gs101_pinctrl_suspend, 2219 .resume = gs101_pinctrl_resume, 2220 }, { 2221 /* pin banks of gs101 pin-controller (HSI2) */ 2222 .pin_banks = gs101_pin_hsi2, 2223 .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), 2224 .eint_gpio_init = exynos_eint_gpio_init, 2225 .suspend = gs101_pinctrl_suspend, 2226 .resume = gs101_pinctrl_resume, 2227 }, 2228 }; 2229 2230 const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { 2231 .ctrl = gs101_pin_ctrl, 2232 .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), 2233 }; 2234 2235 /* pin banks of artpec8 pin-controller (FSYS0) */ 2236 static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = { 2237 ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00), 2238 ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04), 2239 ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08), 2240 ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c), 2241 ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10), 2242 ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14), 2243 ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18), 2244 ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c), 2245 ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20), 2246 ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24), 2247 }; 2248 2249 /* pin banks of artpec8 pin-controller (PERIC) */ 2250 static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = { 2251 ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 2252 ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), 2253 ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 2254 ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c), 2255 }; 2256 2257 static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = { 2258 { 2259 /* pin-controller instance 0 FSYS data */ 2260 .pin_banks = artpec8_pin_banks0, 2261 .nr_banks = ARRAY_SIZE(artpec8_pin_banks0), 2262 .eint_gpio_init = exynos_eint_gpio_init, 2263 }, { 2264 /* pin-controller instance 1 PERIC data */ 2265 .pin_banks = artpec8_pin_banks1, 2266 .nr_banks = ARRAY_SIZE(artpec8_pin_banks1), 2267 .eint_gpio_init = exynos_eint_gpio_init, 2268 }, 2269 }; 2270 2271 const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = { 2272 .ctrl = artpec8_pin_ctrl, 2273 .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl), 2274 }; 2275 2276 /* pin banks of artpec9 pin-controller (FSYS0) */ 2277 static const struct samsung_pin_bank_data artpec9_pin_banks0[] __initconst = { 2278 ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 2279 ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), 2280 ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpe0", 0x08), 2281 ARTPEC_PIN_BANK_EINTG(8, 0x060, "gpe1", 0x0c), 2282 ARTPEC_PIN_BANK_EINTG(8, 0x080, "gpe2", 0x10), 2283 ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe3", 0x14), 2284 ARTPEC_PIN_BANK_EINTG(2, 0x0c0, "gpe4", 0x18), 2285 ARTPEC_PIN_BANK_EINTG(8, 0x0e0, "gps0", 0x1c), 2286 ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps1", 0x20), 2287 ARTPEC_PIN_BANK_EINTG(5, 0x120, "gpi0", 0x24), 2288 }; 2289 2290 /* pin banks of artpec9 pin-controller (FSYS1) */ 2291 static const struct samsung_pin_bank_data artpec9_pin_banks1[] __initconst = { 2292 ARTPEC_PIN_BANK_EINTG(2, 0x000, "gpu0", 0x00), 2293 }; 2294 2295 /* pin banks of artpec9 pin-controller (PERIC) */ 2296 static const struct samsung_pin_bank_data artpec9_pin_banks2[] __initconst = { 2297 ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 2298 ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), 2299 }; 2300 2301 static const struct samsung_pin_ctrl artpec9_pin_ctrl[] __initconst = { 2302 { 2303 /* pin-controller instance 0 FSYS0 data */ 2304 .pin_banks = artpec9_pin_banks0, 2305 .nr_banks = ARRAY_SIZE(artpec9_pin_banks0), 2306 .eint_gpio_init = exynos_eint_gpio_init, 2307 }, { 2308 /* pin-controller instance 1 FSYS1 data */ 2309 .pin_banks = artpec9_pin_banks1, 2310 .nr_banks = ARRAY_SIZE(artpec9_pin_banks1), 2311 .eint_gpio_init = exynos_eint_gpio_init, 2312 }, { 2313 /* pin-controller instance 2 PERIC data */ 2314 .pin_banks = artpec9_pin_banks2, 2315 .nr_banks = ARRAY_SIZE(artpec9_pin_banks2), 2316 .eint_gpio_init = exynos_eint_gpio_init, 2317 }, 2318 }; 2319 2320 const struct samsung_pinctrl_of_match_data artpec9_of_data __initconst = { 2321 .ctrl = artpec9_pin_ctrl, 2322 .num_ctrl = ARRAY_SIZE(artpec9_pin_ctrl), 2323 }; 2324