1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 */ 5 6#include "amlogic-a4-common.dtsi" 7#include "amlogic-a5-reset.h" 8#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 9#include <dt-bindings/power/amlogic,a5-pwrc.h> 10/ { 11 cpus { 12 #address-cells = <2>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-a55"; 18 reg = <0x0 0x0>; 19 enable-method = "psci"; 20 }; 21 22 cpu1: cpu@100 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a55"; 25 reg = <0x0 0x100>; 26 enable-method = "psci"; 27 }; 28 29 cpu2: cpu@200 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a55"; 32 reg = <0x0 0x200>; 33 enable-method = "psci"; 34 }; 35 36 cpu3: cpu@300 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x0 0x300>; 40 enable-method = "psci"; 41 }; 42 }; 43 44 sm: secure-monitor { 45 compatible = "amlogic,meson-gxbb-sm"; 46 47 pwrc: power-controller { 48 compatible = "amlogic,a5-pwrc"; 49 #power-domain-cells = <1>; 50 }; 51 }; 52}; 53 54&apb { 55 reset: reset-controller@2000 { 56 compatible = "amlogic,a5-reset", 57 "amlogic,meson-s4-reset"; 58 reg = <0x0 0x2000 0x0 0x98>; 59 #reset-cells = <1>; 60 }; 61 62 periphs_pinctrl: pinctrl@4000 { 63 compatible = "amlogic,pinctrl-a5", 64 "amlogic,pinctrl-a4"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges = <0x0 0x0 0x0 0x4000 0x0 0x300>; 68 69 gpioz: gpio@c0 { 70 reg = <0x0 0xc0 0x0 0x40>, 71 <0x0 0x18 0x0 0x8>; 72 reg-names = "gpio", "mux"; 73 gpio-controller; 74 #gpio-cells = <2>; 75 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; 76 }; 77 78 gpiox: gpio@100 { 79 reg = <0x0 0x100 0x0 0x40>, 80 <0x0 0xc 0x0 0xc>; 81 reg-names = "gpio", "mux"; 82 gpio-controller; 83 #gpio-cells = <2>; 84 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; 85 }; 86 87 gpiot: gpio@140 { 88 reg = <0x0 0x140 0x0 0x40>, 89 <0x0 0x2c 0x0 0x8>; 90 reg-names = "gpio", "mux"; 91 gpio-controller; 92 #gpio-cells = <2>; 93 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 14>; 94 }; 95 96 gpiod: gpio@180 { 97 reg = <0x0 0x180 0x0 0x40>, 98 <0x0 0x40 0x0 0x8>; 99 reg-names = "gpio", "mux"; 100 gpio-controller; 101 #gpio-cells = <2>; 102 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>; 103 }; 104 105 gpioe: gpio@1c0 { 106 reg = <0x0 0x1c0 0x0 0x40>, 107 <0x0 0x48 0x0 0x4>; 108 reg-names = "gpio", "mux"; 109 gpio-controller; 110 #gpio-cells = <2>; 111 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; 112 }; 113 114 gpioc: gpio@200 { 115 reg = <0x0 0x200 0x0 0x40>, 116 <0x0 0x24 0x0 0x8>; 117 reg-names = "gpio", "mux"; 118 gpio-controller; 119 #gpio-cells = <2>; 120 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 11>; 121 }; 122 123 gpiob: gpio@240 { 124 reg = <0x0 0x240 0x0 0x40>, 125 <0x0 0x0 0x0 0x8>; 126 reg-names = "gpio", "mux"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 130 }; 131 132 gpioh: gpio@280 { 133 reg = <0x0 0x280 0x0 0x40>, 134 <0x0 0x4c 0x0 0x4>; 135 reg-names = "gpio", "mux"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 5>; 139 }; 140 141 gpio_test_n: gpio@2c0 { 142 reg = <0x0 0x2c0 0x0 0x40>, 143 <0x0 0x3c 0x0 0x4>; 144 reg-names = "gpio", "mux"; 145 gpio-controller; 146 #gpio-cells = <2>; 147 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 148 }; 149 }; 150 151 gpio_intc: interrupt-controller@4080 { 152 compatible = "amlogic,a5-gpio-intc", 153 "amlogic,meson-gpio-intc"; 154 reg = <0x0 0x4080 0x0 0x20>; 155 interrupt-controller; 156 #interrupt-cells = <2>; 157 amlogic,channel-interrupts = 158 <10 11 12 13 14 15 16 17 18 19 20 21>; 159 }; 160}; 161