1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 10#include <dt-bindings/power/amlogic,s7d-pwrc.h> 11 12/ { 13 cpus { 14 #address-cells = <2>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 device_type = "cpu"; 19 compatible = "arm,cortex-a55"; 20 reg = <0x0 0x0>; 21 enable-method = "psci"; 22 }; 23 24 cpu1: cpu@100 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a55"; 27 reg = <0x0 0x100>; 28 enable-method = "psci"; 29 }; 30 31 cpu2: cpu@200 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a55"; 34 reg = <0x0 0x200>; 35 enable-method = "psci"; 36 }; 37 38 cpu3: cpu@300 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x0 0x300>; 42 enable-method = "psci"; 43 }; 44 45 }; 46 47 sm: secure-monitor { 48 compatible = "amlogic,meson-gxbb-sm"; 49 50 pwrc: power-controller { 51 compatible = "amlogic,s7d-pwrc"; 52 #power-domain-cells = <1>; 53 }; 54 }; 55 56 timer { 57 compatible = "arm,armv8-timer"; 58 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 59 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 62 }; 63 64 psci { 65 compatible = "arm,psci-1.0"; 66 method = "smc"; 67 }; 68 69 xtal: xtal-clk { 70 compatible = "fixed-clock"; 71 clock-frequency = <24000000>; 72 clock-output-names = "xtal"; 73 #clock-cells = <0>; 74 }; 75 76 soc { 77 compatible = "simple-bus"; 78 #address-cells = <2>; 79 #size-cells = <2>; 80 ranges; 81 82 gic: interrupt-controller@fff01000 { 83 compatible = "arm,gic-400"; 84 #interrupt-cells = <3>; 85 #address-cells = <0>; 86 interrupt-controller; 87 reg = <0x0 0xfff01000 0 0x1000>, 88 <0x0 0xfff02000 0 0x0100>; 89 interrupts = <GIC_PPI 9 0xf04>; 90 }; 91 92 apb: bus@fe000000 { 93 compatible = "simple-bus"; 94 reg = <0x0 0xfe000000 0x0 0x480000>; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 98 99 uart_b: serial@7a000 { 100 compatible = "amlogic,s7d-uart", 101 "amlogic,meson-s4-uart"; 102 reg = <0x0 0x7a000 0x0 0x18>; 103 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 104 clocks = <&xtal>, <&xtal>, <&xtal>; 105 clock-names = "xtal", "pclk", "baud"; 106 status = "disabled"; 107 }; 108 109 periphs_pinctrl: pinctrl@4000 { 110 compatible = "amlogic,pinctrl-s7d", 111 "amlogic,pinctrl-s7"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; 115 116 gpioz: gpio@c0 { 117 reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; 118 reg-names = "gpio", "mux"; 119 gpio-controller; 120 #gpio-cells = <2>; 121 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; 122 }; 123 124 gpiox: gpio@100 { 125 reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; 126 reg-names = "gpio", "mux"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; 130 }; 131 132 gpioh: gpio@140 { 133 reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; 134 reg-names = "gpio", "mux"; 135 gpio-controller; 136 #gpio-cells = <2>; 137 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; 138 }; 139 140 gpiod: gpio@180 { 141 reg = <0 0x180 0 0x20>, <0 0x40 0 0x4>; 142 reg-names = "gpio", "mux"; 143 gpio-controller; 144 #gpio-cells = <2>; 145 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 5>; 146 }; 147 148 gpioe: gpio@1c0 { 149 reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; 150 reg-names = "gpio", "mux"; 151 gpio-controller; 152 #gpio-cells = <2>; 153 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; 154 }; 155 156 gpioc: gpio@200 { 157 reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; 158 reg-names = "gpio", "mux"; 159 gpio-controller; 160 #gpio-cells = <2>; 161 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; 162 }; 163 164 gpiob: gpio@240 { 165 reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; 166 reg-names = "gpio", "mux"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 170 }; 171 172 gpiodv: gpio@280 { 173 reg = <0 0x280 0 0x20>, <0 0x8 0 0x4>; 174 reg-names = "gpio", "mux"; 175 gpio-controller; 176 #gpio-cells = <2>; 177 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_DV<<8) 7>; 178 }; 179 180 test_n: gpio@2c0 { 181 reg = <0 0x2c0 0 0x20>; 182 reg-names = "gpio"; 183 gpio-controller; 184 #gpio-cells = <2>; 185 gpio-ranges = 186 <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 187 }; 188 189 gpiocc: gpio@300 { 190 reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; 191 reg-names = "gpio", "mux"; 192 gpio-controller; 193 #gpio-cells = <2>; 194 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; 195 }; 196 }; 197 198 gpio_intc: interrupt-controller@4080 { 199 compatible = "amlogic,s7d-gpio-intc", 200 "amlogic,meson-gpio-intc"; 201 reg = <0x0 0x4080 0x0 0x20>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 amlogic,channel-interrupts = 205 <10 11 12 13 14 15 16 17 18 19 20 21>; 206 }; 207 208 ao-secure@10220 { 209 compatible = "amlogic,s7d-ao-secure", 210 "amlogic,meson-gx-ao-secure", 211 "syscon"; 212 reg = <0x0 0x10220 0x0 0x140>; 213 amlogic,has-chip-id; 214 }; 215 }; 216 }; 217}; 218