1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/leds.h> 17 #include <linux/phy.h> 18 #include <linux/property.h> 19 #include <linux/ptp_clock_kernel.h> 20 #include <linux/timecounter.h> 21 #include <net/dsa.h> 22 23 #define EDSA_HLEN 8 24 #define MV88E6XXX_N_FID 4096 25 #define MV88E6XXX_N_SID 64 26 27 #define MV88E6XXX_FID_STANDALONE 0 28 #define MV88E6XXX_FID_BRIDGED 1 29 30 /* PVT limits for 4-bit port and 5-bit switch */ 31 #define MV88E6XXX_MAX_PVT_SWITCHES 32 32 #define MV88E6XXX_MAX_PVT_PORTS 16 33 #define MV88E6XXX_MAX_PVT_ENTRIES \ 34 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 35 36 #define MV88E6XXX_MAX_GPIO 16 37 38 enum mv88e6xxx_egress_mode { 39 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 40 MV88E6XXX_EGRESS_MODE_UNTAGGED, 41 MV88E6XXX_EGRESS_MODE_TAGGED, 42 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 43 }; 44 45 enum mv88e6xxx_egress_direction { 46 MV88E6XXX_EGRESS_DIR_INGRESS, 47 MV88E6XXX_EGRESS_DIR_EGRESS, 48 }; 49 50 enum mv88e6xxx_frame_mode { 51 MV88E6XXX_FRAME_MODE_NORMAL, 52 MV88E6XXX_FRAME_MODE_DSA, 53 MV88E6XXX_FRAME_MODE_PROVIDER, 54 MV88E6XXX_FRAME_MODE_ETHERTYPE, 55 }; 56 57 /* List of supported models */ 58 enum mv88e6xxx_model { 59 MV88E6020, 60 MV88E6071, 61 MV88E6085, 62 MV88E6095, 63 MV88E6097, 64 MV88E6123, 65 MV88E6131, 66 MV88E6141, 67 MV88E6161, 68 MV88E6165, 69 MV88E6171, 70 MV88E6172, 71 MV88E6175, 72 MV88E6176, 73 MV88E6185, 74 MV88E6190, 75 MV88E6190X, 76 MV88E6191, 77 MV88E6191X, 78 MV88E6193X, 79 MV88E6220, 80 MV88E6240, 81 MV88E6250, 82 MV88E6290, 83 MV88E6320, 84 MV88E6321, 85 MV88E6341, 86 MV88E6350, 87 MV88E6351, 88 MV88E6352, 89 MV88E6361, 90 MV88E6390, 91 MV88E6390X, 92 MV88E6393X, 93 }; 94 95 enum mv88e6xxx_family { 96 MV88E6XXX_FAMILY_NONE, 97 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 98 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 99 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 100 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 101 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 102 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 103 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 104 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 105 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 106 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 107 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 108 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 109 }; 110 111 /** 112 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 113 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 114 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 115 * egressing FORWARD frames with an EDSA 116 * tag is reserved for future use, but 117 * empirical data shows that this mode 118 * is supported. 119 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 120 */ 121 enum mv88e6xxx_edsa_support { 122 MV88E6XXX_EDSA_UNSUPPORTED = 0, 123 MV88E6XXX_EDSA_UNDOCUMENTED, 124 MV88E6XXX_EDSA_SUPPORTED, 125 }; 126 127 struct mv88e6xxx_ops; 128 129 struct mv88e6xxx_info { 130 enum mv88e6xxx_family family; 131 u16 prod_num; 132 const char *name; 133 unsigned int num_databases; 134 unsigned int num_macs; 135 unsigned int num_ports; 136 unsigned int num_internal_phys; 137 unsigned int num_gpio; 138 unsigned int num_tcam_entries; 139 unsigned int max_vid; 140 unsigned int max_sid; 141 unsigned int port_base_addr; 142 unsigned int phy_base_addr; 143 unsigned int global1_addr; 144 unsigned int global2_addr; 145 unsigned int tcam_addr; 146 unsigned int age_time_coeff; 147 unsigned int g1_irqs; 148 unsigned int g2_irqs; 149 int stats_type; 150 bool pvt; 151 152 /* Mark certain ports as invalid. This is required for example for the 153 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 154 * ports 2-4 are not routet to pins. 155 */ 156 unsigned int invalid_port_mask; 157 /* Multi-chip Addressing Mode. 158 * Some chips respond to only 2 registers of its own SMI device address 159 * when it is non-zero, and use indirect access to internal registers. 160 */ 161 bool multi_chip; 162 /* Dual-chip Addressing Mode 163 * Some chips respond to only half of the 32 SMI addresses, 164 * allowing two to coexist on the same SMI interface. 165 */ 166 bool dual_chip; 167 168 enum mv88e6xxx_edsa_support edsa_support; 169 170 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 171 * operation. 0 means that the ATU Move operation is not supported. 172 */ 173 u8 atu_move_port_mask; 174 const struct mv88e6xxx_ops *ops; 175 176 /* Supports PTP */ 177 bool ptp_support; 178 179 /* Internal PHY start index. 0 means that internal PHYs range starts at 180 * port 0, 1 means internal PHYs range starts at port 1, etc 181 */ 182 unsigned int internal_phys_offset; 183 }; 184 185 struct mv88e6xxx_atu_entry { 186 u8 state; 187 bool trunk; 188 u16 portvec; 189 u8 mac[ETH_ALEN]; 190 }; 191 192 struct mv88e6xxx_vtu_entry { 193 u16 vid; 194 u16 fid; 195 u8 sid; 196 bool valid; 197 bool policy; 198 u8 member[DSA_MAX_PORTS]; 199 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 200 }; 201 202 struct mv88e6xxx_stu_entry { 203 u8 sid; 204 bool valid; 205 u8 state[DSA_MAX_PORTS]; 206 }; 207 208 struct mv88e6xxx_bus_ops; 209 struct mv88e6xxx_irq_ops; 210 struct mv88e6xxx_gpio_ops; 211 struct mv88e6xxx_avb_ops; 212 struct mv88e6xxx_ptp_ops; 213 struct mv88e6xxx_pcs_ops; 214 struct mv88e6xxx_cc_coeffs; 215 struct mv88e6xxx_tcam_ops; 216 217 struct mv88e6xxx_irq { 218 u16 masked; 219 struct irq_chip chip; 220 struct irq_domain *domain; 221 int nirqs; 222 }; 223 224 /* state flags for mv88e6xxx_port_hwtstamp::state */ 225 enum { 226 MV88E6XXX_HWTSTAMP_ENABLED, 227 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 228 }; 229 230 struct mv88e6xxx_port_hwtstamp { 231 /* Port index */ 232 int port_id; 233 234 /* Timestamping state */ 235 unsigned long state; 236 237 /* Resources for receive timestamping */ 238 struct sk_buff_head rx_queue; 239 struct sk_buff_head rx_queue2; 240 241 /* Resources for transmit timestamping */ 242 unsigned long tx_tstamp_start; 243 struct sk_buff *tx_skb; 244 u16 tx_seq_id; 245 246 /* Current timestamp configuration */ 247 struct kernel_hwtstamp_config tstamp_config; 248 }; 249 250 enum mv88e6xxx_policy_mapping { 251 MV88E6XXX_POLICY_MAPPING_DA, 252 MV88E6XXX_POLICY_MAPPING_SA, 253 MV88E6XXX_POLICY_MAPPING_VTU, 254 MV88E6XXX_POLICY_MAPPING_ETYPE, 255 MV88E6XXX_POLICY_MAPPING_PPPOE, 256 MV88E6XXX_POLICY_MAPPING_VBAS, 257 MV88E6XXX_POLICY_MAPPING_OPT82, 258 MV88E6XXX_POLICY_MAPPING_UDP, 259 }; 260 261 enum mv88e6xxx_policy_action { 262 MV88E6XXX_POLICY_ACTION_NORMAL, 263 MV88E6XXX_POLICY_ACTION_MIRROR, 264 MV88E6XXX_POLICY_ACTION_TRAP, 265 MV88E6XXX_POLICY_ACTION_DISCARD, 266 }; 267 268 struct mv88e6xxx_policy { 269 enum mv88e6xxx_policy_mapping mapping; 270 enum mv88e6xxx_policy_action action; 271 struct ethtool_rx_flow_spec fs; 272 u8 addr[ETH_ALEN]; 273 int port; 274 u16 vid; 275 }; 276 277 struct mv88e6xxx_vlan { 278 u16 vid; 279 bool valid; 280 }; 281 282 struct mv88e6xxx_port { 283 struct mv88e6xxx_chip *chip; 284 int port; 285 struct fwnode_handle *fwnode; 286 struct mv88e6xxx_vlan bridge_pvid; 287 u64 serdes_stats[2]; 288 u64 atu_member_violation; 289 u64 atu_miss_violation; 290 u64 atu_full_violation; 291 u64 vtu_member_violation; 292 u64 vtu_miss_violation; 293 phy_interface_t interface; 294 u8 cmode; 295 bool mirror_ingress; 296 bool mirror_egress; 297 struct devlink_region *region; 298 void *pcs_private; 299 300 /* LED related information */ 301 bool fiber; 302 struct led_classdev led0; 303 struct led_classdev led1; 304 305 /* MacAuth Bypass control flag */ 306 bool mab; 307 }; 308 309 enum mv88e6xxx_region_id { 310 MV88E6XXX_REGION_GLOBAL1 = 0, 311 MV88E6XXX_REGION_GLOBAL2, 312 MV88E6XXX_REGION_ATU, 313 MV88E6XXX_REGION_VTU, 314 MV88E6XXX_REGION_STU, 315 MV88E6XXX_REGION_PVT, 316 317 _MV88E6XXX_REGION_MAX, 318 }; 319 320 struct mv88e6xxx_region_priv { 321 enum mv88e6xxx_region_id id; 322 }; 323 324 struct mv88e6xxx_mst { 325 struct list_head node; 326 327 refcount_t refcnt; 328 struct net_device *br; 329 u16 msti; 330 331 struct mv88e6xxx_stu_entry stu; 332 }; 333 334 #define STATS_TYPE_PORT BIT(0) 335 #define STATS_TYPE_BANK0 BIT(1) 336 #define STATS_TYPE_BANK1 BIT(2) 337 338 struct mv88e6xxx_hw_stat { 339 char string[ETH_GSTRING_LEN]; 340 size_t size; 341 int reg; 342 int type; 343 }; 344 345 struct mv88e6xxx_tcam { 346 struct list_head entries; 347 }; 348 349 struct mv88e6xxx_chip { 350 const struct mv88e6xxx_info *info; 351 352 /* Currently configured tagging protocol */ 353 enum dsa_tag_protocol tag_protocol; 354 355 /* The dsa_switch this private structure is related to */ 356 struct dsa_switch *ds; 357 358 /* The device this structure is associated to */ 359 struct device *dev; 360 361 /* This mutex protects the access to the switch registers */ 362 struct mutex reg_lock; 363 364 /* The MII bus and the address on the bus that is used to 365 * communication with the switch 366 */ 367 const struct mv88e6xxx_bus_ops *smi_ops; 368 struct mii_bus *bus; 369 int sw_addr; 370 371 /* Handles automatic disabling and re-enabling of the PHY 372 * polling unit. 373 */ 374 const struct mv88e6xxx_bus_ops *phy_ops; 375 struct mutex ppu_mutex; 376 int ppu_disabled; 377 struct work_struct ppu_work; 378 struct timer_list ppu_timer; 379 380 /* This mutex serialises access to the statistics unit. 381 * Hold this mutex over snapshot + dump sequences. 382 */ 383 struct mutex stats_mutex; 384 385 /* A switch may have a GPIO line tied to its reset pin. Parse 386 * this from the device tree, and use it before performing 387 * switch soft reset. 388 */ 389 struct gpio_desc *reset; 390 391 /* set to size of eeprom if supported by the switch */ 392 u32 eeprom_len; 393 394 /* List of mdio busses */ 395 struct list_head mdios; 396 397 /* Policy Control List IDs and rules */ 398 struct idr policies; 399 400 /* There can be two interrupt controllers, which are chained 401 * off a GPIO as interrupt source 402 */ 403 struct mv88e6xxx_irq g1_irq; 404 struct mv88e6xxx_irq g2_irq; 405 int irq; 406 char irq_name[64]; 407 int device_irq; 408 char device_irq_name[64]; 409 int watchdog_irq; 410 char watchdog_irq_name[64]; 411 412 int atu_prob_irq; 413 char atu_prob_irq_name[64]; 414 int vtu_prob_irq; 415 char vtu_prob_irq_name[64]; 416 struct kthread_worker *kworker; 417 struct kthread_delayed_work irq_poll_work; 418 419 /* GPIO resources */ 420 u8 gpio_data[2]; 421 422 /* This cyclecounter abstracts the switch PTP time. 423 * reg_lock must be held for any operation that read()s. 424 */ 425 struct cyclecounter tstamp_cc; 426 struct timecounter tstamp_tc; 427 struct delayed_work overflow_work; 428 const struct mv88e6xxx_cc_coeffs *cc_coeffs; 429 430 struct ptp_clock *ptp_clock; 431 struct ptp_clock_info ptp_clock_info; 432 struct delayed_work tai_event_work; 433 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 434 u16 enable_count; 435 436 /* Current ingress and egress monitor ports */ 437 int egress_dest_port; 438 int ingress_dest_port; 439 440 /* Per-port timestamping resources. */ 441 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 442 443 /* Array of port structures. */ 444 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 445 446 /* devlink regions */ 447 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 448 449 /* Bridge MST to SID mappings */ 450 struct list_head msts; 451 452 /* FID map */ 453 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 454 455 /* TCAM entries */ 456 struct mv88e6xxx_tcam tcam; 457 }; 458 459 #define TCAM_MATCH_SIZE 96 460 461 struct mv88e6xxx_tcam_key { 462 u16 spv; 463 u16 spv_mask; 464 465 u8 frame_data[TCAM_MATCH_SIZE]; 466 u8 frame_mask[TCAM_MATCH_SIZE]; 467 }; 468 469 struct mv88e6xxx_tcam_action { 470 u8 dpv_mode; 471 u16 dpv; 472 }; 473 474 struct mv88e6xxx_tcam_entry { 475 struct list_head list; 476 unsigned long cookie; 477 u32 prio; 478 u8 hw_idx; 479 480 struct mv88e6xxx_tcam_key key; 481 struct mv88e6xxx_tcam_action action; 482 483 }; 484 485 struct mv88e6xxx_bus_ops { 486 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 487 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 488 int (*init)(struct mv88e6xxx_chip *chip); 489 }; 490 491 struct mv88e6xxx_mdio_bus { 492 struct mii_bus *bus; 493 struct mv88e6xxx_chip *chip; 494 struct list_head list; 495 bool external; 496 }; 497 498 struct mv88e6xxx_ops { 499 /* Switch Setup Errata, called early in the switch setup to 500 * allow any errata actions to be performed 501 */ 502 int (*setup_errata)(struct mv88e6xxx_chip *chip); 503 504 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 505 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 506 507 /* Ingress Rate Limit unit (IRL) operations */ 508 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 509 510 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 511 struct ethtool_eeprom *eeprom, u8 *data); 512 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 513 struct ethtool_eeprom *eeprom, u8 *data); 514 515 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 516 517 int (*phy_read)(struct mv88e6xxx_chip *chip, 518 struct mii_bus *bus, 519 int addr, int reg, u16 *val); 520 int (*phy_write)(struct mv88e6xxx_chip *chip, 521 struct mii_bus *bus, 522 int addr, int reg, u16 val); 523 524 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 525 struct mii_bus *bus, 526 int addr, int devad, int reg, u16 *val); 527 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 528 struct mii_bus *bus, 529 int addr, int devad, int reg, u16 val); 530 531 /* Priority Override Table operations */ 532 int (*pot_clear)(struct mv88e6xxx_chip *chip); 533 534 /* PHY Polling Unit (PPU) operations */ 535 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 536 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 537 538 /* Additional handlers to run before and after hard reset, to make sure 539 * that the switch and EEPROM are in a good state. 540 */ 541 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip); 542 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip); 543 544 /* Switch Software Reset */ 545 int (*reset)(struct mv88e6xxx_chip *chip); 546 547 /* RGMII Receive/Transmit Timing Control 548 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 549 */ 550 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 551 phy_interface_t mode); 552 553 #define LINK_FORCED_DOWN 0 554 #define LINK_FORCED_UP 1 555 #define LINK_UNFORCED -2 556 557 /* Port's MAC link state 558 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 559 * or LINK_UNFORCED for normal link detection. 560 */ 561 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 562 563 /* Synchronise the port link state with that of the SERDES 564 */ 565 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 566 567 #define PAUSE_ON 1 568 #define PAUSE_OFF 0 569 570 /* Enable/disable sending Pause */ 571 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 572 int pause); 573 574 #define SPEED_UNFORCED -2 575 #define DUPLEX_UNFORCED -2 576 577 /* Port's MAC speed (in Mbps) and MAC duplex mode 578 * 579 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 580 * Use SPEED_UNFORCED for normal detection. 581 * 582 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 583 * or DUPLEX_UNFORCED for normal duplex detection. 584 */ 585 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 586 int speed, int duplex); 587 588 /* What interface mode should be used for maximum speed? */ 589 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 590 int port); 591 592 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 593 594 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 595 enum mv88e6xxx_policy_mapping mapping, 596 enum mv88e6xxx_policy_action action); 597 598 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 599 enum mv88e6xxx_frame_mode mode); 600 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 601 bool unicast); 602 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 603 bool multicast); 604 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 605 u16 etype); 606 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 607 size_t size); 608 609 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 610 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 611 u8 out); 612 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 613 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 614 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 615 616 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 617 * Some chips allow this to be configured on specific ports. 618 */ 619 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 620 phy_interface_t mode); 621 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 622 623 /* LED control */ 624 int (*port_setup_leds)(struct mv88e6xxx_chip *chip, int port); 625 626 /* Some devices have a per port register indicating what is 627 * the upstream port this port should forward to. 628 */ 629 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 630 int upstream_port); 631 632 /* Snapshot the statistics for a port. The statistics can then 633 * be read back a leisure but still with a consistent view. 634 */ 635 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 636 637 /* Set the histogram mode for statistics, when the control registers 638 * are separated out of the STATS_OP register. 639 */ 640 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 641 642 /* Return the number of strings describing statistics */ 643 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 644 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t **data); 645 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port, 646 const struct mv88e6xxx_hw_stat *stat, 647 uint64_t *data); 648 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 649 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 650 enum mv88e6xxx_egress_direction direction, 651 int port); 652 653 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 654 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 655 656 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 657 658 const struct mv88e6xxx_irq_ops *watchdog_ops; 659 660 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 661 662 /* SERDES lane mapping */ 663 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 664 665 /* SERDES interrupt handling */ 666 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 667 int port); 668 669 /* Statistics from the SERDES interface */ 670 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 671 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 672 uint8_t **data); 673 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 674 uint64_t *data); 675 676 /* SERDES registers for ethtool */ 677 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 678 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 679 void *_p); 680 681 /* Address Translation Unit operations */ 682 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 683 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 684 685 /* VLAN Translation Unit operations */ 686 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 687 struct mv88e6xxx_vtu_entry *entry); 688 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 689 struct mv88e6xxx_vtu_entry *entry); 690 691 /* Spanning Tree Unit operations */ 692 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 693 struct mv88e6xxx_stu_entry *entry); 694 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 695 struct mv88e6xxx_stu_entry *entry); 696 697 /* GPIO operations */ 698 const struct mv88e6xxx_gpio_ops *gpio_ops; 699 700 /* Interface to the AVB/PTP registers */ 701 const struct mv88e6xxx_avb_ops *avb_ops; 702 703 /* Remote Management Unit operations */ 704 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 705 706 /* Precision Time Protocol operations */ 707 const struct mv88e6xxx_ptp_ops *ptp_ops; 708 709 /* Phylink */ 710 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 711 struct phylink_config *config); 712 713 const struct mv88e6xxx_pcs_ops *pcs_ops; 714 715 /* Max Frame Size */ 716 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 717 718 int (*port_enable_tcam)(struct mv88e6xxx_chip *chip, int port); 719 720 /* Ternary Content Addressable Memory operations */ 721 const struct mv88e6xxx_tcam_ops *tcam_ops; 722 }; 723 724 struct mv88e6xxx_irq_ops { 725 /* Action to be performed when the interrupt happens */ 726 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 727 /* Setup the hardware to generate the interrupt */ 728 int (*irq_setup)(struct mv88e6xxx_chip *chip); 729 /* Reset the hardware to stop generating the interrupt */ 730 void (*irq_free)(struct mv88e6xxx_chip *chip); 731 }; 732 733 struct mv88e6xxx_gpio_ops { 734 /* Get/set data on GPIO pin */ 735 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 736 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 737 int value); 738 739 /* get/set GPIO direction */ 740 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 741 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 742 bool input); 743 744 /* get/set GPIO pin control */ 745 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 746 int *func); 747 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 748 int func); 749 }; 750 751 struct mv88e6xxx_avb_ops { 752 /* Access port-scoped Precision Time Protocol registers */ 753 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 754 u16 *data, int len); 755 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 756 u16 data); 757 758 /* Access global Precision Time Protocol registers */ 759 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 760 int len); 761 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 762 763 /* Access global Time Application Interface registers */ 764 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 765 int len); 766 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 767 }; 768 769 struct mv88e6xxx_ptp_ops { 770 u64 (*clock_read)(struct cyclecounter *cc); 771 int (*ptp_enable)(struct ptp_clock_info *ptp, 772 struct ptp_clock_request *rq, int on); 773 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 774 enum ptp_pin_function func, unsigned int chan); 775 void (*event_work)(struct work_struct *ugly); 776 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 777 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 778 int (*global_enable)(struct mv88e6xxx_chip *chip); 779 int (*global_disable)(struct mv88e6xxx_chip *chip); 780 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 781 int n_ext_ts; 782 int arr0_sts_reg; 783 int arr1_sts_reg; 784 int dep_sts_reg; 785 u32 rx_filters; 786 }; 787 788 struct mv88e6xxx_pcs_ops { 789 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port); 790 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port); 791 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port, 792 phy_interface_t mode); 793 794 }; 795 796 struct mv88e6xxx_tcam_ops { 797 int (*entry_add)(struct mv88e6xxx_chip *chip, 798 struct mv88e6xxx_tcam_entry *entry, u8 idx); 799 int (*flush_tcam)(struct mv88e6xxx_chip *chip); 800 }; 801 802 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 803 { 804 return chip->info->max_sid > 0 && 805 chip->info->ops->stu_loadpurge && 806 chip->info->ops->stu_getnext; 807 } 808 809 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 810 { 811 return chip->info->pvt; 812 } 813 814 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 815 { 816 return !!chip->info->global2_addr; 817 } 818 819 static inline bool mv88e6xxx_has_tcam(struct mv88e6xxx_chip *chip) 820 { 821 return !!chip->info->tcam_addr; 822 } 823 824 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 825 { 826 return chip->info->num_databases; 827 } 828 829 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 830 { 831 return chip->info->num_macs; 832 } 833 834 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 835 { 836 return chip->info->num_ports; 837 } 838 839 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 840 { 841 return chip->info->max_vid; 842 } 843 844 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 845 { 846 return chip->info->max_sid; 847 } 848 849 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 850 { 851 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 852 } 853 854 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 855 { 856 return chip->info->num_gpio; 857 } 858 859 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 860 { 861 return (chip->info->invalid_port_mask & BIT(port)) != 0; 862 } 863 864 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 865 int port, bool mab) 866 { 867 chip->ports[port].mab = mab; 868 } 869 870 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 871 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 872 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 873 u16 mask, u16 val); 874 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 875 int bit, int val); 876 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 877 878 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 879 { 880 mutex_lock(&chip->reg_lock); 881 } 882 883 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 884 { 885 mutex_unlock(&chip->reg_lock); 886 } 887 888 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 889 int (*cb)(struct mv88e6xxx_chip *chip, 890 const struct mv88e6xxx_vtu_entry *entry, 891 void *priv), 892 void *priv); 893 894 #endif /* _MV88E6XXX_CHIP_H */ 895