1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 3#include <dt-bindings/clock/nvidia,tegra264.h> 4#include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/nvidia,tegra264.h> 8#include <dt-bindings/power/nvidia,tegra264-bpmp.h> 9#include <dt-bindings/reset/nvidia,tegra264.h> 10 11#include "thermal/nvidia,tegra264-bpmp.h" 12 13/ { 14 compatible = "nvidia,tegra264"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &{/bpmp/i2c}; 26 i2c6 = &i2c6; 27 i2c7 = &i2c7; 28 i2c8 = &i2c8; 29 i2c9 = &i2c9; 30 i2c10 = &i2c10; 31 i2c11 = &i2c11; 32 i2c12 = &i2c12; 33 i2c14 = &i2c14; 34 i2c15 = &i2c15; 35 i2c16 = &i2c16; 36 }; 37 38 reserved-memory { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 shmem_bpmp: shmem@86070000 { 44 compatible = "nvidia,tegra264-bpmp-shmem"; 45 reg = <0x0 0x86070000 0x0 0x2000>; 46 no-map; 47 }; 48 }; 49 50 /* SYSTEM MMIO */ 51 bus@0 { 52 compatible = "simple-bus"; 53 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 ranges = <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ 58 59 misc@100000 { 60 compatible = "nvidia,tegra234-misc"; 61 reg = <0x0 0x00100000 0x0 0x0f000>, 62 <0x0 0x0c140000 0x0 0x10000>; 63 }; 64 65 fuse@1000000 { 66 compatible = "nvidia,tegra264-efuse"; 67 reg = <0x0 0x1000000 0x0 0x20000>; 68 clocks = <&bpmp TEGRA264_CLK_FUSE>; 69 clock-names = "fuse"; 70 }; 71 72 timer@8000000 { 73 compatible = "nvidia,tegra234-timer"; 74 reg = <0x0 0x08000000 0x0 0x140000>; 75 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 79 status = "disabled"; 80 }; 81 82 hte_lic: hardware-timestamp@8380000 { 83 compatible = "nvidia,tegra264-gte-lic"; 84 reg = <0x0 0x08380000 0x0 0x10000>; 85 interrupts = <GIC_SPI 0x00000268 IRQ_TYPE_LEVEL_HIGH>; 86 nvidia,int-threshold = <1>; 87 #timestamp-cells = <1>; 88 status = "disabled"; 89 }; 90 91 gpcdma: dma-controller@8400000 { 92 compatible = "nvidia,tegra264-gpcdma"; 93 reg = <0x0 0x08400000 0x0 0x210000>; 94 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 126 #dma-cells = <1>; 127 iommus = <&smmu1 0x00000800>; 128 iommu-map = <1 &smmu1 0x801 31>; 129 dma-coherent; 130 dma-channel-mask = <0xfffffffe>; 131 status = "disabled"; 132 }; 133 134 hsp_top: hsp@8800000 { 135 compatible = "nvidia,tegra264-hsp"; 136 reg = <0x0 0x08800000 0x0 0xd0000>; 137 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 147 "shared3", "shared4", "shared5", "shared6", 148 "shared7"; 149 #mbox-cells = <2>; 150 }; 151 152 aconnect@9000000 { 153 compatible = "nvidia,tegra264-aconnect", 154 "nvidia,tegra210-aconnect"; 155 clocks = <&bpmp TEGRA264_CLK_APE>, 156 <&bpmp TEGRA264_CLK_ADSP>; 157 clock-names = "ape", "apb2ape"; 158 power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; 159 status = "disabled"; 160 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges = <0x9000000 0x0 0x9000000 0x2000000>; 164 165 adma: dma-controller@9440000 { 166 compatible = "nvidia,tegra264-adma"; 167 reg = <0x9440000 0xb0000>; 168 interrupt-parent = <&agic_page0>; 169 interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>; 233 #dma-cells = <1>; 234 clocks = <&bpmp TEGRA264_CLK_AHUB>; 235 clock-names = "d_audio"; 236 status = "disabled"; 237 }; 238 239 tegra_ahub: ahub@9630000 { 240 compatible = "nvidia,tegra264-ahub"; 241 reg = <0x9630000 0x10000>; 242 clocks = <&bpmp TEGRA264_CLK_AHUB>; 243 clock-names = "ahub"; 244 assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>; 245 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>; 246 status = "disabled"; 247 248 #address-cells = <1>; 249 #size-cells = <1>; 250 /* ADMA is under AHUB range, its excluded in the defined range */ 251 ranges = <0x9280000 0x9280000 0x1c0000>, 252 <0x9510000 0x9510000 0x370000>; 253 254 tegra_i2s1: i2s@9280000 { 255 compatible = "nvidia,tegra264-i2s"; 256 reg = <0x9280000 0x10000>; 257 clocks = <&bpmp TEGRA264_CLK_I2S1>, 258 <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>; 261 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S1"; 264 status = "disabled"; 265 266 ports { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 port@0 { 271 reg = <0>; 272 273 i2s1_cif: endpoint { 274 remote-endpoint = <&xbar_i2s1>; 275 }; 276 }; 277 278 i2s1_port: port@1 { 279 reg = <1>; 280 281 i2s1_dap: endpoint { 282 dai-format = "i2s"; 283 /* placeholder for external codec */ 284 }; 285 }; 286 }; 287 }; 288 289 tegra_i2s2: i2s@9290000 { 290 compatible = "nvidia,tegra264-i2s"; 291 reg = <0x9290000 0x10000>; 292 clocks = <&bpmp TEGRA264_CLK_I2S2>, 293 <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; 294 clock-names = "i2s", "sync_input"; 295 assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>; 296 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 297 assigned-clock-rates = <1536000>; 298 sound-name-prefix = "I2S2"; 299 status = "disabled"; 300 301 ports { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 port@0 { 306 reg = <0>; 307 308 i2s2_cif: endpoint { 309 remote-endpoint = <&xbar_i2s2>; 310 }; 311 }; 312 313 i2s2_port: port@1 { 314 reg = <1>; 315 316 i2s2_dap: endpoint { 317 dai-format = "i2s"; 318 /* placeholder for external codec */ 319 }; 320 }; 321 }; 322 }; 323 324 tegra_i2s3: i2s@92a0000 { 325 compatible = "nvidia,tegra264-i2s"; 326 reg = <0x92a0000 0x10000>; 327 clocks = <&bpmp TEGRA264_CLK_I2S3>, 328 <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 336 ports { 337 #address-cells = <1>; 338 #size-cells = <0>; 339 340 port@0 { 341 reg = <0>; 342 343 i2s3_cif: endpoint { 344 remote-endpoint = <&xbar_i2s3>; 345 }; 346 }; 347 348 i2s3_port: port@1 { 349 reg = <1>; 350 351 i2s3_dap: endpoint { 352 dai-format = "i2s"; 353 /* placeholder for external codec */ 354 }; 355 }; 356 }; 357 }; 358 359 tegra_i2s4: i2s@92b0000 { 360 compatible = "nvidia,tegra264-i2s"; 361 reg = <0x92b0000 0x10000>; 362 clocks = <&bpmp TEGRA264_CLK_I2S4>, 363 <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; 364 clock-names = "i2s", "sync_input"; 365 assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>; 366 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 367 assigned-clock-rates = <1536000>; 368 sound-name-prefix = "I2S4"; 369 status = "disabled"; 370 371 ports { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 port@0 { 376 reg = <0>; 377 378 i2s4_cif: endpoint { 379 remote-endpoint = <&xbar_i2s4>; 380 }; 381 }; 382 383 i2s4_port: port@1 { 384 reg = <1>; 385 386 i2s4_dap: endpoint { 387 dai-format = "i2s"; 388 /* placeholder for external codec */ 389 }; 390 }; 391 }; 392 }; 393 394 tegra_i2s5: i2s@92c0000 { 395 compatible = "nvidia,tegra264-i2s"; 396 reg = <0x92c0000 0x10000>; 397 clocks = <&bpmp TEGRA264_CLK_I2S5>, 398 <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; 399 clock-names = "i2s", "sync_input"; 400 assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>; 401 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 402 assigned-clock-rates = <1536000>; 403 sound-name-prefix = "I2S5"; 404 status = "disabled"; 405 406 ports { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 410 port@0 { 411 reg = <0>; 412 413 i2s5_cif: endpoint { 414 remote-endpoint = <&xbar_i2s5>; 415 }; 416 }; 417 418 i2s5_port: port@1 { 419 reg = <1>; 420 421 i2s5_dap: endpoint { 422 dai-format = "i2s"; 423 /* placeholder for external codec */ 424 }; 425 }; 426 }; 427 }; 428 429 tegra_i2s6: i2s@92d0000 { 430 compatible = "nvidia,tegra264-i2s"; 431 reg = <0x92d0000 0x10000>; 432 clocks = <&bpmp TEGRA264_CLK_I2S6>, 433 <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; 434 clock-names = "i2s", "sync_input"; 435 assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>; 436 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 437 assigned-clock-rates = <1536000>; 438 sound-name-prefix = "I2S6"; 439 status = "disabled"; 440 441 ports { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 445 port@0 { 446 reg = <0>; 447 448 i2s6_cif: endpoint { 449 remote-endpoint = <&xbar_i2s6>; 450 }; 451 }; 452 453 i2s6_port: port@1 { 454 reg = <1>; 455 456 i2s6_dap: endpoint { 457 dai-format = "i2s"; 458 /* placeholder for external codec */ 459 }; 460 }; 461 }; 462 }; 463 464 tegra_i2s7: i2s@92e0000 { 465 compatible = "nvidia,tegra264-i2s"; 466 reg = <0x92e0000 0x10000>; 467 clocks = <&bpmp TEGRA264_CLK_I2S7>, 468 <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; 469 clock-names = "i2s", "sync_input"; 470 assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>; 471 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 472 assigned-clock-rates = <1536000>; 473 sound-name-prefix = "I2S7"; 474 status = "disabled"; 475 476 ports { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 port@0 { 481 reg = <0>; 482 483 i2s7_cif: endpoint { 484 remote-endpoint = <&xbar_i2s7>; 485 }; 486 }; 487 488 i2s7_port: port@1 { 489 reg = <1>; 490 491 i2s7_dap: endpoint { 492 dai-format = "i2s"; 493 /* placeholder for external codec */ 494 }; 495 }; 496 }; 497 }; 498 499 tegra_i2s8: i2s@92f0000 { 500 compatible = "nvidia,tegra264-i2s"; 501 reg = <0x92f0000 0x10000>; 502 clocks = <&bpmp TEGRA264_CLK_I2S8>, 503 <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; 504 clock-names = "i2s", "sync_input"; 505 assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>; 506 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 507 assigned-clock-rates = <1536000>; 508 sound-name-prefix = "I2S8"; 509 status = "disabled"; 510 511 ports { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 port@0 { 516 reg = <0>; 517 518 i2s8_cif: endpoint { 519 remote-endpoint = <&xbar_i2s8>; 520 }; 521 }; 522 523 i2s8_port: port@1 { 524 reg = <1>; 525 526 i2s8_dap: endpoint { 527 dai-format = "i2s"; 528 /* placeholder for external codec */ 529 }; 530 }; 531 }; 532 }; 533 534 tegra_dmic1: dmic@9300000 { 535 compatible = "nvidia,tegra264-dmic", 536 "nvidia,tegra210-dmic"; 537 reg = <0x9300000 0x10000>; 538 clocks = <&bpmp TEGRA264_CLK_DMIC1>; 539 clock-names = "dmic"; 540 assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; 541 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 542 assigned-clock-rates = <3072000>; 543 sound-name-prefix = "DMIC1"; 544 status = "disabled"; 545 546 ports { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 550 port@0 { 551 reg = <0>; 552 553 dmic1_cif: endpoint { 554 remote-endpoint = <&xbar_dmic1>; 555 }; 556 }; 557 558 dmic1_port: port@1 { 559 reg = <1>; 560 561 dmic1_dap: endpoint { 562 /* placeholder for external codec */ 563 }; 564 }; 565 }; 566 }; 567 568 tegra_dmic2: dmic@9310000 { 569 compatible = "nvidia,tegra264-dmic", 570 "nvidia,tegra210-dmic"; 571 reg = <0x9310000 0x10000>; 572 clocks = <&bpmp TEGRA264_CLK_DMIC1>; 573 clock-names = "dmic"; 574 assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; 575 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 576 assigned-clock-rates = <3072000>; 577 sound-name-prefix = "DMIC2"; 578 status = "disabled"; 579 580 ports { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 port@0 { 585 reg = <0>; 586 587 dmic2_cif: endpoint { 588 remote-endpoint = <&xbar_dmic2>; 589 }; 590 }; 591 592 dmic2_port: port@1 { 593 reg = <1>; 594 595 dmic2_dap: endpoint { 596 /* placeholder for external codec */ 597 }; 598 }; 599 }; 600 }; 601 602 tegra_dspk1: dspk@9380000 { 603 compatible = "nvidia,tegra264-dspk", 604 "nvidia,tegra186-dspk"; 605 reg = <0x9380000 0x10000>; 606 clocks = <&bpmp TEGRA264_CLK_DSPK1>; 607 clock-names = "dspk"; 608 assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>; 609 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 610 assigned-clock-rates = <12288000>; 611 sound-name-prefix = "DSPK1"; 612 status = "disabled"; 613 614 ports { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 618 port@0 { 619 reg = <0>; 620 621 dspk1_cif: endpoint { 622 remote-endpoint = <&xbar_dspk1>; 623 }; 624 }; 625 626 dspk1_port: port@1 { 627 reg = <1>; 628 629 dspk1_dap: endpoint { 630 /* placeholder for external codec */ 631 }; 632 }; 633 }; 634 }; 635 636 tegra_amx1: amx@9510000 { 637 compatible = "nvidia,tegra264-amx"; 638 reg = <0x9510000 0x10000>; 639 sound-name-prefix = "AMX1"; 640 641 ports { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 port@0 { 646 reg = <0>; 647 648 amx1_in1: endpoint { 649 remote-endpoint = <&xbar_amx1_in1>; 650 }; 651 }; 652 653 port@1 { 654 reg = <1>; 655 656 amx1_in2: endpoint { 657 remote-endpoint = <&xbar_amx1_in2>; 658 }; 659 }; 660 661 port@2 { 662 reg = <2>; 663 664 amx1_in3: endpoint { 665 remote-endpoint = <&xbar_amx1_in3>; 666 }; 667 }; 668 669 port@3 { 670 reg = <3>; 671 672 amx1_in4: endpoint { 673 remote-endpoint = <&xbar_amx1_in4>; 674 }; 675 }; 676 677 amx1_out_port: port@4 { 678 reg = <4>; 679 680 amx1_out: endpoint { 681 remote-endpoint = <&xbar_amx1_out>; 682 }; 683 }; 684 }; 685 }; 686 687 tegra_amx2: amx@9520000 { 688 compatible = "nvidia,tegra264-amx"; 689 reg = <0x9520000 0x10000>; 690 sound-name-prefix = "AMX2"; 691 692 ports { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 port@0 { 697 reg = <0>; 698 699 amx2_in1: endpoint { 700 remote-endpoint = <&xbar_amx2_in1>; 701 }; 702 }; 703 704 port@1 { 705 reg = <1>; 706 707 amx2_in2: endpoint { 708 remote-endpoint = <&xbar_amx2_in2>; 709 }; 710 }; 711 712 port@2 { 713 reg = <2>; 714 715 amx2_in3: endpoint { 716 remote-endpoint = <&xbar_amx2_in3>; 717 }; 718 }; 719 720 port@3 { 721 reg = <3>; 722 723 amx2_in4: endpoint { 724 remote-endpoint = <&xbar_amx2_in4>; 725 }; 726 }; 727 728 amx2_out_port: port@4 { 729 reg = <4>; 730 731 amx2_out: endpoint { 732 remote-endpoint = <&xbar_amx2_out>; 733 }; 734 }; 735 }; 736 }; 737 738 tegra_amx3: amx@9530000 { 739 compatible = "nvidia,tegra264-amx"; 740 reg = <0x9530000 0x10000>; 741 sound-name-prefix = "AMX3"; 742 743 ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 port@0 { 748 reg = <0>; 749 750 amx3_in1: endpoint { 751 remote-endpoint = <&xbar_amx3_in1>; 752 }; 753 }; 754 755 port@1 { 756 reg = <1>; 757 758 amx3_in2: endpoint { 759 remote-endpoint = <&xbar_amx3_in2>; 760 }; 761 }; 762 763 port@2 { 764 reg = <2>; 765 766 amx3_in3: endpoint { 767 remote-endpoint = <&xbar_amx3_in3>; 768 }; 769 }; 770 771 port@3 { 772 reg = <3>; 773 774 amx3_in4: endpoint { 775 remote-endpoint = <&xbar_amx3_in4>; 776 }; 777 }; 778 779 amx3_out_port: port@4 { 780 reg = <4>; 781 782 amx3_out: endpoint { 783 remote-endpoint = <&xbar_amx3_out>; 784 }; 785 }; 786 }; 787 }; 788 789 tegra_amx4: amx@9540000 { 790 compatible = "nvidia,tegra264-amx"; 791 reg = <0x9540000 0x10000>; 792 sound-name-prefix = "AMX4"; 793 794 ports { 795 #address-cells = <1>; 796 #size-cells = <0>; 797 798 port@0 { 799 reg = <0>; 800 801 amx4_in1: endpoint { 802 remote-endpoint = <&xbar_amx4_in1>; 803 }; 804 }; 805 806 port@1 { 807 reg = <1>; 808 809 amx4_in2: endpoint { 810 remote-endpoint = <&xbar_amx4_in2>; 811 }; 812 }; 813 814 port@2 { 815 reg = <2>; 816 817 amx4_in3: endpoint { 818 remote-endpoint = <&xbar_amx4_in3>; 819 }; 820 }; 821 822 port@3 { 823 reg = <3>; 824 825 amx4_in4: endpoint { 826 remote-endpoint = <&xbar_amx4_in4>; 827 }; 828 }; 829 830 amx4_out_port: port@4 { 831 reg = <4>; 832 833 amx4_out: endpoint { 834 remote-endpoint = <&xbar_amx4_out>; 835 }; 836 }; 837 }; 838 }; 839 840 tegra_amx5: amx@9550000 { 841 compatible = "nvidia,tegra264-amx"; 842 reg = <0x9550000 0x10000>; 843 sound-name-prefix = "AMX5"; 844 845 ports { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 port@0 { 850 reg = <0>; 851 852 amx5_in1: endpoint { 853 remote-endpoint = <&xbar_amx5_in1>; 854 }; 855 }; 856 857 port@1 { 858 reg = <1>; 859 860 amx5_in2: endpoint { 861 remote-endpoint = <&xbar_amx5_in2>; 862 }; 863 }; 864 865 port@2 { 866 reg = <2>; 867 868 amx5_in3: endpoint { 869 remote-endpoint = <&xbar_amx5_in3>; 870 }; 871 }; 872 873 port@3 { 874 reg = <3>; 875 876 amx5_in4: endpoint { 877 remote-endpoint = <&xbar_amx5_in4>; 878 }; 879 }; 880 881 amx5_out_port: port@4 { 882 reg = <4>; 883 884 amx5_out: endpoint { 885 remote-endpoint = <&xbar_amx5_out>; 886 }; 887 }; 888 }; 889 }; 890 891 tegra_amx6: amx@9560000 { 892 compatible = "nvidia,tegra264-amx"; 893 reg = <0x9560000 0x10000>; 894 sound-name-prefix = "AMX6"; 895 896 ports { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 900 port@0 { 901 reg = <0>; 902 903 amx6_in1: endpoint { 904 remote-endpoint = <&xbar_amx6_in1>; 905 }; 906 }; 907 908 port@1 { 909 reg = <1>; 910 911 amx6_in2: endpoint { 912 remote-endpoint = <&xbar_amx6_in2>; 913 }; 914 }; 915 916 port@2 { 917 reg = <2>; 918 919 amx6_in3: endpoint { 920 remote-endpoint = <&xbar_amx6_in3>; 921 }; 922 }; 923 924 port@3 { 925 reg = <3>; 926 927 amx6_in4: endpoint { 928 remote-endpoint = <&xbar_amx6_in4>; 929 }; 930 }; 931 932 amx6_out_port: port@4 { 933 reg = <4>; 934 935 amx6_out: endpoint { 936 remote-endpoint = <&xbar_amx6_out>; 937 }; 938 }; 939 }; 940 }; 941 942 tegra_adx1: adx@9590000 { 943 compatible = "nvidia,tegra264-adx"; 944 reg = <0x9590000 0x10000>; 945 sound-name-prefix = "ADX1"; 946 947 ports { 948 #address-cells = <1>; 949 #size-cells = <0>; 950 951 port@0 { 952 reg = <0>; 953 954 adx1_in: endpoint { 955 remote-endpoint = <&xbar_adx1_in>; 956 }; 957 }; 958 959 adx1_out1_port: port@1 { 960 reg = <1>; 961 962 adx1_out1: endpoint { 963 remote-endpoint = <&xbar_adx1_out1>; 964 }; 965 }; 966 967 adx1_out2_port: port@2 { 968 reg = <2>; 969 970 adx1_out2: endpoint { 971 remote-endpoint = <&xbar_adx1_out2>; 972 }; 973 }; 974 975 adx1_out3_port: port@3 { 976 reg = <3>; 977 978 adx1_out3: endpoint { 979 remote-endpoint = <&xbar_adx1_out3>; 980 }; 981 }; 982 983 adx1_out4_port: port@4 { 984 reg = <4>; 985 986 adx1_out4: endpoint { 987 remote-endpoint = <&xbar_adx1_out4>; 988 }; 989 }; 990 }; 991 }; 992 993 tegra_adx2: adx@95a0000 { 994 compatible = "nvidia,tegra264-adx"; 995 reg = <0x95a0000 0x10000>; 996 sound-name-prefix = "ADX2"; 997 998 ports { 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 port@0 { 1003 reg = <0>; 1004 1005 adx2_in: endpoint { 1006 remote-endpoint = <&xbar_adx2_in>; 1007 }; 1008 }; 1009 1010 adx2_out1_port: port@1 { 1011 reg = <1>; 1012 1013 adx2_out1: endpoint { 1014 remote-endpoint = <&xbar_adx2_out1>; 1015 }; 1016 }; 1017 1018 adx2_out2_port: port@2 { 1019 reg = <2>; 1020 1021 adx2_out2: endpoint { 1022 remote-endpoint = <&xbar_adx2_out2>; 1023 }; 1024 }; 1025 1026 adx2_out3_port: port@3 { 1027 reg = <3>; 1028 1029 adx2_out3: endpoint { 1030 remote-endpoint = <&xbar_adx2_out3>; 1031 }; 1032 }; 1033 1034 adx2_out4_port: port@4 { 1035 reg = <4>; 1036 1037 adx2_out4: endpoint { 1038 remote-endpoint = <&xbar_adx2_out4>; 1039 }; 1040 }; 1041 }; 1042 }; 1043 1044 tegra_adx3: adx@95b0000 { 1045 compatible = "nvidia,tegra264-adx"; 1046 reg = <0x95b0000 0x10000>; 1047 sound-name-prefix = "ADX3"; 1048 1049 ports { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 port@0 { 1054 reg = <0>; 1055 1056 adx3_in: endpoint { 1057 remote-endpoint = <&xbar_adx3_in>; 1058 }; 1059 }; 1060 1061 adx3_out1_port: port@1 { 1062 reg = <1>; 1063 1064 adx3_out1: endpoint { 1065 remote-endpoint = <&xbar_adx3_out1>; 1066 }; 1067 }; 1068 1069 adx3_out2_port: port@2 { 1070 reg = <2>; 1071 1072 adx3_out2: endpoint { 1073 remote-endpoint = <&xbar_adx3_out2>; 1074 }; 1075 }; 1076 1077 adx3_out3_port: port@3 { 1078 reg = <3>; 1079 1080 adx3_out3: endpoint { 1081 remote-endpoint = <&xbar_adx3_out3>; 1082 }; 1083 }; 1084 1085 adx3_out4_port: port@4 { 1086 reg = <4>; 1087 1088 adx3_out4: endpoint { 1089 remote-endpoint = <&xbar_adx3_out4>; 1090 }; 1091 }; 1092 }; 1093 }; 1094 1095 tegra_adx4: adx@95c0000 { 1096 compatible = "nvidia,tegra264-adx"; 1097 reg = <0x95c0000 0x10000>; 1098 sound-name-prefix = "ADX4"; 1099 1100 ports { 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 1104 port@0 { 1105 reg = <0>; 1106 1107 adx4_in: endpoint { 1108 remote-endpoint = <&xbar_adx4_in>; 1109 }; 1110 }; 1111 1112 adx4_out1_port: port@1 { 1113 reg = <1>; 1114 1115 adx4_out1: endpoint { 1116 remote-endpoint = <&xbar_adx4_out1>; 1117 }; 1118 }; 1119 1120 adx4_out2_port: port@2 { 1121 reg = <2>; 1122 1123 adx4_out2: endpoint { 1124 remote-endpoint = <&xbar_adx4_out2>; 1125 }; 1126 }; 1127 1128 adx4_out3_port: port@3 { 1129 reg = <3>; 1130 1131 adx4_out3: endpoint { 1132 remote-endpoint = <&xbar_adx4_out3>; 1133 }; 1134 }; 1135 1136 adx4_out4_port: port@4 { 1137 reg = <4>; 1138 1139 adx4_out4: endpoint { 1140 remote-endpoint = <&xbar_adx4_out4>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 tegra_adx5: adx@95d0000 { 1147 compatible = "nvidia,tegra264-adx"; 1148 reg = <0x95d0000 0x10000>; 1149 sound-name-prefix = "ADX5"; 1150 1151 ports { 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 1155 port@0 { 1156 reg = <0>; 1157 1158 adx5_in: endpoint { 1159 remote-endpoint = <&xbar_adx5_in>; 1160 }; 1161 }; 1162 1163 adx5_out1_port: port@1 { 1164 reg = <1>; 1165 1166 adx5_out1: endpoint { 1167 remote-endpoint = <&xbar_adx5_out1>; 1168 }; 1169 }; 1170 1171 adx5_out2_port: port@2 { 1172 reg = <2>; 1173 1174 adx5_out2: endpoint { 1175 remote-endpoint = <&xbar_adx5_out2>; 1176 }; 1177 }; 1178 1179 adx5_out3_port: port@3 { 1180 reg = <3>; 1181 1182 adx5_out3: endpoint { 1183 remote-endpoint = <&xbar_adx5_out3>; 1184 }; 1185 }; 1186 1187 adx5_out4_port: port@4 { 1188 reg = <4>; 1189 1190 adx5_out4: endpoint { 1191 remote-endpoint = <&xbar_adx5_out4>; 1192 }; 1193 }; 1194 }; 1195 }; 1196 1197 tegra_adx6: adx@95e0000 { 1198 compatible = "nvidia,tegra264-adx"; 1199 reg = <0x95e0000 0x10000>; 1200 sound-name-prefix = "ADX6"; 1201 1202 ports { 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 port@0 { 1207 reg = <0>; 1208 1209 adx6_in: endpoint { 1210 remote-endpoint = <&xbar_adx6_in>; 1211 }; 1212 }; 1213 1214 adx6_out1_port: port@1 { 1215 reg = <1>; 1216 1217 adx6_out1: endpoint { 1218 remote-endpoint = <&xbar_adx6_out1>; 1219 }; 1220 }; 1221 1222 adx6_out2_port: port@2 { 1223 reg = <2>; 1224 1225 adx6_out2: endpoint { 1226 remote-endpoint = <&xbar_adx6_out2>; 1227 }; 1228 }; 1229 1230 adx6_out3_port: port@3 { 1231 reg = <3>; 1232 1233 adx6_out3: endpoint { 1234 remote-endpoint = <&xbar_adx6_out3>; 1235 }; 1236 }; 1237 1238 adx6_out4_port: port@4 { 1239 reg = <4>; 1240 1241 adx6_out4: endpoint { 1242 remote-endpoint = <&xbar_adx6_out4>; 1243 }; 1244 }; 1245 }; 1246 }; 1247 1248 tegra_admaif: admaif@9610000 { 1249 compatible = "nvidia,tegra264-admaif"; 1250 reg = <0x9610000 0x10000>; 1251 dmas = <&adma 1>, <&adma 1>, 1252 <&adma 2>, <&adma 2>, 1253 <&adma 3>, <&adma 3>, 1254 <&adma 4>, <&adma 4>, 1255 <&adma 5>, <&adma 5>, 1256 <&adma 6>, <&adma 6>, 1257 <&adma 7>, <&adma 7>, 1258 <&adma 8>, <&adma 8>, 1259 <&adma 9>, <&adma 9>, 1260 <&adma 10>, <&adma 10>, 1261 <&adma 11>, <&adma 11>, 1262 <&adma 12>, <&adma 12>, 1263 <&adma 13>, <&adma 13>, 1264 <&adma 14>, <&adma 14>, 1265 <&adma 15>, <&adma 15>, 1266 <&adma 16>, <&adma 16>, 1267 <&adma 17>, <&adma 17>, 1268 <&adma 18>, <&adma 18>, 1269 <&adma 19>, <&adma 19>, 1270 <&adma 20>, <&adma 20>, 1271 <&adma 21>, <&adma 21>, 1272 <&adma 22>, <&adma 22>, 1273 <&adma 23>, <&adma 23>, 1274 <&adma 24>, <&adma 24>, 1275 <&adma 25>, <&adma 25>, 1276 <&adma 26>, <&adma 26>, 1277 <&adma 27>, <&adma 27>, 1278 <&adma 28>, <&adma 28>, 1279 <&adma 29>, <&adma 29>, 1280 <&adma 30>, <&adma 30>, 1281 <&adma 31>, <&adma 31>, 1282 <&adma 32>, <&adma 32>; 1283 dma-names = "rx1", "tx1", 1284 "rx2", "tx2", 1285 "rx3", "tx3", 1286 "rx4", "tx4", 1287 "rx5", "tx5", 1288 "rx6", "tx6", 1289 "rx7", "tx7", 1290 "rx8", "tx8", 1291 "rx9", "tx9", 1292 "rx10", "tx10", 1293 "rx11", "tx11", 1294 "rx12", "tx12", 1295 "rx13", "tx13", 1296 "rx14", "tx14", 1297 "rx15", "tx15", 1298 "rx16", "tx16", 1299 "rx17", "tx17", 1300 "rx18", "tx18", 1301 "rx19", "tx19", 1302 "rx20", "tx20", 1303 "rx21", "tx21", 1304 "rx22", "tx22", 1305 "rx23", "tx23", 1306 "rx24", "tx24", 1307 "rx25", "tx25", 1308 "rx26", "tx26", 1309 "rx27", "tx27", 1310 "rx28", "tx28", 1311 "rx29", "tx29", 1312 "rx30", "tx30", 1313 "rx31", "tx31", 1314 "rx32", "tx32"; 1315 1316 interconnects = <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, 1317 <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; 1318 interconnect-names = "dma-mem", "write"; 1319 1320 iommus = <&smmu1 TEGRA264_SID_APE>; 1321 1322 ports { 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 admaif0_port: port@0 { 1327 reg = <0x0>; 1328 1329 admaif0: endpoint { 1330 remote-endpoint = <&xbar_admaif0>; 1331 }; 1332 }; 1333 1334 admaif1_port: port@1 { 1335 reg = <0x1>; 1336 1337 admaif1: endpoint { 1338 remote-endpoint = <&xbar_admaif1>; 1339 }; 1340 }; 1341 1342 admaif2_port: port@2 { 1343 reg = <0x2>; 1344 1345 admaif2: endpoint { 1346 remote-endpoint = <&xbar_admaif2>; 1347 }; 1348 }; 1349 1350 admaif3_port: port@3 { 1351 reg = <0x3>; 1352 1353 admaif3: endpoint { 1354 remote-endpoint = <&xbar_admaif3>; 1355 }; 1356 }; 1357 1358 admaif4_port: port@4 { 1359 reg = <0x4>; 1360 1361 admaif4: endpoint { 1362 remote-endpoint = <&xbar_admaif4>; 1363 }; 1364 }; 1365 1366 admaif5_port: port@5 { 1367 reg = <0x5>; 1368 1369 admaif5: endpoint { 1370 remote-endpoint = <&xbar_admaif5>; 1371 }; 1372 }; 1373 1374 admaif6_port: port@6 { 1375 reg = <0x6>; 1376 1377 admaif6: endpoint { 1378 remote-endpoint = <&xbar_admaif6>; 1379 }; 1380 }; 1381 1382 admaif7_port: port@7 { 1383 reg = <0x7>; 1384 1385 admaif7: endpoint { 1386 remote-endpoint = <&xbar_admaif7>; 1387 }; 1388 }; 1389 1390 admaif8_port: port@8 { 1391 reg = <0x8>; 1392 1393 admaif8: endpoint { 1394 remote-endpoint = <&xbar_admaif8>; 1395 }; 1396 }; 1397 1398 admaif9_port: port@9 { 1399 reg = <0x9>; 1400 1401 admaif9: endpoint { 1402 remote-endpoint = <&xbar_admaif9>; 1403 }; 1404 }; 1405 1406 admaif10_port: port@a { 1407 reg = <0xa>; 1408 1409 admaif10: endpoint { 1410 remote-endpoint = <&xbar_admaif10>; 1411 }; 1412 }; 1413 1414 admaif11_port: port@b { 1415 reg = <0xb>; 1416 1417 admaif11: endpoint { 1418 remote-endpoint = <&xbar_admaif11>; 1419 }; 1420 }; 1421 1422 admaif12_port: port@c { 1423 reg = <0xc>; 1424 1425 admaif12: endpoint { 1426 remote-endpoint = <&xbar_admaif12>; 1427 }; 1428 }; 1429 1430 admaif13_port: port@d { 1431 reg = <0xd>; 1432 1433 admaif13: endpoint { 1434 remote-endpoint = <&xbar_admaif13>; 1435 }; 1436 }; 1437 1438 admaif14_port: port@e { 1439 reg = <0xe>; 1440 1441 admaif14: endpoint { 1442 remote-endpoint = <&xbar_admaif14>; 1443 }; 1444 }; 1445 1446 admaif15_port: port@f { 1447 reg = <0xf>; 1448 1449 admaif15: endpoint { 1450 remote-endpoint = <&xbar_admaif15>; 1451 }; 1452 }; 1453 1454 admaif16_port: port@10 { 1455 reg = <0x10>; 1456 1457 admaif16: endpoint { 1458 remote-endpoint = <&xbar_admaif16>; 1459 }; 1460 }; 1461 1462 admaif17_port: port@11 { 1463 reg = <0x11>; 1464 1465 admaif17: endpoint { 1466 remote-endpoint = <&xbar_admaif17>; 1467 }; 1468 }; 1469 1470 admaif18_port: port@12 { 1471 reg = <0x12>; 1472 1473 admaif18: endpoint { 1474 remote-endpoint = <&xbar_admaif18>; 1475 }; 1476 }; 1477 1478 admaif19_port: port@13 { 1479 reg = <0x13>; 1480 1481 admaif19: endpoint { 1482 remote-endpoint = <&xbar_admaif19>; 1483 }; 1484 }; 1485 1486 admaif20_port: port@14 { 1487 reg = <0x14>; 1488 1489 admaif20: endpoint { 1490 remote-endpoint = <&xbar_admaif20>; 1491 }; 1492 }; 1493 1494 admaif21_port: port@15 { 1495 reg = <0x15>; 1496 1497 admaif21: endpoint { 1498 remote-endpoint = <&xbar_admaif21>; 1499 }; 1500 }; 1501 1502 admaif22_port: port@16 { 1503 reg = <0x16>; 1504 1505 admaif22: endpoint { 1506 remote-endpoint = <&xbar_admaif22>; 1507 }; 1508 }; 1509 1510 admaif23_port: port@17 { 1511 reg = <0x17>; 1512 1513 admaif23: endpoint { 1514 remote-endpoint = <&xbar_admaif23>; 1515 }; 1516 }; 1517 1518 admaif24_port: port@18 { 1519 reg = <0x18>; 1520 1521 admaif24: endpoint { 1522 remote-endpoint = <&xbar_admaif24>; 1523 }; 1524 }; 1525 1526 admaif25_port: port@19 { 1527 reg = <0x19>; 1528 1529 admaif25: endpoint { 1530 remote-endpoint = <&xbar_admaif25>; 1531 }; 1532 }; 1533 1534 admaif26_port: port@1a { 1535 reg = <0x1a>; 1536 1537 admaif26: endpoint { 1538 remote-endpoint = <&xbar_admaif26>; 1539 }; 1540 }; 1541 1542 admaif27_port: port@1b { 1543 reg = <0x1b>; 1544 1545 admaif27: endpoint { 1546 remote-endpoint = <&xbar_admaif27>; 1547 }; 1548 }; 1549 1550 admaif28_port: port@1c { 1551 reg = <0x1c>; 1552 1553 admaif28: endpoint { 1554 remote-endpoint = <&xbar_admaif28>; 1555 }; 1556 }; 1557 1558 admaif29_port: port@1d { 1559 reg = <0x1d>; 1560 1561 admaif29: endpoint { 1562 remote-endpoint = <&xbar_admaif29>; 1563 }; 1564 }; 1565 1566 admaif30_port: port@1e { 1567 reg = <0x1e>; 1568 1569 admaif30: endpoint { 1570 remote-endpoint = <&xbar_admaif30>; 1571 }; 1572 }; 1573 1574 admaif31_port: port@1f { 1575 reg = <0x1f>; 1576 1577 admaif31: endpoint { 1578 remote-endpoint = <&xbar_admaif31>; 1579 }; 1580 }; 1581 }; 1582 }; 1583 1584 tegra_sfc1: sfc@9700000 { 1585 compatible = "nvidia,tegra264-sfc", 1586 "nvidia,tegra210-sfc"; 1587 reg = <0x9700000 0x10000>; 1588 sound-name-prefix = "SFC1"; 1589 1590 ports { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 port@0 { 1595 reg = <0>; 1596 1597 sfc1_cif_in: endpoint { 1598 remote-endpoint = <&xbar_sfc1_in>; 1599 }; 1600 }; 1601 1602 sfc1_out_port: port@1 { 1603 reg = <1>; 1604 1605 sfc1_cif_out: endpoint { 1606 remote-endpoint = <&xbar_sfc1_out>; 1607 }; 1608 }; 1609 }; 1610 }; 1611 1612 tegra_sfc2: sfc@9710000 { 1613 compatible = "nvidia,tegra264-sfc", 1614 "nvidia,tegra210-sfc"; 1615 reg = <0x9710000 0x10000>; 1616 sound-name-prefix = "SFC2"; 1617 1618 ports { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 port@0 { 1623 reg = <0>; 1624 1625 sfc2_cif_in: endpoint { 1626 remote-endpoint = <&xbar_sfc2_in>; 1627 }; 1628 }; 1629 1630 sfc2_out_port: port@1 { 1631 reg = <1>; 1632 1633 sfc2_cif_out: endpoint { 1634 remote-endpoint = <&xbar_sfc2_out>; 1635 }; 1636 }; 1637 }; 1638 }; 1639 1640 tegra_sfc3: sfc@9720000 { 1641 compatible = "nvidia,tegra264-sfc", 1642 "nvidia,tegra210-sfc"; 1643 reg = <0x9720000 0x10000>; 1644 sound-name-prefix = "SFC3"; 1645 1646 ports { 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 port@0 { 1651 reg = <0>; 1652 1653 sfc3_cif_in: endpoint { 1654 remote-endpoint = <&xbar_sfc3_in>; 1655 }; 1656 }; 1657 1658 sfc3_out_port: port@1 { 1659 reg = <1>; 1660 1661 sfc3_cif_out: endpoint { 1662 remote-endpoint = <&xbar_sfc3_out>; 1663 }; 1664 }; 1665 }; 1666 }; 1667 1668 tegra_sfc4: sfc@9730000 { 1669 compatible = "nvidia,tegra264-sfc", 1670 "nvidia,tegra210-sfc"; 1671 reg = <0x9730000 0x10000>; 1672 sound-name-prefix = "SFC4"; 1673 1674 ports { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 port@0 { 1679 reg = <0>; 1680 1681 sfc4_cif_in: endpoint { 1682 remote-endpoint = <&xbar_sfc4_in>; 1683 }; 1684 }; 1685 1686 sfc4_out_port: port@1 { 1687 reg = <1>; 1688 1689 sfc4_cif_out: endpoint { 1690 remote-endpoint = <&xbar_sfc4_out>; 1691 }; 1692 }; 1693 }; 1694 }; 1695 1696 tegra_ope1: processing-engine@9780000 { 1697 compatible = "nvidia,tegra264-ope", 1698 "nvidia,tegra210-ope"; 1699 reg = <0x9780000 0x10000>; 1700 #address-cells = <1>; 1701 #size-cells = <1>; 1702 ranges = <0x9780000 0x9780000 0x30000>; 1703 sound-name-prefix = "OPE1"; 1704 1705 equalizer@9790000 { 1706 compatible = "nvidia,tegra264-peq", 1707 "nvidia,tegra210-peq"; 1708 reg = <0x9790000 0x10000>; 1709 }; 1710 1711 dynamic-range-compressor@97a0000 { 1712 compatible = "nvidia,tegra264-mbdrc", 1713 "nvidia,tegra210-mbdrc"; 1714 reg = <0x97a0000 0x10000>; 1715 }; 1716 1717 ports { 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 1721 port@0 { 1722 reg = <0x0>; 1723 1724 ope1_cif_in_ep: endpoint { 1725 remote-endpoint = <&xbar_ope1_in_ep>; 1726 }; 1727 }; 1728 1729 ope1_out_port: port@1 { 1730 reg = <0x1>; 1731 1732 ope1_cif_out_ep: endpoint { 1733 remote-endpoint = <&xbar_ope1_out_ep>; 1734 }; 1735 }; 1736 }; 1737 }; 1738 1739 tegra_mvc1: mvc@9800000 { 1740 compatible = "nvidia,tegra264-mvc", 1741 "nvidia,tegra210-mvc"; 1742 reg = <0x9800000 0x10000>; 1743 sound-name-prefix = "MVC1"; 1744 1745 ports { 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 1749 port@0 { 1750 reg = <0>; 1751 1752 mvc1_cif_in: endpoint { 1753 remote-endpoint = <&xbar_mvc1_in>; 1754 }; 1755 }; 1756 1757 mvc1_out_port: port@1 { 1758 reg = <1>; 1759 1760 mvc1_cif_out: endpoint { 1761 remote-endpoint = <&xbar_mvc1_out>; 1762 }; 1763 }; 1764 }; 1765 }; 1766 1767 tegra_mvc2: mvc@9810000 { 1768 compatible = "nvidia,tegra264-mvc", 1769 "nvidia,tegra210-mvc"; 1770 reg = <0x9810000 0x10000>; 1771 sound-name-prefix = "MVC2"; 1772 1773 ports { 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 1777 port@0 { 1778 reg = <0>; 1779 1780 mvc2_cif_in: endpoint { 1781 remote-endpoint = <&xbar_mvc2_in>; 1782 }; 1783 }; 1784 1785 mvc2_out_port: port@1 { 1786 reg = <1>; 1787 1788 mvc2_cif_out: endpoint { 1789 remote-endpoint = <&xbar_mvc2_out>; 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 tegra_amixer: amixer@9820000 { 1796 compatible = "nvidia,tegra264-amixer", 1797 "nvidia,tegra210-amixer"; 1798 reg = <0x9820000 0x10000>; 1799 sound-name-prefix = "MIXER1"; 1800 1801 ports { 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 1805 port@0 { 1806 reg = <0x0>; 1807 1808 mix_in1: endpoint { 1809 remote-endpoint = <&xbar_mix_in1>; 1810 }; 1811 }; 1812 1813 port@1 { 1814 reg = <0x1>; 1815 1816 mix_in2: endpoint { 1817 remote-endpoint = <&xbar_mix_in2>; 1818 }; 1819 }; 1820 1821 port@2 { 1822 reg = <0x2>; 1823 1824 mix_in3: endpoint { 1825 remote-endpoint = <&xbar_mix_in3>; 1826 }; 1827 }; 1828 1829 port@3 { 1830 reg = <0x3>; 1831 1832 mix_in4: endpoint { 1833 remote-endpoint = <&xbar_mix_in4>; 1834 }; 1835 }; 1836 1837 port@4 { 1838 reg = <0x4>; 1839 1840 mix_in5: endpoint { 1841 remote-endpoint = <&xbar_mix_in5>; 1842 }; 1843 }; 1844 1845 port@5 { 1846 reg = <0x5>; 1847 1848 mix_in6: endpoint { 1849 remote-endpoint = <&xbar_mix_in6>; 1850 }; 1851 }; 1852 1853 port@6 { 1854 reg = <0x6>; 1855 1856 mix_in7: endpoint { 1857 remote-endpoint = <&xbar_mix_in7>; 1858 }; 1859 }; 1860 1861 port@7 { 1862 reg = <0x7>; 1863 1864 mix_in8: endpoint { 1865 remote-endpoint = <&xbar_mix_in8>; 1866 }; 1867 }; 1868 1869 port@8 { 1870 reg = <0x8>; 1871 1872 mix_in9: endpoint { 1873 remote-endpoint = <&xbar_mix_in9>; 1874 }; 1875 }; 1876 1877 port@9 { 1878 reg = <0x9>; 1879 1880 mix_in10: endpoint { 1881 remote-endpoint = <&xbar_mix_in10>; 1882 }; 1883 }; 1884 1885 mix_out1_port: port@a { 1886 reg = <0xa>; 1887 1888 mix_out1: endpoint { 1889 remote-endpoint = <&xbar_mix_out1>; 1890 }; 1891 }; 1892 1893 mix_out2_port: port@b { 1894 reg = <0xb>; 1895 1896 mix_out2: endpoint { 1897 remote-endpoint = <&xbar_mix_out2>; 1898 }; 1899 }; 1900 1901 mix_out3_port: port@c { 1902 reg = <0xc>; 1903 1904 mix_out3: endpoint { 1905 remote-endpoint = <&xbar_mix_out3>; 1906 }; 1907 }; 1908 1909 mix_out4_port: port@d { 1910 reg = <0xd>; 1911 1912 mix_out4: endpoint { 1913 remote-endpoint = <&xbar_mix_out4>; 1914 }; 1915 }; 1916 1917 mix_out5_port: port@e { 1918 reg = <0xe>; 1919 1920 mix_out5: endpoint { 1921 remote-endpoint = <&xbar_mix_out5>; 1922 }; 1923 }; 1924 }; 1925 }; 1926 1927 tegra_asrc: asrc@9850000 { 1928 compatible = "nvidia,tegra264-asrc"; 1929 reg = <0x9850000 0x10000>; 1930 sound-name-prefix = "ASRC1"; 1931 1932 ports { 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 1936 port@0 { 1937 reg = <0x0>; 1938 1939 asrc_in1_ep: endpoint { 1940 remote-endpoint = <&xbar_asrc_in1_ep>; 1941 }; 1942 }; 1943 1944 port@1 { 1945 reg = <0x1>; 1946 1947 asrc_in2_ep: endpoint { 1948 remote-endpoint = <&xbar_asrc_in2_ep>; 1949 }; 1950 }; 1951 1952 port@2 { 1953 reg = <0x2>; 1954 1955 asrc_in3_ep: endpoint { 1956 remote-endpoint = <&xbar_asrc_in3_ep>; 1957 }; 1958 }; 1959 1960 port@3 { 1961 reg = <0x3>; 1962 1963 asrc_in4_ep: endpoint { 1964 remote-endpoint = <&xbar_asrc_in4_ep>; 1965 }; 1966 }; 1967 1968 port@4 { 1969 reg = <0x4>; 1970 1971 asrc_in5_ep: endpoint { 1972 remote-endpoint = <&xbar_asrc_in5_ep>; 1973 }; 1974 }; 1975 1976 port@5 { 1977 reg = <0x5>; 1978 1979 asrc_in6_ep: endpoint { 1980 remote-endpoint = <&xbar_asrc_in6_ep>; 1981 }; 1982 }; 1983 1984 port@6 { 1985 reg = <0x6>; 1986 1987 asrc_in7_ep: endpoint { 1988 remote-endpoint = <&xbar_asrc_in7_ep>; 1989 }; 1990 }; 1991 1992 asrc_out1_port: port@7 { 1993 reg = <0x7>; 1994 1995 asrc_out1_ep: endpoint { 1996 remote-endpoint = <&xbar_asrc_out1_ep>; 1997 }; 1998 }; 1999 2000 asrc_out2_port: port@8 { 2001 reg = <0x8>; 2002 2003 asrc_out2_ep: endpoint { 2004 remote-endpoint = <&xbar_asrc_out2_ep>; 2005 }; 2006 }; 2007 2008 asrc_out3_port: port@9 { 2009 reg = <0x9>; 2010 2011 asrc_out3_ep: endpoint { 2012 remote-endpoint = <&xbar_asrc_out3_ep>; 2013 }; 2014 }; 2015 2016 asrc_out4_port: port@a { 2017 reg = <0xa>; 2018 2019 asrc_out4_ep: endpoint { 2020 remote-endpoint = <&xbar_asrc_out4_ep>; 2021 }; 2022 }; 2023 2024 asrc_out5_port: port@b { 2025 reg = <0xb>; 2026 2027 asrc_out5_ep: endpoint { 2028 remote-endpoint = <&xbar_asrc_out5_ep>; 2029 }; 2030 }; 2031 2032 asrc_out6_port: port@c { 2033 reg = <0xc>; 2034 2035 asrc_out6_ep: endpoint { 2036 remote-endpoint = <&xbar_asrc_out6_ep>; 2037 }; 2038 }; 2039 }; 2040 }; 2041 2042 ports { 2043 #address-cells = <1>; 2044 #size-cells = <0>; 2045 2046 port@0 { 2047 reg = <0x0>; 2048 2049 xbar_admaif0: endpoint { 2050 remote-endpoint = <&admaif0>; 2051 }; 2052 }; 2053 2054 port@1 { 2055 reg = <0x1>; 2056 2057 xbar_admaif1: endpoint { 2058 remote-endpoint = <&admaif1>; 2059 }; 2060 }; 2061 2062 port@2 { 2063 reg = <0x2>; 2064 2065 xbar_admaif2: endpoint { 2066 remote-endpoint = <&admaif2>; 2067 }; 2068 }; 2069 2070 port@3 { 2071 reg = <0x3>; 2072 2073 xbar_admaif3: endpoint { 2074 remote-endpoint = <&admaif3>; 2075 }; 2076 }; 2077 2078 port@4 { 2079 reg = <0x4>; 2080 2081 xbar_admaif4: endpoint { 2082 remote-endpoint = <&admaif4>; 2083 }; 2084 }; 2085 2086 port@5 { 2087 reg = <0x5>; 2088 2089 xbar_admaif5: endpoint { 2090 remote-endpoint = <&admaif5>; 2091 }; 2092 }; 2093 2094 port@6 { 2095 reg = <0x6>; 2096 2097 xbar_admaif6: endpoint { 2098 remote-endpoint = <&admaif6>; 2099 }; 2100 }; 2101 2102 port@7 { 2103 reg = <0x7>; 2104 2105 xbar_admaif7: endpoint { 2106 remote-endpoint = <&admaif7>; 2107 }; 2108 }; 2109 2110 port@8 { 2111 reg = <0x8>; 2112 2113 xbar_admaif8: endpoint { 2114 remote-endpoint = <&admaif8>; 2115 }; 2116 }; 2117 2118 port@9 { 2119 reg = <0x9>; 2120 2121 xbar_admaif9: endpoint { 2122 remote-endpoint = <&admaif9>; 2123 }; 2124 }; 2125 2126 port@a { 2127 reg = <0xa>; 2128 2129 xbar_admaif10: endpoint { 2130 remote-endpoint = <&admaif10>; 2131 }; 2132 }; 2133 2134 port@b { 2135 reg = <0xb>; 2136 2137 xbar_admaif11: endpoint { 2138 remote-endpoint = <&admaif11>; 2139 }; 2140 }; 2141 2142 port@c { 2143 reg = <0xc>; 2144 2145 xbar_admaif12: endpoint { 2146 remote-endpoint = <&admaif12>; 2147 }; 2148 }; 2149 2150 port@d { 2151 reg = <0xd>; 2152 2153 xbar_admaif13: endpoint { 2154 remote-endpoint = <&admaif13>; 2155 }; 2156 }; 2157 2158 port@e { 2159 reg = <0xe>; 2160 2161 xbar_admaif14: endpoint { 2162 remote-endpoint = <&admaif14>; 2163 }; 2164 }; 2165 2166 port@f { 2167 reg = <0xf>; 2168 2169 xbar_admaif15: endpoint { 2170 remote-endpoint = <&admaif15>; 2171 }; 2172 }; 2173 2174 port@10 { 2175 reg = <0x10>; 2176 2177 xbar_admaif16: endpoint { 2178 remote-endpoint = <&admaif16>; 2179 }; 2180 }; 2181 2182 port@11 { 2183 reg = <0x11>; 2184 2185 xbar_admaif17: endpoint { 2186 remote-endpoint = <&admaif17>; 2187 }; 2188 }; 2189 2190 port@12 { 2191 reg = <0x12>; 2192 2193 xbar_admaif18: endpoint { 2194 remote-endpoint = <&admaif18>; 2195 }; 2196 }; 2197 2198 port@13 { 2199 reg = <0x13>; 2200 2201 xbar_admaif19: endpoint { 2202 remote-endpoint = <&admaif19>; 2203 }; 2204 }; 2205 2206 port@14 { 2207 reg = <0x14>; 2208 2209 xbar_admaif20: endpoint { 2210 remote-endpoint = <&admaif20>; 2211 }; 2212 }; 2213 2214 port@15 { 2215 reg = <0x15>; 2216 2217 xbar_admaif21: endpoint { 2218 remote-endpoint = <&admaif21>; 2219 }; 2220 }; 2221 2222 port@16 { 2223 reg = <0x16>; 2224 2225 xbar_admaif22: endpoint { 2226 remote-endpoint = <&admaif22>; 2227 }; 2228 }; 2229 2230 port@17 { 2231 reg = <0x17>; 2232 2233 xbar_admaif23: endpoint { 2234 remote-endpoint = <&admaif23>; 2235 }; 2236 }; 2237 2238 port@18 { 2239 reg = <0x18>; 2240 2241 xbar_admaif24: endpoint { 2242 remote-endpoint = <&admaif24>; 2243 }; 2244 }; 2245 2246 port@19 { 2247 reg = <0x19>; 2248 2249 xbar_admaif25: endpoint { 2250 remote-endpoint = <&admaif25>; 2251 }; 2252 }; 2253 2254 port@1a { 2255 reg = <0x1a>; 2256 2257 xbar_admaif26: endpoint { 2258 remote-endpoint = <&admaif26>; 2259 }; 2260 }; 2261 2262 port@1b { 2263 reg = <0x1b>; 2264 2265 xbar_admaif27: endpoint { 2266 remote-endpoint = <&admaif27>; 2267 }; 2268 }; 2269 2270 port@1c { 2271 reg = <0x1c>; 2272 2273 xbar_admaif28: endpoint { 2274 remote-endpoint = <&admaif28>; 2275 }; 2276 }; 2277 2278 port@1d { 2279 reg = <0x1d>; 2280 2281 xbar_admaif29: endpoint { 2282 remote-endpoint = <&admaif29>; 2283 }; 2284 }; 2285 2286 port@1e { 2287 reg = <0x1e>; 2288 2289 xbar_admaif30: endpoint { 2290 remote-endpoint = <&admaif30>; 2291 }; 2292 }; 2293 2294 port@1f { 2295 reg = <0x1f>; 2296 2297 xbar_admaif31: endpoint { 2298 remote-endpoint = <&admaif31>; 2299 }; 2300 }; 2301 2302 xbar_i2s1_port: port@20 { 2303 reg = <0x20>; 2304 2305 xbar_i2s1: endpoint { 2306 remote-endpoint = <&i2s1_cif>; 2307 }; 2308 }; 2309 2310 xbar_i2s2_port: port@21 { 2311 reg = <0x21>; 2312 2313 xbar_i2s2: endpoint { 2314 remote-endpoint = <&i2s2_cif>; 2315 }; 2316 }; 2317 2318 xbar_i2s3_port: port@22 { 2319 reg = <0x22>; 2320 2321 xbar_i2s3: endpoint { 2322 remote-endpoint = <&i2s3_cif>; 2323 }; 2324 }; 2325 2326 xbar_i2s4_port: port@23 { 2327 reg = <0x23>; 2328 2329 xbar_i2s4: endpoint { 2330 remote-endpoint = <&i2s4_cif>; 2331 }; 2332 }; 2333 2334 xbar_i2s5_port: port@24 { 2335 reg = <0x24>; 2336 2337 xbar_i2s5: endpoint { 2338 remote-endpoint = <&i2s5_cif>; 2339 }; 2340 }; 2341 2342 xbar_i2s6_port: port@25 { 2343 reg = <0x25>; 2344 2345 xbar_i2s6: endpoint { 2346 remote-endpoint = <&i2s6_cif>; 2347 }; 2348 }; 2349 2350 xbar_i2s7_port: port@26 { 2351 reg = <0x26>; 2352 2353 xbar_i2s7: endpoint { 2354 remote-endpoint = <&i2s7_cif>; 2355 }; 2356 }; 2357 2358 xbar_i2s8_port: port@27 { 2359 reg = <0x27>; 2360 2361 xbar_i2s8: endpoint { 2362 remote-endpoint = <&i2s8_cif>; 2363 }; 2364 }; 2365 2366 xbar_dmic1_port: port@28 { 2367 reg = <0x28>; 2368 2369 xbar_dmic1: endpoint { 2370 remote-endpoint = <&dmic1_cif>; 2371 }; 2372 }; 2373 2374 xbar_dmic2_port: port@29 { 2375 reg = <0x29>; 2376 2377 xbar_dmic2: endpoint { 2378 remote-endpoint = <&dmic2_cif>; 2379 }; 2380 }; 2381 2382 xbar_dspk1_port: port@2a { 2383 reg = <0x2a>; 2384 2385 xbar_dspk1: endpoint { 2386 remote-endpoint = <&dspk1_cif>; 2387 }; 2388 }; 2389 2390 xbar_sfc1_in_port: port@2b { 2391 reg = <0x2b>; 2392 2393 xbar_sfc1_in: endpoint { 2394 remote-endpoint = <&sfc1_cif_in>; 2395 }; 2396 }; 2397 2398 port@2c { 2399 reg = <0x2c>; 2400 2401 xbar_sfc1_out: endpoint { 2402 remote-endpoint = <&sfc1_cif_out>; 2403 }; 2404 }; 2405 2406 xbar_sfc2_in_port: port@2d { 2407 reg = <0x2d>; 2408 2409 xbar_sfc2_in: endpoint { 2410 remote-endpoint = <&sfc2_cif_in>; 2411 }; 2412 }; 2413 2414 port@2e { 2415 reg = <0x2e>; 2416 2417 xbar_sfc2_out: endpoint { 2418 remote-endpoint = <&sfc2_cif_out>; 2419 }; 2420 }; 2421 2422 xbar_sfc3_in_port: port@2f { 2423 reg = <0x2f>; 2424 2425 xbar_sfc3_in: endpoint { 2426 remote-endpoint = <&sfc3_cif_in>; 2427 }; 2428 }; 2429 2430 port@30 { 2431 reg = <0x30>; 2432 2433 xbar_sfc3_out: endpoint { 2434 remote-endpoint = <&sfc3_cif_out>; 2435 }; 2436 }; 2437 2438 xbar_sfc4_in_port: port@31 { 2439 reg = <0x31>; 2440 2441 xbar_sfc4_in: endpoint { 2442 remote-endpoint = <&sfc4_cif_in>; 2443 }; 2444 }; 2445 2446 port@32 { 2447 reg = <0x32>; 2448 2449 xbar_sfc4_out: endpoint { 2450 remote-endpoint = <&sfc4_cif_out>; 2451 }; 2452 }; 2453 2454 xbar_mvc1_in_port: port@33 { 2455 reg = <0x33>; 2456 2457 xbar_mvc1_in: endpoint { 2458 remote-endpoint = <&mvc1_cif_in>; 2459 }; 2460 }; 2461 2462 port@34 { 2463 reg = <0x34>; 2464 2465 xbar_mvc1_out: endpoint { 2466 remote-endpoint = <&mvc1_cif_out>; 2467 }; 2468 }; 2469 2470 xbar_mvc2_in_port: port@35 { 2471 reg = <0x35>; 2472 2473 xbar_mvc2_in: endpoint { 2474 remote-endpoint = <&mvc2_cif_in>; 2475 }; 2476 }; 2477 2478 port@36 { 2479 reg = <0x36>; 2480 2481 xbar_mvc2_out: endpoint { 2482 remote-endpoint = <&mvc2_cif_out>; 2483 }; 2484 }; 2485 2486 xbar_amx1_in1_port: port@37 { 2487 reg = <0x37>; 2488 2489 xbar_amx1_in1: endpoint { 2490 remote-endpoint = <&amx1_in1>; 2491 }; 2492 }; 2493 2494 xbar_amx1_in2_port: port@38 { 2495 reg = <0x38>; 2496 2497 xbar_amx1_in2: endpoint { 2498 remote-endpoint = <&amx1_in2>; 2499 }; 2500 }; 2501 2502 xbar_amx1_in3_port: port@39 { 2503 reg = <0x39>; 2504 2505 xbar_amx1_in3: endpoint { 2506 remote-endpoint = <&amx1_in3>; 2507 }; 2508 }; 2509 2510 xbar_amx1_in4_port: port@3a { 2511 reg = <0x3a>; 2512 2513 xbar_amx1_in4: endpoint { 2514 remote-endpoint = <&amx1_in4>; 2515 }; 2516 }; 2517 2518 port@3b { 2519 reg = <0x3b>; 2520 2521 xbar_amx1_out: endpoint { 2522 remote-endpoint = <&amx1_out>; 2523 }; 2524 }; 2525 2526 xbar_amx2_in1_port: port@3c { 2527 reg = <0x3c>; 2528 2529 xbar_amx2_in1: endpoint { 2530 remote-endpoint = <&amx2_in1>; 2531 }; 2532 }; 2533 2534 xbar_amx2_in2_port: port@3d { 2535 reg = <0x3d>; 2536 2537 xbar_amx2_in2: endpoint { 2538 remote-endpoint = <&amx2_in2>; 2539 }; 2540 }; 2541 2542 xbar_amx2_in3_port: port@3e { 2543 reg = <0x3e>; 2544 2545 xbar_amx2_in3: endpoint { 2546 remote-endpoint = <&amx2_in3>; 2547 }; 2548 }; 2549 2550 xbar_amx2_in4_port: port@3f { 2551 reg = <0x3f>; 2552 2553 xbar_amx2_in4: endpoint { 2554 remote-endpoint = <&amx2_in4>; 2555 }; 2556 }; 2557 2558 port@40 { 2559 reg = <0x40>; 2560 2561 xbar_amx2_out: endpoint { 2562 remote-endpoint = <&amx2_out>; 2563 }; 2564 }; 2565 2566 xbar_amx3_in1_port: port@41 { 2567 reg = <0x41>; 2568 2569 xbar_amx3_in1: endpoint { 2570 remote-endpoint = <&amx3_in1>; 2571 }; 2572 }; 2573 2574 xbar_amx3_in2_port: port@42 { 2575 reg = <0x42>; 2576 2577 xbar_amx3_in2: endpoint { 2578 remote-endpoint = <&amx3_in2>; 2579 }; 2580 }; 2581 2582 xbar_amx3_in3_port: port@43 { 2583 reg = <0x43>; 2584 2585 xbar_amx3_in3: endpoint { 2586 remote-endpoint = <&amx3_in3>; 2587 }; 2588 }; 2589 2590 xbar_amx3_in4_port: port@44 { 2591 reg = <0x44>; 2592 2593 xbar_amx3_in4: endpoint { 2594 remote-endpoint = <&amx3_in4>; 2595 }; 2596 }; 2597 2598 port@45 { 2599 reg = <0x45>; 2600 2601 xbar_amx3_out: endpoint { 2602 remote-endpoint = <&amx3_out>; 2603 }; 2604 }; 2605 2606 xbar_amx4_in1_port: port@46 { 2607 reg = <0x46>; 2608 2609 xbar_amx4_in1: endpoint { 2610 remote-endpoint = <&amx4_in1>; 2611 }; 2612 }; 2613 2614 xbar_amx4_in2_port: port@47 { 2615 reg = <0x47>; 2616 2617 xbar_amx4_in2: endpoint { 2618 remote-endpoint = <&amx4_in2>; 2619 }; 2620 }; 2621 2622 xbar_amx4_in3_port: port@48 { 2623 reg = <0x48>; 2624 2625 xbar_amx4_in3: endpoint { 2626 remote-endpoint = <&amx4_in3>; 2627 }; 2628 }; 2629 2630 xbar_amx4_in4_port: port@49 { 2631 reg = <0x49>; 2632 2633 xbar_amx4_in4: endpoint { 2634 remote-endpoint = <&amx4_in4>; 2635 }; 2636 }; 2637 2638 port@4a { 2639 reg = <0x4a>; 2640 2641 xbar_amx4_out: endpoint { 2642 remote-endpoint = <&amx4_out>; 2643 }; 2644 }; 2645 2646 xbar_amx5_in1_port: port@4b { 2647 reg = <0x4b>; 2648 2649 xbar_amx5_in1: endpoint { 2650 remote-endpoint = <&amx5_in1>; 2651 }; 2652 }; 2653 2654 xbar_amx5_in2_port: port@4c { 2655 reg = <0x4c>; 2656 2657 xbar_amx5_in2: endpoint { 2658 remote-endpoint = <&amx5_in2>; 2659 }; 2660 }; 2661 2662 xbar_amx5_in3_port: port@4d { 2663 reg = <0x4d>; 2664 2665 xbar_amx5_in3: endpoint { 2666 remote-endpoint = <&amx5_in3>; 2667 }; 2668 }; 2669 2670 xbar_amx5_in4_port: port@4e { 2671 reg = <0x4e>; 2672 2673 xbar_amx5_in4: endpoint { 2674 remote-endpoint = <&amx5_in4>; 2675 }; 2676 }; 2677 2678 port@4f { 2679 reg = <0x4f>; 2680 2681 xbar_amx5_out: endpoint { 2682 remote-endpoint = <&amx5_out>; 2683 }; 2684 }; 2685 2686 xbar_amx6_in1_port: port@50 { 2687 reg = <0x50>; 2688 2689 xbar_amx6_in1: endpoint { 2690 remote-endpoint = <&amx6_in1>; 2691 }; 2692 }; 2693 2694 xbar_amx6_in2_port: port@51 { 2695 reg = <0x51>; 2696 2697 xbar_amx6_in2: endpoint { 2698 remote-endpoint = <&amx6_in2>; 2699 }; 2700 }; 2701 2702 xbar_amx6_in3_port: port@52 { 2703 reg = <0x52>; 2704 2705 xbar_amx6_in3: endpoint { 2706 remote-endpoint = <&amx6_in3>; 2707 }; 2708 }; 2709 2710 xbar_amx6_in4_port: port@53 { 2711 reg = <0x53>; 2712 2713 xbar_amx6_in4: endpoint { 2714 remote-endpoint = <&amx6_in4>; 2715 }; 2716 }; 2717 2718 port@54 { 2719 reg = <0x54>; 2720 2721 xbar_amx6_out: endpoint { 2722 remote-endpoint = <&amx6_out>; 2723 }; 2724 }; 2725 2726 xbar_adx1_in_port: port@55 { 2727 reg = <0x55>; 2728 2729 xbar_adx1_in: endpoint { 2730 remote-endpoint = <&adx1_in>; 2731 }; 2732 }; 2733 2734 port@56 { 2735 reg = <0x56>; 2736 2737 xbar_adx1_out1: endpoint { 2738 remote-endpoint = <&adx1_out1>; 2739 }; 2740 }; 2741 2742 port@57 { 2743 reg = <0x57>; 2744 2745 xbar_adx1_out2: endpoint { 2746 remote-endpoint = <&adx1_out2>; 2747 }; 2748 }; 2749 2750 port@58 { 2751 reg = <0x58>; 2752 2753 xbar_adx1_out3: endpoint { 2754 remote-endpoint = <&adx1_out3>; 2755 }; 2756 }; 2757 2758 port@59 { 2759 reg = <0x59>; 2760 2761 xbar_adx1_out4: endpoint { 2762 remote-endpoint = <&adx1_out4>; 2763 }; 2764 }; 2765 2766 xbar_adx2_in_port: port@5a { 2767 reg = <0x5a>; 2768 2769 xbar_adx2_in: endpoint { 2770 remote-endpoint = <&adx2_in>; 2771 }; 2772 }; 2773 2774 port@5b { 2775 reg = <0x5b>; 2776 2777 xbar_adx2_out1: endpoint { 2778 remote-endpoint = <&adx2_out1>; 2779 }; 2780 }; 2781 2782 port@5c { 2783 reg = <0x5c>; 2784 2785 xbar_adx2_out2: endpoint { 2786 remote-endpoint = <&adx2_out2>; 2787 }; 2788 }; 2789 2790 port@5d { 2791 reg = <0x5d>; 2792 2793 xbar_adx2_out3: endpoint { 2794 remote-endpoint = <&adx2_out3>; 2795 }; 2796 }; 2797 2798 port@5e { 2799 reg = <0x5e>; 2800 2801 xbar_adx2_out4: endpoint { 2802 remote-endpoint = <&adx2_out4>; 2803 }; 2804 }; 2805 2806 xbar_adx3_in_port: port@5f { 2807 reg = <0x5f>; 2808 2809 xbar_adx3_in: endpoint { 2810 remote-endpoint = <&adx3_in>; 2811 }; 2812 }; 2813 2814 port@60 { 2815 reg = <0x60>; 2816 2817 xbar_adx3_out1: endpoint { 2818 remote-endpoint = <&adx3_out1>; 2819 }; 2820 }; 2821 2822 port@61 { 2823 reg = <0x61>; 2824 2825 xbar_adx3_out2: endpoint { 2826 remote-endpoint = <&adx3_out2>; 2827 }; 2828 }; 2829 2830 port@62 { 2831 reg = <0x62>; 2832 2833 xbar_adx3_out3: endpoint { 2834 remote-endpoint = <&adx3_out3>; 2835 }; 2836 }; 2837 2838 port@63 { 2839 reg = <0x63>; 2840 2841 xbar_adx3_out4: endpoint { 2842 remote-endpoint = <&adx3_out4>; 2843 }; 2844 }; 2845 2846 xbar_adx4_in_port: port@64 { 2847 reg = <0x64>; 2848 2849 xbar_adx4_in: endpoint { 2850 remote-endpoint = <&adx4_in>; 2851 }; 2852 }; 2853 2854 port@65 { 2855 reg = <0x65>; 2856 2857 xbar_adx4_out1: endpoint { 2858 remote-endpoint = <&adx4_out1>; 2859 }; 2860 }; 2861 2862 port@66 { 2863 reg = <0x66>; 2864 2865 xbar_adx4_out2: endpoint { 2866 remote-endpoint = <&adx4_out2>; 2867 }; 2868 }; 2869 2870 port@67 { 2871 reg = <0x67>; 2872 2873 xbar_adx4_out3: endpoint { 2874 remote-endpoint = <&adx4_out3>; 2875 }; 2876 }; 2877 2878 port@68 { 2879 reg = <0x68>; 2880 2881 xbar_adx4_out4: endpoint { 2882 remote-endpoint = <&adx4_out4>; 2883 }; 2884 }; 2885 2886 xbar_adx5_in_port: port@69 { 2887 reg = <0x69>; 2888 2889 xbar_adx5_in: endpoint { 2890 remote-endpoint = <&adx5_in>; 2891 }; 2892 }; 2893 2894 port@6a { 2895 reg = <0x6a>; 2896 2897 xbar_adx5_out1: endpoint { 2898 remote-endpoint = <&adx5_out1>; 2899 }; 2900 }; 2901 2902 port@6b { 2903 reg = <0x6b>; 2904 2905 xbar_adx5_out2: endpoint { 2906 remote-endpoint = <&adx5_out2>; 2907 }; 2908 }; 2909 2910 port@6c { 2911 reg = <0x6c>; 2912 2913 xbar_adx5_out3: endpoint { 2914 remote-endpoint = <&adx5_out3>; 2915 }; 2916 }; 2917 2918 port@6d { 2919 reg = <0x6d>; 2920 2921 xbar_adx5_out4: endpoint { 2922 remote-endpoint = <&adx5_out4>; 2923 }; 2924 }; 2925 2926 xbar_adx6_in_port: port@6e { 2927 reg = <0x6e>; 2928 2929 xbar_adx6_in: endpoint { 2930 remote-endpoint = <&adx6_in>; 2931 }; 2932 }; 2933 2934 port@6f { 2935 reg = <0x6f>; 2936 2937 xbar_adx6_out1: endpoint { 2938 remote-endpoint = <&adx6_out1>; 2939 }; 2940 }; 2941 2942 port@70 { 2943 reg = <0x70>; 2944 2945 xbar_adx6_out2: endpoint { 2946 remote-endpoint = <&adx6_out2>; 2947 }; 2948 }; 2949 2950 port@71 { 2951 reg = <0x71>; 2952 2953 xbar_adx6_out3: endpoint { 2954 remote-endpoint = <&adx6_out3>; 2955 }; 2956 }; 2957 2958 port@72 { 2959 reg = <0x72>; 2960 2961 xbar_adx6_out4: endpoint { 2962 remote-endpoint = <&adx6_out4>; 2963 }; 2964 }; 2965 2966 xbar_mix_in1_port: port@73 { 2967 reg = <0x73>; 2968 2969 xbar_mix_in1: endpoint { 2970 remote-endpoint = <&mix_in1>; 2971 }; 2972 }; 2973 2974 xbar_mix_in2_port: port@74 { 2975 reg = <0x74>; 2976 2977 xbar_mix_in2: endpoint { 2978 remote-endpoint = <&mix_in2>; 2979 }; 2980 }; 2981 2982 xbar_mix_in3_port: port@75 { 2983 reg = <0x75>; 2984 2985 xbar_mix_in3: endpoint { 2986 remote-endpoint = <&mix_in3>; 2987 }; 2988 }; 2989 2990 xbar_mix_in4_port: port@76 { 2991 reg = <0x76>; 2992 2993 xbar_mix_in4: endpoint { 2994 remote-endpoint = <&mix_in4>; 2995 }; 2996 }; 2997 2998 xbar_mix_in5_port: port@77 { 2999 reg = <0x77>; 3000 3001 xbar_mix_in5: endpoint { 3002 remote-endpoint = <&mix_in5>; 3003 }; 3004 }; 3005 3006 xbar_mix_in6_port: port@78 { 3007 reg = <0x78>; 3008 3009 xbar_mix_in6: endpoint { 3010 remote-endpoint = <&mix_in6>; 3011 }; 3012 }; 3013 3014 xbar_mix_in7_port: port@79 { 3015 reg = <0x79>; 3016 3017 xbar_mix_in7: endpoint { 3018 remote-endpoint = <&mix_in7>; 3019 }; 3020 }; 3021 3022 xbar_mix_in8_port: port@7a { 3023 reg = <0x7a>; 3024 3025 xbar_mix_in8: endpoint { 3026 remote-endpoint = <&mix_in8>; 3027 }; 3028 }; 3029 3030 xbar_mix_in9_port: port@7b { 3031 reg = <0x7b>; 3032 3033 xbar_mix_in9: endpoint { 3034 remote-endpoint = <&mix_in9>; 3035 }; 3036 }; 3037 3038 xbar_mix_in10_port: port@7c { 3039 reg = <0x7c>; 3040 3041 xbar_mix_in10: endpoint { 3042 remote-endpoint = <&mix_in10>; 3043 }; 3044 }; 3045 3046 port@7d { 3047 reg = <0x7d>; 3048 3049 xbar_mix_out1: endpoint { 3050 remote-endpoint = <&mix_out1>; 3051 }; 3052 }; 3053 3054 port@7e { 3055 reg = <0x7e>; 3056 3057 xbar_mix_out2: endpoint { 3058 remote-endpoint = <&mix_out2>; 3059 }; 3060 }; 3061 3062 port@7f { 3063 reg = <0x7f>; 3064 3065 xbar_mix_out3: endpoint { 3066 remote-endpoint = <&mix_out3>; 3067 }; 3068 }; 3069 3070 port@80 { 3071 reg = <0x80>; 3072 3073 xbar_mix_out4: endpoint { 3074 remote-endpoint = <&mix_out4>; 3075 }; 3076 }; 3077 3078 port@81 { 3079 reg = <0x81>; 3080 3081 xbar_mix_out5: endpoint { 3082 remote-endpoint = <&mix_out5>; 3083 }; 3084 }; 3085 3086 xbar_asrc_in1_port: port@82 { 3087 reg = <0x82>; 3088 3089 xbar_asrc_in1_ep: endpoint { 3090 remote-endpoint = <&asrc_in1_ep>; 3091 }; 3092 }; 3093 3094 port@83 { 3095 reg = <0x83>; 3096 3097 xbar_asrc_out1_ep: endpoint { 3098 remote-endpoint = <&asrc_out1_ep>; 3099 }; 3100 }; 3101 3102 xbar_asrc_in2_port: port@84 { 3103 reg = <0x84>; 3104 3105 xbar_asrc_in2_ep: endpoint { 3106 remote-endpoint = <&asrc_in2_ep>; 3107 }; 3108 }; 3109 3110 port@85 { 3111 reg = <0x85>; 3112 3113 xbar_asrc_out2_ep: endpoint { 3114 remote-endpoint = <&asrc_out2_ep>; 3115 }; 3116 }; 3117 3118 xbar_asrc_in3_port: port@86 { 3119 reg = <0x86>; 3120 3121 xbar_asrc_in3_ep: endpoint { 3122 remote-endpoint = <&asrc_in3_ep>; 3123 }; 3124 }; 3125 3126 port@87 { 3127 reg = <0x87>; 3128 3129 xbar_asrc_out3_ep: endpoint { 3130 remote-endpoint = <&asrc_out3_ep>; 3131 }; 3132 }; 3133 3134 xbar_asrc_in4_port: port@88 { 3135 reg = <0x88>; 3136 3137 xbar_asrc_in4_ep: endpoint { 3138 remote-endpoint = <&asrc_in4_ep>; 3139 }; 3140 }; 3141 3142 port@89 { 3143 reg = <0x89>; 3144 3145 xbar_asrc_out4_ep: endpoint { 3146 remote-endpoint = <&asrc_out4_ep>; 3147 }; 3148 }; 3149 3150 xbar_asrc_in5_port: port@8a { 3151 reg = <0x8a>; 3152 3153 xbar_asrc_in5_ep: endpoint { 3154 remote-endpoint = <&asrc_in5_ep>; 3155 }; 3156 }; 3157 3158 port@8b { 3159 reg = <0x8b>; 3160 3161 xbar_asrc_out5_ep: endpoint { 3162 remote-endpoint = <&asrc_out5_ep>; 3163 }; 3164 }; 3165 3166 xbar_asrc_in6_port: port@8c { 3167 reg = <0x8c>; 3168 3169 xbar_asrc_in6_ep: endpoint { 3170 remote-endpoint = <&asrc_in6_ep>; 3171 }; 3172 }; 3173 3174 port@8d { 3175 reg = <0x8d>; 3176 3177 xbar_asrc_out6_ep: endpoint { 3178 remote-endpoint = <&asrc_out6_ep>; 3179 }; 3180 }; 3181 3182 xbar_asrc_in7_port: port@8e { 3183 reg = <0x8e>; 3184 3185 xbar_asrc_in7_ep: endpoint { 3186 remote-endpoint = <&asrc_in7_ep>; 3187 }; 3188 }; 3189 3190 xbar_ope1_in_port: port@8f { 3191 reg = <0x8f>; 3192 3193 xbar_ope1_in_ep: endpoint { 3194 remote-endpoint = <&ope1_cif_in_ep>; 3195 }; 3196 }; 3197 3198 port@90 { 3199 reg = <0x90>; 3200 3201 xbar_ope1_out_ep: endpoint { 3202 remote-endpoint = <&ope1_cif_out_ep>; 3203 }; 3204 }; 3205 }; 3206 }; 3207 3208 agic_page0: interrupt-controller@9960000 { 3209 compatible = "nvidia,tegra264-agic", 3210 "nvidia,tegra210-agic"; 3211 #interrupt-cells = <3>; 3212 interrupt-controller; 3213 reg = <0x9961000 0x1000>, 3214 <0x9962000 0x1000>; 3215 interrupts = <GIC_SPI 0x230 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3216 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3217 clock-names = "clk"; 3218 status = "disabled"; 3219 }; 3220 3221 agic_page1: interrupt-controller@9970000 { 3222 compatible = "nvidia,tegra264-agic", 3223 "nvidia,tegra210-agic"; 3224 #interrupt-cells = <3>; 3225 interrupt-controller; 3226 reg = <0x9971000 0x1000>, 3227 <0x9972000 0x1000>; 3228 interrupts = <GIC_SPI 0x231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3229 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3230 clock-names = "clk"; 3231 status = "disabled"; 3232 }; 3233 3234 agic_page2: interrupt-controller@9980000 { 3235 compatible = "nvidia,tegra264-agic", 3236 "nvidia,tegra210-agic"; 3237 #interrupt-cells = <3>; 3238 interrupt-controller; 3239 reg = <0x9981000 0x1000>, 3240 <0x9982000 0x1000>; 3241 interrupts = <GIC_SPI 0x232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3242 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3243 clock-names = "clk"; 3244 status = "disabled"; 3245 }; 3246 3247 agic_page3: interrupt-controller@9990000 { 3248 compatible = "nvidia,tegra264-agic", 3249 "nvidia,tegra210-agic"; 3250 #interrupt-cells = <3>; 3251 interrupt-controller; 3252 reg = <0x9991000 0x1000>, 3253 <0x9992000 0x1000>; 3254 interrupts = <GIC_SPI 0x233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3255 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3256 clock-names = "clk"; 3257 status = "disabled"; 3258 }; 3259 3260 agic_page4: interrupt-controller@99a0000 { 3261 compatible = "nvidia,tegra264-agic", 3262 "nvidia,tegra210-agic"; 3263 #interrupt-cells = <3>; 3264 interrupt-controller; 3265 reg = <0x99a1000 0x1000>, 3266 <0x99a2000 0x1000>; 3267 interrupts = <GIC_SPI 0x234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3268 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3269 clock-names = "clk"; 3270 status = "disabled"; 3271 }; 3272 3273 agic_page5: interrupt-controller@99b0000 { 3274 compatible = "nvidia,tegra264-agic", 3275 "nvidia,tegra210-agic"; 3276 #interrupt-cells = <3>; 3277 interrupt-controller; 3278 reg = <0x99b1000 0x1000>, 3279 <0x99b2000 0x1000>; 3280 interrupts = <GIC_SPI 0x235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3281 clocks = <&bpmp TEGRA264_CLK_ADSP>; 3282 clock-names = "clk"; 3283 status = "disabled"; 3284 }; 3285 }; 3286 3287 hte_aon: hardware-timestamp@c2b0000 { 3288 compatible = "nvidia,tegra264-gte-aon"; 3289 reg = <0x0 0x0c2b0000 0x0 0x10000>; 3290 interrupts = <GIC_SPI 0x00000226 IRQ_TYPE_LEVEL_HIGH>; 3291 nvidia,int-threshold = <1>; 3292 #timestamp-cells = <1>; 3293 nvidia,gpio-controller = <&gpio_aon>; 3294 status = "disabled"; 3295 }; 3296 3297 rtc: rtc@c2c0000 { 3298 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; 3299 reg = <0x0 0x0c2c0000 0x0 0x10000>; 3300 interrupt-parent = <&pmc>; 3301 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 3302 clocks = <&bpmp TEGRA264_CLK_CLK_S>; 3303 clock-names = "rtc"; 3304 status = "disabled"; 3305 }; 3306 3307 serial@c4e0000 { 3308 compatible = "nvidia,tegra264-utc"; 3309 reg = <0x0 0x0c4e0000 0x0 0x8000>, 3310 <0x0 0x0c4e8000 0x0 0x8000>; 3311 reg-names = "tx", "rx"; 3312 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 3313 rx-threshold = <4>; 3314 tx-threshold = <4>; 3315 status = "disabled"; 3316 }; 3317 3318 serial@c5a0000 { 3319 compatible = "nvidia,tegra264-utc"; 3320 reg = <0x0 0x0c5a0000 0x0 0x8000>, 3321 <0x0 0x0c5a8000 0x0 0x8000>; 3322 reg-names = "tx", "rx"; 3323 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 3324 rx-threshold = <4>; 3325 tx-threshold = <4>; 3326 status = "disabled"; 3327 }; 3328 3329 uart0: serial@c5f0000 { 3330 compatible = "arm,sbsa-uart"; 3331 reg = <0x0 0x0c5f0000 0x0 0x10000>; 3332 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 3333 status = "disabled"; 3334 }; 3335 3336 i2c2: i2c@c600000 { 3337 compatible = "nvidia,tegra264-i2c"; 3338 reg = <0x0 0x0c600000 0x0 0x10000>; 3339 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 3340 #address-cells = <1>; 3341 #size-cells = <0>; 3342 clock-frequency = <400000>; 3343 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 3344 <&bpmp TEGRA264_CLK_PLLAON>; 3345 clock-names = "div-clk", "parent"; 3346 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 3347 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 3348 resets = <&bpmp TEGRA264_RESET_I2C2>; 3349 reset-names = "i2c"; 3350 status = "disabled"; 3351 }; 3352 3353 i2c3: i2c@c610000 { 3354 compatible = "nvidia,tegra264-i2c"; 3355 reg = <0x0 0x0c610000 0x0 0x10000>; 3356 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 3357 #address-cells = <1>; 3358 #size-cells = <0>; 3359 clock-frequency = <400000>; 3360 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 3361 <&bpmp TEGRA264_CLK_PLLAON>; 3362 clock-names = "div-clk", "parent"; 3363 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 3364 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 3365 resets = <&bpmp TEGRA264_RESET_I2C3>; 3366 reset-names = "i2c"; 3367 status = "disabled"; 3368 }; 3369 3370 pwm4: pwm@c6a0000 { 3371 compatible = "nvidia,tegra264-pwm"; 3372 reg = <0x0 0xc6a0000 0x0 0x10000>; 3373 status = "disabled"; 3374 3375 clocks = <&bpmp TEGRA264_CLK_PWM4>; 3376 resets = <&bpmp TEGRA264_RESET_PWM4>; 3377 reset-names = "pwm"; 3378 3379 #pwm-cells = <2>; 3380 }; 3381 3382 pinmux_aon: pinmux@c7a2000 { 3383 compatible = "nvidia,tegra264-pinmux-aon"; 3384 reg = <0x0 0x0c7a2000 0x0 0x2000>; 3385 }; 3386 3387 pmc: pmc@c800000 { 3388 compatible = "nvidia,tegra264-pmc"; 3389 reg = <0x0 0x0c800000 0x0 0x100000>, 3390 <0x0 0x0c990000 0x0 0x10000>, 3391 <0x0 0x0ca00000 0x0 0x10000>, 3392 <0x0 0x0c980000 0x0 0x10000>, 3393 <0x0 0x0c9c0000 0x0 0x40000>; 3394 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 3395 #interrupt-cells = <2>; 3396 interrupt-controller; 3397 }; 3398 3399 gpio_aon: gpio@cf00000 { 3400 compatible = "nvidia,tegra264-gpio-aon"; 3401 reg = <0x0 0x0cf00000 0x0 0x10000>, 3402 <0x0 0x0cf10000 0x0 0x1000>; 3403 reg-names = "security", "gpio"; 3404 wakeup-parent = <&pmc>; 3405 interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; 3409 gpio-controller; 3410 #gpio-cells = <2>; 3411 interrupt-controller; 3412 #interrupt-cells = <2>; 3413 }; 3414 }; 3415 3416 /* TOP_MMIO */ 3417 bus@8100000000 { 3418 compatible = "simple-bus"; 3419 3420 #address-cells = <2>; 3421 #size-cells = <2>; 3422 3423 ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 3424 <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */ 3425 <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 3426 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 3427 3428 smmu1: iommu@5000000 { 3429 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3430 reg = <0x00 0x5000000 0x0 0x200000>; 3431 interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 3432 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; 3433 interrupt-names = "eventq", "gerror"; 3434 status = "disabled"; 3435 3436 #iommu-cells = <1>; 3437 dma-coherent; 3438 nvidia,cmdqv = <&cmdqv1>; 3439 }; 3440 3441 cmdqv1: cmdqv@5200000 { 3442 compatible = "nvidia,tegra264-cmdqv"; 3443 reg = <0x00 0x5200000 0x0 0x830000>; 3444 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 3445 status = "disabled"; 3446 }; 3447 3448 smmu2: iommu@6000000 { 3449 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3450 reg = <0x00 0x6000000 0x0 0x200000>; 3451 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 3452 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 3453 interrupt-names = "eventq", "gerror"; 3454 status = "disabled"; 3455 3456 #iommu-cells = <1>; 3457 dma-coherent; 3458 nvidia,cmdqv = <&cmdqv2>; 3459 }; 3460 3461 cmdqv2: cmdqv@6200000 { 3462 compatible = "nvidia,tegra264-cmdqv"; 3463 reg = <0x00 0x6200000 0x0 0x830000>; 3464 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 3465 status = "disabled"; 3466 }; 3467 3468 mc: memory-controller@8020000 { 3469 compatible = "nvidia,tegra264-mc"; 3470 reg = <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */ 3471 <0x000 0x8040000 0x0 0x20000>, /* MC 0 */ 3472 <0x000 0x8060000 0x0 0x20000>, /* MC 1 */ 3473 <0x000 0x8080000 0x0 0x20000>, /* MC 2 */ 3474 <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */ 3475 <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */ 3476 <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */ 3477 <0x000 0x8100000 0x0 0x20000>, /* MC 6 */ 3478 <0x000 0x8120000 0x0 0x20000>, /* MC 7 */ 3479 <0x000 0x8140000 0x0 0x20000>, /* MC 8 */ 3480 <0x000 0x8160000 0x0 0x20000>, /* MC 9 */ 3481 <0x000 0x8180000 0x0 0x20000>, /* MC 10 */ 3482 <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */ 3483 <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */ 3484 <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */ 3485 <0x000 0x8200000 0x0 0x20000>, /* MC 14 */ 3486 <0x000 0x8220000 0x0 0x20000>; /* MC 15 */ 3487 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", 3488 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", 3489 "ch10", "ch11", "ch12", "ch13", "ch14", 3490 "ch15"; 3491 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 3499 #interconnect-cells = <1>; 3500 3501 #address-cells = <2>; 3502 #size-cells = <2>; 3503 3504 /* limit the DMA range for memory clients to [39:0] */ 3505 dma-ranges = <0x000 0x0 0x000 0x0 0x100 0x0>; 3506 3507 emc: external-memory-controller@8800000 { 3508 compatible = "nvidia,tegra264-emc"; 3509 reg = <0x000 0x8800000 0x0 0x20000>, 3510 <0x000 0x8890000 0x0 0x20000>; 3511 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 3512 clocks = <&bpmp TEGRA264_CLK_EMC>, 3513 <&bpmp TEGRA264_CLK_DBB_UPHY0>; 3514 clock-names = "emc", "dbb"; 3515 3516 #interconnect-cells = <0>; 3517 nvidia,bpmp = <&bpmp>; 3518 }; 3519 }; 3520 3521 smmu0: iommu@a000000 { 3522 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3523 reg = <0x00 0xa000000 0x0 0x200000>; 3524 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 3525 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 3526 interrupt-names = "eventq", "gerror"; 3527 status = "disabled"; 3528 3529 #iommu-cells = <1>; 3530 dma-coherent; 3531 nvidia,cmdqv = <&cmdqv0>; 3532 }; 3533 3534 cmdqv0: cmdqv@a200000 { 3535 compatible = "nvidia,tegra264-cmdqv"; 3536 reg = <0x00 0xa200000 0x0 0x830000>; 3537 interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>; 3538 status = "disabled"; 3539 }; 3540 3541 smmu4: iommu@b000000 { 3542 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 3543 reg = <0x00 0xb000000 0x0 0x200000>; 3544 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 3545 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 3546 interrupt-names = "eventq", "gerror"; 3547 status = "disabled"; 3548 3549 #iommu-cells = <1>; 3550 dma-coherent; 3551 nvidia,cmdqv = <&cmdqv4>; 3552 }; 3553 3554 cmdqv4: cmdqv@b200000 { 3555 compatible = "nvidia,tegra264-cmdqv"; 3556 reg = <0x00 0xb200000 0x0 0x830000>; 3557 interrupts = <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; 3558 status = "disabled"; 3559 }; 3560 3561 pci@c000000 { 3562 compatible = "nvidia,tegra264-pcie"; 3563 reg = <0x00 0x0c000000 0x0 0x00004000>, 3564 <0x00 0x0c004000 0x0 0x00001000>, 3565 <0x00 0x0c005000 0x0 0x00001000>, 3566 <0xd0 0xb0000000 0x0 0x10000000>; 3567 reg-names = "xal", "xtl", "xtl-pri", "ecam"; 3568 #address-cells = <3>; 3569 #size-cells = <2>; 3570 device_type = "pci"; 3571 linux,pci-domain = <0x00>; 3572 #interrupt-cells = <0x1>; 3573 3574 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 3575 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_HIGH>, 3576 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>, 3577 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>, 3578 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>; 3579 3580 iommu-map = <0x0 &smmu2 0x10000 0x10000>; 3581 msi-map = <0x0 &its 0x210000 0x10000>; 3582 dma-coherent; 3583 3584 ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */ 3585 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */ 3586 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 3587 bus-range = <0x0 0xff>; 3588 3589 nvidia,bpmp = <&bpmp 0>; 3590 status = "disabled"; 3591 3592 pcie@0 { 3593 device_type = "pci"; 3594 compatible = "pciclass,0604"; 3595 reg = <0x0 0x0 0x0 0x0 0x0>; 3596 bus-range = <0x01 0xff>; 3597 #address-cells = <3>; 3598 #size-cells = <2>; 3599 ranges; 3600 }; 3601 }; 3602 3603 pinmux_main: pinmux@c281000 { 3604 compatible = "nvidia,tegra264-pinmux-main"; 3605 reg = <0x00 0x0c281000 0x0 0xc000>; 3606 }; 3607 3608 gpio_main: gpio@c300000 { 3609 compatible = "nvidia,tegra264-gpio"; 3610 reg = <0x00 0x0c300000 0x0 0x4000>, 3611 <0x00 0x0c310000 0x0 0x4000>; 3612 reg-names = "security", "gpio"; 3613 wakeup-parent = <&pmc>; 3614 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3646 gpio-controller; 3647 #gpio-cells = <2>; 3648 interrupt-controller; 3649 #interrupt-cells = <2>; 3650 }; 3651 3652 i2c14: i2c@c410000 { 3653 compatible = "nvidia,tegra264-i2c"; 3654 reg = <0x00 0x0c410000 0x0 0x10000>; 3655 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 3656 #address-cells = <1>; 3657 #size-cells = <0>; 3658 clock-frequency = <400000>; 3659 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3660 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3661 clock-names = "div-clk", "parent"; 3662 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3663 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3664 resets = <&bpmp TEGRA264_RESET_I2C14>; 3665 reset-names = "i2c"; 3666 status = "disabled"; 3667 }; 3668 3669 i2c15: i2c@c420000 { 3670 compatible = "nvidia,tegra264-i2c"; 3671 reg = <0x00 0x0c420000 0x0 0x10000>; 3672 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 3673 #address-cells = <1>; 3674 #size-cells = <0>; 3675 clock-frequency = <400000>; 3676 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3677 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3678 clock-names = "div-clk", "parent"; 3679 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3680 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3681 resets = <&bpmp TEGRA264_RESET_I2C15>; 3682 reset-names = "i2c"; 3683 status = "disabled"; 3684 }; 3685 3686 i2c16: i2c@c430000 { 3687 compatible = "nvidia,tegra264-i2c"; 3688 reg = <0x00 0x0c430000 0x0 0x10000>; 3689 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 3690 #address-cells = <1>; 3691 #size-cells = <0>; 3692 clock-frequency = <400000>; 3693 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3694 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3695 clock-names = "div-clk", "parent"; 3696 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3697 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3698 resets = <&bpmp TEGRA264_RESET_I2C16>; 3699 reset-names = "i2c"; 3700 status = "disabled"; 3701 }; 3702 3703 mmc@c570000 { 3704 compatible = "nvidia,tegra264-sdhci", "nvidia,tegra194-sdhci"; 3705 reg = <0x00 0x0c570000 0x0 0x10000>; 3706 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 3707 clocks = <&bpmp TEGRA264_CLK_SDMMC1>, 3708 <&bpmp TEGRA264_CLK_SDMMC_LEGACY_TM>; 3709 clock-names = "sdhci", "tmclk"; 3710 assigned-clocks = <&bpmp TEGRA264_CLK_SDMMC1>, 3711 <&bpmp TEGRA264_CLK_PLLC4_MUXED>; 3712 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLC4_MUXED>, 3713 <&bpmp TEGRA264_CLK_PLLC4_OUT0>; 3714 resets = <&bpmp TEGRA264_RESET_SDMMC1>; 3715 reset-names = "sdhci"; 3716 interconnects = <&mc TEGRA264_MEMORY_CLIENT_SDMMC0R &emc>, 3717 <&mc TEGRA264_MEMORY_CLIENT_SDMMC0W &emc>; 3718 interconnect-names = "dma-mem", "write"; 3719 iommus = <&smmu2 TEGRA264_SID_SDMMC0>; 3720 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 3721 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 3722 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3723 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3724 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3725 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3726 nvidia,default-tap = <0x6>; 3727 nvidia,default-trim = <0x0>; 3728 sd-uhs-sdr12; 3729 sd-uhs-sdr25; 3730 sd-uhs-sdr50; 3731 sd-uhs-sdr104; 3732 mmc-hs200-1_8v; 3733 dma-coherent; 3734 status = "disabled"; 3735 }; 3736 3737 pwm2: pwm@c5e0000 { 3738 compatible = "nvidia,tegra264-pwm"; 3739 reg = <0x0 0xc5e0000 0x0 0x10000>; 3740 status = "disabled"; 3741 3742 clocks = <&bpmp TEGRA264_CLK_PWM2>; 3743 resets = <&bpmp TEGRA264_RESET_PWM2>; 3744 reset-names = "pwm"; 3745 3746 #pwm-cells = <2>; 3747 }; 3748 3749 pwm3: pwm@c5f0000 { 3750 compatible = "nvidia,tegra264-pwm"; 3751 reg = <0x0 0xc5f0000 0x0 0x10000>; 3752 status = "disabled"; 3753 3754 clocks = <&bpmp TEGRA264_CLK_PWM3>; 3755 resets = <&bpmp TEGRA264_RESET_PWM3>; 3756 reset-names = "pwm"; 3757 3758 #pwm-cells = <2>; 3759 }; 3760 3761 pwm5: pwm@c600000 { 3762 compatible = "nvidia,tegra264-pwm"; 3763 reg = <0x0 0xc600000 0x0 0x10000>; 3764 status = "disabled"; 3765 3766 clocks = <&bpmp TEGRA264_CLK_PWM5>; 3767 resets = <&bpmp TEGRA264_RESET_PWM5>; 3768 reset-names = "pwm"; 3769 3770 #pwm-cells = <2>; 3771 }; 3772 3773 pwm9: pwm@c610000 { 3774 compatible = "nvidia,tegra264-pwm"; 3775 reg = <0x0 0xc610000 0x0 0x10000>; 3776 status = "disabled"; 3777 3778 clocks = <&bpmp TEGRA264_CLK_PWM9>; 3779 resets = <&bpmp TEGRA264_RESET_PWM9>; 3780 reset-names = "pwm"; 3781 3782 #pwm-cells = <2>; 3783 }; 3784 3785 pwm10: pwm@c620000 { 3786 compatible = "nvidia,tegra264-pwm"; 3787 reg = <0x0 0xc620000 0x0 0x10000>; 3788 status = "disabled"; 3789 3790 clocks = <&bpmp TEGRA264_CLK_PWM10>; 3791 resets = <&bpmp TEGRA264_RESET_PWM10>; 3792 reset-names = "pwm"; 3793 3794 #pwm-cells = <2>; 3795 }; 3796 3797 i2c0: i2c@c630000 { 3798 compatible = "nvidia,tegra264-i2c"; 3799 reg = <0x00 0x0c630000 0x0 0x10000>; 3800 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3801 #address-cells = <1>; 3802 #size-cells = <0>; 3803 clock-frequency = <400000>; 3804 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3805 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3806 clock-names = "div-clk", "parent"; 3807 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3808 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3809 resets = <&bpmp TEGRA264_RESET_I2C0>; 3810 reset-names = "i2c"; 3811 status = "disabled"; 3812 }; 3813 3814 i2c1: i2c@c640000 { 3815 compatible = "nvidia,tegra264-i2c"; 3816 reg = <0x00 0x0c640000 0x0 0x10000>; 3817 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 3818 #address-cells = <1>; 3819 #size-cells = <0>; 3820 clock-frequency = <400000>; 3821 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3822 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3823 clock-names = "div-clk", "parent"; 3824 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3825 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3826 resets = <&bpmp TEGRA264_RESET_I2C1>; 3827 reset-names = "i2c"; 3828 status = "disabled"; 3829 }; 3830 3831 i2c4: i2c@c650000 { 3832 compatible = "nvidia,tegra264-i2c"; 3833 reg = <0x00 0x0c650000 0x0 0x10000>; 3834 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 3835 #address-cells = <1>; 3836 #size-cells = <0>; 3837 clock-frequency = <400000>; 3838 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3839 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3840 clock-names = "div-clk", "parent"; 3841 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3842 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3843 resets = <&bpmp TEGRA264_RESET_I2C4>; 3844 reset-names = "i2c"; 3845 status = "disabled"; 3846 }; 3847 3848 i2c6: i2c@c670000 { 3849 compatible = "nvidia,tegra264-i2c"; 3850 reg = <0x00 0x0c670000 0x0 0x10000>; 3851 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3852 #address-cells = <1>; 3853 #size-cells = <0>; 3854 clock-frequency = <400000>; 3855 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3856 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3857 clock-names = "div-clk", "parent"; 3858 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3859 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3860 resets = <&bpmp TEGRA264_RESET_I2C6>; 3861 reset-names = "i2c"; 3862 status = "disabled"; 3863 }; 3864 3865 i2c7: i2c@c680000 { 3866 compatible = "nvidia,tegra264-i2c"; 3867 reg = <0x00 0x0c680000 0x0 0x10000>; 3868 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 3869 #address-cells = <1>; 3870 #size-cells = <0>; 3871 clock-frequency = <400000>; 3872 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3873 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3874 clock-names = "div-clk", "parent"; 3875 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3876 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3877 resets = <&bpmp TEGRA264_RESET_I2C7>; 3878 reset-names = "i2c"; 3879 status = "disabled"; 3880 }; 3881 3882 i2c8: i2c@c690000 { 3883 compatible = "nvidia,tegra264-i2c"; 3884 reg = <0x00 0x0c690000 0x0 0x10000>; 3885 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 3886 #address-cells = <1>; 3887 #size-cells = <0>; 3888 clock-frequency = <400000>; 3889 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3890 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3891 clock-names = "div-clk", "parent"; 3892 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3893 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3894 resets = <&bpmp TEGRA264_RESET_I2C8>; 3895 reset-names = "i2c"; 3896 status = "disabled"; 3897 }; 3898 3899 i2c9: i2c@c6a0000 { 3900 compatible = "nvidia,tegra264-i2c"; 3901 reg = <0x00 0x0c6a0000 0x0 0x10000>; 3902 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3903 #address-cells = <1>; 3904 #size-cells = <0>; 3905 clock-frequency = <400000>; 3906 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3907 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3908 clock-names = "div-clk", "parent"; 3909 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3910 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3911 resets = <&bpmp TEGRA264_RESET_I2C9>; 3912 reset-names = "i2c"; 3913 status = "disabled"; 3914 }; 3915 3916 i2c10: i2c@c6b0000 { 3917 compatible = "nvidia,tegra264-i2c"; 3918 reg = <0x00 0x0c6b0000 0x0 0x10000>; 3919 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3920 #address-cells = <1>; 3921 #size-cells = <0>; 3922 clock-frequency = <400000>; 3923 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3924 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3925 clock-names = "div-clk", "parent"; 3926 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3927 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3928 resets = <&bpmp TEGRA264_RESET_I2C10>; 3929 reset-names = "i2c"; 3930 status = "disabled"; 3931 }; 3932 3933 i2c11: i2c@c6c0000 { 3934 compatible = "nvidia,tegra264-i2c"; 3935 reg = <0x00 0x0c6c0000 0x0 0x10000>; 3936 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3937 #address-cells = <1>; 3938 #size-cells = <0>; 3939 clock-frequency = <400000>; 3940 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3941 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3942 clock-names = "div-clk", "parent"; 3943 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3944 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3945 resets = <&bpmp TEGRA264_RESET_I2C11>; 3946 reset-names = "i2c"; 3947 status = "disabled"; 3948 }; 3949 3950 i2c12: i2c@c6d0000 { 3951 compatible = "nvidia,tegra264-i2c"; 3952 reg = <0x00 0x0c6d0000 0x0 0x10000>; 3953 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3954 #address-cells = <1>; 3955 #size-cells = <0>; 3956 clock-frequency = <400000>; 3957 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 3958 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3959 clock-names = "div-clk", "parent"; 3960 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 3961 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 3962 resets = <&bpmp TEGRA264_RESET_I2C12>; 3963 reset-names = "i2c"; 3964 status = "disabled"; 3965 }; 3966 3967 gic: interrupt-controller@46000000 { 3968 compatible = "arm,gic-v3"; 3969 reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ 3970 <0x00 0x46080000 0x0 0x400000>; /* GICR */ 3971 interrupt-parent = <&gic>; 3972 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3973 3974 redistributor-stride = <0x0 0x40000>; 3975 #redistributor-regions = <1>; 3976 #interrupt-cells = <3>; 3977 interrupt-controller; 3978 3979 #address-cells = <2>; 3980 #size-cells = <2>; 3981 3982 ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>; 3983 3984 its: msi-controller@40000 { 3985 compatible = "arm,gic-v3-its"; 3986 reg = <0x0 0x40000 0x0 0x40000>; 3987 #msi-cells = <1>; 3988 msi-controller; 3989 }; 3990 }; 3991 }; 3992 3993 /* VISION MMIO */ 3994 bus@8180000000 { 3995 compatible = "simple-bus"; 3996 #address-cells = <2>; 3997 #size-cells = <2>; 3998 3999 ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */ 4000 <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ 4001 <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 4002 4003 host1x@1200000 { 4004 compatible = "nvidia,tegra264-host1x"; 4005 reg = <0x0 0x1200000 0x0 0x10000>, 4006 <0x0 0x1210000 0x0 0x10000>, 4007 <0x0 0x1240000 0x0 0x10000>; 4008 reg-names = "common", "hypervisor", "vm"; 4009 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 4018 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 4019 "syncpt5", "syncpt6", "syncpt7", "host1x"; 4020 clocks = <&bpmp TEGRA264_CLK_HOST1X>; 4021 clock-names = "host1x"; 4022 4023 #address-cells = <2>; 4024 #size-cells = <2>; 4025 4026 ranges = <0x000 0x00000000 0x00 0x08000000 0x00 0x01000000>, 4027 <0x000 0x02800000 0x00 0x0a800000 0x00 0x00800000>; 4028 4029 interconnects = <&mc TEGRA264_MEMORY_CLIENT_HOST1XR &emc>; 4030 interconnect-names = "dma-mem"; 4031 iommus = <&smmu1 TEGRA264_SID_HOST1X>; 4032 dma-coherent; 4033 4034 /* Context isolation domains */ 4035 iommu-map = <0 &smmu1 (TEGRA264_SID_VIC + 1) 16>; 4036 4037 vic@50000 { 4038 compatible = "nvidia,tegra264-vic"; 4039 reg = <0x0 0x50000 0x0 0x40000>; 4040 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 4041 clocks = <&bpmp TEGRA264_CLK_VIC>; 4042 clock-names = "vic"; 4043 resets = <&bpmp TEGRA264_RESET_VIC>; 4044 reset-names = "vic"; 4045 power-domains = <&bpmp TEGRA264_POWER_DOMAIN_VIC>; 4046 interconnects = <&mc TEGRA264_MEMORY_CLIENT_VICR &emc>, 4047 <&mc TEGRA264_MEMORY_CLIENT_VICW &emc>; 4048 interconnect-names = "dma-mem", "write"; 4049 4050 iommus = <&smmu1 TEGRA264_SID_VIC>; 4051 dma-coherent; 4052 }; 4053 }; 4054 }; 4055 4056 /* DISP_USB MMIO */ 4057 bus@8800000000 { 4058 compatible = "simple-bus"; 4059 #address-cells = <2>; 4060 #size-cells = <2>; 4061 4062 ranges = <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ 4063 4064 smmu3: iommu@6000000 { 4065 compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; 4066 reg = <0x00 0x6000000 0x0 0x200000>; 4067 interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 4068 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; 4069 interrupt-names = "eventq", "gerror"; 4070 status = "disabled"; 4071 4072 #iommu-cells = <1>; 4073 dma-coherent; 4074 nvidia,cmdqv = <&cmdqv3>; 4075 }; 4076 4077 cmdqv3: cmdqv@6200000 { 4078 compatible = "nvidia,tegra264-cmdqv"; 4079 reg = <0x00 0x6200000 0x0 0x830000>; 4080 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>; 4081 status = "disabled"; 4082 }; 4083 4084 hda@90b0000 { 4085 compatible = "nvidia,tegra264-hda"; 4086 reg = <0x0 0x90b0000 0x0 0x10000>; 4087 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 4088 clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; 4089 clock-names = "hda"; 4090 resets = <&bpmp TEGRA264_RESET_HDA>, 4091 <&bpmp TEGRA264_RESET_HDACODEC>; 4092 reset-names = "hda", "hda2codec_2x"; 4093 interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, 4094 <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; 4095 interconnect-names = "dma-mem", "write"; 4096 iommus = <&smmu3 TEGRA264_SID_HDA>; 4097 status = "disabled"; 4098 }; 4099 }; 4100 4101 /* UPHY MMIO */ 4102 bus@a800000000 { 4103 compatible = "simple-bus"; 4104 #address-cells = <2>; 4105 #size-cells = <2>; 4106 4107 ranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ 4108 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */ 4109 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ 4110 4111 pinmux_uphy: pinmux@82e0000 { 4112 compatible = "nvidia,tegra264-pinmux-uphy"; 4113 reg = <0x00 0x082e0000 0x0 0x4000>; 4114 }; 4115 4116 gpio_uphy: gpio@8300000 { 4117 compatible = "nvidia,tegra264-gpio-uphy"; 4118 reg = <0x00 0x08300000 0x0 0x2000>, 4119 <0x00 0x08310000 0x0 0x2000>; 4120 reg-names = "security", "gpio"; 4121 wakeup-parent = <&pmc>; 4122 interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 4138 gpio-controller; 4139 #gpio-cells = <2>; 4140 interrupt-controller; 4141 #interrupt-cells = <2>; 4142 }; 4143 4144 pci@8400000 { 4145 compatible = "nvidia,tegra264-pcie"; 4146 reg = <0x00 0x08400000 0x0 0x00004000>, 4147 <0x00 0x08404000 0x0 0x00001000>, 4148 <0x00 0x08405000 0x0 0x00001000>, 4149 <0x00 0x08410000 0x0 0x00010000>, 4150 <0xa8 0xb0000000 0x0 0x10000000>; 4151 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4152 #address-cells = <3>; 4153 #size-cells = <2>; 4154 device_type = "pci"; 4155 linux,pci-domain = <0x01>; 4156 #interrupt-cells = <1>; 4157 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4158 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4159 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4160 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4161 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4162 4163 iommu-map = <0x0 &smmu1 0x10000 0x10000>; 4164 msi-map = <0x0 &its 0x110000 0x10000>; 4165 dma-coherent; 4166 4167 ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */ 4168 <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */ 4169 <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4170 bus-range = <0x00 0xff>; 4171 4172 nvidia,bpmp = <&bpmp 1>; 4173 status = "disabled"; 4174 4175 pcie@0 { 4176 device_type = "pci"; 4177 compatible = "pciclass,0604"; 4178 reg = <0x0 0x0 0x0 0x0 0x0>; 4179 bus-range = <0x01 0xff>; 4180 #address-cells = <3>; 4181 #size-cells = <2>; 4182 ranges; 4183 }; 4184 }; 4185 4186 pci@8420000 { 4187 compatible = "nvidia,tegra264-pcie"; 4188 reg = <0x00 0x08420000 0x0 0x00004000>, 4189 <0x00 0x08424000 0x0 0x00001000>, 4190 <0x00 0x08425000 0x0 0x00001000>, 4191 <0x00 0x08430000 0x0 0x00010000>, 4192 <0xb0 0xb0000000 0x0 0x10000000>; 4193 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4194 #address-cells = <3>; 4195 #size-cells = <2>; 4196 device_type = "pci"; 4197 linux,pci-domain = <0x02>; 4198 #interrupt-cells = <1>; 4199 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4200 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4201 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4202 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4203 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4204 4205 iommu-map = <0x0 &smmu1 0x20000 0x10000>; 4206 msi-map = <0x0 &its 0x120000 0x10000>; 4207 dma-coherent; 4208 4209 ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */ 4210 <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */ 4211 <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4212 bus-range = <0x00 0xff>; 4213 4214 nvidia,bpmp = <&bpmp 2>; 4215 status = "disabled"; 4216 4217 pcie@0 { 4218 device_type = "pci"; 4219 compatible = "pciclass,0604"; 4220 reg = <0x0 0x0 0x0 0x0 0x0>; 4221 bus-range = <0x01 0xff>; 4222 #address-cells = <3>; 4223 #size-cells = <2>; 4224 ranges; 4225 }; 4226 }; 4227 4228 pci@8440000 { 4229 compatible = "nvidia,tegra264-pcie"; 4230 reg = <0x00 0x08440000 0x0 0x00004000>, 4231 <0x00 0x08444000 0x0 0x00001000>, 4232 <0x00 0x08445000 0x0 0x00001000>, 4233 <0x00 0x08450000 0x0 0x00010000>, 4234 <0xb8 0xb0000000 0x0 0x10000000>; 4235 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4236 #address-cells = <3>; 4237 #size-cells = <2>; 4238 device_type = "pci"; 4239 linux,pci-domain = <0x03>; 4240 #interrupt-cells = <1>; 4241 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4242 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4243 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4244 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4245 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4246 4247 iommu-map = <0x0 &smmu1 0x30000 0x10000>; 4248 msi-map = <0x0 &its 0x130000 0x10000>; 4249 dma-coherent; 4250 4251 ranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */ 4252 <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */ 4253 <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4254 bus-range = <0x00 0xff>; 4255 4256 nvidia,bpmp = <&bpmp 3>; 4257 status = "disabled"; 4258 4259 pcie@0 { 4260 device_type = "pci"; 4261 compatible = "pciclass,0604"; 4262 reg = <0x0 0x0 0x0 0x0 0x0>; 4263 bus-range = <0x01 0xff>; 4264 #address-cells = <3>; 4265 #size-cells = <2>; 4266 ranges; 4267 }; 4268 }; 4269 4270 pci@8460000 { 4271 compatible = "nvidia,tegra264-pcie"; 4272 reg = <0x00 0x08460000 0x0 0x00004000>, 4273 <0x00 0x08464000 0x0 0x00001000>, 4274 <0x00 0x08465000 0x0 0x00001000>, 4275 <0x00 0x08470000 0x0 0x00010000>, 4276 <0xc0 0xb0000000 0x0 0x10000000>; 4277 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4278 #address-cells = <3>; 4279 #size-cells = <2>; 4280 device_type = "pci"; 4281 linux,pci-domain = <0x04>; 4282 #interrupt-cells = <1>; 4283 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4284 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4285 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4286 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4287 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4288 4289 iommu-map = <0x0 &smmu1 0x40000 0x10000>; 4290 msi-map = <0x0 &its 0x140000 0x10000>; 4291 dma-coherent; 4292 4293 ranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */ 4294 <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */ 4295 <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4296 bus-range = <0x00 0xff>; 4297 4298 nvidia,bpmp = <&bpmp 4>; 4299 status = "disabled"; 4300 4301 pcie@0 { 4302 device_type = "pci"; 4303 compatible = "pciclass,0604"; 4304 reg = <0x0 0x0 0x0 0x0 0x0>; 4305 bus-range = <0x01 0xff>; 4306 #address-cells = <3>; 4307 #size-cells = <2>; 4308 ranges; 4309 }; 4310 }; 4311 4312 pci@8480000 { 4313 compatible = "nvidia,tegra264-pcie"; 4314 reg = <0x00 0x08480000 0x0 0x00004000>, 4315 <0x00 0x08484000 0x0 0x00001000>, 4316 <0x00 0x08485000 0x0 0x00001000>, 4317 <0x00 0x08490000 0x0 0x00010000>, 4318 <0xc8 0xb0000000 0x0 0x10000000>; 4319 reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; 4320 #address-cells = <3>; 4321 #size-cells = <2>; 4322 device_type = "pci"; 4323 linux,pci-domain = <0x05>; 4324 #interrupt-cells = <1>; 4325 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4326 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ 4327 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ 4328 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ 4329 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ 4330 4331 iommu-map = <0x0 &smmu1 0x50000 0x10000>; 4332 msi-map = <0x0 &its 0x150000 0x10000>; 4333 dma-coherent; 4334 4335 ranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */ 4336 <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */ 4337 <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ 4338 bus-range = <0x00 0xff>; 4339 4340 nvidia,bpmp = <&bpmp 5>; 4341 status = "disabled"; 4342 4343 pcie@0 { 4344 device_type = "pci"; 4345 compatible = "pciclass,0604"; 4346 reg = <0x0 0x0 0x0 0x0 0x0>; 4347 bus-range = <0x01 0xff>; 4348 #address-cells = <3>; 4349 #size-cells = <2>; 4350 ranges; 4351 }; 4352 }; 4353 }; 4354 4355 bpmp: bpmp { 4356 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; 4357 mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB 4358 TEGRA_HSP_DB_MASTER_BPMP>; 4359 memory-region = <&shmem_bpmp>; 4360 #clock-cells = <1>; 4361 #reset-cells = <1>; 4362 #power-domain-cells = <1>; 4363 4364 i2c { 4365 compatible = "nvidia,tegra186-bpmp-i2c"; 4366 nvidia,bpmp-bus-id = <5>; 4367 #address-cells = <1>; 4368 #size-cells = <0>; 4369 }; 4370 4371 thermal { 4372 compatible = "nvidia,tegra186-bpmp-thermal"; 4373 #thermal-sensor-cells = <1>; 4374 }; 4375 }; 4376 4377 cpus { 4378 #address-cells = <1>; 4379 #size-cells = <0>; 4380 4381 cpu0: cpu@0 { 4382 compatible = "arm,neoverse-v3ae"; 4383 device_type = "cpu"; 4384 reg = <0x00000>; 4385 4386 enable-method = "psci"; 4387 4388 i-cache-size = <65536>; 4389 i-cache-line-size = <64>; 4390 i-cache-sets = <256>; 4391 d-cache-size = <65536>; 4392 d-cache-line-size = <64>; 4393 d-cache-sets = <256>; 4394 next-level-cache = <&l2c0>; 4395 }; 4396 4397 cpu1: cpu@10000 { 4398 compatible = "arm,neoverse-v3ae"; 4399 device_type = "cpu"; 4400 reg = <0x10000>; 4401 4402 enable-method = "psci"; 4403 4404 i-cache-size = <65536>; 4405 i-cache-line-size = <64>; 4406 i-cache-sets = <256>; 4407 d-cache-size = <65536>; 4408 d-cache-line-size = <64>; 4409 d-cache-sets = <256>; 4410 next-level-cache = <&l2c1>; 4411 }; 4412 4413 cpu2: cpu@20000 { 4414 compatible = "arm,neoverse-v3ae"; 4415 device_type = "cpu"; 4416 reg = <0x20000>; 4417 4418 enable-method = "psci"; 4419 4420 i-cache-size = <65536>; 4421 i-cache-line-size = <64>; 4422 i-cache-sets = <256>; 4423 d-cache-size = <65536>; 4424 d-cache-line-size = <64>; 4425 d-cache-sets = <256>; 4426 next-level-cache = <&l2c2>; 4427 }; 4428 4429 cpu3: cpu@30000 { 4430 compatible = "arm,neoverse-v3ae"; 4431 device_type = "cpu"; 4432 reg = <0x30000>; 4433 4434 enable-method = "psci"; 4435 4436 i-cache-size = <65536>; 4437 i-cache-line-size = <64>; 4438 i-cache-sets = <256>; 4439 d-cache-size = <65536>; 4440 d-cache-line-size = <64>; 4441 d-cache-sets = <256>; 4442 next-level-cache = <&l2c3>; 4443 }; 4444 4445 cpu4: cpu@40000 { 4446 compatible = "arm,neoverse-v3ae"; 4447 device_type = "cpu"; 4448 reg = <0x40000>; 4449 4450 enable-method = "psci"; 4451 4452 i-cache-size = <65536>; 4453 i-cache-line-size = <64>; 4454 i-cache-sets = <256>; 4455 d-cache-size = <65536>; 4456 d-cache-line-size = <64>; 4457 d-cache-sets = <256>; 4458 next-level-cache = <&l2c4>; 4459 }; 4460 4461 cpu5: cpu@50000 { 4462 compatible = "arm,neoverse-v3ae"; 4463 device_type = "cpu"; 4464 reg = <0x50000>; 4465 4466 enable-method = "psci"; 4467 4468 i-cache-size = <65536>; 4469 i-cache-line-size = <64>; 4470 i-cache-sets = <256>; 4471 d-cache-size = <65536>; 4472 d-cache-line-size = <64>; 4473 d-cache-sets = <256>; 4474 next-level-cache = <&l2c5>; 4475 }; 4476 4477 cpu6: cpu@60000 { 4478 compatible = "arm,neoverse-v3ae"; 4479 device_type = "cpu"; 4480 reg = <0x60000>; 4481 4482 enable-method = "psci"; 4483 4484 i-cache-size = <65536>; 4485 i-cache-line-size = <64>; 4486 i-cache-sets = <256>; 4487 d-cache-size = <65536>; 4488 d-cache-line-size = <64>; 4489 d-cache-sets = <256>; 4490 next-level-cache = <&l2c6>; 4491 }; 4492 4493 cpu7: cpu@70000 { 4494 compatible = "arm,neoverse-v3ae"; 4495 device_type = "cpu"; 4496 reg = <0x70000>; 4497 4498 enable-method = "psci"; 4499 4500 i-cache-size = <65536>; 4501 i-cache-line-size = <64>; 4502 i-cache-sets = <256>; 4503 d-cache-size = <65536>; 4504 d-cache-line-size = <64>; 4505 d-cache-sets = <256>; 4506 next-level-cache = <&l2c7>; 4507 }; 4508 4509 cpu8: cpu@80000 { 4510 compatible = "arm,neoverse-v3ae"; 4511 device_type = "cpu"; 4512 reg = <0x80000>; 4513 4514 enable-method = "psci"; 4515 4516 i-cache-size = <65536>; 4517 i-cache-line-size = <64>; 4518 i-cache-sets = <256>; 4519 d-cache-size = <65536>; 4520 d-cache-line-size = <64>; 4521 d-cache-sets = <256>; 4522 next-level-cache = <&l2c8>; 4523 }; 4524 4525 cpu9: cpu@90000 { 4526 compatible = "arm,neoverse-v3ae"; 4527 device_type = "cpu"; 4528 reg = <0x90000>; 4529 4530 enable-method = "psci"; 4531 4532 i-cache-size = <65536>; 4533 i-cache-line-size = <64>; 4534 i-cache-sets = <256>; 4535 d-cache-size = <65536>; 4536 d-cache-line-size = <64>; 4537 d-cache-sets = <256>; 4538 next-level-cache = <&l2c9>; 4539 }; 4540 4541 cpu10: cpu@a0000 { 4542 compatible = "arm,neoverse-v3ae"; 4543 device_type = "cpu"; 4544 reg = <0xa0000>; 4545 4546 enable-method = "psci"; 4547 4548 i-cache-size = <65536>; 4549 i-cache-line-size = <64>; 4550 i-cache-sets = <256>; 4551 d-cache-size = <65536>; 4552 d-cache-line-size = <64>; 4553 d-cache-sets = <256>; 4554 next-level-cache = <&l2c10>; 4555 }; 4556 4557 cpu11: cpu@b0000 { 4558 compatible = "arm,neoverse-v3ae"; 4559 device_type = "cpu"; 4560 reg = <0xb0000>; 4561 4562 enable-method = "psci"; 4563 4564 i-cache-size = <65536>; 4565 i-cache-line-size = <64>; 4566 i-cache-sets = <256>; 4567 d-cache-size = <65536>; 4568 d-cache-line-size = <64>; 4569 d-cache-sets = <256>; 4570 next-level-cache = <&l2c11>; 4571 }; 4572 4573 cpu12: cpu@c0000 { 4574 compatible = "arm,neoverse-v3ae"; 4575 device_type = "cpu"; 4576 reg = <0xc0000>; 4577 4578 enable-method = "psci"; 4579 4580 i-cache-size = <65536>; 4581 i-cache-line-size = <64>; 4582 i-cache-sets = <256>; 4583 d-cache-size = <65536>; 4584 d-cache-line-size = <64>; 4585 d-cache-sets = <256>; 4586 next-level-cache = <&l2c12>; 4587 }; 4588 4589 cpu13: cpu@d0000 { 4590 compatible = "arm,neoverse-v3ae"; 4591 device_type = "cpu"; 4592 reg = <0xd0000>; 4593 4594 enable-method = "psci"; 4595 4596 i-cache-size = <65536>; 4597 i-cache-line-size = <64>; 4598 i-cache-sets = <256>; 4599 d-cache-size = <65536>; 4600 d-cache-line-size = <64>; 4601 d-cache-sets = <256>; 4602 next-level-cache = <&l2c13>; 4603 }; 4604 4605 l2c0: l2-cache-0 { 4606 compatible = "cache"; 4607 cache-level = <2>; 4608 cache-size = <1048576>; 4609 cache-line-size = <64>; 4610 cache-sets = <2048>; 4611 cache-unified; 4612 }; 4613 4614 l2c1: l2-cache-1 { 4615 compatible = "cache"; 4616 cache-level = <2>; 4617 cache-size = <1048576>; 4618 cache-line-size = <64>; 4619 cache-sets = <2048>; 4620 cache-unified; 4621 }; 4622 4623 l2c2: l2-cache-2 { 4624 compatible = "cache"; 4625 cache-level = <2>; 4626 cache-size = <1048576>; 4627 cache-line-size = <64>; 4628 cache-sets = <2048>; 4629 cache-unified; 4630 }; 4631 4632 l2c3: l2-cache-3 { 4633 compatible = "cache"; 4634 cache-level = <2>; 4635 cache-size = <1048576>; 4636 cache-line-size = <64>; 4637 cache-sets = <2048>; 4638 cache-unified; 4639 }; 4640 4641 l2c4: l2-cache-4 { 4642 compatible = "cache"; 4643 cache-level = <2>; 4644 cache-size = <1048576>; 4645 cache-line-size = <64>; 4646 cache-sets = <2048>; 4647 cache-unified; 4648 }; 4649 4650 l2c5: l2-cache-5 { 4651 compatible = "cache"; 4652 cache-level = <2>; 4653 cache-size = <1048576>; 4654 cache-line-size = <64>; 4655 cache-sets = <2048>; 4656 cache-unified; 4657 }; 4658 4659 l2c6: l2-cache-6 { 4660 compatible = "cache"; 4661 cache-level = <2>; 4662 cache-size = <1048576>; 4663 cache-line-size = <64>; 4664 cache-sets = <2048>; 4665 cache-unified; 4666 }; 4667 4668 l2c7: l2-cache-7 { 4669 compatible = "cache"; 4670 cache-level = <2>; 4671 cache-size = <1048576>; 4672 cache-line-size = <64>; 4673 cache-sets = <2048>; 4674 cache-unified; 4675 }; 4676 4677 l2c8: l2-cache-8 { 4678 compatible = "cache"; 4679 cache-level = <2>; 4680 cache-size = <1048576>; 4681 cache-line-size = <64>; 4682 cache-sets = <2048>; 4683 cache-unified; 4684 }; 4685 4686 l2c9: l2-cache-9 { 4687 compatible = "cache"; 4688 cache-level = <2>; 4689 cache-size = <1048576>; 4690 cache-line-size = <64>; 4691 cache-sets = <2048>; 4692 cache-unified; 4693 }; 4694 4695 l2c10: l2-cache-10 { 4696 compatible = "cache"; 4697 cache-level = <2>; 4698 cache-size = <1048576>; 4699 cache-line-size = <64>; 4700 cache-sets = <2048>; 4701 cache-unified; 4702 }; 4703 4704 l2c11: l2-cache-11 { 4705 compatible = "cache"; 4706 cache-level = <2>; 4707 cache-size = <1048576>; 4708 cache-line-size = <64>; 4709 cache-sets = <2048>; 4710 cache-unified; 4711 }; 4712 4713 l2c12: l2-cache-12 { 4714 compatible = "cache"; 4715 cache-level = <2>; 4716 cache-size = <1048576>; 4717 cache-line-size = <64>; 4718 cache-sets = <2048>; 4719 cache-unified; 4720 }; 4721 4722 l2c13: l2-cache-13 { 4723 compatible = "cache"; 4724 cache-level = <2>; 4725 cache-size = <1048576>; 4726 cache-line-size = <64>; 4727 cache-sets = <2048>; 4728 cache-unified; 4729 }; 4730 4731 }; 4732 4733 pmu { 4734 compatible = "arm,armv8-pmuv3"; 4735 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 4736 }; 4737 4738 psci { 4739 compatible = "arm,psci-1.0"; 4740 method = "smc"; 4741 }; 4742 4743 sound { 4744 compatible = "nvidia,tegra264-audio-graph-card"; 4745 4746 clocks = <&bpmp TEGRA264_CLK_PLLA1>, 4747 <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 4748 clock-names = "pll_a", "plla_out0"; 4749 assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>, 4750 <&bpmp TEGRA264_CLK_PLLA1_OUT1>, 4751 <&bpmp TEGRA264_CLK_AUD_MCLK>; 4752 assigned-clock-parents = <0>, 4753 <&bpmp TEGRA264_CLK_PLLA1>, 4754 <&bpmp TEGRA264_CLK_PLLA1_OUT1>; 4755 4756 status = "disabled"; 4757 }; 4758 4759 thermal-zones { 4760 cpu-thermal { 4761 thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_CPU_MAX>; 4762 status = "disabled"; 4763 }; 4764 4765 gpu-thermal { 4766 thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_GPU_MAX>; 4767 status = "disabled"; 4768 }; 4769 4770 soc012-thermal { 4771 thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_012_MAX>; 4772 status = "disabled"; 4773 }; 4774 4775 soc345-thermal { 4776 thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_345_MAX>; 4777 status = "disabled"; 4778 }; 4779 4780 tj-thermal { 4781 thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_TJ_MAX>; 4782 status = "disabled"; 4783 }; 4784 }; 4785 4786 timer { 4787 compatible = "arm,armv8-timer"; 4788 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4789 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4790 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4791 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 4792 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 4793 }; 4794}; 4795