1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "imu_v12_0.h"
33 #include "soc24.h"
34 #include "nvd.h"
35
36 #include "gc/gc_12_0_0_offset.h"
37 #include "gc/gc_12_0_0_sh_mask.h"
38 #include "soc24_enum.h"
39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
40
41 #include "soc15.h"
42 #include "clearstate_gfx12.h"
43 #include "v12_structs.h"
44 #include "gfx_v12_0.h"
45 #include "nbif_v6_3_1.h"
46 #include "mes_v12_0.h"
47 #include "mes_userqueue.h"
48 #include "amdgpu_userq_fence.h"
49
50 #define GFX12_NUM_GFX_RINGS 1
51 #define GFX12_MEC_HPD_SIZE 2048
52
53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
54
55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
62
63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100
66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
71
72
73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");
77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");
78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");
83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
84
85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
139 /* cp header registers */
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
148 /* SE status registers */
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
153 };
154
155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
156 /* compute registers */
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
196 /* cp header registers */
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
205 };
206
207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
208 /* gfx queue registers */
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
234 /* cp header registers */
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
251 };
252
253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
257 };
258
259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
261 };
262
263 #define DEFAULT_SH_MEM_CONFIG \
264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
267
268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
275 struct amdgpu_cu_info *cu_info);
276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
278 u32 sh_num, u32 instance, int xcc_id);
279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
280
281 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
282 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
283 uint32_t val);
284 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
285 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
286 uint16_t pasid, uint32_t flush_type,
287 bool all_hub, uint8_t dst_sel);
288 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
289 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
291 bool enable);
292
gfx_v12_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
294 uint64_t queue_mask)
295 {
296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
304 amdgpu_ring_write(kiq_ring, 0);
305 }
306
gfx_v12_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
308 struct amdgpu_ring *ring)
309 {
310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
311 uint64_t wptr_addr = ring->wptr_gpu_addr;
312 uint32_t me = 0, eng_sel = 0;
313
314 switch (ring->funcs->type) {
315 case AMDGPU_RING_TYPE_COMPUTE:
316 me = 1;
317 eng_sel = 0;
318 break;
319 case AMDGPU_RING_TYPE_GFX:
320 me = 0;
321 eng_sel = 4;
322 break;
323 case AMDGPU_RING_TYPE_MES:
324 me = 2;
325 eng_sel = 5;
326 break;
327 default:
328 WARN_ON(1);
329 }
330
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
338 PACKET3_MAP_QUEUES_ME((me)) |
339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
348 }
349
gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
351 struct amdgpu_ring *ring,
352 enum amdgpu_unmap_queues_action action,
353 u64 gpu_addr, u64 seq)
354 {
355 struct amdgpu_device *adev = kiq_ring->adev;
356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
357
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
360 return;
361 }
362
363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
365 PACKET3_UNMAP_QUEUES_ACTION(action) |
366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
369 amdgpu_ring_write(kiq_ring,
370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
371
372 if (action == PREEMPT_QUEUES_NO_UNMAP) {
373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
375 amdgpu_ring_write(kiq_ring, seq);
376 } else {
377 amdgpu_ring_write(kiq_ring, 0);
378 amdgpu_ring_write(kiq_ring, 0);
379 amdgpu_ring_write(kiq_ring, 0);
380 }
381 }
382
gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
384 struct amdgpu_ring *ring,
385 u64 addr, u64 seq)
386 {
387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
388
389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
390 amdgpu_ring_write(kiq_ring,
391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
393 PACKET3_QUERY_STATUS_COMMAND(2));
394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
401 }
402
gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
404 uint16_t pasid,
405 uint32_t flush_type,
406 bool all_hub)
407 {
408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
409 }
410
411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {
412 .kiq_set_resources = gfx_v12_0_kiq_set_resources,
413 .kiq_map_queues = gfx_v12_0_kiq_map_queues,
414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,
415 .kiq_query_status = gfx_v12_0_kiq_query_status,
416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,
417 .set_resources_size = 8,
418 .map_queues_size = 7,
419 .unmap_queues_size = 6,
420 .query_status_size = 7,
421 .invalidate_tlbs_size = 2,
422 };
423
gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
425 {
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs;
427 }
428
gfx_v12_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref,
432 uint32_t mask, uint32_t inv)
433 {
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436 /* memory (1) or register (0) */
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) | /* wait */
439 WAIT_REG_MEM_FUNCTION(3) | /* equal */
440 WAIT_REG_MEM_ENGINE(eng_sel)));
441
442 if (mem_space)
443 BUG_ON(addr0 & 0x3); /* Dword align */
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv); /* poll interval */
449 }
450
gfx_v12_0_ring_test_ring(struct amdgpu_ring * ring)451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
452 {
453 struct amdgpu_device *adev = ring->adev;
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
455 uint32_t tmp = 0;
456 unsigned i;
457 int r;
458
459 WREG32(scratch, 0xCAFEDEAD);
460 r = amdgpu_ring_alloc(ring, 5);
461 if (r) {
462 dev_err(adev->dev,
463 "amdgpu: cp failed to lock ring %d (%d).\n",
464 ring->idx, r);
465 return r;
466 }
467
468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
470 } else {
471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
472 amdgpu_ring_write(ring, scratch -
473 PACKET3_SET_UCONFIG_REG_START);
474 amdgpu_ring_write(ring, 0xDEADBEEF);
475 }
476 amdgpu_ring_commit(ring);
477
478 for (i = 0; i < adev->usec_timeout; i++) {
479 tmp = RREG32(scratch);
480 if (tmp == 0xDEADBEEF)
481 break;
482 if (amdgpu_emu_mode == 1)
483 msleep(1);
484 else
485 udelay(1);
486 }
487
488 if (i >= adev->usec_timeout)
489 r = -ETIMEDOUT;
490 return r;
491 }
492
gfx_v12_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
494 {
495 struct amdgpu_device *adev = ring->adev;
496 struct amdgpu_ib ib;
497 struct dma_fence *f = NULL;
498 unsigned index;
499 uint64_t gpu_addr;
500 uint32_t *cpu_ptr;
501 long r;
502
503 /* MES KIQ fw hasn't indirect buffer support for now */
504 if (adev->enable_mes_kiq &&
505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
506 return 0;
507
508 memset(&ib, 0, sizeof(ib));
509
510 r = amdgpu_device_wb_get(adev, &index);
511 if (r)
512 return r;
513
514 gpu_addr = adev->wb.gpu_addr + (index * 4);
515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
516 cpu_ptr = &adev->wb.wb[index];
517
518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
519 if (r) {
520 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r);
521 goto err1;
522 }
523
524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
526 ib.ptr[2] = lower_32_bits(gpu_addr);
527 ib.ptr[3] = upper_32_bits(gpu_addr);
528 ib.ptr[4] = 0xDEADBEEF;
529 ib.length_dw = 5;
530
531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
532 if (r)
533 goto err2;
534
535 r = dma_fence_wait_timeout(f, false, timeout);
536 if (r == 0) {
537 r = -ETIMEDOUT;
538 goto err2;
539 } else if (r < 0) {
540 goto err2;
541 }
542
543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
544 r = 0;
545 else
546 r = -EINVAL;
547 err2:
548 amdgpu_ib_free(&ib, NULL);
549 dma_fence_put(f);
550 err1:
551 amdgpu_device_wb_free(adev, index);
552 return r;
553 }
554
gfx_v12_0_free_microcode(struct amdgpu_device * adev)555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)
556 {
557 amdgpu_ucode_release(&adev->gfx.pfp_fw);
558 amdgpu_ucode_release(&adev->gfx.me_fw);
559 amdgpu_ucode_release(&adev->gfx.rlc_fw);
560 amdgpu_ucode_release(&adev->gfx.mec_fw);
561
562 kfree(adev->gfx.rlc.register_list_format);
563 }
564
gfx_v12_0_init_toc_microcode(struct amdgpu_device * adev,const char * ucode_prefix)565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
566 {
567 const struct psp_firmware_header_v1_0 *toc_hdr;
568 int err = 0;
569
570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
571 AMDGPU_UCODE_REQUIRED,
572 "amdgpu/%s_toc.bin", ucode_prefix);
573 if (err)
574 goto out;
575
576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
582 return 0;
583 out:
584 amdgpu_ucode_release(&adev->psp.toc_fw);
585 return err;
586 }
587
gfx_v12_0_init_microcode(struct amdgpu_device * adev)588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
589 {
590 char ucode_prefix[30];
591 int err;
592 const struct rlc_firmware_header_v2_0 *rlc_hdr;
593 uint16_t version_major;
594 uint16_t version_minor;
595
596 DRM_DEBUG("\n");
597
598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
599
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
601 AMDGPU_UCODE_REQUIRED,
602 "amdgpu/%s_pfp.bin", ucode_prefix);
603 if (err)
604 goto out;
605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
607
608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
609 AMDGPU_UCODE_REQUIRED,
610 "amdgpu/%s_me.bin", ucode_prefix);
611 if (err)
612 goto out;
613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
615
616 if (!amdgpu_sriov_vf(adev)) {
617 if (amdgpu_is_kicker_fw(adev))
618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
619 AMDGPU_UCODE_REQUIRED,
620 "amdgpu/%s_rlc_kicker.bin", ucode_prefix);
621 else
622 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
623 AMDGPU_UCODE_REQUIRED,
624 "amdgpu/%s_rlc.bin", ucode_prefix);
625 if (err)
626 goto out;
627 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
628 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
629 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
630 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
631 if (err)
632 goto out;
633 }
634
635 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
636 AMDGPU_UCODE_REQUIRED,
637 "amdgpu/%s_mec.bin", ucode_prefix);
638 if (err)
639 goto out;
640 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
643
644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
645 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);
646
647 /* only one MEC for gfx 12 */
648 adev->gfx.mec2_fw = NULL;
649
650 if (adev->gfx.imu.funcs) {
651 if (adev->gfx.imu.funcs->init_microcode) {
652 err = adev->gfx.imu.funcs->init_microcode(adev);
653 if (err)
654 dev_err(adev->dev, "Failed to load imu firmware!\n");
655 }
656 }
657
658 out:
659 if (err) {
660 amdgpu_ucode_release(&adev->gfx.pfp_fw);
661 amdgpu_ucode_release(&adev->gfx.me_fw);
662 amdgpu_ucode_release(&adev->gfx.rlc_fw);
663 amdgpu_ucode_release(&adev->gfx.mec_fw);
664 }
665
666 return err;
667 }
668
gfx_v12_0_get_csb_size(struct amdgpu_device * adev)669 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)
670 {
671 u32 count = 0;
672 const struct cs_section_def *sect = NULL;
673 const struct cs_extent_def *ext = NULL;
674
675 count += 1;
676
677 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
678 if (sect->id == SECT_CONTEXT) {
679 for (ext = sect->section; ext->extent != NULL; ++ext)
680 count += 2 + ext->reg_count;
681 } else
682 return 0;
683 }
684
685 return count;
686 }
687
gfx_v12_0_get_csb_buffer(struct amdgpu_device * adev,u32 * buffer)688 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
689 {
690 u32 count = 0, clustercount = 0, i;
691 const struct cs_section_def *sect = NULL;
692 const struct cs_extent_def *ext = NULL;
693
694 if (adev->gfx.rlc.cs_data == NULL)
695 return;
696 if (buffer == NULL)
697 return;
698
699 count += 1;
700
701 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
702 if (sect->id == SECT_CONTEXT) {
703 for (ext = sect->section; ext->extent != NULL; ++ext) {
704 clustercount++;
705 buffer[count++] = ext->reg_count;
706 buffer[count++] = ext->reg_index;
707
708 for (i = 0; i < ext->reg_count; i++)
709 buffer[count++] = cpu_to_le32(ext->extent[i]);
710 }
711 } else
712 return;
713 }
714
715 buffer[0] = clustercount;
716 }
717
gfx_v12_0_rlc_fini(struct amdgpu_device * adev)718 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)
719 {
720 /* clear state block */
721 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
722 &adev->gfx.rlc.clear_state_gpu_addr,
723 (void **)&adev->gfx.rlc.cs_ptr);
724
725 /* jump table block */
726 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
727 &adev->gfx.rlc.cp_table_gpu_addr,
728 (void **)&adev->gfx.rlc.cp_table_ptr);
729 }
730
gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)731 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
732 {
733 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
734
735 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
736 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
737 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
738 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
739 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
740 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
741 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
742 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
743 adev->gfx.rlc.rlcg_reg_access_supported = true;
744 }
745
gfx_v12_0_rlc_init(struct amdgpu_device * adev)746 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
747 {
748 const struct cs_section_def *cs_data;
749 int r;
750
751 adev->gfx.rlc.cs_data = gfx12_cs_data;
752
753 cs_data = adev->gfx.rlc.cs_data;
754
755 if (cs_data) {
756 /* init clear state block */
757 r = amdgpu_gfx_rlc_init_csb(adev);
758 if (r)
759 return r;
760 }
761
762 /* init spm vmid with 0xf */
763 if (adev->gfx.rlc.funcs->update_spm_vmid)
764 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
765
766 return 0;
767 }
768
gfx_v12_0_mec_fini(struct amdgpu_device * adev)769 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)
770 {
771 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
772 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
774 }
775
gfx_v12_0_me_init(struct amdgpu_device * adev)776 static void gfx_v12_0_me_init(struct amdgpu_device *adev)
777 {
778 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
779
780 amdgpu_gfx_graphics_queue_acquire(adev);
781 }
782
gfx_v12_0_mec_init(struct amdgpu_device * adev)783 static int gfx_v12_0_mec_init(struct amdgpu_device *adev)
784 {
785 int r;
786 u32 *hpd;
787 size_t mec_hpd_size;
788
789 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
790
791 /* take ownership of the relevant compute queues */
792 amdgpu_gfx_compute_queue_acquire(adev);
793 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;
794
795 if (mec_hpd_size) {
796 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
797 AMDGPU_GEM_DOMAIN_GTT,
798 &adev->gfx.mec.hpd_eop_obj,
799 &adev->gfx.mec.hpd_eop_gpu_addr,
800 (void **)&hpd);
801 if (r) {
802 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
803 gfx_v12_0_mec_fini(adev);
804 return r;
805 }
806
807 memset(hpd, 0, mec_hpd_size);
808
809 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
810 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
811 }
812
813 return 0;
814 }
815
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)816 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
817 {
818 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
819 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
820 (address << SQ_IND_INDEX__INDEX__SHIFT));
821 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
822 }
823
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)824 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
825 uint32_t thread, uint32_t regno,
826 uint32_t num, uint32_t *out)
827 {
828 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
829 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
830 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
831 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
832 (SQ_IND_INDEX__AUTO_INCR_MASK));
833 while (num--)
834 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
835 }
836
gfx_v12_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)837 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
838 uint32_t xcc_id,
839 uint32_t simd, uint32_t wave,
840 uint32_t *dst, int *no_fields)
841 {
842 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE
843 * field when performing a select_se_sh so it should be
844 * zero here */
845 WARN_ON(simd != 0);
846
847 /* type 4 wave data */
848 dst[(*no_fields)++] = 4;
849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
872 }
873
gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)874 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,
875 uint32_t xcc_id, uint32_t simd,
876 uint32_t wave, uint32_t start,
877 uint32_t size, uint32_t *dst)
878 {
879 WARN_ON(simd != 0);
880
881 wave_read_regs(
882 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
883 dst);
884 }
885
gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)886 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,
887 uint32_t xcc_id, uint32_t simd,
888 uint32_t wave, uint32_t thread,
889 uint32_t start, uint32_t size,
890 uint32_t *dst)
891 {
892 wave_read_regs(
893 adev, wave, thread,
894 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
895 }
896
gfx_v12_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)897 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,
898 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
899 {
900 soc24_grbm_select(adev, me, pipe, q, vm);
901 }
902
903 /* all sizes are in bytes */
904 #define MQD_SHADOW_BASE_SIZE 73728
905 #define MQD_SHADOW_BASE_ALIGNMENT 256
906 #define MQD_FWWORKAREA_SIZE 484
907 #define MQD_FWWORKAREA_ALIGNMENT 256
908
gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info)909 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
910 struct amdgpu_gfx_shadow_info *shadow_info)
911 {
912 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
913 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
914 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
915 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
916 }
917
gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info,bool skip_check)918 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,
919 struct amdgpu_gfx_shadow_info *shadow_info,
920 bool skip_check)
921 {
922 if (adev->gfx.cp_gfx_shadow || skip_check) {
923 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
924 return 0;
925 }
926
927 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
928 return -EINVAL;
929 }
930
931 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
932 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
933 .select_se_sh = &gfx_v12_0_select_se_sh,
934 .read_wave_data = &gfx_v12_0_read_wave_data,
935 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs,
936 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
937 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
938 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
939 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info,
940 };
941
gfx_v12_0_gpu_early_init(struct amdgpu_device * adev)942 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
943 {
944
945 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
946 case IP_VERSION(12, 0, 0):
947 case IP_VERSION(12, 0, 1):
948 adev->gfx.config.max_hw_contexts = 8;
949 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
950 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
951 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
952 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
953 break;
954 default:
955 BUG();
956 break;
957 }
958
959 return 0;
960 }
961
gfx_v12_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)962 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
963 int me, int pipe, int queue)
964 {
965 int r;
966 struct amdgpu_ring *ring;
967 unsigned int irq_type;
968
969 ring = &adev->gfx.gfx_ring[ring_id];
970
971 ring->me = me;
972 ring->pipe = pipe;
973 ring->queue = queue;
974
975 ring->ring_obj = NULL;
976 ring->use_doorbell = true;
977
978 if (!ring_id)
979 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
980 else
981 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
982 ring->vm_hub = AMDGPU_GFXHUB(0);
983 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
984
985 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
986 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
987 AMDGPU_RING_PRIO_DEFAULT, NULL);
988 if (r)
989 return r;
990 return 0;
991 }
992
gfx_v12_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)993 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
994 int mec, int pipe, int queue)
995 {
996 int r;
997 unsigned irq_type;
998 struct amdgpu_ring *ring;
999 unsigned int hw_prio;
1000
1001 ring = &adev->gfx.compute_ring[ring_id];
1002
1003 /* mec0 is me1 */
1004 ring->me = mec + 1;
1005 ring->pipe = pipe;
1006 ring->queue = queue;
1007
1008 ring->ring_obj = NULL;
1009 ring->use_doorbell = true;
1010 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1011 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1012 + (ring_id * GFX12_MEC_HPD_SIZE);
1013 ring->vm_hub = AMDGPU_GFXHUB(0);
1014 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1015
1016 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1017 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1018 + ring->pipe;
1019 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1020 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1021 /* type-2 packets are deprecated on MEC, use type-3 instead */
1022 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1023 hw_prio, NULL);
1024 if (r)
1025 return r;
1026
1027 return 0;
1028 }
1029
1030 static struct {
1031 SOC24_FIRMWARE_ID id;
1032 unsigned int offset;
1033 unsigned int size;
1034 unsigned int size_x16;
1035 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];
1036
1037 #define RLC_TOC_OFFSET_DWUNIT 8
1038 #define RLC_SIZE_MULTIPLE 1024
1039 #define RLC_TOC_UMF_SIZE_inM 23ULL
1040 #define RLC_TOC_FORMAT_API 165ULL
1041
gfx_v12_0_parse_rlc_toc(struct amdgpu_device * adev,void * rlc_toc)1042 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1043 {
1044 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;
1045
1046 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) {
1047 rlc_autoload_info[ucode->id].id = ucode->id;
1048 rlc_autoload_info[ucode->id].offset =
1049 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4;
1050 rlc_autoload_info[ucode->id].size =
1051 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 :
1052 ucode->size * 4;
1053 ucode++;
1054 }
1055 }
1056
gfx_v12_0_calc_toc_total_size(struct amdgpu_device * adev)1057 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)
1058 {
1059 uint32_t total_size = 0;
1060 SOC24_FIRMWARE_ID id;
1061
1062 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1063
1064 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++)
1065 total_size += rlc_autoload_info[id].size;
1066
1067 /* In case the offset in rlc toc ucode is aligned */
1068 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)
1069 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +
1070 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;
1071 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20))
1072 total_size = RLC_TOC_UMF_SIZE_inM << 20;
1073
1074 return total_size;
1075 }
1076
gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device * adev)1077 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1078 {
1079 int r;
1080 uint32_t total_size;
1081
1082 total_size = gfx_v12_0_calc_toc_total_size(adev);
1083
1084 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1085 AMDGPU_GEM_DOMAIN_VRAM,
1086 &adev->gfx.rlc.rlc_autoload_bo,
1087 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1088 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1089
1090 if (r) {
1091 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1092 return r;
1093 }
1094
1095 return 0;
1096 }
1097
gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,SOC24_FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)1098 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1099 SOC24_FIRMWARE_ID id,
1100 const void *fw_data,
1101 uint32_t fw_size)
1102 {
1103 uint32_t toc_offset;
1104 uint32_t toc_fw_size;
1105 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1106
1107 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX)
1108 return;
1109
1110 toc_offset = rlc_autoload_info[id].offset;
1111 toc_fw_size = rlc_autoload_info[id].size;
1112
1113 if (fw_size == 0)
1114 fw_size = toc_fw_size;
1115
1116 if (fw_size > toc_fw_size)
1117 fw_size = toc_fw_size;
1118
1119 memcpy(ptr + toc_offset, fw_data, fw_size);
1120
1121 if (fw_size < toc_fw_size)
1122 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1123 }
1124
1125 static void
gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)1126 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
1127 {
1128 void *data;
1129 uint32_t size;
1130 uint32_t *toc_ptr;
1131
1132 data = adev->psp.toc.start_addr;
1133 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;
1134
1135 toc_ptr = (uint32_t *)data + size / 4 - 2;
1136 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1;
1137
1138 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,
1139 data, size);
1140 }
1141
1142 static void
gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)1143 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
1144 {
1145 const __le32 *fw_data;
1146 uint32_t fw_size;
1147 const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1148 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1149 const struct rlc_firmware_header_v2_1 *rlcv21_hdr;
1150 const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1151 uint16_t version_major, version_minor;
1152
1153 /* pfp ucode */
1154 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1155 adev->gfx.pfp_fw->data;
1156 /* instruction */
1157 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1158 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1159 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1160 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,
1161 fw_data, fw_size);
1162 /* data */
1163 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1164 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1165 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1166 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,
1167 fw_data, fw_size);
1168 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,
1169 fw_data, fw_size);
1170 /* me ucode */
1171 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1172 adev->gfx.me_fw->data;
1173 /* instruction */
1174 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1175 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1176 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1177 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,
1178 fw_data, fw_size);
1179 /* data */
1180 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1181 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1182 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1183 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,
1184 fw_data, fw_size);
1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,
1186 fw_data, fw_size);
1187 /* mec ucode */
1188 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1189 adev->gfx.mec_fw->data;
1190 /* instruction */
1191 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1192 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1193 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1194 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,
1195 fw_data, fw_size);
1196 /* data */
1197 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1198 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1199 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1200 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,
1201 fw_data, fw_size);
1202 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,
1203 fw_data, fw_size);
1204 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,
1205 fw_data, fw_size);
1206 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,
1207 fw_data, fw_size);
1208
1209 /* rlc ucode */
1210 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1211 adev->gfx.rlc_fw->data;
1212 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1213 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1214 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1215 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,
1216 fw_data, fw_size);
1217
1218 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1219 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1220 if (version_major == 2) {
1221 if (version_minor >= 1) {
1222 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1223
1224 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1225 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes));
1226 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes);
1227 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,
1228 fw_data, fw_size);
1229
1230 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1231 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes));
1232 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes);
1233 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,
1234 fw_data, fw_size);
1235 }
1236 if (version_minor >= 2) {
1237 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1238
1239 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1240 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1241 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1242 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,
1243 fw_data, fw_size);
1244
1245 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1246 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1247 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1248 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,
1249 fw_data, fw_size);
1250 }
1251 }
1252 }
1253
1254 static void
gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)1255 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
1256 {
1257 const __le32 *fw_data;
1258 uint32_t fw_size;
1259 const struct sdma_firmware_header_v3_0 *sdma_hdr;
1260
1261 sdma_hdr = (const struct sdma_firmware_header_v3_0 *)
1262 adev->sdma.instance[0].fw->data;
1263 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1264 le32_to_cpu(sdma_hdr->ucode_offset_bytes));
1265 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes);
1266
1267 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,
1268 fw_data, fw_size);
1269 }
1270
1271 static void
gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device * adev)1272 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)
1273 {
1274 const __le32 *fw_data;
1275 unsigned fw_size;
1276 const struct mes_firmware_header_v1_0 *mes_hdr;
1277 int pipe, ucode_id, data_id;
1278
1279 for (pipe = 0; pipe < 2; pipe++) {
1280 if (pipe == 0) {
1281 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;
1282 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;
1283 } else {
1284 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;
1285 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;
1286 }
1287
1288 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1289 adev->mes.fw[pipe]->data;
1290
1291 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1292 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1293 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1294
1295 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);
1296
1297 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1298 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1299 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1300
1301 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);
1302 }
1303 }
1304
gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)1305 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1306 {
1307 uint32_t rlc_g_offset, rlc_g_size;
1308 uint64_t gpu_addr;
1309 uint32_t data;
1310
1311 /* RLC autoload sequence 2: copy ucode */
1312 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
1313 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
1314 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);
1315 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
1316
1317 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;
1318 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
1319 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
1320
1321 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1323
1324 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1325
1326 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1327 /* RLC autoload sequence 3: load IMU fw */
1328 if (adev->gfx.imu.funcs->load_microcode)
1329 adev->gfx.imu.funcs->load_microcode(adev);
1330 /* RLC autoload sequence 4 init IMU fw */
1331 if (adev->gfx.imu.funcs->setup_imu)
1332 adev->gfx.imu.funcs->setup_imu(adev);
1333 if (adev->gfx.imu.funcs->start_imu)
1334 adev->gfx.imu.funcs->start_imu(adev);
1335
1336 /* RLC autoload sequence 5 disable gpa mode */
1337 gfx_v12_0_disable_gpa_mode(adev);
1338 } else {
1339 /* unhalt rlc to start autoload without imu */
1340 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1341 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1342 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1343 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1344 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1345 }
1346
1347 return 0;
1348 }
1349
gfx_v12_0_alloc_ip_dump(struct amdgpu_device * adev)1350 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
1351 {
1352 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
1353 uint32_t *ptr;
1354 uint32_t inst;
1355
1356 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1357 if (!ptr) {
1358 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1359 adev->gfx.ip_dump_core = NULL;
1360 } else {
1361 adev->gfx.ip_dump_core = ptr;
1362 }
1363
1364 /* Allocate memory for compute queue registers for all the instances */
1365 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
1366 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1367 adev->gfx.mec.num_queue_per_pipe;
1368
1369 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1370 if (!ptr) {
1371 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1372 adev->gfx.ip_dump_compute_queues = NULL;
1373 } else {
1374 adev->gfx.ip_dump_compute_queues = ptr;
1375 }
1376
1377 /* Allocate memory for gfx queue registers for all the instances */
1378 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
1379 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1380 adev->gfx.me.num_queue_per_pipe;
1381
1382 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1383 if (!ptr) {
1384 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1385 adev->gfx.ip_dump_gfx_queues = NULL;
1386 } else {
1387 adev->gfx.ip_dump_gfx_queues = ptr;
1388 }
1389 }
1390
gfx_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1391 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1392 {
1393 int i, j, k, r, ring_id = 0;
1394 unsigned num_compute_rings;
1395 int xcc_id = 0;
1396 struct amdgpu_device *adev = ip_block->adev;
1397 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1398
1399 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1400
1401 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1402 case IP_VERSION(12, 0, 0):
1403 case IP_VERSION(12, 0, 1):
1404 adev->gfx.me.num_me = 1;
1405 adev->gfx.me.num_pipe_per_me = 1;
1406 adev->gfx.me.num_queue_per_pipe = 8;
1407 adev->gfx.mec.num_mec = 1;
1408 adev->gfx.mec.num_pipe_per_mec = 2;
1409 adev->gfx.mec.num_queue_per_pipe = 4;
1410 break;
1411 default:
1412 adev->gfx.me.num_me = 1;
1413 adev->gfx.me.num_pipe_per_me = 1;
1414 adev->gfx.me.num_queue_per_pipe = 1;
1415 adev->gfx.mec.num_mec = 1;
1416 adev->gfx.mec.num_pipe_per_mec = 4;
1417 adev->gfx.mec.num_queue_per_pipe = 8;
1418 break;
1419 }
1420
1421 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1422 case IP_VERSION(12, 0, 0):
1423 case IP_VERSION(12, 0, 1):
1424 if (!adev->gfx.disable_uq &&
1425 adev->gfx.me_fw_version >= 2780 &&
1426 adev->gfx.pfp_fw_version >= 2840 &&
1427 adev->gfx.mec_fw_version >= 3050 &&
1428 adev->mes.fw_version[0] >= 123) {
1429 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
1430 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
1431 }
1432 break;
1433 default:
1434 break;
1435 }
1436
1437 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1438 case IP_VERSION(12, 0, 0):
1439 case IP_VERSION(12, 0, 1):
1440 if (adev->gfx.me_fw_version >= 2480 &&
1441 adev->gfx.pfp_fw_version >= 2530 &&
1442 adev->gfx.mec_fw_version >= 2680 &&
1443 adev->mes.fw_version[0] >= 100)
1444 adev->gfx.enable_cleaner_shader = true;
1445 break;
1446 default:
1447 adev->gfx.enable_cleaner_shader = false;
1448 break;
1449 }
1450
1451 if (adev->gfx.num_compute_rings) {
1452 /* recalculate compute rings to use based on hardware configuration */
1453 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
1454 adev->gfx.mec.num_queue_per_pipe) / 2;
1455 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
1456 num_compute_rings);
1457 }
1458
1459 /* EOP Event */
1460 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1461 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT,
1462 &adev->gfx.eop_irq);
1463 if (r)
1464 return r;
1465
1466 /* Bad opcode Event */
1467 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1468 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1469 &adev->gfx.bad_op_irq);
1470 if (r)
1471 return r;
1472
1473 /* Privileged reg */
1474 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1475 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT,
1476 &adev->gfx.priv_reg_irq);
1477 if (r)
1478 return r;
1479
1480 /* Privileged inst */
1481 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1482 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1483 &adev->gfx.priv_inst_irq);
1484 if (r)
1485 return r;
1486
1487 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1488
1489 gfx_v12_0_me_init(adev);
1490
1491 r = gfx_v12_0_rlc_init(adev);
1492 if (r) {
1493 dev_err(adev->dev, "Failed to init rlc BOs!\n");
1494 return r;
1495 }
1496
1497 r = gfx_v12_0_mec_init(adev);
1498 if (r) {
1499 dev_err(adev->dev, "Failed to init MEC BOs!\n");
1500 return r;
1501 }
1502
1503 if (adev->gfx.num_gfx_rings) {
1504 /* set up the gfx ring */
1505 for (i = 0; i < adev->gfx.me.num_me; i++) {
1506 for (j = 0; j < num_queue_per_pipe; j++) {
1507 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1508 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1509 continue;
1510
1511 r = gfx_v12_0_gfx_ring_init(adev, ring_id,
1512 i, k, j);
1513 if (r)
1514 return r;
1515 ring_id++;
1516 }
1517 }
1518 }
1519 }
1520
1521 if (adev->gfx.num_compute_rings) {
1522 ring_id = 0;
1523 /* set up the compute queues - allocate horizontally across pipes */
1524 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1525 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1526 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1527 if (!amdgpu_gfx_is_mec_queue_enabled(adev,
1528 0, i, k, j))
1529 continue;
1530
1531 r = gfx_v12_0_compute_ring_init(adev, ring_id,
1532 i, k, j);
1533 if (r)
1534 return r;
1535
1536 ring_id++;
1537 }
1538 }
1539 }
1540 }
1541
1542 adev->gfx.gfx_supported_reset =
1543 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1544 adev->gfx.compute_supported_reset =
1545 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1546 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1547 case IP_VERSION(12, 0, 0):
1548 case IP_VERSION(12, 0, 1):
1549 if ((adev->gfx.me_fw_version >= 2660) &&
1550 (adev->gfx.mec_fw_version >= 2920) &&
1551 !amdgpu_sriov_vf(adev)) {
1552 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1553 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1554 }
1555 break;
1556 default:
1557 break;
1558 }
1559
1560 if (!adev->enable_mes_kiq) {
1561 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);
1562 if (r) {
1563 dev_err(adev->dev, "Failed to init KIQ BOs!\n");
1564 return r;
1565 }
1566
1567 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1568 if (r)
1569 return r;
1570 }
1571
1572 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);
1573 if (r)
1574 return r;
1575
1576 /* allocate visible FB for rlc auto-loading fw */
1577 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1578 r = gfx_v12_0_rlc_autoload_buffer_init(adev);
1579 if (r)
1580 return r;
1581 }
1582
1583 r = gfx_v12_0_gpu_early_init(adev);
1584 if (r)
1585 return r;
1586
1587 gfx_v12_0_alloc_ip_dump(adev);
1588
1589 r = amdgpu_gfx_sysfs_init(adev);
1590 if (r)
1591 return r;
1592
1593 return 0;
1594 }
1595
gfx_v12_0_pfp_fini(struct amdgpu_device * adev)1596 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)
1597 {
1598 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1599 &adev->gfx.pfp.pfp_fw_gpu_addr,
1600 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1601
1602 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1603 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1604 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1605 }
1606
gfx_v12_0_me_fini(struct amdgpu_device * adev)1607 static void gfx_v12_0_me_fini(struct amdgpu_device *adev)
1608 {
1609 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1610 &adev->gfx.me.me_fw_gpu_addr,
1611 (void **)&adev->gfx.me.me_fw_ptr);
1612
1613 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1614 &adev->gfx.me.me_fw_data_gpu_addr,
1615 (void **)&adev->gfx.me.me_fw_data_ptr);
1616 }
1617
gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device * adev)1618 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1619 {
1620 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1621 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1622 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1623 }
1624
gfx_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1625 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1626 {
1627 int i;
1628 struct amdgpu_device *adev = ip_block->adev;
1629
1630 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1631 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1632 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1633 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1634
1635 amdgpu_gfx_mqd_sw_fini(adev, 0);
1636
1637 if (!adev->enable_mes_kiq) {
1638 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1639 amdgpu_gfx_kiq_fini(adev, 0);
1640 }
1641
1642 gfx_v12_0_pfp_fini(adev);
1643 gfx_v12_0_me_fini(adev);
1644 gfx_v12_0_rlc_fini(adev);
1645 gfx_v12_0_mec_fini(adev);
1646
1647 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1648 gfx_v12_0_rlc_autoload_buffer_fini(adev);
1649
1650 gfx_v12_0_free_microcode(adev);
1651
1652 amdgpu_gfx_sysfs_fini(adev);
1653
1654 kfree(adev->gfx.ip_dump_core);
1655 kfree(adev->gfx.ip_dump_compute_queues);
1656 kfree(adev->gfx.ip_dump_gfx_queues);
1657
1658 return 0;
1659 }
1660
gfx_v12_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)1661 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1662 u32 sh_num, u32 instance, int xcc_id)
1663 {
1664 u32 data;
1665
1666 if (instance == 0xffffffff)
1667 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1668 INSTANCE_BROADCAST_WRITES, 1);
1669 else
1670 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1671 instance);
1672
1673 if (se_num == 0xffffffff)
1674 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1675 1);
1676 else
1677 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1678
1679 if (sh_num == 0xffffffff)
1680 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1681 1);
1682 else
1683 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1684
1685 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1686 }
1687
gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device * adev)1688 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1689 {
1690 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1691
1692 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1693 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1694 GRBM_CC_GC_SA_UNIT_DISABLE,
1695 SA_DISABLE);
1696 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1697 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1698 GRBM_GC_USER_SA_UNIT_DISABLE,
1699 SA_DISABLE);
1700 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1701 adev->gfx.config.max_shader_engines);
1702
1703 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1704 }
1705
gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device * adev)1706 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1707 {
1708 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1709 u32 rb_mask;
1710
1711 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1712 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1713 CC_RB_BACKEND_DISABLE,
1714 BACKEND_DISABLE);
1715 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1716 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1717 GC_USER_RB_BACKEND_DISABLE,
1718 BACKEND_DISABLE);
1719 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1720 adev->gfx.config.max_shader_engines);
1721
1722 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1723 }
1724
gfx_v12_0_setup_rb(struct amdgpu_device * adev)1725 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)
1726 {
1727 u32 rb_bitmap_per_sa;
1728 u32 rb_bitmap_width_per_sa;
1729 u32 max_sa;
1730 u32 active_sa_bitmap;
1731 u32 global_active_rb_bitmap;
1732 u32 active_rb_bitmap = 0;
1733 u32 i;
1734
1735 /* query sa bitmap from SA_UNIT_DISABLE registers */
1736 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);
1737 /* query rb bitmap from RB_BACKEND_DISABLE registers */
1738 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);
1739
1740 /* generate active rb bitmap according to active sa bitmap */
1741 max_sa = adev->gfx.config.max_shader_engines *
1742 adev->gfx.config.max_sh_per_se;
1743 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1744 adev->gfx.config.max_sh_per_se;
1745 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);
1746
1747 for (i = 0; i < max_sa; i++) {
1748 if (active_sa_bitmap & (1 << i))
1749 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa));
1750 }
1751
1752 active_rb_bitmap &= global_active_rb_bitmap;
1753 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1754 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1755 }
1756
1757 #define LDS_APP_BASE 0x1
1758 #define SCRATCH_APP_BASE 0x2
1759
gfx_v12_0_init_compute_vmid(struct amdgpu_device * adev)1760 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)
1761 {
1762 int i;
1763 uint32_t sh_mem_bases;
1764 uint32_t data;
1765
1766 /*
1767 * Configure apertures:
1768 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1769 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1770 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1771 */
1772 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1773 SCRATCH_APP_BASE;
1774
1775 mutex_lock(&adev->srbm_mutex);
1776 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1777 soc24_grbm_select(adev, 0, 0, 0, i);
1778 /* CP and shaders */
1779 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1780 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1781
1782 /* Enable trap for each kfd vmid. */
1783 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1784 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1785 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1786 }
1787 soc24_grbm_select(adev, 0, 0, 0, 0);
1788 mutex_unlock(&adev->srbm_mutex);
1789 }
1790
gfx_v12_0_tcp_harvest(struct amdgpu_device * adev)1791 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)
1792 {
1793 /* TODO: harvest feature to be added later. */
1794 }
1795
gfx_v12_0_get_tcc_info(struct amdgpu_device * adev)1796 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)
1797 {
1798 }
1799
gfx_v12_0_constants_init(struct amdgpu_device * adev)1800 static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
1801 {
1802 u32 tmp;
1803 int i;
1804
1805 if (!amdgpu_sriov_vf(adev))
1806 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1807
1808 gfx_v12_0_setup_rb(adev);
1809 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
1810 gfx_v12_0_get_tcc_info(adev);
1811 adev->gfx.config.pa_sc_tile_steering_override = 0;
1812
1813 /* XXX SH_MEM regs */
1814 /* where to put LDS, scratch, GPUVM in FSA64 space */
1815 mutex_lock(&adev->srbm_mutex);
1816 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1817 soc24_grbm_select(adev, 0, 0, 0, i);
1818 /* CP and shaders */
1819 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1820 if (i != 0) {
1821 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1822 (adev->gmc.private_aperture_start >> 48));
1823 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1824 (adev->gmc.shared_aperture_start >> 48));
1825 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1826 }
1827 }
1828 soc24_grbm_select(adev, 0, 0, 0, 0);
1829
1830 mutex_unlock(&adev->srbm_mutex);
1831
1832 gfx_v12_0_init_compute_vmid(adev);
1833 }
1834
gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)1835 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
1836 int me, int pipe)
1837 {
1838 if (me != 0)
1839 return 0;
1840
1841 switch (pipe) {
1842 case 0:
1843 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1844 default:
1845 return 0;
1846 }
1847 }
1848
gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)1849 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
1850 int me, int pipe)
1851 {
1852 /*
1853 * amdgpu controls only the first MEC. That's why this function only
1854 * handles the setting of interrupts for this specific MEC. All other
1855 * pipes' interrupts are set by amdkfd.
1856 */
1857 if (me != 1)
1858 return 0;
1859
1860 switch (pipe) {
1861 case 0:
1862 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1863 case 1:
1864 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1865 default:
1866 return 0;
1867 }
1868 }
1869
gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1870 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1871 bool enable)
1872 {
1873 u32 tmp, cp_int_cntl_reg;
1874 int i, j;
1875
1876 if (amdgpu_sriov_vf(adev))
1877 return;
1878
1879 for (i = 0; i < adev->gfx.me.num_me; i++) {
1880 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
1881 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
1882
1883 if (cp_int_cntl_reg) {
1884 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1885 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1886 enable ? 1 : 0);
1887 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1888 enable ? 1 : 0);
1889 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1890 enable ? 1 : 0);
1891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1892 enable ? 1 : 0);
1893 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1894 }
1895 }
1896 }
1897 }
1898
gfx_v12_0_init_csb(struct amdgpu_device * adev)1899 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
1900 {
1901 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1902
1903 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1904 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1905 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1906 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1907 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1908
1909 return 0;
1910 }
1911
gfx_v12_0_rlc_stop(struct amdgpu_device * adev)1912 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)
1913 {
1914 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1915
1916 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1917 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1918 }
1919
gfx_v12_0_rlc_reset(struct amdgpu_device * adev)1920 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)
1921 {
1922 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1923 udelay(50);
1924 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1925 udelay(50);
1926 }
1927
gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)1928 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1929 bool enable)
1930 {
1931 uint32_t rlc_pg_cntl;
1932
1933 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1934
1935 if (!enable) {
1936 /* RLC_PG_CNTL[23] = 0 (default)
1937 * RLC will wait for handshake acks with SMU
1938 * GFXOFF will be enabled
1939 * RLC_PG_CNTL[23] = 1
1940 * RLC will not issue any message to SMU
1941 * hence no handshake between SMU & RLC
1942 * GFXOFF will be disabled
1943 */
1944 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1945 } else
1946 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1947 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1948 }
1949
gfx_v12_0_rlc_start(struct amdgpu_device * adev)1950 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)
1951 {
1952 /* TODO: enable rlc & smu handshake until smu
1953 * and gfxoff feature works as expected */
1954 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1955 gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
1956
1957 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1958 udelay(50);
1959 }
1960
gfx_v12_0_rlc_enable_srm(struct amdgpu_device * adev)1961 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)
1962 {
1963 uint32_t tmp;
1964
1965 /* enable Save Restore Machine */
1966 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1967 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1968 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1969 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1970 }
1971
gfx_v12_0_load_rlcg_microcode(struct amdgpu_device * adev)1972 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)
1973 {
1974 const struct rlc_firmware_header_v2_0 *hdr;
1975 const __le32 *fw_data;
1976 unsigned i, fw_size;
1977
1978 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1979 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1980 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1981 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1982
1983 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1984 RLCG_UCODE_LOADING_START_ADDRESS);
1985
1986 for (i = 0; i < fw_size; i++)
1987 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1988 le32_to_cpup(fw_data++));
1989
1990 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1991 }
1992
gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device * adev)1993 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1994 {
1995 const struct rlc_firmware_header_v2_2 *hdr;
1996 const __le32 *fw_data;
1997 unsigned i, fw_size;
1998 u32 tmp;
1999
2000 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
2001
2002 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2003 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
2004 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
2005
2006 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2007
2008 for (i = 0; i < fw_size; i++) {
2009 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2010 msleep(1);
2011 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2012 le32_to_cpup(fw_data++));
2013 }
2014
2015 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2016
2017 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2018 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
2019 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
2020
2021 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2022 for (i = 0; i < fw_size; i++) {
2023 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2024 msleep(1);
2025 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2026 le32_to_cpup(fw_data++));
2027 }
2028
2029 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2030
2031 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2032 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
2033 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
2034 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2035 }
2036
gfx_v12_0_rlc_load_microcode(struct amdgpu_device * adev)2037 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)
2038 {
2039 const struct rlc_firmware_header_v2_0 *hdr;
2040 uint16_t version_major;
2041 uint16_t version_minor;
2042
2043 if (!adev->gfx.rlc_fw)
2044 return -EINVAL;
2045
2046 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2047 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2048
2049 version_major = le16_to_cpu(hdr->header.header_version_major);
2050 version_minor = le16_to_cpu(hdr->header.header_version_minor);
2051
2052 if (version_major == 2) {
2053 gfx_v12_0_load_rlcg_microcode(adev);
2054 if (amdgpu_dpm == 1) {
2055 if (version_minor >= 2)
2056 gfx_v12_0_load_rlc_iram_dram_microcode(adev);
2057 }
2058
2059 return 0;
2060 }
2061
2062 return -EINVAL;
2063 }
2064
gfx_v12_0_rlc_resume(struct amdgpu_device * adev)2065 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
2066 {
2067 int r;
2068
2069 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2070 gfx_v12_0_init_csb(adev);
2071
2072 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2073 gfx_v12_0_rlc_enable_srm(adev);
2074 } else {
2075 if (amdgpu_sriov_vf(adev)) {
2076 gfx_v12_0_init_csb(adev);
2077 return 0;
2078 }
2079
2080 adev->gfx.rlc.funcs->stop(adev);
2081
2082 /* disable CG */
2083 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2084
2085 /* disable PG */
2086 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2087
2088 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2089 /* legacy rlc firmware loading */
2090 r = gfx_v12_0_rlc_load_microcode(adev);
2091 if (r)
2092 return r;
2093 }
2094
2095 gfx_v12_0_init_csb(adev);
2096
2097 adev->gfx.rlc.funcs->start(adev);
2098 }
2099
2100 return 0;
2101 }
2102
gfx_v12_0_config_gfx_rs64(struct amdgpu_device * adev)2103 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)
2104 {
2105 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2106 const struct gfx_firmware_header_v2_0 *me_hdr;
2107 const struct gfx_firmware_header_v2_0 *mec_hdr;
2108 uint32_t pipe_id, tmp;
2109
2110 mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2111 adev->gfx.mec_fw->data;
2112 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2113 adev->gfx.me_fw->data;
2114 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2115 adev->gfx.pfp_fw->data;
2116
2117 /* config pfp program start addr */
2118 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2119 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2120 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2121 (pfp_hdr->ucode_start_addr_hi << 30) |
2122 (pfp_hdr->ucode_start_addr_lo >> 2));
2123 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2124 pfp_hdr->ucode_start_addr_hi >> 2);
2125 }
2126 soc24_grbm_select(adev, 0, 0, 0, 0);
2127
2128 /* reset pfp pipe */
2129 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2130 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2132 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2133
2134 /* clear pfp pipe reset */
2135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2137 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2138
2139 /* config me program start addr */
2140 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2141 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2142 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2143 (me_hdr->ucode_start_addr_hi << 30) |
2144 (me_hdr->ucode_start_addr_lo >> 2));
2145 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2146 me_hdr->ucode_start_addr_hi>>2);
2147 }
2148 soc24_grbm_select(adev, 0, 0, 0, 0);
2149
2150 /* reset me pipe */
2151 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2152 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2154 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2155
2156 /* clear me pipe reset */
2157 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2159 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2160
2161 /* config mec program start addr */
2162 for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2163 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2164 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2165 mec_hdr->ucode_start_addr_lo >> 2 |
2166 mec_hdr->ucode_start_addr_hi << 30);
2167 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2168 mec_hdr->ucode_start_addr_hi >> 2);
2169 }
2170 soc24_grbm_select(adev, 0, 0, 0, 0);
2171
2172 /* reset mec pipe */
2173 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2174 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2178 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2179
2180 /* clear mec pipe reset */
2181 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2182 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2184 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2185 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2186 }
2187
gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device * adev)2188 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
2189 {
2190 const struct gfx_firmware_header_v2_0 *cp_hdr;
2191 unsigned pipe_id, tmp;
2192
2193 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2194 adev->gfx.pfp_fw->data;
2195 mutex_lock(&adev->srbm_mutex);
2196 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2197 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2198 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2199 (cp_hdr->ucode_start_addr_hi << 30) |
2200 (cp_hdr->ucode_start_addr_lo >> 2));
2201 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2202 cp_hdr->ucode_start_addr_hi>>2);
2203
2204 /*
2205 * Program CP_ME_CNTL to reset given PIPE to take
2206 * effect of CP_PFP_PRGRM_CNTR_START.
2207 */
2208 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2209 if (pipe_id == 0)
2210 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2211 PFP_PIPE0_RESET, 1);
2212 else
2213 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2214 PFP_PIPE1_RESET, 1);
2215 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2216
2217 /* Clear pfp pipe0 reset bit. */
2218 if (pipe_id == 0)
2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2220 PFP_PIPE0_RESET, 0);
2221 else
2222 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2223 PFP_PIPE1_RESET, 0);
2224 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2225 }
2226 soc24_grbm_select(adev, 0, 0, 0, 0);
2227 mutex_unlock(&adev->srbm_mutex);
2228 }
2229
gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device * adev)2230 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)
2231 {
2232 const struct gfx_firmware_header_v2_0 *cp_hdr;
2233 unsigned pipe_id, tmp;
2234
2235 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2236 adev->gfx.me_fw->data;
2237 mutex_lock(&adev->srbm_mutex);
2238 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2239 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2240 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2241 (cp_hdr->ucode_start_addr_hi << 30) |
2242 (cp_hdr->ucode_start_addr_lo >> 2) );
2243 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2244 cp_hdr->ucode_start_addr_hi>>2);
2245
2246 /*
2247 * Program CP_ME_CNTL to reset given PIPE to take
2248 * effect of CP_ME_PRGRM_CNTR_START.
2249 */
2250 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2251 if (pipe_id == 0)
2252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2253 ME_PIPE0_RESET, 1);
2254 else
2255 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2256 ME_PIPE1_RESET, 1);
2257 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2258
2259 /* Clear pfp pipe0 reset bit. */
2260 if (pipe_id == 0)
2261 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2262 ME_PIPE0_RESET, 0);
2263 else
2264 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2265 ME_PIPE1_RESET, 0);
2266 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2267 }
2268 soc24_grbm_select(adev, 0, 0, 0, 0);
2269 mutex_unlock(&adev->srbm_mutex);
2270 }
2271
gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device * adev)2272 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)
2273 {
2274 const struct gfx_firmware_header_v2_0 *cp_hdr;
2275 unsigned pipe_id;
2276
2277 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2278 adev->gfx.mec_fw->data;
2279 mutex_lock(&adev->srbm_mutex);
2280 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) {
2281 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2282 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2283 cp_hdr->ucode_start_addr_lo >> 2 |
2284 cp_hdr->ucode_start_addr_hi << 30);
2285 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2286 cp_hdr->ucode_start_addr_hi >> 2);
2287 }
2288 soc24_grbm_select(adev, 0, 0, 0, 0);
2289 mutex_unlock(&adev->srbm_mutex);
2290 }
2291
gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)2292 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2293 {
2294 uint32_t cp_status;
2295 uint32_t bootload_status;
2296 int i;
2297
2298 for (i = 0; i < adev->usec_timeout; i++) {
2299 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2300 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2301
2302 if ((cp_status == 0) &&
2303 (REG_GET_FIELD(bootload_status,
2304 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2305 break;
2306 }
2307 udelay(1);
2308 if (amdgpu_emu_mode)
2309 msleep(10);
2310 }
2311
2312 if (i >= adev->usec_timeout) {
2313 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2314 return -ETIMEDOUT;
2315 }
2316
2317 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2318 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2319 gfx_v12_0_set_me_ucode_start_addr(adev);
2320 gfx_v12_0_set_mec_ucode_start_addr(adev);
2321 }
2322
2323 return 0;
2324 }
2325
gfx_v12_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2326 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2327 {
2328 int i;
2329 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2330
2331 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2333 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2334
2335 for (i = 0; i < adev->usec_timeout; i++) {
2336 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2337 break;
2338 udelay(1);
2339 }
2340
2341 if (i >= adev->usec_timeout)
2342 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2343
2344 return 0;
2345 }
2346
gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device * adev)2347 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2348 {
2349 int r;
2350 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2351 const __le32 *fw_ucode, *fw_data;
2352 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2353 uint32_t tmp;
2354 uint32_t usec_timeout = 50000; /* wait for 50ms */
2355
2356 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2357 adev->gfx.pfp_fw->data;
2358
2359 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2360
2361 /* instruction */
2362 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2363 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2364 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2365 /* data */
2366 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2367 le32_to_cpu(pfp_hdr->data_offset_bytes));
2368 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2369
2370 /* 64kb align */
2371 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2372 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2373 &adev->gfx.pfp.pfp_fw_obj,
2374 &adev->gfx.pfp.pfp_fw_gpu_addr,
2375 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2376 if (r) {
2377 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2378 gfx_v12_0_pfp_fini(adev);
2379 return r;
2380 }
2381
2382 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2383 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2384 &adev->gfx.pfp.pfp_fw_data_obj,
2385 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2386 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2387 if (r) {
2388 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2389 gfx_v12_0_pfp_fini(adev);
2390 return r;
2391 }
2392
2393 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2394 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2395
2396 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2397 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2398 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2399 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2400
2401 if (amdgpu_emu_mode == 1)
2402 amdgpu_device_flush_hdp(adev, NULL);
2403
2404 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2405 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2406 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2407 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2408
2409 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2410 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2411 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2412 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2413 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2414
2415 /*
2416 * Programming any of the CP_PFP_IC_BASE registers
2417 * forces invalidation of the ME L1 I$. Wait for the
2418 * invalidation complete
2419 */
2420 for (i = 0; i < usec_timeout; i++) {
2421 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2422 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2423 INVALIDATE_CACHE_COMPLETE))
2424 break;
2425 udelay(1);
2426 }
2427
2428 if (i >= usec_timeout) {
2429 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2430 return -EINVAL;
2431 }
2432
2433 /* Prime the L1 instruction caches */
2434 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2435 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2436 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2437 /* Waiting for cache primed*/
2438 for (i = 0; i < usec_timeout; i++) {
2439 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2440 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2441 ICACHE_PRIMED))
2442 break;
2443 udelay(1);
2444 }
2445
2446 if (i >= usec_timeout) {
2447 dev_err(adev->dev, "failed to prime instruction cache\n");
2448 return -EINVAL;
2449 }
2450
2451 mutex_lock(&adev->srbm_mutex);
2452 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2453 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2454
2455 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2456 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2457 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2458 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2459 }
2460 soc24_grbm_select(adev, 0, 0, 0, 0);
2461 mutex_unlock(&adev->srbm_mutex);
2462
2463 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2464 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2466 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2467
2468 /* Invalidate the data caches */
2469 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2470 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2471 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2472
2473 for (i = 0; i < usec_timeout; i++) {
2474 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2475 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2476 INVALIDATE_DCACHE_COMPLETE))
2477 break;
2478 udelay(1);
2479 }
2480
2481 if (i >= usec_timeout) {
2482 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2483 return -EINVAL;
2484 }
2485
2486 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2487
2488 return 0;
2489 }
2490
gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device * adev)2491 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2492 {
2493 int r;
2494 const struct gfx_firmware_header_v2_0 *me_hdr;
2495 const __le32 *fw_ucode, *fw_data;
2496 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2497 uint32_t tmp;
2498 uint32_t usec_timeout = 50000; /* wait for 50ms */
2499
2500 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2501 adev->gfx.me_fw->data;
2502
2503 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2504
2505 /* instruction */
2506 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2507 le32_to_cpu(me_hdr->ucode_offset_bytes));
2508 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2509 /* data */
2510 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2511 le32_to_cpu(me_hdr->data_offset_bytes));
2512 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2513
2514 /* 64kb align*/
2515 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2516 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2517 &adev->gfx.me.me_fw_obj,
2518 &adev->gfx.me.me_fw_gpu_addr,
2519 (void **)&adev->gfx.me.me_fw_ptr);
2520 if (r) {
2521 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2522 gfx_v12_0_me_fini(adev);
2523 return r;
2524 }
2525
2526 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2527 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2528 &adev->gfx.me.me_fw_data_obj,
2529 &adev->gfx.me.me_fw_data_gpu_addr,
2530 (void **)&adev->gfx.me.me_fw_data_ptr);
2531 if (r) {
2532 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2533 gfx_v12_0_me_fini(adev);
2534 return r;
2535 }
2536
2537 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2538 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2539
2540 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2541 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2542 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2543 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2544
2545 if (amdgpu_emu_mode == 1)
2546 amdgpu_device_flush_hdp(adev, NULL);
2547
2548 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2549 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2550 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2551 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2552
2553 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2554 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2555 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2557 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2558
2559 /*
2560 * Programming any of the CP_ME_IC_BASE registers
2561 * forces invalidation of the ME L1 I$. Wait for the
2562 * invalidation complete
2563 */
2564 for (i = 0; i < usec_timeout; i++) {
2565 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2566 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2567 INVALIDATE_CACHE_COMPLETE))
2568 break;
2569 udelay(1);
2570 }
2571
2572 if (i >= usec_timeout) {
2573 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2574 return -EINVAL;
2575 }
2576
2577 /* Prime the instruction caches */
2578 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2579 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2580 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2581
2582 /* Waiting for instruction cache primed*/
2583 for (i = 0; i < usec_timeout; i++) {
2584 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2585 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2586 ICACHE_PRIMED))
2587 break;
2588 udelay(1);
2589 }
2590
2591 if (i >= usec_timeout) {
2592 dev_err(adev->dev, "failed to prime instruction cache\n");
2593 return -EINVAL;
2594 }
2595
2596 mutex_lock(&adev->srbm_mutex);
2597 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2598 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2599
2600 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2601 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2602 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2603 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2604 }
2605 soc24_grbm_select(adev, 0, 0, 0, 0);
2606 mutex_unlock(&adev->srbm_mutex);
2607
2608 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2609 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2611 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2612
2613 /* Invalidate the data caches */
2614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2615 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2616 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2617
2618 for (i = 0; i < usec_timeout; i++) {
2619 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2620 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2621 INVALIDATE_DCACHE_COMPLETE))
2622 break;
2623 udelay(1);
2624 }
2625
2626 if (i >= usec_timeout) {
2627 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2628 return -EINVAL;
2629 }
2630
2631 gfx_v12_0_set_me_ucode_start_addr(adev);
2632
2633 return 0;
2634 }
2635
gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2636 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2637 {
2638 int r;
2639
2640 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
2641 return -EINVAL;
2642
2643 gfx_v12_0_cp_gfx_enable(adev, false);
2644
2645 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);
2646 if (r) {
2647 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2648 return r;
2649 }
2650
2651 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);
2652 if (r) {
2653 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2654 return r;
2655 }
2656
2657 return 0;
2658 }
2659
gfx_v12_0_cp_gfx_start(struct amdgpu_device * adev)2660 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)
2661 {
2662 /* init the CP */
2663 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2664 adev->gfx.config.max_hw_contexts - 1);
2665 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2666
2667 if (!amdgpu_async_gfx_ring)
2668 gfx_v12_0_cp_gfx_enable(adev, true);
2669
2670 return 0;
2671 }
2672
gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)2673 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2674 CP_PIPE_ID pipe)
2675 {
2676 u32 tmp;
2677
2678 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2679 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2680
2681 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2682 }
2683
gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)2684 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2685 struct amdgpu_ring *ring)
2686 {
2687 u32 tmp;
2688
2689 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2690 if (ring->use_doorbell) {
2691 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2692 DOORBELL_OFFSET, ring->doorbell_index);
2693 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2694 DOORBELL_EN, 1);
2695 } else {
2696 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2697 DOORBELL_EN, 0);
2698 }
2699 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2700
2701 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2702 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2703 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2704
2705 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2706 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2707 }
2708
gfx_v12_0_cp_gfx_resume(struct amdgpu_device * adev)2709 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)
2710 {
2711 struct amdgpu_ring *ring;
2712 u32 tmp;
2713 u32 rb_bufsz;
2714 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2715
2716 /* Set the write pointer delay */
2717 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2718
2719 /* set the RB to use vmid 0 */
2720 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2721
2722 /* Init gfx ring 0 for pipe 0 */
2723 mutex_lock(&adev->srbm_mutex);
2724 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2725
2726 /* Set ring buffer size */
2727 ring = &adev->gfx.gfx_ring[0];
2728 rb_bufsz = order_base_2(ring->ring_size / 8);
2729 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2730 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2731 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2732
2733 /* Initialize the ring buffer's write pointers */
2734 ring->wptr = 0;
2735 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2737
2738 /* set the wb address whether it's enabled or not */
2739 rptr_addr = ring->rptr_gpu_addr;
2740 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2741 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2742 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2743
2744 wptr_gpu_addr = ring->wptr_gpu_addr;
2745 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2746 lower_32_bits(wptr_gpu_addr));
2747 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2748 upper_32_bits(wptr_gpu_addr));
2749
2750 mdelay(1);
2751 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2752
2753 rb_addr = ring->gpu_addr >> 8;
2754 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2755 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2756
2757 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2758
2759 gfx_v12_0_cp_gfx_set_doorbell(adev, ring);
2760 mutex_unlock(&adev->srbm_mutex);
2761
2762 /* Switch to pipe 0 */
2763 mutex_lock(&adev->srbm_mutex);
2764 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2765 mutex_unlock(&adev->srbm_mutex);
2766
2767 /* start the ring */
2768 gfx_v12_0_cp_gfx_start(adev);
2769 return 0;
2770 }
2771
gfx_v12_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2772 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2773 {
2774 u32 data;
2775
2776 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2777 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
2778 enable ? 0 : 1);
2779 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
2780 enable ? 0 : 1);
2781 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
2782 enable ? 0 : 1);
2783 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
2784 enable ? 0 : 1);
2785 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
2786 enable ? 0 : 1);
2787 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
2788 enable ? 1 : 0);
2789 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
2790 enable ? 1 : 0);
2791 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
2792 enable ? 1 : 0);
2793 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
2794 enable ? 1 : 0);
2795 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
2796 enable ? 0 : 1);
2797 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2798
2799 adev->gfx.kiq[0].ring.sched.ready = enable;
2800
2801 udelay(50);
2802 }
2803
gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device * adev)2804 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
2805 {
2806 const struct gfx_firmware_header_v2_0 *mec_hdr;
2807 const __le32 *fw_ucode, *fw_data;
2808 u32 tmp, fw_ucode_size, fw_data_size;
2809 u32 i, usec_timeout = 50000; /* Wait for 50 ms */
2810 u32 *fw_ucode_ptr, *fw_data_ptr;
2811 int r;
2812
2813 if (!adev->gfx.mec_fw)
2814 return -EINVAL;
2815
2816 gfx_v12_0_cp_compute_enable(adev, false);
2817
2818 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
2819 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2820
2821 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
2822 le32_to_cpu(mec_hdr->ucode_offset_bytes));
2823 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
2824
2825 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2826 le32_to_cpu(mec_hdr->data_offset_bytes));
2827 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
2828
2829 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2830 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2831 &adev->gfx.mec.mec_fw_obj,
2832 &adev->gfx.mec.mec_fw_gpu_addr,
2833 (void **)&fw_ucode_ptr);
2834 if (r) {
2835 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2836 gfx_v12_0_mec_fini(adev);
2837 return r;
2838 }
2839
2840 r = amdgpu_bo_create_reserved(adev,
2841 ALIGN(fw_data_size, 64 * 1024) *
2842 adev->gfx.mec.num_pipe_per_mec,
2843 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2844 &adev->gfx.mec.mec_fw_data_obj,
2845 &adev->gfx.mec.mec_fw_data_gpu_addr,
2846 (void **)&fw_data_ptr);
2847 if (r) {
2848 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2849 gfx_v12_0_mec_fini(adev);
2850 return r;
2851 }
2852
2853 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
2854 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2855 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);
2856 }
2857
2858 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2859 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
2860 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2861 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
2862
2863 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2864 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2865 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2866 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2867 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2868
2869 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2870 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2871 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2872 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2873
2874 mutex_lock(&adev->srbm_mutex);
2875 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2876 soc24_grbm_select(adev, 1, i, 0, 0);
2877
2878 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2879 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2880 i * ALIGN(fw_data_size, 64 * 1024)));
2881 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2882 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2883 i * ALIGN(fw_data_size, 64 * 1024)));
2884
2885 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2886 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2887 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2888 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2889 }
2890 mutex_unlock(&adev->srbm_mutex);
2891 soc24_grbm_select(adev, 0, 0, 0, 0);
2892
2893 /* Trigger an invalidation of the L1 instruction caches */
2894 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2895 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2896 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2897
2898 /* Wait for invalidation complete */
2899 for (i = 0; i < usec_timeout; i++) {
2900 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2901 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2902 INVALIDATE_DCACHE_COMPLETE))
2903 break;
2904 udelay(1);
2905 }
2906
2907 if (i >= usec_timeout) {
2908 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2909 return -EINVAL;
2910 }
2911
2912 /* Trigger an invalidation of the L1 instruction caches */
2913 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2914 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2915 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2916
2917 /* Wait for invalidation complete */
2918 for (i = 0; i < usec_timeout; i++) {
2919 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2920 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2921 INVALIDATE_CACHE_COMPLETE))
2922 break;
2923 udelay(1);
2924 }
2925
2926 if (i >= usec_timeout) {
2927 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2928 return -EINVAL;
2929 }
2930
2931 gfx_v12_0_set_mec_ucode_start_addr(adev);
2932
2933 return 0;
2934 }
2935
gfx_v12_0_kiq_setting(struct amdgpu_ring * ring)2936 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
2937 {
2938 uint32_t tmp;
2939 struct amdgpu_device *adev = ring->adev;
2940
2941 /* tell RLC which is KIQ queue */
2942 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2943 tmp &= 0xffffff00;
2944 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2945 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2946 }
2947
gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device * adev)2948 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)
2949 {
2950 /* set graphics engine doorbell range */
2951 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2952 (adev->doorbell_index.gfx_ring0 * 2) << 2);
2953 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2954 (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
2955
2956 /* set compute engine doorbell range */
2957 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2958 (adev->doorbell_index.kiq * 2) << 2);
2959 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
2960 (adev->doorbell_index.userqueue_end * 2) << 2);
2961 }
2962
gfx_v12_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)2963 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
2964 struct amdgpu_mqd_prop *prop)
2965 {
2966 struct v12_gfx_mqd *mqd = m;
2967 uint64_t hqd_gpu_addr, wb_gpu_addr;
2968 uint32_t tmp;
2969 uint32_t rb_bufsz;
2970
2971 /* set up gfx hqd wptr */
2972 mqd->cp_gfx_hqd_wptr = 0;
2973 mqd->cp_gfx_hqd_wptr_hi = 0;
2974
2975 /* set the pointer to the MQD */
2976 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
2977 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
2978
2979 /* set up mqd control */
2980 tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
2981 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2982 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2983 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2984 mqd->cp_gfx_mqd_control = tmp;
2985
2986 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2987 tmp = regCP_GFX_HQD_VMID_DEFAULT;
2988 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2989 mqd->cp_gfx_hqd_vmid = 0;
2990
2991 /* set up default queue priority level
2992 * 0x0 = low priority, 0x1 = high priority */
2993 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
2994 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2995 mqd->cp_gfx_hqd_queue_priority = tmp;
2996
2997 /* set up time quantum */
2998 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
2999 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3000 mqd->cp_gfx_hqd_quantum = tmp;
3001
3002 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3003 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3004 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3005 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3006
3007 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3008 wb_gpu_addr = prop->rptr_gpu_addr;
3009 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3010 mqd->cp_gfx_hqd_rptr_addr_hi =
3011 upper_32_bits(wb_gpu_addr) & 0xffff;
3012
3013 /* set up rb_wptr_poll addr */
3014 wb_gpu_addr = prop->wptr_gpu_addr;
3015 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3016 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3017
3018 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3019 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3020 tmp = regCP_GFX_HQD_CNTL_DEFAULT;
3021 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3023 #ifdef __BIG_ENDIAN
3024 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3025 #endif
3026 if (prop->tmz_queue)
3027 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
3028 if (!prop->kernel_queue)
3029 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
3030 mqd->cp_gfx_hqd_cntl = tmp;
3031
3032 /* set up cp_doorbell_control */
3033 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
3034 if (prop->use_doorbell) {
3035 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3036 DOORBELL_OFFSET, prop->doorbell_index);
3037 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3038 DOORBELL_EN, 1);
3039 } else
3040 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3041 DOORBELL_EN, 0);
3042 mqd->cp_rb_doorbell_control = tmp;
3043
3044 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3045 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
3046
3047 /* active the queue */
3048 mqd->cp_gfx_hqd_active = 1;
3049
3050 /* set gfx UQ items */
3051 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
3052 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);
3053 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
3054 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);
3055 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3056 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3057
3058 return 0;
3059 }
3060
gfx_v12_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)3061 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
3062 {
3063 struct amdgpu_device *adev = ring->adev;
3064 struct v12_gfx_mqd *mqd = ring->mqd_ptr;
3065 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3066
3067 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3068 memset((void *)mqd, 0, sizeof(*mqd));
3069 mutex_lock(&adev->srbm_mutex);
3070 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3071 amdgpu_ring_init_mqd(ring);
3072 soc24_grbm_select(adev, 0, 0, 0, 0);
3073 mutex_unlock(&adev->srbm_mutex);
3074 if (adev->gfx.me.mqd_backup[mqd_idx])
3075 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3076 } else {
3077 /* restore mqd with the backup copy */
3078 if (adev->gfx.me.mqd_backup[mqd_idx])
3079 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3080 /* reset the ring */
3081 ring->wptr = 0;
3082 *ring->wptr_cpu_addr = 0;
3083 amdgpu_ring_clear_ring(ring);
3084 }
3085
3086 return 0;
3087 }
3088
gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)3089 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3090 {
3091 int i, r;
3092
3093 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3094 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3095 if (r)
3096 return r;
3097 }
3098
3099 r = amdgpu_gfx_enable_kgq(adev, 0);
3100 if (r)
3101 return r;
3102
3103 return gfx_v12_0_cp_gfx_start(adev);
3104 }
3105
gfx_v12_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)3106 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3107 struct amdgpu_mqd_prop *prop)
3108 {
3109 struct v12_compute_mqd *mqd = m;
3110 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3111 uint32_t tmp;
3112
3113 mqd->header = 0xC0310800;
3114 mqd->compute_pipelinestat_enable = 0x00000001;
3115 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3116 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3117 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3118 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3119 mqd->compute_misc_reserved = 0x00000007;
3120
3121 eop_base_addr = prop->eop_gpu_addr >> 8;
3122 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3123 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3124
3125 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3126 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
3127 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3128 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
3129
3130 mqd->cp_hqd_eop_control = tmp;
3131
3132 /* enable doorbell? */
3133 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3134
3135 if (prop->use_doorbell) {
3136 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3137 DOORBELL_OFFSET, prop->doorbell_index);
3138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3139 DOORBELL_EN, 1);
3140 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3141 DOORBELL_SOURCE, 0);
3142 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3143 DOORBELL_HIT, 0);
3144 } else {
3145 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3146 DOORBELL_EN, 0);
3147 }
3148
3149 mqd->cp_hqd_pq_doorbell_control = tmp;
3150
3151 /* disable the queue if it's active */
3152 mqd->cp_hqd_dequeue_request = 0;
3153 mqd->cp_hqd_pq_rptr = 0;
3154 mqd->cp_hqd_pq_wptr_lo = 0;
3155 mqd->cp_hqd_pq_wptr_hi = 0;
3156
3157 /* set the pointer to the MQD */
3158 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3159 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3160
3161 /* set MQD vmid to 0 */
3162 tmp = regCP_MQD_CONTROL_DEFAULT;
3163 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3164 mqd->cp_mqd_control = tmp;
3165
3166 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3167 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3168 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3169 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3170
3171 /* set up the HQD, this is similar to CP_RB0_CNTL */
3172 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
3173 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3174 (order_base_2(prop->queue_size / 4) - 1));
3175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3176 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3179 if (prop->kernel_queue) {
3180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3182 }
3183 if (prop->tmz_queue)
3184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
3185 mqd->cp_hqd_pq_control = tmp;
3186
3187 /* set the wb address whether it's enabled or not */
3188 wb_gpu_addr = prop->rptr_gpu_addr;
3189 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3190 mqd->cp_hqd_pq_rptr_report_addr_hi =
3191 upper_32_bits(wb_gpu_addr) & 0xffff;
3192
3193 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3194 wb_gpu_addr = prop->wptr_gpu_addr;
3195 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3196 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3197
3198 tmp = 0;
3199 /* enable the doorbell if requested */
3200 if (prop->use_doorbell) {
3201 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3202 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3203 DOORBELL_OFFSET, prop->doorbell_index);
3204
3205 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3206 DOORBELL_EN, 1);
3207 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3208 DOORBELL_SOURCE, 0);
3209 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3210 DOORBELL_HIT, 0);
3211 }
3212
3213 mqd->cp_hqd_pq_doorbell_control = tmp;
3214
3215 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3216 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
3217
3218 /* set the vmid for the queue */
3219 mqd->cp_hqd_vmid = 0;
3220
3221 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
3222 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3223 mqd->cp_hqd_persistent_state = tmp;
3224
3225 /* set MIN_IB_AVAIL_SIZE */
3226 tmp = regCP_HQD_IB_CONTROL_DEFAULT;
3227 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3228 mqd->cp_hqd_ib_control = tmp;
3229
3230 /* set static priority for a compute queue/ring */
3231 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3232 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3233
3234 mqd->cp_hqd_active = prop->hqd_active;
3235
3236 /* set UQ fenceaddress */
3237 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3238 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3239
3240 return 0;
3241 }
3242
gfx_v12_0_kiq_init_register(struct amdgpu_ring * ring)3243 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
3244 {
3245 struct amdgpu_device *adev = ring->adev;
3246 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3247 int j;
3248
3249 /* inactivate the queue */
3250 if (amdgpu_sriov_vf(adev))
3251 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3252
3253 /* disable wptr polling */
3254 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3255
3256 /* write the EOP addr */
3257 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3258 mqd->cp_hqd_eop_base_addr_lo);
3259 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3260 mqd->cp_hqd_eop_base_addr_hi);
3261
3262 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3263 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3264 mqd->cp_hqd_eop_control);
3265
3266 /* enable doorbell? */
3267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3268 mqd->cp_hqd_pq_doorbell_control);
3269
3270 /* disable the queue if it's active */
3271 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3272 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3273 for (j = 0; j < adev->usec_timeout; j++) {
3274 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3275 break;
3276 udelay(1);
3277 }
3278 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3279 mqd->cp_hqd_dequeue_request);
3280 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3281 mqd->cp_hqd_pq_rptr);
3282 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3283 mqd->cp_hqd_pq_wptr_lo);
3284 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3285 mqd->cp_hqd_pq_wptr_hi);
3286 }
3287
3288 /* set the pointer to the MQD */
3289 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3290 mqd->cp_mqd_base_addr_lo);
3291 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3292 mqd->cp_mqd_base_addr_hi);
3293
3294 /* set MQD vmid to 0 */
3295 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3296 mqd->cp_mqd_control);
3297
3298 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3299 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3300 mqd->cp_hqd_pq_base_lo);
3301 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3302 mqd->cp_hqd_pq_base_hi);
3303
3304 /* set up the HQD, this is similar to CP_RB0_CNTL */
3305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3306 mqd->cp_hqd_pq_control);
3307
3308 /* set the wb address whether it's enabled or not */
3309 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3310 mqd->cp_hqd_pq_rptr_report_addr_lo);
3311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3312 mqd->cp_hqd_pq_rptr_report_addr_hi);
3313
3314 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3316 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3317 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3318 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3319
3320 /* enable the doorbell if requested */
3321 if (ring->use_doorbell) {
3322 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3323 (adev->doorbell_index.kiq * 2) << 2);
3324 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3325 (adev->doorbell_index.userqueue_end * 2) << 2);
3326 }
3327
3328 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3329 mqd->cp_hqd_pq_doorbell_control);
3330
3331 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3332 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3333 mqd->cp_hqd_pq_wptr_lo);
3334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3335 mqd->cp_hqd_pq_wptr_hi);
3336
3337 /* set the vmid for the queue */
3338 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3339
3340 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3341 mqd->cp_hqd_persistent_state);
3342
3343 /* activate the queue */
3344 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3345 mqd->cp_hqd_active);
3346
3347 if (ring->use_doorbell)
3348 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3349
3350 return 0;
3351 }
3352
gfx_v12_0_kiq_init_queue(struct amdgpu_ring * ring)3353 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)
3354 {
3355 struct amdgpu_device *adev = ring->adev;
3356 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3357 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3358
3359 gfx_v12_0_kiq_setting(ring);
3360
3361 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3362 /* reset MQD to a clean status */
3363 if (adev->gfx.mec.mqd_backup[mqd_idx])
3364 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3365
3366 /* reset ring buffer */
3367 ring->wptr = 0;
3368 amdgpu_ring_clear_ring(ring);
3369
3370 mutex_lock(&adev->srbm_mutex);
3371 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3372 gfx_v12_0_kiq_init_register(ring);
3373 soc24_grbm_select(adev, 0, 0, 0, 0);
3374 mutex_unlock(&adev->srbm_mutex);
3375 } else {
3376 memset((void *)mqd, 0, sizeof(*mqd));
3377 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3378 amdgpu_ring_clear_ring(ring);
3379 mutex_lock(&adev->srbm_mutex);
3380 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3381 amdgpu_ring_init_mqd(ring);
3382 gfx_v12_0_kiq_init_register(ring);
3383 soc24_grbm_select(adev, 0, 0, 0, 0);
3384 mutex_unlock(&adev->srbm_mutex);
3385
3386 if (adev->gfx.mec.mqd_backup[mqd_idx])
3387 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3388 }
3389
3390 return 0;
3391 }
3392
gfx_v12_0_kcq_init_queue(struct amdgpu_ring * ring,bool reset)3393 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
3394 {
3395 struct amdgpu_device *adev = ring->adev;
3396 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3397 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3398
3399 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3400 memset((void *)mqd, 0, sizeof(*mqd));
3401 mutex_lock(&adev->srbm_mutex);
3402 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3403 amdgpu_ring_init_mqd(ring);
3404 soc24_grbm_select(adev, 0, 0, 0, 0);
3405 mutex_unlock(&adev->srbm_mutex);
3406
3407 if (adev->gfx.mec.mqd_backup[mqd_idx])
3408 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3409 } else {
3410 /* restore MQD to a clean status */
3411 if (adev->gfx.mec.mqd_backup[mqd_idx])
3412 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3413 /* reset ring buffer */
3414 ring->wptr = 0;
3415 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3416 amdgpu_ring_clear_ring(ring);
3417 }
3418
3419 return 0;
3420 }
3421
gfx_v12_0_kiq_resume(struct amdgpu_device * adev)3422 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3423 {
3424 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3425 adev->gfx.kiq[0].ring.sched.ready = true;
3426 return 0;
3427 }
3428
gfx_v12_0_kcq_resume(struct amdgpu_device * adev)3429 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3430 {
3431 int i, r;
3432
3433 if (!amdgpu_async_gfx_ring)
3434 gfx_v12_0_cp_compute_enable(adev, true);
3435
3436 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3437 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3438 if (r)
3439 return r;
3440 }
3441
3442 return amdgpu_gfx_enable_kcq(adev, 0);
3443 }
3444
gfx_v12_0_cp_resume(struct amdgpu_device * adev)3445 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
3446 {
3447 int r, i;
3448 struct amdgpu_ring *ring;
3449
3450 if (!(adev->flags & AMD_IS_APU))
3451 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3452
3453 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3454 /* legacy firmware loading */
3455 r = gfx_v12_0_cp_gfx_load_microcode(adev);
3456 if (r)
3457 return r;
3458
3459 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);
3460 if (r)
3461 return r;
3462 }
3463
3464 gfx_v12_0_cp_set_doorbell_range(adev);
3465
3466 if (amdgpu_async_gfx_ring) {
3467 gfx_v12_0_cp_compute_enable(adev, true);
3468 gfx_v12_0_cp_gfx_enable(adev, true);
3469 }
3470
3471 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
3472 r = amdgpu_mes_kiq_hw_init(adev);
3473 else
3474 r = gfx_v12_0_kiq_resume(adev);
3475 if (r)
3476 return r;
3477
3478 r = gfx_v12_0_kcq_resume(adev);
3479 if (r)
3480 return r;
3481
3482 if (!amdgpu_async_gfx_ring) {
3483 r = gfx_v12_0_cp_gfx_resume(adev);
3484 if (r)
3485 return r;
3486 } else {
3487 r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
3488 if (r)
3489 return r;
3490 }
3491
3492 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3493 ring = &adev->gfx.gfx_ring[i];
3494 r = amdgpu_ring_test_helper(ring);
3495 if (r)
3496 return r;
3497 }
3498
3499 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3500 ring = &adev->gfx.compute_ring[i];
3501 r = amdgpu_ring_test_helper(ring);
3502 if (r)
3503 return r;
3504 }
3505
3506 return 0;
3507 }
3508
gfx_v12_0_cp_enable(struct amdgpu_device * adev,bool enable)3509 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
3510 {
3511 gfx_v12_0_cp_gfx_enable(adev, enable);
3512 gfx_v12_0_cp_compute_enable(adev, enable);
3513 }
3514
gfx_v12_0_gfxhub_enable(struct amdgpu_device * adev)3515 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
3516 {
3517 int r;
3518 bool value;
3519
3520 r = adev->gfxhub.funcs->gart_enable(adev);
3521 if (r)
3522 return r;
3523
3524 amdgpu_device_flush_hdp(adev, NULL);
3525
3526 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;
3527
3528 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
3529 /* TODO investigate why this and the hdp flush above is needed,
3530 * are we missing a flush somewhere else? */
3531 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
3532
3533 return 0;
3534 }
3535
get_gb_addr_config(struct amdgpu_device * adev)3536 static int get_gb_addr_config(struct amdgpu_device *adev)
3537 {
3538 u32 gb_addr_config;
3539
3540 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3541 if (gb_addr_config == 0)
3542 return -EINVAL;
3543
3544 adev->gfx.config.gb_addr_config_fields.num_pkrs =
3545 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
3546
3547 adev->gfx.config.gb_addr_config = gb_addr_config;
3548
3549 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
3550 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3551 GB_ADDR_CONFIG, NUM_PIPES);
3552
3553 adev->gfx.config.max_tile_pipes =
3554 adev->gfx.config.gb_addr_config_fields.num_pipes;
3555
3556 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
3557 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3558 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
3559 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
3560 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3561 GB_ADDR_CONFIG, NUM_RB_PER_SE);
3562 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
3563 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3564 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
3565 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
3566 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3567 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
3568
3569 return 0;
3570 }
3571
gfx_v12_0_disable_gpa_mode(struct amdgpu_device * adev)3572 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
3573 {
3574 uint32_t data;
3575
3576 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3577 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
3578 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3579
3580 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3581 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
3582 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3583 }
3584
gfx_v12_0_init_golden_registers(struct amdgpu_device * adev)3585 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3586 {
3587 if (amdgpu_sriov_vf(adev))
3588 return;
3589
3590 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3591 case IP_VERSION(12, 0, 0):
3592 case IP_VERSION(12, 0, 1):
3593 soc15_program_register_sequence(adev,
3594 golden_settings_gc_12_0,
3595 (const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3596
3597 if (adev->rev_id == 0)
3598 soc15_program_register_sequence(adev,
3599 golden_settings_gc_12_0_rev0,
3600 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
3601 break;
3602 default:
3603 break;
3604 }
3605 }
3606
gfx_v12_0_hw_init(struct amdgpu_ip_block * ip_block)3607 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
3608 {
3609 int r;
3610 struct amdgpu_device *adev = ip_block->adev;
3611
3612 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
3613 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3614 /* RLC autoload sequence 1: Program rlc ram */
3615 if (adev->gfx.imu.funcs->program_rlc_ram)
3616 adev->gfx.imu.funcs->program_rlc_ram(adev);
3617 }
3618 /* rlc autoload firmware */
3619 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);
3620 if (r)
3621 return r;
3622 } else {
3623 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3624 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3625 if (adev->gfx.imu.funcs->load_microcode)
3626 adev->gfx.imu.funcs->load_microcode(adev);
3627 if (adev->gfx.imu.funcs->setup_imu)
3628 adev->gfx.imu.funcs->setup_imu(adev);
3629 if (adev->gfx.imu.funcs->start_imu)
3630 adev->gfx.imu.funcs->start_imu(adev);
3631 }
3632
3633 /* disable gpa mode in backdoor loading */
3634 gfx_v12_0_disable_gpa_mode(adev);
3635 }
3636 }
3637
3638 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
3639 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3640 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);
3641 if (r) {
3642 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
3643 return r;
3644 }
3645 }
3646
3647 if (!amdgpu_emu_mode)
3648 gfx_v12_0_init_golden_registers(adev);
3649
3650 adev->gfx.is_poweron = true;
3651
3652 if (get_gb_addr_config(adev))
3653 DRM_WARN("Invalid gb_addr_config !\n");
3654
3655 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
3656 gfx_v12_0_config_gfx_rs64(adev);
3657
3658 r = gfx_v12_0_gfxhub_enable(adev);
3659 if (r)
3660 return r;
3661
3662 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||
3663 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &&
3664 (amdgpu_dpm == 1)) {
3665 /**
3666 * For gfx 12, rlc firmware loading relies on smu firmware is
3667 * loaded firstly, so in direct type, it has to load smc ucode
3668 * here before rlc.
3669 */
3670 r = amdgpu_pm_load_smu_firmware(adev, NULL);
3671 if (r)
3672 return r;
3673 }
3674
3675 gfx_v12_0_constants_init(adev);
3676
3677 if (adev->nbio.funcs->gc_doorbell_init)
3678 adev->nbio.funcs->gc_doorbell_init(adev);
3679
3680 r = gfx_v12_0_rlc_resume(adev);
3681 if (r)
3682 return r;
3683
3684 /*
3685 * init golden registers and rlc resume may override some registers,
3686 * reconfig them here
3687 */
3688 gfx_v12_0_tcp_harvest(adev);
3689
3690 r = gfx_v12_0_cp_resume(adev);
3691 if (r)
3692 return r;
3693
3694 return r;
3695 }
3696
gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device * adev,bool enable)3697 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
3698 bool enable)
3699 {
3700 unsigned int irq_type;
3701 int m, p, r;
3702
3703 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
3704 for (m = 0; m < adev->gfx.me.num_me; m++) {
3705 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
3706 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
3707 if (enable)
3708 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3709 irq_type);
3710 else
3711 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3712 irq_type);
3713 if (r)
3714 return r;
3715 }
3716 }
3717 }
3718
3719 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
3720 for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
3721 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
3722 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
3723 + (m * adev->gfx.mec.num_pipe_per_mec)
3724 + p;
3725 if (enable)
3726 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3727 irq_type);
3728 else
3729 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3730 irq_type);
3731 if (r)
3732 return r;
3733 }
3734 }
3735 }
3736
3737 return 0;
3738 }
3739
gfx_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)3740 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
3741 {
3742 struct amdgpu_device *adev = ip_block->adev;
3743 uint32_t tmp;
3744
3745 cancel_delayed_work_sync(&adev->gfx.idle_work);
3746
3747 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3748 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3749 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
3750 gfx_v12_0_set_userq_eop_interrupts(adev, false);
3751
3752 if (!adev->no_hw_access) {
3753 if (amdgpu_async_gfx_ring) {
3754 if (amdgpu_gfx_disable_kgq(adev, 0))
3755 DRM_ERROR("KGQ disable failed\n");
3756 }
3757
3758 if (amdgpu_gfx_disable_kcq(adev, 0))
3759 DRM_ERROR("KCQ disable failed\n");
3760
3761 amdgpu_mes_kiq_hw_fini(adev);
3762 }
3763
3764 if (amdgpu_sriov_vf(adev)) {
3765 gfx_v12_0_cp_gfx_enable(adev, false);
3766 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
3767 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3768 tmp &= 0xffffff00;
3769 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3770
3771 return 0;
3772 }
3773 gfx_v12_0_cp_enable(adev, false);
3774 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3775
3776 adev->gfxhub.funcs->gart_disable(adev);
3777
3778 adev->gfx.is_poweron = false;
3779
3780 return 0;
3781 }
3782
gfx_v12_0_suspend(struct amdgpu_ip_block * ip_block)3783 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)
3784 {
3785 return gfx_v12_0_hw_fini(ip_block);
3786 }
3787
gfx_v12_0_resume(struct amdgpu_ip_block * ip_block)3788 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
3789 {
3790 return gfx_v12_0_hw_init(ip_block);
3791 }
3792
gfx_v12_0_is_idle(struct amdgpu_ip_block * ip_block)3793 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
3794 {
3795 struct amdgpu_device *adev = ip_block->adev;
3796
3797 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3798 GRBM_STATUS, GUI_ACTIVE))
3799 return false;
3800 else
3801 return true;
3802 }
3803
gfx_v12_0_wait_for_idle(struct amdgpu_ip_block * ip_block)3804 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3805 {
3806 unsigned i;
3807 u32 tmp;
3808 struct amdgpu_device *adev = ip_block->adev;
3809
3810 for (i = 0; i < adev->usec_timeout; i++) {
3811 /* read MC_STATUS */
3812 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3813 GRBM_STATUS__GUI_ACTIVE_MASK;
3814
3815 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3816 return 0;
3817 udelay(1);
3818 }
3819 return -ETIMEDOUT;
3820 }
3821
gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device * adev)3822 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3823 {
3824 uint64_t clock = 0;
3825
3826 if (adev->smuio.funcs &&
3827 adev->smuio.funcs->get_gpu_clock_counter)
3828 clock = adev->smuio.funcs->get_gpu_clock_counter(adev);
3829 else
3830 dev_warn(adev->dev, "query gpu clock counter is not supported\n");
3831
3832 return clock;
3833 }
3834
gfx_v12_0_early_init(struct amdgpu_ip_block * ip_block)3835 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
3836 {
3837 struct amdgpu_device *adev = ip_block->adev;
3838
3839 switch (amdgpu_user_queue) {
3840 case -1:
3841 case 0:
3842 default:
3843 adev->gfx.disable_kq = false;
3844 adev->gfx.disable_uq = true;
3845 break;
3846 case 1:
3847 adev->gfx.disable_kq = false;
3848 adev->gfx.disable_uq = false;
3849 break;
3850 case 2:
3851 adev->gfx.disable_kq = true;
3852 adev->gfx.disable_uq = false;
3853 break;
3854 }
3855
3856 adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
3857
3858 if (adev->gfx.disable_kq) {
3859 adev->gfx.num_gfx_rings = 0;
3860 adev->gfx.num_compute_rings = 0;
3861 } else {
3862 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
3863 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3864 AMDGPU_MAX_COMPUTE_RINGS);
3865 }
3866
3867 gfx_v12_0_set_kiq_pm4_funcs(adev);
3868 gfx_v12_0_set_ring_funcs(adev);
3869 gfx_v12_0_set_irq_funcs(adev);
3870 gfx_v12_0_set_rlc_funcs(adev);
3871 gfx_v12_0_set_mqd_funcs(adev);
3872 gfx_v12_0_set_imu_funcs(adev);
3873
3874 gfx_v12_0_init_rlcg_reg_access_ctrl(adev);
3875
3876 return gfx_v12_0_init_microcode(adev);
3877 }
3878
gfx_v12_0_late_init(struct amdgpu_ip_block * ip_block)3879 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
3880 {
3881 struct amdgpu_device *adev = ip_block->adev;
3882 int r;
3883
3884 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3885 if (r)
3886 return r;
3887
3888 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3889 if (r)
3890 return r;
3891
3892 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
3893 if (r)
3894 return r;
3895
3896 r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
3897 if (r)
3898 return r;
3899
3900 return 0;
3901 }
3902
gfx_v12_0_is_rlc_enabled(struct amdgpu_device * adev)3903 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
3904 {
3905 uint32_t rlc_cntl;
3906
3907 /* if RLC is not enabled, do nothing */
3908 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3909 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3910 }
3911
gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)3912 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,
3913 int xcc_id)
3914 {
3915 uint32_t data;
3916 unsigned i;
3917
3918 data = RLC_SAFE_MODE__CMD_MASK;
3919 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3920
3921 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3922
3923 /* wait for RLC_SAFE_MODE */
3924 for (i = 0; i < adev->usec_timeout; i++) {
3925 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3926 RLC_SAFE_MODE, CMD))
3927 break;
3928 udelay(1);
3929 }
3930 }
3931
gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)3932 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
3933 int xcc_id)
3934 {
3935 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3936 }
3937
gfx_v12_0_update_perf_clk(struct amdgpu_device * adev,bool enable)3938 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
3939 bool enable)
3940 {
3941 uint32_t def, data;
3942
3943 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
3944 return;
3945
3946 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3947
3948 if (enable)
3949 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3950 else
3951 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3952
3953 if (def != data)
3954 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
3955 }
3956
gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned vmid)3957 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
3958 struct amdgpu_ring *ring,
3959 unsigned vmid)
3960 {
3961 u32 reg, data;
3962
3963 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3964 if (amdgpu_sriov_is_pp_one_vf(adev))
3965 data = RREG32_NO_KIQ(reg);
3966 else
3967 data = RREG32(reg);
3968
3969 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
3970 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
3971
3972 if (amdgpu_sriov_is_pp_one_vf(adev))
3973 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
3974 else
3975 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
3976
3977 if (ring
3978 && amdgpu_sriov_is_pp_one_vf(adev)
3979 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
3980 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
3981 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3982 amdgpu_ring_emit_wreg(ring, reg, data);
3983 }
3984 }
3985
3986 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {
3987 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled,
3988 .set_safe_mode = gfx_v12_0_set_safe_mode,
3989 .unset_safe_mode = gfx_v12_0_unset_safe_mode,
3990 .init = gfx_v12_0_rlc_init,
3991 .get_csb_size = gfx_v12_0_get_csb_size,
3992 .get_csb_buffer = gfx_v12_0_get_csb_buffer,
3993 .resume = gfx_v12_0_rlc_resume,
3994 .stop = gfx_v12_0_rlc_stop,
3995 .reset = gfx_v12_0_rlc_reset,
3996 .start = gfx_v12_0_rlc_start,
3997 .update_spm_vmid = gfx_v12_0_update_spm_vmid,
3998 };
3999
4000 #if 0
4001 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
4002 {
4003 /* TODO */
4004 }
4005
4006 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
4007 {
4008 /* TODO */
4009 }
4010 #endif
4011
gfx_v12_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)4012 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4013 enum amd_powergating_state state)
4014 {
4015 struct amdgpu_device *adev = ip_block->adev;
4016 bool enable = (state == AMD_PG_STATE_GATE);
4017
4018 if (amdgpu_sriov_vf(adev))
4019 return 0;
4020
4021 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4022 case IP_VERSION(12, 0, 0):
4023 case IP_VERSION(12, 0, 1):
4024 amdgpu_gfx_off_ctrl(adev, enable);
4025 break;
4026 default:
4027 break;
4028 }
4029
4030 return 0;
4031 }
4032
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)4033 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4034 bool enable)
4035 {
4036 uint32_t def, data;
4037
4038 if (!(adev->cg_flags &
4039 (AMD_CG_SUPPORT_GFX_CGCG |
4040 AMD_CG_SUPPORT_GFX_CGLS |
4041 AMD_CG_SUPPORT_GFX_3D_CGCG |
4042 AMD_CG_SUPPORT_GFX_3D_CGLS)))
4043 return;
4044
4045 if (enable) {
4046 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4047
4048 /* unset CGCG override */
4049 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4050 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4052 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4053 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4054 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4055 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4056
4057 /* update CGCG override bits */
4058 if (def != data)
4059 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4060
4061 /* enable cgcg FSM(0x0000363F) */
4062 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4063
4064 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4065 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4066 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4067 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4068 }
4069
4070 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4071 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4072 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4073 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4074 }
4075
4076 if (def != data)
4077 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4078
4079 /* Program RLC_CGCG_CGLS_CTRL_3D */
4080 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4081
4082 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4083 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4084 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4085 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4086 }
4087
4088 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4089 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4090 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4091 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4092 }
4093
4094 if (def != data)
4095 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4096
4097 /* set IDLE_POLL_COUNT(0x00900100) */
4098 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4099
4100 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4101 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4102 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4103
4104 if (def != data)
4105 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4106
4107 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4108 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4109 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4110 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4111 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4112 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4113
4114 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4115 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4116 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4117
4118 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4119 if (adev->sdma.num_instances > 1) {
4120 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4121 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4122 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4123 }
4124 } else {
4125 /* Program RLC_CGCG_CGLS_CTRL */
4126 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4127
4128 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4129 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4130
4131 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4132 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4133
4134 if (def != data)
4135 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4136
4137 /* Program RLC_CGCG_CGLS_CTRL_3D */
4138 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4139
4140 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4141 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4142 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4143 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4144
4145 if (def != data)
4146 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4147 }
4148 }
4149
gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)4150 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4151 bool enable)
4152 {
4153 uint32_t data, def;
4154 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4155 return;
4156
4157 /* It is disabled by HW by default */
4158 if (enable) {
4159 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4160 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4161 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4162
4163 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4164 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4165 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4166
4167 if (def != data)
4168 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4169 }
4170 } else {
4171 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4172 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4173
4174 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4175 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4176 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4177
4178 if (def != data)
4179 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4180 }
4181 }
4182 }
4183
gfx_v12_0_update_repeater_fgcg(struct amdgpu_device * adev,bool enable)4184 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
4185 bool enable)
4186 {
4187 uint32_t def, data;
4188
4189 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4190 return;
4191
4192 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4193
4194 if (enable)
4195 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4196 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
4197 else
4198 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4199 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
4200
4201 if (def != data)
4202 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4203 }
4204
gfx_v12_0_update_sram_fgcg(struct amdgpu_device * adev,bool enable)4205 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,
4206 bool enable)
4207 {
4208 uint32_t def, data;
4209
4210 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4211 return;
4212
4213 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4214
4215 if (enable)
4216 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4217 else
4218 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4219
4220 if (def != data)
4221 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4222 }
4223
gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)4224 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4225 bool enable)
4226 {
4227 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4228
4229 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);
4230
4231 gfx_v12_0_update_medium_grain_clock_gating(adev, enable);
4232
4233 gfx_v12_0_update_repeater_fgcg(adev, enable);
4234
4235 gfx_v12_0_update_sram_fgcg(adev, enable);
4236
4237 gfx_v12_0_update_perf_clk(adev, enable);
4238
4239 if (adev->cg_flags &
4240 (AMD_CG_SUPPORT_GFX_MGCG |
4241 AMD_CG_SUPPORT_GFX_CGLS |
4242 AMD_CG_SUPPORT_GFX_CGCG |
4243 AMD_CG_SUPPORT_GFX_3D_CGCG |
4244 AMD_CG_SUPPORT_GFX_3D_CGLS))
4245 gfx_v12_0_enable_gui_idle_interrupt(adev, enable);
4246
4247 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4248
4249 return 0;
4250 }
4251
gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)4252 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4253 enum amd_clockgating_state state)
4254 {
4255 struct amdgpu_device *adev = ip_block->adev;
4256
4257 if (amdgpu_sriov_vf(adev))
4258 return 0;
4259
4260 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4261 case IP_VERSION(12, 0, 0):
4262 case IP_VERSION(12, 0, 1):
4263 gfx_v12_0_update_gfx_clock_gating(adev,
4264 state == AMD_CG_STATE_GATE);
4265 break;
4266 default:
4267 break;
4268 }
4269
4270 return 0;
4271 }
4272
gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)4273 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
4274 {
4275 struct amdgpu_device *adev = ip_block->adev;
4276 int data;
4277
4278 /* AMD_CG_SUPPORT_GFX_MGCG */
4279 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4280 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4281 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4282
4283 /* AMD_CG_SUPPORT_REPEATER_FGCG */
4284 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
4285 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
4286
4287 /* AMD_CG_SUPPORT_GFX_FGCG */
4288 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
4289 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
4290
4291 /* AMD_CG_SUPPORT_GFX_PERF_CLK */
4292 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
4293 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
4294
4295 /* AMD_CG_SUPPORT_GFX_CGCG */
4296 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4297 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4298 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4299
4300 /* AMD_CG_SUPPORT_GFX_CGLS */
4301 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4302 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4303
4304 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4305 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4306 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4307 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4308
4309 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4310 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4311 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4312 }
4313
gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)4314 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4315 {
4316 /* gfx12 is 32bit rptr*/
4317 return *(uint32_t *)ring->rptr_cpu_addr;
4318 }
4319
gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)4320 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4321 {
4322 struct amdgpu_device *adev = ring->adev;
4323 u64 wptr;
4324
4325 /* XXX check if swapping is necessary on BE */
4326 if (ring->use_doorbell) {
4327 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4328 } else {
4329 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4330 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4331 }
4332
4333 return wptr;
4334 }
4335
gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)4336 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4337 {
4338 struct amdgpu_device *adev = ring->adev;
4339
4340 if (ring->use_doorbell) {
4341 /* XXX check if swapping is necessary on BE */
4342 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4343 ring->wptr);
4344 WDOORBELL64(ring->doorbell_index, ring->wptr);
4345 } else {
4346 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4347 lower_32_bits(ring->wptr));
4348 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4349 upper_32_bits(ring->wptr));
4350 }
4351 }
4352
gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4353 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4354 {
4355 /* gfx12 hardware is 32bit rptr */
4356 return *(uint32_t *)ring->rptr_cpu_addr;
4357 }
4358
gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4359 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4360 {
4361 u64 wptr;
4362
4363 /* XXX check if swapping is necessary on BE */
4364 if (ring->use_doorbell)
4365 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4366 else
4367 BUG();
4368 return wptr;
4369 }
4370
gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4371 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4372 {
4373 struct amdgpu_device *adev = ring->adev;
4374
4375 /* XXX check if swapping is necessary on BE */
4376 if (ring->use_doorbell) {
4377 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4378 ring->wptr);
4379 WDOORBELL64(ring->doorbell_index, ring->wptr);
4380 } else {
4381 BUG(); /* only DOORBELL method supported on gfx12 now */
4382 }
4383 }
4384
gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)4385 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4386 {
4387 struct amdgpu_device *adev = ring->adev;
4388 u32 ref_and_mask, reg_mem_engine;
4389 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4390
4391 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4392 switch (ring->me) {
4393 case 1:
4394 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4395 break;
4396 case 2:
4397 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4398 break;
4399 default:
4400 return;
4401 }
4402 reg_mem_engine = 0;
4403 } else {
4404 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4405 reg_mem_engine = 1; /* pfp */
4406 }
4407
4408 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4409 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4410 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4411 ref_and_mask, ref_and_mask, 0x20);
4412 }
4413
gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4414 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4415 struct amdgpu_job *job,
4416 struct amdgpu_ib *ib,
4417 uint32_t flags)
4418 {
4419 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4420 u32 header, control = 0;
4421
4422 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
4423
4424 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4425
4426 control |= ib->length_dw | (vmid << 24);
4427
4428 amdgpu_ring_write(ring, header);
4429 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4430 amdgpu_ring_write(ring,
4431 #ifdef __BIG_ENDIAN
4432 (2 << 0) |
4433 #endif
4434 lower_32_bits(ib->gpu_addr));
4435 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4436 amdgpu_ring_write(ring, control);
4437 }
4438
gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4439 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4440 struct amdgpu_job *job,
4441 struct amdgpu_ib *ib,
4442 uint32_t flags)
4443 {
4444 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4445 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4446
4447 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4448 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4449 amdgpu_ring_write(ring,
4450 #ifdef __BIG_ENDIAN
4451 (2 << 0) |
4452 #endif
4453 lower_32_bits(ib->gpu_addr));
4454 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4455 amdgpu_ring_write(ring, control);
4456 }
4457
gfx_v12_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4458 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4459 u64 seq, unsigned flags)
4460 {
4461 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4462 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4463
4464 /* RELEASE_MEM - flush caches, send int */
4465 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4466 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4467 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4468 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4469 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4470 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4471 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4472 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4473
4474 /*
4475 * the address should be Qword aligned if 64bit write, Dword
4476 * aligned if only send 32bit data low (discard data high)
4477 */
4478 if (write64bit)
4479 BUG_ON(addr & 0x7);
4480 else
4481 BUG_ON(addr & 0x3);
4482 amdgpu_ring_write(ring, lower_32_bits(addr));
4483 amdgpu_ring_write(ring, upper_32_bits(addr));
4484 amdgpu_ring_write(ring, lower_32_bits(seq));
4485 amdgpu_ring_write(ring, upper_32_bits(seq));
4486 amdgpu_ring_write(ring, 0);
4487 }
4488
gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4489 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4490 {
4491 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4492 uint32_t seq = ring->fence_drv.sync_seq;
4493 uint64_t addr = ring->fence_drv.gpu_addr;
4494
4495 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4496 upper_32_bits(addr), seq, 0xffffffff, 4);
4497 }
4498
gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)4499 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
4500 uint16_t pasid, uint32_t flush_type,
4501 bool all_hub, uint8_t dst_sel)
4502 {
4503 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
4504 amdgpu_ring_write(ring,
4505 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
4506 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
4507 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
4508 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
4509 }
4510
gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4511 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4512 unsigned vmid, uint64_t pd_addr)
4513 {
4514 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4515
4516 /* compute doesn't have PFP */
4517 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4518 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4519 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4520 amdgpu_ring_write(ring, 0x0);
4521 }
4522 }
4523
gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4524 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4525 u64 seq, unsigned int flags)
4526 {
4527 struct amdgpu_device *adev = ring->adev;
4528
4529 /* we only allocate 32bit for each seq wb address */
4530 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4531
4532 /* write fence seq to the "addr" */
4533 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4534 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4535 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4536 amdgpu_ring_write(ring, lower_32_bits(addr));
4537 amdgpu_ring_write(ring, upper_32_bits(addr));
4538 amdgpu_ring_write(ring, lower_32_bits(seq));
4539
4540 if (flags & AMDGPU_FENCE_FLAG_INT) {
4541 /* set register to trigger INT */
4542 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4543 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4544 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4545 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4546 amdgpu_ring_write(ring, 0);
4547 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4548 }
4549 }
4550
gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4551 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4552 uint32_t flags)
4553 {
4554 uint32_t dw2 = 0;
4555
4556 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4557 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4558 /* set load_global_config & load_global_uconfig */
4559 dw2 |= 0x8001;
4560 /* set load_cs_sh_regs */
4561 dw2 |= 0x01000000;
4562 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4563 dw2 |= 0x10002;
4564 }
4565
4566 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4567 amdgpu_ring_write(ring, dw2);
4568 amdgpu_ring_write(ring, 0);
4569 }
4570
gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)4571 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
4572 uint64_t addr)
4573 {
4574 unsigned ret;
4575
4576 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4577 amdgpu_ring_write(ring, lower_32_bits(addr));
4578 amdgpu_ring_write(ring, upper_32_bits(addr));
4579 /* discard following DWs if *cond_exec_gpu_addr==0 */
4580 amdgpu_ring_write(ring, 0);
4581 ret = ring->wptr & ring->buf_mask;
4582 /* patch dummy value later */
4583 amdgpu_ring_write(ring, 0);
4584
4585 return ret;
4586 }
4587
gfx_v12_0_ring_preempt_ib(struct amdgpu_ring * ring)4588 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
4589 {
4590 int i, r = 0;
4591 struct amdgpu_device *adev = ring->adev;
4592 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4593 struct amdgpu_ring *kiq_ring = &kiq->ring;
4594 unsigned long flags;
4595
4596 if (adev->enable_mes)
4597 return -EINVAL;
4598
4599 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4600 return -EINVAL;
4601
4602 spin_lock_irqsave(&kiq->ring_lock, flags);
4603
4604 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
4605 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4606 return -ENOMEM;
4607 }
4608
4609 /* assert preemption condition */
4610 amdgpu_ring_set_preempt_cond_exec(ring, false);
4611
4612 /* assert IB preemption, emit the trailing fence */
4613 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4614 ring->trail_fence_gpu_addr,
4615 ++ring->trail_seq);
4616 amdgpu_ring_commit(kiq_ring);
4617
4618 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4619
4620 /* poll the trailing fence */
4621 for (i = 0; i < adev->usec_timeout; i++) {
4622 if (ring->trail_seq ==
4623 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4624 break;
4625 udelay(1);
4626 }
4627
4628 if (i >= adev->usec_timeout) {
4629 r = -EINVAL;
4630 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4631 }
4632
4633 /* deassert preemption condition */
4634 amdgpu_ring_set_preempt_cond_exec(ring, true);
4635 return r;
4636 }
4637
gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)4638 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring,
4639 bool start,
4640 bool secure)
4641 {
4642 uint32_t v = secure ? FRAME_TMZ : 0;
4643
4644 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4645 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
4646 }
4647
gfx_v12_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)4648 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
4649 uint32_t reg_val_offs)
4650 {
4651 struct amdgpu_device *adev = ring->adev;
4652
4653 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4654 amdgpu_ring_write(ring, 0 | /* src: register*/
4655 (5 << 8) | /* dst: memory */
4656 (1 << 20)); /* write confirm */
4657 amdgpu_ring_write(ring, reg);
4658 amdgpu_ring_write(ring, 0);
4659 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4660 reg_val_offs * 4));
4661 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4662 reg_val_offs * 4));
4663 }
4664
gfx_v12_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4665 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,
4666 uint32_t reg,
4667 uint32_t val)
4668 {
4669 uint32_t cmd = 0;
4670
4671 switch (ring->funcs->type) {
4672 case AMDGPU_RING_TYPE_GFX:
4673 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4674 break;
4675 case AMDGPU_RING_TYPE_KIQ:
4676 cmd = (1 << 16); /* no inc addr */
4677 break;
4678 default:
4679 cmd = WR_CONFIRM;
4680 break;
4681 }
4682 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4683 amdgpu_ring_write(ring, cmd);
4684 amdgpu_ring_write(ring, reg);
4685 amdgpu_ring_write(ring, 0);
4686 amdgpu_ring_write(ring, val);
4687 }
4688
gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4689 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4690 uint32_t val, uint32_t mask)
4691 {
4692 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4693 }
4694
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4695 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4696 uint32_t reg0, uint32_t reg1,
4697 uint32_t ref, uint32_t mask)
4698 {
4699 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4700
4701 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4702 ref, mask, 0x20);
4703 }
4704
4705 static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)4706 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4707 uint32_t me, uint32_t pipe,
4708 enum amdgpu_interrupt_state state)
4709 {
4710 uint32_t cp_int_cntl, cp_int_cntl_reg;
4711
4712 if (!me) {
4713 switch (pipe) {
4714 case 0:
4715 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4716 break;
4717 default:
4718 DRM_DEBUG("invalid pipe %d\n", pipe);
4719 return;
4720 }
4721 } else {
4722 DRM_DEBUG("invalid me %d\n", me);
4723 return;
4724 }
4725
4726 switch (state) {
4727 case AMDGPU_IRQ_STATE_DISABLE:
4728 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4729 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4730 TIME_STAMP_INT_ENABLE, 0);
4731 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4732 GENERIC0_INT_ENABLE, 0);
4733 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4734 break;
4735 case AMDGPU_IRQ_STATE_ENABLE:
4736 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4737 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4738 TIME_STAMP_INT_ENABLE, 1);
4739 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4740 GENERIC0_INT_ENABLE, 1);
4741 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4742 break;
4743 default:
4744 break;
4745 }
4746 }
4747
gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4748 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4749 int me, int pipe,
4750 enum amdgpu_interrupt_state state)
4751 {
4752 u32 mec_int_cntl, mec_int_cntl_reg;
4753
4754 /*
4755 * amdgpu controls only the first MEC. That's why this function only
4756 * handles the setting of interrupts for this specific MEC. All other
4757 * pipes' interrupts are set by amdkfd.
4758 */
4759
4760 if (me == 1) {
4761 switch (pipe) {
4762 case 0:
4763 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4764 break;
4765 case 1:
4766 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4767 break;
4768 default:
4769 DRM_DEBUG("invalid pipe %d\n", pipe);
4770 return;
4771 }
4772 } else {
4773 DRM_DEBUG("invalid me %d\n", me);
4774 return;
4775 }
4776
4777 switch (state) {
4778 case AMDGPU_IRQ_STATE_DISABLE:
4779 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4780 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4781 TIME_STAMP_INT_ENABLE, 0);
4782 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4783 GENERIC0_INT_ENABLE, 0);
4784 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4785 break;
4786 case AMDGPU_IRQ_STATE_ENABLE:
4787 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4788 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4789 TIME_STAMP_INT_ENABLE, 1);
4790 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4791 GENERIC0_INT_ENABLE, 1);
4792 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4793 break;
4794 default:
4795 break;
4796 }
4797 }
4798
gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4799 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4800 struct amdgpu_irq_src *src,
4801 unsigned type,
4802 enum amdgpu_interrupt_state state)
4803 {
4804 switch (type) {
4805 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4806 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4807 break;
4808 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4809 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4810 break;
4811 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4812 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4813 break;
4814 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4815 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4816 break;
4817 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4818 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4819 break;
4820 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4821 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4822 break;
4823 default:
4824 break;
4825 }
4826 return 0;
4827 }
4828
gfx_v12_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4829 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
4830 struct amdgpu_irq_src *source,
4831 struct amdgpu_iv_entry *entry)
4832 {
4833 u32 doorbell_offset = entry->src_data[0];
4834 u8 me_id, pipe_id, queue_id;
4835 struct amdgpu_ring *ring;
4836 int i;
4837
4838 DRM_DEBUG("IH: CP EOP\n");
4839
4840 if (adev->enable_mes && doorbell_offset) {
4841 struct amdgpu_userq_fence_driver *fence_drv = NULL;
4842 struct xarray *xa = &adev->userq_xa;
4843 unsigned long flags;
4844
4845 xa_lock_irqsave(xa, flags);
4846 fence_drv = xa_load(xa, doorbell_offset);
4847 if (fence_drv)
4848 amdgpu_userq_fence_driver_process(fence_drv);
4849 xa_unlock_irqrestore(xa, flags);
4850 } else {
4851 me_id = (entry->ring_id & 0x0c) >> 2;
4852 pipe_id = (entry->ring_id & 0x03) >> 0;
4853 queue_id = (entry->ring_id & 0x70) >> 4;
4854
4855 switch (me_id) {
4856 case 0:
4857 if (pipe_id == 0)
4858 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4859 else
4860 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4861 break;
4862 case 1:
4863 case 2:
4864 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4865 ring = &adev->gfx.compute_ring[i];
4866 /* Per-queue interrupt is supported for MEC starting from VI.
4867 * The interrupt can only be enabled/disabled per pipe instead
4868 * of per queue.
4869 */
4870 if ((ring->me == me_id) &&
4871 (ring->pipe == pipe_id) &&
4872 (ring->queue == queue_id))
4873 amdgpu_fence_process(ring);
4874 }
4875 break;
4876 }
4877 }
4878
4879 return 0;
4880 }
4881
gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4882 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4883 struct amdgpu_irq_src *source,
4884 unsigned int type,
4885 enum amdgpu_interrupt_state state)
4886 {
4887 u32 cp_int_cntl_reg, cp_int_cntl;
4888 int i, j;
4889
4890 switch (state) {
4891 case AMDGPU_IRQ_STATE_DISABLE:
4892 case AMDGPU_IRQ_STATE_ENABLE:
4893 for (i = 0; i < adev->gfx.me.num_me; i++) {
4894 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4895 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4896
4897 if (cp_int_cntl_reg) {
4898 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4899 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4900 PRIV_REG_INT_ENABLE,
4901 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4902 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4903 }
4904 }
4905 }
4906 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4907 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4908 /* MECs start at 1 */
4909 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4910
4911 if (cp_int_cntl_reg) {
4912 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4913 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4914 PRIV_REG_INT_ENABLE,
4915 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4916 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4917 }
4918 }
4919 }
4920 break;
4921 default:
4922 break;
4923 }
4924
4925 return 0;
4926 }
4927
gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4928 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
4929 struct amdgpu_irq_src *source,
4930 unsigned type,
4931 enum amdgpu_interrupt_state state)
4932 {
4933 u32 cp_int_cntl_reg, cp_int_cntl;
4934 int i, j;
4935
4936 switch (state) {
4937 case AMDGPU_IRQ_STATE_DISABLE:
4938 case AMDGPU_IRQ_STATE_ENABLE:
4939 for (i = 0; i < adev->gfx.me.num_me; i++) {
4940 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4941 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4942
4943 if (cp_int_cntl_reg) {
4944 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4945 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4946 OPCODE_ERROR_INT_ENABLE,
4947 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4948 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4949 }
4950 }
4951 }
4952 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4953 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4954 /* MECs start at 1 */
4955 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4956
4957 if (cp_int_cntl_reg) {
4958 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4959 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4960 OPCODE_ERROR_INT_ENABLE,
4961 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4962 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4963 }
4964 }
4965 }
4966 break;
4967 default:
4968 break;
4969 }
4970 return 0;
4971 }
4972
gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4973 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4974 struct amdgpu_irq_src *source,
4975 unsigned int type,
4976 enum amdgpu_interrupt_state state)
4977 {
4978 u32 cp_int_cntl_reg, cp_int_cntl;
4979 int i, j;
4980
4981 switch (state) {
4982 case AMDGPU_IRQ_STATE_DISABLE:
4983 case AMDGPU_IRQ_STATE_ENABLE:
4984 for (i = 0; i < adev->gfx.me.num_me; i++) {
4985 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4986 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4987
4988 if (cp_int_cntl_reg) {
4989 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4990 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4991 PRIV_INSTR_INT_ENABLE,
4992 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4993 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4994 }
4995 }
4996 }
4997 break;
4998 default:
4999 break;
5000 }
5001
5002 return 0;
5003 }
5004
gfx_v12_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)5005 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
5006 struct amdgpu_iv_entry *entry)
5007 {
5008 u8 me_id, pipe_id, queue_id;
5009 struct amdgpu_ring *ring;
5010 int i;
5011
5012 me_id = (entry->ring_id & 0x0c) >> 2;
5013 pipe_id = (entry->ring_id & 0x03) >> 0;
5014 queue_id = (entry->ring_id & 0x70) >> 4;
5015
5016 if (!adev->gfx.disable_kq) {
5017 switch (me_id) {
5018 case 0:
5019 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5020 ring = &adev->gfx.gfx_ring[i];
5021 if (ring->me == me_id && ring->pipe == pipe_id &&
5022 ring->queue == queue_id)
5023 drm_sched_fault(&ring->sched);
5024 }
5025 break;
5026 case 1:
5027 case 2:
5028 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5029 ring = &adev->gfx.compute_ring[i];
5030 if (ring->me == me_id && ring->pipe == pipe_id &&
5031 ring->queue == queue_id)
5032 drm_sched_fault(&ring->sched);
5033 }
5034 break;
5035 default:
5036 BUG();
5037 break;
5038 }
5039 }
5040 }
5041
gfx_v12_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5042 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
5043 struct amdgpu_irq_src *source,
5044 struct amdgpu_iv_entry *entry)
5045 {
5046 DRM_ERROR("Illegal register access in command stream\n");
5047 gfx_v12_0_handle_priv_fault(adev, entry);
5048 return 0;
5049 }
5050
gfx_v12_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5051 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
5052 struct amdgpu_irq_src *source,
5053 struct amdgpu_iv_entry *entry)
5054 {
5055 DRM_ERROR("Illegal opcode in command stream \n");
5056 gfx_v12_0_handle_priv_fault(adev, entry);
5057 return 0;
5058 }
5059
gfx_v12_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5060 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
5061 struct amdgpu_irq_src *source,
5062 struct amdgpu_iv_entry *entry)
5063 {
5064 DRM_ERROR("Illegal instruction in command stream\n");
5065 gfx_v12_0_handle_priv_fault(adev, entry);
5066 return 0;
5067 }
5068
gfx_v12_0_emit_mem_sync(struct amdgpu_ring * ring)5069 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)
5070 {
5071 const unsigned int gcr_cntl =
5072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
5073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
5074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
5079 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
5080
5081 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
5082 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
5083 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
5084 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5085 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
5086 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5087 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5088 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
5089 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
5090 }
5091
gfx_v12_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)5092 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
5093 {
5094 /* Header itself is a NOP packet */
5095 if (num_nop == 1) {
5096 amdgpu_ring_write(ring, ring->funcs->nop);
5097 return;
5098 }
5099
5100 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
5101 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
5102
5103 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
5104 amdgpu_ring_insert_nop(ring, num_nop - 1);
5105 }
5106
gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)5107 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
5108 {
5109 /* Emit the cleaner shader */
5110 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
5111 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
5112 }
5113
gfx_v12_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)5114 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
5115 {
5116 struct amdgpu_device *adev = ip_block->adev;
5117 uint32_t i, j, k, reg, index = 0;
5118 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5119
5120 if (!adev->gfx.ip_dump_core)
5121 return;
5122
5123 for (i = 0; i < reg_count; i++)
5124 drm_printf(p, "%-50s \t 0x%08x\n",
5125 gc_reg_list_12_0[i].reg_name,
5126 adev->gfx.ip_dump_core[i]);
5127
5128 /* print compute queue registers for all instances */
5129 if (!adev->gfx.ip_dump_compute_queues)
5130 return;
5131
5132 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5133 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
5134 adev->gfx.mec.num_mec,
5135 adev->gfx.mec.num_pipe_per_mec,
5136 adev->gfx.mec.num_queue_per_pipe);
5137
5138 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5139 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5140 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5141 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
5142 for (reg = 0; reg < reg_count; reg++) {
5143 drm_printf(p, "%-50s \t 0x%08x\n",
5144 gc_cp_reg_list_12[reg].reg_name,
5145 adev->gfx.ip_dump_compute_queues[index + reg]);
5146 }
5147 index += reg_count;
5148 }
5149 }
5150 }
5151
5152 /* print gfx queue registers for all instances */
5153 if (!adev->gfx.ip_dump_gfx_queues)
5154 return;
5155
5156 index = 0;
5157 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5158 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
5159 adev->gfx.me.num_me,
5160 adev->gfx.me.num_pipe_per_me,
5161 adev->gfx.me.num_queue_per_pipe);
5162
5163 for (i = 0; i < adev->gfx.me.num_me; i++) {
5164 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5165 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5166 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
5167 for (reg = 0; reg < reg_count; reg++) {
5168 drm_printf(p, "%-50s \t 0x%08x\n",
5169 gc_gfx_queue_reg_list_12[reg].reg_name,
5170 adev->gfx.ip_dump_gfx_queues[index + reg]);
5171 }
5172 index += reg_count;
5173 }
5174 }
5175 }
5176 }
5177
gfx_v12_ip_dump(struct amdgpu_ip_block * ip_block)5178 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)
5179 {
5180 struct amdgpu_device *adev = ip_block->adev;
5181 uint32_t i, j, k, reg, index = 0;
5182 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5183
5184 if (!adev->gfx.ip_dump_core)
5185 return;
5186
5187 amdgpu_gfx_off_ctrl(adev, false);
5188 for (i = 0; i < reg_count; i++)
5189 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
5190 amdgpu_gfx_off_ctrl(adev, true);
5191
5192 /* dump compute queue registers for all instances */
5193 if (!adev->gfx.ip_dump_compute_queues)
5194 return;
5195
5196 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5197 amdgpu_gfx_off_ctrl(adev, false);
5198 mutex_lock(&adev->srbm_mutex);
5199 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5200 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5201 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5202 /* ME0 is for GFX so start from 1 for CP */
5203 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
5204 for (reg = 0; reg < reg_count; reg++) {
5205 adev->gfx.ip_dump_compute_queues[index + reg] =
5206 RREG32(SOC15_REG_ENTRY_OFFSET(
5207 gc_cp_reg_list_12[reg]));
5208 }
5209 index += reg_count;
5210 }
5211 }
5212 }
5213 soc24_grbm_select(adev, 0, 0, 0, 0);
5214 mutex_unlock(&adev->srbm_mutex);
5215 amdgpu_gfx_off_ctrl(adev, true);
5216
5217 /* dump gfx queue registers for all instances */
5218 if (!adev->gfx.ip_dump_gfx_queues)
5219 return;
5220
5221 index = 0;
5222 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5223 amdgpu_gfx_off_ctrl(adev, false);
5224 mutex_lock(&adev->srbm_mutex);
5225 for (i = 0; i < adev->gfx.me.num_me; i++) {
5226 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5227 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5228 soc24_grbm_select(adev, i, j, k, 0);
5229
5230 for (reg = 0; reg < reg_count; reg++) {
5231 adev->gfx.ip_dump_gfx_queues[index + reg] =
5232 RREG32(SOC15_REG_ENTRY_OFFSET(
5233 gc_gfx_queue_reg_list_12[reg]));
5234 }
5235 index += reg_count;
5236 }
5237 }
5238 }
5239 soc24_grbm_select(adev, 0, 0, 0, 0);
5240 mutex_unlock(&adev->srbm_mutex);
5241 amdgpu_gfx_off_ctrl(adev, true);
5242 }
5243
gfx_v12_pipe_reset_support(struct amdgpu_device * adev)5244 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)
5245 {
5246 /* Disable the pipe reset until the CPFW fully support it.*/
5247 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
5248 return false;
5249 }
5250
gfx_v12_reset_gfx_pipe(struct amdgpu_ring * ring)5251 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring)
5252 {
5253 struct amdgpu_device *adev = ring->adev;
5254 uint32_t reset_pipe = 0, clean_pipe = 0;
5255 int r;
5256
5257 if (!gfx_v12_pipe_reset_support(adev))
5258 return -EOPNOTSUPP;
5259
5260 gfx_v12_0_set_safe_mode(adev, 0);
5261 mutex_lock(&adev->srbm_mutex);
5262 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5263
5264 switch (ring->pipe) {
5265 case 0:
5266 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5267 PFP_PIPE0_RESET, 1);
5268 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5269 ME_PIPE0_RESET, 1);
5270 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5271 PFP_PIPE0_RESET, 0);
5272 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5273 ME_PIPE0_RESET, 0);
5274 break;
5275 case 1:
5276 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5277 PFP_PIPE1_RESET, 1);
5278 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5279 ME_PIPE1_RESET, 1);
5280 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5281 PFP_PIPE1_RESET, 0);
5282 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5283 ME_PIPE1_RESET, 0);
5284 break;
5285 default:
5286 break;
5287 }
5288
5289 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
5290 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
5291
5292 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
5293 RS64_FW_UC_START_ADDR_LO;
5294 soc24_grbm_select(adev, 0, 0, 0, 0);
5295 mutex_unlock(&adev->srbm_mutex);
5296 gfx_v12_0_unset_safe_mode(adev, 0);
5297
5298 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name,
5299 r == 0 ? "successfully" : "failed");
5300 /* Sometimes the ME start pc counter can't cache correctly, so the
5301 * PC check only as a reference and pipe reset result rely on the
5302 * later ring test.
5303 */
5304 return 0;
5305 }
5306
gfx_v12_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5307 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
5308 unsigned int vmid,
5309 struct amdgpu_fence *timedout_fence)
5310 {
5311 struct amdgpu_device *adev = ring->adev;
5312 int r;
5313
5314 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5315
5316 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
5317 if (r) {
5318 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
5319 r = gfx_v12_reset_gfx_pipe(ring);
5320 if (r)
5321 return r;
5322 }
5323
5324 r = gfx_v12_0_kgq_init_queue(ring, true);
5325 if (r) {
5326 dev_err(adev->dev, "failed to init kgq\n");
5327 return r;
5328 }
5329
5330 r = amdgpu_mes_map_legacy_queue(adev, ring);
5331 if (r) {
5332 dev_err(adev->dev, "failed to remap kgq\n");
5333 return r;
5334 }
5335
5336 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5337 }
5338
gfx_v12_0_reset_compute_pipe(struct amdgpu_ring * ring)5339 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)
5340 {
5341 struct amdgpu_device *adev = ring->adev;
5342 uint32_t reset_pipe = 0, clean_pipe = 0;
5343 int r = 0;
5344
5345 if (!gfx_v12_pipe_reset_support(adev))
5346 return -EOPNOTSUPP;
5347
5348 gfx_v12_0_set_safe_mode(adev, 0);
5349 mutex_lock(&adev->srbm_mutex);
5350 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5351
5352 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
5353 clean_pipe = reset_pipe;
5354
5355 if (adev->gfx.rs64_enable) {
5356 switch (ring->pipe) {
5357 case 0:
5358 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5359 MEC_PIPE0_RESET, 1);
5360 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5361 MEC_PIPE0_RESET, 0);
5362 break;
5363 case 1:
5364 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5365 MEC_PIPE1_RESET, 1);
5366 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5367 MEC_PIPE1_RESET, 0);
5368 break;
5369 case 2:
5370 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5371 MEC_PIPE2_RESET, 1);
5372 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5373 MEC_PIPE2_RESET, 0);
5374 break;
5375 case 3:
5376 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5377 MEC_PIPE3_RESET, 1);
5378 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5379 MEC_PIPE3_RESET, 0);
5380 break;
5381 default:
5382 break;
5383 }
5384 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
5385 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
5386 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
5387 RS64_FW_UC_START_ADDR_LO;
5388 } else {
5389 switch (ring->pipe) {
5390 case 0:
5391 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5392 MEC_ME1_PIPE0_RESET, 1);
5393 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5394 MEC_ME1_PIPE0_RESET, 0);
5395 break;
5396 case 1:
5397 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5398 MEC_ME1_PIPE1_RESET, 1);
5399 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5400 MEC_ME1_PIPE1_RESET, 0);
5401 break;
5402 default:
5403 break;
5404 }
5405 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
5406 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
5407 /* Doesn't find the F32 MEC instruction pointer register, and suppose
5408 * the driver won't run into the F32 mode.
5409 */
5410 }
5411
5412 soc24_grbm_select(adev, 0, 0, 0, 0);
5413 mutex_unlock(&adev->srbm_mutex);
5414 gfx_v12_0_unset_safe_mode(adev, 0);
5415
5416 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name,
5417 r == 0 ? "successfully" : "failed");
5418 /* Need the ring test to verify the pipe reset result.*/
5419 return 0;
5420 }
5421
gfx_v12_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5422 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
5423 unsigned int vmid,
5424 struct amdgpu_fence *timedout_fence)
5425 {
5426 struct amdgpu_device *adev = ring->adev;
5427 int r;
5428
5429 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5430
5431 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
5432 if (r) {
5433 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r);
5434 r = gfx_v12_0_reset_compute_pipe(ring);
5435 if (r)
5436 return r;
5437 }
5438
5439 r = gfx_v12_0_kcq_init_queue(ring, true);
5440 if (r) {
5441 dev_err(adev->dev, "failed to init kcq\n");
5442 return r;
5443 }
5444 r = amdgpu_mes_map_legacy_queue(adev, ring);
5445 if (r) {
5446 dev_err(adev->dev, "failed to remap kcq\n");
5447 return r;
5448 }
5449
5450 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5451 }
5452
gfx_v12_0_ring_begin_use(struct amdgpu_ring * ring)5453 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
5454 {
5455 amdgpu_gfx_profile_ring_begin_use(ring);
5456
5457 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
5458 }
5459
gfx_v12_0_ring_end_use(struct amdgpu_ring * ring)5460 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
5461 {
5462 amdgpu_gfx_profile_ring_end_use(ring);
5463
5464 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
5465 }
5466
5467 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
5468 .name = "gfx_v12_0",
5469 .early_init = gfx_v12_0_early_init,
5470 .late_init = gfx_v12_0_late_init,
5471 .sw_init = gfx_v12_0_sw_init,
5472 .sw_fini = gfx_v12_0_sw_fini,
5473 .hw_init = gfx_v12_0_hw_init,
5474 .hw_fini = gfx_v12_0_hw_fini,
5475 .suspend = gfx_v12_0_suspend,
5476 .resume = gfx_v12_0_resume,
5477 .is_idle = gfx_v12_0_is_idle,
5478 .wait_for_idle = gfx_v12_0_wait_for_idle,
5479 .set_clockgating_state = gfx_v12_0_set_clockgating_state,
5480 .set_powergating_state = gfx_v12_0_set_powergating_state,
5481 .get_clockgating_state = gfx_v12_0_get_clockgating_state,
5482 .dump_ip_state = gfx_v12_ip_dump,
5483 .print_ip_state = gfx_v12_ip_print,
5484 };
5485
5486 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
5487 .type = AMDGPU_RING_TYPE_GFX,
5488 .align_mask = 0xff,
5489 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5490 .support_64bit_ptrs = true,
5491 .secure_submission_supported = true,
5492 .get_rptr = gfx_v12_0_ring_get_rptr_gfx,
5493 .get_wptr = gfx_v12_0_ring_get_wptr_gfx,
5494 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5495 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5496 5 + /* COND_EXEC */
5497 7 + /* PIPELINE_SYNC */
5498 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5499 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5500 2 + /* VM_FLUSH */
5501 8 + /* FENCE for VM_FLUSH */
5502 5 + /* COND_EXEC */
5503 7 + /* HDP_flush */
5504 4 + /* VGT_flush */
5505 31 + /* DE_META */
5506 3 + /* CNTX_CTRL */
5507 5 + /* HDP_INVL */
5508 8 + 8 + /* FENCE x2 */
5509 8 + /* gfx_v12_0_emit_mem_sync */
5510 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5511 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */
5512 .emit_ib = gfx_v12_0_ring_emit_ib_gfx,
5513 .emit_fence = gfx_v12_0_ring_emit_fence,
5514 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5515 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5516 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5517 .test_ring = gfx_v12_0_ring_test_ring,
5518 .test_ib = gfx_v12_0_ring_test_ib,
5519 .insert_nop = gfx_v12_ring_insert_nop,
5520 .pad_ib = amdgpu_ring_generic_pad_ib,
5521 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
5522 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
5523 .preempt_ib = gfx_v12_0_ring_preempt_ib,
5524 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl,
5525 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5526 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5527 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5528 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5529 .reset = gfx_v12_0_reset_kgq,
5530 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5531 .begin_use = gfx_v12_0_ring_begin_use,
5532 .end_use = gfx_v12_0_ring_end_use,
5533 };
5534
5535 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
5536 .type = AMDGPU_RING_TYPE_COMPUTE,
5537 .align_mask = 0xff,
5538 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5539 .support_64bit_ptrs = true,
5540 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5541 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5542 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5543 .emit_frame_size =
5544 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5545 5 + /* hdp invalidate */
5546 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5547 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5548 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5549 2 + /* gfx_v12_0_ring_emit_vm_flush */
5550 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */
5551 8 + /* gfx_v12_0_emit_mem_sync */
5552 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5553 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5554 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5555 .emit_fence = gfx_v12_0_ring_emit_fence,
5556 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5557 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5558 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5559 .test_ring = gfx_v12_0_ring_test_ring,
5560 .test_ib = gfx_v12_0_ring_test_ib,
5561 .insert_nop = gfx_v12_ring_insert_nop,
5562 .pad_ib = amdgpu_ring_generic_pad_ib,
5563 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5564 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5565 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5566 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5567 .reset = gfx_v12_0_reset_kcq,
5568 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5569 .begin_use = gfx_v12_0_ring_begin_use,
5570 .end_use = gfx_v12_0_ring_end_use,
5571 };
5572
5573 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
5574 .type = AMDGPU_RING_TYPE_KIQ,
5575 .align_mask = 0xff,
5576 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5577 .support_64bit_ptrs = true,
5578 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5579 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5580 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5581 .emit_frame_size =
5582 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5583 5 + /*hdp invalidate */
5584 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5585 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5586 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5587 2 + /* gfx_v12_0_ring_emit_vm_flush */
5588 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5589 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5590 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5591 .emit_fence = gfx_v12_0_ring_emit_fence_kiq,
5592 .test_ring = gfx_v12_0_ring_test_ring,
5593 .test_ib = gfx_v12_0_ring_test_ib,
5594 .insert_nop = amdgpu_ring_insert_nop,
5595 .pad_ib = amdgpu_ring_generic_pad_ib,
5596 .emit_rreg = gfx_v12_0_ring_emit_rreg,
5597 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5598 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5599 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5600 };
5601
gfx_v12_0_set_ring_funcs(struct amdgpu_device * adev)5602 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
5603 {
5604 int i;
5605
5606 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;
5607
5608 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5609 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;
5610
5611 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5612 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;
5613 }
5614
5615 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {
5616 .set = gfx_v12_0_set_eop_interrupt_state,
5617 .process = gfx_v12_0_eop_irq,
5618 };
5619
5620 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
5621 .set = gfx_v12_0_set_priv_reg_fault_state,
5622 .process = gfx_v12_0_priv_reg_irq,
5623 };
5624
5625 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
5626 .set = gfx_v12_0_set_bad_op_fault_state,
5627 .process = gfx_v12_0_bad_op_irq,
5628 };
5629
5630 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
5631 .set = gfx_v12_0_set_priv_inst_fault_state,
5632 .process = gfx_v12_0_priv_inst_irq,
5633 };
5634
gfx_v12_0_set_irq_funcs(struct amdgpu_device * adev)5635 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
5636 {
5637 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5638 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;
5639
5640 adev->gfx.priv_reg_irq.num_types = 1;
5641 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;
5642
5643 adev->gfx.bad_op_irq.num_types = 1;
5644 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
5645
5646 adev->gfx.priv_inst_irq.num_types = 1;
5647 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
5648 }
5649
gfx_v12_0_set_imu_funcs(struct amdgpu_device * adev)5650 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)
5651 {
5652 if (adev->flags & AMD_IS_APU)
5653 adev->gfx.imu.mode = MISSION_MODE;
5654 else
5655 adev->gfx.imu.mode = DEBUG_MODE;
5656
5657 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;
5658 }
5659
gfx_v12_0_set_rlc_funcs(struct amdgpu_device * adev)5660 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
5661 {
5662 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;
5663 }
5664
gfx_v12_0_set_mqd_funcs(struct amdgpu_device * adev)5665 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
5666 {
5667 /* set gfx eng mqd */
5668 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
5669 sizeof(struct v12_gfx_mqd);
5670 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
5671 gfx_v12_0_gfx_mqd_init;
5672 /* set compute eng mqd */
5673 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
5674 sizeof(struct v12_compute_mqd);
5675 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
5676 gfx_v12_0_compute_mqd_init;
5677 }
5678
gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)5679 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5680 u32 bitmap)
5681 {
5682 u32 data;
5683
5684 if (!bitmap)
5685 return;
5686
5687 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5688 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5689
5690 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5691 }
5692
gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)5693 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5694 {
5695 u32 data, wgp_bitmask;
5696 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5697 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
5698
5699 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5700 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5701
5702 wgp_bitmask =
5703 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5704
5705 return (~data) & wgp_bitmask;
5706 }
5707
gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)5708 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5709 {
5710 u32 wgp_idx, wgp_active_bitmap;
5711 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5712
5713 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);
5714 cu_active_bitmap = 0;
5715
5716 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5717 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5718 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5719 if (wgp_active_bitmap & (1 << wgp_idx))
5720 cu_active_bitmap |= cu_bitmap_per_wgp;
5721 }
5722
5723 return cu_active_bitmap;
5724 }
5725
gfx_v12_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)5726 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
5727 struct amdgpu_cu_info *cu_info)
5728 {
5729 int i, j, k, counter, active_cu_number = 0;
5730 u32 mask, bitmap;
5731 unsigned disable_masks[8 * 2];
5732
5733 if (!adev || !cu_info)
5734 return -EINVAL;
5735
5736 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
5737
5738 mutex_lock(&adev->grbm_idx_mutex);
5739 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5740 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5741 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5742 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
5743 continue;
5744 mask = 1;
5745 counter = 0;
5746 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5747 if (i < 8 && j < 2)
5748 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(
5749 adev, disable_masks[i * 2 + j]);
5750 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);
5751
5752 /**
5753 * GFX12 could support more than 4 SEs, while the bitmap
5754 * in cu_info struct is 4x4 and ioctl interface struct
5755 * drm_amdgpu_info_device should keep stable.
5756 * So we use last two columns of bitmap to store cu mask for
5757 * SEs 4 to 7, the layout of the bitmap is as below:
5758 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
5759 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
5760 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
5761 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
5762 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
5763 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
5764 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
5765 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
5766 */
5767 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
5768
5769 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5770 if (bitmap & mask)
5771 counter++;
5772
5773 mask <<= 1;
5774 }
5775 active_cu_number += counter;
5776 }
5777 }
5778 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5779 mutex_unlock(&adev->grbm_idx_mutex);
5780
5781 cu_info->number = active_cu_number;
5782 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5783
5784 return 0;
5785 }
5786
5787 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {
5788 .type = AMD_IP_BLOCK_TYPE_GFX,
5789 .major = 12,
5790 .minor = 0,
5791 .rev = 0,
5792 .funcs = &gfx_v12_0_ip_funcs,
5793 };
5794