1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "hardwaremanager.h" 32 #include "ppatomfwctrl.h" 33 #include "atomfirmware.h" 34 #include "cgs_common.h" 35 #include "vega10_powertune.h" 36 #include "smu9.h" 37 #include "smu9_driver_if.h" 38 #include "vega10_inc.h" 39 #include "soc15_common.h" 40 #include "pppcielanes.h" 41 #include "vega10_hwmgr.h" 42 #include "vega10_smumgr.h" 43 #include "vega10_processpptables.h" 44 #include "vega10_pptable.h" 45 #include "vega10_thermal.h" 46 #include "pp_debug.h" 47 #include "amd_pcie_helpers.h" 48 #include "ppinterrupt.h" 49 #include "pp_overdriver.h" 50 #include "pp_thermal.h" 51 #include "vega10_baco.h" 52 53 #include "smuio/smuio_9_0_offset.h" 54 #include "smuio/smuio_9_0_sh_mask.h" 55 56 #define smnPCIE_LC_SPEED_CNTL 0x11140290 57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 58 59 #define HBM_MEMORY_CHANNEL_WIDTH 128 60 61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 62 63 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 65 66 //DF_CS_AON0_DramBaseAddress0 67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 77 78 typedef enum { 79 CLK_SMNCLK = 0, 80 CLK_SOCCLK, 81 CLK_MP0CLK, 82 CLK_MP1CLK, 83 CLK_LCLK, 84 CLK_DCEFCLK, 85 CLK_VCLK, 86 CLK_DCLK, 87 CLK_ECLK, 88 CLK_UCLK, 89 CLK_GFXCLK, 90 CLK_COUNT, 91 } CLOCK_ID_e; 92 93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); 94 95 static struct vega10_power_state *cast_phw_vega10_power_state( 96 struct pp_hw_power_state *hw_ps) 97 { 98 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 99 "Invalid Powerstate Type!", 100 return NULL;); 101 102 return (struct vega10_power_state *)hw_ps; 103 } 104 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state( 106 const struct pp_hw_power_state *hw_ps) 107 { 108 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 109 "Invalid Powerstate Type!", 110 return NULL;); 111 112 return (const struct vega10_power_state *)hw_ps; 113 } 114 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) 116 { 117 struct vega10_hwmgr *data = hwmgr->backend; 118 119 data->registry_data.sclk_dpm_key_disabled = 120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 121 data->registry_data.socclk_dpm_key_disabled = 122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; 123 data->registry_data.mclk_dpm_key_disabled = 124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 125 data->registry_data.pcie_dpm_key_disabled = 126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 127 128 data->registry_data.dcefclk_dpm_key_disabled = 129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; 130 131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { 132 data->registry_data.power_containment_support = 1; 133 data->registry_data.enable_pkg_pwr_tracking_feature = 1; 134 data->registry_data.enable_tdc_limit_feature = 1; 135 } 136 137 data->registry_data.clock_stretcher_support = 138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; 139 140 data->registry_data.ulv_support = 141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 142 143 data->registry_data.sclk_deep_sleep_support = 144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 145 146 data->registry_data.disable_water_mark = 0; 147 148 data->registry_data.fan_control_support = 1; 149 data->registry_data.thermal_support = 1; 150 data->registry_data.fw_ctf_enabled = 1; 151 152 data->registry_data.avfs_support = 153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; 154 data->registry_data.led_dpm_enabled = 1; 155 156 data->registry_data.vr0hot_enabled = 1; 157 data->registry_data.vr1hot_enabled = 1; 158 data->registry_data.regulator_hot_gpio_support = 1; 159 160 data->registry_data.didt_support = 1; 161 if (data->registry_data.didt_support) { 162 data->registry_data.didt_mode = 6; 163 data->registry_data.sq_ramping_support = 1; 164 data->registry_data.db_ramping_support = 0; 165 data->registry_data.td_ramping_support = 0; 166 data->registry_data.tcp_ramping_support = 0; 167 data->registry_data.dbr_ramping_support = 0; 168 data->registry_data.edc_didt_support = 1; 169 data->registry_data.gc_didt_support = 0; 170 data->registry_data.psm_didt_support = 0; 171 } 172 173 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; 174 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 175 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 176 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 177 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 178 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 179 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 180 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 181 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 182 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 183 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 184 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 185 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 186 187 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT; 188 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT; 189 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT; 190 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT; 191 } 192 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) 194 { 195 struct vega10_hwmgr *data = hwmgr->backend; 196 struct phm_ppt_v2_information *table_info = 197 (struct phm_ppt_v2_information *)hwmgr->pptable; 198 struct amdgpu_device *adev = hwmgr->adev; 199 200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 201 PHM_PlatformCaps_SclkDeepSleep); 202 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_DynamicPatchPowerState); 205 206 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) 207 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 208 PHM_PlatformCaps_ControlVDDCI); 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_EnableSMU7ThermalManagement); 212 213 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 214 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 215 PHM_PlatformCaps_UVDPowerGating); 216 217 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 218 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 219 PHM_PlatformCaps_VCEPowerGating); 220 221 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_UnTabledHardwareInterface); 223 224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_FanSpeedInTableIsRPM); 226 227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_ODFuzzyFanControlSupport); 229 230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 231 PHM_PlatformCaps_DynamicPowerManagement); 232 233 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_SMC); 235 236 /* power tune caps */ 237 /* assume disabled */ 238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_PowerContainment); 240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 241 PHM_PlatformCaps_DiDtSupport); 242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_SQRamping); 244 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 245 PHM_PlatformCaps_DBRamping); 246 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 247 PHM_PlatformCaps_TDRamping); 248 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 249 PHM_PlatformCaps_TCPRamping); 250 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 251 PHM_PlatformCaps_DBRRamping); 252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 253 PHM_PlatformCaps_DiDtEDCEnable); 254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 255 PHM_PlatformCaps_GCEDC); 256 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 257 PHM_PlatformCaps_PSM); 258 259 if (data->registry_data.didt_support) { 260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 261 if (data->registry_data.sq_ramping_support) 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 263 if (data->registry_data.db_ramping_support) 264 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 265 if (data->registry_data.td_ramping_support) 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 267 if (data->registry_data.tcp_ramping_support) 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 269 if (data->registry_data.dbr_ramping_support) 270 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 271 if (data->registry_data.edc_didt_support) 272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 273 if (data->registry_data.gc_didt_support) 274 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 275 if (data->registry_data.psm_didt_support) 276 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 277 } 278 279 if (data->registry_data.power_containment_support) 280 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 281 PHM_PlatformCaps_PowerContainment); 282 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_CAC); 284 285 if (table_info->tdp_table->usClockStretchAmount && 286 data->registry_data.clock_stretcher_support) 287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 288 PHM_PlatformCaps_ClockStretcher); 289 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_RegulatorHot); 292 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 293 PHM_PlatformCaps_AutomaticDCTransition); 294 295 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 296 PHM_PlatformCaps_UVDDPM); 297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 298 PHM_PlatformCaps_VCEDPM); 299 300 return 0; 301 } 302 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 304 { 305 struct vega10_hwmgr *data = hwmgr->backend; 306 struct phm_ppt_v2_information *table_info = 307 (struct phm_ppt_v2_information *)(hwmgr->pptable); 308 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 309 struct vega10_odn_vddc_lookup_table *od_lookup_table; 310 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 311 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3]; 312 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; 313 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 314 uint32_t i; 315 int result; 316 317 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 318 if (!result) { 319 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc; 320 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc; 321 } 322 323 od_lookup_table = &odn_table->vddc_lookup_table; 324 vddc_lookup_table = table_info->vddc_lookup_table; 325 326 for (i = 0; i < vddc_lookup_table->count; i++) 327 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd; 328 329 od_lookup_table->count = vddc_lookup_table->count; 330 331 dep_table[0] = table_info->vdd_dep_on_sclk; 332 dep_table[1] = table_info->vdd_dep_on_mclk; 333 dep_table[2] = table_info->vdd_dep_on_socclk; 334 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; 335 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; 336 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; 337 338 for (i = 0; i < 3; i++) 339 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); 340 341 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) 342 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; 343 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) 344 odn_table->min_vddc = dep_table[0]->entries[0].vddc; 345 346 i = od_table[2]->count - 1; 347 od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ? 348 hwmgr->platform_descriptor.overdriveLimit.memoryClock : 349 od_table[2]->entries[i].clk; 350 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? 351 odn_table->max_vddc : 352 od_table[2]->entries[i].vddc; 353 354 return 0; 355 } 356 357 static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) 358 { 359 struct vega10_hwmgr *data = hwmgr->backend; 360 uint32_t sub_vendor_id, hw_revision; 361 uint32_t top32, bottom32; 362 struct amdgpu_device *adev = hwmgr->adev; 363 int ret, i; 364 365 vega10_initialize_power_tune_defaults(hwmgr); 366 367 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 368 data->smu_features[i].smu_feature_id = 0xffff; 369 data->smu_features[i].smu_feature_bitmap = 1 << i; 370 data->smu_features[i].enabled = false; 371 data->smu_features[i].supported = false; 372 } 373 374 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 375 FEATURE_DPM_PREFETCHER_BIT; 376 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 377 FEATURE_DPM_GFXCLK_BIT; 378 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 379 FEATURE_DPM_UCLK_BIT; 380 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 381 FEATURE_DPM_SOCCLK_BIT; 382 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 383 FEATURE_DPM_UVD_BIT; 384 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 385 FEATURE_DPM_VCE_BIT; 386 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 387 FEATURE_DPM_MP0CLK_BIT; 388 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 389 FEATURE_DPM_LINK_BIT; 390 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 391 FEATURE_DPM_DCEFCLK_BIT; 392 data->smu_features[GNLD_ULV].smu_feature_id = 393 FEATURE_ULV_BIT; 394 data->smu_features[GNLD_AVFS].smu_feature_id = 395 FEATURE_AVFS_BIT; 396 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 397 FEATURE_DS_GFXCLK_BIT; 398 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 399 FEATURE_DS_SOCCLK_BIT; 400 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 401 FEATURE_DS_LCLK_BIT; 402 data->smu_features[GNLD_PPT].smu_feature_id = 403 FEATURE_PPT_BIT; 404 data->smu_features[GNLD_TDC].smu_feature_id = 405 FEATURE_TDC_BIT; 406 data->smu_features[GNLD_THERMAL].smu_feature_id = 407 FEATURE_THERMAL_BIT; 408 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 409 FEATURE_GFX_PER_CU_CG_BIT; 410 data->smu_features[GNLD_RM].smu_feature_id = 411 FEATURE_RM_BIT; 412 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 413 FEATURE_DS_DCEFCLK_BIT; 414 data->smu_features[GNLD_ACDC].smu_feature_id = 415 FEATURE_ACDC_BIT; 416 data->smu_features[GNLD_VR0HOT].smu_feature_id = 417 FEATURE_VR0HOT_BIT; 418 data->smu_features[GNLD_VR1HOT].smu_feature_id = 419 FEATURE_VR1HOT_BIT; 420 data->smu_features[GNLD_FW_CTF].smu_feature_id = 421 FEATURE_FW_CTF_BIT; 422 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 423 FEATURE_LED_DISPLAY_BIT; 424 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 425 FEATURE_FAN_CONTROL_BIT; 426 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 427 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 428 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; 429 430 if (!data->registry_data.prefetcher_dpm_key_disabled) 431 data->smu_features[GNLD_DPM_PREFETCHER].supported = true; 432 433 if (!data->registry_data.sclk_dpm_key_disabled) 434 data->smu_features[GNLD_DPM_GFXCLK].supported = true; 435 436 if (!data->registry_data.mclk_dpm_key_disabled) 437 data->smu_features[GNLD_DPM_UCLK].supported = true; 438 439 if (!data->registry_data.socclk_dpm_key_disabled) 440 data->smu_features[GNLD_DPM_SOCCLK].supported = true; 441 442 if (PP_CAP(PHM_PlatformCaps_UVDDPM)) 443 data->smu_features[GNLD_DPM_UVD].supported = true; 444 445 if (PP_CAP(PHM_PlatformCaps_VCEDPM)) 446 data->smu_features[GNLD_DPM_VCE].supported = true; 447 448 data->smu_features[GNLD_DPM_LINK].supported = true; 449 450 if (!data->registry_data.dcefclk_dpm_key_disabled) 451 data->smu_features[GNLD_DPM_DCEFCLK].supported = true; 452 453 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && 454 data->registry_data.sclk_deep_sleep_support) { 455 data->smu_features[GNLD_DS_GFXCLK].supported = true; 456 data->smu_features[GNLD_DS_SOCCLK].supported = true; 457 data->smu_features[GNLD_DS_LCLK].supported = true; 458 data->smu_features[GNLD_DS_DCEFCLK].supported = true; 459 } 460 461 if (data->registry_data.enable_pkg_pwr_tracking_feature) 462 data->smu_features[GNLD_PPT].supported = true; 463 464 if (data->registry_data.enable_tdc_limit_feature) 465 data->smu_features[GNLD_TDC].supported = true; 466 467 if (data->registry_data.thermal_support) 468 data->smu_features[GNLD_THERMAL].supported = true; 469 470 if (data->registry_data.fan_control_support) 471 data->smu_features[GNLD_FAN_CONTROL].supported = true; 472 473 if (data->registry_data.fw_ctf_enabled) 474 data->smu_features[GNLD_FW_CTF].supported = true; 475 476 if (data->registry_data.avfs_support) 477 data->smu_features[GNLD_AVFS].supported = true; 478 479 if (data->registry_data.led_dpm_enabled) 480 data->smu_features[GNLD_LED_DISPLAY].supported = true; 481 482 if (data->registry_data.vr1hot_enabled) 483 data->smu_features[GNLD_VR1HOT].supported = true; 484 485 if (data->registry_data.vr0hot_enabled) 486 data->smu_features[GNLD_VR0HOT].supported = true; 487 488 ret = smum_send_msg_to_smc(hwmgr, 489 PPSMC_MSG_GetSmuVersion, 490 &hwmgr->smu_version); 491 if (ret) 492 return ret; 493 494 /* ACG firmware has major version 5 */ 495 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) 496 data->smu_features[GNLD_ACG].supported = true; 497 if (data->registry_data.didt_support) 498 data->smu_features[GNLD_DIDT].supported = true; 499 500 hw_revision = adev->pdev->revision; 501 sub_vendor_id = adev->pdev->subsystem_vendor; 502 503 if ((hwmgr->chip_id == 0x6862 || 504 hwmgr->chip_id == 0x6861 || 505 hwmgr->chip_id == 0x6868) && 506 (hw_revision == 0) && 507 (sub_vendor_id != 0x1002)) 508 data->smu_features[GNLD_PCC_LIMIT].supported = true; 509 510 /* Get the SN to turn into a Unique ID */ 511 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 512 if (ret) 513 return ret; 514 515 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 516 if (ret) 517 return ret; 518 519 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 520 return 0; 521 } 522 523 #ifdef PPLIB_VEGA10_EVV_SUPPORT 524 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, 525 phm_ppt_v1_voltage_lookup_table *lookup_table, 526 uint16_t virtual_voltage_id, int32_t *socclk) 527 { 528 uint8_t entry_id; 529 uint8_t voltage_id; 530 struct phm_ppt_v2_information *table_info = 531 (struct phm_ppt_v2_information *)(hwmgr->pptable); 532 533 PP_ASSERT_WITH_CODE(lookup_table->count != 0, 534 "Lookup table is empty", 535 return -EINVAL); 536 537 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ 538 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { 539 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd; 540 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) 541 break; 542 } 543 544 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, 545 "Can't find requested voltage id in vdd_dep_on_socclk table!", 546 return -EINVAL); 547 548 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; 549 550 return 0; 551 } 552 553 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 554 /** 555 * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. 556 * 557 * @hwmgr: the address of the powerplay hardware manager. 558 * return: always 0. 559 */ 560 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) 561 { 562 struct vega10_hwmgr *data = hwmgr->backend; 563 uint16_t vv_id; 564 uint32_t vddc = 0; 565 uint16_t i, j; 566 uint32_t sclk = 0; 567 struct phm_ppt_v2_information *table_info = 568 (struct phm_ppt_v2_information *)hwmgr->pptable; 569 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = 570 table_info->vdd_dep_on_socclk; 571 int result; 572 573 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { 574 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 575 576 if (!vega10_get_socclk_for_voltage_evv(hwmgr, 577 table_info->vddc_lookup_table, vv_id, &sclk)) { 578 if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { 579 for (j = 1; j < socclk_table->count; j++) { 580 if (socclk_table->entries[j].clk == sclk && 581 socclk_table->entries[j].cks_enable == 0) { 582 sclk += 5000; 583 break; 584 } 585 } 586 } 587 588 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, 589 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), 590 "Error retrieving EVV voltage value!", 591 continue); 592 593 594 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ 595 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), 596 "Invalid VDDC value", result = -EINVAL;); 597 598 /* the voltage should not be zero nor equal to leakage ID */ 599 if (vddc != 0 && vddc != vv_id) { 600 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); 601 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 602 data->vddc_leakage.count++; 603 } 604 } 605 } 606 607 return 0; 608 } 609 610 /** 611 * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. 612 * 613 * @hwmgr: the address of the powerplay hardware manager. 614 * @voltage: pointer to changing voltage 615 * @leakage_table: pointer to leakage table 616 */ 617 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, 618 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table) 619 { 620 uint32_t index; 621 622 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 623 for (index = 0; index < leakage_table->count; index++) { 624 /* if this voltage matches a leakage voltage ID */ 625 /* patch with actual leakage voltage */ 626 if (leakage_table->leakage_id[index] == *voltage) { 627 *voltage = leakage_table->actual_voltage[index]; 628 break; 629 } 630 } 631 632 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 633 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 634 } 635 636 /** 637 * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 638 * 639 * @hwmgr: the address of the powerplay hardware manager. 640 * @lookup_table: pointer to voltage lookup table 641 * @leakage_table: pointer to leakage table 642 * return: always 0 643 */ 644 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 645 phm_ppt_v1_voltage_lookup_table *lookup_table, 646 struct vega10_leakage_voltage *leakage_table) 647 { 648 uint32_t i; 649 650 for (i = 0; i < lookup_table->count; i++) 651 vega10_patch_with_vdd_leakage(hwmgr, 652 &lookup_table->entries[i].us_vdd, leakage_table); 653 654 return 0; 655 } 656 657 static int vega10_patch_clock_voltage_limits_with_vddc_leakage( 658 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, 659 uint16_t *vddc) 660 { 661 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 662 663 return 0; 664 } 665 #endif 666 667 static int vega10_patch_voltage_dependency_tables_with_lookup_table( 668 struct pp_hwmgr *hwmgr) 669 { 670 uint8_t entry_id, voltage_id; 671 unsigned i; 672 struct phm_ppt_v2_information *table_info = 673 (struct phm_ppt_v2_information *)(hwmgr->pptable); 674 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 675 table_info->mm_dep_table; 676 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 677 table_info->vdd_dep_on_mclk; 678 679 for (i = 0; i < 6; i++) { 680 struct phm_ppt_v1_clock_voltage_dependency_table *vdt; 681 switch (i) { 682 case 0: vdt = table_info->vdd_dep_on_socclk; break; 683 case 1: vdt = table_info->vdd_dep_on_sclk; break; 684 case 2: vdt = table_info->vdd_dep_on_dcefclk; break; 685 case 3: vdt = table_info->vdd_dep_on_pixclk; break; 686 case 4: vdt = table_info->vdd_dep_on_dispclk; break; 687 case 5: vdt = table_info->vdd_dep_on_phyclk; break; 688 } 689 690 for (entry_id = 0; entry_id < vdt->count; entry_id++) { 691 voltage_id = vdt->entries[entry_id].vddInd; 692 vdt->entries[entry_id].vddc = 693 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 694 } 695 } 696 697 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 698 voltage_id = mm_table->entries[entry_id].vddcInd; 699 mm_table->entries[entry_id].vddc = 700 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 701 } 702 703 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 704 voltage_id = mclk_table->entries[entry_id].vddInd; 705 mclk_table->entries[entry_id].vddc = 706 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 707 voltage_id = mclk_table->entries[entry_id].vddciInd; 708 mclk_table->entries[entry_id].vddci = 709 table_info->vddci_lookup_table->entries[voltage_id].us_vdd; 710 voltage_id = mclk_table->entries[entry_id].mvddInd; 711 mclk_table->entries[entry_id].mvdd = 712 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; 713 } 714 715 716 return 0; 717 718 } 719 720 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, 721 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 722 { 723 uint32_t table_size, i, j; 724 725 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, 726 "Lookup table is empty", return -EINVAL); 727 728 table_size = lookup_table->count; 729 730 /* Sorting voltages */ 731 for (i = 0; i < table_size - 1; i++) { 732 for (j = i + 1; j > 0; j--) { 733 if (lookup_table->entries[j].us_vdd < 734 lookup_table->entries[j - 1].us_vdd) { 735 swap(lookup_table->entries[j - 1], 736 lookup_table->entries[j]); 737 } 738 } 739 } 740 741 return 0; 742 } 743 744 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) 745 { 746 int result = 0; 747 int tmp_result; 748 struct phm_ppt_v2_information *table_info = 749 (struct phm_ppt_v2_information *)(hwmgr->pptable); 750 #ifdef PPLIB_VEGA10_EVV_SUPPORT 751 struct vega10_hwmgr *data = hwmgr->backend; 752 753 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, 754 table_info->vddc_lookup_table, &(data->vddc_leakage)); 755 if (tmp_result) 756 result = tmp_result; 757 758 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 759 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 760 if (tmp_result) 761 result = tmp_result; 762 #endif 763 764 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 765 if (tmp_result) 766 result = tmp_result; 767 768 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 769 if (tmp_result) 770 result = tmp_result; 771 772 return result; 773 } 774 775 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 776 { 777 struct phm_ppt_v2_information *table_info = 778 (struct phm_ppt_v2_information *)(hwmgr->pptable); 779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 780 table_info->vdd_dep_on_socclk; 781 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 782 table_info->vdd_dep_on_mclk; 783 784 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, 785 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); 786 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 787 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); 788 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 790 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); 791 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 792 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); 793 794 table_info->max_clock_voltage_on_ac.sclk = 795 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 796 table_info->max_clock_voltage_on_ac.mclk = 797 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 798 table_info->max_clock_voltage_on_ac.vddc = 799 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 800 table_info->max_clock_voltage_on_ac.vddci = 801 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 802 803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 804 table_info->max_clock_voltage_on_ac.sclk; 805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 806 table_info->max_clock_voltage_on_ac.mclk; 807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 808 table_info->max_clock_voltage_on_ac.vddc; 809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = 810 table_info->max_clock_voltage_on_ac.vddci; 811 812 return 0; 813 } 814 815 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 816 { 817 kfree(hwmgr->backend); 818 hwmgr->backend = NULL; 819 820 return 0; 821 } 822 823 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 824 { 825 int result = 0; 826 struct vega10_hwmgr *data; 827 uint32_t config_telemetry = 0; 828 struct pp_atomfwctrl_voltage_table vol_table; 829 struct amdgpu_device *adev = hwmgr->adev; 830 831 data = kzalloc_obj(struct vega10_hwmgr); 832 if (data == NULL) 833 return -ENOMEM; 834 835 hwmgr->backend = data; 836 837 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 838 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 839 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 840 841 vega10_set_default_registry_data(hwmgr); 842 data->disable_dpm_mask = 0xff; 843 844 /* need to set voltage control types before EVV patching */ 845 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE; 846 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; 847 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE; 848 849 /* VDDCR_SOC */ 850 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 851 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { 852 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 853 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2, 854 &vol_table)) { 855 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | 856 (vol_table.telemetry_offset & 0xff); 857 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 858 } 859 } else { 860 kfree(hwmgr->backend); 861 hwmgr->backend = NULL; 862 PP_ASSERT_WITH_CODE(false, 863 "VDDCR_SOC is not SVID2!", 864 return -1); 865 } 866 867 /* MVDDC */ 868 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 869 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) { 870 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 871 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2, 872 &vol_table)) { 873 config_telemetry |= 874 ((vol_table.telemetry_slope << 24) & 0xff000000) | 875 ((vol_table.telemetry_offset << 16) & 0xff0000); 876 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 877 } 878 } 879 880 /* VDDCI_MEM */ 881 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { 882 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 883 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 884 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; 885 } 886 887 data->config_telemetry = config_telemetry; 888 889 vega10_set_features_platform_caps(hwmgr); 890 891 result = vega10_init_dpm_defaults(hwmgr); 892 if (result) 893 return result; 894 895 #ifdef PPLIB_VEGA10_EVV_SUPPORT 896 /* Get leakage voltage based on leakage ID. */ 897 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), 898 "Get EVV Voltage Failed. Abort Driver loading!", 899 return -1); 900 #endif 901 902 /* Patch our voltage dependency table with actual leakage voltage 903 * We need to perform leakage translation before it's used by other functions 904 */ 905 vega10_complete_dependency_tables(hwmgr); 906 907 /* Parse pptable data read from VBIOS */ 908 vega10_set_private_data_based_on_pptable(hwmgr); 909 910 data->is_tlu_enabled = false; 911 912 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 913 VEGA10_MAX_HARDWARE_POWERLEVELS; 914 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 915 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 916 917 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 918 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 919 hwmgr->platform_descriptor.clockStep.engineClock = 500; 920 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 921 922 data->total_active_cus = adev->gfx.cu_info.number; 923 if (!hwmgr->not_vf) 924 return result; 925 926 /* Setup default Overdrive Fan control settings */ 927 data->odn_fan_table.target_fan_speed = 928 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 929 data->odn_fan_table.target_temperature = 930 hwmgr->thermal_controller. 931 advanceFanControlParameters.ucTargetTemperature; 932 data->odn_fan_table.min_performance_clock = 933 hwmgr->thermal_controller.advanceFanControlParameters. 934 ulMinFanSCLKAcousticLimit; 935 data->odn_fan_table.min_fan_limit = 936 hwmgr->thermal_controller. 937 advanceFanControlParameters.usFanPWMMinLimit * 938 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 939 940 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & 941 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> 942 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 943 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), 944 "Mem Channel Index Exceeded maximum!", 945 return -EINVAL); 946 947 return result; 948 } 949 950 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) 951 { 952 struct vega10_hwmgr *data = hwmgr->backend; 953 954 data->low_sclk_interrupt_threshold = 0; 955 956 return 0; 957 } 958 959 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) 960 { 961 struct vega10_hwmgr *data = hwmgr->backend; 962 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 963 964 struct pp_atomfwctrl_voltage_table table; 965 uint8_t i, j; 966 uint32_t mask = 0; 967 uint32_t tmp; 968 int32_t ret = 0; 969 970 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, 971 VOLTAGE_OBJ_GPIO_LUT, &table); 972 973 if (!ret) { 974 tmp = table.mask_low; 975 for (i = 0, j = 0; i < 32; i++) { 976 if (tmp & 1) { 977 mask |= (uint32_t)(i << (8 * j)); 978 if (++j >= 3) 979 break; 980 } 981 tmp >>= 1; 982 } 983 } 984 985 pp_table->LedPin0 = (uint8_t)(mask & 0xff); 986 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); 987 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); 988 return 0; 989 } 990 991 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) 992 { 993 if (!hwmgr->not_vf) 994 return 0; 995 996 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), 997 "Failed to init sclk threshold!", 998 return -EINVAL); 999 1000 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), 1001 "Failed to set up led dpm config!", 1002 return -EINVAL); 1003 1004 smum_send_msg_to_smc_with_parameter(hwmgr, 1005 PPSMC_MSG_NumOfDisplays, 1006 0, 1007 NULL); 1008 1009 return 0; 1010 } 1011 1012 /** 1013 * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. 1014 * 1015 * @hwmgr: the address of the powerplay hardware manager. 1016 * @vol_table: the pointer to changing voltage table 1017 * return: 0 in success 1018 */ 1019 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, 1020 struct pp_atomfwctrl_voltage_table *vol_table) 1021 { 1022 uint32_t i, j; 1023 uint16_t vvalue; 1024 bool found = false; 1025 struct pp_atomfwctrl_voltage_table *table; 1026 1027 PP_ASSERT_WITH_CODE(vol_table, 1028 "Voltage Table empty.", return -EINVAL); 1029 table = kzalloc_obj(struct pp_atomfwctrl_voltage_table); 1030 1031 if (!table) 1032 return -ENOMEM; 1033 1034 table->mask_low = vol_table->mask_low; 1035 table->phase_delay = vol_table->phase_delay; 1036 1037 for (i = 0; i < vol_table->count; i++) { 1038 vvalue = vol_table->entries[i].value; 1039 found = false; 1040 1041 for (j = 0; j < table->count; j++) { 1042 if (vvalue == table->entries[j].value) { 1043 found = true; 1044 break; 1045 } 1046 } 1047 1048 if (!found) { 1049 table->entries[table->count].value = vvalue; 1050 table->entries[table->count].smio_low = 1051 vol_table->entries[i].smio_low; 1052 table->count++; 1053 } 1054 } 1055 1056 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table)); 1057 kfree(table); 1058 1059 return 0; 1060 } 1061 1062 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, 1063 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1064 struct pp_atomfwctrl_voltage_table *vol_table) 1065 { 1066 int i; 1067 1068 PP_ASSERT_WITH_CODE(dep_table->count, 1069 "Voltage Dependency Table empty.", 1070 return -EINVAL); 1071 1072 vol_table->mask_low = 0; 1073 vol_table->phase_delay = 0; 1074 vol_table->count = dep_table->count; 1075 1076 for (i = 0; i < vol_table->count; i++) { 1077 vol_table->entries[i].value = dep_table->entries[i].mvdd; 1078 vol_table->entries[i].smio_low = 0; 1079 } 1080 1081 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, 1082 vol_table), 1083 "Failed to trim MVDD Table!", 1084 return -1); 1085 1086 return 0; 1087 } 1088 1089 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, 1090 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1091 struct pp_atomfwctrl_voltage_table *vol_table) 1092 { 1093 uint32_t i; 1094 1095 PP_ASSERT_WITH_CODE(dep_table->count, 1096 "Voltage Dependency Table empty.", 1097 return -EINVAL); 1098 1099 vol_table->mask_low = 0; 1100 vol_table->phase_delay = 0; 1101 vol_table->count = dep_table->count; 1102 1103 for (i = 0; i < dep_table->count; i++) { 1104 vol_table->entries[i].value = dep_table->entries[i].vddci; 1105 vol_table->entries[i].smio_low = 0; 1106 } 1107 1108 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), 1109 "Failed to trim VDDCI table.", 1110 return -1); 1111 1112 return 0; 1113 } 1114 1115 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, 1116 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1117 struct pp_atomfwctrl_voltage_table *vol_table) 1118 { 1119 int i; 1120 1121 PP_ASSERT_WITH_CODE(dep_table->count, 1122 "Voltage Dependency Table empty.", 1123 return -EINVAL); 1124 1125 vol_table->mask_low = 0; 1126 vol_table->phase_delay = 0; 1127 vol_table->count = dep_table->count; 1128 1129 for (i = 0; i < vol_table->count; i++) { 1130 vol_table->entries[i].value = dep_table->entries[i].vddc; 1131 vol_table->entries[i].smio_low = 0; 1132 } 1133 1134 return 0; 1135 } 1136 1137 /* ---- Voltage Tables ---- 1138 * If the voltage table would be bigger than 1139 * what will fit into the state table on 1140 * the SMC keep only the higher entries. 1141 */ 1142 static void vega10_trim_voltage_table_to_fit_state_table( 1143 struct pp_hwmgr *hwmgr, 1144 uint32_t max_vol_steps, 1145 struct pp_atomfwctrl_voltage_table *vol_table) 1146 { 1147 unsigned int i, diff; 1148 1149 if (vol_table->count <= max_vol_steps) 1150 return; 1151 1152 diff = vol_table->count - max_vol_steps; 1153 1154 for (i = 0; i < max_vol_steps; i++) 1155 vol_table->entries[i] = vol_table->entries[i + diff]; 1156 1157 vol_table->count = max_vol_steps; 1158 } 1159 1160 /** 1161 * vega10_construct_voltage_tables - Create Voltage Tables. 1162 * 1163 * @hwmgr: the address of the powerplay hardware manager. 1164 * return: always 0 1165 */ 1166 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) 1167 { 1168 struct vega10_hwmgr *data = hwmgr->backend; 1169 struct phm_ppt_v2_information *table_info = 1170 (struct phm_ppt_v2_information *)hwmgr->pptable; 1171 int result; 1172 1173 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1174 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1175 result = vega10_get_mvdd_voltage_table(hwmgr, 1176 table_info->vdd_dep_on_mclk, 1177 &(data->mvdd_voltage_table)); 1178 PP_ASSERT_WITH_CODE(!result, 1179 "Failed to retrieve MVDDC table!", 1180 return result); 1181 } 1182 1183 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1184 result = vega10_get_vddci_voltage_table(hwmgr, 1185 table_info->vdd_dep_on_mclk, 1186 &(data->vddci_voltage_table)); 1187 PP_ASSERT_WITH_CODE(!result, 1188 "Failed to retrieve VDDCI_MEM table!", 1189 return result); 1190 } 1191 1192 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1193 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1194 result = vega10_get_vdd_voltage_table(hwmgr, 1195 table_info->vdd_dep_on_sclk, 1196 &(data->vddc_voltage_table)); 1197 PP_ASSERT_WITH_CODE(!result, 1198 "Failed to retrieve VDDCR_SOC table!", 1199 return result); 1200 } 1201 1202 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, 1203 "Too many voltage values for VDDC. Trimming to fit state table.", 1204 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1205 16, &(data->vddc_voltage_table))); 1206 1207 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, 1208 "Too many voltage values for VDDCI. Trimming to fit state table.", 1209 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1210 16, &(data->vddci_voltage_table))); 1211 1212 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, 1213 "Too many voltage values for MVDD. Trimming to fit state table.", 1214 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1215 16, &(data->mvdd_voltage_table))); 1216 1217 1218 return 0; 1219 } 1220 1221 /* 1222 * vega10_init_dpm_state 1223 * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 1224 * 1225 * @dpm_state: - the address of the DPM Table to initiailize. 1226 * return: None. 1227 */ 1228 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state) 1229 { 1230 dpm_state->soft_min_level = 0xff; 1231 dpm_state->soft_max_level = 0xff; 1232 dpm_state->hard_min_level = 0xff; 1233 dpm_state->hard_max_level = 0xff; 1234 } 1235 1236 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, 1237 struct vega10_single_dpm_table *dpm_table, 1238 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) 1239 { 1240 int i; 1241 1242 dpm_table->count = 0; 1243 1244 for (i = 0; i < dep_table->count; i++) { 1245 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1246 dep_table->entries[i].clk) { 1247 dpm_table->dpm_levels[dpm_table->count].value = 1248 dep_table->entries[i].clk; 1249 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1250 dpm_table->count++; 1251 } 1252 } 1253 } 1254 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 1255 { 1256 struct vega10_hwmgr *data = hwmgr->backend; 1257 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); 1258 struct phm_ppt_v2_information *table_info = 1259 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1260 struct phm_ppt_v1_pcie_table *bios_pcie_table = 1261 table_info->pcie_table; 1262 uint32_t i; 1263 1264 PP_ASSERT_WITH_CODE(bios_pcie_table->count, 1265 "Incorrect number of PCIE States from VBIOS!", 1266 return -1); 1267 1268 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1269 if (data->registry_data.pcieSpeedOverride) 1270 pcie_table->pcie_gen[i] = 1271 data->registry_data.pcieSpeedOverride; 1272 else 1273 pcie_table->pcie_gen[i] = 1274 bios_pcie_table->entries[i].gen_speed; 1275 1276 if (data->registry_data.pcieLaneOverride) 1277 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1278 data->registry_data.pcieLaneOverride); 1279 else 1280 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1281 bios_pcie_table->entries[i].lane_width); 1282 if (data->registry_data.pcieClockOverride) 1283 pcie_table->lclk[i] = 1284 data->registry_data.pcieClockOverride; 1285 else 1286 pcie_table->lclk[i] = 1287 bios_pcie_table->entries[i].pcie_sclk; 1288 } 1289 1290 pcie_table->count = NUM_LINK_LEVELS; 1291 1292 return 0; 1293 } 1294 1295 /* 1296 * This function is to initialize all DPM state tables 1297 * for SMU based on the dependency table. 1298 * Dynamic state patching function will then trim these 1299 * state tables to the allowed range based 1300 * on the power policy or external client requests, 1301 * such as UVD request, etc. 1302 */ 1303 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1304 { 1305 struct vega10_hwmgr *data = hwmgr->backend; 1306 struct phm_ppt_v2_information *table_info = 1307 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1308 struct vega10_single_dpm_table *dpm_table; 1309 uint32_t i; 1310 1311 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table = 1312 table_info->vdd_dep_on_socclk; 1313 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table = 1314 table_info->vdd_dep_on_sclk; 1315 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 1316 table_info->vdd_dep_on_mclk; 1317 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table = 1318 table_info->mm_dep_table; 1319 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table = 1320 table_info->vdd_dep_on_dcefclk; 1321 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table = 1322 table_info->vdd_dep_on_pixclk; 1323 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table = 1324 table_info->vdd_dep_on_dispclk; 1325 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table = 1326 table_info->vdd_dep_on_phyclk; 1327 1328 PP_ASSERT_WITH_CODE(dep_soc_table, 1329 "SOCCLK dependency table is missing. This table is mandatory", 1330 return -EINVAL); 1331 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, 1332 "SOCCLK dependency table is empty. This table is mandatory", 1333 return -EINVAL); 1334 1335 PP_ASSERT_WITH_CODE(dep_gfx_table, 1336 "GFXCLK dependency table is missing. This table is mandatory", 1337 return -EINVAL); 1338 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, 1339 "GFXCLK dependency table is empty. This table is mandatory", 1340 return -EINVAL); 1341 1342 PP_ASSERT_WITH_CODE(dep_mclk_table, 1343 "MCLK dependency table is missing. This table is mandatory", 1344 return -EINVAL); 1345 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 1346 "MCLK dependency table has to have is missing. This table is mandatory", 1347 return -EINVAL); 1348 1349 /* Initialize Sclk DPM table based on allow Sclk values */ 1350 dpm_table = &(data->dpm_table.soc_table); 1351 vega10_setup_default_single_dpm_table(hwmgr, 1352 dpm_table, 1353 dep_soc_table); 1354 1355 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1356 1357 dpm_table = &(data->dpm_table.gfx_table); 1358 vega10_setup_default_single_dpm_table(hwmgr, 1359 dpm_table, 1360 dep_gfx_table); 1361 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 1362 hwmgr->platform_descriptor.overdriveLimit.engineClock = 1363 dpm_table->dpm_levels[dpm_table->count-1].value; 1364 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1365 1366 /* Initialize Mclk DPM table based on allow Mclk values */ 1367 data->dpm_table.mem_table.count = 0; 1368 dpm_table = &(data->dpm_table.mem_table); 1369 vega10_setup_default_single_dpm_table(hwmgr, 1370 dpm_table, 1371 dep_mclk_table); 1372 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 1373 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 1374 dpm_table->dpm_levels[dpm_table->count-1].value; 1375 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1376 1377 data->dpm_table.eclk_table.count = 0; 1378 dpm_table = &(data->dpm_table.eclk_table); 1379 for (i = 0; i < dep_mm_table->count; i++) { 1380 if (i == 0 || dpm_table->dpm_levels 1381 [dpm_table->count - 1].value <= 1382 dep_mm_table->entries[i].eclk) { 1383 dpm_table->dpm_levels[dpm_table->count].value = 1384 dep_mm_table->entries[i].eclk; 1385 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1386 dpm_table->count++; 1387 } 1388 } 1389 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1390 1391 data->dpm_table.vclk_table.count = 0; 1392 data->dpm_table.dclk_table.count = 0; 1393 dpm_table = &(data->dpm_table.vclk_table); 1394 for (i = 0; i < dep_mm_table->count; i++) { 1395 if (i == 0 || dpm_table->dpm_levels 1396 [dpm_table->count - 1].value <= 1397 dep_mm_table->entries[i].vclk) { 1398 dpm_table->dpm_levels[dpm_table->count].value = 1399 dep_mm_table->entries[i].vclk; 1400 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1401 dpm_table->count++; 1402 } 1403 } 1404 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1405 1406 dpm_table = &(data->dpm_table.dclk_table); 1407 for (i = 0; i < dep_mm_table->count; i++) { 1408 if (i == 0 || dpm_table->dpm_levels 1409 [dpm_table->count - 1].value <= 1410 dep_mm_table->entries[i].dclk) { 1411 dpm_table->dpm_levels[dpm_table->count].value = 1412 dep_mm_table->entries[i].dclk; 1413 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1414 dpm_table->count++; 1415 } 1416 } 1417 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1418 1419 /* Assume there is no headless Vega10 for now */ 1420 dpm_table = &(data->dpm_table.dcef_table); 1421 vega10_setup_default_single_dpm_table(hwmgr, 1422 dpm_table, 1423 dep_dcef_table); 1424 1425 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1426 1427 dpm_table = &(data->dpm_table.pixel_table); 1428 vega10_setup_default_single_dpm_table(hwmgr, 1429 dpm_table, 1430 dep_pix_table); 1431 1432 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1433 1434 dpm_table = &(data->dpm_table.display_table); 1435 vega10_setup_default_single_dpm_table(hwmgr, 1436 dpm_table, 1437 dep_disp_table); 1438 1439 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1440 1441 dpm_table = &(data->dpm_table.phy_table); 1442 vega10_setup_default_single_dpm_table(hwmgr, 1443 dpm_table, 1444 dep_phy_table); 1445 1446 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1447 1448 vega10_setup_default_pcie_table(hwmgr); 1449 1450 /* Zero out the saved copy of the CUSTOM profile 1451 * This will be checked when trying to set the profile 1452 * and will require that new values be passed in 1453 */ 1454 data->custom_profile_mode[0] = 0; 1455 data->custom_profile_mode[1] = 0; 1456 data->custom_profile_mode[2] = 0; 1457 data->custom_profile_mode[3] = 0; 1458 1459 /* save a copy of the default DPM table */ 1460 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1461 sizeof(struct vega10_dpm_table)); 1462 1463 return 0; 1464 } 1465 1466 /* 1467 * vega10_populate_ulv_state 1468 * Function to provide parameters for Utral Low Voltage state to SMC. 1469 * 1470 * @hwmgr: - the address of the hardware manager. 1471 * return: Always 0. 1472 */ 1473 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) 1474 { 1475 struct vega10_hwmgr *data = hwmgr->backend; 1476 struct phm_ppt_v2_information *table_info = 1477 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1478 1479 data->smc_state_table.pp_table.UlvOffsetVid = 1480 (uint8_t)table_info->us_ulv_voltage_offset; 1481 1482 data->smc_state_table.pp_table.UlvSmnclkDid = 1483 (uint8_t)(table_info->us_ulv_smnclk_did); 1484 data->smc_state_table.pp_table.UlvMp1clkDid = 1485 (uint8_t)(table_info->us_ulv_mp1clk_did); 1486 data->smc_state_table.pp_table.UlvGfxclkBypass = 1487 (uint8_t)(table_info->us_ulv_gfxclk_bypass); 1488 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = 1489 (uint8_t)(data->vddc_voltage_table.psi0_enable); 1490 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = 1491 (uint8_t)(data->vddc_voltage_table.psi1_enable); 1492 1493 return 0; 1494 } 1495 1496 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, 1497 uint32_t lclock, uint8_t *curr_lclk_did) 1498 { 1499 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1500 1501 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1502 hwmgr, 1503 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1504 lclock, ÷rs), 1505 "Failed to get LCLK clock settings from VBIOS!", 1506 return -1); 1507 1508 *curr_lclk_did = dividers.ulDid; 1509 1510 return 0; 1511 } 1512 1513 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) 1514 { 1515 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 1516 struct vega10_hwmgr *data = 1517 (struct vega10_hwmgr *)(hwmgr->backend); 1518 uint32_t pcie_gen = 0, pcie_width = 0; 1519 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1520 int i; 1521 1522 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1523 pcie_gen = 3; 1524 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1525 pcie_gen = 2; 1526 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1527 pcie_gen = 1; 1528 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1529 pcie_gen = 0; 1530 1531 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1532 pcie_width = 6; 1533 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1534 pcie_width = 5; 1535 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1536 pcie_width = 4; 1537 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1538 pcie_width = 3; 1539 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1540 pcie_width = 2; 1541 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1542 pcie_width = 1; 1543 1544 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1545 if (pp_table->PcieGenSpeed[i] > pcie_gen) 1546 pp_table->PcieGenSpeed[i] = pcie_gen; 1547 1548 if (pp_table->PcieLaneCount[i] > pcie_width) 1549 pp_table->PcieLaneCount[i] = pcie_width; 1550 } 1551 1552 if (data->registry_data.pcie_dpm_key_disabled) { 1553 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1554 pp_table->PcieGenSpeed[i] = pcie_gen; 1555 pp_table->PcieLaneCount[i] = pcie_width; 1556 } 1557 } 1558 1559 return 0; 1560 } 1561 1562 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) 1563 { 1564 int result = -1; 1565 struct vega10_hwmgr *data = hwmgr->backend; 1566 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1567 struct vega10_pcie_table *pcie_table = 1568 &(data->dpm_table.pcie_table); 1569 uint32_t i, j; 1570 1571 for (i = 0; i < pcie_table->count; i++) { 1572 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i]; 1573 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; 1574 1575 result = vega10_populate_single_lclk_level(hwmgr, 1576 pcie_table->lclk[i], &(pp_table->LclkDid[i])); 1577 if (result) { 1578 pr_info("Populate LClock Level %d Failed!\n", i); 1579 return result; 1580 } 1581 } 1582 1583 j = i - 1; 1584 while (i < NUM_LINK_LEVELS) { 1585 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; 1586 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; 1587 1588 result = vega10_populate_single_lclk_level(hwmgr, 1589 pcie_table->lclk[j], &(pp_table->LclkDid[i])); 1590 if (result) { 1591 pr_info("Populate LClock Level %d Failed!\n", i); 1592 return result; 1593 } 1594 i++; 1595 } 1596 1597 return result; 1598 } 1599 1600 /** 1601 * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure 1602 * using the provided engine clock 1603 * 1604 * @hwmgr: the address of the hardware manager 1605 * @gfx_clock: the GFX clock to use to populate the structure. 1606 * @current_gfxclk_level: location in PPTable for the SMC GFXCLK structure. 1607 * @acg_freq: ACG frequenty to return (MHz) 1608 */ 1609 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, 1610 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, 1611 uint32_t *acg_freq) 1612 { 1613 struct phm_ppt_v2_information *table_info = 1614 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1615 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk; 1616 struct vega10_hwmgr *data = hwmgr->backend; 1617 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1618 uint32_t gfx_max_clock = 1619 hwmgr->platform_descriptor.overdriveLimit.engineClock; 1620 uint32_t i = 0; 1621 1622 if (hwmgr->od_enabled) 1623 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1624 &(data->odn_dpm_table.vdd_dep_on_sclk); 1625 else 1626 dep_on_sclk = table_info->vdd_dep_on_sclk; 1627 1628 PP_ASSERT_WITH_CODE(dep_on_sclk, 1629 "Invalid SOC_VDD-GFX_CLK Dependency Table!", 1630 return -EINVAL); 1631 1632 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 1633 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; 1634 else { 1635 for (i = 0; i < dep_on_sclk->count; i++) { 1636 if (dep_on_sclk->entries[i].clk == gfx_clock) 1637 break; 1638 } 1639 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, 1640 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", 1641 return -EINVAL); 1642 } 1643 1644 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1645 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, 1646 gfx_clock, ÷rs), 1647 "Failed to get GFX Clock settings from VBIOS!", 1648 return -EINVAL); 1649 1650 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ 1651 current_gfxclk_level->FbMult = 1652 cpu_to_le32(dividers.ulPll_fb_mult); 1653 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ 1654 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; 1655 current_gfxclk_level->SsFbMult = 1656 cpu_to_le32(dividers.ulPll_ss_fbsmult); 1657 current_gfxclk_level->SsSlewFrac = 1658 cpu_to_le16(dividers.usPll_ss_slew_frac); 1659 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); 1660 1661 *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ 1662 1663 return 0; 1664 } 1665 1666 /** 1667 * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure 1668 * using the provided clock. 1669 * 1670 * @hwmgr: the address of the hardware manager. 1671 * @soc_clock: the SOC clock to use to populate the structure. 1672 * @current_soc_did: DFS divider to pass back to caller 1673 * @current_vol_index: index of current VDD to pass back to caller 1674 * return: 0 on success 1675 */ 1676 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, 1677 uint32_t soc_clock, uint8_t *current_soc_did, 1678 uint8_t *current_vol_index) 1679 { 1680 struct vega10_hwmgr *data = hwmgr->backend; 1681 struct phm_ppt_v2_information *table_info = 1682 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1683 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc; 1684 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1685 uint32_t i; 1686 1687 if (hwmgr->od_enabled) { 1688 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1689 &data->odn_dpm_table.vdd_dep_on_socclk; 1690 for (i = 0; i < dep_on_soc->count; i++) { 1691 if (dep_on_soc->entries[i].clk >= soc_clock) 1692 break; 1693 } 1694 } else { 1695 dep_on_soc = table_info->vdd_dep_on_socclk; 1696 for (i = 0; i < dep_on_soc->count; i++) { 1697 if (dep_on_soc->entries[i].clk == soc_clock) 1698 break; 1699 } 1700 } 1701 1702 PP_ASSERT_WITH_CODE(dep_on_soc->count > i, 1703 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table", 1704 return -EINVAL); 1705 1706 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1707 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1708 soc_clock, ÷rs), 1709 "Failed to get SOC Clock settings from VBIOS!", 1710 return -EINVAL); 1711 1712 *current_soc_did = (uint8_t)dividers.ulDid; 1713 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd); 1714 return 0; 1715 } 1716 1717 /** 1718 * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure 1719 * based on the trimmed allowed dpm engine clock states 1720 * 1721 * @hwmgr: the address of the hardware manager 1722 */ 1723 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 1724 { 1725 struct vega10_hwmgr *data = hwmgr->backend; 1726 struct phm_ppt_v2_information *table_info = 1727 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1728 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1729 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 1730 int result = 0; 1731 uint32_t i, j; 1732 1733 for (i = 0; i < dpm_table->count; i++) { 1734 result = vega10_populate_single_gfx_level(hwmgr, 1735 dpm_table->dpm_levels[i].value, 1736 &(pp_table->GfxclkLevel[i]), 1737 &(pp_table->AcgFreqTable[i])); 1738 if (result) 1739 return result; 1740 } 1741 1742 j = i - 1; 1743 while (i < NUM_GFXCLK_DPM_LEVELS) { 1744 result = vega10_populate_single_gfx_level(hwmgr, 1745 dpm_table->dpm_levels[j].value, 1746 &(pp_table->GfxclkLevel[i]), 1747 &(pp_table->AcgFreqTable[i])); 1748 if (result) 1749 return result; 1750 i++; 1751 } 1752 1753 pp_table->GfxclkSlewRate = 1754 cpu_to_le16(table_info->us_gfxclk_slew_rate); 1755 1756 dpm_table = &(data->dpm_table.soc_table); 1757 for (i = 0; i < dpm_table->count; i++) { 1758 result = vega10_populate_single_soc_level(hwmgr, 1759 dpm_table->dpm_levels[i].value, 1760 &(pp_table->SocclkDid[i]), 1761 &(pp_table->SocDpmVoltageIndex[i])); 1762 if (result) 1763 return result; 1764 } 1765 1766 j = i - 1; 1767 while (i < NUM_SOCCLK_DPM_LEVELS) { 1768 result = vega10_populate_single_soc_level(hwmgr, 1769 dpm_table->dpm_levels[j].value, 1770 &(pp_table->SocclkDid[i]), 1771 &(pp_table->SocDpmVoltageIndex[i])); 1772 if (result) 1773 return result; 1774 i++; 1775 } 1776 1777 return result; 1778 } 1779 1780 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) 1781 { 1782 struct vega10_hwmgr *data = hwmgr->backend; 1783 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1784 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 1785 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 1786 1787 uint8_t soc_vid = 0; 1788 uint32_t i, max_vddc_level; 1789 1790 if (hwmgr->od_enabled) 1791 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table; 1792 else 1793 vddc_lookup_table = table_info->vddc_lookup_table; 1794 1795 max_vddc_level = vddc_lookup_table->count; 1796 for (i = 0; i < max_vddc_level; i++) { 1797 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd); 1798 pp_table->SocVid[i] = soc_vid; 1799 } 1800 while (i < MAX_REGULAR_DPM_NUMBER) { 1801 pp_table->SocVid[i] = soc_vid; 1802 i++; 1803 } 1804 } 1805 1806 /* 1807 * Populates single SMC GFXCLK structure using the provided clock. 1808 * 1809 * @hwmgr: the address of the hardware manager. 1810 * @mem_clock: the memory clock to use to populate the structure. 1811 * return: 0 on success.. 1812 */ 1813 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, 1814 uint32_t mem_clock, uint8_t *current_mem_vid, 1815 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind) 1816 { 1817 struct vega10_hwmgr *data = hwmgr->backend; 1818 struct phm_ppt_v2_information *table_info = 1819 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1820 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk; 1821 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1822 uint32_t mem_max_clock = 1823 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 1824 uint32_t i = 0; 1825 1826 if (hwmgr->od_enabled) 1827 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1828 &data->odn_dpm_table.vdd_dep_on_mclk; 1829 else 1830 dep_on_mclk = table_info->vdd_dep_on_mclk; 1831 1832 PP_ASSERT_WITH_CODE(dep_on_mclk, 1833 "Invalid SOC_VDD-UCLK Dependency Table!", 1834 return -EINVAL); 1835 1836 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 1837 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; 1838 } else { 1839 for (i = 0; i < dep_on_mclk->count; i++) { 1840 if (dep_on_mclk->entries[i].clk == mem_clock) 1841 break; 1842 } 1843 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, 1844 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", 1845 return -EINVAL); 1846 } 1847 1848 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1849 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), 1850 "Failed to get UCLK settings from VBIOS!", 1851 return -1); 1852 1853 *current_mem_vid = 1854 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd)); 1855 *current_mem_soc_vind = 1856 (uint8_t)(dep_on_mclk->entries[i].vddInd); 1857 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); 1858 current_memclk_level->Did = (uint8_t)(dividers.ulDid); 1859 1860 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, 1861 "Invalid Divider ID!", 1862 return -EINVAL); 1863 1864 return 0; 1865 } 1866 1867 /** 1868 * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure 1869 * based on the trimmed allowed dpm memory clock states. 1870 * 1871 * @hwmgr: the address of the hardware manager. 1872 * return: PP_Result_OK on success. 1873 */ 1874 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1875 { 1876 struct vega10_hwmgr *data = hwmgr->backend; 1877 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1878 struct vega10_single_dpm_table *dpm_table = 1879 &(data->dpm_table.mem_table); 1880 int result = 0; 1881 uint32_t i, j; 1882 1883 for (i = 0; i < dpm_table->count; i++) { 1884 result = vega10_populate_single_memory_level(hwmgr, 1885 dpm_table->dpm_levels[i].value, 1886 &(pp_table->MemVid[i]), 1887 &(pp_table->UclkLevel[i]), 1888 &(pp_table->MemSocVoltageIndex[i])); 1889 if (result) 1890 return result; 1891 } 1892 1893 j = i - 1; 1894 while (i < NUM_UCLK_DPM_LEVELS) { 1895 result = vega10_populate_single_memory_level(hwmgr, 1896 dpm_table->dpm_levels[j].value, 1897 &(pp_table->MemVid[i]), 1898 &(pp_table->UclkLevel[i]), 1899 &(pp_table->MemSocVoltageIndex[i])); 1900 if (result) 1901 return result; 1902 i++; 1903 } 1904 1905 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); 1906 pp_table->MemoryChannelWidth = 1907 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * 1908 channel_number[data->mem_channels]); 1909 1910 pp_table->LowestUclkReservedForUlv = 1911 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1912 1913 return result; 1914 } 1915 1916 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, 1917 DSPCLK_e disp_clock) 1918 { 1919 struct vega10_hwmgr *data = hwmgr->backend; 1920 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1921 struct phm_ppt_v2_information *table_info = 1922 (struct phm_ppt_v2_information *) 1923 (hwmgr->pptable); 1924 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1925 uint32_t i; 1926 uint16_t clk = 0, vddc = 0; 1927 uint8_t vid = 0; 1928 1929 switch (disp_clock) { 1930 case DSPCLK_DCEFCLK: 1931 dep_table = table_info->vdd_dep_on_dcefclk; 1932 break; 1933 case DSPCLK_DISPCLK: 1934 dep_table = table_info->vdd_dep_on_dispclk; 1935 break; 1936 case DSPCLK_PIXCLK: 1937 dep_table = table_info->vdd_dep_on_pixclk; 1938 break; 1939 case DSPCLK_PHYCLK: 1940 dep_table = table_info->vdd_dep_on_phyclk; 1941 break; 1942 default: 1943 return -1; 1944 } 1945 1946 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, 1947 "Number Of Entries Exceeded maximum!", 1948 return -1); 1949 1950 for (i = 0; i < dep_table->count; i++) { 1951 clk = (uint16_t)(dep_table->entries[i].clk / 100); 1952 vddc = table_info->vddc_lookup_table-> 1953 entries[dep_table->entries[i].vddInd].us_vdd; 1954 vid = (uint8_t)convert_to_vid(vddc); 1955 pp_table->DisplayClockTable[disp_clock][i].Freq = 1956 cpu_to_le16(clk); 1957 pp_table->DisplayClockTable[disp_clock][i].Vid = 1958 cpu_to_le16(vid); 1959 } 1960 1961 while (i < NUM_DSPCLK_LEVELS) { 1962 pp_table->DisplayClockTable[disp_clock][i].Freq = 1963 cpu_to_le16(clk); 1964 pp_table->DisplayClockTable[disp_clock][i].Vid = 1965 cpu_to_le16(vid); 1966 i++; 1967 } 1968 1969 return 0; 1970 } 1971 1972 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) 1973 { 1974 uint32_t i; 1975 1976 for (i = 0; i < DSPCLK_COUNT; i++) { 1977 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), 1978 "Failed to populate Clock in DisplayClockTable!", 1979 return -1); 1980 } 1981 1982 return 0; 1983 } 1984 1985 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, 1986 uint32_t eclock, uint8_t *current_eclk_did, 1987 uint8_t *current_soc_vol) 1988 { 1989 struct phm_ppt_v2_information *table_info = 1990 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1991 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 1992 table_info->mm_dep_table; 1993 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1994 uint32_t i; 1995 1996 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1997 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1998 eclock, ÷rs), 1999 "Failed to get ECLK clock settings from VBIOS!", 2000 return -1); 2001 2002 *current_eclk_did = (uint8_t)dividers.ulDid; 2003 2004 for (i = 0; i < dep_table->count; i++) { 2005 if (dep_table->entries[i].eclk == eclock) 2006 *current_soc_vol = dep_table->entries[i].vddcInd; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) 2013 { 2014 struct vega10_hwmgr *data = hwmgr->backend; 2015 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2016 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); 2017 int result = -EINVAL; 2018 uint32_t i, j; 2019 2020 for (i = 0; i < dpm_table->count; i++) { 2021 result = vega10_populate_single_eclock_level(hwmgr, 2022 dpm_table->dpm_levels[i].value, 2023 &(pp_table->EclkDid[i]), 2024 &(pp_table->VceDpmVoltageIndex[i])); 2025 if (result) 2026 return result; 2027 } 2028 2029 j = i - 1; 2030 while (i < NUM_VCE_DPM_LEVELS) { 2031 result = vega10_populate_single_eclock_level(hwmgr, 2032 dpm_table->dpm_levels[j].value, 2033 &(pp_table->EclkDid[i]), 2034 &(pp_table->VceDpmVoltageIndex[i])); 2035 if (result) 2036 return result; 2037 i++; 2038 } 2039 2040 return result; 2041 } 2042 2043 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, 2044 uint32_t vclock, uint8_t *current_vclk_did) 2045 { 2046 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2047 2048 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2049 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2050 vclock, ÷rs), 2051 "Failed to get VCLK clock settings from VBIOS!", 2052 return -EINVAL); 2053 2054 *current_vclk_did = (uint8_t)dividers.ulDid; 2055 2056 return 0; 2057 } 2058 2059 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, 2060 uint32_t dclock, uint8_t *current_dclk_did) 2061 { 2062 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2063 2064 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2065 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2066 dclock, ÷rs), 2067 "Failed to get DCLK clock settings from VBIOS!", 2068 return -EINVAL); 2069 2070 *current_dclk_did = (uint8_t)dividers.ulDid; 2071 2072 return 0; 2073 } 2074 2075 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) 2076 { 2077 struct vega10_hwmgr *data = hwmgr->backend; 2078 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2079 struct vega10_single_dpm_table *vclk_dpm_table = 2080 &(data->dpm_table.vclk_table); 2081 struct vega10_single_dpm_table *dclk_dpm_table = 2082 &(data->dpm_table.dclk_table); 2083 struct phm_ppt_v2_information *table_info = 2084 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2085 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 2086 table_info->mm_dep_table; 2087 int result = -EINVAL; 2088 uint32_t i, j; 2089 2090 for (i = 0; i < vclk_dpm_table->count; i++) { 2091 result = vega10_populate_single_vclock_level(hwmgr, 2092 vclk_dpm_table->dpm_levels[i].value, 2093 &(pp_table->VclkDid[i])); 2094 if (result) 2095 return result; 2096 } 2097 2098 j = i - 1; 2099 while (i < NUM_UVD_DPM_LEVELS) { 2100 result = vega10_populate_single_vclock_level(hwmgr, 2101 vclk_dpm_table->dpm_levels[j].value, 2102 &(pp_table->VclkDid[i])); 2103 if (result) 2104 return result; 2105 i++; 2106 } 2107 2108 for (i = 0; i < dclk_dpm_table->count; i++) { 2109 result = vega10_populate_single_dclock_level(hwmgr, 2110 dclk_dpm_table->dpm_levels[i].value, 2111 &(pp_table->DclkDid[i])); 2112 if (result) 2113 return result; 2114 } 2115 2116 j = i - 1; 2117 while (i < NUM_UVD_DPM_LEVELS) { 2118 result = vega10_populate_single_dclock_level(hwmgr, 2119 dclk_dpm_table->dpm_levels[j].value, 2120 &(pp_table->DclkDid[i])); 2121 if (result) 2122 return result; 2123 i++; 2124 } 2125 2126 for (i = 0; i < dep_table->count; i++) { 2127 if (dep_table->entries[i].vclk == 2128 vclk_dpm_table->dpm_levels[i].value && 2129 dep_table->entries[i].dclk == 2130 dclk_dpm_table->dpm_levels[i].value) 2131 pp_table->UvdDpmVoltageIndex[i] = 2132 dep_table->entries[i].vddcInd; 2133 else 2134 return -1; 2135 } 2136 2137 j = i - 1; 2138 while (i < NUM_UVD_DPM_LEVELS) { 2139 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd; 2140 i++; 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) 2147 { 2148 struct vega10_hwmgr *data = hwmgr->backend; 2149 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2150 struct phm_ppt_v2_information *table_info = 2151 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2152 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2153 table_info->vdd_dep_on_sclk; 2154 uint32_t i; 2155 2156 for (i = 0; i < dep_table->count; i++) { 2157 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable; 2158 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset 2159 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 2166 { 2167 struct vega10_hwmgr *data = hwmgr->backend; 2168 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2169 struct phm_ppt_v2_information *table_info = 2170 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2171 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2172 table_info->vdd_dep_on_sclk; 2173 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 2174 int result = 0; 2175 uint32_t i; 2176 2177 pp_table->MinVoltageVid = (uint8_t)0xff; 2178 pp_table->MaxVoltageVid = (uint8_t)0; 2179 2180 if (data->smu_features[GNLD_AVFS].supported) { 2181 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 2182 if (!result) { 2183 pp_table->MinVoltageVid = (uint8_t) 2184 convert_to_vid((uint16_t)(avfs_params.ulMinVddc)); 2185 pp_table->MaxVoltageVid = (uint8_t) 2186 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc)); 2187 2188 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); 2189 pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1); 2190 pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2); 2191 pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2192 pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean); 2193 pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2194 pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor); 2195 2196 pp_table->BtcGbVdroopTableCksOff.a0 = 2197 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0); 2198 pp_table->BtcGbVdroopTableCksOff.a0_shift = 20; 2199 pp_table->BtcGbVdroopTableCksOff.a1 = 2200 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1); 2201 pp_table->BtcGbVdroopTableCksOff.a1_shift = 20; 2202 pp_table->BtcGbVdroopTableCksOff.a2 = 2203 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2); 2204 pp_table->BtcGbVdroopTableCksOff.a2_shift = 20; 2205 2206 pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson; 2207 pp_table->BtcGbVdroopTableCksOn.a0 = 2208 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0); 2209 pp_table->BtcGbVdroopTableCksOn.a0_shift = 20; 2210 pp_table->BtcGbVdroopTableCksOn.a1 = 2211 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1); 2212 pp_table->BtcGbVdroopTableCksOn.a1_shift = 20; 2213 pp_table->BtcGbVdroopTableCksOn.a2 = 2214 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2); 2215 pp_table->BtcGbVdroopTableCksOn.a2_shift = 20; 2216 2217 pp_table->AvfsGbCksOn.m1 = 2218 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); 2219 pp_table->AvfsGbCksOn.m2 = 2220 cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); 2221 pp_table->AvfsGbCksOn.b = 2222 cpu_to_le32(avfs_params.ulGbFuseTableCksonB); 2223 pp_table->AvfsGbCksOn.m1_shift = 24; 2224 pp_table->AvfsGbCksOn.m2_shift = 12; 2225 pp_table->AvfsGbCksOn.b_shift = 0; 2226 2227 pp_table->OverrideAvfsGbCksOn = 2228 avfs_params.ucEnableGbFuseTableCkson; 2229 pp_table->AvfsGbCksOff.m1 = 2230 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); 2231 pp_table->AvfsGbCksOff.m2 = 2232 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); 2233 pp_table->AvfsGbCksOff.b = 2234 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); 2235 pp_table->AvfsGbCksOff.m1_shift = 24; 2236 pp_table->AvfsGbCksOff.m2_shift = 12; 2237 pp_table->AvfsGbCksOff.b_shift = 0; 2238 2239 for (i = 0; i < dep_table->count; i++) 2240 pp_table->StaticVoltageOffsetVid[i] = 2241 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset)); 2242 2243 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2244 data->disp_clk_quad_eqn_a) && 2245 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2246 data->disp_clk_quad_eqn_b)) { 2247 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2248 (int32_t)data->disp_clk_quad_eqn_a; 2249 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2250 (int32_t)data->disp_clk_quad_eqn_b; 2251 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2252 (int32_t)data->disp_clk_quad_eqn_c; 2253 } else { 2254 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2255 (int32_t)avfs_params.ulDispclk2GfxclkM1; 2256 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2257 (int32_t)avfs_params.ulDispclk2GfxclkM2; 2258 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2259 (int32_t)avfs_params.ulDispclk2GfxclkB; 2260 } 2261 2262 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; 2263 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; 2264 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; 2265 2266 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2267 data->dcef_clk_quad_eqn_a) && 2268 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2269 data->dcef_clk_quad_eqn_b)) { 2270 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2271 (int32_t)data->dcef_clk_quad_eqn_a; 2272 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2273 (int32_t)data->dcef_clk_quad_eqn_b; 2274 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2275 (int32_t)data->dcef_clk_quad_eqn_c; 2276 } else { 2277 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2278 (int32_t)avfs_params.ulDcefclk2GfxclkM1; 2279 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2280 (int32_t)avfs_params.ulDcefclk2GfxclkM2; 2281 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2282 (int32_t)avfs_params.ulDcefclk2GfxclkB; 2283 } 2284 2285 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; 2286 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; 2287 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; 2288 2289 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2290 data->pixel_clk_quad_eqn_a) && 2291 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2292 data->pixel_clk_quad_eqn_b)) { 2293 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2294 (int32_t)data->pixel_clk_quad_eqn_a; 2295 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2296 (int32_t)data->pixel_clk_quad_eqn_b; 2297 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2298 (int32_t)data->pixel_clk_quad_eqn_c; 2299 } else { 2300 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2301 (int32_t)avfs_params.ulPixelclk2GfxclkM1; 2302 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2303 (int32_t)avfs_params.ulPixelclk2GfxclkM2; 2304 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2305 (int32_t)avfs_params.ulPixelclk2GfxclkB; 2306 } 2307 2308 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; 2309 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; 2310 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; 2311 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2312 data->phy_clk_quad_eqn_a) && 2313 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2314 data->phy_clk_quad_eqn_b)) { 2315 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2316 (int32_t)data->phy_clk_quad_eqn_a; 2317 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2318 (int32_t)data->phy_clk_quad_eqn_b; 2319 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2320 (int32_t)data->phy_clk_quad_eqn_c; 2321 } else { 2322 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2323 (int32_t)avfs_params.ulPhyclk2GfxclkM1; 2324 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2325 (int32_t)avfs_params.ulPhyclk2GfxclkM2; 2326 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2327 (int32_t)avfs_params.ulPhyclk2GfxclkB; 2328 } 2329 2330 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; 2331 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; 2332 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; 2333 2334 pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0; 2335 pp_table->AcgBtcGbVdroopTable.a0_shift = 20; 2336 pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1; 2337 pp_table->AcgBtcGbVdroopTable.a1_shift = 20; 2338 pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2; 2339 pp_table->AcgBtcGbVdroopTable.a2_shift = 20; 2340 2341 pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1; 2342 pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2; 2343 pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB; 2344 pp_table->AcgAvfsGb.m1_shift = 24; 2345 pp_table->AcgAvfsGb.m2_shift = 12; 2346 pp_table->AcgAvfsGb.b_shift = 0; 2347 2348 } else { 2349 data->smu_features[GNLD_AVFS].supported = false; 2350 } 2351 } 2352 2353 return 0; 2354 } 2355 2356 static int vega10_acg_enable(struct pp_hwmgr *hwmgr) 2357 { 2358 struct vega10_hwmgr *data = hwmgr->backend; 2359 uint32_t agc_btc_response; 2360 int ret; 2361 2362 if (data->smu_features[GNLD_ACG].supported) { 2363 if (0 == vega10_enable_smc_features(hwmgr, true, 2364 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) 2365 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; 2366 2367 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); 2368 if (ret) 2369 return ret; 2370 2371 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); 2372 if (ret) 2373 agc_btc_response = 0; 2374 2375 if (1 == agc_btc_response) { 2376 if (1 == data->acg_loop_state) 2377 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); 2378 else if (2 == data->acg_loop_state) 2379 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); 2380 if (0 == vega10_enable_smc_features(hwmgr, true, 2381 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2382 data->smu_features[GNLD_ACG].enabled = true; 2383 } else { 2384 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n"); 2385 data->smu_features[GNLD_ACG].enabled = false; 2386 } 2387 } 2388 2389 return 0; 2390 } 2391 2392 static int vega10_acg_disable(struct pp_hwmgr *hwmgr) 2393 { 2394 struct vega10_hwmgr *data = hwmgr->backend; 2395 2396 if (data->smu_features[GNLD_ACG].supported && 2397 data->smu_features[GNLD_ACG].enabled) 2398 if (!vega10_enable_smc_features(hwmgr, false, 2399 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2400 data->smu_features[GNLD_ACG].enabled = false; 2401 2402 return 0; 2403 } 2404 2405 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) 2406 { 2407 struct vega10_hwmgr *data = hwmgr->backend; 2408 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2409 struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; 2410 int result; 2411 2412 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); 2413 if (!result) { 2414 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && 2415 data->registry_data.regulator_hot_gpio_support) { 2416 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; 2417 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; 2418 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; 2419 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity; 2420 } else { 2421 pp_table->VR0HotGpio = 0; 2422 pp_table->VR0HotPolarity = 0; 2423 pp_table->VR1HotGpio = 0; 2424 pp_table->VR1HotPolarity = 0; 2425 } 2426 2427 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && 2428 data->registry_data.ac_dc_switch_gpio_support) { 2429 pp_table->AcDcGpio = gpio_params.ucAcDcGpio; 2430 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; 2431 } else { 2432 pp_table->AcDcGpio = 0; 2433 pp_table->AcDcPolarity = 0; 2434 } 2435 } 2436 2437 return result; 2438 } 2439 2440 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) 2441 { 2442 struct vega10_hwmgr *data = hwmgr->backend; 2443 2444 if (data->smu_features[GNLD_AVFS].supported) { 2445 /* Already enabled or disabled */ 2446 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled)) 2447 return 0; 2448 2449 if (enable) { 2450 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2451 true, 2452 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2453 "[avfs_control] Attempt to Enable AVFS feature Failed!", 2454 return -1); 2455 data->smu_features[GNLD_AVFS].enabled = true; 2456 } else { 2457 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2458 false, 2459 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2460 "[avfs_control] Attempt to Disable AVFS feature Failed!", 2461 return -1); 2462 data->smu_features[GNLD_AVFS].enabled = false; 2463 } 2464 } 2465 2466 return 0; 2467 } 2468 2469 static int vega10_update_avfs(struct pp_hwmgr *hwmgr) 2470 { 2471 struct vega10_hwmgr *data = hwmgr->backend; 2472 2473 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 2474 vega10_avfs_enable(hwmgr, false); 2475 } else if (data->need_update_dpm_table) { 2476 vega10_avfs_enable(hwmgr, false); 2477 vega10_avfs_enable(hwmgr, true); 2478 } else { 2479 vega10_avfs_enable(hwmgr, true); 2480 } 2481 2482 return 0; 2483 } 2484 2485 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) 2486 { 2487 int result = 0; 2488 2489 uint64_t serial_number = 0; 2490 uint32_t top32, bottom32; 2491 struct phm_fuses_default fuse; 2492 2493 struct vega10_hwmgr *data = hwmgr->backend; 2494 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); 2495 2496 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 2497 if (result) 2498 return result; 2499 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 2500 if (result) 2501 return result; 2502 serial_number = ((uint64_t)bottom32 << 32) | top32; 2503 2504 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { 2505 avfs_fuse_table->VFT0_b = fuse.VFT0_b; 2506 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; 2507 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; 2508 avfs_fuse_table->VFT1_b = fuse.VFT1_b; 2509 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; 2510 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; 2511 avfs_fuse_table->VFT2_b = fuse.VFT2_b; 2512 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; 2513 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; 2514 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, 2515 AVFSFUSETABLE, false); 2516 PP_ASSERT_WITH_CODE(!result, 2517 "Failed to upload FuseOVerride!", 2518 ); 2519 } 2520 2521 return result; 2522 } 2523 2524 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 2525 { 2526 struct vega10_hwmgr *data = hwmgr->backend; 2527 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2528 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 2529 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 2530 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 2531 uint32_t i; 2532 2533 dep_table = table_info->vdd_dep_on_mclk; 2534 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk); 2535 2536 for (i = 0; i < dep_table->count; i++) { 2537 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2538 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 2539 return; 2540 } 2541 } 2542 2543 dep_table = table_info->vdd_dep_on_sclk; 2544 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk); 2545 for (i = 0; i < dep_table->count; i++) { 2546 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2547 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 2548 return; 2549 } 2550 } 2551 } 2552 2553 /** 2554 * vega10_init_smc_table - Initializes the SMC table and uploads it 2555 * 2556 * @hwmgr: the address of the powerplay hardware manager. 2557 * return: always 0 2558 */ 2559 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) 2560 { 2561 int result; 2562 struct vega10_hwmgr *data = hwmgr->backend; 2563 struct phm_ppt_v2_information *table_info = 2564 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2565 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2566 struct pp_atomfwctrl_voltage_table voltage_table; 2567 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 2568 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2569 2570 result = vega10_setup_default_dpm_tables(hwmgr); 2571 PP_ASSERT_WITH_CODE(!result, 2572 "Failed to setup default DPM tables!", 2573 return result); 2574 2575 if (!hwmgr->not_vf) 2576 return 0; 2577 2578 /* initialize ODN table */ 2579 if (hwmgr->od_enabled) { 2580 if (odn_table->max_vddc) { 2581 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 2582 vega10_check_dpm_table_updated(hwmgr); 2583 } else { 2584 vega10_odn_initial_default_setting(hwmgr); 2585 } 2586 } 2587 2588 result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, 2589 VOLTAGE_OBJ_SVID2, &voltage_table); 2590 PP_ASSERT_WITH_CODE(!result, 2591 "Failed to get voltage table!", 2592 return result); 2593 pp_table->MaxVidStep = voltage_table.max_vid_step; 2594 2595 pp_table->GfxDpmVoltageMode = 2596 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode); 2597 pp_table->SocDpmVoltageMode = 2598 (uint8_t)(table_info->uc_soc_dpm_voltage_mode); 2599 pp_table->UclkDpmVoltageMode = 2600 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode); 2601 pp_table->UvdDpmVoltageMode = 2602 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode); 2603 pp_table->VceDpmVoltageMode = 2604 (uint8_t)(table_info->uc_vce_dpm_voltage_mode); 2605 pp_table->Mp0DpmVoltageMode = 2606 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode); 2607 2608 pp_table->DisplayDpmVoltageMode = 2609 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); 2610 2611 data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; 2612 data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; 2613 2614 if (data->registry_data.ulv_support && 2615 table_info->us_ulv_voltage_offset) { 2616 result = vega10_populate_ulv_state(hwmgr); 2617 PP_ASSERT_WITH_CODE(!result, 2618 "Failed to initialize ULV state!", 2619 return result); 2620 } 2621 2622 result = vega10_populate_smc_link_levels(hwmgr); 2623 PP_ASSERT_WITH_CODE(!result, 2624 "Failed to initialize Link Level!", 2625 return result); 2626 2627 result = vega10_override_pcie_parameters(hwmgr); 2628 PP_ASSERT_WITH_CODE(!result, 2629 "Failed to override pcie parameters!", 2630 return result); 2631 2632 result = vega10_populate_all_graphic_levels(hwmgr); 2633 PP_ASSERT_WITH_CODE(!result, 2634 "Failed to initialize Graphics Level!", 2635 return result); 2636 2637 result = vega10_populate_all_memory_levels(hwmgr); 2638 PP_ASSERT_WITH_CODE(!result, 2639 "Failed to initialize Memory Level!", 2640 return result); 2641 2642 vega10_populate_vddc_soc_levels(hwmgr); 2643 2644 result = vega10_populate_all_display_clock_levels(hwmgr); 2645 PP_ASSERT_WITH_CODE(!result, 2646 "Failed to initialize Display Level!", 2647 return result); 2648 2649 result = vega10_populate_smc_vce_levels(hwmgr); 2650 PP_ASSERT_WITH_CODE(!result, 2651 "Failed to initialize VCE Level!", 2652 return result); 2653 2654 result = vega10_populate_smc_uvd_levels(hwmgr); 2655 PP_ASSERT_WITH_CODE(!result, 2656 "Failed to initialize UVD Level!", 2657 return result); 2658 2659 if (data->registry_data.clock_stretcher_support) { 2660 result = vega10_populate_clock_stretcher_table(hwmgr); 2661 PP_ASSERT_WITH_CODE(!result, 2662 "Failed to populate Clock Stretcher Table!", 2663 return result); 2664 } 2665 2666 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 2667 if (!result) { 2668 data->vbios_boot_state.vddc = boot_up_values.usVddc; 2669 data->vbios_boot_state.vddci = boot_up_values.usVddci; 2670 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 2671 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 2672 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 2673 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2674 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); 2675 2676 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2677 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); 2678 2679 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 2680 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 2681 if (0 != boot_up_values.usVddc) { 2682 smum_send_msg_to_smc_with_parameter(hwmgr, 2683 PPSMC_MSG_SetFloorSocVoltage, 2684 (boot_up_values.usVddc * 4), 2685 NULL); 2686 data->vbios_boot_state.bsoc_vddc_lock = true; 2687 } else { 2688 data->vbios_boot_state.bsoc_vddc_lock = false; 2689 } 2690 smum_send_msg_to_smc_with_parameter(hwmgr, 2691 PPSMC_MSG_SetMinDeepSleepDcefclk, 2692 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 2693 NULL); 2694 } 2695 2696 result = vega10_populate_avfs_parameters(hwmgr); 2697 PP_ASSERT_WITH_CODE(!result, 2698 "Failed to initialize AVFS Parameters!", 2699 return result); 2700 2701 result = vega10_populate_gpio_parameters(hwmgr); 2702 PP_ASSERT_WITH_CODE(!result, 2703 "Failed to initialize GPIO Parameters!", 2704 return result); 2705 2706 pp_table->GfxclkAverageAlpha = (uint8_t) 2707 (data->gfxclk_average_alpha); 2708 pp_table->SocclkAverageAlpha = (uint8_t) 2709 (data->socclk_average_alpha); 2710 pp_table->UclkAverageAlpha = (uint8_t) 2711 (data->uclk_average_alpha); 2712 pp_table->GfxActivityAverageAlpha = (uint8_t) 2713 (data->gfx_activity_average_alpha); 2714 2715 vega10_populate_and_upload_avfs_fuse_override(hwmgr); 2716 2717 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 2718 2719 PP_ASSERT_WITH_CODE(!result, 2720 "Failed to upload PPtable!", return result); 2721 2722 result = vega10_avfs_enable(hwmgr, true); 2723 PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", 2724 return result); 2725 vega10_acg_enable(hwmgr); 2726 2727 return 0; 2728 } 2729 2730 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) 2731 { 2732 struct vega10_hwmgr *data = hwmgr->backend; 2733 2734 if (data->smu_features[GNLD_THERMAL].supported) { 2735 if (data->smu_features[GNLD_THERMAL].enabled) 2736 pr_info("THERMAL Feature Already enabled!"); 2737 2738 PP_ASSERT_WITH_CODE( 2739 !vega10_enable_smc_features(hwmgr, 2740 true, 2741 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2742 "Enable THERMAL Feature Failed!", 2743 return -1); 2744 data->smu_features[GNLD_THERMAL].enabled = true; 2745 } 2746 2747 return 0; 2748 } 2749 2750 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) 2751 { 2752 struct vega10_hwmgr *data = hwmgr->backend; 2753 2754 if (data->smu_features[GNLD_THERMAL].supported) { 2755 if (!data->smu_features[GNLD_THERMAL].enabled) 2756 pr_info("THERMAL Feature Already disabled!"); 2757 2758 PP_ASSERT_WITH_CODE( 2759 !vega10_enable_smc_features(hwmgr, 2760 false, 2761 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2762 "disable THERMAL Feature Failed!", 2763 return -1); 2764 data->smu_features[GNLD_THERMAL].enabled = false; 2765 } 2766 2767 return 0; 2768 } 2769 2770 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) 2771 { 2772 struct vega10_hwmgr *data = hwmgr->backend; 2773 2774 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { 2775 if (data->smu_features[GNLD_VR0HOT].supported) { 2776 PP_ASSERT_WITH_CODE( 2777 !vega10_enable_smc_features(hwmgr, 2778 true, 2779 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), 2780 "Attempt to Enable VR0 Hot feature Failed!", 2781 return -1); 2782 data->smu_features[GNLD_VR0HOT].enabled = true; 2783 } else { 2784 if (data->smu_features[GNLD_VR1HOT].supported) { 2785 PP_ASSERT_WITH_CODE( 2786 !vega10_enable_smc_features(hwmgr, 2787 true, 2788 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), 2789 "Attempt to Enable VR0 Hot feature Failed!", 2790 return -1); 2791 data->smu_features[GNLD_VR1HOT].enabled = true; 2792 } 2793 } 2794 } 2795 return 0; 2796 } 2797 2798 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) 2799 { 2800 struct vega10_hwmgr *data = hwmgr->backend; 2801 2802 if (data->registry_data.ulv_support) { 2803 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2804 true, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2805 "Enable ULV Feature Failed!", 2806 return -1); 2807 data->smu_features[GNLD_ULV].enabled = true; 2808 } 2809 2810 return 0; 2811 } 2812 2813 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) 2814 { 2815 struct vega10_hwmgr *data = hwmgr->backend; 2816 2817 if (data->registry_data.ulv_support) { 2818 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2819 false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2820 "disable ULV Feature Failed!", 2821 return -EINVAL); 2822 data->smu_features[GNLD_ULV].enabled = false; 2823 } 2824 2825 return 0; 2826 } 2827 2828 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2829 { 2830 struct vega10_hwmgr *data = hwmgr->backend; 2831 2832 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2833 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2834 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2835 "Attempt to Enable DS_GFXCLK Feature Failed!", 2836 return -EINVAL); 2837 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 2838 } 2839 2840 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2841 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2842 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2843 "Attempt to Enable DS_SOCCLK Feature Failed!", 2844 return -EINVAL); 2845 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 2846 } 2847 2848 if (data->smu_features[GNLD_DS_LCLK].supported) { 2849 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2850 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2851 "Attempt to Enable DS_LCLK Feature Failed!", 2852 return -EINVAL); 2853 data->smu_features[GNLD_DS_LCLK].enabled = true; 2854 } 2855 2856 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2857 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2858 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2859 "Attempt to Enable DS_DCEFCLK Feature Failed!", 2860 return -EINVAL); 2861 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 2862 } 2863 2864 return 0; 2865 } 2866 2867 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2868 { 2869 struct vega10_hwmgr *data = hwmgr->backend; 2870 2871 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2872 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2873 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2874 "Attempt to disable DS_GFXCLK Feature Failed!", 2875 return -EINVAL); 2876 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 2877 } 2878 2879 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2880 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2881 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2882 "Attempt to disable DS_ Feature Failed!", 2883 return -EINVAL); 2884 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 2885 } 2886 2887 if (data->smu_features[GNLD_DS_LCLK].supported) { 2888 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2889 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2890 "Attempt to disable DS_LCLK Feature Failed!", 2891 return -EINVAL); 2892 data->smu_features[GNLD_DS_LCLK].enabled = false; 2893 } 2894 2895 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2896 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2897 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2898 "Attempt to disable DS_DCEFCLK Feature Failed!", 2899 return -EINVAL); 2900 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 2901 } 2902 2903 return 0; 2904 } 2905 2906 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2907 { 2908 struct vega10_hwmgr *data = hwmgr->backend; 2909 uint32_t i, feature_mask = 0; 2910 2911 if (!hwmgr->not_vf) 2912 return 0; 2913 2914 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2915 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2916 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2917 "Attempt to disable LED DPM feature failed!", return -EINVAL); 2918 data->smu_features[GNLD_LED_DISPLAY].enabled = false; 2919 } 2920 2921 for (i = 0; i < GNLD_DPM_MAX; i++) { 2922 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2923 if (data->smu_features[i].supported) { 2924 if (data->smu_features[i].enabled) { 2925 feature_mask |= data->smu_features[i]. 2926 smu_feature_bitmap; 2927 data->smu_features[i].enabled = false; 2928 } 2929 } 2930 } 2931 } 2932 2933 return vega10_enable_smc_features(hwmgr, false, feature_mask); 2934 } 2935 2936 /** 2937 * vega10_start_dpm - Tell SMC to enabled the supported DPMs. 2938 * 2939 * @hwmgr: the address of the powerplay hardware manager. 2940 * @bitmap: bitmap for the features to enabled. 2941 * return: 0 on at least one DPM is successfully enabled. 2942 */ 2943 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2944 { 2945 struct vega10_hwmgr *data = hwmgr->backend; 2946 uint32_t i, feature_mask = 0; 2947 2948 for (i = 0; i < GNLD_DPM_MAX; i++) { 2949 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2950 if (data->smu_features[i].supported) { 2951 if (!data->smu_features[i].enabled) { 2952 feature_mask |= data->smu_features[i]. 2953 smu_feature_bitmap; 2954 data->smu_features[i].enabled = true; 2955 } 2956 } 2957 } 2958 } 2959 2960 if (vega10_enable_smc_features(hwmgr, 2961 true, feature_mask)) { 2962 for (i = 0; i < GNLD_DPM_MAX; i++) { 2963 if (data->smu_features[i].smu_feature_bitmap & 2964 feature_mask) 2965 data->smu_features[i].enabled = false; 2966 } 2967 } 2968 2969 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2970 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2971 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2972 "Attempt to Enable LED DPM feature Failed!", return -EINVAL); 2973 data->smu_features[GNLD_LED_DISPLAY].enabled = true; 2974 } 2975 2976 if (data->vbios_boot_state.bsoc_vddc_lock) { 2977 smum_send_msg_to_smc_with_parameter(hwmgr, 2978 PPSMC_MSG_SetFloorSocVoltage, 0, 2979 NULL); 2980 data->vbios_boot_state.bsoc_vddc_lock = false; 2981 } 2982 2983 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { 2984 if (data->smu_features[GNLD_ACDC].supported) { 2985 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2986 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), 2987 "Attempt to Enable DS_GFXCLK Feature Failed!", 2988 return -1); 2989 data->smu_features[GNLD_ACDC].enabled = true; 2990 } 2991 } 2992 2993 if (data->registry_data.pcie_dpm_key_disabled) { 2994 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2995 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), 2996 "Attempt to Disable Link DPM feature Failed!", return -EINVAL); 2997 data->smu_features[GNLD_DPM_LINK].enabled = false; 2998 data->smu_features[GNLD_DPM_LINK].supported = false; 2999 } 3000 3001 return 0; 3002 } 3003 3004 3005 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) 3006 { 3007 struct vega10_hwmgr *data = hwmgr->backend; 3008 3009 if (data->smu_features[GNLD_PCC_LIMIT].supported) { 3010 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) 3011 pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); 3012 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3013 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), 3014 "Attempt to Enable PCC Limit feature Failed!", 3015 return -EINVAL); 3016 data->smu_features[GNLD_PCC_LIMIT].enabled = enable; 3017 } 3018 3019 return 0; 3020 } 3021 3022 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 3023 { 3024 struct phm_ppt_v2_information *table_info = 3025 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3026 3027 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 3028 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 3029 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 3030 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 3031 } else { 3032 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3033 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; 3034 } 3035 3036 hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk; 3037 hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk; 3038 3039 /* make sure the output is in Mhz */ 3040 hwmgr->pstate_sclk /= 100; 3041 hwmgr->pstate_mclk /= 100; 3042 hwmgr->pstate_sclk_peak /= 100; 3043 hwmgr->pstate_mclk_peak /= 100; 3044 } 3045 3046 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 3047 { 3048 struct vega10_hwmgr *data = hwmgr->backend; 3049 int tmp_result, result = 0; 3050 3051 if (hwmgr->not_vf) { 3052 vega10_enable_disable_PCC_limit_feature(hwmgr, true); 3053 3054 smum_send_msg_to_smc_with_parameter(hwmgr, 3055 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry, 3056 NULL); 3057 3058 tmp_result = vega10_construct_voltage_tables(hwmgr); 3059 PP_ASSERT_WITH_CODE(!tmp_result, 3060 "Failed to construct voltage tables!", 3061 result = tmp_result); 3062 } 3063 3064 if (hwmgr->not_vf || hwmgr->pp_one_vf) { 3065 tmp_result = vega10_init_smc_table(hwmgr); 3066 PP_ASSERT_WITH_CODE(!tmp_result, 3067 "Failed to initialize SMC table!", 3068 result = tmp_result); 3069 } 3070 3071 if (hwmgr->not_vf) { 3072 if (PP_CAP(PHM_PlatformCaps_ThermalController)) { 3073 tmp_result = vega10_enable_thermal_protection(hwmgr); 3074 PP_ASSERT_WITH_CODE(!tmp_result, 3075 "Failed to enable thermal protection!", 3076 result = tmp_result); 3077 } 3078 3079 tmp_result = vega10_enable_vrhot_feature(hwmgr); 3080 PP_ASSERT_WITH_CODE(!tmp_result, 3081 "Failed to enable VR hot feature!", 3082 result = tmp_result); 3083 3084 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); 3085 PP_ASSERT_WITH_CODE(!tmp_result, 3086 "Failed to enable deep sleep master switch!", 3087 result = tmp_result); 3088 } 3089 3090 if (hwmgr->not_vf) { 3091 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); 3092 PP_ASSERT_WITH_CODE(!tmp_result, 3093 "Failed to start DPM!", result = tmp_result); 3094 } 3095 3096 if (hwmgr->not_vf) { 3097 /* enable didt, do not abort if failed didt */ 3098 tmp_result = vega10_enable_didt_config(hwmgr); 3099 PP_ASSERT(!tmp_result, 3100 "Failed to enable didt config!"); 3101 } 3102 3103 tmp_result = vega10_enable_power_containment(hwmgr); 3104 PP_ASSERT_WITH_CODE(!tmp_result, 3105 "Failed to enable power containment!", 3106 result = tmp_result); 3107 3108 if (hwmgr->not_vf) { 3109 tmp_result = vega10_power_control_set_level(hwmgr); 3110 PP_ASSERT_WITH_CODE(!tmp_result, 3111 "Failed to power control set level!", 3112 result = tmp_result); 3113 3114 tmp_result = vega10_enable_ulv(hwmgr); 3115 PP_ASSERT_WITH_CODE(!tmp_result, 3116 "Failed to enable ULV!", 3117 result = tmp_result); 3118 } 3119 3120 vega10_populate_umdpstate_clocks(hwmgr); 3121 3122 return result; 3123 } 3124 3125 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) 3126 { 3127 return sizeof(struct vega10_power_state); 3128 } 3129 3130 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, 3131 void *state, struct pp_power_state *power_state, 3132 void *pp_table, uint32_t classification_flag) 3133 { 3134 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; 3135 struct vega10_power_state *vega10_ps = 3136 cast_phw_vega10_power_state(&(power_state->hardware)); 3137 struct vega10_performance_level *performance_level; 3138 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state; 3139 ATOM_Vega10_POWERPLAYTABLE *powerplay_table = 3140 (ATOM_Vega10_POWERPLAYTABLE *)pp_table; 3141 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = 3142 (ATOM_Vega10_SOCCLK_Dependency_Table *) 3143 (((unsigned long)powerplay_table) + 3144 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); 3145 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 3146 (ATOM_Vega10_GFXCLK_Dependency_Table *) 3147 (((unsigned long)powerplay_table) + 3148 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 3149 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = 3150 (ATOM_Vega10_MCLK_Dependency_Table *) 3151 (((unsigned long)powerplay_table) + 3152 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3153 3154 3155 /* The following fields are not initialized here: 3156 * id orderedList allStatesList 3157 */ 3158 power_state->classification.ui_label = 3159 (le16_to_cpu(state_entry->usClassification) & 3160 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3161 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3162 power_state->classification.flags = classification_flag; 3163 /* NOTE: There is a classification2 flag in BIOS 3164 * that is not being used right now 3165 */ 3166 power_state->classification.temporary_state = false; 3167 power_state->classification.to_be_deleted = false; 3168 3169 power_state->validation.disallowOnDC = 3170 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3171 ATOM_Vega10_DISALLOW_ON_DC) != 0); 3172 3173 power_state->display.disableFrameModulation = false; 3174 power_state->display.limitRefreshrate = false; 3175 power_state->display.enableVariBright = 3176 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3177 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); 3178 3179 power_state->validation.supportedPowerLevels = 0; 3180 power_state->uvd_clocks.VCLK = 0; 3181 power_state->uvd_clocks.DCLK = 0; 3182 power_state->temperatures.min = 0; 3183 power_state->temperatures.max = 0; 3184 3185 performance_level = &(vega10_ps->performance_levels 3186 [vega10_ps->performance_level_count++]); 3187 3188 PP_ASSERT_WITH_CODE( 3189 (vega10_ps->performance_level_count < 3190 NUM_GFXCLK_DPM_LEVELS), 3191 "Performance levels exceeds SMC limit!", 3192 return -1); 3193 3194 PP_ASSERT_WITH_CODE( 3195 (vega10_ps->performance_level_count < 3196 hwmgr->platform_descriptor. 3197 hardwareActivityPerformanceLevels), 3198 "Performance levels exceeds Driver limit!", 3199 return -1); 3200 3201 /* Performance levels are arranged from low to high. */ 3202 performance_level->soc_clock = socclk_dep_table->entries 3203 [state_entry->ucSocClockIndexLow].ulClk; 3204 performance_level->gfx_clock = gfxclk_dep_table->entries 3205 [state_entry->ucGfxClockIndexLow].ulClk; 3206 performance_level->mem_clock = mclk_dep_table->entries 3207 [state_entry->ucMemClockIndexLow].ulMemClk; 3208 3209 performance_level = &(vega10_ps->performance_levels 3210 [vega10_ps->performance_level_count++]); 3211 performance_level->soc_clock = socclk_dep_table->entries 3212 [state_entry->ucSocClockIndexHigh].ulClk; 3213 if (gfxclk_dep_table->ucRevId == 0) { 3214 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 3215 * to level-4 due to the limited 110w-power 3216 */ 3217 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3218 performance_level->gfx_clock = 3219 gfxclk_dep_table->entries[4].ulClk; 3220 else 3221 performance_level->gfx_clock = gfxclk_dep_table->entries 3222 [state_entry->ucGfxClockIndexHigh].ulClk; 3223 } else if (gfxclk_dep_table->ucRevId == 1) { 3224 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; 3225 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3226 performance_level->gfx_clock = patom_record_V2[4].ulClk; 3227 else 3228 performance_level->gfx_clock = 3229 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; 3230 } 3231 3232 performance_level->mem_clock = mclk_dep_table->entries 3233 [state_entry->ucMemClockIndexHigh].ulMemClk; 3234 return 0; 3235 } 3236 3237 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3238 unsigned long entry_index, struct pp_power_state *state) 3239 { 3240 int result; 3241 struct vega10_power_state *vega10_ps; 3242 3243 state->hardware.magic = PhwVega10_Magic; 3244 3245 vega10_ps = cast_phw_vega10_power_state(&state->hardware); 3246 3247 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, 3248 vega10_get_pp_table_entry_callback_func); 3249 if (result) 3250 return result; 3251 3252 /* 3253 * This is the earliest time we have all the dependency table 3254 * and the VBIOS boot state 3255 */ 3256 /* set DC compatible flag if this state supports DC */ 3257 if (!state->validation.disallowOnDC) 3258 vega10_ps->dc_compatible = true; 3259 3260 vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3261 vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3262 3263 return 0; 3264 } 3265 3266 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, 3267 struct pp_hw_power_state *hw_ps) 3268 { 3269 return 0; 3270 } 3271 3272 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3273 struct pp_power_state *request_ps, 3274 const struct pp_power_state *current_ps) 3275 { 3276 struct amdgpu_device *adev = hwmgr->adev; 3277 struct vega10_power_state *vega10_ps; 3278 uint32_t sclk; 3279 uint32_t mclk; 3280 struct PP_Clocks minimum_clocks = {0}; 3281 bool disable_mclk_switching; 3282 bool disable_mclk_switching_for_frame_lock; 3283 bool disable_mclk_switching_for_vr; 3284 bool force_mclk_high; 3285 const struct phm_clock_and_voltage_limits *max_limits; 3286 uint32_t i; 3287 struct vega10_hwmgr *data = hwmgr->backend; 3288 struct phm_ppt_v2_information *table_info = 3289 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3290 int32_t count; 3291 uint32_t stable_pstate_sclk_dpm_percentage; 3292 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3293 uint32_t latency; 3294 3295 vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware); 3296 if (!vega10_ps) 3297 return -EINVAL; 3298 3299 data->battery_state = (PP_StateUILabel_Battery == 3300 request_ps->classification.ui_label); 3301 3302 if (vega10_ps->performance_level_count != 2) 3303 pr_info("VI should always have 2 performance levels"); 3304 3305 max_limits = adev->pm.ac_power ? 3306 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3307 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3308 3309 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3310 if (!adev->pm.ac_power) { 3311 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3312 if (vega10_ps->performance_levels[i].mem_clock > 3313 max_limits->mclk) 3314 vega10_ps->performance_levels[i].mem_clock = 3315 max_limits->mclk; 3316 if (vega10_ps->performance_levels[i].gfx_clock > 3317 max_limits->sclk) 3318 vega10_ps->performance_levels[i].gfx_clock = 3319 max_limits->sclk; 3320 } 3321 } 3322 3323 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ 3324 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3325 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3326 3327 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3328 stable_pstate_sclk_dpm_percentage = 3329 data->registry_data.stable_pstate_sclk_dpm_percentage; 3330 PP_ASSERT_WITH_CODE( 3331 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && 3332 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, 3333 "percent sclk value must range from 1% to 100%, setting default value", 3334 stable_pstate_sclk_dpm_percentage = 75); 3335 3336 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3337 stable_pstate_sclk = (max_limits->sclk * 3338 stable_pstate_sclk_dpm_percentage) / 100; 3339 3340 for (count = table_info->vdd_dep_on_sclk->count - 1; 3341 count >= 0; count--) { 3342 if (stable_pstate_sclk >= 3343 table_info->vdd_dep_on_sclk->entries[count].clk) { 3344 stable_pstate_sclk = 3345 table_info->vdd_dep_on_sclk->entries[count].clk; 3346 break; 3347 } 3348 } 3349 3350 if (count < 0) 3351 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3352 3353 stable_pstate_mclk = max_limits->mclk; 3354 3355 minimum_clocks.engineClock = stable_pstate_sclk; 3356 minimum_clocks.memoryClock = stable_pstate_mclk; 3357 } 3358 3359 disable_mclk_switching_for_frame_lock = 3360 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3361 disable_mclk_switching_for_vr = 3362 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3363 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3364 3365 if (hwmgr->display_config->num_display == 0) 3366 disable_mclk_switching = false; 3367 else 3368 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3369 !hwmgr->display_config->multi_monitor_in_sync) || 3370 disable_mclk_switching_for_frame_lock || 3371 disable_mclk_switching_for_vr || 3372 force_mclk_high; 3373 3374 sclk = vega10_ps->performance_levels[0].gfx_clock; 3375 mclk = vega10_ps->performance_levels[0].mem_clock; 3376 3377 if (sclk < minimum_clocks.engineClock) 3378 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3379 max_limits->sclk : minimum_clocks.engineClock; 3380 3381 if (mclk < minimum_clocks.memoryClock) 3382 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3383 max_limits->mclk : minimum_clocks.memoryClock; 3384 3385 vega10_ps->performance_levels[0].gfx_clock = sclk; 3386 vega10_ps->performance_levels[0].mem_clock = mclk; 3387 3388 if (vega10_ps->performance_levels[1].gfx_clock < 3389 vega10_ps->performance_levels[0].gfx_clock) 3390 vega10_ps->performance_levels[0].gfx_clock = 3391 vega10_ps->performance_levels[1].gfx_clock; 3392 3393 if (disable_mclk_switching) { 3394 /* Set Mclk the max of level 0 and level 1 */ 3395 if (mclk < vega10_ps->performance_levels[1].mem_clock) 3396 mclk = vega10_ps->performance_levels[1].mem_clock; 3397 3398 /* Find the lowest MCLK frequency that is within 3399 * the tolerable latency defined in DAL 3400 */ 3401 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3402 for (i = 0; i < data->mclk_latency_table.count; i++) { 3403 if ((data->mclk_latency_table.entries[i].latency <= latency) && 3404 (data->mclk_latency_table.entries[i].frequency >= 3405 vega10_ps->performance_levels[0].mem_clock) && 3406 (data->mclk_latency_table.entries[i].frequency <= 3407 vega10_ps->performance_levels[1].mem_clock)) 3408 mclk = data->mclk_latency_table.entries[i].frequency; 3409 } 3410 vega10_ps->performance_levels[0].mem_clock = mclk; 3411 } else { 3412 if (vega10_ps->performance_levels[1].mem_clock < 3413 vega10_ps->performance_levels[0].mem_clock) 3414 vega10_ps->performance_levels[0].mem_clock = 3415 vega10_ps->performance_levels[1].mem_clock; 3416 } 3417 3418 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3419 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3420 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; 3421 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; 3422 } 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 3429 { 3430 struct vega10_hwmgr *data = hwmgr->backend; 3431 const struct phm_set_power_state_input *states = 3432 (const struct phm_set_power_state_input *)input; 3433 const struct vega10_power_state *vega10_ps = 3434 cast_const_phw_vega10_power_state(states->pnew_state); 3435 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 3436 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 3437 uint32_t sclk, mclk; 3438 uint32_t i; 3439 3440 if (vega10_ps == NULL) 3441 return -EINVAL; 3442 sclk = vega10_ps->performance_levels 3443 [vega10_ps->performance_level_count - 1].gfx_clock; 3444 mclk = vega10_ps->performance_levels 3445 [vega10_ps->performance_level_count - 1].mem_clock; 3446 3447 for (i = 0; i < sclk_table->count; i++) { 3448 if (sclk == sclk_table->dpm_levels[i].value) 3449 break; 3450 } 3451 3452 if (i >= sclk_table->count) { 3453 if (sclk > sclk_table->dpm_levels[i-1].value) { 3454 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3455 sclk_table->dpm_levels[i-1].value = sclk; 3456 } 3457 } 3458 3459 for (i = 0; i < mclk_table->count; i++) { 3460 if (mclk == mclk_table->dpm_levels[i].value) 3461 break; 3462 } 3463 3464 if (i >= mclk_table->count) { 3465 if (mclk > mclk_table->dpm_levels[i-1].value) { 3466 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3467 mclk_table->dpm_levels[i-1].value = mclk; 3468 } 3469 } 3470 3471 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3472 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; 3473 3474 return 0; 3475 } 3476 3477 static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 3478 struct pp_hwmgr *hwmgr, const void *input) 3479 { 3480 int result = 0; 3481 struct vega10_hwmgr *data = hwmgr->backend; 3482 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3483 struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; 3484 struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; 3485 int count; 3486 3487 if (!data->need_update_dpm_table) 3488 return 0; 3489 3490 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 3491 for (count = 0; count < dpm_table->gfx_table.count; count++) 3492 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3493 } 3494 3495 odn_clk_table = &odn_table->vdd_dep_on_mclk; 3496 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 3497 for (count = 0; count < dpm_table->mem_table.count; count++) 3498 dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3499 } 3500 3501 if (data->need_update_dpm_table & 3502 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { 3503 result = vega10_populate_all_graphic_levels(hwmgr); 3504 PP_ASSERT_WITH_CODE((0 == result), 3505 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 3506 return result); 3507 } 3508 3509 if (data->need_update_dpm_table & 3510 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3511 result = vega10_populate_all_memory_levels(hwmgr); 3512 PP_ASSERT_WITH_CODE((0 == result), 3513 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 3514 return result); 3515 } 3516 3517 vega10_populate_vddc_soc_levels(hwmgr); 3518 3519 return result; 3520 } 3521 3522 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 3523 struct vega10_single_dpm_table *dpm_table, 3524 uint32_t low_limit, uint32_t high_limit) 3525 { 3526 uint32_t i; 3527 3528 for (i = 0; i < dpm_table->count; i++) { 3529 if ((dpm_table->dpm_levels[i].value < low_limit) || 3530 (dpm_table->dpm_levels[i].value > high_limit)) 3531 dpm_table->dpm_levels[i].enabled = false; 3532 else 3533 dpm_table->dpm_levels[i].enabled = true; 3534 } 3535 return 0; 3536 } 3537 3538 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, 3539 struct vega10_single_dpm_table *dpm_table, 3540 uint32_t low_limit, uint32_t high_limit, 3541 uint32_t disable_dpm_mask) 3542 { 3543 uint32_t i; 3544 3545 for (i = 0; i < dpm_table->count; i++) { 3546 if ((dpm_table->dpm_levels[i].value < low_limit) || 3547 (dpm_table->dpm_levels[i].value > high_limit)) 3548 dpm_table->dpm_levels[i].enabled = false; 3549 else if (!((1 << i) & disable_dpm_mask)) 3550 dpm_table->dpm_levels[i].enabled = false; 3551 else 3552 dpm_table->dpm_levels[i].enabled = true; 3553 } 3554 return 0; 3555 } 3556 3557 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, 3558 const struct vega10_power_state *vega10_ps) 3559 { 3560 struct vega10_hwmgr *data = hwmgr->backend; 3561 uint32_t high_limit_count; 3562 3563 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), 3564 "power state did not have any performance level", 3565 return -1); 3566 3567 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; 3568 3569 vega10_trim_single_dpm_states(hwmgr, 3570 &(data->dpm_table.soc_table), 3571 vega10_ps->performance_levels[0].soc_clock, 3572 vega10_ps->performance_levels[high_limit_count].soc_clock); 3573 3574 vega10_trim_single_dpm_states_with_mask(hwmgr, 3575 &(data->dpm_table.gfx_table), 3576 vega10_ps->performance_levels[0].gfx_clock, 3577 vega10_ps->performance_levels[high_limit_count].gfx_clock, 3578 data->disable_dpm_mask); 3579 3580 vega10_trim_single_dpm_states(hwmgr, 3581 &(data->dpm_table.mem_table), 3582 vega10_ps->performance_levels[0].mem_clock, 3583 vega10_ps->performance_levels[high_limit_count].mem_clock); 3584 3585 return 0; 3586 } 3587 3588 static uint32_t vega10_find_lowest_dpm_level( 3589 struct vega10_single_dpm_table *table) 3590 { 3591 uint32_t i; 3592 3593 for (i = 0; i < table->count; i++) { 3594 if (table->dpm_levels[i].enabled) 3595 break; 3596 } 3597 3598 return i; 3599 } 3600 3601 static uint32_t vega10_find_highest_dpm_level( 3602 struct vega10_single_dpm_table *table) 3603 { 3604 uint32_t i = 0; 3605 3606 if (table->count <= MAX_REGULAR_DPM_NUMBER) { 3607 for (i = table->count; i > 0; i--) { 3608 if (table->dpm_levels[i - 1].enabled) 3609 return i - 1; 3610 } 3611 } else { 3612 pr_info("DPM Table Has Too Many Entries!"); 3613 return MAX_REGULAR_DPM_NUMBER - 1; 3614 } 3615 3616 return i; 3617 } 3618 3619 static void vega10_apply_dal_minimum_voltage_request( 3620 struct pp_hwmgr *hwmgr) 3621 { 3622 return; 3623 } 3624 3625 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) 3626 { 3627 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; 3628 struct phm_ppt_v2_information *table_info = 3629 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3630 3631 vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; 3632 3633 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; 3634 } 3635 3636 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) 3637 { 3638 struct vega10_hwmgr *data = hwmgr->backend; 3639 uint32_t socclk_idx; 3640 3641 vega10_apply_dal_minimum_voltage_request(hwmgr); 3642 3643 if (!data->registry_data.sclk_dpm_key_disabled) { 3644 if (data->smc_state_table.gfx_boot_level != 3645 data->dpm_table.gfx_table.dpm_state.soft_min_level) { 3646 smum_send_msg_to_smc_with_parameter(hwmgr, 3647 PPSMC_MSG_SetSoftMinGfxclkByIndex, 3648 data->smc_state_table.gfx_boot_level, 3649 NULL); 3650 3651 data->dpm_table.gfx_table.dpm_state.soft_min_level = 3652 data->smc_state_table.gfx_boot_level; 3653 } 3654 } 3655 3656 if (!data->registry_data.mclk_dpm_key_disabled) { 3657 if (data->smc_state_table.mem_boot_level != 3658 data->dpm_table.mem_table.dpm_state.soft_min_level) { 3659 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) 3660 && hwmgr->not_vf) { 3661 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); 3662 smum_send_msg_to_smc_with_parameter(hwmgr, 3663 PPSMC_MSG_SetSoftMinSocclkByIndex, 3664 socclk_idx, 3665 NULL); 3666 } else { 3667 smum_send_msg_to_smc_with_parameter(hwmgr, 3668 PPSMC_MSG_SetSoftMinUclkByIndex, 3669 data->smc_state_table.mem_boot_level, 3670 NULL); 3671 } 3672 data->dpm_table.mem_table.dpm_state.soft_min_level = 3673 data->smc_state_table.mem_boot_level; 3674 } 3675 } 3676 3677 if (!hwmgr->not_vf) 3678 return 0; 3679 3680 if (!data->registry_data.socclk_dpm_key_disabled) { 3681 if (data->smc_state_table.soc_boot_level != 3682 data->dpm_table.soc_table.dpm_state.soft_min_level) { 3683 smum_send_msg_to_smc_with_parameter(hwmgr, 3684 PPSMC_MSG_SetSoftMinSocclkByIndex, 3685 data->smc_state_table.soc_boot_level, 3686 NULL); 3687 data->dpm_table.soc_table.dpm_state.soft_min_level = 3688 data->smc_state_table.soc_boot_level; 3689 } 3690 } 3691 3692 return 0; 3693 } 3694 3695 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 3696 { 3697 struct vega10_hwmgr *data = hwmgr->backend; 3698 3699 vega10_apply_dal_minimum_voltage_request(hwmgr); 3700 3701 if (!data->registry_data.sclk_dpm_key_disabled) { 3702 if (data->smc_state_table.gfx_max_level != 3703 data->dpm_table.gfx_table.dpm_state.soft_max_level) { 3704 smum_send_msg_to_smc_with_parameter(hwmgr, 3705 PPSMC_MSG_SetSoftMaxGfxclkByIndex, 3706 data->smc_state_table.gfx_max_level, 3707 NULL); 3708 data->dpm_table.gfx_table.dpm_state.soft_max_level = 3709 data->smc_state_table.gfx_max_level; 3710 } 3711 } 3712 3713 if (!data->registry_data.mclk_dpm_key_disabled) { 3714 if (data->smc_state_table.mem_max_level != 3715 data->dpm_table.mem_table.dpm_state.soft_max_level) { 3716 smum_send_msg_to_smc_with_parameter(hwmgr, 3717 PPSMC_MSG_SetSoftMaxUclkByIndex, 3718 data->smc_state_table.mem_max_level, 3719 NULL); 3720 data->dpm_table.mem_table.dpm_state.soft_max_level = 3721 data->smc_state_table.mem_max_level; 3722 } 3723 } 3724 3725 if (!hwmgr->not_vf) 3726 return 0; 3727 3728 if (!data->registry_data.socclk_dpm_key_disabled) { 3729 if (data->smc_state_table.soc_max_level != 3730 data->dpm_table.soc_table.dpm_state.soft_max_level) { 3731 smum_send_msg_to_smc_with_parameter(hwmgr, 3732 PPSMC_MSG_SetSoftMaxSocclkByIndex, 3733 data->smc_state_table.soc_max_level, 3734 NULL); 3735 data->dpm_table.soc_table.dpm_state.soft_max_level = 3736 data->smc_state_table.soc_max_level; 3737 } 3738 } 3739 3740 return 0; 3741 } 3742 3743 static int vega10_generate_dpm_level_enable_mask( 3744 struct pp_hwmgr *hwmgr, const void *input) 3745 { 3746 struct vega10_hwmgr *data = hwmgr->backend; 3747 const struct phm_set_power_state_input *states = 3748 (const struct phm_set_power_state_input *)input; 3749 const struct vega10_power_state *vega10_ps = 3750 cast_const_phw_vega10_power_state(states->pnew_state); 3751 int i; 3752 3753 if (vega10_ps == NULL) 3754 return -EINVAL; 3755 3756 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), 3757 "Attempt to Trim DPM States Failed!", 3758 return -1); 3759 3760 data->smc_state_table.gfx_boot_level = 3761 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 3762 data->smc_state_table.gfx_max_level = 3763 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 3764 data->smc_state_table.mem_boot_level = 3765 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 3766 data->smc_state_table.mem_max_level = 3767 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 3768 data->smc_state_table.soc_boot_level = 3769 vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 3770 data->smc_state_table.soc_max_level = 3771 vega10_find_highest_dpm_level(&(data->dpm_table.soc_table)); 3772 3773 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 3774 "Attempt to upload DPM Bootup Levels Failed!", 3775 return -1); 3776 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 3777 "Attempt to upload DPM Max Levels Failed!", 3778 return -1); 3779 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) 3780 data->dpm_table.gfx_table.dpm_levels[i].enabled = true; 3781 3782 3783 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) 3784 data->dpm_table.mem_table.dpm_levels[i].enabled = true; 3785 3786 for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) 3787 data->dpm_table.soc_table.dpm_levels[i].enabled = true; 3788 3789 return 0; 3790 } 3791 3792 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 3793 { 3794 struct vega10_hwmgr *data = hwmgr->backend; 3795 3796 if (data->smu_features[GNLD_DPM_VCE].supported) { 3797 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3798 enable, 3799 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 3800 "Attempt to Enable/Disable DPM VCE Failed!", 3801 return -1); 3802 data->smu_features[GNLD_DPM_VCE].enabled = enable; 3803 } 3804 3805 return 0; 3806 } 3807 3808 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 3809 { 3810 struct vega10_hwmgr *data = hwmgr->backend; 3811 uint32_t low_sclk_interrupt_threshold = 0; 3812 3813 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && 3814 (data->low_sclk_interrupt_threshold != 0)) { 3815 low_sclk_interrupt_threshold = 3816 data->low_sclk_interrupt_threshold; 3817 3818 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = 3819 cpu_to_le32(low_sclk_interrupt_threshold); 3820 3821 /* This message will also enable SmcToHost Interrupt */ 3822 smum_send_msg_to_smc_with_parameter(hwmgr, 3823 PPSMC_MSG_SetLowGfxclkInterruptThreshold, 3824 (uint32_t)low_sclk_interrupt_threshold, 3825 NULL); 3826 } 3827 3828 return 0; 3829 } 3830 3831 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, 3832 const void *input) 3833 { 3834 int tmp_result, result = 0; 3835 struct vega10_hwmgr *data = hwmgr->backend; 3836 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 3837 3838 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 3839 PP_ASSERT_WITH_CODE(!tmp_result, 3840 "Failed to find DPM states clocks in DPM table!", 3841 result = tmp_result); 3842 3843 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 3844 PP_ASSERT_WITH_CODE(!tmp_result, 3845 "Failed to populate and upload SCLK MCLK DPM levels!", 3846 result = tmp_result); 3847 3848 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); 3849 PP_ASSERT_WITH_CODE(!tmp_result, 3850 "Failed to generate DPM level enabled mask!", 3851 result = tmp_result); 3852 3853 tmp_result = vega10_update_sclk_threshold(hwmgr); 3854 PP_ASSERT_WITH_CODE(!tmp_result, 3855 "Failed to update SCLK threshold!", 3856 result = tmp_result); 3857 3858 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 3859 PP_ASSERT_WITH_CODE(!result, 3860 "Failed to upload PPtable!", return result); 3861 3862 /* 3863 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 3864 * That effectively disables AVFS feature. 3865 */ 3866 if(hwmgr->hardcode_pp_table != NULL) 3867 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 3868 3869 vega10_update_avfs(hwmgr); 3870 3871 /* 3872 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC. 3873 * That will help to keep AVFS disabled. 3874 */ 3875 data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 3876 3877 return 0; 3878 } 3879 3880 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3881 { 3882 struct pp_power_state *ps; 3883 struct vega10_power_state *vega10_ps; 3884 3885 if (hwmgr == NULL) 3886 return -EINVAL; 3887 3888 ps = hwmgr->request_ps; 3889 3890 if (ps == NULL) 3891 return -EINVAL; 3892 3893 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3894 3895 if (low) 3896 return vega10_ps->performance_levels[0].gfx_clock; 3897 else 3898 return vega10_ps->performance_levels 3899 [vega10_ps->performance_level_count - 1].gfx_clock; 3900 } 3901 3902 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3903 { 3904 struct pp_power_state *ps; 3905 struct vega10_power_state *vega10_ps; 3906 3907 if (hwmgr == NULL) 3908 return -EINVAL; 3909 3910 ps = hwmgr->request_ps; 3911 3912 if (ps == NULL) 3913 return -EINVAL; 3914 3915 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3916 3917 if (low) 3918 return vega10_ps->performance_levels[0].mem_clock; 3919 else 3920 return vega10_ps->performance_levels 3921 [vega10_ps->performance_level_count-1].mem_clock; 3922 } 3923 3924 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, 3925 uint32_t *query) 3926 { 3927 uint32_t value; 3928 int ret; 3929 3930 if (!query) 3931 return -EINVAL; 3932 3933 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); 3934 if (ret) 3935 return ret; 3936 3937 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ 3938 *query = value << 8; 3939 3940 return 0; 3941 } 3942 3943 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3944 void *value, int *size) 3945 { 3946 struct amdgpu_device *adev = hwmgr->adev; 3947 uint32_t sclk_mhz, mclk_idx, activity_percent = 0; 3948 struct vega10_hwmgr *data = hwmgr->backend; 3949 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3950 int ret = 0; 3951 uint32_t val_vid; 3952 3953 switch (idx) { 3954 case AMDGPU_PP_SENSOR_GFX_SCLK: 3955 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); 3956 if (ret) 3957 break; 3958 3959 *((uint32_t *)value) = sclk_mhz * 100; 3960 break; 3961 case AMDGPU_PP_SENSOR_GFX_MCLK: 3962 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); 3963 if (ret) 3964 break; 3965 if (mclk_idx < dpm_table->mem_table.count) { 3966 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; 3967 *size = 4; 3968 } else { 3969 ret = -EINVAL; 3970 } 3971 break; 3972 case AMDGPU_PP_SENSOR_GPU_LOAD: 3973 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, 3974 &activity_percent); 3975 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3976 *size = 4; 3977 break; 3978 case AMDGPU_PP_SENSOR_GPU_TEMP: 3979 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); 3980 *size = 4; 3981 break; 3982 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 3983 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); 3984 *((uint32_t *)value) = *((uint32_t *)value) * 3985 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3986 *size = 4; 3987 break; 3988 case AMDGPU_PP_SENSOR_MEM_TEMP: 3989 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); 3990 *((uint32_t *)value) = *((uint32_t *)value) * 3991 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3992 *size = 4; 3993 break; 3994 case AMDGPU_PP_SENSOR_UVD_POWER: 3995 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 3996 *size = 4; 3997 break; 3998 case AMDGPU_PP_SENSOR_VCE_POWER: 3999 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 4000 *size = 4; 4001 break; 4002 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 4003 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); 4004 break; 4005 case AMDGPU_PP_SENSOR_VDDGFX: 4006 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & 4007 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> 4008 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; 4009 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); 4010 return 0; 4011 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 4012 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); 4013 if (!ret) 4014 *size = 8; 4015 break; 4016 default: 4017 ret = -EOPNOTSUPP; 4018 break; 4019 } 4020 4021 return ret; 4022 } 4023 4024 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, 4025 bool has_disp) 4026 { 4027 smum_send_msg_to_smc_with_parameter(hwmgr, 4028 PPSMC_MSG_SetUclkFastSwitch, 4029 has_disp ? 1 : 0, 4030 NULL); 4031 } 4032 4033 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 4034 struct pp_display_clock_request *clock_req) 4035 { 4036 int result = 0; 4037 enum amd_pp_clock_type clk_type = clock_req->clock_type; 4038 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 4039 DSPCLK_e clk_select = 0; 4040 uint32_t clk_request = 0; 4041 4042 switch (clk_type) { 4043 case amd_pp_dcef_clock: 4044 clk_select = DSPCLK_DCEFCLK; 4045 break; 4046 case amd_pp_disp_clock: 4047 clk_select = DSPCLK_DISPCLK; 4048 break; 4049 case amd_pp_pixel_clock: 4050 clk_select = DSPCLK_PIXCLK; 4051 break; 4052 case amd_pp_phy_clock: 4053 clk_select = DSPCLK_PHYCLK; 4054 break; 4055 default: 4056 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 4057 result = -1; 4058 break; 4059 } 4060 4061 if (!result) { 4062 clk_request = (clk_freq << 16) | clk_select; 4063 smum_send_msg_to_smc_with_parameter(hwmgr, 4064 PPSMC_MSG_RequestDisplayClockByFreq, 4065 clk_request, 4066 NULL); 4067 } 4068 4069 return result; 4070 } 4071 4072 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, 4073 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, 4074 uint32_t frequency) 4075 { 4076 uint8_t count; 4077 uint8_t i; 4078 4079 if (mclk_table == NULL || mclk_table->count == 0) 4080 return 0; 4081 4082 count = (uint8_t)(mclk_table->count); 4083 4084 for(i = 0; i < count; i++) { 4085 if(mclk_table->entries[i].clk >= frequency) 4086 return i; 4087 } 4088 4089 return i-1; 4090 } 4091 4092 static int vega10_notify_smc_display_config_after_ps_adjustment( 4093 struct pp_hwmgr *hwmgr) 4094 { 4095 struct vega10_hwmgr *data = hwmgr->backend; 4096 struct vega10_single_dpm_table *dpm_table = 4097 &data->dpm_table.dcef_table; 4098 struct phm_ppt_v2_information *table_info = 4099 (struct phm_ppt_v2_information *)hwmgr->pptable; 4100 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; 4101 uint32_t idx; 4102 struct PP_Clocks min_clocks = {0}; 4103 uint32_t i; 4104 struct pp_display_clock_request clock_req; 4105 4106 if ((hwmgr->display_config->num_display > 1) && 4107 !hwmgr->display_config->multi_monitor_in_sync && 4108 !hwmgr->display_config->nb_pstate_switch_disable) 4109 vega10_notify_smc_display_change(hwmgr, false); 4110 else 4111 vega10_notify_smc_display_change(hwmgr, true); 4112 4113 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 4114 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 4115 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 4116 4117 for (i = 0; i < dpm_table->count; i++) { 4118 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) 4119 break; 4120 } 4121 4122 if (i < dpm_table->count) { 4123 clock_req.clock_type = amd_pp_dcef_clock; 4124 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; 4125 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 4126 smum_send_msg_to_smc_with_parameter( 4127 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 4128 min_clocks.dcefClockInSR / 100, 4129 NULL); 4130 } else { 4131 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 4132 } 4133 } else { 4134 pr_debug("Cannot find requested DCEFCLK!"); 4135 } 4136 4137 if (min_clocks.memoryClock != 0) { 4138 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 4139 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, 4140 NULL); 4141 data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 4142 } 4143 4144 return 0; 4145 } 4146 4147 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) 4148 { 4149 struct vega10_hwmgr *data = hwmgr->backend; 4150 4151 data->smc_state_table.gfx_boot_level = 4152 data->smc_state_table.gfx_max_level = 4153 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4154 data->smc_state_table.mem_boot_level = 4155 data->smc_state_table.mem_max_level = 4156 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4157 4158 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4159 "Failed to upload boot level to highest!", 4160 return -1); 4161 4162 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4163 "Failed to upload dpm max level to highest!", 4164 return -1); 4165 4166 return 0; 4167 } 4168 4169 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) 4170 { 4171 struct vega10_hwmgr *data = hwmgr->backend; 4172 4173 data->smc_state_table.gfx_boot_level = 4174 data->smc_state_table.gfx_max_level = 4175 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4176 data->smc_state_table.mem_boot_level = 4177 data->smc_state_table.mem_max_level = 4178 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4179 4180 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4181 "Failed to upload boot level to highest!", 4182 return -1); 4183 4184 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4185 "Failed to upload dpm max level to highest!", 4186 return -1); 4187 4188 return 0; 4189 4190 } 4191 4192 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 4193 { 4194 struct vega10_hwmgr *data = hwmgr->backend; 4195 4196 data->smc_state_table.gfx_boot_level = 4197 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4198 data->smc_state_table.gfx_max_level = 4199 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4200 data->smc_state_table.mem_boot_level = 4201 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4202 data->smc_state_table.mem_max_level = 4203 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4204 4205 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4206 "Failed to upload DPM Bootup Levels!", 4207 return -1); 4208 4209 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4210 "Failed to upload DPM Max Levels!", 4211 return -1); 4212 return 0; 4213 } 4214 4215 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 4216 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 4217 { 4218 struct phm_ppt_v2_information *table_info = 4219 (struct phm_ppt_v2_information *)(hwmgr->pptable); 4220 4221 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 4222 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL && 4223 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 4224 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4225 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; 4226 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; 4227 } 4228 4229 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 4230 *sclk_mask = 0; 4231 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 4232 *mclk_mask = 0; 4233 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 4234 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 4235 * to level-4 due to the limited power 4236 */ 4237 if (hwmgr->pp_one_vf) 4238 *sclk_mask = 4; 4239 else 4240 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 4241 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; 4242 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; 4243 } 4244 4245 return 0; 4246 } 4247 4248 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 4249 { 4250 if (!hwmgr->not_vf) 4251 return; 4252 4253 switch (mode) { 4254 case AMD_FAN_CTRL_NONE: 4255 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 4256 break; 4257 case AMD_FAN_CTRL_MANUAL: 4258 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4259 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 4260 break; 4261 case AMD_FAN_CTRL_AUTO: 4262 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4263 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 4264 break; 4265 default: 4266 break; 4267 } 4268 } 4269 4270 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, 4271 enum pp_clock_type type, uint32_t mask) 4272 { 4273 struct vega10_hwmgr *data = hwmgr->backend; 4274 4275 switch (type) { 4276 case PP_SCLK: 4277 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; 4278 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; 4279 4280 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4281 "Failed to upload boot level to lowest!", 4282 return -EINVAL); 4283 4284 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4285 "Failed to upload dpm max level to highest!", 4286 return -EINVAL); 4287 break; 4288 4289 case PP_MCLK: 4290 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; 4291 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; 4292 4293 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4294 "Failed to upload boot level to lowest!", 4295 return -EINVAL); 4296 4297 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4298 "Failed to upload dpm max level to highest!", 4299 return -EINVAL); 4300 4301 break; 4302 4303 case PP_SOCCLK: 4304 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; 4305 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; 4306 4307 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4308 "Failed to upload boot level to lowest!", 4309 return -EINVAL); 4310 4311 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4312 "Failed to upload dpm max level to highest!", 4313 return -EINVAL); 4314 4315 break; 4316 4317 case PP_DCEFCLK: 4318 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); 4319 break; 4320 4321 case PP_PCIE: 4322 default: 4323 break; 4324 } 4325 4326 return 0; 4327 } 4328 4329 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 4330 enum amd_dpm_forced_level level) 4331 { 4332 int ret = 0; 4333 uint32_t sclk_mask = 0; 4334 uint32_t mclk_mask = 0; 4335 uint32_t soc_mask = 0; 4336 4337 switch (level) { 4338 case AMD_DPM_FORCED_LEVEL_HIGH: 4339 ret = vega10_force_dpm_highest(hwmgr); 4340 break; 4341 case AMD_DPM_FORCED_LEVEL_LOW: 4342 ret = vega10_force_dpm_lowest(hwmgr); 4343 break; 4344 case AMD_DPM_FORCED_LEVEL_AUTO: 4345 ret = vega10_unforce_dpm_levels(hwmgr); 4346 break; 4347 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 4348 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 4349 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 4350 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 4351 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4352 if (ret) 4353 return ret; 4354 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 4355 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 4356 break; 4357 case AMD_DPM_FORCED_LEVEL_MANUAL: 4358 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 4359 default: 4360 break; 4361 } 4362 4363 if (!hwmgr->not_vf) 4364 return ret; 4365 4366 if (!ret) { 4367 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4368 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); 4369 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4370 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); 4371 } 4372 4373 return ret; 4374 } 4375 4376 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) 4377 { 4378 struct vega10_hwmgr *data = hwmgr->backend; 4379 4380 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 4381 return AMD_FAN_CTRL_MANUAL; 4382 else 4383 return AMD_FAN_CTRL_AUTO; 4384 } 4385 4386 static void vega10_get_sclks(struct pp_hwmgr *hwmgr, 4387 struct pp_clock_levels_with_latency *clocks) 4388 { 4389 struct phm_ppt_v2_information *table_info = 4390 (struct phm_ppt_v2_information *)hwmgr->pptable; 4391 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4392 table_info->vdd_dep_on_sclk; 4393 uint32_t i; 4394 4395 clocks->num_levels = 0; 4396 for (i = 0; i < dep_table->count; i++) { 4397 if (dep_table->entries[i].clk) { 4398 clocks->data[clocks->num_levels].clocks_in_khz = 4399 dep_table->entries[i].clk * 10; 4400 clocks->num_levels++; 4401 } 4402 } 4403 4404 } 4405 4406 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, 4407 struct pp_clock_levels_with_latency *clocks) 4408 { 4409 struct phm_ppt_v2_information *table_info = 4410 (struct phm_ppt_v2_information *)hwmgr->pptable; 4411 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4412 table_info->vdd_dep_on_mclk; 4413 struct vega10_hwmgr *data = hwmgr->backend; 4414 uint32_t j = 0; 4415 uint32_t i; 4416 4417 for (i = 0; i < dep_table->count; i++) { 4418 if (dep_table->entries[i].clk) { 4419 4420 clocks->data[j].clocks_in_khz = 4421 dep_table->entries[i].clk * 10; 4422 data->mclk_latency_table.entries[j].frequency = 4423 dep_table->entries[i].clk; 4424 clocks->data[j].latency_in_us = 4425 data->mclk_latency_table.entries[j].latency = 25; 4426 j++; 4427 } 4428 } 4429 clocks->num_levels = data->mclk_latency_table.count = j; 4430 } 4431 4432 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, 4433 struct pp_clock_levels_with_latency *clocks) 4434 { 4435 struct phm_ppt_v2_information *table_info = 4436 (struct phm_ppt_v2_information *)hwmgr->pptable; 4437 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4438 table_info->vdd_dep_on_dcefclk; 4439 uint32_t i; 4440 4441 for (i = 0; i < dep_table->count; i++) { 4442 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4443 clocks->data[i].latency_in_us = 0; 4444 clocks->num_levels++; 4445 } 4446 } 4447 4448 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, 4449 struct pp_clock_levels_with_latency *clocks) 4450 { 4451 struct phm_ppt_v2_information *table_info = 4452 (struct phm_ppt_v2_information *)hwmgr->pptable; 4453 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4454 table_info->vdd_dep_on_socclk; 4455 uint32_t i; 4456 4457 for (i = 0; i < dep_table->count; i++) { 4458 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4459 clocks->data[i].latency_in_us = 0; 4460 clocks->num_levels++; 4461 } 4462 } 4463 4464 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 4465 enum amd_pp_clock_type type, 4466 struct pp_clock_levels_with_latency *clocks) 4467 { 4468 switch (type) { 4469 case amd_pp_sys_clock: 4470 vega10_get_sclks(hwmgr, clocks); 4471 break; 4472 case amd_pp_mem_clock: 4473 vega10_get_memclocks(hwmgr, clocks); 4474 break; 4475 case amd_pp_dcef_clock: 4476 vega10_get_dcefclocks(hwmgr, clocks); 4477 break; 4478 case amd_pp_soc_clock: 4479 vega10_get_socclocks(hwmgr, clocks); 4480 break; 4481 default: 4482 return -1; 4483 } 4484 4485 return 0; 4486 } 4487 4488 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 4489 enum amd_pp_clock_type type, 4490 struct pp_clock_levels_with_voltage *clocks) 4491 { 4492 struct phm_ppt_v2_information *table_info = 4493 (struct phm_ppt_v2_information *)hwmgr->pptable; 4494 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 4495 uint32_t i; 4496 4497 switch (type) { 4498 case amd_pp_mem_clock: 4499 dep_table = table_info->vdd_dep_on_mclk; 4500 break; 4501 case amd_pp_dcef_clock: 4502 dep_table = table_info->vdd_dep_on_dcefclk; 4503 break; 4504 case amd_pp_disp_clock: 4505 dep_table = table_info->vdd_dep_on_dispclk; 4506 break; 4507 case amd_pp_pixel_clock: 4508 dep_table = table_info->vdd_dep_on_pixclk; 4509 break; 4510 case amd_pp_phy_clock: 4511 dep_table = table_info->vdd_dep_on_phyclk; 4512 break; 4513 default: 4514 return -1; 4515 } 4516 4517 for (i = 0; i < dep_table->count; i++) { 4518 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4519 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> 4520 entries[dep_table->entries[i].vddInd].us_vdd); 4521 clocks->num_levels++; 4522 } 4523 4524 if (i < dep_table->count) 4525 return -1; 4526 4527 return 0; 4528 } 4529 4530 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 4531 void *clock_range) 4532 { 4533 struct vega10_hwmgr *data = hwmgr->backend; 4534 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; 4535 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 4536 4537 if (!data->registry_data.disable_water_mark) { 4538 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 4539 data->water_marks_bitmap = WaterMarksExist; 4540 } 4541 4542 return 0; 4543 } 4544 4545 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 4546 { 4547 static const char *ppfeature_name[] = { 4548 "DPM_PREFETCHER", 4549 "GFXCLK_DPM", 4550 "UCLK_DPM", 4551 "SOCCLK_DPM", 4552 "UVD_DPM", 4553 "VCE_DPM", 4554 "ULV", 4555 "MP0CLK_DPM", 4556 "LINK_DPM", 4557 "DCEFCLK_DPM", 4558 "AVFS", 4559 "GFXCLK_DS", 4560 "SOCCLK_DS", 4561 "LCLK_DS", 4562 "PPT", 4563 "TDC", 4564 "THERMAL", 4565 "GFX_PER_CU_CG", 4566 "RM", 4567 "DCEFCLK_DS", 4568 "ACDC", 4569 "VR0HOT", 4570 "VR1HOT", 4571 "FW_CTF", 4572 "LED_DISPLAY", 4573 "FAN_CONTROL", 4574 "FAST_PPT", 4575 "DIDT", 4576 "ACG", 4577 "PCC_LIMIT"}; 4578 static const char *output_title[] = { 4579 "FEATURES", 4580 "BITMASK", 4581 "ENABLEMENT"}; 4582 uint64_t features_enabled; 4583 int i; 4584 int ret = 0; 4585 int size = 0; 4586 4587 phm_get_sysfs_buf(&buf, &size); 4588 4589 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4590 PP_ASSERT_WITH_CODE(!ret, 4591 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 4592 return ret); 4593 4594 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 4595 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 4596 output_title[0], 4597 output_title[1], 4598 output_title[2]); 4599 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 4600 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 4601 ppfeature_name[i], 4602 1ULL << i, 4603 (features_enabled & (1ULL << i)) ? "Y" : "N"); 4604 } 4605 4606 return size; 4607 } 4608 4609 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 4610 { 4611 uint64_t features_enabled; 4612 uint64_t features_to_enable; 4613 uint64_t features_to_disable; 4614 int ret = 0; 4615 4616 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 4617 return -EINVAL; 4618 4619 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4620 if (ret) 4621 return ret; 4622 4623 features_to_disable = 4624 features_enabled & ~new_ppfeature_masks; 4625 features_to_enable = 4626 ~features_enabled & new_ppfeature_masks; 4627 4628 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 4629 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 4630 4631 if (features_to_disable) { 4632 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); 4633 if (ret) 4634 return ret; 4635 } 4636 4637 if (features_to_enable) { 4638 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); 4639 if (ret) 4640 return ret; 4641 } 4642 4643 return 0; 4644 } 4645 4646 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 4647 { 4648 struct amdgpu_device *adev = hwmgr->adev; 4649 4650 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 4651 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 4652 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 4653 } 4654 4655 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 4656 { 4657 struct amdgpu_device *adev = hwmgr->adev; 4658 4659 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 4660 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 4661 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 4662 } 4663 4664 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, 4665 enum pp_clock_type type, char *buf, int *offset) 4666 { 4667 struct vega10_hwmgr *data = hwmgr->backend; 4668 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4669 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4670 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4671 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4672 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4673 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4674 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4675 4676 uint32_t i, now, count = 0; 4677 int ret = 0; 4678 4679 switch (type) { 4680 case PP_SCLK: 4681 if (data->registry_data.sclk_dpm_key_disabled) 4682 return -EOPNOTSUPP; 4683 4684 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4685 if (unlikely(ret != 0)) 4686 return ret; 4687 4688 if (hwmgr->pp_one_vf && 4689 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4690 count = 5; 4691 else 4692 count = sclk_table->count; 4693 for (i = 0; i < count; i++) 4694 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4695 i, sclk_table->dpm_levels[i].value / 100, 4696 (i == now) ? "*" : ""); 4697 break; 4698 case PP_MCLK: 4699 if (data->registry_data.mclk_dpm_key_disabled) 4700 return -EOPNOTSUPP; 4701 4702 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4703 if (unlikely(ret != 0)) 4704 return ret; 4705 4706 for (i = 0; i < mclk_table->count; i++) 4707 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4708 i, mclk_table->dpm_levels[i].value / 100, 4709 (i == now) ? "*" : ""); 4710 break; 4711 case PP_SOCCLK: 4712 if (data->registry_data.socclk_dpm_key_disabled) 4713 return -EOPNOTSUPP; 4714 4715 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4716 if (unlikely(ret != 0)) 4717 return ret; 4718 4719 for (i = 0; i < soc_table->count; i++) 4720 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4721 i, soc_table->dpm_levels[i].value / 100, 4722 (i == now) ? "*" : ""); 4723 break; 4724 case PP_DCEFCLK: 4725 if (data->registry_data.dcefclk_dpm_key_disabled) 4726 return -EOPNOTSUPP; 4727 4728 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4729 PPSMC_MSG_GetClockFreqMHz, 4730 CLK_DCEFCLK, &now); 4731 if (unlikely(ret != 0)) 4732 return ret; 4733 4734 for (i = 0; i < dcef_table->count; i++) 4735 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4736 i, dcef_table->dpm_levels[i].value / 100, 4737 (dcef_table->dpm_levels[i].value / 100 == now) ? 4738 "*" : ""); 4739 break; 4740 case PP_PCIE: 4741 current_gen_speed = 4742 vega10_get_current_pcie_link_speed_level(hwmgr); 4743 current_lane_width = 4744 vega10_get_current_pcie_link_width_level(hwmgr); 4745 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4746 gen_speed = pptable->PcieGenSpeed[i]; 4747 lane_width = pptable->PcieLaneCount[i]; 4748 4749 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i, 4750 (gen_speed == 0) ? "2.5GT/s," : 4751 (gen_speed == 1) ? "5.0GT/s," : 4752 (gen_speed == 2) ? "8.0GT/s," : 4753 (gen_speed == 3) ? "16.0GT/s," : "", 4754 (lane_width == 1) ? "x1" : 4755 (lane_width == 2) ? "x2" : 4756 (lane_width == 3) ? "x4" : 4757 (lane_width == 4) ? "x8" : 4758 (lane_width == 5) ? "x12" : 4759 (lane_width == 6) ? "x16" : "", 4760 (current_gen_speed == gen_speed) && 4761 (current_lane_width == lane_width) ? 4762 "*" : ""); 4763 } 4764 break; 4765 4766 case OD_SCLK: 4767 if (!hwmgr->od_enabled) 4768 return -EOPNOTSUPP; 4769 4770 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 4771 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4772 for (i = 0; i < podn_vdd_dep->count; i++) 4773 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4774 i, podn_vdd_dep->entries[i].clk / 100, 4775 podn_vdd_dep->entries[i].vddc); 4776 break; 4777 case OD_MCLK: 4778 if (!hwmgr->od_enabled) 4779 return -EOPNOTSUPP; 4780 4781 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 4782 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4783 for (i = 0; i < podn_vdd_dep->count; i++) 4784 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4785 i, podn_vdd_dep->entries[i].clk/100, 4786 podn_vdd_dep->entries[i].vddc); 4787 break; 4788 case OD_RANGE: 4789 if (!hwmgr->od_enabled) 4790 return -EOPNOTSUPP; 4791 4792 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 4793 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n", 4794 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4795 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4796 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n", 4797 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4798 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4799 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n", 4800 data->odn_dpm_table.min_vddc, 4801 data->odn_dpm_table.max_vddc); 4802 break; 4803 default: 4804 ret = -ENOENT; 4805 break; 4806 } 4807 return ret; 4808 } 4809 4810 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4811 { 4812 struct vega10_hwmgr *data = hwmgr->backend; 4813 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 4814 int result = 0; 4815 4816 if ((data->water_marks_bitmap & WaterMarksExist) && 4817 !(data->water_marks_bitmap & WaterMarksLoaded)) { 4818 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); 4819 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 4820 data->water_marks_bitmap |= WaterMarksLoaded; 4821 } 4822 4823 if (data->water_marks_bitmap & WaterMarksLoaded) { 4824 smum_send_msg_to_smc_with_parameter(hwmgr, 4825 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 4826 NULL); 4827 } 4828 4829 return result; 4830 } 4831 4832 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 4833 { 4834 struct vega10_hwmgr *data = hwmgr->backend; 4835 4836 if (data->smu_features[GNLD_DPM_UVD].supported) { 4837 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 4838 enable, 4839 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 4840 "Attempt to Enable/Disable DPM UVD Failed!", 4841 return -1); 4842 data->smu_features[GNLD_DPM_UVD].enabled = enable; 4843 } 4844 return 0; 4845 } 4846 4847 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 4848 { 4849 struct vega10_hwmgr *data = hwmgr->backend; 4850 4851 data->vce_power_gated = bgate; 4852 vega10_enable_disable_vce_dpm(hwmgr, !bgate); 4853 } 4854 4855 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 4856 { 4857 struct vega10_hwmgr *data = hwmgr->backend; 4858 4859 data->uvd_power_gated = bgate; 4860 vega10_enable_disable_uvd_dpm(hwmgr, !bgate); 4861 } 4862 4863 static inline bool vega10_are_power_levels_equal( 4864 const struct vega10_performance_level *pl1, 4865 const struct vega10_performance_level *pl2) 4866 { 4867 return ((pl1->soc_clock == pl2->soc_clock) && 4868 (pl1->gfx_clock == pl2->gfx_clock) && 4869 (pl1->mem_clock == pl2->mem_clock)); 4870 } 4871 4872 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, 4873 const struct pp_hw_power_state *pstate1, 4874 const struct pp_hw_power_state *pstate2, bool *equal) 4875 { 4876 const struct vega10_power_state *vega10_psa; 4877 const struct vega10_power_state *vega10_psb; 4878 int i; 4879 4880 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4881 return -EINVAL; 4882 4883 vega10_psa = cast_const_phw_vega10_power_state(pstate1); 4884 vega10_psb = cast_const_phw_vega10_power_state(pstate2); 4885 if (vega10_psa == NULL || vega10_psb == NULL) 4886 return -EINVAL; 4887 4888 /* If the two states don't even have the same number of performance levels 4889 * they cannot be the same state. 4890 */ 4891 if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) { 4892 *equal = false; 4893 return 0; 4894 } 4895 4896 for (i = 0; i < vega10_psa->performance_level_count; i++) { 4897 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]), 4898 &(vega10_psb->performance_levels[i]))) { 4899 /* If we have found even one performance level pair 4900 * that is different the states are different. 4901 */ 4902 *equal = false; 4903 return 0; 4904 } 4905 } 4906 4907 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 4908 *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) && 4909 (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk)); 4910 *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) && 4911 (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk)); 4912 *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold); 4913 4914 return 0; 4915 } 4916 4917 static bool 4918 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 4919 { 4920 struct vega10_hwmgr *data = hwmgr->backend; 4921 bool is_update_required = false; 4922 4923 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4924 is_update_required = true; 4925 4926 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { 4927 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 4928 is_update_required = true; 4929 } 4930 4931 return is_update_required; 4932 } 4933 4934 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 4935 { 4936 int tmp_result, result = 0; 4937 4938 if (!hwmgr->not_vf) 4939 return 0; 4940 4941 if (PP_CAP(PHM_PlatformCaps_ThermalController)) 4942 vega10_disable_thermal_protection(hwmgr); 4943 4944 tmp_result = vega10_disable_power_containment(hwmgr); 4945 PP_ASSERT_WITH_CODE((tmp_result == 0), 4946 "Failed to disable power containment!", result = tmp_result); 4947 4948 tmp_result = vega10_disable_didt_config(hwmgr); 4949 PP_ASSERT_WITH_CODE((tmp_result == 0), 4950 "Failed to disable didt config!", result = tmp_result); 4951 4952 tmp_result = vega10_avfs_enable(hwmgr, false); 4953 PP_ASSERT_WITH_CODE((tmp_result == 0), 4954 "Failed to disable AVFS!", result = tmp_result); 4955 4956 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 4957 PP_ASSERT_WITH_CODE((tmp_result == 0), 4958 "Failed to stop DPM!", result = tmp_result); 4959 4960 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); 4961 PP_ASSERT_WITH_CODE((tmp_result == 0), 4962 "Failed to disable deep sleep!", result = tmp_result); 4963 4964 tmp_result = vega10_disable_ulv(hwmgr); 4965 PP_ASSERT_WITH_CODE((tmp_result == 0), 4966 "Failed to disable ulv!", result = tmp_result); 4967 4968 tmp_result = vega10_acg_disable(hwmgr); 4969 PP_ASSERT_WITH_CODE((tmp_result == 0), 4970 "Failed to disable acg!", result = tmp_result); 4971 4972 vega10_enable_disable_PCC_limit_feature(hwmgr, false); 4973 return result; 4974 } 4975 4976 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) 4977 { 4978 struct vega10_hwmgr *data = hwmgr->backend; 4979 int result; 4980 4981 result = vega10_disable_dpm_tasks(hwmgr); 4982 PP_ASSERT_WITH_CODE((0 == result), 4983 "[disable_dpm_tasks] Failed to disable DPM!", 4984 ); 4985 data->water_marks_bitmap &= ~(WaterMarksLoaded); 4986 4987 return result; 4988 } 4989 4990 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) 4991 { 4992 struct vega10_hwmgr *data = hwmgr->backend; 4993 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4994 struct vega10_single_dpm_table *golden_sclk_table = 4995 &(data->golden_dpm_table.gfx_table); 4996 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 4997 int golden_value = golden_sclk_table->dpm_levels 4998 [golden_sclk_table->count - 1].value; 4999 5000 value -= golden_value; 5001 value = DIV_ROUND_UP(value * 100, golden_value); 5002 5003 return value; 5004 } 5005 5006 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5007 { 5008 struct vega10_hwmgr *data = hwmgr->backend; 5009 struct vega10_single_dpm_table *golden_sclk_table = 5010 &(data->golden_dpm_table.gfx_table); 5011 struct pp_power_state *ps; 5012 struct vega10_power_state *vega10_ps; 5013 5014 ps = hwmgr->request_ps; 5015 5016 if (ps == NULL) 5017 return -EINVAL; 5018 5019 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5020 if (vega10_ps == NULL) 5021 return -EINVAL; 5022 5023 vega10_ps->performance_levels 5024 [vega10_ps->performance_level_count - 1].gfx_clock = 5025 golden_sclk_table->dpm_levels 5026 [golden_sclk_table->count - 1].value * 5027 value / 100 + 5028 golden_sclk_table->dpm_levels 5029 [golden_sclk_table->count - 1].value; 5030 5031 if (vega10_ps->performance_levels 5032 [vega10_ps->performance_level_count - 1].gfx_clock > 5033 hwmgr->platform_descriptor.overdriveLimit.engineClock) { 5034 vega10_ps->performance_levels 5035 [vega10_ps->performance_level_count - 1].gfx_clock = 5036 hwmgr->platform_descriptor.overdriveLimit.engineClock; 5037 pr_warn("max sclk supported by vbios is %d\n", 5038 hwmgr->platform_descriptor.overdriveLimit.engineClock); 5039 } 5040 return 0; 5041 } 5042 5043 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) 5044 { 5045 struct vega10_hwmgr *data = hwmgr->backend; 5046 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 5047 struct vega10_single_dpm_table *golden_mclk_table = 5048 &(data->golden_dpm_table.mem_table); 5049 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5050 int golden_value = golden_mclk_table->dpm_levels 5051 [golden_mclk_table->count - 1].value; 5052 5053 value -= golden_value; 5054 value = DIV_ROUND_UP(value * 100, golden_value); 5055 5056 return value; 5057 } 5058 5059 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5060 { 5061 struct vega10_hwmgr *data = hwmgr->backend; 5062 struct vega10_single_dpm_table *golden_mclk_table = 5063 &(data->golden_dpm_table.mem_table); 5064 struct pp_power_state *ps; 5065 struct vega10_power_state *vega10_ps; 5066 5067 ps = hwmgr->request_ps; 5068 5069 if (ps == NULL) 5070 return -EINVAL; 5071 5072 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5073 if (vega10_ps == NULL) 5074 return -EINVAL; 5075 5076 vega10_ps->performance_levels 5077 [vega10_ps->performance_level_count - 1].mem_clock = 5078 golden_mclk_table->dpm_levels 5079 [golden_mclk_table->count - 1].value * 5080 value / 100 + 5081 golden_mclk_table->dpm_levels 5082 [golden_mclk_table->count - 1].value; 5083 5084 if (vega10_ps->performance_levels 5085 [vega10_ps->performance_level_count - 1].mem_clock > 5086 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { 5087 vega10_ps->performance_levels 5088 [vega10_ps->performance_level_count - 1].mem_clock = 5089 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 5090 pr_warn("max mclk supported by vbios is %d\n", 5091 hwmgr->platform_descriptor.overdriveLimit.memoryClock); 5092 } 5093 5094 return 0; 5095 } 5096 5097 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5098 uint32_t virtual_addr_low, 5099 uint32_t virtual_addr_hi, 5100 uint32_t mc_addr_low, 5101 uint32_t mc_addr_hi, 5102 uint32_t size) 5103 { 5104 smum_send_msg_to_smc_with_parameter(hwmgr, 5105 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 5106 virtual_addr_hi, 5107 NULL); 5108 smum_send_msg_to_smc_with_parameter(hwmgr, 5109 PPSMC_MSG_SetSystemVirtualDramAddrLow, 5110 virtual_addr_low, 5111 NULL); 5112 smum_send_msg_to_smc_with_parameter(hwmgr, 5113 PPSMC_MSG_DramLogSetDramAddrHigh, 5114 mc_addr_hi, 5115 NULL); 5116 5117 smum_send_msg_to_smc_with_parameter(hwmgr, 5118 PPSMC_MSG_DramLogSetDramAddrLow, 5119 mc_addr_low, 5120 NULL); 5121 5122 smum_send_msg_to_smc_with_parameter(hwmgr, 5123 PPSMC_MSG_DramLogSetDramSize, 5124 size, 5125 NULL); 5126 return 0; 5127 } 5128 5129 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5130 struct PP_TemperatureRange *thermal_data) 5131 { 5132 struct vega10_hwmgr *data = hwmgr->backend; 5133 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 5134 struct phm_ppt_v2_information *pp_table_info = 5135 (struct phm_ppt_v2_information *)(hwmgr->pptable); 5136 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table; 5137 5138 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 5139 5140 thermal_data->max = pp_table->TedgeLimit * 5141 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5142 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 5143 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5144 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 5145 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5146 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 5147 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5148 thermal_data->mem_crit_max = pp_table->ThbmLimit * 5149 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5150 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 5151 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5152 5153 if (tdp_table->usSoftwareShutdownTemp > pp_table->ThotspotLimit && 5154 tdp_table->usSoftwareShutdownTemp < VEGA10_THERMAL_MAXIMUM_ALERT_TEMP) 5155 thermal_data->sw_ctf_threshold = tdp_table->usSoftwareShutdownTemp; 5156 else 5157 thermal_data->sw_ctf_threshold = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP; 5158 thermal_data->sw_ctf_threshold *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5159 5160 return 0; 5161 } 5162 5163 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5164 { 5165 struct vega10_hwmgr *data = hwmgr->backend; 5166 uint32_t i, size = 0; 5167 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 5168 {70, 60, 1, 3,}, 5169 {90, 60, 0, 0,}, 5170 {70, 60, 0, 0,}, 5171 {70, 90, 0, 0,}, 5172 {30, 60, 0, 6,}, 5173 }; 5174 static const char *title[6] = {"NUM", 5175 "MODE_NAME", 5176 "BUSY_SET_POINT", 5177 "FPS", 5178 "USE_RLC_BUSY", 5179 "MIN_ACTIVE_LEVEL"}; 5180 5181 if (!buf) 5182 return -EINVAL; 5183 5184 phm_get_sysfs_buf(&buf, &size); 5185 5186 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], 5187 title[1], title[2], title[3], title[4], title[5]); 5188 5189 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) 5190 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", 5191 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5192 profile_mode_setting[i][0], profile_mode_setting[i][1], 5193 profile_mode_setting[i][2], profile_mode_setting[i][3]); 5194 5195 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, 5196 amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5197 data->custom_profile_mode[0], data->custom_profile_mode[1], 5198 data->custom_profile_mode[2], data->custom_profile_mode[3]); 5199 return size; 5200 } 5201 5202 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) 5203 { 5204 struct amdgpu_device *adev = hwmgr->adev; 5205 5206 return (adev->pdev->device == 0x6860); 5207 } 5208 5209 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5210 { 5211 struct vega10_hwmgr *data = hwmgr->backend; 5212 uint8_t busy_set_point; 5213 uint8_t FPS; 5214 uint8_t use_rlc_busy; 5215 uint8_t min_active_level; 5216 uint32_t power_profile_mode = input[size]; 5217 5218 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 5219 if (size != 0 && size != 4) 5220 return -EINVAL; 5221 5222 /* If size = 0 and the CUSTOM profile has been set already 5223 * then just apply the profile. The copy stored in the hwmgr 5224 * is zeroed out on init 5225 */ 5226 if (size == 0) { 5227 if (data->custom_profile_mode[0] != 0) 5228 goto out; 5229 else 5230 return -EINVAL; 5231 } 5232 5233 data->custom_profile_mode[0] = busy_set_point = input[0]; 5234 data->custom_profile_mode[1] = FPS = input[1]; 5235 data->custom_profile_mode[2] = use_rlc_busy = input[2]; 5236 data->custom_profile_mode[3] = min_active_level = input[3]; 5237 smum_send_msg_to_smc_with_parameter(hwmgr, 5238 PPSMC_MSG_SetCustomGfxDpmParameters, 5239 busy_set_point | FPS<<8 | 5240 use_rlc_busy << 16 | min_active_level<<24, 5241 NULL); 5242 } 5243 5244 out: 5245 if (vega10_get_power_profile_mode_quirks(hwmgr)) 5246 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5247 1 << power_profile_mode, 5248 NULL); 5249 else 5250 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5251 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), 5252 NULL); 5253 5254 hwmgr->power_profile_mode = power_profile_mode; 5255 5256 return 0; 5257 } 5258 5259 5260 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5261 enum PP_OD_DPM_TABLE_COMMAND type, 5262 uint32_t clk, 5263 uint32_t voltage) 5264 { 5265 struct vega10_hwmgr *data = hwmgr->backend; 5266 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 5267 struct vega10_single_dpm_table *golden_table; 5268 5269 if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) { 5270 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc); 5271 return false; 5272 } 5273 5274 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5275 golden_table = &(data->golden_dpm_table.gfx_table); 5276 if (golden_table->dpm_levels[0].value > clk || 5277 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5278 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5279 golden_table->dpm_levels[0].value/100, 5280 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5281 return false; 5282 } 5283 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5284 golden_table = &(data->golden_dpm_table.mem_table); 5285 if (golden_table->dpm_levels[0].value > clk || 5286 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5287 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5288 golden_table->dpm_levels[0].value/100, 5289 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5290 return false; 5291 } 5292 } else { 5293 return false; 5294 } 5295 5296 return true; 5297 } 5298 5299 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) 5300 { 5301 struct vega10_hwmgr *data = hwmgr->backend; 5302 struct pp_power_state *ps = hwmgr->request_ps; 5303 struct vega10_power_state *vega10_ps; 5304 struct vega10_single_dpm_table *gfx_dpm_table = 5305 &data->dpm_table.gfx_table; 5306 struct vega10_single_dpm_table *soc_dpm_table = 5307 &data->dpm_table.soc_table; 5308 struct vega10_single_dpm_table *mem_dpm_table = 5309 &data->dpm_table.mem_table; 5310 int max_level; 5311 5312 if (!ps) 5313 return; 5314 5315 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5316 if (vega10_ps == NULL) 5317 return; 5318 5319 max_level = vega10_ps->performance_level_count - 1; 5320 5321 if (vega10_ps->performance_levels[max_level].gfx_clock != 5322 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5323 vega10_ps->performance_levels[max_level].gfx_clock = 5324 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5325 5326 if (vega10_ps->performance_levels[max_level].soc_clock != 5327 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5328 vega10_ps->performance_levels[max_level].soc_clock = 5329 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5330 5331 if (vega10_ps->performance_levels[max_level].mem_clock != 5332 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5333 vega10_ps->performance_levels[max_level].mem_clock = 5334 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5335 5336 if (!hwmgr->ps) 5337 return; 5338 5339 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); 5340 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5341 if (vega10_ps == NULL) 5342 return; 5343 5344 max_level = vega10_ps->performance_level_count - 1; 5345 5346 if (vega10_ps->performance_levels[max_level].gfx_clock != 5347 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5348 vega10_ps->performance_levels[max_level].gfx_clock = 5349 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5350 5351 if (vega10_ps->performance_levels[max_level].soc_clock != 5352 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5353 vega10_ps->performance_levels[max_level].soc_clock = 5354 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5355 5356 if (vega10_ps->performance_levels[max_level].mem_clock != 5357 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5358 vega10_ps->performance_levels[max_level].mem_clock = 5359 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5360 } 5361 5362 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, 5363 enum PP_OD_DPM_TABLE_COMMAND type) 5364 { 5365 struct vega10_hwmgr *data = hwmgr->backend; 5366 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 5367 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk; 5368 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; 5369 5370 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk = 5371 &data->odn_dpm_table.vdd_dep_on_socclk; 5372 struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table; 5373 5374 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep; 5375 uint8_t i, j; 5376 5377 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5378 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 5379 for (i = 0; i < podn_vdd_dep->count; i++) 5380 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5381 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5382 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 5383 for (i = 0; i < dpm_table->count; i++) { 5384 for (j = 0; j < od_vddc_lookup_table->count; j++) { 5385 if (od_vddc_lookup_table->entries[j].us_vdd > 5386 podn_vdd_dep->entries[i].vddc) 5387 break; 5388 } 5389 if (j == od_vddc_lookup_table->count) { 5390 j = od_vddc_lookup_table->count - 1; 5391 od_vddc_lookup_table->entries[j].us_vdd = 5392 podn_vdd_dep->entries[i].vddc; 5393 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 5394 } 5395 podn_vdd_dep->entries[i].vddInd = j; 5396 } 5397 dpm_table = &data->dpm_table.soc_table; 5398 for (i = 0; i < dep_table->count; i++) { 5399 if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd && 5400 dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) { 5401 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5402 for (; (i < dep_table->count) && 5403 (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) { 5404 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk; 5405 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk; 5406 } 5407 break; 5408 } else { 5409 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk; 5410 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc; 5411 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd; 5412 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk; 5413 } 5414 } 5415 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk < 5416 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) { 5417 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5418 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = 5419 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5420 dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = 5421 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5422 } 5423 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd < 5424 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) { 5425 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5426 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = 5427 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd; 5428 } 5429 } 5430 vega10_odn_update_power_state(hwmgr); 5431 } 5432 5433 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5434 enum PP_OD_DPM_TABLE_COMMAND type, 5435 long *input, uint32_t size) 5436 { 5437 struct vega10_hwmgr *data = hwmgr->backend; 5438 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table; 5439 struct vega10_single_dpm_table *dpm_table; 5440 5441 uint32_t input_clk; 5442 uint32_t input_vol; 5443 uint32_t input_level; 5444 uint32_t i; 5445 5446 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5447 return -EINVAL); 5448 5449 if (!hwmgr->od_enabled) { 5450 pr_info("OverDrive feature not enabled\n"); 5451 return -EINVAL; 5452 } 5453 5454 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5455 dpm_table = &data->dpm_table.gfx_table; 5456 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk; 5457 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 5458 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5459 dpm_table = &data->dpm_table.mem_table; 5460 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk; 5461 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 5462 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5463 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); 5464 vega10_odn_initial_default_setting(hwmgr); 5465 vega10_odn_update_power_state(hwmgr); 5466 /* force to update all clock tables */ 5467 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | 5468 DPMTABLE_UPDATE_MCLK | 5469 DPMTABLE_UPDATE_SOCCLK; 5470 return 0; 5471 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5472 vega10_check_dpm_table_updated(hwmgr); 5473 return 0; 5474 } else { 5475 return -EINVAL; 5476 } 5477 5478 for (i = 0; i < size; i += 3) { 5479 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) { 5480 pr_info("invalid clock voltage input\n"); 5481 return 0; 5482 } 5483 input_level = input[i]; 5484 input_clk = input[i+1] * 100; 5485 input_vol = input[i+2]; 5486 5487 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5488 dpm_table->dpm_levels[input_level].value = input_clk; 5489 podn_vdd_dep_table->entries[input_level].clk = input_clk; 5490 podn_vdd_dep_table->entries[input_level].vddc = input_vol; 5491 } else { 5492 return -EINVAL; 5493 } 5494 } 5495 vega10_odn_update_soc_table(hwmgr, type); 5496 return 0; 5497 } 5498 5499 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, 5500 enum pp_mp1_state mp1_state) 5501 { 5502 uint16_t msg; 5503 int ret; 5504 5505 switch (mp1_state) { 5506 case PP_MP1_STATE_UNLOAD: 5507 msg = PPSMC_MSG_PrepareMp1ForUnload; 5508 break; 5509 case PP_MP1_STATE_SHUTDOWN: 5510 case PP_MP1_STATE_RESET: 5511 case PP_MP1_STATE_NONE: 5512 default: 5513 return 0; 5514 } 5515 5516 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 5517 "[PrepareMp1] Failed!", 5518 return ret); 5519 5520 return 0; 5521 } 5522 5523 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5524 PHM_PerformanceLevelDesignation designation, uint32_t index, 5525 PHM_PerformanceLevel *level) 5526 { 5527 const struct vega10_power_state *vega10_ps; 5528 uint32_t i; 5529 5530 if (level == NULL || hwmgr == NULL || state == NULL) 5531 return -EINVAL; 5532 5533 vega10_ps = cast_const_phw_vega10_power_state(state); 5534 if (vega10_ps == NULL) 5535 return -EINVAL; 5536 5537 i = index > vega10_ps->performance_level_count - 1 ? 5538 vega10_ps->performance_level_count - 1 : index; 5539 5540 level->coreClock = vega10_ps->performance_levels[i].gfx_clock; 5541 level->memory_clock = vega10_ps->performance_levels[i].mem_clock; 5542 5543 return 0; 5544 } 5545 5546 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) 5547 { 5548 struct vega10_hwmgr *data = hwmgr->backend; 5549 uint32_t feature_mask = 0; 5550 5551 if (disable) { 5552 feature_mask |= data->smu_features[GNLD_ULV].enabled ? 5553 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5554 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? 5555 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5556 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? 5557 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5558 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? 5559 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5560 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? 5561 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5562 } else { 5563 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? 5564 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5565 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? 5566 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5567 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? 5568 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5569 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? 5570 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5571 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? 5572 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5573 } 5574 5575 if (feature_mask) 5576 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 5577 !disable, feature_mask), 5578 "enable/disable power features for compute performance Failed!", 5579 return -EINVAL); 5580 5581 if (disable) { 5582 data->smu_features[GNLD_ULV].enabled = false; 5583 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 5584 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 5585 data->smu_features[GNLD_DS_LCLK].enabled = false; 5586 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 5587 } else { 5588 data->smu_features[GNLD_ULV].enabled = true; 5589 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 5590 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 5591 data->smu_features[GNLD_DS_LCLK].enabled = true; 5592 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 5593 } 5594 5595 return 0; 5596 5597 } 5598 5599 static const struct pp_hwmgr_func vega10_hwmgr_funcs = { 5600 .backend_init = vega10_hwmgr_backend_init, 5601 .backend_fini = vega10_hwmgr_backend_fini, 5602 .asic_setup = vega10_setup_asic_task, 5603 .dynamic_state_management_enable = vega10_enable_dpm_tasks, 5604 .dynamic_state_management_disable = vega10_disable_dpm_tasks, 5605 .get_num_of_pp_table_entries = 5606 vega10_get_number_of_powerplay_table_entries, 5607 .get_power_state_size = vega10_get_power_state_size, 5608 .get_pp_table_entry = vega10_get_pp_table_entry, 5609 .patch_boot_state = vega10_patch_boot_state, 5610 .apply_state_adjust_rules = vega10_apply_state_adjust_rules, 5611 .power_state_set = vega10_set_power_state_tasks, 5612 .get_sclk = vega10_dpm_get_sclk, 5613 .get_mclk = vega10_dpm_get_mclk, 5614 .notify_smc_display_config_after_ps_adjustment = 5615 vega10_notify_smc_display_config_after_ps_adjustment, 5616 .force_dpm_level = vega10_dpm_force_dpm_level, 5617 .stop_thermal_controller = vega10_thermal_stop_thermal_controller, 5618 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info, 5619 .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm, 5620 .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm, 5621 .reset_fan_speed_to_default = 5622 vega10_fan_ctrl_reset_fan_speed_to_default, 5623 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm, 5624 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm, 5625 .uninitialize_thermal_controller = 5626 vega10_thermal_ctrl_uninitialize_thermal_controller, 5627 .set_fan_control_mode = vega10_set_fan_control_mode, 5628 .get_fan_control_mode = vega10_get_fan_control_mode, 5629 .read_sensor = vega10_read_sensor, 5630 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency, 5631 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage, 5632 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges, 5633 .display_clock_voltage_request = vega10_display_clock_voltage_request, 5634 .force_clock_level = vega10_force_clock_level, 5635 .emit_clock_levels = vega10_emit_clock_levels, 5636 .display_config_changed = vega10_display_configuration_changed_task, 5637 .powergate_uvd = vega10_power_gate_uvd, 5638 .powergate_vce = vega10_power_gate_vce, 5639 .check_states_equal = vega10_check_states_equal, 5640 .check_smc_update_required_for_display_configuration = 5641 vega10_check_smc_update_required_for_display_configuration, 5642 .power_off_asic = vega10_power_off_asic, 5643 .disable_smc_firmware_ctf = vega10_thermal_disable_alert, 5644 .get_sclk_od = vega10_get_sclk_od, 5645 .set_sclk_od = vega10_set_sclk_od, 5646 .get_mclk_od = vega10_get_mclk_od, 5647 .set_mclk_od = vega10_set_mclk_od, 5648 .avfs_control = vega10_avfs_enable, 5649 .notify_cac_buffer_info = vega10_notify_cac_buffer_info, 5650 .get_thermal_temperature_range = vega10_get_thermal_temperature_range, 5651 .register_irq_handlers = smu9_register_irq_handlers, 5652 .start_thermal_controller = vega10_start_thermal_controller, 5653 .get_power_profile_mode = vega10_get_power_profile_mode, 5654 .set_power_profile_mode = vega10_set_power_profile_mode, 5655 .set_power_limit = vega10_set_power_limit, 5656 .odn_edit_dpm_table = vega10_odn_edit_dpm_table, 5657 .get_performance_level = vega10_get_performance_level, 5658 .get_bamaco_support = smu9_get_bamaco_support, 5659 .get_asic_baco_state = smu9_baco_get_state, 5660 .set_asic_baco_state = vega10_baco_set_state, 5661 .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost, 5662 .get_ppfeature_status = vega10_get_ppfeature_status, 5663 .set_ppfeature_status = vega10_set_ppfeature_status, 5664 .set_mp1_state = vega10_set_mp1_state, 5665 .disable_power_features_for_compute_performance = 5666 vega10_disable_power_features_for_compute_performance, 5667 }; 5668 5669 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) 5670 { 5671 struct amdgpu_device *adev = hwmgr->adev; 5672 5673 hwmgr->hwmgr_func = &vega10_hwmgr_funcs; 5674 hwmgr->pptable_func = &vega10_pptable_funcs; 5675 if (amdgpu_passthrough(adev)) 5676 return vega10_baco_set_cap(hwmgr); 5677 5678 return 0; 5679 } 5680