1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * AMD MP2 common macros and structures 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com> 9 */ 10 #ifndef AMD_SFH_COMMON_H 11 #define AMD_SFH_COMMON_H 12 13 #include <linux/auxiliary_bus.h> 14 #include <linux/mutex.h> 15 #include <linux/pci.h> 16 #include <linux/sizes.h> 17 #include "amd_sfh_hid.h" 18 19 #define PCI_DEVICE_ID_AMD_MP2 0x15E4 20 #define PCI_DEVICE_ID_AMD_MP2_1_1 0x164A 21 #define PCI_DEVICE_ID_AMD_MP2_1_2 0x1152 22 23 /* The BAR 2 size must cover the highest register offset (0x10958) */ 24 #define AMD_SFH_MIN_BAR_SIZE SZ_128K 25 26 #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4)) 27 #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4)) 28 29 #define AMD_C2P_MSG_V1(regno) (0x10900 + ((regno) * 4)) 30 #define AMD_P2C_MSG_V1(regno) (0x10500 + ((regno) * 4)) 31 32 #define SENSOR_ENABLED 4 33 #define SENSOR_DISABLED 5 34 35 #define AMD_SFH_IDLE_LOOP 200 36 37 enum cmd_id { 38 NO_OP, 39 ENABLE_SENSOR, 40 DISABLE_SENSOR, 41 STOP_ALL_SENSORS = 8, 42 }; 43 44 enum amd_mp2_version { 45 MP2_VER_V2 = 1, 46 MP2_VER_1_1 = 2, 47 MP2_VER_1_2 = 3, 48 }; 49 50 struct amd_mp2_sensor_info { 51 u8 sensor_idx; 52 u32 period; 53 dma_addr_t dma_address; 54 }; 55 56 struct sfh_dev_status { 57 bool is_hpd_present; 58 bool is_hpd_enabled; 59 bool is_als_present; 60 bool is_sra_present; 61 }; 62 63 struct amd_mp2_dev { 64 struct pci_dev *pdev; 65 struct amdtp_cl_data *cl_data; 66 void __iomem *mmio; 67 void __iomem *vsbase; 68 const struct amd_sfh1_1_ops *sfh1_1_ops; 69 struct amd_mp2_ops *mp2_ops; 70 struct amd_input_data in_data; 71 /* mp2 active control status */ 72 u32 mp2_acs; 73 struct sfh_dev_status dev_en; 74 struct work_struct work; 75 /* mp2 to protect data */ 76 struct mutex lock; 77 u8 init_done; 78 u8 rver; 79 u8 mp2_ver; 80 struct auxiliary_device *tm_auxdev; 81 }; 82 83 struct amd_mp2_ops { 84 void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); 85 void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx); 86 void (*stop_all)(struct amd_mp2_dev *privdata); 87 int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts); 88 void (*clear_intr)(struct amd_mp2_dev *privdata); 89 int (*init_intr)(struct amd_mp2_dev *privdata); 90 int (*discovery_status)(struct amd_mp2_dev *privdata); 91 void (*suspend)(struct amd_mp2_dev *mp2); 92 void (*resume)(struct amd_mp2_dev *mp2); 93 void (*remove)(void *privdata); 94 int (*get_rep_desc)(int sensor_idx, u8 rep_desc[]); 95 u32 (*get_desc_sz)(int sensor_idx, int descriptor_name); 96 u8 (*get_feat_rep)(int sensor_idx, int report_id, u8 *feature_report); 97 u8 (*get_in_rep)(u8 current_index, int sensor_idx, int report_id, 98 struct amd_input_data *in_data); 99 }; 100 101 void amd_sfh_work(struct work_struct *work); 102 void amd_sfh_work_buffer(struct work_struct *work); 103 void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata); 104 int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata); 105 void amd_sfh_clear_intr(struct amd_mp2_dev *privdata); 106 int amd_sfh_irq_init(struct amd_mp2_dev *privdata); 107 108 static inline u64 amd_get_c2p_val(struct amd_mp2_dev *mp2, u32 idx) 109 { 110 return mp2->rver == 1 ? AMD_C2P_MSG_V1(idx) : AMD_C2P_MSG(idx); 111 } 112 113 static inline u64 amd_get_p2c_val(struct amd_mp2_dev *mp2, u32 idx) 114 { 115 return mp2->rver == 1 ? AMD_P2C_MSG_V1(idx) : AMD_P2C_MSG(idx); 116 } 117 118 bool amd_sfh_op_idx_enabled(struct amd_mp2_dev *mp2); 119 void sfh_set_emp2(struct amd_mp2_dev *mp2); 120 void sfh_deinit_emp2(void); 121 122 #endif 123