1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include "opt_rss.h"
27 #include "opt_ratelimit.h"
28
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #if defined(CONFIG_X86)
35 #include <asm/pat.h>
36 #endif
37 #include <linux/sched.h>
38 #include <linux/delay.h>
39 #include <linux/fs.h>
40 #undef inode
41 #include <rdma/ib_user_verbs.h>
42 #include <rdma/ib_addr.h>
43 #include <rdma/ib_cache.h>
44 #include <dev/mlx5/port.h>
45 #include <dev/mlx5/vport.h>
46 #include <linux/list.h>
47 #include <rdma/ib_smi.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/uverbs_ioctl.h>
50 #include <rdma/uverbs_types.h>
51 #include <rdma/uverbs_std_types.h>
52 #define UVERBS_MODULE_NAME mlx5_ib
53 #include <rdma/uverbs_named_ioctl.h>
54 #include <rdma/mlx5_user_ioctl_cmds.h>
55 #include <rdma/mlx5_user_ioctl_verbs.h>
56 #include <linux/in.h>
57 #include <linux/etherdevice.h>
58 #include <dev/mlx5/fs.h>
59 #include <dev/mlx5/mlx5_ib/mlx5_ib.h>
60
61 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
64 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
65 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
66 MODULE_VERSION(mlx5ib, 1);
67
68 enum {
69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
70 };
71
72 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)73 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
74 {
75 switch (port_type_cap) {
76 case MLX5_CAP_PORT_TYPE_IB:
77 return IB_LINK_LAYER_INFINIBAND;
78 case MLX5_CAP_PORT_TYPE_ETH:
79 return IB_LINK_LAYER_ETHERNET;
80 default:
81 return IB_LINK_LAYER_UNSPECIFIED;
82 }
83 }
84
85 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u8 port_num)86 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
87 {
88 struct mlx5_ib_dev *dev = to_mdev(device);
89 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
90
91 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
92 }
93
mlx5_netdev_match(if_t ndev,struct mlx5_core_dev * mdev,const char * dname)94 static bool mlx5_netdev_match(if_t ndev,
95 struct mlx5_core_dev *mdev,
96 const char *dname)
97 {
98 return if_gettype(ndev) == IFT_ETHER &&
99 if_getdname(ndev) != NULL &&
100 strcmp(if_getdname(ndev), dname) == 0 &&
101 if_getsoftc(ndev) != NULL &&
102 *(struct mlx5_core_dev **)if_getsoftc(ndev) == mdev;
103 }
104
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)105 static int mlx5_netdev_event(struct notifier_block *this,
106 unsigned long event, void *ptr)
107 {
108 if_t ndev = netdev_notifier_info_to_ifp(ptr);
109 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
110 roce.nb);
111
112 switch (event) {
113 case NETDEV_REGISTER:
114 case NETDEV_UNREGISTER:
115 write_lock(&ibdev->roce.netdev_lock);
116 /* check if network interface belongs to mlx5en */
117 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
118 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
119 NULL : ndev;
120 write_unlock(&ibdev->roce.netdev_lock);
121 break;
122
123 case NETDEV_UP:
124 case NETDEV_DOWN: {
125 if_t upper = NULL;
126
127 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
128 && ibdev->ib_active) {
129 struct ib_event ibev = {0};
130
131 ibev.device = &ibdev->ib_dev;
132 ibev.event = (event == NETDEV_UP) ?
133 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
134 ibev.element.port_num = 1;
135 ib_dispatch_event(&ibev);
136 }
137 break;
138 }
139
140 default:
141 break;
142 }
143
144 return NOTIFY_DONE;
145 }
146
mlx5_ib_get_netdev(struct ib_device * device,u8 port_num)147 static if_t mlx5_ib_get_netdev(struct ib_device *device,
148 u8 port_num)
149 {
150 struct mlx5_ib_dev *ibdev = to_mdev(device);
151 if_t ndev;
152
153 /* Ensure ndev does not disappear before we invoke if_ref()
154 */
155 read_lock(&ibdev->roce.netdev_lock);
156 ndev = ibdev->roce.netdev;
157 if (ndev)
158 if_ref(ndev);
159 read_unlock(&ibdev->roce.netdev_lock);
160
161 return ndev;
162 }
163
translate_eth_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)164 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
165 u8 *active_width)
166 {
167 switch (eth_proto_oper) {
168 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
169 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
170 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
171 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
172 *active_width = IB_WIDTH_1X;
173 *active_speed = IB_SPEED_SDR;
174 break;
175 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
176 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
177 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
178 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
179 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
180 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
181 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR):
182 *active_width = IB_WIDTH_1X;
183 *active_speed = IB_SPEED_QDR;
184 break;
185 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
186 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
187 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
188 *active_width = IB_WIDTH_1X;
189 *active_speed = IB_SPEED_EDR;
190 break;
191 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
192 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
193 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
194 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4):
195 *active_width = IB_WIDTH_4X;
196 *active_speed = IB_SPEED_QDR;
197 break;
198 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
199 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
200 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4):
201 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
202 *active_width = IB_WIDTH_1X;
203 *active_speed = IB_SPEED_HDR;
204 break;
205 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
206 *active_width = IB_WIDTH_4X;
207 *active_speed = IB_SPEED_FDR;
208 break;
209 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
210 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
211 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
212 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
213 *active_width = IB_WIDTH_4X;
214 *active_speed = IB_SPEED_EDR;
215 break;
216 default:
217 *active_width = IB_WIDTH_4X;
218 *active_speed = IB_SPEED_QDR;
219 return -EINVAL;
220 }
221
222 return 0;
223 }
224
translate_eth_ext_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)225 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
226 u8 *active_width)
227 {
228 switch (eth_proto_oper) {
229 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
230 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
231 *active_width = IB_WIDTH_1X;
232 *active_speed = IB_SPEED_SDR;
233 break;
234 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
235 *active_width = IB_WIDTH_1X;
236 *active_speed = IB_SPEED_DDR;
237 break;
238 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
239 *active_width = IB_WIDTH_1X;
240 *active_speed = IB_SPEED_QDR;
241 break;
242 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
243 *active_width = IB_WIDTH_4X;
244 *active_speed = IB_SPEED_QDR;
245 break;
246 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
247 *active_width = IB_WIDTH_1X;
248 *active_speed = IB_SPEED_EDR;
249 break;
250 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
251 *active_width = IB_WIDTH_2X;
252 *active_speed = IB_SPEED_EDR;
253 break;
254 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
255 *active_width = IB_WIDTH_1X;
256 *active_speed = IB_SPEED_HDR;
257 break;
258 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
259 *active_width = IB_WIDTH_4X;
260 *active_speed = IB_SPEED_EDR;
261 break;
262 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
263 *active_width = IB_WIDTH_2X;
264 *active_speed = IB_SPEED_HDR;
265 break;
266 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
267 *active_width = IB_WIDTH_1X;
268 *active_speed = IB_SPEED_NDR;
269 break;
270 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
271 *active_width = IB_WIDTH_4X;
272 *active_speed = IB_SPEED_HDR;
273 break;
274 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
275 *active_width = IB_WIDTH_2X;
276 *active_speed = IB_SPEED_NDR;
277 break;
278 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
279 *active_width = IB_WIDTH_4X;
280 *active_speed = IB_SPEED_NDR;
281 break;
282 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2):
283 *active_width = IB_WIDTH_2X;
284 *active_speed = IB_SPEED_XDR;
285 break;
286 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
287 *active_width = IB_WIDTH_8X;
288 *active_speed = IB_SPEED_NDR;
289 break;
290 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4):
291 *active_width = IB_WIDTH_4X;
292 *active_speed = IB_SPEED_XDR;
293 break;
294 default:
295 *active_width = IB_WIDTH_4X;
296 *active_speed = IB_SPEED_QDR;
297 return -EINVAL;
298 }
299
300 return 0;
301 }
302
mlx5_query_port_roce(struct ib_device * device,u8 port_num,struct ib_port_attr * props)303 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
304 struct ib_port_attr *props)
305 {
306 struct mlx5_ib_dev *dev = to_mdev(device);
307 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
308 if_t ndev;
309 enum ib_mtu ndev_ib_mtu;
310 u16 qkey_viol_cntr;
311 u32 eth_prot_oper;
312 bool ext;
313 int err;
314
315 memset(props, 0, sizeof(*props));
316
317 /* Possible bad flows are checked before filling out props so in case
318 * of an error it will still be zeroed out.
319 */
320 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN,
321 port_num);
322 if (err)
323 return err;
324
325 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
326 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
327
328 if (ext)
329 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed,
330 &props->active_width);
331 else
332 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
333 &props->active_width);
334
335 props->port_cap_flags |= IB_PORT_CM_SUP;
336 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
337
338 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
339 roce_address_table_size);
340 props->max_mtu = IB_MTU_4096;
341 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
342 props->pkey_tbl_len = 1;
343 props->state = IB_PORT_DOWN;
344 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
345
346 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
347 props->qkey_viol_cntr = qkey_viol_cntr;
348
349 ndev = mlx5_ib_get_netdev(device, port_num);
350 if (!ndev)
351 return 0;
352
353 if (if_getdrvflags(ndev) & IFF_DRV_RUNNING &&
354 if_getlinkstate(ndev) == LINK_STATE_UP) {
355 props->state = IB_PORT_ACTIVE;
356 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
357 }
358
359 ndev_ib_mtu = iboe_get_mtu(if_getmtu(ndev));
360
361 if_rele(ndev);
362
363 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
364 return 0;
365 }
366
ib_gid_to_mlx5_roce_addr(const union ib_gid * gid,const struct ib_gid_attr * attr,void * mlx5_addr)367 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
368 const struct ib_gid_attr *attr,
369 void *mlx5_addr)
370 {
371 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
372 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
373 source_l3_address);
374 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
375 source_mac_47_32);
376 u16 vlan_id;
377 int ret;
378
379 if (!gid)
380 return;
381
382
383 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mlx5_addr_mac);
384 if (ret != 0)
385 return;
386
387 if (vlan_id != 0xffff) {
388 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
389 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id);
390 }
391
392 switch (attr->gid_type) {
393 case IB_GID_TYPE_IB:
394 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
395 break;
396 case IB_GID_TYPE_ROCE_UDP_ENCAP:
397 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
398 break;
399
400 default:
401 WARN_ON(true);
402 }
403
404 if (attr->gid_type != IB_GID_TYPE_IB) {
405 if (ipv6_addr_v4mapped((void *)gid))
406 MLX5_SET_RA(mlx5_addr, roce_l3_type,
407 MLX5_ROCE_L3_TYPE_IPV4);
408 else
409 MLX5_SET_RA(mlx5_addr, roce_l3_type,
410 MLX5_ROCE_L3_TYPE_IPV6);
411 }
412
413 if ((attr->gid_type == IB_GID_TYPE_IB) ||
414 !ipv6_addr_v4mapped((void *)gid))
415 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
416 else
417 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
418 }
419
set_roce_addr(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)420 static int set_roce_addr(struct ib_device *device, u8 port_num,
421 unsigned int index,
422 const union ib_gid *gid,
423 const struct ib_gid_attr *attr)
424 {
425 struct mlx5_ib_dev *dev = to_mdev(device);
426 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
427 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
428 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
429 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
430
431 if (ll != IB_LINK_LAYER_ETHERNET)
432 return -EINVAL;
433
434 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
435
436 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
437 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
438 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
439 }
440
mlx5_ib_add_gid(const struct ib_gid_attr * attr,__always_unused void ** context)441 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
442 __always_unused void **context)
443 {
444 return set_roce_addr(attr->device, attr->port_num, attr->index,
445 &attr->gid, attr);
446 }
447
mlx5_ib_del_gid(const struct ib_gid_attr * attr,__always_unused void ** context)448 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
449 __always_unused void **context)
450 {
451 return set_roce_addr(attr->device, attr->port_num, attr->index, NULL,
452 NULL);
453 }
454
mlx5_get_roce_udp_sport(struct mlx5_ib_dev * dev,const struct ib_gid_attr * attr)455 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
456 const struct ib_gid_attr *attr)
457 {
458 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
459 return 0;
460
461 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
462 }
463
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)464 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
465 {
466 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
467 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
468 return 0;
469 }
470
471 enum {
472 MLX5_VPORT_ACCESS_METHOD_MAD,
473 MLX5_VPORT_ACCESS_METHOD_HCA,
474 MLX5_VPORT_ACCESS_METHOD_NIC,
475 };
476
mlx5_get_vport_access_method(struct ib_device * ibdev)477 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
478 {
479 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
480 return MLX5_VPORT_ACCESS_METHOD_MAD;
481
482 if (mlx5_ib_port_link_layer(ibdev, 1) ==
483 IB_LINK_LAYER_ETHERNET)
484 return MLX5_VPORT_ACCESS_METHOD_NIC;
485
486 return MLX5_VPORT_ACCESS_METHOD_HCA;
487 }
488
get_atomic_caps(struct mlx5_ib_dev * dev,struct ib_device_attr * props)489 static void get_atomic_caps(struct mlx5_ib_dev *dev,
490 struct ib_device_attr *props)
491 {
492 u8 tmp;
493 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
494 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
495 u8 atomic_req_8B_endianness_mode =
496 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
497
498 /* Check if HW supports 8 bytes standard atomic operations and capable
499 * of host endianness respond
500 */
501 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
502 if (((atomic_operations & tmp) == tmp) &&
503 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
504 (atomic_req_8B_endianness_mode)) {
505 props->atomic_cap = IB_ATOMIC_HCA;
506 } else {
507 props->atomic_cap = IB_ATOMIC_NONE;
508 }
509 }
510
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)511 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
512 __be64 *sys_image_guid)
513 {
514 struct mlx5_ib_dev *dev = to_mdev(ibdev);
515 struct mlx5_core_dev *mdev = dev->mdev;
516 u64 tmp;
517 int err;
518
519 switch (mlx5_get_vport_access_method(ibdev)) {
520 case MLX5_VPORT_ACCESS_METHOD_MAD:
521 return mlx5_query_mad_ifc_system_image_guid(ibdev,
522 sys_image_guid);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
526 break;
527
528 case MLX5_VPORT_ACCESS_METHOD_NIC:
529 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
530 break;
531
532 default:
533 return -EINVAL;
534 }
535
536 if (!err)
537 *sys_image_guid = cpu_to_be64(tmp);
538
539 return err;
540
541 }
542
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)543 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
544 u16 *max_pkeys)
545 {
546 struct mlx5_ib_dev *dev = to_mdev(ibdev);
547 struct mlx5_core_dev *mdev = dev->mdev;
548
549 switch (mlx5_get_vport_access_method(ibdev)) {
550 case MLX5_VPORT_ACCESS_METHOD_MAD:
551 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
552
553 case MLX5_VPORT_ACCESS_METHOD_HCA:
554 case MLX5_VPORT_ACCESS_METHOD_NIC:
555 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
556 pkey_table_size));
557 return 0;
558
559 default:
560 return -EINVAL;
561 }
562 }
563
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)564 static int mlx5_query_vendor_id(struct ib_device *ibdev,
565 u32 *vendor_id)
566 {
567 struct mlx5_ib_dev *dev = to_mdev(ibdev);
568
569 switch (mlx5_get_vport_access_method(ibdev)) {
570 case MLX5_VPORT_ACCESS_METHOD_MAD:
571 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
572
573 case MLX5_VPORT_ACCESS_METHOD_HCA:
574 case MLX5_VPORT_ACCESS_METHOD_NIC:
575 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
576
577 default:
578 return -EINVAL;
579 }
580 }
581
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)582 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
583 __be64 *node_guid)
584 {
585 u64 tmp;
586 int err;
587
588 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
589 case MLX5_VPORT_ACCESS_METHOD_MAD:
590 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
591
592 case MLX5_VPORT_ACCESS_METHOD_HCA:
593 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
594 break;
595
596 case MLX5_VPORT_ACCESS_METHOD_NIC:
597 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
598 break;
599
600 default:
601 return -EINVAL;
602 }
603
604 if (!err)
605 *node_guid = cpu_to_be64(tmp);
606
607 return err;
608 }
609
610 struct mlx5_reg_node_desc {
611 u8 desc[IB_DEVICE_NODE_DESC_MAX];
612 };
613
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)614 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
615 {
616 struct mlx5_reg_node_desc in;
617
618 if (mlx5_use_mad_ifc(dev))
619 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
620
621 memset(&in, 0, sizeof(in));
622
623 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
624 sizeof(struct mlx5_reg_node_desc),
625 MLX5_REG_NODE_DESC, 0, 0);
626 }
627
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)628 static int mlx5_ib_query_device(struct ib_device *ibdev,
629 struct ib_device_attr *props,
630 struct ib_udata *uhw)
631 {
632 struct mlx5_ib_dev *dev = to_mdev(ibdev);
633 struct mlx5_core_dev *mdev = dev->mdev;
634 int err = -ENOMEM;
635 int max_sq_desc;
636 int max_rq_sg;
637 int max_sq_sg;
638 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
639 struct mlx5_ib_query_device_resp resp = {};
640 size_t resp_len;
641 u64 max_tso;
642
643 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
644 if (uhw->outlen && uhw->outlen < resp_len)
645 return -EINVAL;
646 else
647 resp.response_length = resp_len;
648
649 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
650 return -EINVAL;
651
652 memset(props, 0, sizeof(*props));
653 err = mlx5_query_system_image_guid(ibdev,
654 &props->sys_image_guid);
655 if (err)
656 return err;
657
658 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
659 if (err)
660 return err;
661
662 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
663 if (err)
664 return err;
665
666 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
667 ((u32)fw_rev_min(dev->mdev) << 16) |
668 fw_rev_sub(dev->mdev);
669 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
670 IB_DEVICE_PORT_ACTIVE_EVENT |
671 IB_DEVICE_SYS_IMAGE_GUID |
672 IB_DEVICE_RC_RNR_NAK_GEN |
673 IB_DEVICE_KNOWSEPOCH;
674
675 if (MLX5_CAP_GEN(mdev, pkv))
676 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
677 if (MLX5_CAP_GEN(mdev, qkv))
678 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
679 if (MLX5_CAP_GEN(mdev, apm))
680 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
681 if (MLX5_CAP_GEN(mdev, xrc))
682 props->device_cap_flags |= IB_DEVICE_XRC;
683 if (MLX5_CAP_GEN(mdev, imaicl)) {
684 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
685 IB_DEVICE_MEM_WINDOW_TYPE_2B;
686 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
687 /* We support 'Gappy' memory registration too */
688 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
689 }
690 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
691 if (MLX5_CAP_GEN(mdev, sho)) {
692 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
693 /* At this stage no support for signature handover */
694 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
695 IB_PROT_T10DIF_TYPE_2 |
696 IB_PROT_T10DIF_TYPE_3;
697 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
698 IB_GUARD_T10DIF_CSUM;
699 }
700 if (MLX5_CAP_GEN(mdev, block_lb_mc))
701 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
702
703 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
704 if (MLX5_CAP_ETH(mdev, csum_cap))
705 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
706
707 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
708 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
709 if (max_tso) {
710 resp.tso_caps.max_tso = 1 << max_tso;
711 resp.tso_caps.supported_qpts |=
712 1 << IB_QPT_RAW_PACKET;
713 resp.response_length += sizeof(resp.tso_caps);
714 }
715 }
716
717 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
718 resp.rss_caps.rx_hash_function =
719 MLX5_RX_HASH_FUNC_TOEPLITZ;
720 resp.rss_caps.rx_hash_fields_mask =
721 MLX5_RX_HASH_SRC_IPV4 |
722 MLX5_RX_HASH_DST_IPV4 |
723 MLX5_RX_HASH_SRC_IPV6 |
724 MLX5_RX_HASH_DST_IPV6 |
725 MLX5_RX_HASH_SRC_PORT_TCP |
726 MLX5_RX_HASH_DST_PORT_TCP |
727 MLX5_RX_HASH_SRC_PORT_UDP |
728 MLX5_RX_HASH_DST_PORT_UDP;
729 resp.response_length += sizeof(resp.rss_caps);
730 }
731 } else {
732 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
733 resp.response_length += sizeof(resp.tso_caps);
734 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
735 resp.response_length += sizeof(resp.rss_caps);
736 }
737
738 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
739 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
740 props->device_cap_flags |= IB_DEVICE_UD_TSO;
741 }
742
743 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
744 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
745 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
746
747 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
748 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
749
750 props->vendor_part_id = mdev->pdev->device;
751 props->hw_ver = mdev->pdev->revision;
752
753 props->max_mr_size = ~0ull;
754 props->page_size_cap = ~(min_page_size - 1);
755 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
756 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
757 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
758 sizeof(struct mlx5_wqe_data_seg);
759 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
760 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
761 sizeof(struct mlx5_wqe_raddr_seg)) /
762 sizeof(struct mlx5_wqe_data_seg);
763 props->max_sge = min(max_rq_sg, max_sq_sg);
764 props->max_sge_rd = MLX5_MAX_SGE_RD;
765 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
766 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
767 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
768 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
769 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
770 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
771 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
772 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
773 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
774 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
775 props->max_srq_sge = max_rq_sg - 1;
776 props->max_fast_reg_page_list_len =
777 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
778 get_atomic_caps(dev, props);
779 props->masked_atomic_cap = IB_ATOMIC_NONE;
780 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
781 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
782 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
783 props->max_mcast_grp;
784 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
785 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
786 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
787
788 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
789 if (MLX5_CAP_GEN(mdev, pg))
790 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
791 props->odp_caps = dev->odp_caps;
792 #endif
793
794 if (MLX5_CAP_GEN(mdev, cd))
795 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
796
797 if (!mlx5_core_is_pf(mdev))
798 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
799
800 if (mlx5_ib_port_link_layer(ibdev, 1) ==
801 IB_LINK_LAYER_ETHERNET) {
802 props->rss_caps.max_rwq_indirection_tables =
803 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
804 props->rss_caps.max_rwq_indirection_table_size =
805 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
806 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
807 props->max_wq_type_rq =
808 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
809 }
810
811 if (uhw->outlen) {
812 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
813
814 if (err)
815 return err;
816 }
817
818 return 0;
819 }
820
821 enum mlx5_ib_width {
822 MLX5_IB_WIDTH_1X = 1 << 0,
823 MLX5_IB_WIDTH_2X = 1 << 1,
824 MLX5_IB_WIDTH_4X = 1 << 2,
825 MLX5_IB_WIDTH_8X = 1 << 3,
826 MLX5_IB_WIDTH_12X = 1 << 4
827 };
828
translate_active_width(struct ib_device * ibdev,u8 active_width,u8 * ib_width)829 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
830 u8 *ib_width)
831 {
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
833 int err = 0;
834
835 if (active_width & MLX5_IB_WIDTH_1X) {
836 *ib_width = IB_WIDTH_1X;
837 } else if (active_width & MLX5_IB_WIDTH_2X) {
838 *ib_width = IB_WIDTH_2X;
839 } else if (active_width & MLX5_IB_WIDTH_4X) {
840 *ib_width = IB_WIDTH_4X;
841 } else if (active_width & MLX5_IB_WIDTH_8X) {
842 *ib_width = IB_WIDTH_8X;
843 } else if (active_width & MLX5_IB_WIDTH_12X) {
844 *ib_width = IB_WIDTH_12X;
845 } else {
846 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
847 (int)active_width);
848 err = -EINVAL;
849 }
850
851 return err;
852 }
853
854 enum ib_max_vl_num {
855 __IB_MAX_VL_0 = 1,
856 __IB_MAX_VL_0_1 = 2,
857 __IB_MAX_VL_0_3 = 3,
858 __IB_MAX_VL_0_7 = 4,
859 __IB_MAX_VL_0_14 = 5,
860 };
861
862 enum mlx5_vl_hw_cap {
863 MLX5_VL_HW_0 = 1,
864 MLX5_VL_HW_0_1 = 2,
865 MLX5_VL_HW_0_2 = 3,
866 MLX5_VL_HW_0_3 = 4,
867 MLX5_VL_HW_0_4 = 5,
868 MLX5_VL_HW_0_5 = 6,
869 MLX5_VL_HW_0_6 = 7,
870 MLX5_VL_HW_0_7 = 8,
871 MLX5_VL_HW_0_14 = 15
872 };
873
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)874 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
875 u8 *max_vl_num)
876 {
877 switch (vl_hw_cap) {
878 case MLX5_VL_HW_0:
879 *max_vl_num = __IB_MAX_VL_0;
880 break;
881 case MLX5_VL_HW_0_1:
882 *max_vl_num = __IB_MAX_VL_0_1;
883 break;
884 case MLX5_VL_HW_0_3:
885 *max_vl_num = __IB_MAX_VL_0_3;
886 break;
887 case MLX5_VL_HW_0_7:
888 *max_vl_num = __IB_MAX_VL_0_7;
889 break;
890 case MLX5_VL_HW_0_14:
891 *max_vl_num = __IB_MAX_VL_0_14;
892 break;
893
894 default:
895 return -EINVAL;
896 }
897
898 return 0;
899 }
900
mlx5_query_hca_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)901 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
902 struct ib_port_attr *props)
903 {
904 struct mlx5_ib_dev *dev = to_mdev(ibdev);
905 struct mlx5_core_dev *mdev = dev->mdev;
906 u32 *rep;
907 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
908 struct mlx5_ptys_reg *ptys;
909 struct mlx5_pmtu_reg *pmtu;
910 struct mlx5_pvlc_reg pvlc;
911 void *ctx;
912 int err;
913
914 rep = mlx5_vzalloc(replen);
915 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
916 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
917 if (!rep || !ptys || !pmtu) {
918 err = -ENOMEM;
919 goto out;
920 }
921
922 memset(props, 0, sizeof(*props));
923
924 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
925 if (err)
926 goto out;
927
928 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
929
930 props->lid = MLX5_GET(hca_vport_context, ctx, lid);
931 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc);
932 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid);
933 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl);
934 props->state = MLX5_GET(hca_vport_context, ctx, vport_state);
935 props->phys_state = MLX5_GET(hca_vport_context, ctx,
936 port_physical_state);
937 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1);
938 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
939 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
940 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
941 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx,
942 pkey_violation_counter);
943 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx,
944 qkey_violation_counter);
945 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx,
946 subnet_timeout);
947 props->init_type_reply = MLX5_GET(hca_vport_context, ctx,
948 init_type_reply);
949 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required);
950
951 ptys->proto_mask |= MLX5_PTYS_IB;
952 ptys->local_port = port;
953 err = mlx5_core_access_ptys(mdev, ptys, 0);
954 if (err)
955 goto out;
956
957 err = translate_active_width(ibdev, ptys->ib_link_width_oper,
958 &props->active_width);
959 if (err)
960 goto out;
961
962 props->active_speed = (u16)ptys->ib_proto_oper;
963
964 pmtu->local_port = port;
965 err = mlx5_core_access_pmtu(mdev, pmtu, 0);
966 if (err)
967 goto out;
968
969 props->max_mtu = pmtu->max_mtu;
970 props->active_mtu = pmtu->oper_mtu;
971
972 memset(&pvlc, 0, sizeof(pvlc));
973 pvlc.local_port = port;
974 err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
975 if (err)
976 goto out;
977
978 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
979 &props->max_vl_num);
980 out:
981 kvfree(rep);
982 kfree(ptys);
983 kfree(pmtu);
984 return err;
985 }
986
mlx5_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)987 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
988 struct ib_port_attr *props)
989 {
990 switch (mlx5_get_vport_access_method(ibdev)) {
991 case MLX5_VPORT_ACCESS_METHOD_MAD:
992 return mlx5_query_mad_ifc_port(ibdev, port, props);
993
994 case MLX5_VPORT_ACCESS_METHOD_HCA:
995 return mlx5_query_hca_port(ibdev, port, props);
996
997 case MLX5_VPORT_ACCESS_METHOD_NIC:
998 return mlx5_query_port_roce(ibdev, port, props);
999
1000 default:
1001 return -EINVAL;
1002 }
1003 }
1004
mlx5_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)1005 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1006 union ib_gid *gid)
1007 {
1008 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1009 struct mlx5_core_dev *mdev = dev->mdev;
1010
1011 switch (mlx5_get_vport_access_method(ibdev)) {
1012 case MLX5_VPORT_ACCESS_METHOD_MAD:
1013 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1014
1015 case MLX5_VPORT_ACCESS_METHOD_HCA:
1016 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
1017
1018 default:
1019 return -EINVAL;
1020 }
1021
1022 }
1023
mlx5_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)1024 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1025 u16 *pkey)
1026 {
1027 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1028 struct mlx5_core_dev *mdev = dev->mdev;
1029
1030 switch (mlx5_get_vport_access_method(ibdev)) {
1031 case MLX5_VPORT_ACCESS_METHOD_MAD:
1032 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1033
1034 case MLX5_VPORT_ACCESS_METHOD_HCA:
1035 case MLX5_VPORT_ACCESS_METHOD_NIC:
1036 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1037 pkey);
1038 default:
1039 return -EINVAL;
1040 }
1041 }
1042
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)1043 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1044 struct ib_device_modify *props)
1045 {
1046 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1047 struct mlx5_reg_node_desc in;
1048 struct mlx5_reg_node_desc out;
1049 int err;
1050
1051 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1052 return -EOPNOTSUPP;
1053
1054 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1055 return 0;
1056
1057 /*
1058 * If possible, pass node desc to FW, so it can generate
1059 * a 144 trap. If cmd fails, just ignore.
1060 */
1061 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1062 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1063 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1064 if (err)
1065 return err;
1066
1067 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1068
1069 return err;
1070 }
1071
mlx5_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)1072 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1073 struct ib_port_modify *props)
1074 {
1075 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1076 struct ib_port_attr attr;
1077 u32 tmp;
1078 int err;
1079
1080 /*
1081 * CM layer calls ib_modify_port() regardless of the link
1082 * layer. For Ethernet ports, qkey violation and Port
1083 * capabilities are meaningless.
1084 */
1085 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET)
1086 return 0;
1087
1088 mutex_lock(&dev->cap_mask_mutex);
1089
1090 err = mlx5_ib_query_port(ibdev, port, &attr);
1091 if (err)
1092 goto out;
1093
1094 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1095 ~props->clr_port_cap_mask;
1096
1097 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1098
1099 out:
1100 mutex_unlock(&dev->cap_mask_mutex);
1101 return err;
1102 }
1103
print_lib_caps(struct mlx5_ib_dev * dev,u64 caps)1104 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1105 {
1106 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1107 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1108 }
1109
calc_dynamic_bfregs(int uars_per_sys_page)1110 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1111 {
1112 /* Large page with non 4k uar support might limit the dynamic size */
1113 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1114 return MLX5_MIN_DYN_BFREGS;
1115
1116 return MLX5_MAX_DYN_BFREGS;
1117 }
1118
calc_total_bfregs(struct mlx5_ib_dev * dev,bool lib_uar_4k,struct mlx5_ib_alloc_ucontext_req_v2 * req,struct mlx5_bfreg_info * bfregi)1119 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1120 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1121 struct mlx5_bfreg_info *bfregi)
1122 {
1123 int uars_per_sys_page;
1124 int bfregs_per_sys_page;
1125 int ref_bfregs = req->total_num_bfregs;
1126
1127 if (req->total_num_bfregs == 0)
1128 return -EINVAL;
1129
1130 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1131 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1132
1133 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1134 return -ENOMEM;
1135
1136 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1137 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1138 /* This holds the required static allocation asked by the user */
1139 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1140 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1141 return -EINVAL;
1142
1143 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1144 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1145 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1146 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1147
1148 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1149 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1150 lib_uar_4k ? "yes" : "no", ref_bfregs,
1151 req->total_num_bfregs, bfregi->total_num_bfregs,
1152 bfregi->num_sys_pages);
1153
1154 return 0;
1155 }
1156
allocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1157 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1158 {
1159 struct mlx5_bfreg_info *bfregi;
1160 int err;
1161 int i;
1162
1163 bfregi = &context->bfregi;
1164 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1165 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1166 if (err)
1167 goto error;
1168
1169 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1170 }
1171
1172 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1173 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1174
1175 return 0;
1176
1177 error:
1178 for (--i; i >= 0; i--)
1179 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1180 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1181
1182 return err;
1183 }
1184
deallocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1185 static void deallocate_uars(struct mlx5_ib_dev *dev,
1186 struct mlx5_ib_ucontext *context)
1187 {
1188 struct mlx5_bfreg_info *bfregi;
1189 int i;
1190
1191 bfregi = &context->bfregi;
1192 for (i = 0; i < bfregi->num_sys_pages; i++)
1193 if (i < bfregi->num_static_sys_pages ||
1194 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1195 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1196 }
1197
mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev * dev,u32 * tdn,u16 uid)1198 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1199 u16 uid)
1200 {
1201 int err;
1202
1203 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1204 return 0;
1205
1206 err = mlx5_alloc_transport_domain(dev->mdev, tdn, uid);
1207 if (err)
1208 return err;
1209
1210 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1211 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1212 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1213 return 0;
1214
1215 mutex_lock(&dev->lb_mutex);
1216 dev->user_td++;
1217
1218 if (dev->user_td == 2)
1219 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1220
1221 mutex_unlock(&dev->lb_mutex);
1222
1223 if (err != 0)
1224 mlx5_dealloc_transport_domain(dev->mdev, *tdn, uid);
1225 return err;
1226 }
1227
mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev * dev,u32 tdn,u16 uid)1228 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1229 u16 uid)
1230 {
1231 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1232 return;
1233
1234 mlx5_dealloc_transport_domain(dev->mdev, tdn, uid);
1235
1236 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1237 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1238 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1239 return;
1240
1241 mutex_lock(&dev->lb_mutex);
1242 dev->user_td--;
1243
1244 if (dev->user_td < 2)
1245 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1246
1247 mutex_unlock(&dev->lb_mutex);
1248 }
1249
mlx5_ib_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)1250 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1251 struct ib_udata *udata)
1252 {
1253 struct ib_device *ibdev = uctx->device;
1254 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1255 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1256 struct mlx5_ib_alloc_ucontext_resp resp = {};
1257 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1258 struct mlx5_bfreg_info *bfregi;
1259 int ver;
1260 int err;
1261 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1262 max_cqe_version);
1263 bool lib_uar_4k;
1264 bool lib_uar_dyn;
1265
1266 if (!dev->ib_active)
1267 return -EAGAIN;
1268
1269 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1270 ver = 0;
1271 else if (udata->inlen >= min_req_v2)
1272 ver = 2;
1273 else
1274 return -EINVAL;
1275
1276 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1277 if (err)
1278 return err;
1279
1280 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1281 return -EOPNOTSUPP;
1282
1283 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1284 return -EOPNOTSUPP;
1285
1286 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1287 MLX5_NON_FP_BFREGS_PER_UAR);
1288 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1289 return -EINVAL;
1290
1291 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1292 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1293 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1294 resp.cache_line_size = cache_line_size();
1295 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1296 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1297 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1298 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1299 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1300 resp.cqe_version = min_t(__u8,
1301 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1302 req.max_cqe_version);
1303 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1304 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1305 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1306 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1307 resp.response_length = min(offsetof(typeof(resp), response_length) +
1308 sizeof(resp.response_length), udata->outlen);
1309
1310 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1311 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1312 bfregi = &context->bfregi;
1313
1314 if (lib_uar_dyn) {
1315 bfregi->lib_uar_dyn = lib_uar_dyn;
1316 goto uar_done;
1317 }
1318
1319 /* updates req->total_num_bfregs */
1320 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1321 if (err)
1322 goto out_ctx;
1323
1324 mutex_init(&bfregi->lock);
1325 bfregi->lib_uar_4k = lib_uar_4k;
1326 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1327 GFP_KERNEL);
1328 if (!bfregi->count) {
1329 err = -ENOMEM;
1330 goto out_ctx;
1331 }
1332
1333 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1334 sizeof(*bfregi->sys_pages),
1335 GFP_KERNEL);
1336 if (!bfregi->sys_pages) {
1337 err = -ENOMEM;
1338 goto out_count;
1339 }
1340
1341 err = allocate_uars(dev, context);
1342 if (err)
1343 goto out_sys_pages;
1344
1345 uar_done:
1346 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1347 err = mlx5_ib_devx_create(dev, true);
1348 if (err < 0)
1349 goto out_uars;
1350 context->devx_uid = err;
1351 }
1352
1353 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1354 context->devx_uid);
1355 if (err)
1356 goto out_devx;
1357
1358 INIT_LIST_HEAD(&context->db_page_list);
1359 mutex_init(&context->db_page_mutex);
1360
1361 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs;
1362 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1363
1364 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1365 resp.response_length += sizeof(resp.cqe_version);
1366
1367 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1368 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1369 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1370 resp.response_length += sizeof(resp.cmds_supp_uhw);
1371 }
1372
1373 /*
1374 * We don't want to expose information from the PCI bar that is located
1375 * after 4096 bytes, so if the arch only supports larger pages, let's
1376 * pretend we don't support reading the HCA's core clock. This is also
1377 * forced by mmap function.
1378 */
1379 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
1380 if (PAGE_SIZE <= 4096) {
1381 resp.comp_mask |=
1382 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1383 resp.hca_core_clock_offset =
1384 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1385 }
1386 resp.response_length += sizeof(resp.hca_core_clock_offset);
1387 }
1388
1389 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
1390 resp.response_length += sizeof(resp.log_uar_size);
1391
1392 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
1393 resp.response_length += sizeof(resp.num_uars_per_page);
1394
1395 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
1396 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1397 resp.response_length += sizeof(resp.num_dyn_bfregs);
1398 }
1399
1400 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1401 if (err)
1402 goto out_mdev;
1403
1404 bfregi->ver = ver;
1405 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1406 context->cqe_version = resp.cqe_version;
1407 context->lib_caps = req.lib_caps;
1408 print_lib_caps(dev, context->lib_caps);
1409
1410 return 0;
1411
1412 out_mdev:
1413 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1414 out_devx:
1415 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1416 mlx5_ib_devx_destroy(dev, context->devx_uid);
1417
1418 out_uars:
1419 deallocate_uars(dev, context);
1420
1421 out_sys_pages:
1422 kfree(bfregi->sys_pages);
1423
1424 out_count:
1425 kfree(bfregi->count);
1426
1427 out_ctx:
1428 return err;
1429 }
1430
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1431 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1432 {
1433 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1434 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1435 struct mlx5_bfreg_info *bfregi;
1436
1437 bfregi = &context->bfregi;
1438 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1439
1440 if (context->devx_uid)
1441 mlx5_ib_devx_destroy(dev, context->devx_uid);
1442
1443 deallocate_uars(dev, context);
1444 kfree(bfregi->sys_pages);
1445 kfree(bfregi->count);
1446 }
1447
uar_index2pfn(struct mlx5_ib_dev * dev,int uar_idx)1448 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1449 int uar_idx)
1450 {
1451 int fw_uars_per_page;
1452
1453 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1454
1455 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1456 }
1457
get_command(unsigned long offset)1458 static int get_command(unsigned long offset)
1459 {
1460 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1461 }
1462
get_arg(unsigned long offset)1463 static int get_arg(unsigned long offset)
1464 {
1465 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1466 }
1467
get_index(unsigned long offset)1468 static int get_index(unsigned long offset)
1469 {
1470 return get_arg(offset);
1471 }
1472
1473 /* Index resides in an extra byte to enable larger values than 255 */
get_extended_index(unsigned long offset)1474 static int get_extended_index(unsigned long offset)
1475 {
1476 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1477 }
1478
1479
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1480 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1481 {
1482 }
1483
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)1484 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1485 {
1486 switch (cmd) {
1487 case MLX5_IB_MMAP_WC_PAGE:
1488 return "WC";
1489 case MLX5_IB_MMAP_REGULAR_PAGE:
1490 return "best effort WC";
1491 case MLX5_IB_MMAP_NC_PAGE:
1492 return "NC";
1493 default:
1494 return NULL;
1495 }
1496 }
1497
mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)1498 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1499 struct vm_area_struct *vma,
1500 struct mlx5_ib_ucontext *context)
1501 {
1502 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
1503 !(vma->vm_flags & VM_SHARED))
1504 return -EINVAL;
1505
1506 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1507 return -EOPNOTSUPP;
1508
1509 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1510 return -EPERM;
1511
1512 return -EOPNOTSUPP;
1513 }
1514
mlx5_cmd_uar_alloc(struct mlx5_core_dev * dev,u32 * uarn,u16 uid)1515 static int mlx5_cmd_uar_alloc(struct mlx5_core_dev *dev, u32 *uarn, u16 uid)
1516 {
1517 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {};
1518 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {};
1519 int err;
1520
1521 MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR);
1522 MLX5_SET(alloc_uar_in, in, uid, uid);
1523 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
1524 if (err)
1525 return err;
1526
1527 *uarn = MLX5_GET(alloc_uar_out, out, uar);
1528 return 0;
1529 }
1530
mlx5_cmd_uar_dealloc(struct mlx5_core_dev * dev,u32 uarn,u16 uid)1531 static int mlx5_cmd_uar_dealloc(struct mlx5_core_dev *dev, u32 uarn, u16 uid)
1532 {
1533 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {};
1534 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {};
1535
1536 MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR);
1537 MLX5_SET(dealloc_uar_in, in, uar, uarn);
1538 MLX5_SET(dealloc_uar_in, in, uid, uid);
1539 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
1540 }
1541
mlx5_ib_mmap_free(struct rdma_user_mmap_entry * entry)1542 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
1543 {
1544 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
1545 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
1546 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
1547
1548 switch (mentry->mmap_flag) {
1549 case MLX5_IB_MMAP_TYPE_UAR_WC:
1550 case MLX5_IB_MMAP_TYPE_UAR_NC:
1551 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
1552 context->devx_uid);
1553 kfree(mentry);
1554 break;
1555 default:
1556 WARN_ON(true);
1557 }
1558 }
1559
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)1560 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1561 struct vm_area_struct *vma,
1562 struct mlx5_ib_ucontext *context)
1563 {
1564 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1565 int err;
1566 unsigned long idx;
1567 phys_addr_t pfn;
1568 pgprot_t prot;
1569 u32 bfreg_dyn_idx = 0;
1570 u32 uar_index;
1571 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1572 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1573 bfregi->num_static_sys_pages;
1574
1575 if (bfregi->lib_uar_dyn)
1576 return -EINVAL;
1577
1578 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1579 return -EINVAL;
1580
1581 if (dyn_uar)
1582 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
1583 else
1584 idx = get_index(vma->vm_pgoff);
1585
1586 if (idx >= max_valid_idx) {
1587 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
1588 idx, max_valid_idx);
1589 return -EINVAL;
1590 }
1591
1592 switch (cmd) {
1593 case MLX5_IB_MMAP_WC_PAGE:
1594 case MLX5_IB_MMAP_ALLOC_WC:
1595 case MLX5_IB_MMAP_REGULAR_PAGE:
1596 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1597 prot = pgprot_writecombine(vma->vm_page_prot);
1598 break;
1599 case MLX5_IB_MMAP_NC_PAGE:
1600 prot = pgprot_noncached(vma->vm_page_prot);
1601 break;
1602 default:
1603 return -EINVAL;
1604 }
1605
1606 if (dyn_uar) {
1607 int uars_per_page;
1608
1609 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1610 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
1611 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
1612 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
1613 bfreg_dyn_idx, bfregi->total_num_bfregs);
1614 return -EINVAL;
1615 }
1616
1617 mutex_lock(&bfregi->lock);
1618 /* Fail if uar already allocated, first bfreg index of each
1619 * page holds its count.
1620 */
1621 if (bfregi->count[bfreg_dyn_idx]) {
1622 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
1623 mutex_unlock(&bfregi->lock);
1624 return -EINVAL;
1625 }
1626
1627 bfregi->count[bfreg_dyn_idx]++;
1628 mutex_unlock(&bfregi->lock);
1629
1630 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
1631 if (err) {
1632 mlx5_ib_warn(dev, "UAR alloc failed\n");
1633 goto free_bfreg;
1634 }
1635 } else {
1636 uar_index = bfregi->sys_pages[idx];
1637 }
1638
1639 pfn = uar_index2pfn(dev, uar_index);
1640 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1641
1642 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
1643 prot, NULL);
1644 if (err) {
1645 mlx5_ib_err(dev,
1646 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
1647 err, mmap_cmd2str(cmd));
1648 goto err;
1649 }
1650
1651 if (dyn_uar)
1652 bfregi->sys_pages[idx] = uar_index;
1653 return 0;
1654
1655 err:
1656 if (!dyn_uar)
1657 return err;
1658
1659 mlx5_cmd_free_uar(dev->mdev, idx);
1660
1661 free_bfreg:
1662 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
1663
1664 return err;
1665 }
1666
mlx5_vma_to_pgoff(struct vm_area_struct * vma)1667 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
1668 {
1669 unsigned long idx;
1670 u8 command;
1671
1672 command = get_command(vma->vm_pgoff);
1673 idx = get_extended_index(vma->vm_pgoff);
1674
1675 return (command << 16 | idx);
1676 }
1677
mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry * entry)1678 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
1679 {
1680 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
1681 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
1682
1683 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
1684 (index & 0xFF)) << PAGE_SHIFT;
1685 }
1686
mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext * c,struct mlx5_user_mmap_entry * entry,size_t length)1687 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
1688 struct mlx5_user_mmap_entry *entry,
1689 size_t length)
1690 {
1691 return rdma_user_mmap_entry_insert_range(
1692 &c->ibucontext, &entry->rdma_entry, length,
1693 (MLX5_IB_MMAP_OFFSET_START << 16),
1694 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
1695 }
1696
mlx5_ib_mmap_offset(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct ib_ucontext * ucontext)1697 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
1698 struct vm_area_struct *vma,
1699 struct ib_ucontext *ucontext)
1700 {
1701 struct mlx5_user_mmap_entry *mentry;
1702 struct rdma_user_mmap_entry *entry;
1703 unsigned long pgoff;
1704 pgprot_t prot;
1705 phys_addr_t pfn;
1706 int ret;
1707
1708 pgoff = mlx5_vma_to_pgoff(vma);
1709 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
1710 if (!entry)
1711 return -EINVAL;
1712
1713 mentry = to_mmmap(entry);
1714 pfn = (mentry->address >> PAGE_SHIFT);
1715 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
1716 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
1717 prot = pgprot_noncached(vma->vm_page_prot);
1718 else
1719 prot = pgprot_writecombine(vma->vm_page_prot);
1720 ret = rdma_user_mmap_io(ucontext, vma, pfn,
1721 entry->npages * PAGE_SIZE,
1722 prot,
1723 entry);
1724 rdma_user_mmap_entry_put(&mentry->rdma_entry);
1725 return ret;
1726 }
1727
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)1728 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1729 {
1730 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1731 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1732 unsigned long command;
1733 phys_addr_t pfn;
1734
1735 command = get_command(vma->vm_pgoff);
1736 switch (command) {
1737 case MLX5_IB_MMAP_WC_PAGE:
1738 case MLX5_IB_MMAP_ALLOC_WC:
1739 if (!dev->wc_support)
1740 return -EPERM;
1741 /* FALLTHROUGH */
1742 case MLX5_IB_MMAP_NC_PAGE:
1743 case MLX5_IB_MMAP_REGULAR_PAGE:
1744 return uar_mmap(dev, command, vma, context);
1745
1746 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1747 return -ENOSYS;
1748
1749 case MLX5_IB_MMAP_CORE_CLOCK:
1750 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1751 return -EINVAL;
1752
1753 if (vma->vm_flags & VM_WRITE)
1754 return -EPERM;
1755
1756 /* Don't expose to user-space information it shouldn't have */
1757 if (PAGE_SIZE > 4096)
1758 return -EOPNOTSUPP;
1759
1760 pfn = (dev->mdev->iseg_base +
1761 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1762 PAGE_SHIFT;
1763 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
1764 PAGE_SIZE,
1765 pgprot_noncached(vma->vm_page_prot),
1766 NULL);
1767 case MLX5_IB_MMAP_CLOCK_INFO:
1768 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
1769
1770 default:
1771 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
1772 }
1773
1774 return 0;
1775 }
1776
mlx5_ib_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)1777 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
1778 {
1779 struct mlx5_ib_pd *pd = to_mpd(ibpd);
1780 struct ib_device *ibdev = ibpd->device;
1781 struct mlx5_ib_alloc_pd_resp resp;
1782 int err;
1783 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1784 udata, struct mlx5_ib_ucontext, ibucontext);
1785 u16 uid = context ? context->devx_uid : 0;
1786
1787 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn, uid);
1788 if (err)
1789 return (err);
1790
1791 pd->uid = uid;
1792 if (udata) {
1793 resp.pdn = pd->pdn;
1794 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1795 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
1796 return -EFAULT;
1797 }
1798 }
1799
1800 return 0;
1801 }
1802
mlx5_ib_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)1803 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
1804 {
1805 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1806 struct mlx5_ib_pd *mpd = to_mpd(pd);
1807
1808 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
1809 }
1810
1811 enum {
1812 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1813 MATCH_CRITERIA_ENABLE_MISC_BIT,
1814 MATCH_CRITERIA_ENABLE_INNER_BIT
1815 };
1816
1817 #define HEADER_IS_ZERO(match_criteria, headers) \
1818 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1819 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1820
get_match_criteria_enable(u32 * match_criteria)1821 static u8 get_match_criteria_enable(u32 *match_criteria)
1822 {
1823 u8 match_criteria_enable;
1824
1825 match_criteria_enable =
1826 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1827 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1828 match_criteria_enable |=
1829 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1830 MATCH_CRITERIA_ENABLE_MISC_BIT;
1831 match_criteria_enable |=
1832 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1833 MATCH_CRITERIA_ENABLE_INNER_BIT;
1834
1835 return match_criteria_enable;
1836 }
1837
set_proto(void * outer_c,void * outer_v,u8 mask,u8 val)1838 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1839 {
1840 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1841 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1842 }
1843
set_tos(void * outer_c,void * outer_v,u8 mask,u8 val)1844 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1845 {
1846 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1847 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1848 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1849 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1850 }
1851
1852 #define LAST_ETH_FIELD vlan_tag
1853 #define LAST_IB_FIELD sl
1854 #define LAST_IPV4_FIELD tos
1855 #define LAST_IPV6_FIELD traffic_class
1856 #define LAST_TCP_UDP_FIELD src_port
1857
1858 /* Field is the last supported field */
1859 #define FIELDS_NOT_SUPPORTED(filter, field)\
1860 memchr_inv((void *)&filter.field +\
1861 sizeof(filter.field), 0,\
1862 sizeof(filter) -\
1863 offsetof(typeof(filter), field) -\
1864 sizeof(filter.field))
1865
parse_flow_attr(u32 * match_c,u32 * match_v,const union ib_flow_spec * ib_spec)1866 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1867 const union ib_flow_spec *ib_spec)
1868 {
1869 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1870 outer_headers);
1871 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1872 outer_headers);
1873 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1874 misc_parameters);
1875 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1876 misc_parameters);
1877
1878 switch (ib_spec->type) {
1879 case IB_FLOW_SPEC_ETH:
1880 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1881 return -ENOTSUPP;
1882
1883 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1884 dmac_47_16),
1885 ib_spec->eth.mask.dst_mac);
1886 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1887 dmac_47_16),
1888 ib_spec->eth.val.dst_mac);
1889
1890 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1891 smac_47_16),
1892 ib_spec->eth.mask.src_mac);
1893 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1894 smac_47_16),
1895 ib_spec->eth.val.src_mac);
1896
1897 if (ib_spec->eth.mask.vlan_tag) {
1898 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1899 cvlan_tag, 1);
1900 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1901 cvlan_tag, 1);
1902
1903 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1904 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1905 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1906 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1907
1908 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1909 first_cfi,
1910 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1911 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1912 first_cfi,
1913 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1914
1915 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1916 first_prio,
1917 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1918 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1919 first_prio,
1920 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1921 }
1922 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1923 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1924 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1925 ethertype, ntohs(ib_spec->eth.val.ether_type));
1926 break;
1927 case IB_FLOW_SPEC_IPV4:
1928 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1929 return -ENOTSUPP;
1930
1931 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1932 ethertype, 0xffff);
1933 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1934 ethertype, ETH_P_IP);
1935
1936 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1937 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1938 &ib_spec->ipv4.mask.src_ip,
1939 sizeof(ib_spec->ipv4.mask.src_ip));
1940 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1941 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1942 &ib_spec->ipv4.val.src_ip,
1943 sizeof(ib_spec->ipv4.val.src_ip));
1944 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1945 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1946 &ib_spec->ipv4.mask.dst_ip,
1947 sizeof(ib_spec->ipv4.mask.dst_ip));
1948 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1949 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1950 &ib_spec->ipv4.val.dst_ip,
1951 sizeof(ib_spec->ipv4.val.dst_ip));
1952
1953 set_tos(outer_headers_c, outer_headers_v,
1954 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1955
1956 set_proto(outer_headers_c, outer_headers_v,
1957 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1958 break;
1959 case IB_FLOW_SPEC_IPV6:
1960 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1961 return -ENOTSUPP;
1962
1963 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1964 ethertype, 0xffff);
1965 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1966 ethertype, ETH_P_IPV6);
1967
1968 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1969 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1970 &ib_spec->ipv6.mask.src_ip,
1971 sizeof(ib_spec->ipv6.mask.src_ip));
1972 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1973 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1974 &ib_spec->ipv6.val.src_ip,
1975 sizeof(ib_spec->ipv6.val.src_ip));
1976 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1977 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1978 &ib_spec->ipv6.mask.dst_ip,
1979 sizeof(ib_spec->ipv6.mask.dst_ip));
1980 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1981 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1982 &ib_spec->ipv6.val.dst_ip,
1983 sizeof(ib_spec->ipv6.val.dst_ip));
1984
1985 set_tos(outer_headers_c, outer_headers_v,
1986 ib_spec->ipv6.mask.traffic_class,
1987 ib_spec->ipv6.val.traffic_class);
1988
1989 set_proto(outer_headers_c, outer_headers_v,
1990 ib_spec->ipv6.mask.next_hdr,
1991 ib_spec->ipv6.val.next_hdr);
1992
1993 MLX5_SET(fte_match_set_misc, misc_params_c,
1994 outer_ipv6_flow_label,
1995 ntohl(ib_spec->ipv6.mask.flow_label));
1996 MLX5_SET(fte_match_set_misc, misc_params_v,
1997 outer_ipv6_flow_label,
1998 ntohl(ib_spec->ipv6.val.flow_label));
1999 break;
2000 case IB_FLOW_SPEC_TCP:
2001 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2002 LAST_TCP_UDP_FIELD))
2003 return -ENOTSUPP;
2004
2005 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
2006 0xff);
2007 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
2008 IPPROTO_TCP);
2009
2010 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
2011 ntohs(ib_spec->tcp_udp.mask.src_port));
2012 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
2013 ntohs(ib_spec->tcp_udp.val.src_port));
2014
2015 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
2016 ntohs(ib_spec->tcp_udp.mask.dst_port));
2017 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
2018 ntohs(ib_spec->tcp_udp.val.dst_port));
2019 break;
2020 case IB_FLOW_SPEC_UDP:
2021 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2022 LAST_TCP_UDP_FIELD))
2023 return -ENOTSUPP;
2024
2025 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
2026 0xff);
2027 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
2028 IPPROTO_UDP);
2029
2030 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
2031 ntohs(ib_spec->tcp_udp.mask.src_port));
2032 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
2033 ntohs(ib_spec->tcp_udp.val.src_port));
2034
2035 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
2036 ntohs(ib_spec->tcp_udp.mask.dst_port));
2037 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
2038 ntohs(ib_spec->tcp_udp.val.dst_port));
2039 break;
2040 default:
2041 return -EINVAL;
2042 }
2043
2044 return 0;
2045 }
2046
2047 /* If a flow could catch both multicast and unicast packets,
2048 * it won't fall into the multicast flow steering table and this rule
2049 * could steal other multicast packets.
2050 */
flow_is_multicast_only(struct ib_flow_attr * ib_attr)2051 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2052 {
2053 struct ib_flow_spec_eth *eth_spec;
2054
2055 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2056 ib_attr->size < sizeof(struct ib_flow_attr) +
2057 sizeof(struct ib_flow_spec_eth) ||
2058 ib_attr->num_of_specs < 1)
2059 return false;
2060
2061 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2062 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2063 eth_spec->size != sizeof(*eth_spec))
2064 return false;
2065
2066 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2067 is_multicast_ether_addr(eth_spec->val.dst_mac);
2068 }
2069
is_valid_attr(const struct ib_flow_attr * flow_attr)2070 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
2071 {
2072 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2073 bool has_ipv4_spec = false;
2074 bool eth_type_ipv4 = true;
2075 unsigned int spec_index;
2076
2077 /* Validate that ethertype is correct */
2078 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2079 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
2080 ib_spec->eth.mask.ether_type) {
2081 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
2082 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
2083 eth_type_ipv4 = false;
2084 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
2085 has_ipv4_spec = true;
2086 }
2087 ib_spec = (void *)ib_spec + ib_spec->size;
2088 }
2089 return !has_ipv4_spec || eth_type_ipv4;
2090 }
2091
put_flow_table(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * prio,bool ft_added)2092 static void put_flow_table(struct mlx5_ib_dev *dev,
2093 struct mlx5_ib_flow_prio *prio, bool ft_added)
2094 {
2095 prio->refcount -= !!ft_added;
2096 if (!prio->refcount) {
2097 mlx5_destroy_flow_table(prio->flow_table);
2098 prio->flow_table = NULL;
2099 }
2100 }
2101
mlx5_ib_destroy_flow(struct ib_flow * flow_id)2102 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2103 {
2104 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2105 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2106 struct mlx5_ib_flow_handler,
2107 ibflow);
2108 struct mlx5_ib_flow_handler *iter, *tmp;
2109
2110 mutex_lock(&dev->flow_db.lock);
2111
2112 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2113 mlx5_del_flow_rules(&iter->rule);
2114 put_flow_table(dev, iter->prio, true);
2115 list_del(&iter->list);
2116 kfree(iter);
2117 }
2118
2119 mlx5_del_flow_rules(&handler->rule);
2120 put_flow_table(dev, handler->prio, true);
2121 mutex_unlock(&dev->flow_db.lock);
2122
2123 kfree(handler);
2124
2125 return 0;
2126 }
2127
ib_prio_to_core_prio(unsigned int priority,bool dont_trap)2128 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2129 {
2130 priority *= 2;
2131 if (!dont_trap)
2132 priority++;
2133 return priority;
2134 }
2135
2136 enum flow_table_type {
2137 MLX5_IB_FT_RX,
2138 MLX5_IB_FT_TX
2139 };
2140
2141 #define MLX5_FS_MAX_TYPES 10
2142 #define MLX5_FS_MAX_ENTRIES 32000UL
get_flow_table(struct mlx5_ib_dev * dev,struct ib_flow_attr * flow_attr,enum flow_table_type ft_type)2143 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2144 struct ib_flow_attr *flow_attr,
2145 enum flow_table_type ft_type)
2146 {
2147 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2148 struct mlx5_flow_table_attr ft_attr = {};
2149 struct mlx5_flow_namespace *ns = NULL;
2150 struct mlx5_ib_flow_prio *prio;
2151 struct mlx5_flow_table *ft;
2152 int num_entries;
2153 int num_groups;
2154 int priority;
2155 int err = 0;
2156
2157 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2158 if (flow_is_multicast_only(flow_attr) &&
2159 !dont_trap)
2160 priority = MLX5_IB_FLOW_MCAST_PRIO;
2161 else
2162 priority = ib_prio_to_core_prio(flow_attr->priority,
2163 dont_trap);
2164 ns = mlx5_get_flow_namespace(dev->mdev,
2165 MLX5_FLOW_NAMESPACE_BYPASS);
2166 num_entries = MLX5_FS_MAX_ENTRIES;
2167 num_groups = MLX5_FS_MAX_TYPES;
2168 prio = &dev->flow_db.prios[priority];
2169 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2170 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2171 ns = mlx5_get_flow_namespace(dev->mdev,
2172 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2173 build_leftovers_ft_param("bypass", &priority,
2174 &num_entries,
2175 &num_groups);
2176 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2177 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2178 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2179 allow_sniffer_and_nic_rx_shared_tir))
2180 return ERR_PTR(-ENOTSUPP);
2181
2182 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2183 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2184 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2185
2186 prio = &dev->flow_db.sniffer[ft_type];
2187 priority = 0;
2188 num_entries = 1;
2189 num_groups = 1;
2190 }
2191
2192 if (!ns)
2193 return ERR_PTR(-ENOTSUPP);
2194
2195 ft = prio->flow_table;
2196 if (!ft) {
2197 ft_attr.prio = priority;
2198 ft_attr.max_fte = num_entries;
2199 ft_attr.autogroup.max_num_groups = num_groups;
2200
2201 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
2202
2203 if (!IS_ERR(ft)) {
2204 prio->refcount = 0;
2205 prio->flow_table = ft;
2206 } else {
2207 err = PTR_ERR(ft);
2208 }
2209 }
2210
2211 return err ? ERR_PTR(err) : prio;
2212 }
2213
create_flow_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,const struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2214 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2215 struct mlx5_ib_flow_prio *ft_prio,
2216 const struct ib_flow_attr *flow_attr,
2217 struct mlx5_flow_destination *dst)
2218 {
2219 struct mlx5_flow_table *ft = ft_prio->flow_table;
2220 struct mlx5_ib_flow_handler *handler;
2221 struct mlx5_flow_spec *spec;
2222 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2223 unsigned int spec_index;
2224 struct mlx5_flow_act flow_act = {};
2225
2226 u32 action;
2227 int err = 0;
2228
2229 if (!is_valid_attr(flow_attr))
2230 return ERR_PTR(-EINVAL);
2231
2232 spec = mlx5_vzalloc(sizeof(*spec));
2233 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2234 if (!handler || !spec) {
2235 err = -ENOMEM;
2236 goto free;
2237 }
2238
2239 spec->flow_context.flags = FLOW_CONTEXT_HAS_TAG;
2240 spec->flow_context.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2241
2242 INIT_LIST_HEAD(&handler->list);
2243
2244 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2245 err = parse_flow_attr(spec->match_criteria,
2246 spec->match_value, ib_flow);
2247 if (err < 0)
2248 goto free;
2249
2250 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2251 }
2252
2253 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2254 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 0;
2255 flow_act.action = action;
2256 handler->rule = mlx5_add_flow_rules(ft, spec, &flow_act, dst, 1);
2257
2258 if (IS_ERR(handler->rule)) {
2259 err = PTR_ERR(handler->rule);
2260 goto free;
2261 }
2262
2263 ft_prio->refcount++;
2264 handler->prio = ft_prio;
2265
2266 ft_prio->flow_table = ft;
2267 free:
2268 if (err)
2269 kfree(handler);
2270 kvfree(spec);
2271 return err ? ERR_PTR(err) : handler;
2272 }
2273
create_dont_trap_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2274 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2275 struct mlx5_ib_flow_prio *ft_prio,
2276 struct ib_flow_attr *flow_attr,
2277 struct mlx5_flow_destination *dst)
2278 {
2279 struct mlx5_ib_flow_handler *handler_dst = NULL;
2280 struct mlx5_ib_flow_handler *handler = NULL;
2281
2282 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2283 if (!IS_ERR(handler)) {
2284 handler_dst = create_flow_rule(dev, ft_prio,
2285 flow_attr, dst);
2286 if (IS_ERR(handler_dst)) {
2287 mlx5_del_flow_rules(&handler->rule);
2288 ft_prio->refcount--;
2289 kfree(handler);
2290 handler = handler_dst;
2291 } else {
2292 list_add(&handler_dst->list, &handler->list);
2293 }
2294 }
2295
2296 return handler;
2297 }
2298 enum {
2299 LEFTOVERS_MC,
2300 LEFTOVERS_UC,
2301 };
2302
create_leftovers_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2303 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2304 struct mlx5_ib_flow_prio *ft_prio,
2305 struct ib_flow_attr *flow_attr,
2306 struct mlx5_flow_destination *dst)
2307 {
2308 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2309 struct mlx5_ib_flow_handler *handler = NULL;
2310
2311 static struct {
2312 struct ib_flow_attr flow_attr;
2313 struct ib_flow_spec_eth eth_flow;
2314 } leftovers_specs[] = {
2315 [LEFTOVERS_MC] = {
2316 .flow_attr = {
2317 .num_of_specs = 1,
2318 .size = sizeof(leftovers_specs[0])
2319 },
2320 .eth_flow = {
2321 .type = IB_FLOW_SPEC_ETH,
2322 .size = sizeof(struct ib_flow_spec_eth),
2323 .mask = {.dst_mac = {0x1} },
2324 .val = {.dst_mac = {0x1} }
2325 }
2326 },
2327 [LEFTOVERS_UC] = {
2328 .flow_attr = {
2329 .num_of_specs = 1,
2330 .size = sizeof(leftovers_specs[0])
2331 },
2332 .eth_flow = {
2333 .type = IB_FLOW_SPEC_ETH,
2334 .size = sizeof(struct ib_flow_spec_eth),
2335 .mask = {.dst_mac = {0x1} },
2336 .val = {.dst_mac = {} }
2337 }
2338 }
2339 };
2340
2341 handler = create_flow_rule(dev, ft_prio,
2342 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2343 dst);
2344 if (!IS_ERR(handler) &&
2345 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2346 handler_ucast = create_flow_rule(dev, ft_prio,
2347 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2348 dst);
2349 if (IS_ERR(handler_ucast)) {
2350 mlx5_del_flow_rules(&handler->rule);
2351 ft_prio->refcount--;
2352 kfree(handler);
2353 handler = handler_ucast;
2354 } else {
2355 list_add(&handler_ucast->list, &handler->list);
2356 }
2357 }
2358
2359 return handler;
2360 }
2361
create_sniffer_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_rx,struct mlx5_ib_flow_prio * ft_tx,struct mlx5_flow_destination * dst)2362 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2363 struct mlx5_ib_flow_prio *ft_rx,
2364 struct mlx5_ib_flow_prio *ft_tx,
2365 struct mlx5_flow_destination *dst)
2366 {
2367 struct mlx5_ib_flow_handler *handler_rx;
2368 struct mlx5_ib_flow_handler *handler_tx;
2369 int err;
2370 static const struct ib_flow_attr flow_attr = {
2371 .num_of_specs = 0,
2372 .type = IB_FLOW_ATTR_SNIFFER,
2373 .size = sizeof(flow_attr)
2374 };
2375
2376 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2377 if (IS_ERR(handler_rx)) {
2378 err = PTR_ERR(handler_rx);
2379 goto err;
2380 }
2381
2382 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2383 if (IS_ERR(handler_tx)) {
2384 err = PTR_ERR(handler_tx);
2385 goto err_tx;
2386 }
2387
2388 list_add(&handler_tx->list, &handler_rx->list);
2389
2390 return handler_rx;
2391
2392 err_tx:
2393 mlx5_del_flow_rules(&handler_rx->rule);
2394 ft_rx->refcount--;
2395 kfree(handler_rx);
2396 err:
2397 return ERR_PTR(err);
2398 }
2399
mlx5_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain,struct ib_udata * udata)2400 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2401 struct ib_flow_attr *flow_attr,
2402 int domain,
2403 struct ib_udata *udata)
2404 {
2405 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2406 struct mlx5_ib_qp *mqp = to_mqp(qp);
2407 struct mlx5_ib_flow_handler *handler = NULL;
2408 struct mlx5_flow_destination *dst = NULL;
2409 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2410 struct mlx5_ib_flow_prio *ft_prio;
2411 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
2412 size_t min_ucmd_sz, required_ucmd_sz;
2413 int err;
2414
2415 if (udata && udata->inlen) {
2416 min_ucmd_sz = offsetofend(struct mlx5_ib_create_flow, reserved);
2417 if (udata->inlen < min_ucmd_sz)
2418 return ERR_PTR(-EOPNOTSUPP);
2419
2420 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
2421 if (err)
2422 return ERR_PTR(err);
2423
2424 /* currently supports only one counters data */
2425 if (ucmd_hdr.ncounters_data > 1)
2426 return ERR_PTR(-EINVAL);
2427
2428 required_ucmd_sz = min_ucmd_sz +
2429 sizeof(struct mlx5_ib_flow_counters_data) *
2430 ucmd_hdr.ncounters_data;
2431 if (udata->inlen > required_ucmd_sz &&
2432 !ib_is_udata_cleared(udata, required_ucmd_sz,
2433 udata->inlen - required_ucmd_sz))
2434 return ERR_PTR(-EOPNOTSUPP);
2435
2436 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
2437 if (!ucmd)
2438 return ERR_PTR(-ENOMEM);
2439
2440 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
2441 if (err)
2442 goto free_ucmd;
2443 }
2444
2445 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
2446 err = -ENOMEM;
2447 goto free_ucmd;
2448 }
2449
2450 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2451 err = -EINVAL;
2452 goto free_ucmd;
2453 }
2454
2455 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2456 if (!dst) {
2457 err = -ENOMEM;
2458 goto free_ucmd;
2459 }
2460
2461 mutex_lock(&dev->flow_db.lock);
2462
2463 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2464 if (IS_ERR(ft_prio)) {
2465 err = PTR_ERR(ft_prio);
2466 goto unlock;
2467 }
2468 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2469 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2470 if (IS_ERR(ft_prio_tx)) {
2471 err = PTR_ERR(ft_prio_tx);
2472 ft_prio_tx = NULL;
2473 goto destroy_ft;
2474 }
2475 }
2476
2477 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2478 if (mqp->flags & MLX5_IB_QP_RSS)
2479 dst->tir_num = mqp->rss_qp.tirn;
2480 else
2481 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2482
2483 switch (flow_attr->type) {
2484 case IB_FLOW_ATTR_NORMAL:
2485 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2486 err = -EOPNOTSUPP;
2487 goto destroy_ft;
2488 }
2489 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2490 handler = create_dont_trap_rule(dev, ft_prio, flow_attr, dst);
2491 } else {
2492 handler = create_flow_rule(dev, ft_prio, flow_attr, dst);
2493 }
2494 break;
2495 case IB_FLOW_ATTR_ALL_DEFAULT:
2496 case IB_FLOW_ATTR_MC_DEFAULT:
2497 handler = create_leftovers_rule(dev, ft_prio, flow_attr, dst);
2498 break;
2499 case IB_FLOW_ATTR_SNIFFER:
2500 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2501 break;
2502 default:
2503 err = -EINVAL;
2504 goto destroy_ft;
2505 }
2506
2507 if (IS_ERR(handler)) {
2508 err = PTR_ERR(handler);
2509 handler = NULL;
2510 goto destroy_ft;
2511 }
2512
2513 mutex_unlock(&dev->flow_db.lock);
2514 kfree(dst);
2515 kfree(ucmd);
2516
2517 return &handler->ibflow;
2518
2519 destroy_ft:
2520 put_flow_table(dev, ft_prio, false);
2521 if (ft_prio_tx)
2522 put_flow_table(dev, ft_prio_tx, false);
2523 unlock:
2524 mutex_unlock(&dev->flow_db.lock);
2525 kfree(dst);
2526 free_ucmd:
2527 kfree(ucmd);
2528 return ERR_PTR(err);
2529 }
2530
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2531 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2532 {
2533 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2534 int err;
2535
2536 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2537 if (err)
2538 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2539 ibqp->qp_num, gid->raw);
2540
2541 return err;
2542 }
2543
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2544 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2545 {
2546 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2547 int err;
2548
2549 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2550 if (err)
2551 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2552 ibqp->qp_num, gid->raw);
2553
2554 return err;
2555 }
2556
init_node_data(struct mlx5_ib_dev * dev)2557 static int init_node_data(struct mlx5_ib_dev *dev)
2558 {
2559 int err;
2560
2561 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2562 if (err)
2563 return err;
2564
2565 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2566 }
2567
show_fw_pages(struct device * device,struct device_attribute * attr,char * buf)2568 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2569 char *buf)
2570 {
2571 struct mlx5_ib_dev *dev =
2572 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2573
2574 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2575 }
2576
show_reg_pages(struct device * device,struct device_attribute * attr,char * buf)2577 static ssize_t show_reg_pages(struct device *device,
2578 struct device_attribute *attr, char *buf)
2579 {
2580 struct mlx5_ib_dev *dev =
2581 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2582
2583 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2584 }
2585
show_hca(struct device * device,struct device_attribute * attr,char * buf)2586 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2587 char *buf)
2588 {
2589 struct mlx5_ib_dev *dev =
2590 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2591 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2592 }
2593
show_rev(struct device * device,struct device_attribute * attr,char * buf)2594 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2595 char *buf)
2596 {
2597 struct mlx5_ib_dev *dev =
2598 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2599 return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2600 }
2601
show_board(struct device * device,struct device_attribute * attr,char * buf)2602 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2603 char *buf)
2604 {
2605 struct mlx5_ib_dev *dev =
2606 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2607 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2608 dev->mdev->board_id);
2609 }
2610
2611 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2612 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2613 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2614 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2615 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2616
2617 static struct device_attribute *mlx5_class_attributes[] = {
2618 &dev_attr_hw_rev,
2619 &dev_attr_hca_type,
2620 &dev_attr_board_id,
2621 &dev_attr_fw_pages,
2622 &dev_attr_reg_pages,
2623 };
2624
pkey_change_handler(struct work_struct * work)2625 static void pkey_change_handler(struct work_struct *work)
2626 {
2627 struct mlx5_ib_port_resources *ports =
2628 container_of(work, struct mlx5_ib_port_resources,
2629 pkey_change_work);
2630
2631 mutex_lock(&ports->devr->mutex);
2632 mlx5_ib_gsi_pkey_change(ports->gsi);
2633 mutex_unlock(&ports->devr->mutex);
2634 }
2635
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2636 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2637 {
2638 struct mlx5_ib_qp *mqp;
2639 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2640 struct mlx5_core_cq *mcq;
2641 struct list_head cq_armed_list;
2642 unsigned long flags_qp;
2643 unsigned long flags_cq;
2644 unsigned long flags;
2645
2646 INIT_LIST_HEAD(&cq_armed_list);
2647
2648 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2649 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2650 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2651 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2652 if (mqp->sq.tail != mqp->sq.head) {
2653 send_mcq = to_mcq(mqp->ibqp.send_cq);
2654 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2655 if (send_mcq->mcq.comp &&
2656 mqp->ibqp.send_cq->comp_handler) {
2657 if (!send_mcq->mcq.reset_notify_added) {
2658 send_mcq->mcq.reset_notify_added = 1;
2659 list_add_tail(&send_mcq->mcq.reset_notify,
2660 &cq_armed_list);
2661 }
2662 }
2663 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2664 }
2665 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2666 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2667 /* no handling is needed for SRQ */
2668 if (!mqp->ibqp.srq) {
2669 if (mqp->rq.tail != mqp->rq.head) {
2670 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2671 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2672 if (recv_mcq->mcq.comp &&
2673 mqp->ibqp.recv_cq->comp_handler) {
2674 if (!recv_mcq->mcq.reset_notify_added) {
2675 recv_mcq->mcq.reset_notify_added = 1;
2676 list_add_tail(&recv_mcq->mcq.reset_notify,
2677 &cq_armed_list);
2678 }
2679 }
2680 spin_unlock_irqrestore(&recv_mcq->lock,
2681 flags_cq);
2682 }
2683 }
2684 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2685 }
2686 /*At that point all inflight post send were put to be executed as of we
2687 * lock/unlock above locks Now need to arm all involved CQs.
2688 */
2689 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2690 mcq->comp(mcq, NULL);
2691 }
2692 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2693 }
2694
mlx5_ib_event(struct mlx5_core_dev * dev,void * context,enum mlx5_dev_event event,unsigned long param)2695 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2696 enum mlx5_dev_event event, unsigned long param)
2697 {
2698 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2699 struct ib_event ibev;
2700 bool fatal = false;
2701 u8 port = (u8)param;
2702
2703 switch (event) {
2704 case MLX5_DEV_EVENT_SYS_ERROR:
2705 ibev.event = IB_EVENT_DEVICE_FATAL;
2706 mlx5_ib_handle_internal_error(ibdev);
2707 fatal = true;
2708 break;
2709
2710 case MLX5_DEV_EVENT_PORT_UP:
2711 case MLX5_DEV_EVENT_PORT_DOWN:
2712 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2713 /* In RoCE, port up/down events are handled in
2714 * mlx5_netdev_event().
2715 */
2716 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2717 IB_LINK_LAYER_ETHERNET)
2718 return;
2719
2720 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2721 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2722 break;
2723
2724 case MLX5_DEV_EVENT_LID_CHANGE:
2725 ibev.event = IB_EVENT_LID_CHANGE;
2726 break;
2727
2728 case MLX5_DEV_EVENT_PKEY_CHANGE:
2729 ibev.event = IB_EVENT_PKEY_CHANGE;
2730
2731 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2732 break;
2733
2734 case MLX5_DEV_EVENT_GUID_CHANGE:
2735 ibev.event = IB_EVENT_GID_CHANGE;
2736 break;
2737
2738 case MLX5_DEV_EVENT_CLIENT_REREG:
2739 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2740 break;
2741
2742 default:
2743 /* unsupported event */
2744 return;
2745 }
2746
2747 ibev.device = &ibdev->ib_dev;
2748 ibev.element.port_num = port;
2749
2750 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
2751 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port);
2752 return;
2753 }
2754
2755 if (ibdev->ib_active)
2756 ib_dispatch_event(&ibev);
2757
2758 if (fatal)
2759 ibdev->ib_active = false;
2760 }
2761
get_ext_port_caps(struct mlx5_ib_dev * dev)2762 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2763 {
2764 int port;
2765
2766 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2767 mlx5_query_ext_port_caps(dev, port);
2768 }
2769
get_port_caps(struct mlx5_ib_dev * dev)2770 static int get_port_caps(struct mlx5_ib_dev *dev)
2771 {
2772 struct ib_device_attr *dprops = NULL;
2773 struct ib_port_attr *pprops = NULL;
2774 int err = -ENOMEM;
2775 int port;
2776 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2777
2778 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2779 if (!pprops)
2780 goto out;
2781
2782 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2783 if (!dprops)
2784 goto out;
2785
2786 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2787 if (err) {
2788 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2789 goto out;
2790 }
2791
2792 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2793 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2794 if (err) {
2795 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2796 port, err);
2797 break;
2798 }
2799 dev->mdev->port_caps[port - 1].pkey_table_len =
2800 dprops->max_pkeys;
2801 dev->mdev->port_caps[port - 1].gid_table_len =
2802 pprops->gid_tbl_len;
2803 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2804 dprops->max_pkeys, pprops->gid_tbl_len);
2805 }
2806
2807 out:
2808 kfree(pprops);
2809 kfree(dprops);
2810
2811 return err;
2812 }
2813
destroy_umrc_res(struct mlx5_ib_dev * dev)2814 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2815 {
2816 int err;
2817
2818 err = mlx5_mr_cache_cleanup(dev);
2819 if (err)
2820 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2821
2822 if (dev->umrc.qp)
2823 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
2824 if (dev->umrc.cq)
2825 ib_free_cq(dev->umrc.cq);
2826 if (dev->umrc.pd)
2827 ib_dealloc_pd(dev->umrc.pd);
2828 }
2829
2830 enum {
2831 MAX_UMR_WR = 128,
2832 };
2833
create_umr_res(struct mlx5_ib_dev * dev)2834 static int create_umr_res(struct mlx5_ib_dev *dev)
2835 {
2836 struct ib_qp_init_attr *init_attr = NULL;
2837 struct ib_qp_attr *attr = NULL;
2838 struct ib_pd *pd;
2839 struct ib_cq *cq;
2840 struct ib_qp *qp;
2841 int ret;
2842
2843 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2844 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2845 if (!attr || !init_attr) {
2846 ret = -ENOMEM;
2847 goto error_0;
2848 }
2849
2850 pd = ib_alloc_pd(&dev->ib_dev, 0);
2851 if (IS_ERR(pd)) {
2852 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2853 ret = PTR_ERR(pd);
2854 goto error_0;
2855 }
2856
2857 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2858 if (IS_ERR(cq)) {
2859 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2860 ret = PTR_ERR(cq);
2861 goto error_2;
2862 }
2863
2864 init_attr->send_cq = cq;
2865 init_attr->recv_cq = cq;
2866 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2867 init_attr->cap.max_send_wr = MAX_UMR_WR;
2868 init_attr->cap.max_send_sge = 1;
2869 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2870 init_attr->port_num = 1;
2871 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2872 if (IS_ERR(qp)) {
2873 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2874 ret = PTR_ERR(qp);
2875 goto error_3;
2876 }
2877 qp->device = &dev->ib_dev;
2878 qp->real_qp = qp;
2879 qp->uobject = NULL;
2880 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2881
2882 attr->qp_state = IB_QPS_INIT;
2883 attr->port_num = 1;
2884 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2885 IB_QP_PORT, NULL);
2886 if (ret) {
2887 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2888 goto error_4;
2889 }
2890
2891 memset(attr, 0, sizeof(*attr));
2892 attr->qp_state = IB_QPS_RTR;
2893 attr->path_mtu = IB_MTU_256;
2894
2895 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2896 if (ret) {
2897 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2898 goto error_4;
2899 }
2900
2901 memset(attr, 0, sizeof(*attr));
2902 attr->qp_state = IB_QPS_RTS;
2903 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2904 if (ret) {
2905 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2906 goto error_4;
2907 }
2908
2909 dev->umrc.qp = qp;
2910 dev->umrc.cq = cq;
2911 dev->umrc.pd = pd;
2912
2913 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2914 ret = mlx5_mr_cache_init(dev);
2915 if (ret) {
2916 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2917 goto error_4;
2918 }
2919
2920 kfree(attr);
2921 kfree(init_attr);
2922
2923 return 0;
2924
2925 error_4:
2926 mlx5_ib_destroy_qp(qp, NULL);
2927 dev->umrc.qp = NULL;
2928
2929 error_3:
2930 ib_free_cq(cq);
2931 dev->umrc.cq = NULL;
2932
2933 error_2:
2934 ib_dealloc_pd(pd);
2935 dev->umrc.pd = NULL;
2936
2937 error_0:
2938 kfree(attr);
2939 kfree(init_attr);
2940 return ret;
2941 }
2942
create_dev_resources(struct mlx5_ib_resources * devr)2943 static int create_dev_resources(struct mlx5_ib_resources *devr)
2944 {
2945 struct ib_srq_init_attr attr;
2946 struct mlx5_ib_dev *dev;
2947 struct ib_device *ibdev;
2948 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2949 int port;
2950 int ret = 0;
2951
2952 dev = container_of(devr, struct mlx5_ib_dev, devr);
2953 ibdev = &dev->ib_dev;
2954
2955 mutex_init(&devr->mutex);
2956
2957 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2958 if (!devr->p0)
2959 return -ENOMEM;
2960
2961 devr->p0->device = ibdev;
2962 devr->p0->uobject = NULL;
2963 atomic_set(&devr->p0->usecnt, 0);
2964
2965 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2966 if (ret)
2967 goto error0;
2968
2969 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2970 if (!devr->c0) {
2971 ret = -ENOMEM;
2972 goto error1;
2973 }
2974
2975 devr->c0->device = &dev->ib_dev;
2976 atomic_set(&devr->c0->usecnt, 0);
2977
2978 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2979 if (ret)
2980 goto err_create_cq;
2981
2982 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
2983 if (IS_ERR(devr->x0)) {
2984 ret = PTR_ERR(devr->x0);
2985 goto error2;
2986 }
2987 devr->x0->device = &dev->ib_dev;
2988 devr->x0->inode = NULL;
2989 atomic_set(&devr->x0->usecnt, 0);
2990 mutex_init(&devr->x0->tgt_qp_mutex);
2991 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2992
2993 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
2994 if (IS_ERR(devr->x1)) {
2995 ret = PTR_ERR(devr->x1);
2996 goto error3;
2997 }
2998 devr->x1->device = &dev->ib_dev;
2999 devr->x1->inode = NULL;
3000 atomic_set(&devr->x1->usecnt, 0);
3001 mutex_init(&devr->x1->tgt_qp_mutex);
3002 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3003
3004 memset(&attr, 0, sizeof(attr));
3005 attr.attr.max_sge = 1;
3006 attr.attr.max_wr = 1;
3007 attr.srq_type = IB_SRQT_XRC;
3008 attr.ext.cq = devr->c0;
3009 attr.ext.xrc.xrcd = devr->x0;
3010
3011 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3012 if (!devr->s0) {
3013 ret = -ENOMEM;
3014 goto error4;
3015 }
3016
3017 devr->s0->device = &dev->ib_dev;
3018 devr->s0->pd = devr->p0;
3019 devr->s0->srq_type = IB_SRQT_XRC;
3020 devr->s0->ext.xrc.xrcd = devr->x0;
3021 devr->s0->ext.cq = devr->c0;
3022 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
3023 if (ret)
3024 goto err_create;
3025
3026 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3027 atomic_inc(&devr->s0->ext.cq->usecnt);
3028 atomic_inc(&devr->p0->usecnt);
3029 atomic_set(&devr->s0->usecnt, 0);
3030
3031 memset(&attr, 0, sizeof(attr));
3032 attr.attr.max_sge = 1;
3033 attr.attr.max_wr = 1;
3034 attr.srq_type = IB_SRQT_BASIC;
3035 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3036 if (!devr->s1) {
3037 ret = -ENOMEM;
3038 goto error5;
3039 }
3040
3041 devr->s1->device = &dev->ib_dev;
3042 devr->s1->pd = devr->p0;
3043 devr->s1->srq_type = IB_SRQT_BASIC;
3044 devr->s1->ext.cq = devr->c0;
3045
3046 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
3047 if (ret)
3048 goto error6;
3049
3050 atomic_inc(&devr->p0->usecnt);
3051 atomic_set(&devr->s1->usecnt, 0);
3052
3053 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3054 INIT_WORK(&devr->ports[port].pkey_change_work,
3055 pkey_change_handler);
3056 devr->ports[port].devr = devr;
3057 }
3058
3059 return 0;
3060
3061 error6:
3062 kfree(devr->s1);
3063 error5:
3064 mlx5_ib_destroy_srq(devr->s0, NULL);
3065 err_create:
3066 kfree(devr->s0);
3067 error4:
3068 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
3069 error3:
3070 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
3071 error2:
3072 mlx5_ib_destroy_cq(devr->c0, NULL);
3073 err_create_cq:
3074 kfree(devr->c0);
3075 error1:
3076 mlx5_ib_dealloc_pd(devr->p0, NULL);
3077 error0:
3078 kfree(devr->p0);
3079 return ret;
3080 }
3081
destroy_dev_resources(struct mlx5_ib_resources * devr)3082 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3083 {
3084 int port;
3085
3086 mlx5_ib_destroy_srq(devr->s1, NULL);
3087 kfree(devr->s1);
3088 mlx5_ib_destroy_srq(devr->s0, NULL);
3089 kfree(devr->s0);
3090 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
3091 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
3092 mlx5_ib_destroy_cq(devr->c0, NULL);
3093 kfree(devr->c0);
3094 mlx5_ib_dealloc_pd(devr->p0, NULL);
3095 kfree(devr->p0);
3096
3097 /* Make sure no change P_Key work items are still executing */
3098 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3099 cancel_work_sync(&devr->ports[port].pkey_change_work);
3100 }
3101
get_core_cap_flags(struct ib_device * ibdev)3102 static u32 get_core_cap_flags(struct ib_device *ibdev)
3103 {
3104 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3105 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3106 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3107 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3108 u32 ret = 0;
3109
3110 if (ll == IB_LINK_LAYER_INFINIBAND)
3111 return RDMA_CORE_PORT_IBA_IB;
3112
3113 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3114 return 0;
3115
3116 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3117 return 0;
3118
3119 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3120 ret |= RDMA_CORE_PORT_IBA_ROCE;
3121
3122 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3123 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3124
3125 return ret;
3126 }
3127
mlx5_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)3128 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3129 struct ib_port_immutable *immutable)
3130 {
3131 struct ib_port_attr attr;
3132 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3133 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3134 int err;
3135
3136 err = mlx5_ib_query_port(ibdev, port_num, &attr);
3137 if (err)
3138 return err;
3139
3140 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3141 immutable->gid_tbl_len = attr.gid_tbl_len;
3142 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3143 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3144 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3145
3146 return 0;
3147 }
3148
get_dev_fw_str(struct ib_device * ibdev,char * str,size_t str_len)3149 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3150 size_t str_len)
3151 {
3152 struct mlx5_ib_dev *dev =
3153 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3154 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3155 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3156 }
3157
mlx5_roce_lag_init(struct mlx5_ib_dev * dev)3158 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
3159 {
3160 return 0;
3161 }
3162
mlx5_roce_lag_cleanup(struct mlx5_ib_dev * dev)3163 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
3164 {
3165 }
3166
mlx5_remove_roce_notifier(struct mlx5_ib_dev * dev)3167 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
3168 {
3169 if (dev->roce.nb.notifier_call) {
3170 unregister_netdevice_notifier(&dev->roce.nb);
3171 dev->roce.nb.notifier_call = NULL;
3172 }
3173 }
3174
3175 static int
mlx5_enable_roce_if_cb(if_t ifp,void * arg)3176 mlx5_enable_roce_if_cb(if_t ifp, void *arg)
3177 {
3178 struct mlx5_ib_dev *dev = arg;
3179
3180 /* check if network interface belongs to mlx5en */
3181 if (!mlx5_netdev_match(ifp, dev->mdev, "mce"))
3182 return (0);
3183
3184 write_lock(&dev->roce.netdev_lock);
3185 dev->roce.netdev = ifp;
3186 write_unlock(&dev->roce.netdev_lock);
3187
3188 return (0);
3189 }
3190
mlx5_enable_roce(struct mlx5_ib_dev * dev)3191 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
3192 {
3193 struct epoch_tracker et;
3194 VNET_ITERATOR_DECL(vnet_iter);
3195 int err;
3196
3197 /* Check if mlx5en net device already exists */
3198 VNET_LIST_RLOCK();
3199 NET_EPOCH_ENTER(et);
3200 VNET_FOREACH(vnet_iter) {
3201 CURVNET_SET_QUIET(vnet_iter);
3202 if_foreach(mlx5_enable_roce_if_cb, dev);
3203 CURVNET_RESTORE();
3204 }
3205 NET_EPOCH_EXIT(et);
3206 VNET_LIST_RUNLOCK();
3207
3208 dev->roce.nb.notifier_call = mlx5_netdev_event;
3209 err = register_netdevice_notifier(&dev->roce.nb);
3210 if (err) {
3211 dev->roce.nb.notifier_call = NULL;
3212 return err;
3213 }
3214
3215 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3216 err = mlx5_nic_vport_enable_roce(dev->mdev);
3217 if (err)
3218 goto err_unregister_netdevice_notifier;
3219 }
3220
3221 err = mlx5_roce_lag_init(dev);
3222 if (err)
3223 goto err_disable_roce;
3224
3225 return 0;
3226
3227 err_disable_roce:
3228 if (MLX5_CAP_GEN(dev->mdev, roce))
3229 mlx5_nic_vport_disable_roce(dev->mdev);
3230
3231 err_unregister_netdevice_notifier:
3232 mlx5_remove_roce_notifier(dev);
3233 return err;
3234 }
3235
mlx5_disable_roce(struct mlx5_ib_dev * dev)3236 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
3237 {
3238 mlx5_roce_lag_cleanup(dev);
3239 if (MLX5_CAP_GEN(dev->mdev, roce))
3240 mlx5_nic_vport_disable_roce(dev->mdev);
3241 }
3242
mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev * dev,u8 port_num)3243 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
3244 {
3245 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
3246 u32 out[MLX5_ST_SZ_DW(dealloc_q_counter_out)] = {};
3247
3248 if (!dev->port[port_num].q_cnt_id)
3249 return;
3250
3251 MLX5_SET(dealloc_q_counter_in, in, opcode,
3252 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
3253 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
3254 dev->port[port_num].q_cnt_id);
3255 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
3256 dev->port[port_num].q_cnt_id = 0;
3257 }
3258
mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev * dev)3259 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3260 {
3261 unsigned int i;
3262
3263 for (i = 0; i < dev->num_ports; i++)
3264 mlx5_ib_dealloc_q_port_counter(dev, i);
3265 }
3266
mlx5_ib_alloc_q_counters(struct mlx5_ib_dev * dev)3267 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3268 {
3269 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
3270 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
3271 int i;
3272 int ret;
3273
3274 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3275 /*
3276 * On devices that support user contexts, allocate the queue counters
3277 * as a shared resource so QPs owned by a user context (DEVX uid) can
3278 * reference them; otherwise RST2INIT_QP fails with a firmware "bad
3279 * resource state" error.
3280 */
3281 if (MLX5_CAP_GEN(dev->mdev, log_max_uctx))
3282 MLX5_SET(alloc_q_counter_in, in, uid, MLX5_SHARED_RESOURCE_UID);
3283
3284 for (i = 0; i < dev->num_ports; i++) {
3285 ret = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
3286 if (ret) {
3287 mlx5_ib_warn(dev,
3288 "couldn't allocate queue counter for port %d, err %d\n",
3289 i + 1, ret);
3290 goto dealloc_counters;
3291 }
3292 dev->port[i].q_cnt_id = MLX5_GET(alloc_q_counter_out, out,
3293 counter_set_id);
3294 }
3295
3296 return 0;
3297
3298 dealloc_counters:
3299 while (--i >= 0)
3300 mlx5_ib_dealloc_q_port_counter(dev, i);
3301
3302 return ret;
3303 }
3304
3305 static const char * const names[] = {
3306 "rx_write_requests",
3307 "rx_read_requests",
3308 "rx_atomic_requests",
3309 "out_of_buffer",
3310 "out_of_sequence",
3311 "duplicate_request",
3312 "rnr_nak_retry_err",
3313 "packet_seq_err",
3314 "implied_nak_seq_err",
3315 "local_ack_timeout_err",
3316 };
3317
3318 static const size_t stats_offsets[] = {
3319 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
3320 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
3321 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
3322 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
3323 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
3324 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
3325 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
3326 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
3327 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
3328 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
3329 };
3330
mlx5_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)3331 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3332 u8 port_num)
3333 {
3334 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
3335
3336 /* We support only per port stats */
3337 if (port_num == 0)
3338 return NULL;
3339
3340 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
3341 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3342 }
3343
mlx5_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)3344 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3345 struct rdma_hw_stats *stats,
3346 u8 port, int index)
3347 {
3348 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3349 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3350 void *out;
3351 __be32 val;
3352 int ret;
3353 int i;
3354
3355 if (!port || !stats)
3356 return -ENOSYS;
3357
3358 out = mlx5_vzalloc(outlen);
3359 if (!out)
3360 return -ENOMEM;
3361
3362 ret = mlx5_vport_query_q_counter(dev->mdev,
3363 dev->port[port - 1].q_cnt_id, 0,
3364 out, outlen);
3365 if (ret)
3366 goto free;
3367
3368 for (i = 0; i < ARRAY_SIZE(names); i++) {
3369 val = *(__be32 *)(out + stats_offsets[i]);
3370 stats->value[i] = (u64)be32_to_cpu(val);
3371 }
3372 free:
3373 kvfree(out);
3374 return ARRAY_SIZE(names);
3375 }
3376
3377 /*
3378 * MLX5_IB_OBJECT_UAR: allocate a dedicated UAR for user space and expose it
3379 * through an mmap entry. Modern libmlx5 uses this (dynamic UAR) to obtain the
3380 * UAR backing CQ/QP doorbells instead of the legacy static UAR pages.
3381 */
mmap_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)3382 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3383 enum rdma_remove_reason why,
3384 struct uverbs_attr_bundle *attrs)
3385 {
3386 struct mlx5_user_mmap_entry *obj = uobject->object;
3387
3388 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3389 return 0;
3390 }
3391
UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)3392 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3393 struct uverbs_attr_bundle *attrs)
3394 {
3395 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
3396 MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3397 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3398 struct mlx5_user_mmap_entry *entry;
3399 struct mlx5_ib_ucontext *c;
3400 struct mlx5_ib_dev *dev;
3401 u32 uar_index;
3402 u32 length = PAGE_SIZE;
3403 u64 mmap_offset;
3404 int err;
3405
3406 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3407 if (IS_ERR(c))
3408 return PTR_ERR(c);
3409 dev = to_mdev(c->ibucontext.device);
3410
3411 err = uverbs_get_const(&alloc_type, attrs,
3412 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3413 if (err)
3414 return err;
3415
3416 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3417 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3418 return -EOPNOTSUPP;
3419
3420 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && !dev->wc_support)
3421 return -EOPNOTSUPP;
3422
3423 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
3424 if (err)
3425 return err;
3426
3427 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3428 if (!entry) {
3429 err = -ENOMEM;
3430 goto err_uar;
3431 }
3432
3433 entry->mmap_flag = (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) ?
3434 MLX5_IB_MMAP_TYPE_UAR_NC : MLX5_IB_MMAP_TYPE_UAR_WC;
3435 entry->page_idx = uar_index;
3436 entry->address = uar_index2pfn(dev, uar_index) << PAGE_SHIFT;
3437
3438 err = mlx5_rdma_user_mmap_entry_insert(c, entry, length);
3439 if (err)
3440 goto err_entry;
3441
3442 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3443 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3444 &mmap_offset, sizeof(mmap_offset));
3445 if (err)
3446 goto err_insert;
3447 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3448 &length, sizeof(length));
3449 if (err)
3450 goto err_insert;
3451 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3452 &uar_index, sizeof(uar_index));
3453 if (err)
3454 goto err_insert;
3455
3456 uobj->object = entry;
3457 return 0;
3458
3459 err_insert:
3460 /* Removing the entry frees the UAR and the entry itself. */
3461 rdma_user_mmap_entry_remove(&entry->rdma_entry);
3462 return err;
3463 err_entry:
3464 kfree(entry);
3465 err_uar:
3466 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
3467 return err;
3468 }
3469
3470 DECLARE_UVERBS_NAMED_METHOD(
3471 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3472 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3473 MLX5_IB_OBJECT_UAR,
3474 UVERBS_ACCESS_NEW,
3475 UA_MANDATORY),
3476 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3477 enum mlx5_ib_uapi_uar_alloc_type,
3478 UA_MANDATORY),
3479 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3480 UVERBS_ATTR_TYPE(u32),
3481 UA_MANDATORY),
3482 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3483 UVERBS_ATTR_TYPE(u32),
3484 UA_MANDATORY),
3485 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3486 UVERBS_ATTR_TYPE(u64),
3487 UA_MANDATORY));
3488
3489 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3490 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3491 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3492 MLX5_IB_OBJECT_UAR,
3493 UVERBS_ACCESS_DESTROY,
3494 UA_MANDATORY));
3495
3496 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3497 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3498 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3499 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3500
3501 static const struct uapi_definition mlx5_ib_defs[] = {
3502 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3503 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3504 {}
3505 };
3506
mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev * dev)3507 static int mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev *dev)
3508 {
3509 int err;
3510
3511 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3512 if (err)
3513 return err;
3514
3515 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3516 if (err) {
3517 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3518 return err;
3519 }
3520
3521 err = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false);
3522 if (err) {
3523 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3524 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3525 }
3526
3527 return err;
3528 }
3529
mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev * dev)3530 static void mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev *dev)
3531 {
3532 mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg);
3533 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3534 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3535 }
3536
mlx5_ib_add(struct mlx5_core_dev * mdev)3537 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3538 {
3539 struct mlx5_ib_dev *dev;
3540 enum rdma_link_layer ll;
3541 int port_type_cap;
3542 int err;
3543 int i;
3544
3545 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3546 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3547
3548 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3549 if (!dev)
3550 return NULL;
3551
3552 dev->mdev = mdev;
3553
3554 /*
3555 * Write-combining is required to expose BlueFlame (WC) UARs through the
3556 * dynamic MLX5_IB_OBJECT_UAR ioctl path. The legacy static UAR path
3557 * already maps doorbell pages with pgprot_writecombine(), so advertise
3558 * WC support whenever the platform actually provides it.
3559 */
3560 #if defined(VM_MEMATTR_WRITE_COMBINING)
3561 dev->wc_support = true;
3562 #endif
3563
3564 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3565 GFP_KERNEL);
3566 if (!dev->port)
3567 goto err_dealloc;
3568
3569 rwlock_init(&dev->roce.netdev_lock);
3570 err = get_port_caps(dev);
3571 if (err)
3572 goto err_free_port;
3573
3574 if (mlx5_use_mad_ifc(dev))
3575 get_ext_port_caps(dev);
3576
3577 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3578
3579 mutex_init(&dev->lb_mutex);
3580
3581 INIT_IB_DEVICE_OPS(&dev->ib_dev.ops, mlx5, MLX5);
3582 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev));
3583 dev->ib_dev.owner = THIS_MODULE;
3584 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3585 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3586 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3587 dev->ib_dev.phys_port_cnt = dev->num_ports;
3588 dev->ib_dev.num_comp_vectors =
3589 dev->mdev->priv.eq_table.num_comp_vectors;
3590 dev->ib_dev.dma_device = &mdev->pdev->dev;
3591 dev->ib_dev.driver_def = mlx5_ib_defs;
3592
3593 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3594 dev->ib_dev.uverbs_cmd_mask =
3595 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3596 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3597 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3598 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3599 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3600 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3601 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3602 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3603 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3604 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3605 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3606 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3607 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3608 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3609 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3610 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3611 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3612 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3613 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3614 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3615 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3616 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3617 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3618 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3619 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3620 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3621 dev->ib_dev.uverbs_ex_cmd_mask =
3622 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3623 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3624 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3625
3626 dev->ib_dev.query_device = mlx5_ib_query_device;
3627 dev->ib_dev.query_port = mlx5_ib_query_port;
3628 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3629 if (ll == IB_LINK_LAYER_ETHERNET)
3630 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3631 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3632 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3633 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3634 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3635 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3636 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3637 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3638 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3639 dev->ib_dev.mmap = mlx5_ib_mmap;
3640 dev->ib_dev.mmap_free = mlx5_ib_mmap_free;
3641 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3642 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3643 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3644 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3645 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3646 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3647 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3648 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3649 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3650 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3651 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3652 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3653 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3654 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3655 dev->ib_dev.post_send = mlx5_ib_post_send;
3656 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3657 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3658 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3659 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3660 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3661 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3662 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3663 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3664 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3665 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3666 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3667 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3668 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3669 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3670 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3671 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3672 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3673 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3674 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3675 if (mlx5_core_is_pf(mdev)) {
3676 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3677 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3678 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3679 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3680 }
3681
3682 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3683
3684 mlx5_ib_internal_fill_odp_caps(dev);
3685
3686 if (MLX5_CAP_GEN(mdev, imaicl)) {
3687 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3688 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3689 dev->ib_dev.uverbs_cmd_mask |=
3690 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3691 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3692 }
3693
3694 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3695 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3696 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3697 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3698 }
3699
3700 if (MLX5_CAP_GEN(mdev, xrc)) {
3701 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3702 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3703 dev->ib_dev.uverbs_cmd_mask |=
3704 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3705 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3706 }
3707
3708 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3709 IB_LINK_LAYER_ETHERNET) {
3710 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3711 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3712 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3713 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3714 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3715 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3716 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3717 dev->ib_dev.uverbs_ex_cmd_mask |=
3718 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3719 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3720 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3721 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3722 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3723 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3724 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3725 }
3726 err = init_node_data(dev);
3727 if (err)
3728 goto err_free_port;
3729
3730 mutex_init(&dev->flow_db.lock);
3731 mutex_init(&dev->cap_mask_mutex);
3732 INIT_LIST_HEAD(&dev->qp_list);
3733 spin_lock_init(&dev->reset_flow_resource_lock);
3734
3735 if (ll == IB_LINK_LAYER_ETHERNET) {
3736 err = mlx5_enable_roce(dev);
3737 if (err)
3738 goto err_free_port;
3739 }
3740
3741 err = create_dev_resources(&dev->devr);
3742 if (err)
3743 goto err_disable_roce;
3744
3745 err = mlx5_ib_odp_init_one(dev);
3746 if (err)
3747 goto err_rsrc;
3748
3749 err = mlx5_ib_alloc_q_counters(dev);
3750 if (err)
3751 goto err_odp;
3752
3753 err = mlx5_ib_stage_bfreg_init(dev);
3754 if (err)
3755 goto err_q_cnt;
3756
3757 /*
3758 * Initialize the DEVX event table before ib_register_device().
3759 * Registration merges ib_dev.driver_def into the uverbs uapi, which
3760 * makes the DEVX object tree live immediately; initializing the event
3761 * table afterwards would leave a window where a DEVX ioctl could touch
3762 * an uninitialized dev->devx_event_table.
3763 */
3764 mlx5_ib_devx_init_event_table(dev);
3765
3766 err = ib_register_device(&dev->ib_dev, NULL);
3767 if (err)
3768 goto err_devx;
3769
3770 err = create_umr_res(dev);
3771 if (err)
3772 goto err_dev;
3773
3774 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3775 err = device_create_file(&dev->ib_dev.dev,
3776 mlx5_class_attributes[i]);
3777 if (err)
3778 goto err_umrc;
3779 }
3780
3781 err = mlx5_ib_init_congestion(dev);
3782 if (err)
3783 goto err_umrc;
3784
3785 dev->ib_active = true;
3786
3787 return dev;
3788
3789 err_umrc:
3790 destroy_umrc_res(dev);
3791
3792 err_dev:
3793 ib_unregister_device(&dev->ib_dev);
3794
3795 err_devx:
3796 mlx5_ib_devx_cleanup_event_table(dev);
3797
3798 mlx5_ib_stage_bfreg_cleanup(dev);
3799
3800 err_q_cnt:
3801 mlx5_ib_dealloc_q_counters(dev);
3802
3803 err_odp:
3804 mlx5_ib_odp_remove_one(dev);
3805
3806 err_rsrc:
3807 destroy_dev_resources(&dev->devr);
3808
3809 err_disable_roce:
3810 if (ll == IB_LINK_LAYER_ETHERNET) {
3811 mlx5_disable_roce(dev);
3812 mlx5_remove_roce_notifier(dev);
3813 }
3814
3815 err_free_port:
3816 kfree(dev->port);
3817
3818 err_dealloc:
3819 ib_dealloc_device((struct ib_device *)dev);
3820
3821 return NULL;
3822 }
3823
mlx5_ib_remove(struct mlx5_core_dev * mdev,void * context)3824 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3825 {
3826 struct mlx5_ib_dev *dev = context;
3827 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3828
3829 mlx5_ib_devx_cleanup_event_table(dev);
3830 mlx5_ib_cleanup_congestion(dev);
3831 mlx5_remove_roce_notifier(dev);
3832 ib_unregister_device(&dev->ib_dev);
3833 mlx5_ib_stage_bfreg_cleanup(dev);
3834 mlx5_ib_dealloc_q_counters(dev);
3835 destroy_umrc_res(dev);
3836 mlx5_ib_odp_remove_one(dev);
3837 destroy_dev_resources(&dev->devr);
3838 if (ll == IB_LINK_LAYER_ETHERNET)
3839 mlx5_disable_roce(dev);
3840 kfree(dev->port);
3841 ib_dealloc_device(&dev->ib_dev);
3842 }
3843
3844 static struct mlx5_interface mlx5_ib_interface = {
3845 .add = mlx5_ib_add,
3846 .remove = mlx5_ib_remove,
3847 .event = mlx5_ib_event,
3848 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3849 };
3850
mlx5_ib_init(void)3851 static int __init mlx5_ib_init(void)
3852 {
3853 int err;
3854
3855 err = mlx5_ib_odp_init();
3856 if (err)
3857 return err;
3858
3859 err = mlx5_register_interface(&mlx5_ib_interface);
3860 if (err)
3861 goto clean_odp;
3862
3863 return err;
3864
3865 clean_odp:
3866 mlx5_ib_odp_cleanup();
3867 return err;
3868 }
3869
mlx5_ib_cleanup(void)3870 static void __exit mlx5_ib_cleanup(void)
3871 {
3872 mlx5_unregister_interface(&mlx5_ib_interface);
3873 mlx5_ib_odp_cleanup();
3874 }
3875
3876 module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH);
3877 module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH);
3878