1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/etherdevice.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
15 #include <linux/bitfield.h>
16
17 #define DP83822_PHY_ID 0x2000a240
18 #define DP83825S_PHY_ID 0x2000a140
19 #define DP83825I_PHY_ID 0x2000a150
20 #define DP83825CM_PHY_ID 0x2000a160
21 #define DP83825CS_PHY_ID 0x2000a170
22 #define DP83826C_PHY_ID 0x2000a130
23 #define DP83826NC_PHY_ID 0x2000a110
24
25 #define MII_DP83822_CTRL_2 0x0a
26 #define MII_DP83822_PHYSTS 0x10
27 #define MII_DP83822_PHYSCR 0x11
28 #define MII_DP83822_MISR1 0x12
29 #define MII_DP83822_MISR2 0x13
30 #define MII_DP83822_FCSCR 0x14
31 #define MII_DP83822_RCSR 0x17
32 #define MII_DP83822_RESET_CTRL 0x1f
33 #define MII_DP83822_MLEDCR 0x25
34 #define MII_DP83822_LDCTRL 0x403
35 #define MII_DP83822_LEDCFG1 0x460
36 #define MII_DP83822_IOCTRL 0x461
37 #define MII_DP83822_IOCTRL1 0x462
38 #define MII_DP83822_IOCTRL2 0x463
39 #define MII_DP83822_GENCFG 0x465
40 #define MII_DP83822_SOR1 0x467
41
42 /* DP83826 specific registers */
43 #define MII_DP83826_VOD_CFG1 0x30b
44 #define MII_DP83826_VOD_CFG2 0x30c
45
46 /* GENCFG */
47 #define DP83822_SIG_DET_LOW BIT(0)
48
49 /* Control Register 2 bits */
50 #define DP83822_FX_ENABLE BIT(14)
51
52 #define DP83822_SW_RESET BIT(15)
53 #define DP83822_DIG_RESTART BIT(14)
54
55 /* PHY STS bits */
56 #define DP83822_PHYSTS_DUPLEX BIT(2)
57 #define DP83822_PHYSTS_10 BIT(1)
58 #define DP83822_PHYSTS_LINK BIT(0)
59
60 /* PHYSCR Register Fields */
61 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
62 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
63
64 /* MISR1 bits */
65 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
66 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
67 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
68 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
69 #define DP83822_SPEED_CHANGED_INT_EN BIT(4)
70 #define DP83822_LINK_STAT_INT_EN BIT(5)
71 #define DP83822_ENERGY_DET_INT_EN BIT(6)
72 #define DP83822_LINK_QUAL_INT_EN BIT(7)
73
74 /* MISR2 bits */
75 #define DP83822_JABBER_DET_INT_EN BIT(0)
76 #define DP83822_WOL_PKT_INT_EN BIT(1)
77 #define DP83822_SLEEP_MODE_INT_EN BIT(2)
78 #define DP83822_MDI_XOVER_INT_EN BIT(3)
79 #define DP83822_LB_FIFO_INT_EN BIT(4)
80 #define DP83822_PAGE_RX_INT_EN BIT(5)
81 #define DP83822_ANEG_ERR_INT_EN BIT(6)
82 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
83
84 /* INT_STAT1 bits */
85 #define DP83822_WOL_INT_EN BIT(4)
86 #define DP83822_WOL_INT_STAT BIT(12)
87
88 #define MII_DP83822_RXSOP1 0x04a5
89 #define MII_DP83822_RXSOP2 0x04a6
90 #define MII_DP83822_RXSOP3 0x04a7
91
92 /* WoL Registers */
93 #define MII_DP83822_WOL_CFG 0x04a0
94 #define MII_DP83822_WOL_STAT 0x04a1
95 #define MII_DP83822_WOL_DA1 0x04a2
96 #define MII_DP83822_WOL_DA2 0x04a3
97 #define MII_DP83822_WOL_DA3 0x04a4
98
99 /* WoL bits */
100 #define DP83822_WOL_MAGIC_EN BIT(0)
101 #define DP83822_WOL_SECURE_ON BIT(5)
102 #define DP83822_WOL_EN BIT(7)
103 #define DP83822_WOL_INDICATION_SEL BIT(8)
104 #define DP83822_WOL_CLR_INDICATION BIT(11)
105
106 /* RCSR bits */
107 #define DP83822_RMII_MODE_EN BIT(5)
108 #define DP83822_RMII_MODE_SEL BIT(7)
109 #define DP83822_RGMII_MODE_EN BIT(9)
110 #define DP83822_RX_CLK_SHIFT BIT(12)
111 #define DP83822_TX_CLK_SHIFT BIT(11)
112
113 /* MLEDCR bits */
114 #define DP83822_MLEDCR_CFG GENMASK(6, 3)
115 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0)
116 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE
117
118 /* LEDCFG1 bits */
119 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8)
120 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4)
121
122 /* IOCTRL bits */
123 #define DP83822_IOCTRL_MAC_IMPEDANCE_CTRL GENMASK(4, 1)
124
125 /* IOCTRL1 bits */
126 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8)
127 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0)
128 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0)
129 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0)
130
131 /* LDCTRL bits */
132 #define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4)
133
134 /* IOCTRL2 bits */
135 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
136 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
137 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)
138 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0)
139
140 #define DP83822_CLK_SRC_MAC_IF 0x0
141 #define DP83822_CLK_SRC_XI 0x1
142 #define DP83822_CLK_SRC_INT_REF 0x2
143 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4
144 #define DP83822_CLK_SRC_FREE_RUNNING 0x6
145 #define DP83822_CLK_SRC_RECOVERED 0x7
146
147 #define DP83822_LED_FN_LINK 0x0 /* Link established */
148 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
149 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */
150 #define DP83822_LED_FN_RX 0x3 /* Receive activity */
151 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */
152 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */
153 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */
154 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */
155 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */
156 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */
157 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */
158 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */
159 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */
160 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */
161 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */
162
163 /* SOR1 mode */
164 #define DP83822_STRAP_MODE1 0
165 #define DP83822_STRAP_MODE2 BIT(0)
166 #define DP83822_STRAP_MODE3 BIT(1)
167 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
168
169 #define DP83822_COL_STRAP_MASK GENMASK(11, 10)
170 #define DP83822_COL_SHIFT 10
171 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
172 #define DP83822_RX_ER_SHIFT 8
173
174 /* DP83826: VOD_CFG1 & VOD_CFG2 */
175 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)
176 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)
177 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)
178 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)
179 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)
180 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)
181 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)
182 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625
183 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000
184 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30
185 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10
186
187 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
188 ADVERTISED_FIBRE | \
189 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
190
191 #define DP83822_MAX_LED_PINS 4
192
193 #define DP83822_LED_INDEX_LED_0 0
194 #define DP83822_LED_INDEX_LED_1_GPIO1 1
195 #define DP83822_LED_INDEX_COL_GPIO2 2
196 #define DP83822_LED_INDEX_RX_D3_GPIO3 3
197
198 struct dp83822_private {
199 bool fx_signal_det_low;
200 int fx_enabled;
201 u16 fx_sd_enable;
202 u8 cfg_dac_minus;
203 u8 cfg_dac_plus;
204 struct ethtool_wolinfo wol;
205 bool set_gpio2_clk_out;
206 u32 gpio2_clk_out;
207 bool led_pin_enable[DP83822_MAX_LED_PINS];
208 int tx_amplitude_100base_tx_index;
209 int mac_termination_index;
210 };
211
dp83822_config_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)212 static int dp83822_config_wol(struct phy_device *phydev,
213 struct ethtool_wolinfo *wol)
214 {
215 struct net_device *ndev = phydev->attached_dev;
216 u16 value;
217 const u8 *mac;
218
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
220 mac = (const u8 *)ndev->dev_addr;
221
222 if (!is_valid_ether_addr(mac))
223 return -EINVAL;
224
225 /* MAC addresses start with byte 5, but stored in mac[0].
226 * 822 PHYs store bytes 4|5, 2|3, 0|1
227 */
228 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1,
229 (mac[1] << 8) | mac[0]);
230 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2,
231 (mac[3] << 8) | mac[2]);
232 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3,
233 (mac[5] << 8) | mac[4]);
234
235 value = phy_read_mmd(phydev, MDIO_MMD_VEND2,
236 MII_DP83822_WOL_CFG);
237 if (wol->wolopts & WAKE_MAGIC)
238 value |= DP83822_WOL_MAGIC_EN;
239 else
240 value &= ~DP83822_WOL_MAGIC_EN;
241
242 if (wol->wolopts & WAKE_MAGICSECURE) {
243 phy_write_mmd(phydev, MDIO_MMD_VEND2,
244 MII_DP83822_RXSOP1,
245 (wol->sopass[1] << 8) | wol->sopass[0]);
246 phy_write_mmd(phydev, MDIO_MMD_VEND2,
247 MII_DP83822_RXSOP2,
248 (wol->sopass[3] << 8) | wol->sopass[2]);
249 phy_write_mmd(phydev, MDIO_MMD_VEND2,
250 MII_DP83822_RXSOP3,
251 (wol->sopass[5] << 8) | wol->sopass[4]);
252 value |= DP83822_WOL_SECURE_ON;
253 } else {
254 value &= ~DP83822_WOL_SECURE_ON;
255 }
256
257 /* Clear any pending WoL interrupt */
258 phy_read(phydev, MII_DP83822_MISR2);
259
260 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
261 DP83822_WOL_CLR_INDICATION;
262
263 return phy_write_mmd(phydev, MDIO_MMD_VEND2,
264 MII_DP83822_WOL_CFG, value);
265 } else {
266 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
267 MII_DP83822_WOL_CFG,
268 DP83822_WOL_EN |
269 DP83822_WOL_MAGIC_EN |
270 DP83822_WOL_SECURE_ON);
271 }
272 }
273
dp83822_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)274 static int dp83822_set_wol(struct phy_device *phydev,
275 struct ethtool_wolinfo *wol)
276 {
277 struct dp83822_private *dp83822 = phydev->priv;
278 int ret;
279
280 ret = dp83822_config_wol(phydev, wol);
281 if (!ret)
282 memcpy(&dp83822->wol, wol, sizeof(*wol));
283 return ret;
284 }
285
dp83822_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)286 static void dp83822_get_wol(struct phy_device *phydev,
287 struct ethtool_wolinfo *wol)
288 {
289 int value;
290 u16 sopass_val;
291
292 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
293 wol->wolopts = 0;
294
295 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
296
297 if (value & DP83822_WOL_MAGIC_EN)
298 wol->wolopts |= WAKE_MAGIC;
299
300 if (value & DP83822_WOL_SECURE_ON) {
301 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
302 MII_DP83822_RXSOP1);
303 wol->sopass[0] = (sopass_val & 0xff);
304 wol->sopass[1] = (sopass_val >> 8);
305
306 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
307 MII_DP83822_RXSOP2);
308 wol->sopass[2] = (sopass_val & 0xff);
309 wol->sopass[3] = (sopass_val >> 8);
310
311 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
312 MII_DP83822_RXSOP3);
313 wol->sopass[4] = (sopass_val & 0xff);
314 wol->sopass[5] = (sopass_val >> 8);
315
316 wol->wolopts |= WAKE_MAGICSECURE;
317 }
318
319 /* WoL is not enabled so set wolopts to 0 */
320 if (!(value & DP83822_WOL_EN))
321 wol->wolopts = 0;
322 }
323
dp83822_config_intr(struct phy_device * phydev)324 static int dp83822_config_intr(struct phy_device *phydev)
325 {
326 struct dp83822_private *dp83822 = phydev->priv;
327 int misr_status;
328 int physcr_status;
329 int err;
330
331 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
332 misr_status = phy_read(phydev, MII_DP83822_MISR1);
333 if (misr_status < 0)
334 return misr_status;
335
336 misr_status |= (DP83822_LINK_STAT_INT_EN |
337 DP83822_ENERGY_DET_INT_EN |
338 DP83822_LINK_QUAL_INT_EN);
339
340 if (!dp83822->fx_enabled)
341 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
342 DP83822_DUP_MODE_CHANGE_INT_EN |
343 DP83822_SPEED_CHANGED_INT_EN;
344
345
346 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
347 if (err < 0)
348 return err;
349
350 misr_status = phy_read(phydev, MII_DP83822_MISR2);
351 if (misr_status < 0)
352 return misr_status;
353
354 misr_status |= (DP83822_JABBER_DET_INT_EN |
355 DP83822_SLEEP_MODE_INT_EN |
356 DP83822_LB_FIFO_INT_EN |
357 DP83822_PAGE_RX_INT_EN |
358 DP83822_EEE_ERROR_CHANGE_INT_EN);
359
360 if (!dp83822->fx_enabled)
361 misr_status |= DP83822_ANEG_ERR_INT_EN |
362 DP83822_WOL_PKT_INT_EN;
363
364 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
365 if (err < 0)
366 return err;
367
368 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
369 if (physcr_status < 0)
370 return physcr_status;
371
372 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
373
374 } else {
375 err = phy_write(phydev, MII_DP83822_MISR1, 0);
376 if (err < 0)
377 return err;
378
379 err = phy_write(phydev, MII_DP83822_MISR2, 0);
380 if (err < 0)
381 return err;
382
383 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
384 if (physcr_status < 0)
385 return physcr_status;
386
387 physcr_status &= ~DP83822_PHYSCR_INTEN;
388 }
389
390 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
391 }
392
dp83822_handle_interrupt(struct phy_device * phydev)393 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
394 {
395 bool trigger_machine = false;
396 int irq_status;
397
398 /* The MISR1 and MISR2 registers are holding the interrupt status in
399 * the upper half (15:8), while the lower half (7:0) is used for
400 * controlling the interrupt enable state of those individual interrupt
401 * sources. To determine the possible interrupt sources, just read the
402 * MISR* register and use it directly to know which interrupts have
403 * been enabled previously or not.
404 */
405 irq_status = phy_read(phydev, MII_DP83822_MISR1);
406 if (irq_status < 0) {
407 phy_error(phydev);
408 return IRQ_NONE;
409 }
410 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
411 trigger_machine = true;
412
413 irq_status = phy_read(phydev, MII_DP83822_MISR2);
414 if (irq_status < 0) {
415 phy_error(phydev);
416 return IRQ_NONE;
417 }
418 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
419 trigger_machine = true;
420
421 if (!trigger_machine)
422 return IRQ_NONE;
423
424 phy_trigger_machine(phydev);
425
426 return IRQ_HANDLED;
427 }
428
dp83822_read_status(struct phy_device * phydev)429 static int dp83822_read_status(struct phy_device *phydev)
430 {
431 struct dp83822_private *dp83822 = phydev->priv;
432 int status = phy_read(phydev, MII_DP83822_PHYSTS);
433 int ctrl2;
434 int ret;
435
436 if (dp83822->fx_enabled) {
437 if (status & DP83822_PHYSTS_LINK) {
438 phydev->speed = SPEED_UNKNOWN;
439 phydev->duplex = DUPLEX_UNKNOWN;
440 } else {
441 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
442 if (ctrl2 < 0)
443 return ctrl2;
444
445 if (!(ctrl2 & DP83822_FX_ENABLE)) {
446 ret = phy_write(phydev, MII_DP83822_CTRL_2,
447 DP83822_FX_ENABLE | ctrl2);
448 if (ret < 0)
449 return ret;
450 }
451 }
452 }
453
454 ret = genphy_read_status(phydev);
455 if (ret)
456 return ret;
457
458 if (status < 0)
459 return status;
460
461 if (status & DP83822_PHYSTS_DUPLEX)
462 phydev->duplex = DUPLEX_FULL;
463 else
464 phydev->duplex = DUPLEX_HALF;
465
466 if (status & DP83822_PHYSTS_10)
467 phydev->speed = SPEED_10;
468 else
469 phydev->speed = SPEED_100;
470
471 return 0;
472 }
473
dp83822_config_init_leds(struct phy_device * phydev)474 static int dp83822_config_init_leds(struct phy_device *phydev)
475 {
476 struct dp83822_private *dp83822 = phydev->priv;
477 int ret;
478
479 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) {
480 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR,
481 DP83822_MLEDCR_ROUTE,
482 FIELD_PREP(DP83822_MLEDCR_ROUTE,
483 DP83822_MLEDCR_ROUTE_LED_0));
484 if (ret)
485 return ret;
486 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
487 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
488 DP83822_IOCTRL2_GPIO2_CTRL,
489 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
490 DP83822_IOCTRL2_GPIO2_CTRL_MLED));
491 if (ret)
492 return ret;
493 }
494
495 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) {
496 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
497 DP83822_IOCTRL1_GPIO1_CTRL,
498 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL,
499 DP83822_IOCTRL1_GPIO1_CTRL_LED_1));
500 if (ret)
501 return ret;
502 }
503
504 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) {
505 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
506 DP83822_IOCTRL1_GPIO3_CTRL,
507 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL,
508 DP83822_IOCTRL1_GPIO3_CTRL_LED3));
509 if (ret)
510 return ret;
511 }
512
513 return 0;
514 }
515
dp83822_config_init(struct phy_device * phydev)516 static int dp83822_config_init(struct phy_device *phydev)
517 {
518 struct dp83822_private *dp83822 = phydev->priv;
519 int rgmii_delay = 0;
520 s32 rx_int_delay;
521 s32 tx_int_delay;
522 int err = 0;
523 int bmcr;
524
525 if (dp83822->set_gpio2_clk_out)
526 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
527 DP83822_IOCTRL2_GPIO2_CTRL |
528 DP83822_IOCTRL2_GPIO2_CLK_SRC,
529 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
530 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) |
531 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
532 dp83822->gpio2_clk_out));
533
534 if (dp83822->tx_amplitude_100base_tx_index >= 0)
535 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL,
536 DP83822_100BASE_TX_LINE_DRIVER_SWING,
537 FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING,
538 dp83822->tx_amplitude_100base_tx_index));
539
540 if (dp83822->mac_termination_index >= 0)
541 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL,
542 DP83822_IOCTRL_MAC_IMPEDANCE_CTRL,
543 FIELD_PREP(DP83822_IOCTRL_MAC_IMPEDANCE_CTRL,
544 dp83822->mac_termination_index));
545
546 err = dp83822_config_init_leds(phydev);
547 if (err)
548 return err;
549
550 if (phy_interface_is_rgmii(phydev)) {
551 rx_int_delay = phy_get_internal_delay(phydev, NULL, 0, true);
552
553 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
554 if (rx_int_delay > 0)
555 rgmii_delay |= DP83822_RX_CLK_SHIFT;
556
557 tx_int_delay = phy_get_internal_delay(phydev, NULL, 0, false);
558
559 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
560 if (tx_int_delay <= 0)
561 rgmii_delay |= DP83822_TX_CLK_SHIFT;
562
563 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
564 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
565 if (err)
566 return err;
567
568 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
569 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
570
571 if (err)
572 return err;
573 } else {
574 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
575 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
576
577 if (err)
578 return err;
579 }
580
581 if (dp83822->fx_enabled) {
582 err = phy_modify(phydev, MII_DP83822_CTRL_2,
583 DP83822_FX_ENABLE, 1);
584 if (err < 0)
585 return err;
586
587 /* Only allow advertising what this PHY supports */
588 linkmode_and(phydev->advertising, phydev->advertising,
589 phydev->supported);
590
591 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
592 phydev->supported);
593 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
594 phydev->advertising);
595 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
596 phydev->supported);
597 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
598 phydev->supported);
599 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
600 phydev->advertising);
601 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
602 phydev->advertising);
603
604 /* Auto neg is not supported in fiber mode */
605 bmcr = phy_read(phydev, MII_BMCR);
606 if (bmcr < 0)
607 return bmcr;
608
609 if (bmcr & BMCR_ANENABLE) {
610 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
611 if (err < 0)
612 return err;
613 }
614 phydev->autoneg = AUTONEG_DISABLE;
615 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
616 phydev->supported);
617 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
618 phydev->advertising);
619
620 /* Setup fiber advertisement */
621 err = phy_modify_changed(phydev, MII_ADVERTISE,
622 MII_DP83822_FIBER_ADVERTISE,
623 MII_DP83822_FIBER_ADVERTISE);
624
625 if (err < 0)
626 return err;
627
628 if (dp83822->fx_signal_det_low) {
629 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
630 MII_DP83822_GENCFG,
631 DP83822_SIG_DET_LOW);
632 if (err)
633 return err;
634 }
635 }
636 return dp83822_config_wol(phydev, &dp83822->wol);
637 }
638
dp8382x_config_rmii_mode(struct phy_device * phydev)639 static int dp8382x_config_rmii_mode(struct phy_device *phydev)
640 {
641 struct device *dev = &phydev->mdio.dev;
642 const char *of_val;
643 int ret;
644
645 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
646 if (strcmp(of_val, "master") == 0) {
647 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
648 DP83822_RMII_MODE_SEL);
649 } else if (strcmp(of_val, "slave") == 0) {
650 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
651 DP83822_RMII_MODE_SEL);
652 } else {
653 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
654 of_val);
655 ret = -EINVAL;
656 }
657
658 if (ret)
659 return ret;
660 }
661
662 return 0;
663 }
664
dp83826_config_init(struct phy_device * phydev)665 static int dp83826_config_init(struct phy_device *phydev)
666 {
667 struct dp83822_private *dp83822 = phydev->priv;
668 u16 val, mask;
669 int ret;
670
671 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
672 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
673 DP83822_RMII_MODE_EN);
674 if (ret)
675 return ret;
676
677 ret = dp8382x_config_rmii_mode(phydev);
678 if (ret)
679 return ret;
680 } else {
681 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
682 DP83822_RMII_MODE_EN);
683 if (ret)
684 return ret;
685 }
686
687 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
688 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
689 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,
690 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
691 dp83822->cfg_dac_minus));
692 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
693 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
694 if (ret)
695 return ret;
696
697 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK,
698 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
699 dp83822->cfg_dac_minus));
700 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
701 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
702 if (ret)
703 return ret;
704 }
705
706 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) {
707 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
708 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
709 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
710 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
711 if (ret)
712 return ret;
713 }
714
715 return dp83822_config_wol(phydev, &dp83822->wol);
716 }
717
dp83825_config_init(struct phy_device * phydev)718 static int dp83825_config_init(struct phy_device *phydev)
719 {
720 struct dp83822_private *dp83822 = phydev->priv;
721 int ret;
722
723 ret = dp8382x_config_rmii_mode(phydev);
724 if (ret)
725 return ret;
726
727 return dp83822_config_wol(phydev, &dp83822->wol);
728 }
729
dp83822_phy_reset(struct phy_device * phydev)730 static int dp83822_phy_reset(struct phy_device *phydev)
731 {
732 int err;
733
734 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
735 if (err < 0)
736 return err;
737
738 return phydev->drv->config_init(phydev);
739 }
740
741 #if IS_ENABLED(CONFIG_OF_MDIO)
742 static const u32 tx_amplitude_100base_tx_gain[] = {
743 80, 82, 83, 85, 87, 88, 90, 92,
744 93, 95, 97, 98, 100, 102, 103, 105,
745 };
746
747 static const u32 mac_termination[] = {
748 99, 91, 84, 78, 73, 69, 65, 61, 58, 55, 53, 50, 48, 46, 44, 43,
749 };
750
dp83822_of_init_leds(struct phy_device * phydev)751 static int dp83822_of_init_leds(struct phy_device *phydev)
752 {
753 struct device_node *node = phydev->mdio.dev.of_node;
754 struct dp83822_private *dp83822 = phydev->priv;
755 struct device_node *leds;
756 u32 index;
757 int err;
758
759 if (!node)
760 return 0;
761
762 leds = of_get_child_by_name(node, "leds");
763 if (!leds)
764 return 0;
765
766 for_each_available_child_of_node_scoped(leds, led) {
767 err = of_property_read_u32(led, "reg", &index);
768 if (err) {
769 of_node_put(leds);
770 return err;
771 }
772
773 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) {
774 dp83822->led_pin_enable[index] = true;
775 } else {
776 of_node_put(leds);
777 return -EINVAL;
778 }
779 }
780
781 of_node_put(leds);
782 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to
783 * only one of these two pins at a time.
784 */
785 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] &&
786 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
787 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n");
788 return -EINVAL;
789 }
790
791 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] &&
792 dp83822->set_gpio2_clk_out) {
793 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n");
794 return -EINVAL;
795 }
796
797 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] &&
798 phydev->interface != PHY_INTERFACE_MODE_RMII) {
799 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n");
800 return -EINVAL;
801 }
802
803 return 0;
804 }
805
dp83822_of_init(struct phy_device * phydev)806 static int dp83822_of_init(struct phy_device *phydev)
807 {
808 struct dp83822_private *dp83822 = phydev->priv;
809 struct device *dev = &phydev->mdio.dev;
810 const char *of_val;
811 int i, ret;
812 u32 val;
813
814 /* Signal detection for the PHY is only enabled if the FX_EN and the
815 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
816 * is strapped otherwise signal detection is disabled for the PHY.
817 */
818 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
819 dp83822->fx_signal_det_low = device_property_present(dev,
820 "ti,link-loss-low");
821 if (!dp83822->fx_enabled)
822 dp83822->fx_enabled = device_property_present(dev,
823 "ti,fiber-mode");
824
825 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) {
826 if (strcmp(of_val, "mac-if") == 0) {
827 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF;
828 } else if (strcmp(of_val, "xi") == 0) {
829 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI;
830 } else if (strcmp(of_val, "int-ref") == 0) {
831 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF;
832 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {
833 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF;
834 } else if (strcmp(of_val, "free-running") == 0) {
835 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING;
836 } else if (strcmp(of_val, "recovered") == 0) {
837 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED;
838 } else {
839 phydev_err(phydev,
840 "Invalid value for ti,gpio2-clk-out property (%s)\n",
841 of_val);
842 return -EINVAL;
843 }
844
845 dp83822->set_gpio2_clk_out = true;
846 }
847
848 ret = phy_get_tx_amplitude_gain(phydev, dev,
849 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
850 &val);
851 if (!ret) {
852 for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) {
853 if (tx_amplitude_100base_tx_gain[i] == val) {
854 dp83822->tx_amplitude_100base_tx_index = i;
855 break;
856 }
857 }
858
859 if (dp83822->tx_amplitude_100base_tx_index < 0) {
860 phydev_err(phydev,
861 "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n",
862 val);
863 return -EINVAL;
864 }
865 }
866
867 ret = phy_get_mac_termination(phydev, dev, &val);
868 if (!ret) {
869 for (i = 0; i < ARRAY_SIZE(mac_termination); i++) {
870 if (mac_termination[i] == val) {
871 dp83822->mac_termination_index = i;
872 break;
873 }
874 }
875
876 if (dp83822->mac_termination_index < 0) {
877 phydev_err(phydev,
878 "Invalid value for mac-termination-ohms property (%u)\n",
879 val);
880 return -EINVAL;
881 }
882 }
883
884 return dp83822_of_init_leds(phydev);
885 }
886
dp83826_to_dac_minus_one_regval(int percent)887 static int dp83826_to_dac_minus_one_regval(int percent)
888 {
889 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent;
890
891 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
892 }
893
dp83826_to_dac_plus_one_regval(int percent)894 static int dp83826_to_dac_plus_one_regval(int percent)
895 {
896 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT;
897
898 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
899 }
900
dp83826_of_init(struct phy_device * phydev)901 static void dp83826_of_init(struct phy_device *phydev)
902 {
903 struct dp83822_private *dp83822 = phydev->priv;
904 struct device *dev = &phydev->mdio.dev;
905 u32 val;
906
907 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT;
908 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val))
909 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val);
910
911 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT;
912 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val))
913 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val);
914 }
915 #else
dp83822_of_init(struct phy_device * phydev)916 static int dp83822_of_init(struct phy_device *phydev)
917 {
918 return 0;
919 }
920
dp83826_of_init(struct phy_device * phydev)921 static void dp83826_of_init(struct phy_device *phydev)
922 {
923 }
924 #endif /* CONFIG_OF_MDIO */
925
dp83822_read_straps(struct phy_device * phydev)926 static int dp83822_read_straps(struct phy_device *phydev)
927 {
928 struct dp83822_private *dp83822 = phydev->priv;
929 int fx_enabled, fx_sd_enable;
930 int val;
931
932 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1);
933 if (val < 0)
934 return val;
935
936 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);
937
938 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
939 if (fx_enabled == DP83822_STRAP_MODE2 ||
940 fx_enabled == DP83822_STRAP_MODE3)
941 dp83822->fx_enabled = 1;
942
943 if (dp83822->fx_enabled) {
944 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
945 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
946 fx_sd_enable == DP83822_STRAP_MODE4)
947 dp83822->fx_sd_enable = 1;
948 }
949
950 return 0;
951 }
952
dp8382x_probe(struct phy_device * phydev)953 static int dp8382x_probe(struct phy_device *phydev)
954 {
955 struct dp83822_private *dp83822;
956
957 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
958 GFP_KERNEL);
959 if (!dp83822)
960 return -ENOMEM;
961
962 dp83822->tx_amplitude_100base_tx_index = -1;
963 dp83822->mac_termination_index = -1;
964 phydev->priv = dp83822;
965
966 return 0;
967 }
968
dp83822_probe(struct phy_device * phydev)969 static int dp83822_probe(struct phy_device *phydev)
970 {
971 struct dp83822_private *dp83822;
972 int ret;
973
974 ret = dp8382x_probe(phydev);
975 if (ret)
976 return ret;
977
978 dp83822 = phydev->priv;
979
980 ret = dp83822_read_straps(phydev);
981 if (ret)
982 return ret;
983
984 ret = dp83822_of_init(phydev);
985 if (ret)
986 return ret;
987
988 if (dp83822->fx_enabled)
989 phydev->port = PORT_FIBRE;
990
991 return 0;
992 }
993
dp83826_probe(struct phy_device * phydev)994 static int dp83826_probe(struct phy_device *phydev)
995 {
996 int ret;
997
998 ret = dp8382x_probe(phydev);
999 if (ret)
1000 return ret;
1001
1002 dp83826_of_init(phydev);
1003
1004 return 0;
1005 }
1006
dp83822_suspend(struct phy_device * phydev)1007 static int dp83822_suspend(struct phy_device *phydev)
1008 {
1009 int value;
1010
1011 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
1012
1013 if (!(value & DP83822_WOL_EN))
1014 genphy_suspend(phydev);
1015
1016 return 0;
1017 }
1018
dp83822_resume(struct phy_device * phydev)1019 static int dp83822_resume(struct phy_device *phydev)
1020 {
1021 int value;
1022
1023 genphy_resume(phydev);
1024
1025 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
1026
1027 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value |
1028 DP83822_WOL_CLR_INDICATION);
1029
1030 return 0;
1031 }
1032
dp83822_led_mode(u8 index,unsigned long rules)1033 static int dp83822_led_mode(u8 index, unsigned long rules)
1034 {
1035 switch (rules) {
1036 case BIT(TRIGGER_NETDEV_LINK):
1037 return DP83822_LED_FN_LINK;
1038 case BIT(TRIGGER_NETDEV_LINK_10):
1039 return DP83822_LED_FN_LINK_10_BT;
1040 case BIT(TRIGGER_NETDEV_LINK_100):
1041 return DP83822_LED_FN_LINK_100_BTX;
1042 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1043 return DP83822_LED_FN_FULL_DUPLEX;
1044 case BIT(TRIGGER_NETDEV_TX):
1045 return DP83822_LED_FN_TX;
1046 case BIT(TRIGGER_NETDEV_RX):
1047 return DP83822_LED_FN_RX;
1048 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1049 return DP83822_LED_FN_RX_TX;
1050 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR):
1051 return DP83822_LED_FN_RX_TX_ERR;
1052 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1053 return DP83822_LED_FN_LINK_RX_TX;
1054 default:
1055 return -EOPNOTSUPP;
1056 }
1057 }
1058
dp83822_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1059 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index,
1060 unsigned long rules)
1061 {
1062 int mode;
1063
1064 mode = dp83822_led_mode(index, rules);
1065 if (mode < 0)
1066 return mode;
1067
1068 return 0;
1069 }
1070
dp83822_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1071 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index,
1072 unsigned long rules)
1073 {
1074 int mode;
1075
1076 mode = dp83822_led_mode(index, rules);
1077 if (mode < 0)
1078 return mode;
1079
1080 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2)
1081 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1082 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG,
1083 FIELD_PREP(DP83822_MLEDCR_CFG, mode));
1084 else if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1085 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1086 MII_DP83822_LEDCFG1,
1087 DP83822_LEDCFG1_LED1_CTRL,
1088 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL,
1089 mode));
1090 else
1091 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1092 MII_DP83822_LEDCFG1,
1093 DP83822_LEDCFG1_LED3_CTRL,
1094 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL,
1095 mode));
1096 }
1097
dp83822_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1098 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index,
1099 unsigned long *rules)
1100 {
1101 int val;
1102
1103 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) {
1104 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR);
1105 if (val < 0)
1106 return val;
1107
1108 val = FIELD_GET(DP83822_MLEDCR_CFG, val);
1109 } else {
1110 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1);
1111 if (val < 0)
1112 return val;
1113
1114 if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1115 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val);
1116 else
1117 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val);
1118 }
1119
1120 switch (val) {
1121 case DP83822_LED_FN_LINK:
1122 *rules = BIT(TRIGGER_NETDEV_LINK);
1123 break;
1124 case DP83822_LED_FN_LINK_10_BT:
1125 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1126 break;
1127 case DP83822_LED_FN_LINK_100_BTX:
1128 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1129 break;
1130 case DP83822_LED_FN_FULL_DUPLEX:
1131 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1132 break;
1133 case DP83822_LED_FN_TX:
1134 *rules = BIT(TRIGGER_NETDEV_TX);
1135 break;
1136 case DP83822_LED_FN_RX:
1137 *rules = BIT(TRIGGER_NETDEV_RX);
1138 break;
1139 case DP83822_LED_FN_RX_TX:
1140 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1141 break;
1142 case DP83822_LED_FN_RX_TX_ERR:
1143 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR);
1144 break;
1145 case DP83822_LED_FN_LINK_RX_TX:
1146 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1147 BIT(TRIGGER_NETDEV_RX);
1148 break;
1149 default:
1150 *rules = 0;
1151 break;
1152 }
1153
1154 return 0;
1155 }
1156
1157 #define DP83822_PHY_DRIVER(_id, _name) \
1158 { \
1159 PHY_ID_MATCH_MODEL(_id), \
1160 .name = (_name), \
1161 /* PHY_BASIC_FEATURES */ \
1162 .probe = dp83822_probe, \
1163 .soft_reset = dp83822_phy_reset, \
1164 .config_init = dp83822_config_init, \
1165 .read_status = dp83822_read_status, \
1166 .get_wol = dp83822_get_wol, \
1167 .set_wol = dp83822_set_wol, \
1168 .config_intr = dp83822_config_intr, \
1169 .handle_interrupt = dp83822_handle_interrupt, \
1170 .suspend = dp83822_suspend, \
1171 .resume = dp83822_resume, \
1172 .led_hw_is_supported = dp83822_led_hw_is_supported, \
1173 .led_hw_control_set = dp83822_led_hw_control_set, \
1174 .led_hw_control_get = dp83822_led_hw_control_get, \
1175 }
1176
1177 #define DP83825_PHY_DRIVER(_id, _name) \
1178 { \
1179 PHY_ID_MATCH_MODEL(_id), \
1180 .name = (_name), \
1181 /* PHY_BASIC_FEATURES */ \
1182 .probe = dp8382x_probe, \
1183 .soft_reset = dp83822_phy_reset, \
1184 .config_init = dp83825_config_init, \
1185 .get_wol = dp83822_get_wol, \
1186 .set_wol = dp83822_set_wol, \
1187 .config_intr = dp83822_config_intr, \
1188 .handle_interrupt = dp83822_handle_interrupt, \
1189 .suspend = dp83822_suspend, \
1190 .resume = dp83822_resume, \
1191 }
1192
1193 #define DP83826_PHY_DRIVER(_id, _name) \
1194 { \
1195 PHY_ID_MATCH_MODEL(_id), \
1196 .name = (_name), \
1197 /* PHY_BASIC_FEATURES */ \
1198 .probe = dp83826_probe, \
1199 .soft_reset = dp83822_phy_reset, \
1200 .config_init = dp83826_config_init, \
1201 .get_wol = dp83822_get_wol, \
1202 .set_wol = dp83822_set_wol, \
1203 .config_intr = dp83822_config_intr, \
1204 .handle_interrupt = dp83822_handle_interrupt, \
1205 .suspend = dp83822_suspend, \
1206 .resume = dp83822_resume, \
1207 }
1208
1209 static struct phy_driver dp83822_driver[] = {
1210 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
1211 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
1212 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
1213 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
1214 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
1215 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
1216 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
1217 };
1218 module_phy_driver(dp83822_driver);
1219
1220 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = {
1221 { DP83822_PHY_ID, 0xfffffff0 },
1222 { DP83825I_PHY_ID, 0xfffffff0 },
1223 { DP83826C_PHY_ID, 0xfffffff0 },
1224 { DP83826NC_PHY_ID, 0xfffffff0 },
1225 { DP83825S_PHY_ID, 0xfffffff0 },
1226 { DP83825CM_PHY_ID, 0xfffffff0 },
1227 { DP83825CS_PHY_ID, 0xfffffff0 },
1228 { },
1229 };
1230 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
1231
1232 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
1233 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1234 MODULE_LICENSE("GPL v2");
1235