1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Faraday FTGMAC100 Gigabit Ethernet
4 *
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/clk.h>
12 #include <linux/reset.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
20 #include <linux/of.h>
21 #include <linux/of_mdio.h>
22 #include <linux/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/crc32.h>
26 #include <linux/if_vlan.h>
27 #include <linux/of_net.h>
28 #include <linux/phy_fixed.h>
29 #include <net/ip.h>
30 #include <net/ncsi.h>
31
32 #include "ftgmac100.h"
33
34 #define DRV_NAME "ftgmac100"
35
36 /* Arbitrary values, I am not sure the HW has limits */
37 #define MAX_RX_QUEUE_ENTRIES 1024
38 #define MAX_TX_QUEUE_ENTRIES 1024
39 #define MIN_RX_QUEUE_ENTRIES 32
40 #define MIN_TX_QUEUE_ENTRIES 32
41
42 /* Defaults */
43 #define DEF_RX_QUEUE_ENTRIES 128
44 #define DEF_TX_QUEUE_ENTRIES 128
45
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
48
49 /* Min number of tx ring entries before stopping queue */
50 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
51
52 #define FTGMAC_100MHZ 100000000
53 #define FTGMAC_25MHZ 25000000
54
55 /* For NC-SI to register a fixed-link phy device */
56 static struct fixed_phy_status ncsi_phy_status = {
57 .link = 1,
58 .speed = SPEED_100,
59 .duplex = DUPLEX_FULL,
60 .pause = 0,
61 .asym_pause = 0
62 };
63
64 struct ftgmac100 {
65 /* Registers */
66 struct resource *res;
67 void __iomem *base;
68
69 /* Rx ring */
70 unsigned int rx_q_entries;
71 struct ftgmac100_rxdes *rxdes;
72 dma_addr_t rxdes_dma;
73 struct sk_buff **rx_skbs;
74 unsigned int rx_pointer;
75 u32 rxdes0_edorr_mask;
76
77 /* Tx ring */
78 unsigned int tx_q_entries;
79 struct ftgmac100_txdes *txdes;
80 dma_addr_t txdes_dma;
81 struct sk_buff **tx_skbs;
82 unsigned int tx_clean_pointer;
83 unsigned int tx_pointer;
84 u32 txdes0_edotr_mask;
85
86 /* Used to signal the reset task of ring change request */
87 unsigned int new_rx_q_entries;
88 unsigned int new_tx_q_entries;
89
90 /* Scratch page to use when rx skb alloc fails */
91 void *rx_scratch;
92 dma_addr_t rx_scratch_dma;
93
94 /* Component structures */
95 struct net_device *netdev;
96 struct device *dev;
97 struct ncsi_dev *ndev;
98 struct napi_struct napi;
99 struct work_struct reset_task;
100 struct mii_bus *mii_bus;
101 struct clk *clk;
102
103 /* AST2500/AST2600 RMII ref clock gate */
104 struct clk *rclk;
105 /* Aspeed reset control */
106 struct reset_control *rst;
107
108 /* Link management */
109 int cur_speed;
110 int cur_duplex;
111 bool use_ncsi;
112
113 /* Multicast filter settings */
114 u32 maht0;
115 u32 maht1;
116
117 /* Flow control settings */
118 bool tx_pause;
119 bool rx_pause;
120 bool aneg_pause;
121
122 /* Misc */
123 bool need_mac_restart;
124 bool is_aspeed;
125 };
126
ftgmac100_reset_mac(struct ftgmac100 * priv,u32 maccr)127 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
128 {
129 struct net_device *netdev = priv->netdev;
130 int i;
131
132 /* NOTE: reset clears all registers */
133 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
134 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
135 priv->base + FTGMAC100_OFFSET_MACCR);
136 for (i = 0; i < 200; i++) {
137 unsigned int maccr;
138
139 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
140 if (!(maccr & FTGMAC100_MACCR_SW_RST))
141 return 0;
142
143 udelay(1);
144 }
145
146 netdev_err(netdev, "Hardware reset failed\n");
147 return -EIO;
148 }
149
ftgmac100_reset_and_config_mac(struct ftgmac100 * priv)150 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
151 {
152 u32 maccr = 0;
153
154 /* Aspeed RMII needs SCU reset to clear status */
155 if (priv->is_aspeed && priv->netdev->phydev->interface == PHY_INTERFACE_MODE_RMII) {
156 int err;
157
158 err = reset_control_assert(priv->rst);
159 if (err) {
160 dev_err(priv->dev, "Failed to reset mac (%d)\n", err);
161 return err;
162 }
163 usleep_range(10000, 20000);
164 err = reset_control_deassert(priv->rst);
165 if (err) {
166 dev_err(priv->dev, "Failed to deassert mac reset (%d)\n", err);
167 return err;
168 }
169 }
170
171 switch (priv->cur_speed) {
172 case SPEED_10:
173 case 0: /* no link */
174 break;
175
176 case SPEED_100:
177 maccr |= FTGMAC100_MACCR_FAST_MODE;
178 break;
179
180 case SPEED_1000:
181 maccr |= FTGMAC100_MACCR_GIGA_MODE;
182 break;
183 default:
184 netdev_err(priv->netdev, "Unknown speed %d !\n",
185 priv->cur_speed);
186 break;
187 }
188
189 /* (Re)initialize the queue pointers */
190 priv->rx_pointer = 0;
191 priv->tx_clean_pointer = 0;
192 priv->tx_pointer = 0;
193
194 /* The doc says reset twice with 10us interval */
195 if (ftgmac100_reset_mac(priv, maccr))
196 return -EIO;
197 usleep_range(10, 1000);
198 return ftgmac100_reset_mac(priv, maccr);
199 }
200
ftgmac100_write_mac_addr(struct ftgmac100 * priv,const u8 * mac)201 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
202 {
203 unsigned int maddr = mac[0] << 8 | mac[1];
204 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
205
206 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
207 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
208 }
209
ftgmac100_initial_mac(struct ftgmac100 * priv)210 static int ftgmac100_initial_mac(struct ftgmac100 *priv)
211 {
212 u8 mac[ETH_ALEN];
213 unsigned int m;
214 unsigned int l;
215 int err;
216
217 err = of_get_ethdev_address(priv->dev->of_node, priv->netdev);
218 if (err == -EPROBE_DEFER)
219 return err;
220 if (!err) {
221 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
222 priv->netdev->dev_addr);
223 return 0;
224 }
225
226 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
227 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
228
229 mac[0] = (m >> 8) & 0xff;
230 mac[1] = m & 0xff;
231 mac[2] = (l >> 24) & 0xff;
232 mac[3] = (l >> 16) & 0xff;
233 mac[4] = (l >> 8) & 0xff;
234 mac[5] = l & 0xff;
235
236 if (is_valid_ether_addr(mac)) {
237 eth_hw_addr_set(priv->netdev, mac);
238 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
239 } else {
240 eth_hw_addr_random(priv->netdev);
241 dev_info(priv->dev, "Generated random MAC address %pM\n",
242 priv->netdev->dev_addr);
243 }
244
245 return 0;
246 }
247
ftgmac100_set_mac_addr(struct net_device * dev,void * p)248 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
249 {
250 int ret;
251
252 ret = eth_prepare_mac_addr_change(dev, p);
253 if (ret < 0)
254 return ret;
255
256 eth_commit_mac_addr_change(dev, p);
257 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
258
259 return 0;
260 }
261
ftgmac100_config_pause(struct ftgmac100 * priv)262 static void ftgmac100_config_pause(struct ftgmac100 *priv)
263 {
264 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
265
266 /* Throttle tx queue when receiving pause frames */
267 if (priv->rx_pause)
268 fcr |= FTGMAC100_FCR_FC_EN;
269
270 /* Enables sending pause frames when the RX queue is past a
271 * certain threshold.
272 */
273 if (priv->tx_pause)
274 fcr |= FTGMAC100_FCR_FCTHR_EN;
275
276 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
277 }
278
ftgmac100_init_hw(struct ftgmac100 * priv)279 static void ftgmac100_init_hw(struct ftgmac100 *priv)
280 {
281 u32 reg, rfifo_sz, tfifo_sz;
282
283 /* Clear stale interrupts */
284 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
285 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
286
287 /* Setup RX ring buffer base */
288 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
289
290 /* Setup TX ring buffer base */
291 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
292
293 /* Configure RX buffer size */
294 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
295 priv->base + FTGMAC100_OFFSET_RBSR);
296
297 /* Set RX descriptor autopoll */
298 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
299 priv->base + FTGMAC100_OFFSET_APTC);
300
301 /* Write MAC address */
302 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
303
304 /* Write multicast filter */
305 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
306 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
307
308 /* Configure descriptor sizes and increase burst sizes according
309 * to values in Aspeed SDK. The FIFO arbitration is enabled and
310 * the thresholds set based on the recommended values in the
311 * AST2400 specification.
312 */
313 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
314 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
315 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
316 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
317 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
318 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
319 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
320 priv->base + FTGMAC100_OFFSET_DBLAC);
321
322 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
323 * mitigation doesn't seem to provide any benefit with NAPI so leave
324 * it at that.
325 */
326 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
327 FTGMAC100_ITC_TXINT_THR(1),
328 priv->base + FTGMAC100_OFFSET_ITC);
329
330 /* Configure FIFO sizes in the TPAFCR register */
331 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
332 rfifo_sz = reg & 0x00000007;
333 tfifo_sz = (reg >> 3) & 0x00000007;
334 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
335 reg &= ~0x3f000000;
336 reg |= (tfifo_sz << 27);
337 reg |= (rfifo_sz << 24);
338 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
339 }
340
ftgmac100_start_hw(struct ftgmac100 * priv)341 static void ftgmac100_start_hw(struct ftgmac100 *priv)
342 {
343 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
344
345 /* Keep the original GMAC and FAST bits */
346 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
347
348 /* Add all the main enable bits */
349 maccr |= FTGMAC100_MACCR_TXDMA_EN |
350 FTGMAC100_MACCR_RXDMA_EN |
351 FTGMAC100_MACCR_TXMAC_EN |
352 FTGMAC100_MACCR_RXMAC_EN |
353 FTGMAC100_MACCR_CRC_APD |
354 FTGMAC100_MACCR_PHY_LINK_LEVEL |
355 FTGMAC100_MACCR_RX_RUNT |
356 FTGMAC100_MACCR_RX_BROADPKT;
357
358 /* Add other bits as needed */
359 if (priv->cur_duplex == DUPLEX_FULL)
360 maccr |= FTGMAC100_MACCR_FULLDUP;
361 if (priv->netdev->flags & IFF_PROMISC)
362 maccr |= FTGMAC100_MACCR_RX_ALL;
363 if (priv->netdev->flags & IFF_ALLMULTI)
364 maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
365 else if (netdev_mc_count(priv->netdev))
366 maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
367
368 /* Vlan filtering enabled */
369 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
370 maccr |= FTGMAC100_MACCR_RM_VLAN;
371
372 /* Hit the HW */
373 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
374 }
375
ftgmac100_stop_hw(struct ftgmac100 * priv)376 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
377 {
378 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
379 }
380
ftgmac100_calc_mc_hash(struct ftgmac100 * priv)381 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
382 {
383 struct netdev_hw_addr *ha;
384
385 priv->maht1 = 0;
386 priv->maht0 = 0;
387 netdev_for_each_mc_addr(ha, priv->netdev) {
388 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
389
390 crc_val = (~(crc_val >> 2)) & 0x3f;
391 if (crc_val >= 32)
392 priv->maht1 |= 1ul << (crc_val - 32);
393 else
394 priv->maht0 |= 1ul << (crc_val);
395 }
396 }
397
ftgmac100_set_rx_mode(struct net_device * netdev)398 static void ftgmac100_set_rx_mode(struct net_device *netdev)
399 {
400 struct ftgmac100 *priv = netdev_priv(netdev);
401
402 /* Setup the hash filter */
403 ftgmac100_calc_mc_hash(priv);
404
405 /* Interface down ? that's all there is to do */
406 if (!netif_running(netdev))
407 return;
408
409 /* Update the HW */
410 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
411 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
412
413 /* Reconfigure MACCR */
414 ftgmac100_start_hw(priv);
415 }
416
ftgmac100_alloc_rx_buf(struct ftgmac100 * priv,unsigned int entry,struct ftgmac100_rxdes * rxdes,gfp_t gfp)417 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
418 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
419 {
420 struct net_device *netdev = priv->netdev;
421 struct sk_buff *skb;
422 dma_addr_t map;
423 int err = 0;
424
425 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
426 if (unlikely(!skb)) {
427 if (net_ratelimit())
428 netdev_warn(netdev, "failed to allocate rx skb\n");
429 err = -ENOMEM;
430 map = priv->rx_scratch_dma;
431 } else {
432 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
433 DMA_FROM_DEVICE);
434 if (unlikely(dma_mapping_error(priv->dev, map))) {
435 if (net_ratelimit())
436 netdev_err(netdev, "failed to map rx page\n");
437 dev_kfree_skb_any(skb);
438 map = priv->rx_scratch_dma;
439 skb = NULL;
440 err = -ENOMEM;
441 }
442 }
443
444 /* Store skb */
445 priv->rx_skbs[entry] = skb;
446
447 /* Store DMA address into RX desc */
448 rxdes->rxdes3 = cpu_to_le32(map);
449
450 /* Ensure the above is ordered vs clearing the OWN bit */
451 dma_wmb();
452
453 /* Clean status (which resets own bit) */
454 if (entry == (priv->rx_q_entries - 1))
455 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
456 else
457 rxdes->rxdes0 = 0;
458
459 return err;
460 }
461
ftgmac100_next_rx_pointer(struct ftgmac100 * priv,unsigned int pointer)462 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
463 unsigned int pointer)
464 {
465 return (pointer + 1) & (priv->rx_q_entries - 1);
466 }
467
ftgmac100_rx_packet_error(struct ftgmac100 * priv,u32 status)468 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
469 {
470 struct net_device *netdev = priv->netdev;
471
472 if (status & FTGMAC100_RXDES0_RX_ERR)
473 netdev->stats.rx_errors++;
474
475 if (status & FTGMAC100_RXDES0_CRC_ERR)
476 netdev->stats.rx_crc_errors++;
477
478 if (status & (FTGMAC100_RXDES0_FTL |
479 FTGMAC100_RXDES0_RUNT |
480 FTGMAC100_RXDES0_RX_ODD_NB))
481 netdev->stats.rx_length_errors++;
482 }
483
ftgmac100_rx_packet(struct ftgmac100 * priv,int * processed)484 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
485 {
486 struct net_device *netdev = priv->netdev;
487 struct ftgmac100_rxdes *rxdes;
488 struct sk_buff *skb;
489 unsigned int pointer, size;
490 u32 status, csum_vlan;
491 dma_addr_t map;
492
493 /* Grab next RX descriptor */
494 pointer = priv->rx_pointer;
495 rxdes = &priv->rxdes[pointer];
496
497 /* Grab descriptor status */
498 status = le32_to_cpu(rxdes->rxdes0);
499
500 /* Do we have a packet ? */
501 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
502 return false;
503
504 /* Order subsequent reads with the test for the ready bit */
505 dma_rmb();
506
507 /* We don't cope with fragmented RX packets */
508 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
509 !(status & FTGMAC100_RXDES0_LRS)))
510 goto drop;
511
512 /* Grab received size and csum vlan field in the descriptor */
513 size = status & FTGMAC100_RXDES0_VDBC;
514 csum_vlan = le32_to_cpu(rxdes->rxdes1);
515
516 /* Any error (other than csum offload) flagged ? */
517 if (unlikely(status & RXDES0_ANY_ERROR)) {
518 /* Correct for incorrect flagging of runt packets
519 * with vlan tags... Just accept a runt packet that
520 * has been flagged as vlan and whose size is at
521 * least 60 bytes.
522 */
523 if ((status & FTGMAC100_RXDES0_RUNT) &&
524 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
525 (size >= 60))
526 status &= ~FTGMAC100_RXDES0_RUNT;
527
528 /* Any error still in there ? */
529 if (status & RXDES0_ANY_ERROR) {
530 ftgmac100_rx_packet_error(priv, status);
531 goto drop;
532 }
533 }
534
535 /* If the packet had no skb (failed to allocate earlier)
536 * then try to allocate one and skip
537 */
538 skb = priv->rx_skbs[pointer];
539 if (!unlikely(skb)) {
540 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
541 goto drop;
542 }
543
544 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
545 netdev->stats.multicast++;
546
547 /* If the HW found checksum errors, bounce it to software.
548 *
549 * If we didn't, we need to see if the packet was recognized
550 * by HW as one of the supported checksummed protocols before
551 * we accept the HW test results.
552 */
553 if (netdev->features & NETIF_F_RXCSUM) {
554 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
555 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
556 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
557 if ((csum_vlan & err_bits) ||
558 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
559 skb->ip_summed = CHECKSUM_NONE;
560 else
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 }
563
564 /* Transfer received size to skb */
565 skb_put(skb, size);
566
567 /* Extract vlan tag */
568 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
569 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
570 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
571 csum_vlan & 0xffff);
572
573 /* Tear down DMA mapping, do necessary cache management */
574 map = le32_to_cpu(rxdes->rxdes3);
575
576 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
577 /* When we don't have an iommu, we can save cycles by not
578 * invalidating the cache for the part of the packet that
579 * wasn't received.
580 */
581 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
582 #else
583 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
584 #endif
585
586
587 /* Resplenish rx ring */
588 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
589 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
590
591 skb->protocol = eth_type_trans(skb, netdev);
592
593 netdev->stats.rx_packets++;
594 netdev->stats.rx_bytes += size;
595
596 /* push packet to protocol stack */
597 if (skb->ip_summed == CHECKSUM_NONE)
598 netif_receive_skb(skb);
599 else
600 napi_gro_receive(&priv->napi, skb);
601
602 (*processed)++;
603 return true;
604
605 drop:
606 /* Clean rxdes0 (which resets own bit) */
607 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
608 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
609 netdev->stats.rx_dropped++;
610 return true;
611 }
612
ftgmac100_base_tx_ctlstat(struct ftgmac100 * priv,unsigned int index)613 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
614 unsigned int index)
615 {
616 if (index == (priv->tx_q_entries - 1))
617 return priv->txdes0_edotr_mask;
618 else
619 return 0;
620 }
621
ftgmac100_next_tx_pointer(struct ftgmac100 * priv,unsigned int pointer)622 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
623 unsigned int pointer)
624 {
625 return (pointer + 1) & (priv->tx_q_entries - 1);
626 }
627
ftgmac100_tx_buf_avail(struct ftgmac100 * priv)628 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
629 {
630 /* Returns the number of available slots in the TX queue
631 *
632 * This always leaves one free slot so we don't have to
633 * worry about empty vs. full, and this simplifies the
634 * test for ftgmac100_tx_buf_cleanable() below
635 */
636 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
637 (priv->tx_q_entries - 1);
638 }
639
ftgmac100_tx_buf_cleanable(struct ftgmac100 * priv)640 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
641 {
642 return priv->tx_pointer != priv->tx_clean_pointer;
643 }
644
ftgmac100_free_tx_packet(struct ftgmac100 * priv,unsigned int pointer,struct sk_buff * skb,struct ftgmac100_txdes * txdes,u32 ctl_stat)645 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
646 unsigned int pointer,
647 struct sk_buff *skb,
648 struct ftgmac100_txdes *txdes,
649 u32 ctl_stat)
650 {
651 dma_addr_t map = le32_to_cpu(txdes->txdes3);
652 size_t len;
653
654 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
655 len = skb_headlen(skb);
656 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
657 } else {
658 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
659 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
660 }
661
662 /* Free SKB on last segment */
663 if (ctl_stat & FTGMAC100_TXDES0_LTS)
664 dev_kfree_skb(skb);
665 priv->tx_skbs[pointer] = NULL;
666 }
667
ftgmac100_tx_complete_packet(struct ftgmac100 * priv)668 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
669 {
670 struct net_device *netdev = priv->netdev;
671 struct ftgmac100_txdes *txdes;
672 struct sk_buff *skb;
673 unsigned int pointer;
674 u32 ctl_stat;
675
676 pointer = priv->tx_clean_pointer;
677 txdes = &priv->txdes[pointer];
678
679 ctl_stat = le32_to_cpu(txdes->txdes0);
680 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
681 return false;
682
683 skb = priv->tx_skbs[pointer];
684 netdev->stats.tx_packets++;
685 netdev->stats.tx_bytes += skb->len;
686 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
687 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
688
689 /* Ensure the descriptor config is visible before setting the tx
690 * pointer.
691 */
692 smp_wmb();
693
694 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
695
696 return true;
697 }
698
ftgmac100_tx_complete(struct ftgmac100 * priv)699 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
700 {
701 struct net_device *netdev = priv->netdev;
702
703 /* Process all completed packets */
704 while (ftgmac100_tx_buf_cleanable(priv) &&
705 ftgmac100_tx_complete_packet(priv))
706 ;
707
708 /* Restart queue if needed */
709 smp_mb();
710 if (unlikely(netif_queue_stopped(netdev) &&
711 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
712 struct netdev_queue *txq;
713
714 txq = netdev_get_tx_queue(netdev, 0);
715 __netif_tx_lock(txq, smp_processor_id());
716 if (netif_queue_stopped(netdev) &&
717 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
718 netif_wake_queue(netdev);
719 __netif_tx_unlock(txq);
720 }
721 }
722
ftgmac100_prep_tx_csum(struct sk_buff * skb,u32 * csum_vlan)723 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
724 {
725 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
726 u8 ip_proto = ip_hdr(skb)->protocol;
727
728 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
729 switch(ip_proto) {
730 case IPPROTO_TCP:
731 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
732 return true;
733 case IPPROTO_UDP:
734 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
735 return true;
736 case IPPROTO_IP:
737 return true;
738 }
739 }
740 return skb_checksum_help(skb) == 0;
741 }
742
ftgmac100_hard_start_xmit(struct sk_buff * skb,struct net_device * netdev)743 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
744 struct net_device *netdev)
745 {
746 struct ftgmac100 *priv = netdev_priv(netdev);
747 struct ftgmac100_txdes *txdes, *first;
748 unsigned int pointer, nfrags, len, i, j;
749 u32 f_ctl_stat, ctl_stat, csum_vlan;
750 dma_addr_t map;
751
752 /* The HW doesn't pad small frames */
753 if (eth_skb_pad(skb)) {
754 netdev->stats.tx_dropped++;
755 return NETDEV_TX_OK;
756 }
757
758 /* Reject oversize packets */
759 if (unlikely(skb->len > MAX_PKT_SIZE)) {
760 if (net_ratelimit())
761 netdev_dbg(netdev, "tx packet too big\n");
762 goto drop;
763 }
764
765 /* Do we have a limit on #fragments ? I yet have to get a reply
766 * from Aspeed. If there's one I haven't hit it.
767 */
768 nfrags = skb_shinfo(skb)->nr_frags;
769
770 /* Setup HW checksumming */
771 csum_vlan = 0;
772 if (skb->ip_summed == CHECKSUM_PARTIAL &&
773 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
774 goto drop;
775
776 /* Add VLAN tag */
777 if (skb_vlan_tag_present(skb)) {
778 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
779 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
780 }
781
782 /* Get header len */
783 len = skb_headlen(skb);
784
785 /* Map the packet head */
786 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
787 if (dma_mapping_error(priv->dev, map)) {
788 if (net_ratelimit())
789 netdev_err(netdev, "map tx packet head failed\n");
790 goto drop;
791 }
792
793 /* Grab the next free tx descriptor */
794 pointer = priv->tx_pointer;
795 txdes = first = &priv->txdes[pointer];
796
797 /* Setup it up with the packet head. Don't write the head to the
798 * ring just yet
799 */
800 priv->tx_skbs[pointer] = skb;
801 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
802 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
803 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
804 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
805 if (nfrags == 0)
806 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
807 txdes->txdes3 = cpu_to_le32(map);
808 txdes->txdes1 = cpu_to_le32(csum_vlan);
809
810 /* Next descriptor */
811 pointer = ftgmac100_next_tx_pointer(priv, pointer);
812
813 /* Add the fragments */
814 for (i = 0; i < nfrags; i++) {
815 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
816
817 len = skb_frag_size(frag);
818
819 /* Map it */
820 map = skb_frag_dma_map(priv->dev, frag, 0, len,
821 DMA_TO_DEVICE);
822 if (dma_mapping_error(priv->dev, map))
823 goto dma_err;
824
825 /* Setup descriptor */
826 priv->tx_skbs[pointer] = skb;
827 txdes = &priv->txdes[pointer];
828 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
829 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
830 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
831 if (i == (nfrags - 1))
832 ctl_stat |= FTGMAC100_TXDES0_LTS;
833 txdes->txdes0 = cpu_to_le32(ctl_stat);
834 txdes->txdes1 = 0;
835 txdes->txdes3 = cpu_to_le32(map);
836
837 /* Next one */
838 pointer = ftgmac100_next_tx_pointer(priv, pointer);
839 }
840
841 /* Order the previous packet and descriptor udpates
842 * before setting the OWN bit on the first descriptor.
843 */
844 dma_wmb();
845 first->txdes0 = cpu_to_le32(f_ctl_stat);
846
847 /* Ensure the descriptor config is visible before setting the tx
848 * pointer.
849 */
850 smp_wmb();
851
852 /* Update next TX pointer */
853 priv->tx_pointer = pointer;
854
855 /* If there isn't enough room for all the fragments of a new packet
856 * in the TX ring, stop the queue. The sequence below is race free
857 * vs. a concurrent restart in ftgmac100_poll()
858 */
859 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
860 netif_stop_queue(netdev);
861 /* Order the queue stop with the test below */
862 smp_mb();
863 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
864 netif_wake_queue(netdev);
865 }
866
867 /* Poke transmitter to read the updated TX descriptors */
868 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
869
870 return NETDEV_TX_OK;
871
872 dma_err:
873 if (net_ratelimit())
874 netdev_err(netdev, "map tx fragment failed\n");
875
876 /* Free head */
877 pointer = priv->tx_pointer;
878 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
879 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
880
881 /* Then all fragments */
882 for (j = 0; j < i; j++) {
883 pointer = ftgmac100_next_tx_pointer(priv, pointer);
884 txdes = &priv->txdes[pointer];
885 ctl_stat = le32_to_cpu(txdes->txdes0);
886 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
887 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
888 }
889
890 /* This cannot be reached if we successfully mapped the
891 * last fragment, so we know ftgmac100_free_tx_packet()
892 * hasn't freed the skb yet.
893 */
894 drop:
895 /* Drop the packet */
896 dev_kfree_skb_any(skb);
897 netdev->stats.tx_dropped++;
898
899 return NETDEV_TX_OK;
900 }
901
ftgmac100_free_buffers(struct ftgmac100 * priv)902 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
903 {
904 int i;
905
906 /* Free all RX buffers */
907 for (i = 0; i < priv->rx_q_entries; i++) {
908 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
909 struct sk_buff *skb = priv->rx_skbs[i];
910 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
911
912 if (!skb)
913 continue;
914
915 priv->rx_skbs[i] = NULL;
916 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
917 dev_kfree_skb_any(skb);
918 }
919
920 /* Free all TX buffers */
921 for (i = 0; i < priv->tx_q_entries; i++) {
922 struct ftgmac100_txdes *txdes = &priv->txdes[i];
923 struct sk_buff *skb = priv->tx_skbs[i];
924
925 if (!skb)
926 continue;
927 ftgmac100_free_tx_packet(priv, i, skb, txdes,
928 le32_to_cpu(txdes->txdes0));
929 }
930 }
931
ftgmac100_free_rings(struct ftgmac100 * priv)932 static void ftgmac100_free_rings(struct ftgmac100 *priv)
933 {
934 /* Free skb arrays */
935 kfree(priv->rx_skbs);
936 kfree(priv->tx_skbs);
937
938 /* Free descriptors */
939 if (priv->rxdes)
940 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
941 sizeof(struct ftgmac100_rxdes),
942 priv->rxdes, priv->rxdes_dma);
943 priv->rxdes = NULL;
944
945 if (priv->txdes)
946 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
947 sizeof(struct ftgmac100_txdes),
948 priv->txdes, priv->txdes_dma);
949 priv->txdes = NULL;
950
951 /* Free scratch packet buffer */
952 if (priv->rx_scratch)
953 dma_free_coherent(priv->dev, RX_BUF_SIZE,
954 priv->rx_scratch, priv->rx_scratch_dma);
955 }
956
ftgmac100_alloc_rings(struct ftgmac100 * priv)957 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
958 {
959 /* Allocate skb arrays */
960 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
961 GFP_KERNEL);
962 if (!priv->rx_skbs)
963 return -ENOMEM;
964 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
965 GFP_KERNEL);
966 if (!priv->tx_skbs)
967 return -ENOMEM;
968
969 /* Allocate descriptors */
970 priv->rxdes = dma_alloc_coherent(priv->dev,
971 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
972 &priv->rxdes_dma, GFP_KERNEL);
973 if (!priv->rxdes)
974 return -ENOMEM;
975 priv->txdes = dma_alloc_coherent(priv->dev,
976 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
977 &priv->txdes_dma, GFP_KERNEL);
978 if (!priv->txdes)
979 return -ENOMEM;
980
981 /* Allocate scratch packet buffer */
982 priv->rx_scratch = dma_alloc_coherent(priv->dev,
983 RX_BUF_SIZE,
984 &priv->rx_scratch_dma,
985 GFP_KERNEL);
986 if (!priv->rx_scratch)
987 return -ENOMEM;
988
989 return 0;
990 }
991
ftgmac100_init_rings(struct ftgmac100 * priv)992 static void ftgmac100_init_rings(struct ftgmac100 *priv)
993 {
994 struct ftgmac100_rxdes *rxdes = NULL;
995 struct ftgmac100_txdes *txdes = NULL;
996 int i;
997
998 /* Update entries counts */
999 priv->rx_q_entries = priv->new_rx_q_entries;
1000 priv->tx_q_entries = priv->new_tx_q_entries;
1001
1002 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
1003 return;
1004
1005 /* Initialize RX ring */
1006 for (i = 0; i < priv->rx_q_entries; i++) {
1007 rxdes = &priv->rxdes[i];
1008 rxdes->rxdes0 = 0;
1009 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
1010 }
1011 /* Mark the end of the ring */
1012 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
1013
1014 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
1015 return;
1016
1017 /* Initialize TX ring */
1018 for (i = 0; i < priv->tx_q_entries; i++) {
1019 txdes = &priv->txdes[i];
1020 txdes->txdes0 = 0;
1021 }
1022 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
1023 }
1024
ftgmac100_alloc_rx_buffers(struct ftgmac100 * priv)1025 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
1026 {
1027 int i;
1028
1029 for (i = 0; i < priv->rx_q_entries; i++) {
1030 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
1031
1032 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
1033 return -ENOMEM;
1034 }
1035 return 0;
1036 }
1037
ftgmac100_mdiobus_read(struct mii_bus * bus,int phy_addr,int regnum)1038 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1039 {
1040 struct net_device *netdev = bus->priv;
1041 struct ftgmac100 *priv = netdev_priv(netdev);
1042 unsigned int phycr;
1043 int i;
1044
1045 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1046
1047 /* preserve MDC cycle threshold */
1048 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1049
1050 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1051 FTGMAC100_PHYCR_REGAD(regnum) |
1052 FTGMAC100_PHYCR_MIIRD;
1053
1054 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1055
1056 for (i = 0; i < 10; i++) {
1057 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1058
1059 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1060 int data;
1061
1062 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1063 return FTGMAC100_PHYDATA_MIIRDATA(data);
1064 }
1065
1066 udelay(100);
1067 }
1068
1069 netdev_err(netdev, "mdio read timed out\n");
1070 return -EIO;
1071 }
1072
ftgmac100_mdiobus_write(struct mii_bus * bus,int phy_addr,int regnum,u16 value)1073 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1074 int regnum, u16 value)
1075 {
1076 struct net_device *netdev = bus->priv;
1077 struct ftgmac100 *priv = netdev_priv(netdev);
1078 unsigned int phycr;
1079 int data;
1080 int i;
1081
1082 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1083
1084 /* preserve MDC cycle threshold */
1085 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1086
1087 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1088 FTGMAC100_PHYCR_REGAD(regnum) |
1089 FTGMAC100_PHYCR_MIIWR;
1090
1091 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1092
1093 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1094 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1095
1096 for (i = 0; i < 10; i++) {
1097 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1098
1099 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1100 return 0;
1101
1102 udelay(100);
1103 }
1104
1105 netdev_err(netdev, "mdio write timed out\n");
1106 return -EIO;
1107 }
1108
ftgmac100_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)1109 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1110 struct ethtool_drvinfo *info)
1111 {
1112 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1113 strscpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1114 }
1115
1116 static void
ftgmac100_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)1117 ftgmac100_get_ringparam(struct net_device *netdev,
1118 struct ethtool_ringparam *ering,
1119 struct kernel_ethtool_ringparam *kernel_ering,
1120 struct netlink_ext_ack *extack)
1121 {
1122 struct ftgmac100 *priv = netdev_priv(netdev);
1123
1124 memset(ering, 0, sizeof(*ering));
1125 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1126 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1127 ering->rx_pending = priv->rx_q_entries;
1128 ering->tx_pending = priv->tx_q_entries;
1129 }
1130
1131 static int
ftgmac100_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)1132 ftgmac100_set_ringparam(struct net_device *netdev,
1133 struct ethtool_ringparam *ering,
1134 struct kernel_ethtool_ringparam *kernel_ering,
1135 struct netlink_ext_ack *extack)
1136 {
1137 struct ftgmac100 *priv = netdev_priv(netdev);
1138
1139 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1140 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1141 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1142 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1143 !is_power_of_2(ering->rx_pending) ||
1144 !is_power_of_2(ering->tx_pending))
1145 return -EINVAL;
1146
1147 priv->new_rx_q_entries = ering->rx_pending;
1148 priv->new_tx_q_entries = ering->tx_pending;
1149 if (netif_running(netdev))
1150 schedule_work(&priv->reset_task);
1151
1152 return 0;
1153 }
1154
ftgmac100_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)1155 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1156 struct ethtool_pauseparam *pause)
1157 {
1158 struct ftgmac100 *priv = netdev_priv(netdev);
1159
1160 pause->autoneg = priv->aneg_pause;
1161 pause->tx_pause = priv->tx_pause;
1162 pause->rx_pause = priv->rx_pause;
1163 }
1164
ftgmac100_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)1165 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1166 struct ethtool_pauseparam *pause)
1167 {
1168 struct ftgmac100 *priv = netdev_priv(netdev);
1169 struct phy_device *phydev = netdev->phydev;
1170
1171 priv->aneg_pause = pause->autoneg;
1172 priv->tx_pause = pause->tx_pause;
1173 priv->rx_pause = pause->rx_pause;
1174
1175 if (phydev)
1176 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1177
1178 if (netif_running(netdev)) {
1179 if (!(phydev && priv->aneg_pause))
1180 ftgmac100_config_pause(priv);
1181 }
1182
1183 return 0;
1184 }
1185
1186 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1187 .get_drvinfo = ftgmac100_get_drvinfo,
1188 .get_link = ethtool_op_get_link,
1189 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1190 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1191 .nway_reset = phy_ethtool_nway_reset,
1192 .get_ringparam = ftgmac100_get_ringparam,
1193 .set_ringparam = ftgmac100_set_ringparam,
1194 .get_pauseparam = ftgmac100_get_pauseparam,
1195 .set_pauseparam = ftgmac100_set_pauseparam,
1196 };
1197
ftgmac100_interrupt(int irq,void * dev_id)1198 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1199 {
1200 struct net_device *netdev = dev_id;
1201 struct ftgmac100 *priv = netdev_priv(netdev);
1202 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1203
1204 /* Fetch and clear interrupt bits, process abnormal ones */
1205 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1206 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1207 if (unlikely(status & FTGMAC100_INT_BAD)) {
1208
1209 /* RX buffer unavailable */
1210 if (status & FTGMAC100_INT_NO_RXBUF)
1211 netdev->stats.rx_over_errors++;
1212
1213 /* received packet lost due to RX FIFO full */
1214 if (status & FTGMAC100_INT_RPKT_LOST)
1215 netdev->stats.rx_fifo_errors++;
1216
1217 /* sent packet lost due to excessive TX collision */
1218 if (status & FTGMAC100_INT_XPKT_LOST)
1219 netdev->stats.tx_fifo_errors++;
1220
1221 /* AHB error -> Reset the chip */
1222 if (status & FTGMAC100_INT_AHB_ERR) {
1223 if (net_ratelimit())
1224 netdev_warn(netdev,
1225 "AHB bus error ! Resetting chip.\n");
1226 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1227 schedule_work(&priv->reset_task);
1228 return IRQ_HANDLED;
1229 }
1230
1231 /* We may need to restart the MAC after such errors, delay
1232 * this until after we have freed some Rx buffers though
1233 */
1234 priv->need_mac_restart = true;
1235
1236 /* Disable those errors until we restart */
1237 new_mask &= ~status;
1238 }
1239
1240 /* Only enable "bad" interrupts while NAPI is on */
1241 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1242
1243 /* Schedule NAPI bh */
1244 napi_schedule_irqoff(&priv->napi);
1245
1246 return IRQ_HANDLED;
1247 }
1248
ftgmac100_check_rx(struct ftgmac100 * priv)1249 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1250 {
1251 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1252
1253 /* Do we have a packet ? */
1254 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1255 }
1256
ftgmac100_poll(struct napi_struct * napi,int budget)1257 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1258 {
1259 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1260 int work_done = 0;
1261 bool more;
1262
1263 /* Handle TX completions */
1264 if (ftgmac100_tx_buf_cleanable(priv))
1265 ftgmac100_tx_complete(priv);
1266
1267 /* Handle RX packets */
1268 do {
1269 more = ftgmac100_rx_packet(priv, &work_done);
1270 } while (more && work_done < budget);
1271
1272
1273 /* The interrupt is telling us to kick the MAC back to life
1274 * after an RX overflow
1275 */
1276 if (unlikely(priv->need_mac_restart)) {
1277 ftgmac100_start_hw(priv);
1278 priv->need_mac_restart = false;
1279
1280 /* Re-enable "bad" interrupts */
1281 iowrite32(FTGMAC100_INT_BAD,
1282 priv->base + FTGMAC100_OFFSET_IER);
1283 }
1284
1285 /* As long as we are waiting for transmit packets to be
1286 * completed we keep NAPI going
1287 */
1288 if (ftgmac100_tx_buf_cleanable(priv))
1289 work_done = budget;
1290
1291 if (work_done < budget) {
1292 /* We are about to re-enable all interrupts. However
1293 * the HW has been latching RX/TX packet interrupts while
1294 * they were masked. So we clear them first, then we need
1295 * to re-check if there's something to process
1296 */
1297 iowrite32(FTGMAC100_INT_RXTX,
1298 priv->base + FTGMAC100_OFFSET_ISR);
1299
1300 /* Push the above (and provides a barrier vs. subsequent
1301 * reads of the descriptor).
1302 */
1303 ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1304
1305 /* Check RX and TX descriptors for more work to do */
1306 if (ftgmac100_check_rx(priv) ||
1307 ftgmac100_tx_buf_cleanable(priv))
1308 return budget;
1309
1310 /* deschedule NAPI */
1311 napi_complete(napi);
1312
1313 /* enable all interrupts */
1314 iowrite32(FTGMAC100_INT_ALL,
1315 priv->base + FTGMAC100_OFFSET_IER);
1316 }
1317
1318 return work_done;
1319 }
1320
ftgmac100_init_all(struct ftgmac100 * priv,bool ignore_alloc_err)1321 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1322 {
1323 int err = 0;
1324
1325 /* Re-init descriptors (adjust queue sizes) */
1326 ftgmac100_init_rings(priv);
1327
1328 /* Realloc rx descriptors */
1329 err = ftgmac100_alloc_rx_buffers(priv);
1330 if (err && !ignore_alloc_err)
1331 return err;
1332
1333 /* Reinit and restart HW */
1334 ftgmac100_init_hw(priv);
1335 ftgmac100_config_pause(priv);
1336 ftgmac100_start_hw(priv);
1337
1338 /* Re-enable the device */
1339 napi_enable(&priv->napi);
1340 netif_start_queue(priv->netdev);
1341
1342 /* Enable all interrupts */
1343 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1344
1345 return err;
1346 }
1347
ftgmac100_reset(struct ftgmac100 * priv)1348 static void ftgmac100_reset(struct ftgmac100 *priv)
1349 {
1350 struct net_device *netdev = priv->netdev;
1351 int err;
1352
1353 netdev_dbg(netdev, "Resetting NIC...\n");
1354
1355 /* Lock the world */
1356 rtnl_lock();
1357 if (netdev->phydev)
1358 mutex_lock(&netdev->phydev->lock);
1359 if (priv->mii_bus)
1360 mutex_lock(&priv->mii_bus->mdio_lock);
1361
1362
1363 /* Check if the interface is still up */
1364 if (!netif_running(netdev))
1365 goto bail;
1366
1367 /* Stop the network stack */
1368 netif_trans_update(netdev);
1369 napi_disable(&priv->napi);
1370 netif_tx_disable(netdev);
1371
1372 /* Stop and reset the MAC */
1373 ftgmac100_stop_hw(priv);
1374 err = ftgmac100_reset_and_config_mac(priv);
1375 if (err) {
1376 /* Not much we can do ... it might come back... */
1377 netdev_err(netdev, "attempting to continue...\n");
1378 }
1379
1380 /* Free all rx and tx buffers */
1381 ftgmac100_free_buffers(priv);
1382
1383 /* Setup everything again and restart chip */
1384 ftgmac100_init_all(priv, true);
1385
1386 netdev_dbg(netdev, "Reset done !\n");
1387 bail:
1388 if (priv->mii_bus)
1389 mutex_unlock(&priv->mii_bus->mdio_lock);
1390 if (netdev->phydev)
1391 mutex_unlock(&netdev->phydev->lock);
1392 rtnl_unlock();
1393 }
1394
ftgmac100_reset_task(struct work_struct * work)1395 static void ftgmac100_reset_task(struct work_struct *work)
1396 {
1397 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1398 reset_task);
1399
1400 ftgmac100_reset(priv);
1401 }
1402
ftgmac100_adjust_link(struct net_device * netdev)1403 static void ftgmac100_adjust_link(struct net_device *netdev)
1404 {
1405 struct ftgmac100 *priv = netdev_priv(netdev);
1406 struct phy_device *phydev = netdev->phydev;
1407 bool tx_pause, rx_pause;
1408 int new_speed;
1409
1410 /* We store "no link" as speed 0 */
1411 if (!phydev->link)
1412 new_speed = 0;
1413 else
1414 new_speed = phydev->speed;
1415
1416 /* Grab pause settings from PHY if configured to do so */
1417 if (priv->aneg_pause) {
1418 rx_pause = tx_pause = phydev->pause;
1419 if (phydev->asym_pause)
1420 tx_pause = !rx_pause;
1421 } else {
1422 rx_pause = priv->rx_pause;
1423 tx_pause = priv->tx_pause;
1424 }
1425
1426 /* Link hasn't changed, do nothing */
1427 if (phydev->speed == priv->cur_speed &&
1428 phydev->duplex == priv->cur_duplex &&
1429 rx_pause == priv->rx_pause &&
1430 tx_pause == priv->tx_pause)
1431 return;
1432
1433 /* Print status if we have a link or we had one and just lost it,
1434 * don't print otherwise.
1435 */
1436 if (new_speed || priv->cur_speed)
1437 phy_print_status(phydev);
1438
1439 priv->cur_speed = new_speed;
1440 priv->cur_duplex = phydev->duplex;
1441 priv->rx_pause = rx_pause;
1442 priv->tx_pause = tx_pause;
1443
1444 /* Link is down, do nothing else */
1445 if (!new_speed)
1446 return;
1447
1448 /* Disable all interrupts */
1449 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1450
1451 /* Release phy lock to allow ftgmac100_reset to acquire it, keeping lock
1452 * order consistent to prevent dead lock.
1453 */
1454 if (netdev->phydev)
1455 mutex_unlock(&netdev->phydev->lock);
1456
1457 ftgmac100_reset(priv);
1458
1459 if (netdev->phydev)
1460 mutex_lock(&netdev->phydev->lock);
1461
1462 }
1463
ftgmac100_mii_probe(struct net_device * netdev)1464 static int ftgmac100_mii_probe(struct net_device *netdev)
1465 {
1466 struct ftgmac100 *priv = netdev_priv(netdev);
1467 struct platform_device *pdev = to_platform_device(priv->dev);
1468 struct device_node *np = pdev->dev.of_node;
1469 struct phy_device *phydev;
1470 phy_interface_t phy_intf;
1471 int err;
1472
1473 /* Default to RGMII. It's a gigabit part after all */
1474 err = of_get_phy_mode(np, &phy_intf);
1475 if (err)
1476 phy_intf = PHY_INTERFACE_MODE_RGMII;
1477
1478 /* Aspeed only supports these. I don't know about other IP
1479 * block vendors so I'm going to just let them through for
1480 * now. Note that this is only a warning if for some obscure
1481 * reason the DT really means to lie about it or it's a newer
1482 * part we don't know about.
1483 *
1484 * On the Aspeed SoC there are additionally straps and SCU
1485 * control bits that could tell us what the interface is
1486 * (or allow us to configure it while the IP block is held
1487 * in reset). For now I chose to keep this driver away from
1488 * those SoC specific bits and assume the device-tree is
1489 * right and the SCU has been configured properly by pinmux
1490 * or the firmware.
1491 */
1492 if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
1493 netdev_warn(netdev,
1494 "Unsupported PHY mode %s !\n",
1495 phy_modes(phy_intf));
1496 }
1497
1498 phydev = phy_find_first(priv->mii_bus);
1499 if (!phydev) {
1500 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1501 return -ENODEV;
1502 }
1503
1504 phydev = phy_connect(netdev, phydev_name(phydev),
1505 &ftgmac100_adjust_link, phy_intf);
1506
1507 if (IS_ERR(phydev)) {
1508 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1509 return PTR_ERR(phydev);
1510 }
1511
1512 /* Indicate that we support PAUSE frames (see comment in
1513 * Documentation/networking/phy.rst)
1514 */
1515 phy_support_asym_pause(phydev);
1516
1517 /* Display what we found */
1518 phy_attached_info(phydev);
1519
1520 return 0;
1521 }
1522
ftgmac100_open(struct net_device * netdev)1523 static int ftgmac100_open(struct net_device *netdev)
1524 {
1525 struct ftgmac100 *priv = netdev_priv(netdev);
1526 int err;
1527
1528 /* Allocate ring buffers */
1529 err = ftgmac100_alloc_rings(priv);
1530 if (err) {
1531 netdev_err(netdev, "Failed to allocate descriptors\n");
1532 return err;
1533 }
1534
1535 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1536 *
1537 * Otherwise we leave it set to 0 (no link), the link
1538 * message from the PHY layer will handle setting it up to
1539 * something else if needed.
1540 */
1541 if (priv->use_ncsi) {
1542 priv->cur_duplex = DUPLEX_FULL;
1543 priv->cur_speed = SPEED_100;
1544 } else {
1545 priv->cur_duplex = 0;
1546 priv->cur_speed = 0;
1547 }
1548
1549 /* Reset the hardware */
1550 err = ftgmac100_reset_and_config_mac(priv);
1551 if (err)
1552 goto err_hw;
1553
1554 /* Initialize NAPI */
1555 netif_napi_add(netdev, &priv->napi, ftgmac100_poll);
1556
1557 /* Grab our interrupt */
1558 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1559 if (err) {
1560 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1561 goto err_irq;
1562 }
1563
1564 /* Start things up */
1565 err = ftgmac100_init_all(priv, false);
1566 if (err) {
1567 netdev_err(netdev, "Failed to allocate packet buffers\n");
1568 goto err_alloc;
1569 }
1570
1571 if (netdev->phydev) {
1572 /* If we have a PHY, start polling */
1573 phy_start(netdev->phydev);
1574 }
1575 if (priv->use_ncsi) {
1576 /* If using NC-SI, set our carrier on and start the stack */
1577 netif_carrier_on(netdev);
1578
1579 /* Start the NCSI device */
1580 err = ncsi_start_dev(priv->ndev);
1581 if (err)
1582 goto err_ncsi;
1583 }
1584
1585 return 0;
1586
1587 err_ncsi:
1588 phy_stop(netdev->phydev);
1589 napi_disable(&priv->napi);
1590 netif_stop_queue(netdev);
1591 err_alloc:
1592 ftgmac100_free_buffers(priv);
1593 free_irq(netdev->irq, netdev);
1594 err_irq:
1595 netif_napi_del(&priv->napi);
1596 err_hw:
1597 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1598 ftgmac100_free_rings(priv);
1599 return err;
1600 }
1601
ftgmac100_stop(struct net_device * netdev)1602 static int ftgmac100_stop(struct net_device *netdev)
1603 {
1604 struct ftgmac100 *priv = netdev_priv(netdev);
1605
1606 /* Note about the reset task: We are called with the rtnl lock
1607 * held, so we are synchronized against the core of the reset
1608 * task. We must not try to synchronously cancel it otherwise
1609 * we can deadlock. But since it will test for netif_running()
1610 * which has already been cleared by the net core, we don't
1611 * anything special to do.
1612 */
1613
1614 /* disable all interrupts */
1615 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1616
1617 netif_stop_queue(netdev);
1618 napi_disable(&priv->napi);
1619 netif_napi_del(&priv->napi);
1620 if (netdev->phydev)
1621 phy_stop(netdev->phydev);
1622 if (priv->use_ncsi)
1623 ncsi_stop_dev(priv->ndev);
1624
1625 ftgmac100_stop_hw(priv);
1626 free_irq(netdev->irq, netdev);
1627 ftgmac100_free_buffers(priv);
1628 ftgmac100_free_rings(priv);
1629
1630 return 0;
1631 }
1632
ftgmac100_tx_timeout(struct net_device * netdev,unsigned int txqueue)1633 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1634 {
1635 struct ftgmac100 *priv = netdev_priv(netdev);
1636
1637 /* Disable all interrupts */
1638 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1639
1640 /* Do the reset outside of interrupt context */
1641 schedule_work(&priv->reset_task);
1642 }
1643
ftgmac100_set_features(struct net_device * netdev,netdev_features_t features)1644 static int ftgmac100_set_features(struct net_device *netdev,
1645 netdev_features_t features)
1646 {
1647 struct ftgmac100 *priv = netdev_priv(netdev);
1648 netdev_features_t changed = netdev->features ^ features;
1649
1650 if (!netif_running(netdev))
1651 return 0;
1652
1653 /* Update the vlan filtering bit */
1654 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1655 u32 maccr;
1656
1657 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1658 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1659 maccr |= FTGMAC100_MACCR_RM_VLAN;
1660 else
1661 maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1662 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1663 }
1664
1665 return 0;
1666 }
1667
1668 #ifdef CONFIG_NET_POLL_CONTROLLER
ftgmac100_poll_controller(struct net_device * netdev)1669 static void ftgmac100_poll_controller(struct net_device *netdev)
1670 {
1671 unsigned long flags;
1672
1673 local_irq_save(flags);
1674 ftgmac100_interrupt(netdev->irq, netdev);
1675 local_irq_restore(flags);
1676 }
1677 #endif
1678
1679 static const struct net_device_ops ftgmac100_netdev_ops = {
1680 .ndo_open = ftgmac100_open,
1681 .ndo_stop = ftgmac100_stop,
1682 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1683 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1684 .ndo_validate_addr = eth_validate_addr,
1685 .ndo_eth_ioctl = phy_do_ioctl,
1686 .ndo_tx_timeout = ftgmac100_tx_timeout,
1687 .ndo_set_rx_mode = ftgmac100_set_rx_mode,
1688 .ndo_set_features = ftgmac100_set_features,
1689 #ifdef CONFIG_NET_POLL_CONTROLLER
1690 .ndo_poll_controller = ftgmac100_poll_controller,
1691 #endif
1692 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid,
1693 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid,
1694 };
1695
ftgmac100_setup_mdio(struct net_device * netdev)1696 static int ftgmac100_setup_mdio(struct net_device *netdev)
1697 {
1698 struct ftgmac100 *priv = netdev_priv(netdev);
1699 struct platform_device *pdev = to_platform_device(priv->dev);
1700 struct device_node *np = pdev->dev.of_node;
1701 struct device_node *mdio_np;
1702 int i, err = 0;
1703 u32 reg;
1704
1705 /* initialize mdio bus */
1706 priv->mii_bus = mdiobus_alloc();
1707 if (!priv->mii_bus)
1708 return -EIO;
1709
1710 if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1711 of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1712 /* The AST2600 has a separate MDIO controller */
1713
1714 /* For the AST2400 and AST2500 this driver only supports the
1715 * old MDIO interface
1716 */
1717 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1718 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1719 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1720 }
1721
1722 priv->mii_bus->name = "ftgmac100_mdio";
1723 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1724 pdev->name, pdev->id);
1725 priv->mii_bus->parent = priv->dev;
1726 priv->mii_bus->priv = priv->netdev;
1727 priv->mii_bus->read = ftgmac100_mdiobus_read;
1728 priv->mii_bus->write = ftgmac100_mdiobus_write;
1729
1730 for (i = 0; i < PHY_MAX_ADDR; i++)
1731 priv->mii_bus->irq[i] = PHY_POLL;
1732
1733 mdio_np = of_get_child_by_name(np, "mdio");
1734
1735 err = of_mdiobus_register(priv->mii_bus, mdio_np);
1736 if (err) {
1737 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1738 goto err_register_mdiobus;
1739 }
1740
1741 of_node_put(mdio_np);
1742
1743 return 0;
1744
1745 err_register_mdiobus:
1746 mdiobus_free(priv->mii_bus);
1747 return err;
1748 }
1749
ftgmac100_phy_disconnect(struct net_device * netdev)1750 static void ftgmac100_phy_disconnect(struct net_device *netdev)
1751 {
1752 struct ftgmac100 *priv = netdev_priv(netdev);
1753
1754 if (!netdev->phydev)
1755 return;
1756
1757 phy_disconnect(netdev->phydev);
1758 if (of_phy_is_fixed_link(priv->dev->of_node))
1759 of_phy_deregister_fixed_link(priv->dev->of_node);
1760
1761 if (priv->use_ncsi)
1762 fixed_phy_unregister(netdev->phydev);
1763 }
1764
ftgmac100_destroy_mdio(struct net_device * netdev)1765 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1766 {
1767 struct ftgmac100 *priv = netdev_priv(netdev);
1768
1769 if (!priv->mii_bus)
1770 return;
1771
1772 mdiobus_unregister(priv->mii_bus);
1773 mdiobus_free(priv->mii_bus);
1774 }
1775
ftgmac100_ncsi_handler(struct ncsi_dev * nd)1776 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1777 {
1778 if (unlikely(nd->state != ncsi_dev_state_functional))
1779 return;
1780
1781 netdev_dbg(nd->dev, "NCSI interface %s\n",
1782 nd->link_up ? "up" : "down");
1783 }
1784
ftgmac100_setup_clk(struct ftgmac100 * priv)1785 static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1786 {
1787 struct clk *clk;
1788 int rc;
1789
1790 clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1791 if (IS_ERR(clk))
1792 return PTR_ERR(clk);
1793 priv->clk = clk;
1794 rc = clk_prepare_enable(priv->clk);
1795 if (rc)
1796 return rc;
1797
1798 /* Aspeed specifies a 100MHz clock is required for up to
1799 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1800 * is sufficient
1801 */
1802 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1803 FTGMAC_100MHZ);
1804 if (rc)
1805 goto cleanup_clk;
1806
1807 /* RCLK is for RMII, typically used for NCSI. Optional because it's not
1808 * necessary if it's the AST2400 MAC, or the MAC is configured for
1809 * RGMII, or the controller is not an ASPEED-based controller.
1810 */
1811 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1812 rc = clk_prepare_enable(priv->rclk);
1813 if (!rc)
1814 return 0;
1815
1816 cleanup_clk:
1817 clk_disable_unprepare(priv->clk);
1818
1819 return rc;
1820 }
1821
ftgmac100_has_child_node(struct device_node * np,const char * name)1822 static bool ftgmac100_has_child_node(struct device_node *np, const char *name)
1823 {
1824 struct device_node *child_np = of_get_child_by_name(np, name);
1825 bool ret = false;
1826
1827 if (child_np) {
1828 ret = true;
1829 of_node_put(child_np);
1830 }
1831
1832 return ret;
1833 }
1834
ftgmac100_probe(struct platform_device * pdev)1835 static int ftgmac100_probe(struct platform_device *pdev)
1836 {
1837 struct resource *res;
1838 int irq;
1839 struct net_device *netdev;
1840 struct phy_device *phydev;
1841 struct ftgmac100 *priv;
1842 struct device_node *np;
1843 int err = 0;
1844
1845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1846 if (!res)
1847 return -ENXIO;
1848
1849 irq = platform_get_irq(pdev, 0);
1850 if (irq < 0)
1851 return irq;
1852
1853 /* setup net_device */
1854 netdev = alloc_etherdev(sizeof(*priv));
1855 if (!netdev) {
1856 err = -ENOMEM;
1857 goto err_alloc_etherdev;
1858 }
1859
1860 SET_NETDEV_DEV(netdev, &pdev->dev);
1861
1862 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1863 netdev->netdev_ops = &ftgmac100_netdev_ops;
1864 netdev->watchdog_timeo = 5 * HZ;
1865
1866 platform_set_drvdata(pdev, netdev);
1867
1868 /* setup private data */
1869 priv = netdev_priv(netdev);
1870 priv->netdev = netdev;
1871 priv->dev = &pdev->dev;
1872 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1873
1874 /* map io memory */
1875 priv->res = request_mem_region(res->start, resource_size(res),
1876 dev_name(&pdev->dev));
1877 if (!priv->res) {
1878 dev_err(&pdev->dev, "Could not reserve memory region\n");
1879 err = -ENOMEM;
1880 goto err_req_mem;
1881 }
1882
1883 priv->base = ioremap(res->start, resource_size(res));
1884 if (!priv->base) {
1885 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1886 err = -EIO;
1887 goto err_ioremap;
1888 }
1889
1890 netdev->irq = irq;
1891
1892 /* Enable pause */
1893 priv->tx_pause = true;
1894 priv->rx_pause = true;
1895 priv->aneg_pause = true;
1896
1897 /* MAC address from chip or random one */
1898 err = ftgmac100_initial_mac(priv);
1899 if (err)
1900 goto err_phy_connect;
1901
1902 np = pdev->dev.of_node;
1903 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1904 of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1905 of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1906 priv->rxdes0_edorr_mask = BIT(30);
1907 priv->txdes0_edotr_mask = BIT(30);
1908 priv->is_aspeed = true;
1909 } else {
1910 priv->rxdes0_edorr_mask = BIT(15);
1911 priv->txdes0_edotr_mask = BIT(15);
1912 }
1913
1914 if (np && of_get_property(np, "use-ncsi", NULL)) {
1915 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1916 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1917 err = -EINVAL;
1918 goto err_phy_connect;
1919 }
1920
1921 dev_info(&pdev->dev, "Using NCSI interface\n");
1922 priv->use_ncsi = true;
1923 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1924 if (!priv->ndev) {
1925 err = -EINVAL;
1926 goto err_phy_connect;
1927 }
1928
1929 phydev = fixed_phy_register(&ncsi_phy_status, np);
1930 if (IS_ERR(phydev)) {
1931 dev_err(&pdev->dev, "failed to register fixed PHY device\n");
1932 err = PTR_ERR(phydev);
1933 goto err_phy_connect;
1934 }
1935 err = phy_connect_direct(netdev, phydev, ftgmac100_adjust_link,
1936 PHY_INTERFACE_MODE_RMII);
1937 if (err) {
1938 dev_err(&pdev->dev, "Connecting PHY failed\n");
1939 goto err_phy_connect;
1940 }
1941 } else if (np && (of_phy_is_fixed_link(np) ||
1942 of_get_property(np, "phy-handle", NULL))) {
1943 struct phy_device *phy;
1944
1945 /* Support "mdio"/"phy" child nodes for ast2400/2500 with
1946 * an embedded MDIO controller. Automatically scan the DTS for
1947 * available PHYs and register them.
1948 */
1949 if (of_get_property(np, "phy-handle", NULL) &&
1950 (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1951 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1952 err = ftgmac100_setup_mdio(netdev);
1953 if (err)
1954 goto err_setup_mdio;
1955 }
1956
1957 phy = of_phy_get_and_connect(priv->netdev, np,
1958 &ftgmac100_adjust_link);
1959 if (!phy) {
1960 dev_err(&pdev->dev, "Failed to connect to phy\n");
1961 err = -EINVAL;
1962 goto err_phy_connect;
1963 }
1964
1965 /* Indicate that we support PAUSE frames (see comment in
1966 * Documentation/networking/phy.rst)
1967 */
1968 phy_support_asym_pause(phy);
1969
1970 /* Display what we found */
1971 phy_attached_info(phy);
1972 } else if (np && !ftgmac100_has_child_node(np, "mdio")) {
1973 /* Support legacy ASPEED devicetree descriptions that decribe a
1974 * MAC with an embedded MDIO controller but have no "mdio"
1975 * child node. Automatically scan the MDIO bus for available
1976 * PHYs.
1977 */
1978 priv->use_ncsi = false;
1979 err = ftgmac100_setup_mdio(netdev);
1980 if (err)
1981 goto err_setup_mdio;
1982
1983 err = ftgmac100_mii_probe(netdev);
1984 if (err) {
1985 dev_err(priv->dev, "MII probe failed!\n");
1986 goto err_ncsi_dev;
1987 }
1988
1989 }
1990
1991 priv->rst = devm_reset_control_get_optional_exclusive(priv->dev, NULL);
1992 if (IS_ERR(priv->rst)) {
1993 err = PTR_ERR(priv->rst);
1994 goto err_phy_connect;
1995 }
1996
1997 if (priv->is_aspeed) {
1998 err = ftgmac100_setup_clk(priv);
1999 if (err)
2000 goto err_phy_connect;
2001
2002 /* Disable ast2600 problematic HW arbitration */
2003 if (of_device_is_compatible(np, "aspeed,ast2600-mac"))
2004 iowrite32(FTGMAC100_TM_DEFAULT,
2005 priv->base + FTGMAC100_OFFSET_TM);
2006 }
2007
2008 /* Default ring sizes */
2009 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
2010 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
2011
2012 /* Base feature set */
2013 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
2014 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
2015 NETIF_F_HW_VLAN_CTAG_TX;
2016
2017 if (priv->use_ncsi)
2018 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2019
2020 /* AST2400 doesn't have working HW checksum generation */
2021 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
2022 netdev->hw_features &= ~NETIF_F_HW_CSUM;
2023
2024 /* AST2600 tx checksum with NCSI is broken */
2025 if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac"))
2026 netdev->hw_features &= ~NETIF_F_HW_CSUM;
2027
2028 if (np && of_get_property(np, "no-hw-checksum", NULL))
2029 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
2030 netdev->features |= netdev->hw_features;
2031
2032 /* register network device */
2033 err = register_netdev(netdev);
2034 if (err) {
2035 dev_err(&pdev->dev, "Failed to register netdev\n");
2036 goto err_register_netdev;
2037 }
2038
2039 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
2040
2041 return 0;
2042
2043 err_register_netdev:
2044 clk_disable_unprepare(priv->rclk);
2045 clk_disable_unprepare(priv->clk);
2046 err_phy_connect:
2047 ftgmac100_phy_disconnect(netdev);
2048 err_ncsi_dev:
2049 if (priv->ndev)
2050 ncsi_unregister_dev(priv->ndev);
2051 ftgmac100_destroy_mdio(netdev);
2052 err_setup_mdio:
2053 iounmap(priv->base);
2054 err_ioremap:
2055 release_resource(priv->res);
2056 err_req_mem:
2057 free_netdev(netdev);
2058 err_alloc_etherdev:
2059 return err;
2060 }
2061
ftgmac100_remove(struct platform_device * pdev)2062 static void ftgmac100_remove(struct platform_device *pdev)
2063 {
2064 struct net_device *netdev;
2065 struct ftgmac100 *priv;
2066
2067 netdev = platform_get_drvdata(pdev);
2068 priv = netdev_priv(netdev);
2069
2070 if (priv->ndev)
2071 ncsi_unregister_dev(priv->ndev);
2072 unregister_netdev(netdev);
2073
2074 clk_disable_unprepare(priv->rclk);
2075 clk_disable_unprepare(priv->clk);
2076
2077 /* There's a small chance the reset task will have been re-queued,
2078 * during stop, make sure it's gone before we free the structure.
2079 */
2080 cancel_work_sync(&priv->reset_task);
2081
2082 ftgmac100_phy_disconnect(netdev);
2083 ftgmac100_destroy_mdio(netdev);
2084
2085 iounmap(priv->base);
2086 release_resource(priv->res);
2087
2088 netif_napi_del(&priv->napi);
2089 free_netdev(netdev);
2090 }
2091
2092 static const struct of_device_id ftgmac100_of_match[] = {
2093 { .compatible = "faraday,ftgmac100" },
2094 { }
2095 };
2096 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
2097
2098 static struct platform_driver ftgmac100_driver = {
2099 .probe = ftgmac100_probe,
2100 .remove = ftgmac100_remove,
2101 .driver = {
2102 .name = DRV_NAME,
2103 .of_match_table = ftgmac100_of_match,
2104 },
2105 };
2106 module_platform_driver(ftgmac100_driver);
2107
2108 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
2109 MODULE_DESCRIPTION("FTGMAC100 driver");
2110 MODULE_LICENSE("GPL");
2111