1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/firmware/imx/sm.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 static const char * const inc_mode[] = { 45 "On enabled and bitcount increment", "On enabled" 46 }; 47 48 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum, 49 FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode); 50 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum, 51 FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode); 52 53 static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = { 54 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_SAI_TTCTL, 55 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0, 56 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 57 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum, 58 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 59 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_SAI_TTCTL, 60 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0, 61 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 62 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_SAI_TTCTL, 63 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0, 64 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 65 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_SAI_TTCTN, 66 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 67 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_SAI_TBCTN, 68 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 69 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_SAI_TTCAP, 70 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 71 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_SAI_RTCTL, 72 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0, 73 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 74 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum, 75 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 76 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_SAI_RTCTL, 77 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0, 78 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 79 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_SAI_RTCTL, 80 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0, 81 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 82 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_SAI_RTCTN, 83 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 84 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_SAI_RBCTN, 85 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 86 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_SAI_RTCAP, 87 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 88 }; 89 90 /** 91 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 92 * 93 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 94 * or Receiver's for both streams. This function is used to check if clocks of 95 * the stream's are synced by the opposite stream. 96 * 97 * @sai: SAI context 98 * @dir: stream direction 99 */ 100 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 101 { 102 int adir = (dir == TX) ? RX : TX; 103 104 /* current dir in async mode while opposite dir in sync mode */ 105 return !sai->synchronous[dir] && sai->synchronous[adir]; 106 } 107 108 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 109 { 110 struct pinctrl_state *state = NULL; 111 112 if (sai->is_pdm_mode) { 113 /* DSD512@44.1kHz, DSD512@48kHz */ 114 if (bclk >= 22579200) 115 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 116 117 /* Get default DSD state */ 118 if (IS_ERR_OR_NULL(state)) 119 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 120 } else { 121 /* 706k32b2c, 768k32b2c, etc */ 122 if (bclk >= 45158400) 123 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 124 } 125 126 /* Get default state */ 127 if (IS_ERR_OR_NULL(state)) 128 state = pinctrl_lookup_state(sai->pinctrl, "default"); 129 130 return state; 131 } 132 133 static irqreturn_t fsl_sai_isr(int irq, void *devid) 134 { 135 struct fsl_sai *sai = (struct fsl_sai *)devid; 136 unsigned int ofs = sai->soc_data->reg_offset; 137 struct device *dev = &sai->pdev->dev; 138 u32 flags, xcsr, mask; 139 irqreturn_t iret = IRQ_NONE; 140 141 /* 142 * Both IRQ status bits and IRQ mask bits are in the xCSR but 143 * different shifts. And we here create a mask only for those 144 * IRQs that we activated. 145 */ 146 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 147 148 /* Tx IRQ */ 149 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 150 flags = xcsr & mask; 151 152 if (flags) 153 iret = IRQ_HANDLED; 154 else 155 goto irq_rx; 156 157 if (flags & FSL_SAI_CSR_WSF) 158 dev_dbg(dev, "isr: Start of Tx word detected\n"); 159 160 if (flags & FSL_SAI_CSR_SEF) 161 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 162 163 if (flags & FSL_SAI_CSR_FEF) 164 dev_dbg(dev, "isr: Transmit underrun detected\n"); 165 166 if (flags & FSL_SAI_CSR_FWF) 167 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 168 169 if (flags & FSL_SAI_CSR_FRF) 170 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 171 172 flags &= FSL_SAI_CSR_xF_W_MASK; 173 xcsr &= ~FSL_SAI_CSR_xF_MASK; 174 175 if (flags) 176 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 177 178 irq_rx: 179 /* Rx IRQ */ 180 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 181 flags = xcsr & mask; 182 183 if (flags) 184 iret = IRQ_HANDLED; 185 else 186 goto out; 187 188 if (flags & FSL_SAI_CSR_WSF) 189 dev_dbg(dev, "isr: Start of Rx word detected\n"); 190 191 if (flags & FSL_SAI_CSR_SEF) 192 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 193 194 if (flags & FSL_SAI_CSR_FEF) 195 dev_dbg(dev, "isr: Receive overflow detected\n"); 196 197 if (flags & FSL_SAI_CSR_FWF) 198 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 199 200 if (flags & FSL_SAI_CSR_FRF) 201 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 202 203 flags &= FSL_SAI_CSR_xF_W_MASK; 204 xcsr &= ~FSL_SAI_CSR_xF_MASK; 205 206 if (flags) 207 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 208 209 out: 210 return iret; 211 } 212 213 static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 214 u32 rx_mask, int slots, int slot_width) 215 { 216 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 217 bool tx = true; 218 219 sai->slots[tx] = slots; 220 sai->slot_width[tx] = slot_width; 221 222 return 0; 223 } 224 225 static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 226 u32 rx_mask, int slots, int slot_width) 227 { 228 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 229 bool tx = false; 230 231 sai->slots[tx] = slots; 232 sai->slot_width[tx] = slot_width; 233 234 return 0; 235 } 236 237 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 238 u32 rx_mask, int slots, int slot_width) 239 { 240 int ret; 241 242 ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 243 if (ret) 244 return ret; 245 246 return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 247 } 248 249 static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots, 250 unsigned int *tx_mask, unsigned int *rx_mask) 251 { 252 /* Leave it empty, don't change the value of tx_mask and rx_mask */ 253 return 0; 254 } 255 256 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 257 unsigned int ratio) 258 { 259 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 260 261 sai->bclk_ratio = ratio; 262 263 return 0; 264 } 265 266 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 267 int clk_id, unsigned int freq, bool tx) 268 { 269 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 270 unsigned int ofs = sai->soc_data->reg_offset; 271 u32 val_cr2 = 0; 272 273 switch (clk_id) { 274 case FSL_SAI_CLK_BUS: 275 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 276 break; 277 case FSL_SAI_CLK_MAST1: 278 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 279 break; 280 case FSL_SAI_CLK_MAST2: 281 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 282 break; 283 case FSL_SAI_CLK_MAST3: 284 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 291 FSL_SAI_CR2_MSEL_MASK, val_cr2); 292 293 return 0; 294 } 295 296 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 297 { 298 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 299 int ret; 300 301 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 302 sai->pll8k_clk, sai->pll11k_clk, freq); 303 304 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 305 if (ret < 0) 306 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 307 308 return ret; 309 } 310 311 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 312 int clk_id, unsigned int freq, int dir) 313 { 314 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 315 int ret; 316 317 if (dir == SND_SOC_CLOCK_IN) 318 return 0; 319 320 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 321 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 322 return -EINVAL; 323 } 324 325 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 326 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 327 return -EINVAL; 328 } 329 330 if (sai->mclk_streams == 0 && freq > 0) { 331 ret = fsl_sai_set_mclk_rate(cpu_dai, 332 clk_id ? clk_id : FSL_SAI_CLK_MAST1, 333 freq); 334 if (ret < 0) 335 return ret; 336 } 337 338 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 339 if (ret) { 340 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 341 return ret; 342 } 343 344 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 345 if (ret) 346 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 347 348 return ret; 349 } 350 351 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 352 unsigned int fmt, bool tx) 353 { 354 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 355 unsigned int ofs = sai->soc_data->reg_offset; 356 u32 val_cr2 = 0, val_cr4 = 0; 357 358 if (sai->is_bit_clock_swap) 359 val_cr2 |= FSL_SAI_CR2_BCS; 360 361 if (!sai->is_lsb_first) 362 val_cr4 |= FSL_SAI_CR4_MF; 363 364 sai->is_pdm_mode = false; 365 sai->is_dsp_mode[tx] = false; 366 /* DAI mode */ 367 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 368 case SND_SOC_DAIFMT_I2S: 369 /* 370 * Frame low, 1clk before data, one word length for frame sync, 371 * frame sync starts one serial clock cycle earlier, 372 * that is, together with the last bit of the previous 373 * data word. 374 */ 375 val_cr2 |= FSL_SAI_CR2_BCP; 376 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 377 break; 378 case SND_SOC_DAIFMT_LEFT_J: 379 /* 380 * Frame high, one word length for frame sync, 381 * frame sync asserts with the first bit of the frame. 382 */ 383 val_cr2 |= FSL_SAI_CR2_BCP; 384 break; 385 case SND_SOC_DAIFMT_DSP_A: 386 /* 387 * Frame high, 1clk before data, one bit for frame sync, 388 * frame sync starts one serial clock cycle earlier, 389 * that is, together with the last bit of the previous 390 * data word. 391 */ 392 val_cr2 |= FSL_SAI_CR2_BCP; 393 val_cr4 |= FSL_SAI_CR4_FSE; 394 sai->is_dsp_mode[tx] = true; 395 break; 396 case SND_SOC_DAIFMT_DSP_B: 397 /* 398 * Frame high, one bit for frame sync, 399 * frame sync asserts with the first bit of the frame. 400 */ 401 val_cr2 |= FSL_SAI_CR2_BCP; 402 sai->is_dsp_mode[tx] = true; 403 break; 404 case SND_SOC_DAIFMT_PDM: 405 val_cr2 |= FSL_SAI_CR2_BCP; 406 sai->is_pdm_mode = true; 407 break; 408 case SND_SOC_DAIFMT_RIGHT_J: 409 /* To be done */ 410 default: 411 return -EINVAL; 412 } 413 414 /* DAI clock inversion */ 415 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 416 case SND_SOC_DAIFMT_IB_IF: 417 /* Invert both clocks */ 418 val_cr2 ^= FSL_SAI_CR2_BCP; 419 val_cr4 ^= FSL_SAI_CR4_FSP; 420 break; 421 case SND_SOC_DAIFMT_IB_NF: 422 /* Invert bit clock */ 423 val_cr2 ^= FSL_SAI_CR2_BCP; 424 break; 425 case SND_SOC_DAIFMT_NB_IF: 426 /* Invert frame clock */ 427 val_cr4 ^= FSL_SAI_CR4_FSP; 428 break; 429 case SND_SOC_DAIFMT_NB_NF: 430 /* Nothing to do for both normal cases */ 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 /* DAI clock provider masks */ 437 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 438 case SND_SOC_DAIFMT_BP_FP: 439 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 440 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 441 sai->is_consumer_mode[tx] = false; 442 break; 443 case SND_SOC_DAIFMT_BC_FC: 444 sai->is_consumer_mode[tx] = true; 445 break; 446 case SND_SOC_DAIFMT_BP_FC: 447 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 448 sai->is_consumer_mode[tx] = false; 449 break; 450 case SND_SOC_DAIFMT_BC_FP: 451 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 452 sai->is_consumer_mode[tx] = true; 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 459 FSL_SAI_CR2_BCS | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, 460 val_cr2); 461 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 462 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 463 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 464 465 return 0; 466 } 467 468 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 469 { 470 int ret; 471 472 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 473 if (ret) { 474 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 475 return ret; 476 } 477 478 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 479 if (ret) 480 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 481 482 return ret; 483 } 484 485 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 486 { 487 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 488 } 489 490 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 491 { 492 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 493 } 494 495 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 496 { 497 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 498 unsigned int reg, ofs = sai->soc_data->reg_offset; 499 unsigned long clk_rate; 500 u32 savediv = 0, ratio, bestdiff = freq; 501 int adir = tx ? RX : TX; 502 int dir = tx ? TX : RX; 503 u32 id; 504 bool support_1_1_ratio = sai->verid.version >= 0x0301; 505 506 /* Don't apply to consumer mode */ 507 if (sai->is_consumer_mode[tx]) 508 return 0; 509 510 /* 511 * There is no point in polling MCLK0 if it is identical to MCLK1. 512 * And given that MQS use case has to use MCLK1 though two clocks 513 * are the same, we simply skip MCLK0 and start to find from MCLK1. 514 */ 515 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 516 517 for (; id < FSL_SAI_MCLK_MAX; id++) { 518 int diff; 519 520 clk_rate = clk_get_rate(sai->mclk_clk[id]); 521 if (!clk_rate) 522 continue; 523 524 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 525 if (!ratio || ratio > 512) 526 continue; 527 if (ratio == 1 && !support_1_1_ratio) 528 continue; 529 if ((ratio & 1) && ratio > 1) 530 continue; 531 532 diff = abs((long)clk_rate - ratio * freq); 533 534 /* 535 * Drop the source that can not be 536 * divided into the required rate. 537 */ 538 if (diff != 0 && clk_rate / diff < 1000) 539 continue; 540 541 dev_dbg(dai->dev, 542 "ratio %d for freq %dHz based on clock %ldHz\n", 543 ratio, freq, clk_rate); 544 545 546 if (diff < bestdiff) { 547 savediv = ratio; 548 sai->mclk_id[tx] = id; 549 bestdiff = diff; 550 } 551 552 if (diff == 0) 553 break; 554 } 555 556 if (savediv == 0) { 557 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 558 tx ? 'T' : 'R', freq); 559 return -EINVAL; 560 } 561 562 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 563 sai->mclk_id[tx], savediv, bestdiff); 564 565 /* 566 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 567 * set TCR2 register for playback. 568 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 569 * and capture. 570 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 571 * and capture. 572 * 4) For Tx and Rx are both Synchronous with another SAI, we just 573 * ignore it. 574 */ 575 if (fsl_sai_dir_is_synced(sai, adir)) 576 reg = FSL_SAI_xCR2(!tx, ofs); 577 else if (!sai->synchronous[dir]) 578 reg = FSL_SAI_xCR2(tx, ofs); 579 else 580 return 0; 581 582 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 583 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 584 585 if (savediv == 1) { 586 regmap_update_bits(sai->regmap, reg, 587 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 588 FSL_SAI_CR2_BYP); 589 if (fsl_sai_dir_is_synced(sai, adir)) 590 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 591 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 592 else 593 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 594 FSL_SAI_CR2_BCI, 0); 595 } else { 596 regmap_update_bits(sai->regmap, reg, 597 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 598 savediv / 2 - 1); 599 } 600 601 return 0; 602 } 603 604 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 605 struct snd_pcm_hw_params *params, 606 struct snd_soc_dai *cpu_dai) 607 { 608 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 609 unsigned int ofs = sai->soc_data->reg_offset; 610 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 611 unsigned int channels = params_channels(params); 612 struct snd_dmaengine_dai_dma_data *dma_params; 613 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 614 u32 word_width = params_width(params); 615 int trce_mask = 0, dl_cfg_idx = 0; 616 int dl_cfg_cnt = sai->dl_cfg_cnt; 617 u32 dl_type = FSL_SAI_DL_I2S; 618 u32 val_cr4 = 0, val_cr5 = 0; 619 u32 slots = (channels == 1) ? 2 : channels; 620 u32 slot_width = word_width; 621 int adir = tx ? RX : TX; 622 u32 pins, bclk; 623 u32 watermark; 624 int ret, i; 625 626 if (sai->slot_width[tx]) 627 slot_width = sai->slot_width[tx]; 628 629 if (sai->slots[tx]) 630 slots = sai->slots[tx]; 631 else if (sai->bclk_ratio) 632 slots = sai->bclk_ratio / slot_width; 633 634 pins = DIV_ROUND_UP(channels, slots); 635 636 /* 637 * PDM mode, channels are independent 638 * each channels are on one dataline/FIFO. 639 */ 640 if (sai->is_pdm_mode) { 641 pins = channels; 642 dl_type = FSL_SAI_DL_PDM; 643 } 644 645 for (i = 0; i < dl_cfg_cnt; i++) { 646 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 647 dl_cfg_idx = i; 648 break; 649 } 650 } 651 652 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 653 dev_err(cpu_dai->dev, "channel not supported\n"); 654 return -EINVAL; 655 } 656 657 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 658 659 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 660 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 661 if (!IS_ERR_OR_NULL(sai->pins_state)) { 662 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 663 if (ret) { 664 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 665 return ret; 666 } 667 } 668 } 669 670 if (!sai->is_consumer_mode[tx]) { 671 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 672 if (ret) 673 return ret; 674 675 /* Do not enable the clock if it is already enabled */ 676 if (!(sai->mclk_streams & BIT(substream->stream))) { 677 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 678 if (ret) 679 return ret; 680 681 sai->mclk_streams |= BIT(substream->stream); 682 } 683 } 684 685 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode) 686 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 687 688 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 689 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 690 691 if (sai->is_lsb_first) 692 val_cr5 |= FSL_SAI_CR5_FBT(0); 693 else 694 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 695 696 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 697 698 /* Set to avoid channel swap */ 699 val_cr4 |= FSL_SAI_CR4_FCONT; 700 701 /* Set to output mode to avoid tri-stated data pins */ 702 if (tx) 703 val_cr4 |= FSL_SAI_CR4_CHMOD; 704 705 /* 706 * When Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will provide bclk and 707 * frame clock for Tx(Rx). We should set RCR4(TCR4), RCR5(TCR5) 708 * for playback(capture), or there will be sync error. 709 */ 710 711 if (fsl_sai_dir_is_synced(sai, adir)) { 712 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 713 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 714 FSL_SAI_CR4_CHMOD_MASK, 715 val_cr4); 716 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 717 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 718 FSL_SAI_CR5_FBT_MASK, val_cr5); 719 } 720 721 /* 722 * Combine mode has limation: 723 * - Can't used for singel dataline/FIFO case except the FIFO0 724 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 725 * are successive and start from FIFO0 726 * 727 * So for common usage, all multi fifo case disable the combine mode. 728 */ 729 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 730 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 731 FSL_SAI_CR4_FCOMB_MASK, 0); 732 else 733 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 734 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 735 736 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 737 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 738 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 739 740 if (sai->is_multi_fifo_dma) { 741 sai->audio_config[tx].words_per_fifo = min(slots, channels); 742 if (tx) { 743 sai->audio_config[tx].n_fifos_dst = pins; 744 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 745 } else { 746 sai->audio_config[tx].n_fifos_src = pins; 747 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 748 } 749 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 750 dma_params->peripheral_config = &sai->audio_config[tx]; 751 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 752 753 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 754 (dma_params->maxburst - 1); 755 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 756 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 757 watermark); 758 } 759 760 /* Find a proper tcre setting */ 761 for (i = 0; i < sai->soc_data->pins; i++) { 762 trce_mask = (1 << (i + 1)) - 1; 763 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 764 break; 765 } 766 767 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 768 FSL_SAI_CR3_TRCE_MASK, 769 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 770 771 /* 772 * When the TERE and FSD_MSTR enabled before configuring the word width 773 * There will be no frame sync clock issue, because word width impact 774 * the generation of frame sync clock. 775 * 776 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 777 * We need to disable FSD_MSTR before configuring word width, then enable 778 * FSD_MSTR bit for this specific case. 779 */ 780 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 781 !sai->is_consumer_mode[tx]) 782 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 783 FSL_SAI_CR4_FSD_MSTR, 0); 784 785 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 786 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 787 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK, 788 val_cr4); 789 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 790 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 791 FSL_SAI_CR5_FBT_MASK, val_cr5); 792 793 /* Enable FSD_MSTR after configuring word width */ 794 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 795 !sai->is_consumer_mode[tx]) 796 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 797 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 798 799 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 800 ~GENMASK_U32(min(channels, slots) - 1, 0)); 801 802 return 0; 803 } 804 805 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 806 struct snd_soc_dai *cpu_dai) 807 { 808 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 809 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 810 unsigned int ofs = sai->soc_data->reg_offset; 811 812 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 813 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 814 815 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 816 FSL_SAI_CR3_TRCE_MASK, 0); 817 818 if (!sai->is_consumer_mode[tx] && 819 sai->mclk_streams & BIT(substream->stream)) { 820 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 821 sai->mclk_streams &= ~BIT(substream->stream); 822 } 823 824 return 0; 825 } 826 827 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 828 { 829 unsigned int ofs = sai->soc_data->reg_offset; 830 bool tx = dir == TX; 831 u32 xcsr, count = 100, mask; 832 833 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 834 mask = FSL_SAI_CSR_TERE; 835 else 836 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 837 838 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 839 mask, 0); 840 841 /* TERE will remain set till the end of current frame */ 842 do { 843 udelay(10); 844 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 845 } while (--count && xcsr & FSL_SAI_CSR_TERE); 846 847 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 848 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 849 850 /* 851 * For sai master mode, after several open/close sai, 852 * there will be no frame clock, and can't recover 853 * anymore. Add software reset to fix this issue. 854 * This is a hardware bug, and will be fix in the 855 * next sai version. 856 * 857 * In consumer mode, this can happen even after a 858 * single open/close, especially if both tx and rx 859 * are running concurrently. 860 */ 861 /* Software Reset */ 862 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 863 /* Clear SR bit to finish the reset */ 864 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0); 865 } 866 867 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 868 struct snd_soc_dai *cpu_dai) 869 { 870 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 871 unsigned int ofs = sai->soc_data->reg_offset; 872 873 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 874 int adir = tx ? RX : TX; 875 int dir = tx ? TX : RX; 876 u32 xcsr; 877 878 /* 879 * Asynchronous mode: Clear SYNC for both Tx and Rx. 880 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 881 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 882 */ 883 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 884 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 885 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 886 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 887 888 /* 889 * It is recommended that the transmitter is the last enabled 890 * and the first disabled. 891 */ 892 switch (cmd) { 893 case SNDRV_PCM_TRIGGER_START: 894 case SNDRV_PCM_TRIGGER_RESUME: 895 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 896 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 897 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 898 899 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 900 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 901 /* 902 * Enable the opposite direction for synchronous mode 903 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 904 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 905 * 906 * RM recommends to enable RE after TE for case 1 and to enable 907 * TE after RE for case 2, but we here may not always guarantee 908 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 909 * TE after RE, which is against what RM recommends but should 910 * be safe to do, judging by years of testing results. 911 */ 912 if (fsl_sai_dir_is_synced(sai, adir)) 913 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 914 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 915 916 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 917 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 918 break; 919 case SNDRV_PCM_TRIGGER_STOP: 920 case SNDRV_PCM_TRIGGER_SUSPEND: 921 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 922 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 923 FSL_SAI_CSR_FRDE, 0); 924 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 925 FSL_SAI_CSR_xIE_MASK, 0); 926 927 /* Check if the opposite FRDE is also disabled */ 928 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 929 930 /* 931 * If opposite stream provides clocks for synchronous mode and 932 * it is inactive, disable it before disabling the current one 933 */ 934 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 935 fsl_sai_config_disable(sai, adir); 936 937 /* 938 * Disable current stream if either of: 939 * 1. current stream doesn't provide clocks for synchronous mode 940 * 2. current stream provides clocks for synchronous mode but no 941 * more stream is active. 942 */ 943 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 944 fsl_sai_config_disable(sai, dir); 945 946 break; 947 default: 948 return -EINVAL; 949 } 950 951 return 0; 952 } 953 954 static int fsl_sai_startup(struct snd_pcm_substream *substream, 955 struct snd_soc_dai *cpu_dai) 956 { 957 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 958 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 959 int ret; 960 961 /* 962 * EDMA controller needs period size to be a multiple of 963 * tx/rx maxburst 964 */ 965 if (sai->soc_data->use_edma) 966 snd_pcm_hw_constraint_step(substream->runtime, 0, 967 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 968 tx ? sai->dma_params_tx.maxburst : 969 sai->dma_params_rx.maxburst); 970 971 if (sai->is_consumer_mode[tx]) 972 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 973 SNDRV_PCM_HW_PARAM_RATE, 974 &fsl_sai_rate_constraints); 975 else 976 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 977 SNDRV_PCM_HW_PARAM_RATE, 978 &sai->constraint_rates); 979 980 return ret; 981 } 982 983 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 984 { 985 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 986 unsigned int ofs = sai->soc_data->reg_offset; 987 988 /* Software Reset for both Tx and Rx */ 989 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 990 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 991 /* Clear SR bit to finish the reset */ 992 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 993 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 994 995 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 996 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 997 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 998 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 999 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 1000 sai->dma_params_rx.maxburst - 1); 1001 1002 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 1003 &sai->dma_params_rx); 1004 1005 return 0; 1006 } 1007 1008 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 1009 .probe = fsl_sai_dai_probe, 1010 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1011 .set_sysclk = fsl_sai_set_dai_sysclk, 1012 .set_fmt = fsl_sai_set_dai_fmt, 1013 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 1014 .hw_params = fsl_sai_hw_params, 1015 .hw_free = fsl_sai_hw_free, 1016 .trigger = fsl_sai_trigger, 1017 .startup = fsl_sai_startup, 1018 }; 1019 1020 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = { 1021 .probe = fsl_sai_dai_probe, 1022 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1023 .set_sysclk = fsl_sai_set_dai_sysclk, 1024 .set_fmt = fsl_sai_set_dai_fmt_tx, 1025 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_tx, 1026 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 1027 .hw_params = fsl_sai_hw_params, 1028 .hw_free = fsl_sai_hw_free, 1029 .trigger = fsl_sai_trigger, 1030 .startup = fsl_sai_startup, 1031 }; 1032 1033 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = { 1034 .probe = fsl_sai_dai_probe, 1035 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1036 .set_sysclk = fsl_sai_set_dai_sysclk, 1037 .set_fmt = fsl_sai_set_dai_fmt_rx, 1038 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_rx, 1039 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 1040 .hw_params = fsl_sai_hw_params, 1041 .hw_free = fsl_sai_hw_free, 1042 .trigger = fsl_sai_trigger, 1043 .startup = fsl_sai_startup, 1044 }; 1045 1046 static int fsl_sai_dai_resume(struct snd_soc_component *component) 1047 { 1048 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 1049 struct device *dev = &sai->pdev->dev; 1050 int ret; 1051 1052 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 1053 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 1054 if (ret) { 1055 dev_err(dev, "failed to set proper pins state: %d\n", ret); 1056 return ret; 1057 } 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int fsl_sai_component_probe(struct snd_soc_component *component) 1064 { 1065 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 1066 1067 if (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN) 1068 snd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls, 1069 ARRAY_SIZE(fsl_sai_timestamp_ctrls)); 1070 1071 return 0; 1072 } 1073 1074 static struct snd_soc_dai_driver fsl_sai_dai_template[] = { 1075 { 1076 .name = "sai-tx-rx", 1077 .playback = { 1078 .stream_name = "CPU-Playback", 1079 .channels_min = 1, 1080 .channels_max = 32, 1081 .rate_min = 8000, 1082 .rate_max = 2822400, 1083 .rates = SNDRV_PCM_RATE_KNOT, 1084 .formats = FSL_SAI_FORMATS, 1085 }, 1086 .capture = { 1087 .stream_name = "CPU-Capture", 1088 .channels_min = 1, 1089 .channels_max = 32, 1090 .rate_min = 8000, 1091 .rate_max = 2822400, 1092 .rates = SNDRV_PCM_RATE_KNOT, 1093 .formats = FSL_SAI_FORMATS, 1094 }, 1095 .ops = &fsl_sai_pcm_dai_ops, 1096 }, 1097 { 1098 .name = "sai-tx", 1099 .playback = { 1100 .stream_name = "SAI-Playback", 1101 .channels_min = 1, 1102 .channels_max = 32, 1103 .rate_min = 8000, 1104 .rate_max = 2822400, 1105 .rates = SNDRV_PCM_RATE_KNOT, 1106 .formats = FSL_SAI_FORMATS, 1107 }, 1108 .ops = &fsl_sai_pcm_dai_tx_ops, 1109 }, 1110 { 1111 .name = "sai-rx", 1112 .capture = { 1113 .stream_name = "SAI-Capture", 1114 .channels_min = 1, 1115 .channels_max = 32, 1116 .rate_min = 8000, 1117 .rate_max = 2822400, 1118 .rates = SNDRV_PCM_RATE_KNOT, 1119 .formats = FSL_SAI_FORMATS, 1120 }, 1121 .ops = &fsl_sai_pcm_dai_rx_ops, 1122 }, 1123 }; 1124 1125 static const struct snd_soc_component_driver fsl_component = { 1126 .name = "fsl-sai", 1127 .probe = fsl_sai_component_probe, 1128 .resume = fsl_sai_dai_resume, 1129 .legacy_dai_naming = 1, 1130 }; 1131 1132 static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { 1133 {FSL_SAI_TCR1(0), 0}, 1134 {FSL_SAI_TCR2(0), 0}, 1135 {FSL_SAI_TCR3(0), 0}, 1136 {FSL_SAI_TCR4(0), 0}, 1137 {FSL_SAI_TCR5(0), 0}, 1138 {FSL_SAI_TDR0, 0}, 1139 {FSL_SAI_TDR1, 0}, 1140 {FSL_SAI_TDR2, 0}, 1141 {FSL_SAI_TDR3, 0}, 1142 {FSL_SAI_TDR4, 0}, 1143 {FSL_SAI_TDR5, 0}, 1144 {FSL_SAI_TDR6, 0}, 1145 {FSL_SAI_TDR7, 0}, 1146 {FSL_SAI_TMR, 0}, 1147 {FSL_SAI_TTCTL, 0}, 1148 {FSL_SAI_RCR1(0), 0}, 1149 {FSL_SAI_RCR2(0), 0}, 1150 {FSL_SAI_RCR3(0), 0}, 1151 {FSL_SAI_RCR4(0), 0}, 1152 {FSL_SAI_RCR5(0), 0}, 1153 {FSL_SAI_RMR, 0}, 1154 }; 1155 1156 static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { 1157 {FSL_SAI_TCR1(8), 0}, 1158 {FSL_SAI_TCR2(8), 0}, 1159 {FSL_SAI_TCR3(8), 0}, 1160 {FSL_SAI_TCR4(8), 0}, 1161 {FSL_SAI_TCR5(8), 0}, 1162 {FSL_SAI_TDR0, 0}, 1163 {FSL_SAI_TDR1, 0}, 1164 {FSL_SAI_TDR2, 0}, 1165 {FSL_SAI_TDR3, 0}, 1166 {FSL_SAI_TDR4, 0}, 1167 {FSL_SAI_TDR5, 0}, 1168 {FSL_SAI_TDR6, 0}, 1169 {FSL_SAI_TDR7, 0}, 1170 {FSL_SAI_TMR, 0}, 1171 {FSL_SAI_TTCTL, 0}, 1172 {FSL_SAI_RCR1(8), 0}, 1173 {FSL_SAI_RCR2(8), 0}, 1174 {FSL_SAI_RCR3(8), 0}, 1175 {FSL_SAI_RCR4(8), 0}, 1176 {FSL_SAI_RCR5(8), 0}, 1177 {FSL_SAI_RMR, 0}, 1178 {FSL_SAI_RTCTL, 0}, 1179 {FSL_SAI_MCTL, 0}, 1180 {FSL_SAI_MDIV, 0}, 1181 }; 1182 1183 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1184 { 1185 struct fsl_sai *sai = dev_get_drvdata(dev); 1186 unsigned int ofs = sai->soc_data->reg_offset; 1187 1188 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1189 return true; 1190 1191 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1192 return true; 1193 1194 switch (reg) { 1195 case FSL_SAI_TFR0: 1196 case FSL_SAI_TFR1: 1197 case FSL_SAI_TFR2: 1198 case FSL_SAI_TFR3: 1199 case FSL_SAI_TFR4: 1200 case FSL_SAI_TFR5: 1201 case FSL_SAI_TFR6: 1202 case FSL_SAI_TFR7: 1203 case FSL_SAI_TMR: 1204 case FSL_SAI_RDR0: 1205 case FSL_SAI_RDR1: 1206 case FSL_SAI_RDR2: 1207 case FSL_SAI_RDR3: 1208 case FSL_SAI_RDR4: 1209 case FSL_SAI_RDR5: 1210 case FSL_SAI_RDR6: 1211 case FSL_SAI_RDR7: 1212 case FSL_SAI_RFR0: 1213 case FSL_SAI_RFR1: 1214 case FSL_SAI_RFR2: 1215 case FSL_SAI_RFR3: 1216 case FSL_SAI_RFR4: 1217 case FSL_SAI_RFR5: 1218 case FSL_SAI_RFR6: 1219 case FSL_SAI_RFR7: 1220 case FSL_SAI_RMR: 1221 case FSL_SAI_MCTL: 1222 case FSL_SAI_MDIV: 1223 case FSL_SAI_VERID: 1224 case FSL_SAI_PARAM: 1225 case FSL_SAI_TTCTN: 1226 case FSL_SAI_RTCTN: 1227 case FSL_SAI_TTCTL: 1228 case FSL_SAI_TBCTN: 1229 case FSL_SAI_TTCAP: 1230 case FSL_SAI_RTCTL: 1231 case FSL_SAI_RBCTN: 1232 case FSL_SAI_RTCAP: 1233 return true; 1234 default: 1235 return false; 1236 } 1237 } 1238 1239 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1240 { 1241 struct fsl_sai *sai = dev_get_drvdata(dev); 1242 unsigned int ofs = sai->soc_data->reg_offset; 1243 1244 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1245 return true; 1246 1247 /* Set VERID and PARAM be volatile for reading value in probe */ 1248 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1249 return true; 1250 1251 switch (reg) { 1252 case FSL_SAI_TFR0: 1253 case FSL_SAI_TFR1: 1254 case FSL_SAI_TFR2: 1255 case FSL_SAI_TFR3: 1256 case FSL_SAI_TFR4: 1257 case FSL_SAI_TFR5: 1258 case FSL_SAI_TFR6: 1259 case FSL_SAI_TFR7: 1260 case FSL_SAI_RFR0: 1261 case FSL_SAI_RFR1: 1262 case FSL_SAI_RFR2: 1263 case FSL_SAI_RFR3: 1264 case FSL_SAI_RFR4: 1265 case FSL_SAI_RFR5: 1266 case FSL_SAI_RFR6: 1267 case FSL_SAI_RFR7: 1268 case FSL_SAI_RDR0: 1269 case FSL_SAI_RDR1: 1270 case FSL_SAI_RDR2: 1271 case FSL_SAI_RDR3: 1272 case FSL_SAI_RDR4: 1273 case FSL_SAI_RDR5: 1274 case FSL_SAI_RDR6: 1275 case FSL_SAI_RDR7: 1276 case FSL_SAI_TTCTN: 1277 case FSL_SAI_RTCTN: 1278 case FSL_SAI_TTCTL: 1279 case FSL_SAI_TBCTN: 1280 case FSL_SAI_TTCAP: 1281 case FSL_SAI_RTCTL: 1282 case FSL_SAI_RBCTN: 1283 case FSL_SAI_RTCAP: 1284 return true; 1285 default: 1286 return false; 1287 } 1288 } 1289 1290 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1291 { 1292 struct fsl_sai *sai = dev_get_drvdata(dev); 1293 unsigned int ofs = sai->soc_data->reg_offset; 1294 1295 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1296 return true; 1297 1298 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1299 return true; 1300 1301 switch (reg) { 1302 case FSL_SAI_TDR0: 1303 case FSL_SAI_TDR1: 1304 case FSL_SAI_TDR2: 1305 case FSL_SAI_TDR3: 1306 case FSL_SAI_TDR4: 1307 case FSL_SAI_TDR5: 1308 case FSL_SAI_TDR6: 1309 case FSL_SAI_TDR7: 1310 case FSL_SAI_TMR: 1311 case FSL_SAI_RMR: 1312 case FSL_SAI_MCTL: 1313 case FSL_SAI_MDIV: 1314 case FSL_SAI_TTCTL: 1315 case FSL_SAI_RTCTL: 1316 return true; 1317 default: 1318 return false; 1319 } 1320 } 1321 1322 static struct regmap_config fsl_sai_regmap_config = { 1323 .reg_bits = 32, 1324 .reg_stride = 4, 1325 .val_bits = 32, 1326 1327 .max_register = FSL_SAI_RMR, 1328 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1329 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1330 .readable_reg = fsl_sai_readable_reg, 1331 .volatile_reg = fsl_sai_volatile_reg, 1332 .writeable_reg = fsl_sai_writeable_reg, 1333 .cache_type = REGCACHE_FLAT, 1334 }; 1335 1336 static int fsl_sai_check_version(struct device *dev) 1337 { 1338 struct fsl_sai *sai = dev_get_drvdata(dev); 1339 unsigned char ofs = sai->soc_data->reg_offset; 1340 unsigned int val; 1341 int ret; 1342 1343 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1344 return 0; 1345 1346 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1347 if (ret < 0) 1348 return ret; 1349 1350 dev_dbg(dev, "VERID: 0x%016X\n", val); 1351 1352 sai->verid.version = val & 1353 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1354 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1355 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1356 1357 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1358 if (ret < 0) 1359 return ret; 1360 1361 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1362 1363 /* Max slots per frame, power of 2 */ 1364 sai->param.slot_num = 1 << 1365 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1366 1367 /* Words per fifo, power of 2 */ 1368 sai->param.fifo_depth = 1 << 1369 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1370 1371 /* Number of datalines implemented */ 1372 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1373 1374 return 0; 1375 } 1376 1377 static int fsl_sai_reset_hw(struct device *dev) 1378 { 1379 struct fsl_sai *sai = dev_get_drvdata(dev); 1380 unsigned char ofs = sai->soc_data->reg_offset; 1381 int ret; 1382 1383 /* 1384 * Clear TCSR/RCSR to reset SAI and disable all interrupts. 1385 * Bootloader may leave SAI running causing interrupt storm. 1386 */ 1387 ret = regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1388 if (ret) { 1389 dev_err(dev, "Failed to clear TCSR: %d\n", ret); 1390 return ret; 1391 } 1392 1393 ret = regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1394 if (ret) { 1395 dev_err(dev, "Failed to clear RCSR: %d\n", ret); 1396 return ret; 1397 } 1398 1399 return 0; 1400 } 1401 1402 /* 1403 * Calculate the offset between first two datalines, don't 1404 * different offset in one case. 1405 */ 1406 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1407 { 1408 int fbidx, nbidx, offset; 1409 1410 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1411 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1412 offset = nbidx - fbidx - 1; 1413 1414 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1415 } 1416 1417 /* 1418 * read the fsl,dataline property from dts file. 1419 * It has 3 value for each configuration, first one means the type: 1420 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1421 * dataline mask for 'tx'. for example 1422 * 1423 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1424 * 1425 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1426 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1427 * 1428 */ 1429 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1430 { 1431 struct platform_device *pdev = sai->pdev; 1432 struct device_node *np = pdev->dev.of_node; 1433 struct device *dev = &pdev->dev; 1434 int ret, elems, i, index, num_cfg; 1435 char *propname = "fsl,dataline"; 1436 struct fsl_sai_dl_cfg *cfg; 1437 unsigned long dl_mask; 1438 unsigned int soc_dl; 1439 u32 rx, tx, type; 1440 1441 elems = of_property_count_u32_elems(np, propname); 1442 1443 if (elems <= 0) { 1444 elems = 0; 1445 } else if (elems % 3) { 1446 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1447 return -EINVAL; 1448 } 1449 1450 num_cfg = elems / 3; 1451 /* Add one more for default value */ 1452 cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL); 1453 if (!cfg) 1454 return -ENOMEM; 1455 1456 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1457 soc_dl = BIT(sai->soc_data->pins) - 1; 1458 cfg[0].type = FSL_SAI_DL_DEFAULT; 1459 cfg[0].pins[0] = sai->soc_data->pins; 1460 cfg[0].mask[0] = soc_dl; 1461 cfg[0].start_off[0] = 0; 1462 cfg[0].next_off[0] = 0; 1463 1464 cfg[0].pins[1] = sai->soc_data->pins; 1465 cfg[0].mask[1] = soc_dl; 1466 cfg[0].start_off[1] = 0; 1467 cfg[0].next_off[1] = 0; 1468 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1469 /* 1470 * type of dataline 1471 * 0 means default mode 1472 * 1 means I2S mode 1473 * 2 means PDM mode 1474 */ 1475 ret = of_property_read_u32_index(np, propname, index++, &type); 1476 if (ret) 1477 return -EINVAL; 1478 1479 ret = of_property_read_u32_index(np, propname, index++, &rx); 1480 if (ret) 1481 return -EINVAL; 1482 1483 ret = of_property_read_u32_index(np, propname, index++, &tx); 1484 if (ret) 1485 return -EINVAL; 1486 1487 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1488 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1489 return -EINVAL; 1490 } 1491 1492 rx = rx & soc_dl; 1493 tx = tx & soc_dl; 1494 1495 cfg[i].type = type; 1496 cfg[i].pins[0] = hweight8(rx); 1497 cfg[i].mask[0] = rx; 1498 dl_mask = rx; 1499 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1500 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1501 1502 cfg[i].pins[1] = hweight8(tx); 1503 cfg[i].mask[1] = tx; 1504 dl_mask = tx; 1505 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1506 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1507 } 1508 1509 sai->dl_cfg = cfg; 1510 sai->dl_cfg_cnt = num_cfg + 1; 1511 return 0; 1512 } 1513 1514 static int fsl_sai_runtime_suspend(struct device *dev); 1515 static int fsl_sai_runtime_resume(struct device *dev); 1516 1517 static int fsl_sai_probe(struct platform_device *pdev) 1518 { 1519 struct device_node *np = pdev->dev.of_node; 1520 struct device *dev = &pdev->dev; 1521 struct fsl_sai *sai; 1522 struct regmap *gpr; 1523 void __iomem *base; 1524 const char *str = NULL; 1525 char tmp[8]; 1526 int irq, ret, i; 1527 int index; 1528 u32 dmas[4]; 1529 u32 val; 1530 1531 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1532 if (!sai) 1533 return -ENOMEM; 1534 1535 sai->pdev = pdev; 1536 sai->soc_data = of_device_get_match_data(dev); 1537 1538 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1539 sai->is_bit_clock_swap = of_property_read_bool(np, "fsl,sai-bit-clock-swap"); 1540 1541 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1542 if (IS_ERR(base)) 1543 return PTR_ERR(base); 1544 1545 if (sai->soc_data->reg_offset == 8) { 1546 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1547 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1548 fsl_sai_regmap_config.num_reg_defaults = 1549 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1550 } 1551 1552 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1553 if (IS_ERR(sai->regmap)) { 1554 dev_err(dev, "regmap init failed\n"); 1555 return PTR_ERR(sai->regmap); 1556 } 1557 1558 sai->bus_clk = devm_clk_get(dev, "bus"); 1559 /* Compatible with old DTB cases */ 1560 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1561 sai->bus_clk = devm_clk_get(dev, "sai"); 1562 if (IS_ERR(sai->bus_clk)) { 1563 dev_err(dev, "failed to get bus clock: %ld\n", 1564 PTR_ERR(sai->bus_clk)); 1565 /* -EPROBE_DEFER */ 1566 return PTR_ERR(sai->bus_clk); 1567 } 1568 1569 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1570 sprintf(tmp, "mclk%d", i); 1571 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1572 if (IS_ERR(sai->mclk_clk[i])) { 1573 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1574 i, PTR_ERR(sai->mclk_clk[i])); 1575 sai->mclk_clk[i] = NULL; 1576 } 1577 } 1578 1579 if (sai->soc_data->mclk0_is_mclk1) 1580 sai->mclk_clk[0] = sai->mclk_clk[1]; 1581 else 1582 sai->mclk_clk[0] = sai->bus_clk; 1583 1584 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1585 &sai->pll11k_clk); 1586 1587 fsl_asoc_constrain_rates(&sai->constraint_rates, 1588 &fsl_sai_rate_constraints, 1589 sai->pll8k_clk, sai->pll11k_clk, NULL, 1590 sai->constraint_rates_list); 1591 1592 /* Use Multi FIFO mode depending on the support from SDMA script */ 1593 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1594 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1595 sai->is_multi_fifo_dma = true; 1596 1597 /* read dataline mask for rx and tx*/ 1598 ret = fsl_sai_read_dlcfg(sai); 1599 if (ret < 0) { 1600 dev_err(dev, "failed to read dlcfg %d\n", ret); 1601 return ret; 1602 } 1603 1604 irq = platform_get_irq(pdev, 0); 1605 if (irq < 0) 1606 return irq; 1607 1608 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template, 1609 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template)); 1610 1611 /* Sync Tx with Rx as default by following old DT binding */ 1612 sai->synchronous[RX] = true; 1613 sai->synchronous[TX] = false; 1614 sai->cpu_dai_drv[0].symmetric_rate = 1; 1615 sai->cpu_dai_drv[0].symmetric_channels = 1; 1616 sai->cpu_dai_drv[0].symmetric_sample_bits = 1; 1617 1618 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1619 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1620 /* error out if both synchronous and asynchronous are present */ 1621 dev_err(dev, "invalid binding for synchronous mode\n"); 1622 return -EINVAL; 1623 } 1624 1625 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1626 /* Sync Rx with Tx */ 1627 sai->synchronous[RX] = false; 1628 sai->synchronous[TX] = true; 1629 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1630 /* Discard all settings for asynchronous mode */ 1631 sai->synchronous[RX] = false; 1632 sai->synchronous[TX] = false; 1633 sai->cpu_dai_drv[0].symmetric_rate = 0; 1634 sai->cpu_dai_drv[0].symmetric_channels = 0; 1635 sai->cpu_dai_drv[0].symmetric_sample_bits = 0; 1636 } 1637 1638 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1639 1640 if (sai->mclk_direction_output && 1641 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1642 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1643 if (IS_ERR(gpr)) { 1644 dev_err(dev, "cannot find iomuxc registers\n"); 1645 return PTR_ERR(gpr); 1646 } 1647 1648 index = of_alias_get_id(np, "sai"); 1649 if (index < 0) 1650 return index; 1651 1652 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1653 MCLK_DIR(index)); 1654 } 1655 1656 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1657 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1658 sai->dma_params_rx.maxburst = 1659 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1660 sai->dma_params_tx.maxburst = 1661 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1662 1663 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1664 1665 platform_set_drvdata(pdev, sai); 1666 pm_runtime_enable(dev); 1667 if (!pm_runtime_enabled(dev)) { 1668 ret = fsl_sai_runtime_resume(dev); 1669 if (ret) 1670 goto err_pm_disable; 1671 } 1672 1673 ret = pm_runtime_resume_and_get(dev); 1674 if (ret < 0) 1675 goto err_pm_get_sync; 1676 1677 /* Get sai version */ 1678 ret = fsl_sai_check_version(dev); 1679 if (ret < 0) 1680 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1681 1682 ret = fsl_sai_reset_hw(dev); 1683 if (ret < 0) 1684 dev_warn(dev, "Failed to reset hardware: %d\n", ret); 1685 1686 /* Select MCLK direction */ 1687 if (sai->mclk_direction_output && 1688 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1689 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1690 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1691 } 1692 1693 ret = pm_runtime_put_sync(dev); 1694 if (ret < 0 && ret != -ENOSYS) 1695 goto err_pm_get_sync; 1696 1697 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1698 np->name, sai); 1699 if (ret) { 1700 dev_err(dev, "failed to claim irq %u\n", irq); 1701 goto err_pm_get_sync; 1702 } 1703 1704 if (of_device_is_compatible(np, "fsl,imx952-sai") && 1705 !of_property_read_string(np, "fsl,sai-amix-mode", &str)) { 1706 if (!strcmp(str, "bypass")) 1707 val = FSL_SAI_AMIX_BYPASS; 1708 else if (!strcmp(str, "audmix")) 1709 val = FSL_SAI_AMIX_AUDMIX; 1710 else 1711 val = FSL_SAI_AMIX_NONE; 1712 1713 if (val < FSL_SAI_AMIX_NONE) { 1714 ret = scmi_imx_misc_ctrl_set(SCMI_IMX952_CTRL_BYPASS_AUDMIX, val); 1715 if (ret) { 1716 dev_err_probe(dev, ret, "Error setting audmix mode\n"); 1717 goto err_pm_get_sync; 1718 } 1719 } 1720 } 1721 1722 /* 1723 * Register platform component before registering cpu dai for there 1724 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1725 */ 1726 if (sai->soc_data->use_imx_pcm) { 1727 ret = imx_pcm_dma_init(pdev); 1728 if (ret) { 1729 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1730 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1731 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1732 goto err_pm_get_sync; 1733 } 1734 } else { 1735 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1736 if (ret) { 1737 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1738 goto err_pm_get_sync; 1739 } 1740 } 1741 1742 ret = devm_snd_soc_register_component(dev, &fsl_component, 1743 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template)); 1744 if (ret) 1745 goto err_pm_get_sync; 1746 1747 return ret; 1748 1749 err_pm_get_sync: 1750 if (!pm_runtime_status_suspended(dev)) 1751 fsl_sai_runtime_suspend(dev); 1752 err_pm_disable: 1753 pm_runtime_disable(dev); 1754 1755 return ret; 1756 } 1757 1758 static void fsl_sai_remove(struct platform_device *pdev) 1759 { 1760 pm_runtime_disable(&pdev->dev); 1761 if (!pm_runtime_status_suspended(&pdev->dev)) 1762 fsl_sai_runtime_suspend(&pdev->dev); 1763 } 1764 1765 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1766 .use_imx_pcm = false, 1767 .use_edma = false, 1768 .fifo_depth = 32, 1769 .pins = 1, 1770 .reg_offset = 0, 1771 .mclk0_is_mclk1 = false, 1772 .flags = 0, 1773 .max_register = FSL_SAI_RMR, 1774 }; 1775 1776 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1777 .use_imx_pcm = true, 1778 .use_edma = false, 1779 .fifo_depth = 32, 1780 .pins = 1, 1781 .reg_offset = 0, 1782 .mclk0_is_mclk1 = true, 1783 .flags = 0, 1784 .max_register = FSL_SAI_RMR, 1785 }; 1786 1787 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1788 .use_imx_pcm = true, 1789 .use_edma = false, 1790 .fifo_depth = 16, 1791 .pins = 2, 1792 .reg_offset = 8, 1793 .mclk0_is_mclk1 = false, 1794 .flags = PMQOS_CPU_LATENCY, 1795 .max_register = FSL_SAI_RMR, 1796 }; 1797 1798 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1799 .use_imx_pcm = true, 1800 .use_edma = false, 1801 .fifo_depth = 128, 1802 .pins = 8, 1803 .reg_offset = 8, 1804 .mclk0_is_mclk1 = false, 1805 .flags = 0, 1806 .max_register = FSL_SAI_RMR, 1807 }; 1808 1809 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1810 .use_imx_pcm = true, 1811 .use_edma = true, 1812 .fifo_depth = 64, 1813 .pins = 4, 1814 .reg_offset = 0, 1815 .mclk0_is_mclk1 = false, 1816 .flags = 0, 1817 .max_register = FSL_SAI_RMR, 1818 }; 1819 1820 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1821 .use_imx_pcm = true, 1822 .use_edma = false, 1823 .fifo_depth = 128, 1824 .reg_offset = 8, 1825 .mclk0_is_mclk1 = false, 1826 .pins = 8, 1827 .flags = 0, 1828 .max_register = FSL_SAI_MCTL, 1829 }; 1830 1831 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1832 .use_imx_pcm = true, 1833 .use_edma = false, 1834 .fifo_depth = 128, 1835 .reg_offset = 8, 1836 .mclk0_is_mclk1 = false, 1837 .pins = 8, 1838 .flags = 0, 1839 .max_register = FSL_SAI_MDIV, 1840 }; 1841 1842 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1843 .use_imx_pcm = true, 1844 .use_edma = false, 1845 .fifo_depth = 128, 1846 .reg_offset = 8, 1847 .mclk0_is_mclk1 = false, 1848 .pins = 8, 1849 .flags = 0, 1850 .max_register = FSL_SAI_MDIV, 1851 .mclk_with_tere = true, 1852 }; 1853 1854 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1855 .use_imx_pcm = true, 1856 .use_edma = true, 1857 .fifo_depth = 16, 1858 .reg_offset = 8, 1859 .mclk0_is_mclk1 = false, 1860 .pins = 4, 1861 .flags = PMQOS_CPU_LATENCY, 1862 .max_register = FSL_SAI_RTCAP, 1863 }; 1864 1865 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1866 .use_imx_pcm = true, 1867 .use_edma = true, 1868 .fifo_depth = 128, 1869 .reg_offset = 8, 1870 .mclk0_is_mclk1 = false, 1871 .pins = 4, 1872 .flags = 0, 1873 .max_register = FSL_SAI_MCTL, 1874 .max_burst = {8, 8}, 1875 }; 1876 1877 static const struct fsl_sai_soc_data fsl_sai_imx95_data = { 1878 .use_imx_pcm = true, 1879 .use_edma = true, 1880 .fifo_depth = 128, 1881 .reg_offset = 8, 1882 .mclk0_is_mclk1 = false, 1883 .pins = 8, 1884 .flags = 0, 1885 .max_register = FSL_SAI_MCTL, 1886 .max_burst = {8, 8}, 1887 }; 1888 1889 static const struct of_device_id fsl_sai_ids[] = { 1890 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1891 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1892 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1893 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1894 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1895 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1896 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1897 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1898 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1899 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1900 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1901 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data }, 1902 { /* sentinel */ } 1903 }; 1904 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1905 1906 static int fsl_sai_runtime_suspend(struct device *dev) 1907 { 1908 struct fsl_sai *sai = dev_get_drvdata(dev); 1909 1910 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1911 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1912 1913 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1914 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1915 1916 clk_disable_unprepare(sai->bus_clk); 1917 1918 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1919 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1920 1921 regcache_cache_only(sai->regmap, true); 1922 1923 return 0; 1924 } 1925 1926 static int fsl_sai_runtime_resume(struct device *dev) 1927 { 1928 struct fsl_sai *sai = dev_get_drvdata(dev); 1929 unsigned int ofs = sai->soc_data->reg_offset; 1930 int ret; 1931 1932 ret = clk_prepare_enable(sai->bus_clk); 1933 if (ret) { 1934 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1935 return ret; 1936 } 1937 1938 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1939 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1940 if (ret) 1941 goto disable_bus_clk; 1942 } 1943 1944 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1945 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1946 if (ret) 1947 goto disable_tx_clk; 1948 } 1949 1950 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1951 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1952 1953 regcache_cache_only(sai->regmap, false); 1954 regcache_mark_dirty(sai->regmap); 1955 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1956 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1957 usleep_range(1000, 2000); 1958 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 1959 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 1960 1961 ret = regcache_sync(sai->regmap); 1962 if (ret) 1963 goto disable_rx_clk; 1964 1965 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1966 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1967 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1968 1969 return 0; 1970 1971 disable_rx_clk: 1972 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1973 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1974 disable_tx_clk: 1975 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1976 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1977 disable_bus_clk: 1978 clk_disable_unprepare(sai->bus_clk); 1979 1980 return ret; 1981 } 1982 1983 static const struct dev_pm_ops fsl_sai_pm_ops = { 1984 RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL) 1985 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1986 }; 1987 1988 static struct platform_driver fsl_sai_driver = { 1989 .probe = fsl_sai_probe, 1990 .remove = fsl_sai_remove, 1991 .driver = { 1992 .name = "fsl-sai", 1993 .pm = pm_ptr(&fsl_sai_pm_ops), 1994 .of_match_table = fsl_sai_ids, 1995 }, 1996 }; 1997 module_platform_driver(fsl_sai_driver); 1998 1999 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 2000 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 2001 MODULE_ALIAS("platform:fsl-sai"); 2002 MODULE_LICENSE("GPL"); 2003