1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 //
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/firmware/imx/sm.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/pm_qos.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/time.h>
19 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24
25 #include "fsl_sai.h"
26 #include "fsl_utils.h"
27 #include "imx-pcm.h"
28
29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
30 FSL_SAI_CSR_FEIE)
31
32 static const unsigned int fsl_sai_rates[] = {
33 8000, 11025, 12000, 16000, 22050,
34 24000, 32000, 44100, 48000, 64000,
35 88200, 96000, 176400, 192000, 352800,
36 384000, 705600, 768000, 1411200, 2822400,
37 };
38
39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
40 .count = ARRAY_SIZE(fsl_sai_rates),
41 .list = fsl_sai_rates,
42 };
43
44 static const char * const inc_mode[] = {
45 "On enabled and bitcount increment", "On enabled"
46 };
47
48 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
49 FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
50 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
51 FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
52
53 static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = {
54 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_SAI_TTCTL,
55 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
56 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
57 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
58 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
59 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_SAI_TTCTL,
60 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
61 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
62 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_SAI_TTCTL,
63 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
64 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
65 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_SAI_TTCTN,
66 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
67 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_SAI_TBCTN,
68 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
69 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_SAI_TTCAP,
70 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
71 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_SAI_RTCTL,
72 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
73 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
74 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
75 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
76 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_SAI_RTCTL,
77 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
78 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
79 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_SAI_RTCTL,
80 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
81 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
82 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_SAI_RTCTN,
83 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
84 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_SAI_RBCTN,
85 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
86 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_SAI_RTCAP,
87 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
88 };
89
90 /**
91 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
92 *
93 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
94 * or Receiver's for both streams. This function is used to check if clocks of
95 * the stream's are synced by the opposite stream.
96 *
97 * @sai: SAI context
98 * @dir: stream direction
99 */
fsl_sai_dir_is_synced(struct fsl_sai * sai,int dir)100 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
101 {
102 int adir = (dir == TX) ? RX : TX;
103
104 /* current dir in async mode while opposite dir in sync mode */
105 return !sai->synchronous[dir] && sai->synchronous[adir];
106 }
107
fsl_sai_get_pins_state(struct fsl_sai * sai,u32 bclk)108 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
109 {
110 struct pinctrl_state *state = NULL;
111
112 if (sai->is_pdm_mode) {
113 /* DSD512@44.1kHz, DSD512@48kHz */
114 if (bclk >= 22579200)
115 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
116
117 /* Get default DSD state */
118 if (IS_ERR_OR_NULL(state))
119 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
120 } else {
121 /* 706k32b2c, 768k32b2c, etc */
122 if (bclk >= 45158400)
123 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
124 }
125
126 /* Get default state */
127 if (IS_ERR_OR_NULL(state))
128 state = pinctrl_lookup_state(sai->pinctrl, "default");
129
130 return state;
131 }
132
fsl_sai_isr(int irq,void * devid)133 static irqreturn_t fsl_sai_isr(int irq, void *devid)
134 {
135 struct fsl_sai *sai = (struct fsl_sai *)devid;
136 unsigned int ofs = sai->soc_data->reg_offset;
137 struct device *dev = &sai->pdev->dev;
138 u32 flags, xcsr, mask;
139 irqreturn_t iret = IRQ_NONE;
140
141 /*
142 * Both IRQ status bits and IRQ mask bits are in the xCSR but
143 * different shifts. And we here create a mask only for those
144 * IRQs that we activated.
145 */
146 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
147
148 /* Tx IRQ */
149 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
150 flags = xcsr & mask;
151
152 if (flags)
153 iret = IRQ_HANDLED;
154 else
155 goto irq_rx;
156
157 if (flags & FSL_SAI_CSR_WSF)
158 dev_dbg(dev, "isr: Start of Tx word detected\n");
159
160 if (flags & FSL_SAI_CSR_SEF)
161 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
162
163 if (flags & FSL_SAI_CSR_FEF)
164 dev_dbg(dev, "isr: Transmit underrun detected\n");
165
166 if (flags & FSL_SAI_CSR_FWF)
167 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
168
169 if (flags & FSL_SAI_CSR_FRF)
170 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
171
172 flags &= FSL_SAI_CSR_xF_W_MASK;
173 xcsr &= ~FSL_SAI_CSR_xF_MASK;
174
175 if (flags)
176 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
177
178 irq_rx:
179 /* Rx IRQ */
180 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
181 flags = xcsr & mask;
182
183 if (flags)
184 iret = IRQ_HANDLED;
185 else
186 goto out;
187
188 if (flags & FSL_SAI_CSR_WSF)
189 dev_dbg(dev, "isr: Start of Rx word detected\n");
190
191 if (flags & FSL_SAI_CSR_SEF)
192 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
193
194 if (flags & FSL_SAI_CSR_FEF)
195 dev_dbg(dev, "isr: Receive overflow detected\n");
196
197 if (flags & FSL_SAI_CSR_FWF)
198 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
199
200 if (flags & FSL_SAI_CSR_FRF)
201 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
202
203 flags &= FSL_SAI_CSR_xF_W_MASK;
204 xcsr &= ~FSL_SAI_CSR_xF_MASK;
205
206 if (flags)
207 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
208
209 out:
210 return iret;
211 }
212
fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)213 static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask,
214 u32 rx_mask, int slots, int slot_width)
215 {
216 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
217 bool tx = true;
218
219 sai->slots[tx] = slots;
220 sai->slot_width[tx] = slot_width;
221
222 return 0;
223 }
224
fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)225 static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask,
226 u32 rx_mask, int slots, int slot_width)
227 {
228 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
229 bool tx = false;
230
231 sai->slots[tx] = slots;
232 sai->slot_width[tx] = slot_width;
233
234 return 0;
235 }
236
fsl_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)237 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
238 u32 rx_mask, int slots, int slot_width)
239 {
240 int ret;
241
242 ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width);
243 if (ret)
244 return ret;
245
246 return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width);
247 }
248
fsl_sai_xlate_tdm_slot_mask(unsigned int slots,unsigned int * tx_mask,unsigned int * rx_mask)249 static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots,
250 unsigned int *tx_mask, unsigned int *rx_mask)
251 {
252 /* Leave it empty, don't change the value of tx_mask and rx_mask */
253 return 0;
254 }
255
fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)256 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
257 unsigned int ratio)
258 {
259 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
260
261 sai->bclk_ratio = ratio;
262
263 return 0;
264 }
265
fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,bool tx)266 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
267 int clk_id, unsigned int freq, bool tx)
268 {
269 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
270 unsigned int ofs = sai->soc_data->reg_offset;
271 u32 val_cr2 = 0;
272
273 switch (clk_id) {
274 case FSL_SAI_CLK_BUS:
275 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
276 break;
277 case FSL_SAI_CLK_MAST1:
278 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
279 break;
280 case FSL_SAI_CLK_MAST2:
281 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
282 break;
283 case FSL_SAI_CLK_MAST3:
284 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
285 break;
286 default:
287 return -EINVAL;
288 }
289
290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
291 FSL_SAI_CR2_MSEL_MASK, val_cr2);
292
293 return 0;
294 }
295
fsl_sai_set_mclk_rate(struct snd_soc_dai * dai,int clk_id,unsigned int freq)296 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
297 {
298 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
299 int ret;
300
301 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
302 sai->pll8k_clk, sai->pll11k_clk, freq);
303
304 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
305 if (ret < 0)
306 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
307
308 return ret;
309 }
310
fsl_sai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)311 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
312 int clk_id, unsigned int freq, int dir)
313 {
314 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
315 int ret;
316
317 if (dir == SND_SOC_CLOCK_IN)
318 return 0;
319
320 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
321 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
322 return -EINVAL;
323 }
324
325 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
326 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
327 return -EINVAL;
328 }
329
330 if (sai->mclk_streams == 0 && freq > 0) {
331 ret = fsl_sai_set_mclk_rate(cpu_dai,
332 clk_id ? clk_id : FSL_SAI_CLK_MAST1,
333 freq);
334 if (ret < 0)
335 return ret;
336 }
337
338 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
339 if (ret) {
340 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
341 return ret;
342 }
343
344 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
345 if (ret)
346 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
347
348 return ret;
349 }
350
fsl_sai_set_dai_fmt_tr(struct snd_soc_dai * cpu_dai,unsigned int fmt,bool tx)351 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
352 unsigned int fmt, bool tx)
353 {
354 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
355 unsigned int ofs = sai->soc_data->reg_offset;
356 u32 val_cr2 = 0, val_cr4 = 0;
357
358 if (sai->is_bit_clock_swap)
359 val_cr2 |= FSL_SAI_CR2_BCS;
360
361 if (!sai->is_lsb_first)
362 val_cr4 |= FSL_SAI_CR4_MF;
363
364 sai->is_pdm_mode = false;
365 sai->is_dsp_mode[tx] = false;
366 /* DAI mode */
367 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
368 case SND_SOC_DAIFMT_I2S:
369 /*
370 * Frame low, 1clk before data, one word length for frame sync,
371 * frame sync starts one serial clock cycle earlier,
372 * that is, together with the last bit of the previous
373 * data word.
374 */
375 val_cr2 |= FSL_SAI_CR2_BCP;
376 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
377 break;
378 case SND_SOC_DAIFMT_LEFT_J:
379 /*
380 * Frame high, one word length for frame sync,
381 * frame sync asserts with the first bit of the frame.
382 */
383 val_cr2 |= FSL_SAI_CR2_BCP;
384 break;
385 case SND_SOC_DAIFMT_DSP_A:
386 /*
387 * Frame high, 1clk before data, one bit for frame sync,
388 * frame sync starts one serial clock cycle earlier,
389 * that is, together with the last bit of the previous
390 * data word.
391 */
392 val_cr2 |= FSL_SAI_CR2_BCP;
393 val_cr4 |= FSL_SAI_CR4_FSE;
394 sai->is_dsp_mode[tx] = true;
395 break;
396 case SND_SOC_DAIFMT_DSP_B:
397 /*
398 * Frame high, one bit for frame sync,
399 * frame sync asserts with the first bit of the frame.
400 */
401 val_cr2 |= FSL_SAI_CR2_BCP;
402 sai->is_dsp_mode[tx] = true;
403 break;
404 case SND_SOC_DAIFMT_PDM:
405 val_cr2 |= FSL_SAI_CR2_BCP;
406 sai->is_pdm_mode = true;
407 break;
408 case SND_SOC_DAIFMT_RIGHT_J:
409 /* To be done */
410 default:
411 return -EINVAL;
412 }
413
414 /* DAI clock inversion */
415 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
416 case SND_SOC_DAIFMT_IB_IF:
417 /* Invert both clocks */
418 val_cr2 ^= FSL_SAI_CR2_BCP;
419 val_cr4 ^= FSL_SAI_CR4_FSP;
420 break;
421 case SND_SOC_DAIFMT_IB_NF:
422 /* Invert bit clock */
423 val_cr2 ^= FSL_SAI_CR2_BCP;
424 break;
425 case SND_SOC_DAIFMT_NB_IF:
426 /* Invert frame clock */
427 val_cr4 ^= FSL_SAI_CR4_FSP;
428 break;
429 case SND_SOC_DAIFMT_NB_NF:
430 /* Nothing to do for both normal cases */
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 /* DAI clock provider masks */
437 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
438 case SND_SOC_DAIFMT_BP_FP:
439 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
440 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
441 sai->is_consumer_mode[tx] = false;
442 break;
443 case SND_SOC_DAIFMT_BC_FC:
444 sai->is_consumer_mode[tx] = true;
445 break;
446 case SND_SOC_DAIFMT_BP_FC:
447 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
448 sai->is_consumer_mode[tx] = false;
449 break;
450 case SND_SOC_DAIFMT_BC_FP:
451 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
452 sai->is_consumer_mode[tx] = true;
453 break;
454 default:
455 return -EINVAL;
456 }
457
458 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
459 FSL_SAI_CR2_BCS | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR,
460 val_cr2);
461 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
462 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
463 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
464
465 return 0;
466 }
467
fsl_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)468 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
469 {
470 int ret;
471
472 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
473 if (ret) {
474 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
475 return ret;
476 }
477
478 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
479 if (ret)
480 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
481
482 return ret;
483 }
484
fsl_sai_set_dai_fmt_tx(struct snd_soc_dai * cpu_dai,unsigned int fmt)485 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
486 {
487 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
488 }
489
fsl_sai_set_dai_fmt_rx(struct snd_soc_dai * cpu_dai,unsigned int fmt)490 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
491 {
492 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
493 }
494
fsl_sai_set_bclk(struct snd_soc_dai * dai,bool tx,u32 freq)495 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
496 {
497 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
498 unsigned int reg, ofs = sai->soc_data->reg_offset;
499 unsigned long clk_rate;
500 u32 savediv = 0, ratio, bestdiff = freq;
501 int adir = tx ? RX : TX;
502 int dir = tx ? TX : RX;
503 u32 id;
504 bool support_1_1_ratio = sai->verid.version >= 0x0301;
505
506 /* Don't apply to consumer mode */
507 if (sai->is_consumer_mode[tx])
508 return 0;
509
510 /*
511 * There is no point in polling MCLK0 if it is identical to MCLK1.
512 * And given that MQS use case has to use MCLK1 though two clocks
513 * are the same, we simply skip MCLK0 and start to find from MCLK1.
514 */
515 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
516
517 for (; id < FSL_SAI_MCLK_MAX; id++) {
518 int diff;
519
520 clk_rate = clk_get_rate(sai->mclk_clk[id]);
521 if (!clk_rate)
522 continue;
523
524 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
525 if (!ratio || ratio > 512)
526 continue;
527 if (ratio == 1 && !support_1_1_ratio)
528 continue;
529 if ((ratio & 1) && ratio > 1)
530 continue;
531
532 diff = abs((long)clk_rate - ratio * freq);
533
534 /*
535 * Drop the source that can not be
536 * divided into the required rate.
537 */
538 if (diff != 0 && clk_rate / diff < 1000)
539 continue;
540
541 dev_dbg(dai->dev,
542 "ratio %d for freq %dHz based on clock %ldHz\n",
543 ratio, freq, clk_rate);
544
545
546 if (diff < bestdiff) {
547 savediv = ratio;
548 sai->mclk_id[tx] = id;
549 bestdiff = diff;
550 }
551
552 if (diff == 0)
553 break;
554 }
555
556 if (savediv == 0) {
557 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
558 tx ? 'T' : 'R', freq);
559 return -EINVAL;
560 }
561
562 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
563 sai->mclk_id[tx], savediv, bestdiff);
564
565 /*
566 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
567 * set TCR2 register for playback.
568 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
569 * and capture.
570 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
571 * and capture.
572 * 4) For Tx and Rx are both Synchronous with another SAI, we just
573 * ignore it.
574 */
575 if (fsl_sai_dir_is_synced(sai, adir))
576 reg = FSL_SAI_xCR2(!tx, ofs);
577 else if (!sai->synchronous[dir])
578 reg = FSL_SAI_xCR2(tx, ofs);
579 else
580 return 0;
581
582 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
583 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
584
585 if (savediv == 1) {
586 regmap_update_bits(sai->regmap, reg,
587 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
588 FSL_SAI_CR2_BYP);
589 if (fsl_sai_dir_is_synced(sai, adir))
590 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
591 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
592 else
593 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
594 FSL_SAI_CR2_BCI, 0);
595 } else {
596 regmap_update_bits(sai->regmap, reg,
597 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
598 savediv / 2 - 1);
599 }
600
601 return 0;
602 }
603
fsl_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)604 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
605 struct snd_pcm_hw_params *params,
606 struct snd_soc_dai *cpu_dai)
607 {
608 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
609 unsigned int ofs = sai->soc_data->reg_offset;
610 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
611 unsigned int channels = params_channels(params);
612 struct snd_dmaengine_dai_dma_data *dma_params;
613 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
614 u32 word_width = params_width(params);
615 int trce_mask = 0, dl_cfg_idx = 0;
616 int dl_cfg_cnt = sai->dl_cfg_cnt;
617 u32 dl_type = FSL_SAI_DL_I2S;
618 u32 val_cr4 = 0, val_cr5 = 0;
619 u32 slots = (channels == 1) ? 2 : channels;
620 u32 slot_width = word_width;
621 int adir = tx ? RX : TX;
622 u32 pins, bclk;
623 u32 watermark;
624 int ret, i;
625
626 if (sai->slot_width[tx])
627 slot_width = sai->slot_width[tx];
628
629 if (sai->slots[tx])
630 slots = sai->slots[tx];
631 else if (sai->bclk_ratio)
632 slots = sai->bclk_ratio / slot_width;
633
634 pins = DIV_ROUND_UP(channels, slots);
635
636 /*
637 * PDM mode, channels are independent
638 * each channels are on one dataline/FIFO.
639 */
640 if (sai->is_pdm_mode) {
641 pins = channels;
642 dl_type = FSL_SAI_DL_PDM;
643 }
644
645 for (i = 0; i < dl_cfg_cnt; i++) {
646 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
647 dl_cfg_idx = i;
648 break;
649 }
650 }
651
652 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
653 dev_err(cpu_dai->dev, "channel not supported\n");
654 return -EINVAL;
655 }
656
657 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
658
659 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
660 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
661 if (!IS_ERR_OR_NULL(sai->pins_state)) {
662 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
663 if (ret) {
664 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
665 return ret;
666 }
667 }
668 }
669
670 if (!sai->is_consumer_mode[tx]) {
671 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
672 if (ret)
673 return ret;
674
675 /* Do not enable the clock if it is already enabled */
676 if (!(sai->mclk_streams & BIT(substream->stream))) {
677 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
678 if (ret)
679 return ret;
680
681 sai->mclk_streams |= BIT(substream->stream);
682 }
683 }
684
685 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode)
686 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
687
688 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
689 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
690
691 if (sai->is_lsb_first)
692 val_cr5 |= FSL_SAI_CR5_FBT(0);
693 else
694 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
695
696 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
697
698 /* Set to avoid channel swap */
699 val_cr4 |= FSL_SAI_CR4_FCONT;
700
701 /* Set to output mode to avoid tri-stated data pins */
702 if (tx)
703 val_cr4 |= FSL_SAI_CR4_CHMOD;
704
705 /*
706 * When Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will provide bclk and
707 * frame clock for Tx(Rx). We should set RCR4(TCR4), RCR5(TCR5)
708 * for playback(capture), or there will be sync error.
709 */
710
711 if (fsl_sai_dir_is_synced(sai, adir)) {
712 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
713 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
714 FSL_SAI_CR4_CHMOD_MASK,
715 val_cr4);
716 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
717 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
718 FSL_SAI_CR5_FBT_MASK, val_cr5);
719 }
720
721 /*
722 * Combine mode has limation:
723 * - Can't used for singel dataline/FIFO case except the FIFO0
724 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
725 * are successive and start from FIFO0
726 *
727 * So for common usage, all multi fifo case disable the combine mode.
728 */
729 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
730 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
731 FSL_SAI_CR4_FCOMB_MASK, 0);
732 else
733 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
734 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
735
736 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
737 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
738 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
739
740 if (sai->is_multi_fifo_dma) {
741 sai->audio_config[tx].words_per_fifo = min(slots, channels);
742 if (tx) {
743 sai->audio_config[tx].n_fifos_dst = pins;
744 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
745 } else {
746 sai->audio_config[tx].n_fifos_src = pins;
747 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
748 }
749 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
750 dma_params->peripheral_config = &sai->audio_config[tx];
751 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
752
753 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
754 (dma_params->maxburst - 1);
755 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
756 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
757 watermark);
758 }
759
760 /* Find a proper tcre setting */
761 for (i = 0; i < sai->soc_data->pins; i++) {
762 trce_mask = (1 << (i + 1)) - 1;
763 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
764 break;
765 }
766
767 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
768 FSL_SAI_CR3_TRCE_MASK,
769 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
770
771 /*
772 * When the TERE and FSD_MSTR enabled before configuring the word width
773 * There will be no frame sync clock issue, because word width impact
774 * the generation of frame sync clock.
775 *
776 * TERE enabled earlier only for i.MX8MP case for the hardware limitation,
777 * We need to disable FSD_MSTR before configuring word width, then enable
778 * FSD_MSTR bit for this specific case.
779 */
780 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
781 !sai->is_consumer_mode[tx])
782 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
783 FSL_SAI_CR4_FSD_MSTR, 0);
784
785 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
786 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
787 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK,
788 val_cr4);
789 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
790 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
791 FSL_SAI_CR5_FBT_MASK, val_cr5);
792
793 /* Enable FSD_MSTR after configuring word width */
794 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
795 !sai->is_consumer_mode[tx])
796 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
797 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR);
798
799 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
800 ~GENMASK_U32(min(channels, slots) - 1, 0));
801
802 return 0;
803 }
804
fsl_sai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)805 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
806 struct snd_soc_dai *cpu_dai)
807 {
808 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
809 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
810 unsigned int ofs = sai->soc_data->reg_offset;
811 int adir = tx ? RX : TX;
812 int dir = tx ? TX : RX;
813
814 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */
815 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);
816
817 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
818 FSL_SAI_CR3_TRCE_MASK, 0);
819
820 if (!sai->is_consumer_mode[tx]) {
821 bool adir_active = !!(sai->mclk_streams & BIT(!substream->stream));
822 /*
823 * If opposite stream provides clocks for synchronous mode and
824 * it is inactive, Clear BYP and BCI
825 */
826 if (fsl_sai_dir_is_synced(sai, adir) && !adir_active)
827 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
828 FSL_SAI_CR2_BCI | FSL_SAI_CR2_BYP, 0);
829 /*
830 * Clear BYP and BCI of current stream if either of:
831 * 1. current stream doesn't provide clocks for synchronous mode
832 * 2. current stream provides clocks for synchronous mode but no
833 * more stream is active.
834 */
835 if (!fsl_sai_dir_is_synced(sai, dir) || !adir_active)
836 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
837 FSL_SAI_CR2_BCI | FSL_SAI_CR2_BYP, 0);
838
839 if (sai->mclk_streams & BIT(substream->stream)) {
840 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
841 sai->mclk_streams &= ~BIT(substream->stream);
842 }
843 }
844
845 return 0;
846 }
847
fsl_sai_config_disable(struct fsl_sai * sai,int dir)848 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
849 {
850 unsigned int ofs = sai->soc_data->reg_offset;
851 bool tx = dir == TX;
852 u32 xcsr, count = 100, mask;
853
854 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
855 mask = FSL_SAI_CSR_TERE;
856 else
857 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
858
859 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
860 mask, 0);
861
862 /* TERE will remain set till the end of current frame */
863 do {
864 udelay(10);
865 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
866 } while (--count && xcsr & FSL_SAI_CSR_TERE);
867
868 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
869 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
870
871 /*
872 * For sai master mode, after several open/close sai,
873 * there will be no frame clock, and can't recover
874 * anymore. Add software reset to fix this issue.
875 * This is a hardware bug, and will be fix in the
876 * next sai version.
877 *
878 * In consumer mode, this can happen even after a
879 * single open/close, especially if both tx and rx
880 * are running concurrently.
881 */
882 /* Software Reset */
883 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
884 /* Clear SR bit to finish the reset */
885 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0);
886 }
887
fsl_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)888 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
889 struct snd_soc_dai *cpu_dai)
890 {
891 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
892 unsigned int ofs = sai->soc_data->reg_offset;
893
894 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
895 int adir = tx ? RX : TX;
896 int dir = tx ? TX : RX;
897 u32 xcsr;
898
899 /*
900 * Asynchronous mode: Clear SYNC for both Tx and Rx.
901 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
902 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
903 */
904 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
905 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
906 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
907 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
908
909 /*
910 * It is recommended that the transmitter is the last enabled
911 * and the first disabled.
912 */
913 switch (cmd) {
914 case SNDRV_PCM_TRIGGER_START:
915 case SNDRV_PCM_TRIGGER_RESUME:
916 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
917 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
918 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
919
920 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
921 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
922 /*
923 * Enable the opposite direction for synchronous mode
924 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
925 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
926 *
927 * RM recommends to enable RE after TE for case 1 and to enable
928 * TE after RE for case 2, but we here may not always guarantee
929 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
930 * TE after RE, which is against what RM recommends but should
931 * be safe to do, judging by years of testing results.
932 */
933 if (fsl_sai_dir_is_synced(sai, adir))
934 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
935 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
936
937 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
938 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
939 break;
940 case SNDRV_PCM_TRIGGER_STOP:
941 case SNDRV_PCM_TRIGGER_SUSPEND:
942 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
943 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
944 FSL_SAI_CSR_FRDE, 0);
945 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
946 FSL_SAI_CSR_xIE_MASK, 0);
947
948 /* Check if the opposite FRDE is also disabled */
949 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
950
951 /*
952 * If opposite stream provides clocks for synchronous mode and
953 * it is inactive, disable it before disabling the current one
954 */
955 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
956 fsl_sai_config_disable(sai, adir);
957
958 /*
959 * Disable current stream if either of:
960 * 1. current stream doesn't provide clocks for synchronous mode
961 * 2. current stream provides clocks for synchronous mode but no
962 * more stream is active.
963 */
964 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
965 fsl_sai_config_disable(sai, dir);
966
967 break;
968 default:
969 return -EINVAL;
970 }
971
972 return 0;
973 }
974
fsl_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)975 static int fsl_sai_startup(struct snd_pcm_substream *substream,
976 struct snd_soc_dai *cpu_dai)
977 {
978 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
979 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
980 int ret;
981
982 /*
983 * EDMA controller needs period size to be a multiple of
984 * tx/rx maxburst
985 */
986 if (sai->soc_data->use_edma)
987 snd_pcm_hw_constraint_step(substream->runtime, 0,
988 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
989 tx ? sai->dma_params_tx.maxburst :
990 sai->dma_params_rx.maxburst);
991
992 if (sai->is_consumer_mode[tx])
993 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
994 SNDRV_PCM_HW_PARAM_RATE,
995 &fsl_sai_rate_constraints);
996 else
997 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
998 SNDRV_PCM_HW_PARAM_RATE,
999 &sai->constraint_rates);
1000
1001 return ret;
1002 }
1003
fsl_sai_dai_probe(struct snd_soc_dai * cpu_dai)1004 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1005 {
1006 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
1007 unsigned int ofs = sai->soc_data->reg_offset;
1008
1009 /* Software Reset for both Tx and Rx */
1010 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1011 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1012 /* Clear SR bit to finish the reset */
1013 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
1014 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
1015
1016 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
1017 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
1018 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
1019 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
1020 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
1021 sai->dma_params_rx.maxburst - 1);
1022
1023 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
1024 &sai->dma_params_rx);
1025
1026 return 0;
1027 }
1028
1029 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
1030 .probe = fsl_sai_dai_probe,
1031 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
1032 .set_sysclk = fsl_sai_set_dai_sysclk,
1033 .set_fmt = fsl_sai_set_dai_fmt,
1034 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
1035 .hw_params = fsl_sai_hw_params,
1036 .hw_free = fsl_sai_hw_free,
1037 .trigger = fsl_sai_trigger,
1038 .startup = fsl_sai_startup,
1039 };
1040
1041 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = {
1042 .probe = fsl_sai_dai_probe,
1043 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
1044 .set_sysclk = fsl_sai_set_dai_sysclk,
1045 .set_fmt = fsl_sai_set_dai_fmt_tx,
1046 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_tx,
1047 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask,
1048 .hw_params = fsl_sai_hw_params,
1049 .hw_free = fsl_sai_hw_free,
1050 .trigger = fsl_sai_trigger,
1051 .startup = fsl_sai_startup,
1052 };
1053
1054 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = {
1055 .probe = fsl_sai_dai_probe,
1056 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
1057 .set_sysclk = fsl_sai_set_dai_sysclk,
1058 .set_fmt = fsl_sai_set_dai_fmt_rx,
1059 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_rx,
1060 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask,
1061 .hw_params = fsl_sai_hw_params,
1062 .hw_free = fsl_sai_hw_free,
1063 .trigger = fsl_sai_trigger,
1064 .startup = fsl_sai_startup,
1065 };
1066
fsl_sai_dai_resume(struct snd_soc_component * component)1067 static int fsl_sai_dai_resume(struct snd_soc_component *component)
1068 {
1069 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
1070 struct device *dev = &sai->pdev->dev;
1071 int ret;
1072
1073 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
1074 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
1075 if (ret) {
1076 dev_err(dev, "failed to set proper pins state: %d\n", ret);
1077 return ret;
1078 }
1079 }
1080
1081 return 0;
1082 }
1083
fsl_sai_component_probe(struct snd_soc_component * component)1084 static int fsl_sai_component_probe(struct snd_soc_component *component)
1085 {
1086 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
1087
1088 if (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN)
1089 snd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls,
1090 ARRAY_SIZE(fsl_sai_timestamp_ctrls));
1091
1092 return 0;
1093 }
1094
1095 static struct snd_soc_dai_driver fsl_sai_dai_template[] = {
1096 {
1097 .name = "sai-tx-rx",
1098 .playback = {
1099 .stream_name = "CPU-Playback",
1100 .channels_min = 1,
1101 .channels_max = 32,
1102 .rate_min = 8000,
1103 .rate_max = 2822400,
1104 .rates = SNDRV_PCM_RATE_KNOT,
1105 .formats = FSL_SAI_FORMATS,
1106 },
1107 .capture = {
1108 .stream_name = "CPU-Capture",
1109 .channels_min = 1,
1110 .channels_max = 32,
1111 .rate_min = 8000,
1112 .rate_max = 2822400,
1113 .rates = SNDRV_PCM_RATE_KNOT,
1114 .formats = FSL_SAI_FORMATS,
1115 },
1116 .ops = &fsl_sai_pcm_dai_ops,
1117 },
1118 {
1119 .name = "sai-tx",
1120 .playback = {
1121 .stream_name = "SAI-Playback",
1122 .channels_min = 1,
1123 .channels_max = 32,
1124 .rate_min = 8000,
1125 .rate_max = 2822400,
1126 .rates = SNDRV_PCM_RATE_KNOT,
1127 .formats = FSL_SAI_FORMATS,
1128 },
1129 .ops = &fsl_sai_pcm_dai_tx_ops,
1130 },
1131 {
1132 .name = "sai-rx",
1133 .capture = {
1134 .stream_name = "SAI-Capture",
1135 .channels_min = 1,
1136 .channels_max = 32,
1137 .rate_min = 8000,
1138 .rate_max = 2822400,
1139 .rates = SNDRV_PCM_RATE_KNOT,
1140 .formats = FSL_SAI_FORMATS,
1141 },
1142 .ops = &fsl_sai_pcm_dai_rx_ops,
1143 },
1144 };
1145
1146 static const struct snd_soc_component_driver fsl_component = {
1147 .name = "fsl-sai",
1148 .probe = fsl_sai_component_probe,
1149 .resume = fsl_sai_dai_resume,
1150 .legacy_dai_naming = 1,
1151 };
1152
1153 static const struct reg_default fsl_sai_reg_defaults_ofs0[] = {
1154 {FSL_SAI_TCR1(0), 0},
1155 {FSL_SAI_TCR2(0), 0},
1156 {FSL_SAI_TCR3(0), 0},
1157 {FSL_SAI_TCR4(0), 0},
1158 {FSL_SAI_TCR5(0), 0},
1159 {FSL_SAI_TDR0, 0},
1160 {FSL_SAI_TDR1, 0},
1161 {FSL_SAI_TDR2, 0},
1162 {FSL_SAI_TDR3, 0},
1163 {FSL_SAI_TDR4, 0},
1164 {FSL_SAI_TDR5, 0},
1165 {FSL_SAI_TDR6, 0},
1166 {FSL_SAI_TDR7, 0},
1167 {FSL_SAI_TMR, 0},
1168 {FSL_SAI_TTCTL, 0},
1169 {FSL_SAI_RCR1(0), 0},
1170 {FSL_SAI_RCR2(0), 0},
1171 {FSL_SAI_RCR3(0), 0},
1172 {FSL_SAI_RCR4(0), 0},
1173 {FSL_SAI_RCR5(0), 0},
1174 {FSL_SAI_RMR, 0},
1175 };
1176
1177 static const struct reg_default fsl_sai_reg_defaults_ofs8[] = {
1178 {FSL_SAI_TCR1(8), 0},
1179 {FSL_SAI_TCR2(8), 0},
1180 {FSL_SAI_TCR3(8), 0},
1181 {FSL_SAI_TCR4(8), 0},
1182 {FSL_SAI_TCR5(8), 0},
1183 {FSL_SAI_TDR0, 0},
1184 {FSL_SAI_TDR1, 0},
1185 {FSL_SAI_TDR2, 0},
1186 {FSL_SAI_TDR3, 0},
1187 {FSL_SAI_TDR4, 0},
1188 {FSL_SAI_TDR5, 0},
1189 {FSL_SAI_TDR6, 0},
1190 {FSL_SAI_TDR7, 0},
1191 {FSL_SAI_TMR, 0},
1192 {FSL_SAI_TTCTL, 0},
1193 {FSL_SAI_RCR1(8), 0},
1194 {FSL_SAI_RCR2(8), 0},
1195 {FSL_SAI_RCR3(8), 0},
1196 {FSL_SAI_RCR4(8), 0},
1197 {FSL_SAI_RCR5(8), 0},
1198 {FSL_SAI_RMR, 0},
1199 {FSL_SAI_RTCTL, 0},
1200 {FSL_SAI_MCTL, 0},
1201 {FSL_SAI_MDIV, 0},
1202 };
1203
fsl_sai_readable_reg(struct device * dev,unsigned int reg)1204 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
1205 {
1206 struct fsl_sai *sai = dev_get_drvdata(dev);
1207 unsigned int ofs = sai->soc_data->reg_offset;
1208
1209 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1210 return true;
1211
1212 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1213 return true;
1214
1215 switch (reg) {
1216 case FSL_SAI_TFR0:
1217 case FSL_SAI_TFR1:
1218 case FSL_SAI_TFR2:
1219 case FSL_SAI_TFR3:
1220 case FSL_SAI_TFR4:
1221 case FSL_SAI_TFR5:
1222 case FSL_SAI_TFR6:
1223 case FSL_SAI_TFR7:
1224 case FSL_SAI_TMR:
1225 case FSL_SAI_RDR0:
1226 case FSL_SAI_RDR1:
1227 case FSL_SAI_RDR2:
1228 case FSL_SAI_RDR3:
1229 case FSL_SAI_RDR4:
1230 case FSL_SAI_RDR5:
1231 case FSL_SAI_RDR6:
1232 case FSL_SAI_RDR7:
1233 case FSL_SAI_RFR0:
1234 case FSL_SAI_RFR1:
1235 case FSL_SAI_RFR2:
1236 case FSL_SAI_RFR3:
1237 case FSL_SAI_RFR4:
1238 case FSL_SAI_RFR5:
1239 case FSL_SAI_RFR6:
1240 case FSL_SAI_RFR7:
1241 case FSL_SAI_RMR:
1242 case FSL_SAI_MCTL:
1243 case FSL_SAI_MDIV:
1244 case FSL_SAI_VERID:
1245 case FSL_SAI_PARAM:
1246 case FSL_SAI_TTCTN:
1247 case FSL_SAI_RTCTN:
1248 case FSL_SAI_TTCTL:
1249 case FSL_SAI_TBCTN:
1250 case FSL_SAI_TTCAP:
1251 case FSL_SAI_RTCTL:
1252 case FSL_SAI_RBCTN:
1253 case FSL_SAI_RTCAP:
1254 return true;
1255 default:
1256 return false;
1257 }
1258 }
1259
fsl_sai_volatile_reg(struct device * dev,unsigned int reg)1260 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1261 {
1262 struct fsl_sai *sai = dev_get_drvdata(dev);
1263 unsigned int ofs = sai->soc_data->reg_offset;
1264
1265 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1266 return true;
1267
1268 /* Set VERID and PARAM be volatile for reading value in probe */
1269 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1270 return true;
1271
1272 switch (reg) {
1273 case FSL_SAI_TFR0:
1274 case FSL_SAI_TFR1:
1275 case FSL_SAI_TFR2:
1276 case FSL_SAI_TFR3:
1277 case FSL_SAI_TFR4:
1278 case FSL_SAI_TFR5:
1279 case FSL_SAI_TFR6:
1280 case FSL_SAI_TFR7:
1281 case FSL_SAI_RFR0:
1282 case FSL_SAI_RFR1:
1283 case FSL_SAI_RFR2:
1284 case FSL_SAI_RFR3:
1285 case FSL_SAI_RFR4:
1286 case FSL_SAI_RFR5:
1287 case FSL_SAI_RFR6:
1288 case FSL_SAI_RFR7:
1289 case FSL_SAI_RDR0:
1290 case FSL_SAI_RDR1:
1291 case FSL_SAI_RDR2:
1292 case FSL_SAI_RDR3:
1293 case FSL_SAI_RDR4:
1294 case FSL_SAI_RDR5:
1295 case FSL_SAI_RDR6:
1296 case FSL_SAI_RDR7:
1297 case FSL_SAI_TTCTN:
1298 case FSL_SAI_RTCTN:
1299 case FSL_SAI_TTCTL:
1300 case FSL_SAI_TBCTN:
1301 case FSL_SAI_TTCAP:
1302 case FSL_SAI_RTCTL:
1303 case FSL_SAI_RBCTN:
1304 case FSL_SAI_RTCAP:
1305 return true;
1306 default:
1307 return false;
1308 }
1309 }
1310
fsl_sai_writeable_reg(struct device * dev,unsigned int reg)1311 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1312 {
1313 struct fsl_sai *sai = dev_get_drvdata(dev);
1314 unsigned int ofs = sai->soc_data->reg_offset;
1315
1316 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1317 return true;
1318
1319 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1320 return true;
1321
1322 switch (reg) {
1323 case FSL_SAI_TDR0:
1324 case FSL_SAI_TDR1:
1325 case FSL_SAI_TDR2:
1326 case FSL_SAI_TDR3:
1327 case FSL_SAI_TDR4:
1328 case FSL_SAI_TDR5:
1329 case FSL_SAI_TDR6:
1330 case FSL_SAI_TDR7:
1331 case FSL_SAI_TMR:
1332 case FSL_SAI_RMR:
1333 case FSL_SAI_MCTL:
1334 case FSL_SAI_MDIV:
1335 case FSL_SAI_TTCTL:
1336 case FSL_SAI_RTCTL:
1337 return true;
1338 default:
1339 return false;
1340 }
1341 }
1342
1343 static struct regmap_config fsl_sai_regmap_config = {
1344 .reg_bits = 32,
1345 .reg_stride = 4,
1346 .val_bits = 32,
1347
1348 .max_register = FSL_SAI_RMR,
1349 .reg_defaults = fsl_sai_reg_defaults_ofs0,
1350 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1351 .readable_reg = fsl_sai_readable_reg,
1352 .volatile_reg = fsl_sai_volatile_reg,
1353 .writeable_reg = fsl_sai_writeable_reg,
1354 .cache_type = REGCACHE_FLAT,
1355 };
1356
fsl_sai_check_version(struct device * dev)1357 static int fsl_sai_check_version(struct device *dev)
1358 {
1359 struct fsl_sai *sai = dev_get_drvdata(dev);
1360 unsigned char ofs = sai->soc_data->reg_offset;
1361 unsigned int val;
1362 int ret;
1363
1364 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1365 return 0;
1366
1367 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1368 if (ret < 0)
1369 return ret;
1370
1371 dev_dbg(dev, "VERID: 0x%016X\n", val);
1372
1373 sai->verid.version = val &
1374 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1375 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1376 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1377
1378 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1379 if (ret < 0)
1380 return ret;
1381
1382 dev_dbg(dev, "PARAM: 0x%016X\n", val);
1383
1384 /* Max slots per frame, power of 2 */
1385 sai->param.slot_num = 1 <<
1386 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1387
1388 /* Words per fifo, power of 2 */
1389 sai->param.fifo_depth = 1 <<
1390 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1391
1392 /* Number of datalines implemented */
1393 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1394
1395 return 0;
1396 }
1397
fsl_sai_reset_hw(struct device * dev)1398 static int fsl_sai_reset_hw(struct device *dev)
1399 {
1400 struct fsl_sai *sai = dev_get_drvdata(dev);
1401 unsigned char ofs = sai->soc_data->reg_offset;
1402 int ret;
1403
1404 /*
1405 * Clear TCSR/RCSR to reset SAI and disable all interrupts.
1406 * Bootloader may leave SAI running causing interrupt storm.
1407 */
1408 ret = regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1409 if (ret) {
1410 dev_err(dev, "Failed to clear TCSR: %d\n", ret);
1411 return ret;
1412 }
1413
1414 ret = regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1415 if (ret) {
1416 dev_err(dev, "Failed to clear RCSR: %d\n", ret);
1417 return ret;
1418 }
1419
1420 return 0;
1421 }
1422
1423 /*
1424 * Calculate the offset between first two datalines, don't
1425 * different offset in one case.
1426 */
fsl_sai_calc_dl_off(unsigned long dl_mask)1427 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1428 {
1429 int fbidx, nbidx, offset;
1430
1431 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1432 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1433 offset = nbidx - fbidx - 1;
1434
1435 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1436 }
1437
1438 /*
1439 * read the fsl,dataline property from dts file.
1440 * It has 3 value for each configuration, first one means the type:
1441 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1442 * dataline mask for 'tx'. for example
1443 *
1444 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1445 *
1446 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1447 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1448 *
1449 */
fsl_sai_read_dlcfg(struct fsl_sai * sai)1450 static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1451 {
1452 struct platform_device *pdev = sai->pdev;
1453 struct device_node *np = pdev->dev.of_node;
1454 struct device *dev = &pdev->dev;
1455 int ret, elems, i, index, num_cfg;
1456 char *propname = "fsl,dataline";
1457 struct fsl_sai_dl_cfg *cfg;
1458 unsigned long dl_mask;
1459 unsigned int soc_dl;
1460 u32 rx, tx, type;
1461
1462 elems = of_property_count_u32_elems(np, propname);
1463
1464 if (elems <= 0) {
1465 elems = 0;
1466 } else if (elems % 3) {
1467 dev_err(dev, "Number of elements must be divisible to 3.\n");
1468 return -EINVAL;
1469 }
1470
1471 num_cfg = elems / 3;
1472 /* Add one more for default value */
1473 cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL);
1474 if (!cfg)
1475 return -ENOMEM;
1476
1477 /* Consider default value "0 0xFF 0xFF" if property is missing */
1478 soc_dl = BIT(sai->soc_data->pins) - 1;
1479 cfg[0].type = FSL_SAI_DL_DEFAULT;
1480 cfg[0].pins[0] = sai->soc_data->pins;
1481 cfg[0].mask[0] = soc_dl;
1482 cfg[0].start_off[0] = 0;
1483 cfg[0].next_off[0] = 0;
1484
1485 cfg[0].pins[1] = sai->soc_data->pins;
1486 cfg[0].mask[1] = soc_dl;
1487 cfg[0].start_off[1] = 0;
1488 cfg[0].next_off[1] = 0;
1489 for (i = 1, index = 0; i < num_cfg + 1; i++) {
1490 /*
1491 * type of dataline
1492 * 0 means default mode
1493 * 1 means I2S mode
1494 * 2 means PDM mode
1495 */
1496 ret = of_property_read_u32_index(np, propname, index++, &type);
1497 if (ret)
1498 return -EINVAL;
1499
1500 ret = of_property_read_u32_index(np, propname, index++, &rx);
1501 if (ret)
1502 return -EINVAL;
1503
1504 ret = of_property_read_u32_index(np, propname, index++, &tx);
1505 if (ret)
1506 return -EINVAL;
1507
1508 if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1509 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1510 return -EINVAL;
1511 }
1512
1513 rx = rx & soc_dl;
1514 tx = tx & soc_dl;
1515
1516 cfg[i].type = type;
1517 cfg[i].pins[0] = hweight8(rx);
1518 cfg[i].mask[0] = rx;
1519 dl_mask = rx;
1520 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1521 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1522
1523 cfg[i].pins[1] = hweight8(tx);
1524 cfg[i].mask[1] = tx;
1525 dl_mask = tx;
1526 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1527 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1528 }
1529
1530 sai->dl_cfg = cfg;
1531 sai->dl_cfg_cnt = num_cfg + 1;
1532 return 0;
1533 }
1534
1535 static int fsl_sai_runtime_suspend(struct device *dev);
1536 static int fsl_sai_runtime_resume(struct device *dev);
1537
fsl_sai_probe(struct platform_device * pdev)1538 static int fsl_sai_probe(struct platform_device *pdev)
1539 {
1540 struct device_node *np = pdev->dev.of_node;
1541 struct device *dev = &pdev->dev;
1542 struct fsl_sai *sai;
1543 struct regmap *gpr;
1544 void __iomem *base;
1545 const char *str = NULL;
1546 char tmp[8];
1547 int irq, ret, i;
1548 int index;
1549 u32 dmas[4];
1550 u32 val;
1551
1552 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1553 if (!sai)
1554 return -ENOMEM;
1555
1556 sai->pdev = pdev;
1557 sai->soc_data = of_device_get_match_data(dev);
1558
1559 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1560 sai->is_bit_clock_swap = of_property_read_bool(np, "fsl,sai-bit-clock-swap");
1561
1562 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1563 if (IS_ERR(base))
1564 return PTR_ERR(base);
1565
1566 if (sai->soc_data->reg_offset == 8) {
1567 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1568 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1569 fsl_sai_regmap_config.num_reg_defaults =
1570 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1571 }
1572
1573 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1574 if (IS_ERR(sai->regmap)) {
1575 dev_err(dev, "regmap init failed\n");
1576 return PTR_ERR(sai->regmap);
1577 }
1578
1579 sai->bus_clk = devm_clk_get(dev, "bus");
1580 /* Compatible with old DTB cases */
1581 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1582 sai->bus_clk = devm_clk_get(dev, "sai");
1583 if (IS_ERR(sai->bus_clk)) {
1584 dev_err(dev, "failed to get bus clock: %ld\n",
1585 PTR_ERR(sai->bus_clk));
1586 /* -EPROBE_DEFER */
1587 return PTR_ERR(sai->bus_clk);
1588 }
1589
1590 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1591 sprintf(tmp, "mclk%d", i);
1592 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1593 if (IS_ERR(sai->mclk_clk[i])) {
1594 dev_err(dev, "failed to get mclk%d clock: %ld\n",
1595 i, PTR_ERR(sai->mclk_clk[i]));
1596 sai->mclk_clk[i] = NULL;
1597 }
1598 }
1599
1600 if (sai->soc_data->mclk0_is_mclk1)
1601 sai->mclk_clk[0] = sai->mclk_clk[1];
1602 else
1603 sai->mclk_clk[0] = sai->bus_clk;
1604
1605 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1606 &sai->pll11k_clk);
1607
1608 fsl_asoc_constrain_rates(&sai->constraint_rates,
1609 &fsl_sai_rate_constraints,
1610 sai->pll8k_clk, sai->pll11k_clk, NULL,
1611 sai->constraint_rates_list);
1612
1613 /* Use Multi FIFO mode depending on the support from SDMA script */
1614 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1615 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1616 sai->is_multi_fifo_dma = true;
1617
1618 /* read dataline mask for rx and tx*/
1619 ret = fsl_sai_read_dlcfg(sai);
1620 if (ret < 0) {
1621 dev_err(dev, "failed to read dlcfg %d\n", ret);
1622 return ret;
1623 }
1624
1625 irq = platform_get_irq(pdev, 0);
1626 if (irq < 0)
1627 return irq;
1628
1629 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template,
1630 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template));
1631
1632 /* Sync Tx with Rx as default by following old DT binding */
1633 sai->synchronous[RX] = true;
1634 sai->synchronous[TX] = false;
1635 sai->cpu_dai_drv[0].symmetric_rate = 1;
1636 sai->cpu_dai_drv[0].symmetric_channels = 1;
1637 sai->cpu_dai_drv[0].symmetric_sample_bits = 1;
1638
1639 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1640 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1641 /* error out if both synchronous and asynchronous are present */
1642 dev_err(dev, "invalid binding for synchronous mode\n");
1643 return -EINVAL;
1644 }
1645
1646 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1647 /* Sync Rx with Tx */
1648 sai->synchronous[RX] = false;
1649 sai->synchronous[TX] = true;
1650 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1651 /* Discard all settings for asynchronous mode */
1652 sai->synchronous[RX] = false;
1653 sai->synchronous[TX] = false;
1654 sai->cpu_dai_drv[0].symmetric_rate = 0;
1655 sai->cpu_dai_drv[0].symmetric_channels = 0;
1656 sai->cpu_dai_drv[0].symmetric_sample_bits = 0;
1657 }
1658
1659 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1660
1661 if (sai->mclk_direction_output &&
1662 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1663 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1664 if (IS_ERR(gpr)) {
1665 dev_err(dev, "cannot find iomuxc registers\n");
1666 return PTR_ERR(gpr);
1667 }
1668
1669 index = of_alias_get_id(np, "sai");
1670 if (index < 0)
1671 return index;
1672
1673 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1674 MCLK_DIR(index));
1675 }
1676
1677 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1678 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1679 sai->dma_params_rx.maxburst =
1680 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1681 sai->dma_params_tx.maxburst =
1682 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1683
1684 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1685
1686 platform_set_drvdata(pdev, sai);
1687 pm_runtime_enable(dev);
1688 if (!pm_runtime_enabled(dev)) {
1689 ret = fsl_sai_runtime_resume(dev);
1690 if (ret)
1691 goto err_pm_disable;
1692 }
1693
1694 ret = pm_runtime_resume_and_get(dev);
1695 if (ret < 0)
1696 goto err_pm_get_sync;
1697
1698 /* Get sai version */
1699 ret = fsl_sai_check_version(dev);
1700 if (ret < 0)
1701 dev_warn(dev, "Error reading SAI version: %d\n", ret);
1702
1703 ret = fsl_sai_reset_hw(dev);
1704 if (ret < 0)
1705 dev_warn(dev, "Failed to reset hardware: %d\n", ret);
1706
1707 /* Select MCLK direction */
1708 if (sai->mclk_direction_output &&
1709 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1710 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1711 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1712 }
1713
1714 ret = pm_runtime_put_sync(dev);
1715 if (ret < 0 && ret != -ENOSYS)
1716 goto err_pm_get_sync;
1717
1718 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1719 np->name, sai);
1720 if (ret) {
1721 dev_err(dev, "failed to claim irq %u\n", irq);
1722 goto err_pm_get_sync;
1723 }
1724
1725 if (of_device_is_compatible(np, "fsl,imx952-sai") &&
1726 !of_property_read_string(np, "fsl,sai-amix-mode", &str)) {
1727 if (!strcmp(str, "bypass"))
1728 val = FSL_SAI_AMIX_BYPASS;
1729 else if (!strcmp(str, "audmix"))
1730 val = FSL_SAI_AMIX_AUDMIX;
1731 else
1732 val = FSL_SAI_AMIX_NONE;
1733
1734 if (val < FSL_SAI_AMIX_NONE) {
1735 ret = scmi_imx_misc_ctrl_set(SCMI_IMX952_CTRL_BYPASS_AUDMIX, val);
1736 if (ret) {
1737 dev_err_probe(dev, ret, "Error setting audmix mode\n");
1738 goto err_pm_get_sync;
1739 }
1740 }
1741 }
1742
1743 /*
1744 * Register platform component before registering cpu dai for there
1745 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1746 */
1747 if (sai->soc_data->use_imx_pcm) {
1748 ret = imx_pcm_dma_init(pdev);
1749 if (ret) {
1750 dev_err_probe(dev, ret, "PCM DMA init failed\n");
1751 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1752 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1753 goto err_pm_get_sync;
1754 }
1755 } else {
1756 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1757 if (ret) {
1758 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1759 goto err_pm_get_sync;
1760 }
1761 }
1762
1763 ret = devm_snd_soc_register_component(dev, &fsl_component,
1764 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template));
1765 if (ret)
1766 goto err_pm_get_sync;
1767
1768 return ret;
1769
1770 err_pm_get_sync:
1771 if (!pm_runtime_status_suspended(dev))
1772 fsl_sai_runtime_suspend(dev);
1773 err_pm_disable:
1774 pm_runtime_disable(dev);
1775
1776 return ret;
1777 }
1778
fsl_sai_remove(struct platform_device * pdev)1779 static void fsl_sai_remove(struct platform_device *pdev)
1780 {
1781 pm_runtime_disable(&pdev->dev);
1782 if (!pm_runtime_status_suspended(&pdev->dev))
1783 fsl_sai_runtime_suspend(&pdev->dev);
1784 }
1785
1786 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1787 .use_imx_pcm = false,
1788 .use_edma = false,
1789 .fifo_depth = 32,
1790 .pins = 1,
1791 .reg_offset = 0,
1792 .mclk0_is_mclk1 = false,
1793 .flags = 0,
1794 .max_register = FSL_SAI_RMR,
1795 };
1796
1797 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1798 .use_imx_pcm = true,
1799 .use_edma = false,
1800 .fifo_depth = 32,
1801 .pins = 1,
1802 .reg_offset = 0,
1803 .mclk0_is_mclk1 = true,
1804 .flags = 0,
1805 .max_register = FSL_SAI_RMR,
1806 };
1807
1808 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1809 .use_imx_pcm = true,
1810 .use_edma = false,
1811 .fifo_depth = 16,
1812 .pins = 2,
1813 .reg_offset = 8,
1814 .mclk0_is_mclk1 = false,
1815 .flags = PMQOS_CPU_LATENCY,
1816 .max_register = FSL_SAI_RMR,
1817 };
1818
1819 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1820 .use_imx_pcm = true,
1821 .use_edma = false,
1822 .fifo_depth = 128,
1823 .pins = 8,
1824 .reg_offset = 8,
1825 .mclk0_is_mclk1 = false,
1826 .flags = 0,
1827 .max_register = FSL_SAI_RMR,
1828 };
1829
1830 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1831 .use_imx_pcm = true,
1832 .use_edma = true,
1833 .fifo_depth = 64,
1834 .pins = 4,
1835 .reg_offset = 0,
1836 .mclk0_is_mclk1 = false,
1837 .flags = 0,
1838 .max_register = FSL_SAI_RMR,
1839 };
1840
1841 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1842 .use_imx_pcm = true,
1843 .use_edma = false,
1844 .fifo_depth = 128,
1845 .reg_offset = 8,
1846 .mclk0_is_mclk1 = false,
1847 .pins = 8,
1848 .flags = 0,
1849 .max_register = FSL_SAI_MCTL,
1850 };
1851
1852 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1853 .use_imx_pcm = true,
1854 .use_edma = false,
1855 .fifo_depth = 128,
1856 .reg_offset = 8,
1857 .mclk0_is_mclk1 = false,
1858 .pins = 8,
1859 .flags = 0,
1860 .max_register = FSL_SAI_MDIV,
1861 };
1862
1863 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1864 .use_imx_pcm = true,
1865 .use_edma = false,
1866 .fifo_depth = 128,
1867 .reg_offset = 8,
1868 .mclk0_is_mclk1 = false,
1869 .pins = 8,
1870 .flags = 0,
1871 .max_register = FSL_SAI_MDIV,
1872 .mclk_with_tere = true,
1873 };
1874
1875 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1876 .use_imx_pcm = true,
1877 .use_edma = true,
1878 .fifo_depth = 16,
1879 .reg_offset = 8,
1880 .mclk0_is_mclk1 = false,
1881 .pins = 4,
1882 .flags = PMQOS_CPU_LATENCY,
1883 .max_register = FSL_SAI_RTCAP,
1884 };
1885
1886 static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1887 .use_imx_pcm = true,
1888 .use_edma = true,
1889 .fifo_depth = 128,
1890 .reg_offset = 8,
1891 .mclk0_is_mclk1 = false,
1892 .pins = 4,
1893 .flags = 0,
1894 .max_register = FSL_SAI_MCTL,
1895 .max_burst = {8, 8},
1896 };
1897
1898 static const struct fsl_sai_soc_data fsl_sai_imx95_data = {
1899 .use_imx_pcm = true,
1900 .use_edma = true,
1901 .fifo_depth = 128,
1902 .reg_offset = 8,
1903 .mclk0_is_mclk1 = false,
1904 .pins = 8,
1905 .flags = 0,
1906 .max_register = FSL_SAI_MCTL,
1907 .max_burst = {8, 8},
1908 };
1909
1910 static const struct of_device_id fsl_sai_ids[] = {
1911 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1912 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1913 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1914 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1915 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1916 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1917 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1918 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1919 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1920 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1921 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1922 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data },
1923 { /* sentinel */ }
1924 };
1925 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1926
fsl_sai_runtime_suspend(struct device * dev)1927 static int fsl_sai_runtime_suspend(struct device *dev)
1928 {
1929 struct fsl_sai *sai = dev_get_drvdata(dev);
1930
1931 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1932 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1933
1934 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1935 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1936
1937 clk_disable_unprepare(sai->bus_clk);
1938
1939 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1940 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1941
1942 regcache_cache_only(sai->regmap, true);
1943
1944 return 0;
1945 }
1946
fsl_sai_runtime_resume(struct device * dev)1947 static int fsl_sai_runtime_resume(struct device *dev)
1948 {
1949 struct fsl_sai *sai = dev_get_drvdata(dev);
1950 unsigned int ofs = sai->soc_data->reg_offset;
1951 int ret;
1952
1953 ret = clk_prepare_enable(sai->bus_clk);
1954 if (ret) {
1955 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1956 return ret;
1957 }
1958
1959 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1960 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1961 if (ret)
1962 goto disable_bus_clk;
1963 }
1964
1965 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1966 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1967 if (ret)
1968 goto disable_tx_clk;
1969 }
1970
1971 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1972 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1973
1974 regcache_cache_only(sai->regmap, false);
1975 regcache_mark_dirty(sai->regmap);
1976 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1977 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1978 usleep_range(1000, 2000);
1979 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
1980 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
1981
1982 ret = regcache_sync(sai->regmap);
1983 if (ret)
1984 goto disable_rx_clk;
1985
1986 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1987 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1988 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1989
1990 return 0;
1991
1992 disable_rx_clk:
1993 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1994 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1995 disable_tx_clk:
1996 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1997 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1998 disable_bus_clk:
1999 clk_disable_unprepare(sai->bus_clk);
2000
2001 return ret;
2002 }
2003
2004 static const struct dev_pm_ops fsl_sai_pm_ops = {
2005 RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL)
2006 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
2007 };
2008
2009 static struct platform_driver fsl_sai_driver = {
2010 .probe = fsl_sai_probe,
2011 .remove = fsl_sai_remove,
2012 .driver = {
2013 .name = "fsl-sai",
2014 .pm = pm_ptr(&fsl_sai_pm_ops),
2015 .of_match_table = fsl_sai_ids,
2016 },
2017 };
2018 module_platform_driver(fsl_sai_driver);
2019
2020 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
2021 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
2022 MODULE_ALIAS("platform:fsl-sai");
2023 MODULE_LICENSE("GPL");
2024