1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 *
5 * Copyright (c) 2009, Intel Corporation.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/preempt.h>
14 #include <linux/highmem.h>
15 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
19 #include <linux/string.h>
20 #include <linux/of.h>
21
22 #include "internals.h"
23 #include "spi-dw.h"
24
25 #ifdef CONFIG_DEBUG_FS
26 #include <linux/debugfs.h>
27 #endif
28
29 /* Slave spi_device related */
30 struct dw_spi_chip_data {
31 u32 cr0;
32 u32 rx_sample_dly; /* RX sample delay */
33 };
34
35 #ifdef CONFIG_DEBUG_FS
36
37 #define DW_SPI_DBGFS_REG(_name, _off) \
38 { \
39 .name = _name, \
40 .offset = _off, \
41 }
42
43 static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
44 DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
45 DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
46 DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
47 DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
48 DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
49 DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
50 DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
51 DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
52 DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
53 DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
54 DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
55 DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
56 DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
57 DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
58 DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
59 DW_SPI_DBGFS_REG("RX_SAMPLE_DLY", DW_SPI_RX_SAMPLE_DLY),
60 };
61
dw_spi_debugfs_init(struct dw_spi * dws)62 static void dw_spi_debugfs_init(struct dw_spi *dws)
63 {
64 char name[32];
65
66 snprintf(name, 32, "dw_spi%d", dws->ctlr->bus_num);
67 dws->debugfs = debugfs_create_dir(name, NULL);
68
69 dws->regset.regs = dw_spi_dbgfs_regs;
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
71 dws->regset.base = dws->regs;
72 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
73 }
74
dw_spi_debugfs_remove(struct dw_spi * dws)75 static void dw_spi_debugfs_remove(struct dw_spi *dws)
76 {
77 debugfs_remove_recursive(dws->debugfs);
78 }
79
80 #else
dw_spi_debugfs_init(struct dw_spi * dws)81 static inline void dw_spi_debugfs_init(struct dw_spi *dws)
82 {
83 }
84
dw_spi_debugfs_remove(struct dw_spi * dws)85 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
86 {
87 }
88 #endif /* CONFIG_DEBUG_FS */
89
dw_spi_set_cs(struct spi_device * spi,bool enable)90 void dw_spi_set_cs(struct spi_device *spi, bool enable)
91 {
92 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
93 bool cs_high = !!(spi->mode & SPI_CS_HIGH);
94
95 /*
96 * DW SPI controller demands any native CS being set in order to
97 * proceed with data transfer. So in order to activate the SPI
98 * communications we must set a corresponding bit in the Slave
99 * Enable register no matter whether the SPI core is configured to
100 * support active-high or active-low CS level.
101 */
102 if (cs_high == enable)
103 dw_writel(dws, DW_SPI_SER, BIT(spi_get_chipselect(spi, 0)));
104 else
105 dw_writel(dws, DW_SPI_SER, 0);
106 }
107 EXPORT_SYMBOL_NS_GPL(dw_spi_set_cs, "SPI_DW_CORE");
108
109 /* Return the max entries we can fill into tx fifo */
dw_spi_tx_max(struct dw_spi * dws)110 static inline u32 dw_spi_tx_max(struct dw_spi *dws)
111 {
112 u32 tx_room, rxtx_gap;
113
114 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
115
116 /*
117 * Another concern is about the tx/rx mismatch, we
118 * though to use (dws->fifo_len - rxflr - txflr) as
119 * one maximum value for tx, but it doesn't cover the
120 * data which is out of tx/rx fifo and inside the
121 * shift registers. So a control from sw point of
122 * view is taken.
123 */
124 rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
125
126 return min3((u32)dws->tx_len, tx_room, rxtx_gap);
127 }
128
129 /* Return the max entries we should read out of rx fifo */
dw_spi_rx_max(struct dw_spi * dws)130 static inline u32 dw_spi_rx_max(struct dw_spi *dws)
131 {
132 return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR));
133 }
134
dw_writer(struct dw_spi * dws)135 static void dw_writer(struct dw_spi *dws)
136 {
137 u32 max = dw_spi_tx_max(dws);
138 u32 txw = 0;
139
140 while (max--) {
141 if (dws->tx) {
142 if (dws->n_bytes == 1)
143 txw = *(u8 *)(dws->tx);
144 else if (dws->n_bytes == 2)
145 txw = *(u16 *)(dws->tx);
146 else
147 txw = *(u32 *)(dws->tx);
148
149 dws->tx += dws->n_bytes;
150 }
151 dw_write_io_reg(dws, DW_SPI_DR, txw);
152 --dws->tx_len;
153 }
154 }
155
dw_reader(struct dw_spi * dws)156 static void dw_reader(struct dw_spi *dws)
157 {
158 u32 max = dw_spi_rx_max(dws);
159 u32 rxw;
160
161 while (max--) {
162 rxw = dw_read_io_reg(dws, DW_SPI_DR);
163 if (dws->rx) {
164 if (dws->n_bytes == 1)
165 *(u8 *)(dws->rx) = rxw;
166 else if (dws->n_bytes == 2)
167 *(u16 *)(dws->rx) = rxw;
168 else
169 *(u32 *)(dws->rx) = rxw;
170
171 dws->rx += dws->n_bytes;
172 }
173 --dws->rx_len;
174 }
175 }
176
dw_spi_check_status(struct dw_spi * dws,bool raw)177 int dw_spi_check_status(struct dw_spi *dws, bool raw)
178 {
179 u32 irq_status;
180 int ret = 0;
181
182 if (raw)
183 irq_status = dw_readl(dws, DW_SPI_RISR);
184 else
185 irq_status = dw_readl(dws, DW_SPI_ISR);
186
187 if (irq_status & DW_SPI_INT_RXOI) {
188 dev_err(&dws->ctlr->dev, "RX FIFO overflow detected\n");
189 ret = -EIO;
190 }
191
192 if (irq_status & DW_SPI_INT_RXUI) {
193 dev_err(&dws->ctlr->dev, "RX FIFO underflow detected\n");
194 ret = -EIO;
195 }
196
197 if (irq_status & DW_SPI_INT_TXOI) {
198 dev_err(&dws->ctlr->dev, "TX FIFO overflow detected\n");
199 ret = -EIO;
200 }
201
202 /* Generically handle the erroneous situation */
203 if (ret) {
204 dw_spi_reset_chip(dws);
205 if (dws->ctlr->cur_msg)
206 dws->ctlr->cur_msg->status = ret;
207 }
208
209 return ret;
210 }
211 EXPORT_SYMBOL_NS_GPL(dw_spi_check_status, "SPI_DW_CORE");
212
dw_spi_transfer_handler(struct dw_spi * dws)213 static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
214 {
215 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
216
217 if (dw_spi_check_status(dws, false)) {
218 spi_finalize_current_transfer(dws->ctlr);
219 return IRQ_HANDLED;
220 }
221
222 /*
223 * Read data from the Rx FIFO every time we've got a chance executing
224 * this method. If there is nothing left to receive, terminate the
225 * procedure. Otherwise adjust the Rx FIFO Threshold level if it's a
226 * final stage of the transfer. By doing so we'll get the next IRQ
227 * right when the leftover incoming data is received.
228 */
229 dw_reader(dws);
230 if (!dws->rx_len) {
231 dw_spi_mask_intr(dws, 0xff);
232 spi_finalize_current_transfer(dws->ctlr);
233 } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
234 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
235 }
236
237 /*
238 * Send data out if Tx FIFO Empty IRQ is received. The IRQ will be
239 * disabled after the data transmission is finished so not to
240 * have the TXE IRQ flood at the final stage of the transfer.
241 */
242 if (irq_status & DW_SPI_INT_TXEI) {
243 dw_writer(dws);
244 if (!dws->tx_len)
245 dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
246 }
247
248 return IRQ_HANDLED;
249 }
250
dw_spi_enh_handler(struct dw_spi * dws)251 static irqreturn_t dw_spi_enh_handler(struct dw_spi *dws)
252 {
253 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
254
255 if (irq_status & DW_SPI_INT_RXFI) {
256 dw_reader(dws);
257 if (dws->rx_len && dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR))
258 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
259 }
260
261 if (irq_status & DW_SPI_INT_TXEI)
262 dw_writer(dws);
263
264 if (!dws->tx_len && dws->rx_len) {
265 dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
266 } else if (!dws->rx_len && !dws->tx_len) {
267 dw_spi_mask_intr(dws, 0xff);
268 spi_finalize_current_transfer(dws->ctlr);
269 }
270
271 return IRQ_HANDLED;
272 }
273
dw_spi_irq(int irq,void * dev_id)274 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
275 {
276 struct spi_controller *ctlr = dev_id;
277 struct dw_spi *dws = spi_controller_get_devdata(ctlr);
278 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
279
280 if (!irq_status)
281 return IRQ_NONE;
282
283 if (!dws->transfer_handler ||
284 (!ctlr->cur_msg && dws->transfer_handler == dw_spi_transfer_handler)) {
285 dw_spi_mask_intr(dws, 0xff);
286 return IRQ_HANDLED;
287 }
288 if (dws->transfer_handler == dw_spi_enh_handler &&
289 !dws->rx_len && !dws->tx_len) {
290 dw_spi_mask_intr(dws, 0xff);
291 spi_finalize_current_transfer(ctlr);
292 return IRQ_HANDLED;
293 }
294
295 return dws->transfer_handler(dws);
296 }
297
dw_spi_prepare_cr0(struct dw_spi * dws,struct spi_device * spi)298 static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
299 {
300 u32 cr0 = 0;
301
302 if (dw_spi_ip_is(dws, PSSI)) {
303 /* CTRLR0[ 5: 4] Frame Format */
304 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
305
306 /*
307 * SPI mode (SCPOL|SCPH)
308 * CTRLR0[ 6] Serial Clock Phase
309 * CTRLR0[ 7] Serial Clock Polarity
310 */
311 if (spi->mode & SPI_CPOL)
312 cr0 |= DW_PSSI_CTRLR0_SCPOL;
313 if (spi->mode & SPI_CPHA)
314 cr0 |= DW_PSSI_CTRLR0_SCPHA;
315
316 /* CTRLR0[11] Shift Register Loop */
317 if (spi->mode & SPI_LOOP)
318 cr0 |= DW_PSSI_CTRLR0_SRL;
319 } else {
320 /* CTRLR0[ 7: 6] Frame Format */
321 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
322
323 /*
324 * SPI mode (SCPOL|SCPH)
325 * CTRLR0[ 8] Serial Clock Phase
326 * CTRLR0[ 9] Serial Clock Polarity
327 */
328 if (spi->mode & SPI_CPOL)
329 cr0 |= DW_HSSI_CTRLR0_SCPOL;
330 if (spi->mode & SPI_CPHA)
331 cr0 |= DW_HSSI_CTRLR0_SCPHA;
332
333 /* CTRLR0[13] Shift Register Loop */
334 if (spi->mode & SPI_LOOP)
335 cr0 |= DW_HSSI_CTRLR0_SRL;
336
337 /* CTRLR0[31] MST */
338 if (dw_spi_ver_is_ge(dws, HSSI, 102A))
339 cr0 |= DW_HSSI_CTRLR0_MST;
340 }
341
342 return cr0;
343 }
344
dw_spi_update_config(struct dw_spi * dws,struct spi_device * spi,struct dw_spi_cfg * cfg,struct dw_spi_enh_cfg * enh_cfg)345 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
346 struct dw_spi_cfg *cfg, struct dw_spi_enh_cfg *enh_cfg)
347 {
348 struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
349 u32 cr0 = chip->cr0;
350 u32 speed_hz;
351 u16 clk_div;
352
353 /* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */
354 cr0 |= (cfg->dfs - 1) << dws->dfs_offset;
355
356 if (dw_spi_ip_is(dws, PSSI))
357 /* CTRLR0[ 9:8] Transfer Mode */
358 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode);
359 else
360 /* CTRLR0[11:10] Transfer Mode */
361 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
362
363 if (dw_spi_ver_is_ge(dws, HSSI, 103A)) {
364 cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK;
365 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
366 cfg->spi_frf);
367 } else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) {
368 cr0 &= ~DW_PSSI_CTRLR0_SPI_FRF_MASK;
369 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK,
370 cfg->spi_frf);
371 }
372
373 dw_writel(dws, DW_SPI_CTRLR0, cr0);
374
375 if (spi_controller_is_target(dws->ctlr))
376 return;
377
378 if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
379 cfg->tmode == DW_SPI_CTRLR0_TMOD_RO)
380 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
381 else if (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO &&
382 dws->caps & DW_SPI_CAP_EMODE)
383 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf);
384
385 /* Note DW APB SSI clock divider doesn't support odd numbers */
386 clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
387 speed_hz = dws->max_freq / clk_div;
388
389 if (dws->current_freq != speed_hz) {
390 dw_spi_set_clk(dws, clk_div);
391 dws->current_freq = speed_hz;
392 }
393
394 /* Update RX sample delay if required */
395 if (dws->cur_rx_sample_dly != chip->rx_sample_dly) {
396 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly);
397 dws->cur_rx_sample_dly = chip->rx_sample_dly;
398 }
399
400 if (enh_cfg) {
401 cr0 = DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN;
402 cr0 |= FIELD_PREP(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK, enh_cfg->wait_c);
403 cr0 |= FIELD_PREP(DW_SPI_ENH_CTRLR0_INST_L_MASK, enh_cfg->inst_l);
404 cr0 |= FIELD_PREP(DW_SPI_ENH_CTRLR0_ADDR_L_MASK, enh_cfg->addr_l);
405 cr0 |= FIELD_PREP(DW_SPI_ENH_CTRLR0_TRANS_TYPE_MASK, enh_cfg->trans_t);
406 dw_writel(dws, DW_SPI_SPI_CTRLR0, cr0);
407 }
408 }
409 EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, "SPI_DW_CORE");
410
dw_spi_irq_setup(struct dw_spi * dws)411 static void dw_spi_irq_setup(struct dw_spi *dws)
412 {
413 u16 level;
414 u8 imask;
415
416 /*
417 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
418 * will be adjusted at the final stage of the IRQ-based SPI transfer
419 * execution so not to lose the leftover of the incoming data.
420 */
421 level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len);
422 dw_writel(dws, DW_SPI_TXFTLR, level);
423 dw_writel(dws, DW_SPI_RXFTLR, level - 1);
424
425 dws->transfer_handler = dw_spi_transfer_handler;
426
427 imask = DW_SPI_INT_TXEI | DW_SPI_INT_TXOI |
428 DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI;
429 dw_spi_umask_intr(dws, imask);
430 }
431
dw_spi_enh_irq_setup(struct dw_spi * dws)432 static void dw_spi_enh_irq_setup(struct dw_spi *dws)
433 {
434 u16 level;
435 u8 imask;
436
437 /*
438 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
439 * will be adjusted at the final stage of the IRQ-based SPI transfer
440 * execution so not to lose the leftover of the incoming data.
441 */
442 level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len);
443 dw_writel(dws, DW_SPI_TXFTLR, level);
444
445 /*
446 * In enhanced mode if we are reading then tx_len is 0 as we
447 * have nothing to transmit. Calculate DW_SPI_RXFTLR with
448 * rx_len.
449 */
450 level = min_t(unsigned int, dws->fifo_len / 2, dws->rx_len);
451 dw_writel(dws, DW_SPI_RXFTLR, level ? level - 1 : 0);
452
453 dws->transfer_handler = dw_spi_enh_handler;
454
455 imask = DW_SPI_INT_TXEI | DW_SPI_INT_RXFI;
456 dw_spi_umask_intr(dws, imask);
457 }
458
459 /*
460 * The iterative procedure of the poll-based transfer is simple: write as much
461 * as possible to the Tx FIFO, wait until the pending to receive data is ready
462 * to be read, read it from the Rx FIFO and check whether the performed
463 * procedure has been successful.
464 *
465 * Note this method the same way as the IRQ-based transfer won't work well for
466 * the SPI devices connected to the controller with native CS due to the
467 * automatic CS assertion/de-assertion.
468 */
dw_spi_poll_transfer(struct dw_spi * dws,struct spi_transfer * transfer)469 static int dw_spi_poll_transfer(struct dw_spi *dws,
470 struct spi_transfer *transfer)
471 {
472 struct spi_delay delay;
473 u16 nbits;
474 int ret;
475
476 delay.unit = SPI_DELAY_UNIT_SCK;
477 nbits = dws->n_bytes * BITS_PER_BYTE;
478
479 do {
480 dw_writer(dws);
481
482 delay.value = nbits * (dws->rx_len - dws->tx_len);
483 spi_delay_exec(&delay, transfer);
484
485 dw_reader(dws);
486
487 ret = dw_spi_check_status(dws, true);
488 if (ret)
489 return ret;
490 } while (dws->rx_len);
491
492 return 0;
493 }
494
dw_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * transfer)495 static int dw_spi_transfer_one(struct spi_controller *ctlr,
496 struct spi_device *spi,
497 struct spi_transfer *transfer)
498 {
499 struct dw_spi *dws = spi_controller_get_devdata(ctlr);
500 struct dw_spi_cfg cfg = {
501 .tmode = DW_SPI_CTRLR0_TMOD_TR,
502 .dfs = transfer->bits_per_word,
503 .freq = transfer->speed_hz,
504 .spi_frf = DW_SPI_CTRLR0_SPI_FRF_STD_SPI,
505 };
506 int ret;
507
508 dws->dma_mapped = 0;
509 dws->n_bytes = spi_bpw_to_bytes(transfer->bits_per_word);
510 dws->tx = (void *)transfer->tx_buf;
511 dws->tx_len = transfer->len / dws->n_bytes;
512 dws->rx = transfer->rx_buf;
513 dws->rx_len = dws->tx_len;
514
515 /* Ensure the data above is visible for all CPUs */
516 smp_mb();
517
518 dw_spi_enable_chip(dws, 0);
519
520 dw_spi_update_config(dws, spi, &cfg, NULL);
521
522 transfer->effective_speed_hz = dws->current_freq;
523
524 /* Check if current transfer is a DMA transaction */
525 dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
526
527 /* For poll mode just disable all interrupts */
528 dw_spi_mask_intr(dws, 0xff);
529
530 if (dws->dma_mapped) {
531 ret = dws->dma_ops->dma_setup(dws, transfer);
532 if (ret)
533 return ret;
534 }
535
536 dw_spi_enable_chip(dws, 1);
537
538 if (dws->dma_mapped)
539 return dws->dma_ops->dma_transfer(dws, transfer);
540 else if (dws->irq == IRQ_NOTCONNECTED)
541 return dw_spi_poll_transfer(dws, transfer);
542
543 dw_spi_irq_setup(dws);
544
545 return 1;
546 }
547
dw_spi_abort(struct spi_controller * ctlr)548 static inline void dw_spi_abort(struct spi_controller *ctlr)
549 {
550 struct dw_spi *dws = spi_controller_get_devdata(ctlr);
551
552 if (dws->dma_mapped)
553 dws->dma_ops->dma_stop(dws);
554
555 disable_irq(dws->irq);
556 dw_spi_reset_chip(dws);
557 enable_irq(dws->irq);
558 }
559
dw_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)560 static void dw_spi_handle_err(struct spi_controller *ctlr,
561 struct spi_message *msg)
562 {
563 dw_spi_abort(ctlr);
564 }
565
dw_spi_target_abort(struct spi_controller * ctlr)566 static int dw_spi_target_abort(struct spi_controller *ctlr)
567 {
568 dw_spi_abort(ctlr);
569
570 return 0;
571 }
572
dw_spi_adjust_enh_mem_op_size(struct spi_mem * mem,struct spi_mem_op * op)573 static int dw_spi_adjust_enh_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
574 {
575 if (op->data.dir == SPI_MEM_DATA_IN)
576 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1);
577 else
578 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK);
579
580 return 0;
581 }
582
dw_spi_adjust_mem_op_size(struct spi_mem * mem,struct spi_mem_op * op)583 static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
584 {
585 if (op->data.dir == SPI_MEM_DATA_IN)
586 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1);
587
588 return 0;
589 }
590
dw_spi_supports_enh_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)591 static bool dw_spi_supports_enh_mem_op(struct spi_mem *mem,
592 const struct spi_mem_op *op)
593 {
594 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
595
596 if (op->addr.nbytes != 0 && op->addr.buswidth != 1 &&
597 op->addr.buswidth != op->data.buswidth)
598 return false;
599
600 if (op->addr.nbytes >= 8)
601 return false;
602
603 if (op->cmd.buswidth != 1 && op->cmd.buswidth != op->addr.buswidth &&
604 op->cmd.buswidth != op->data.buswidth)
605 return false;
606
607 if (op->dummy.nbytes && !op->dummy.buswidth)
608 return false;
609
610 if (op->dummy.nbytes != 0 && op->data.dir == SPI_MEM_DATA_OUT)
611 return false;
612
613 /* WAIT_CYCLES is a 5-bit field in SPI_CTRLR0 */
614 if (op->dummy.nbytes != 0 &&
615 op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
616 FIELD_MAX(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK))
617 return false;
618
619 if ((dws->quirk_flags & DW_SPI_QUIRK_JHB100) && op->addr.nbytes &&
620 op->addr.nbytes != 3 && op->addr.nbytes != 4)
621 return false;
622
623 return spi_mem_default_supports_op(mem, op);
624 }
625
dw_spi_supports_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)626 static bool dw_spi_supports_mem_op(struct spi_mem *mem,
627 const struct spi_mem_op *op)
628 {
629 if (op->data.buswidth > 1 || op->addr.buswidth > 1 ||
630 op->dummy.buswidth > 1 || op->cmd.buswidth > 1)
631 return false;
632
633 return spi_mem_default_supports_op(mem, op);
634 }
635
dw_spi_init_mem_buf(struct dw_spi * dws,const struct spi_mem_op * op)636 static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
637 {
638 unsigned int i, j, len;
639 u8 *out;
640
641 /*
642 * Calculate the total length of the EEPROM command transfer and
643 * either use the pre-allocated buffer or create a temporary one.
644 */
645 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
646 if (op->data.dir == SPI_MEM_DATA_OUT)
647 len += op->data.nbytes;
648
649 if (len <= DW_SPI_BUF_SIZE) {
650 out = dws->buf;
651 } else {
652 out = kzalloc(len, GFP_KERNEL);
653 if (!out)
654 return -ENOMEM;
655 }
656
657 /*
658 * Collect the operation code, address and dummy bytes into the single
659 * buffer. If it's a transfer with data to be sent, also copy it into the
660 * single buffer in order to speed the data transmission up.
661 */
662 for (i = 0; i < op->cmd.nbytes; ++i)
663 out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1);
664 for (j = 0; j < op->addr.nbytes; ++i, ++j)
665 out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
666 for (j = 0; j < op->dummy.nbytes; ++i, ++j)
667 out[i] = 0x0;
668
669 if (op->data.dir == SPI_MEM_DATA_OUT)
670 memcpy(&out[i], op->data.buf.out, op->data.nbytes);
671
672 dws->n_bytes = 1;
673 dws->tx = out;
674 dws->tx_len = len;
675 if (op->data.dir == SPI_MEM_DATA_IN) {
676 dws->rx = op->data.buf.in;
677 dws->rx_len = op->data.nbytes;
678 } else {
679 dws->rx = NULL;
680 dws->rx_len = 0;
681 }
682
683 return 0;
684 }
685
dw_spi_free_mem_buf(struct dw_spi * dws)686 static void dw_spi_free_mem_buf(struct dw_spi *dws)
687 {
688 if (dws->tx != dws->buf)
689 kfree(dws->tx);
690 }
691
dw_spi_write_then_read(struct dw_spi * dws,struct spi_device * spi)692 static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
693 {
694 u32 room, entries, sts;
695 unsigned int len;
696 u8 *buf;
697
698 /*
699 * At initial stage we just pre-fill the Tx FIFO in with no rush,
700 * since native CS hasn't been enabled yet and the automatic data
701 * transmission won't start til we do that.
702 */
703 len = min(dws->fifo_len, dws->tx_len);
704 buf = dws->tx;
705 while (len--)
706 dw_write_io_reg(dws, DW_SPI_DR, *buf++);
707
708 /*
709 * After setting any bit in the SER register the transmission will
710 * start automatically. We have to keep up with that procedure
711 * otherwise the CS de-assertion will happen whereupon the memory
712 * operation will be pre-terminated.
713 */
714 len = dws->tx_len - ((void *)buf - dws->tx);
715 dw_spi_set_cs(spi, false);
716 while (len) {
717 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
718 if (!entries) {
719 dev_err(&dws->ctlr->dev, "CS de-assertion on Tx\n");
720 return -EIO;
721 }
722 room = min(dws->fifo_len - entries, len);
723 for (; room; --room, --len)
724 dw_write_io_reg(dws, DW_SPI_DR, *buf++);
725 }
726
727 /*
728 * Data fetching will start automatically if the EEPROM-read mode is
729 * activated. We have to keep up with the incoming data pace to
730 * prevent the Rx FIFO overflow causing the inbound data loss.
731 */
732 len = dws->rx_len;
733 buf = dws->rx;
734 while (len) {
735 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR);
736 if (!entries) {
737 sts = readl_relaxed(dws->regs + DW_SPI_RISR);
738 if (sts & DW_SPI_INT_RXOI) {
739 dev_err(&dws->ctlr->dev, "FIFO overflow on Rx\n");
740 return -EIO;
741 }
742 continue;
743 }
744 entries = min(entries, len);
745 for (; entries; --entries, --len)
746 *buf++ = dw_read_io_reg(dws, DW_SPI_DR);
747 }
748
749 return 0;
750 }
751
dw_spi_ctlr_busy(struct dw_spi * dws)752 static inline bool dw_spi_ctlr_busy(struct dw_spi *dws)
753 {
754 return dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_BUSY;
755 }
756
dw_spi_wait_mem_op_done(struct dw_spi * dws)757 static int dw_spi_wait_mem_op_done(struct dw_spi *dws)
758 {
759 int retry = DW_SPI_WAIT_RETRIES;
760 struct spi_delay delay;
761 unsigned long ns, us;
762 u32 nents;
763
764 nents = dw_readl(dws, DW_SPI_TXFLR);
765 ns = NSEC_PER_SEC / dws->current_freq * nents;
766 ns *= dws->n_bytes * BITS_PER_BYTE;
767 if (ns <= NSEC_PER_USEC) {
768 delay.unit = SPI_DELAY_UNIT_NSECS;
769 delay.value = ns;
770 } else {
771 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
772 delay.unit = SPI_DELAY_UNIT_USECS;
773 delay.value = clamp_val(us, 0, USHRT_MAX);
774 }
775
776 while (dw_spi_ctlr_busy(dws) && retry--)
777 spi_delay_exec(&delay, NULL);
778
779 if (retry < 0) {
780 dev_err(&dws->ctlr->dev, "Mem op hanged up\n");
781 return -EIO;
782 }
783
784 return 0;
785 }
786
dw_spi_stop_mem_op(struct dw_spi * dws,struct spi_device * spi)787 static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
788 {
789 dw_spi_enable_chip(dws, 0);
790 dw_spi_set_cs(spi, true);
791 dw_spi_enable_chip(dws, 1);
792 }
793
794 /*
795 * The SPI memory operation implementation below is the best choice for the
796 * devices, which are selected by the native chip-select lane. It's
797 * specifically developed to workaround the problem with automatic chip-select
798 * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current
799 * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
800 * unavailable.
801 */
dw_spi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)802 static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
803 {
804 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
805 struct dw_spi_cfg cfg = {0};
806 unsigned long flags;
807 int ret;
808
809 /*
810 * Collect the outbound data into a single buffer to speed the
811 * transmission up at least on the initial stage.
812 */
813 ret = dw_spi_init_mem_buf(dws, op);
814 if (ret)
815 return ret;
816
817 /*
818 * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN
819 * operation. Transmit-only mode is suitable for the rest of them.
820 */
821 cfg.dfs = 8;
822 cfg.freq = clamp(op->max_freq, 0U, dws->max_mem_freq);
823 if (op->data.dir == SPI_MEM_DATA_IN) {
824 cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
825 cfg.ndf = op->data.nbytes;
826 } else {
827 cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
828 }
829
830 dw_spi_enable_chip(dws, 0);
831
832 dw_spi_update_config(dws, mem->spi, &cfg, NULL);
833
834 dw_spi_mask_intr(dws, 0xff);
835
836 dw_spi_enable_chip(dws, 1);
837
838 /*
839 * DW APB SSI controller has very nasty peculiarities. First originally
840 * (without any vendor-specific modifications) it doesn't provide a
841 * direct way to set and clear the native chip-select signal. Instead
842 * the controller asserts the CS lane if Tx FIFO isn't empty and a
843 * transmission is going on, and automatically de-asserts it back to
844 * the high level if the Tx FIFO doesn't have anything to be pushed
845 * out. Due to that a multi-tasking or heavy IRQs activity might be
846 * fatal, since the transfer procedure preemption may cause the Tx FIFO
847 * getting empty and sudden CS de-assertion, which in the middle of the
848 * transfer will most likely cause the data loss. Secondly the
849 * EEPROM-read or Read-only DW SPI transfer modes imply the incoming
850 * data being automatically pulled in into the Rx FIFO. So if the
851 * driver software is late in fetching the data from the FIFO before
852 * it's overflown, new incoming data will be lost. In order to make
853 * sure the executed memory operations are CS-atomic and to prevent the
854 * Rx FIFO overflow we have to disable the local interrupts so to block
855 * any preemption during the subsequent IO operations.
856 *
857 * Note. At some circumstances disabling IRQs may not help to prevent
858 * the problems described above. The CS de-assertion and Rx FIFO
859 * overflow may still happen due to the relatively slow system bus or
860 * CPU not working fast enough, so the write-then-read algo implemented
861 * here just won't keep up with the SPI bus data transfer. Such
862 * situation is highly platform specific and is supposed to be fixed by
863 * manually restricting the SPI bus frequency using the
864 * dws->max_mem_freq parameter.
865 */
866 local_irq_save(flags);
867 preempt_disable();
868
869 ret = dw_spi_write_then_read(dws, mem->spi);
870
871 local_irq_restore(flags);
872 preempt_enable();
873
874 /*
875 * Wait for the operation being finished and check the controller
876 * status only if there hasn't been any run-time error detected. In the
877 * former case it's just pointless. In the later one to prevent an
878 * additional error message printing since any hw error flag being set
879 * would be due to an error detected on the data transfer.
880 */
881 if (!ret) {
882 ret = dw_spi_wait_mem_op_done(dws);
883 if (!ret)
884 ret = dw_spi_check_status(dws, true);
885 }
886
887 dw_spi_stop_mem_op(dws, mem->spi);
888
889 dw_spi_free_mem_buf(dws);
890
891 return ret;
892 }
893
dw_spi_init_enh_mem_buf(struct dw_spi * dws,const struct spi_mem_op * op)894 static void dw_spi_init_enh_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
895 {
896 dws->n_bytes = 1;
897 if (op->data.dir == SPI_MEM_DATA_IN) {
898 dws->rx = op->data.buf.in;
899 dws->rx_len = op->data.nbytes;
900 dws->tx = NULL;
901 dws->tx_len = 0;
902 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
903 dws->tx_len = op->data.nbytes;
904 dws->tx = (void *)op->data.buf.out;
905 dws->rx = NULL;
906 dws->rx_len = 0;
907 } else {
908 dws->rx = NULL;
909 dws->rx_len = 0;
910 dws->tx = NULL;
911 dws->tx_len = 0;
912 }
913 }
914
dw_spi_enh_write_cmd_addr(struct dw_spi * dws,const struct spi_mem_op * op,struct spi_mem * mem)915 static void dw_spi_enh_write_cmd_addr(struct dw_spi *dws, const struct spi_mem_op *op,
916 struct spi_mem *mem)
917 {
918 if (dws->quirk_flags & DW_SPI_QUIRK_JHB100) {
919 dw_write_io_reg(dws, DW_SPI_JHB100_INST, op->cmd.opcode);
920 if (op->addr.nbytes)
921 dw_write_io_reg(dws, DW_SPI_JHB100_ADDR, op->addr.val);
922
923 dw_spi_set_cs(mem->spi, false);
924 dw_spi_enable_chip(dws, 1);
925 } else {
926 dw_spi_enable_chip(dws, 1);
927
928 /* Send cmd as 32 bit value */
929 dw_write_io_reg(dws, DW_SPI_DR, op->cmd.opcode);
930 if (op->addr.nbytes) {
931 dw_write_io_reg(dws, DW_SPI_DR, lower_32_bits(op->addr.val));
932 if (op->addr.nbytes > 4) {
933 /* address more than 32bit */
934 dw_write_io_reg(dws, DW_SPI_DR, upper_32_bits(op->addr.val));
935 }
936 }
937
938 dw_spi_set_cs(mem->spi, false);
939 }
940 }
941
dw_spi_exec_enh_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)942 static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
943 {
944 struct spi_controller *ctlr = mem->spi->controller;
945 struct dw_spi *dws = spi_controller_get_devdata(ctlr);
946 struct dw_spi_enh_cfg enh_cfg = {0};
947 struct dw_spi_cfg cfg = {0};
948 unsigned long long ms;
949 int ret;
950
951 switch (op->data.buswidth) {
952 case 0:
953 case 1:
954 cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_STD_SPI;
955 break;
956 case 2:
957 cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI;
958 break;
959 case 4:
960 cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI;
961 break;
962 case 8:
963 cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_OCT_SPI;
964 break;
965 default:
966 return -EINVAL;
967 }
968
969 dw_spi_init_enh_mem_buf(dws, op);
970
971 cfg.dfs = 8;
972 cfg.freq = clamp(op->max_freq, 0U, dws->max_mem_freq);
973 cfg.ndf = op->data.nbytes;
974 if (op->data.dir == SPI_MEM_DATA_IN)
975 cfg.tmode = DW_SPI_CTRLR0_TMOD_RO;
976 else
977 cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
978
979 if (op->data.buswidth == op->addr.buswidth &&
980 op->data.buswidth == op->cmd.buswidth)
981 enh_cfg.trans_t = DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT2;
982 else if (op->data.buswidth == op->addr.buswidth)
983 enh_cfg.trans_t = DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT1;
984 else
985 enh_cfg.trans_t = DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT0;
986
987 enh_cfg.addr_l = op->addr.nbytes << 1;
988 if (op->cmd.nbytes == 2)
989 enh_cfg.inst_l = DW_SPI_ENH_CTRLR0_INST_L_INST_L16;
990 else if (op->cmd.nbytes == 1)
991 enh_cfg.inst_l = DW_SPI_ENH_CTRLR0_INST_L_INST_L8;
992 else
993 enh_cfg.inst_l = DW_SPI_ENH_CTRLR0_INST_L_INST_L0;
994
995 if (op->dummy.buswidth)
996 enh_cfg.wait_c = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
997
998 dw_spi_enable_chip(dws, 0);
999
1000 dw_spi_update_config(dws, mem->spi, &cfg, &enh_cfg);
1001
1002 dw_spi_mask_intr(dws, 0xff);
1003 reinit_completion(&ctlr->xfer_completion);
1004
1005 if (op->addr.nbytes && dws->set_addr_nbyte) {
1006 ret = dws->set_addr_nbyte(mem->spi, op->addr.nbytes);
1007 if (ret) {
1008 dw_spi_enable_chip(dws, 1);
1009 return ret;
1010 }
1011 }
1012
1013 dw_spi_enh_write_cmd_addr(dws, op, mem);
1014
1015 /*
1016 * FIXME: The exact reason for this delay is not fully understood,
1017 * but empirical testing shows it significantly improves the stability
1018 * of read/write operations. Without this delay, occasional transfer
1019 * errors or timeouts may occur under certain conditions.
1020 * Keeping it as a safeguard based on practical validation.
1021 */
1022 udelay(5);
1023
1024 dw_spi_enh_irq_setup(dws);
1025
1026 /* Use timeout calculation from spi_transfer_wait() */
1027 ms = 8LL * MSEC_PER_SEC * (dws->rx_len ? dws->rx_len : dws->tx_len);
1028 do_div(ms, dws->current_freq);
1029
1030 /*
1031 * Increase it twice and add 200 ms tolerance, use
1032 * predefined maximum in case of overflow.
1033 */
1034 ms += ms + 200;
1035 if (ms > UINT_MAX)
1036 ms = UINT_MAX;
1037
1038 ms = wait_for_completion_timeout(&ctlr->xfer_completion,
1039 msecs_to_jiffies(ms));
1040 if (ms == 0) {
1041 dw_spi_mask_intr(dws, 0xff);
1042 synchronize_irq(dws->irq);
1043 dws->rx = NULL;
1044 dws->tx = NULL;
1045 dws->rx_len = 0;
1046 dws->tx_len = 0;
1047 dw_spi_stop_mem_op(dws, mem->spi);
1048 return -EIO;
1049 }
1050
1051 ret = dw_spi_wait_mem_op_done(dws);
1052
1053 dw_spi_stop_mem_op(dws, mem->spi);
1054
1055 return ret;
1056 }
1057
dw_spi_can_use_mem_ops(struct dw_spi * dws)1058 static bool dw_spi_can_use_mem_ops(struct dw_spi *dws)
1059 {
1060 return !dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) &&
1061 !dws->set_cs;
1062 }
1063
1064 /*
1065 * Initialize the default memory operations if a glue layer hasn't specified
1066 * custom ones. Direct mapping operations will be preserved anyway since DW SPI
1067 * controller doesn't have an embedded dirmap interface. Note the memory
1068 * operations implemented in this driver is the best choice only for the DW APB
1069 * SSI controller with standard native CS functionality. If a hardware vendor
1070 * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
1071 * be safer to use the normal SPI-messages-based transfers implementation.
1072 */
dw_spi_init_mem_ops(struct dw_spi * dws)1073 static void dw_spi_init_mem_ops(struct dw_spi *dws)
1074 {
1075 if (dw_spi_can_use_mem_ops(dws)) {
1076 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
1077 if (dws->caps & DW_SPI_CAP_EMODE) {
1078 dws->mem_ops.exec_op = dw_spi_exec_enh_mem_op;
1079 dws->mem_ops.supports_op = dw_spi_supports_enh_mem_op;
1080 dws->mem_ops.adjust_op_size = dw_spi_adjust_enh_mem_op_size;
1081 } else {
1082 dws->mem_ops.exec_op = dw_spi_exec_mem_op;
1083 dws->mem_ops.supports_op = dw_spi_supports_mem_op;
1084 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
1085 }
1086
1087 if (!dws->max_mem_freq)
1088 dws->max_mem_freq = dws->max_freq;
1089 }
1090 }
1091
1092 /* This may be called twice for each spi dev */
dw_spi_setup(struct spi_device * spi)1093 static int dw_spi_setup(struct spi_device *spi)
1094 {
1095 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
1096 struct dw_spi_chip_data *chip;
1097
1098 /* Only alloc on first setup */
1099 chip = spi_get_ctldata(spi);
1100 if (!chip) {
1101 u32 rx_sample_dly_ns;
1102
1103 chip = kzalloc_obj(*chip);
1104 if (!chip)
1105 return -ENOMEM;
1106 spi_set_ctldata(spi, chip);
1107 /* Get specific / default rx-sample-delay */
1108 if (device_property_read_u32(&spi->dev,
1109 "rx-sample-delay-ns",
1110 &rx_sample_dly_ns) != 0)
1111 /* Use default controller value */
1112 rx_sample_dly_ns = dws->def_rx_sample_dly_ns;
1113 chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns,
1114 NSEC_PER_SEC /
1115 dws->max_freq);
1116 }
1117
1118 /*
1119 * Update CR0 data each time the setup callback is invoked since
1120 * the device parameters could have been changed, for instance, by
1121 * the MMC SPI driver or something else.
1122 */
1123 chip->cr0 = dw_spi_prepare_cr0(dws, spi);
1124
1125 return 0;
1126 }
1127
dw_spi_cleanup(struct spi_device * spi)1128 static void dw_spi_cleanup(struct spi_device *spi)
1129 {
1130 struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
1131
1132 kfree(chip);
1133 spi_set_ctldata(spi, NULL);
1134 }
1135
detect_enh_mode(struct dw_spi * dws)1136 static u16 detect_enh_mode(struct dw_spi *dws)
1137 {
1138 u32 tmp_spi_ctrlr0, tmp_ctrlr0;
1139 u32 tmp_val, frf_shift;
1140 u16 mode = 0;
1141
1142 if (dw_spi_ver_is_ge(dws, HSSI, 103A))
1143 frf_shift = __bf_shf(DW_HSSI_CTRLR0_SPI_FRF_MASK);
1144 else if (dw_spi_ver_is_ge(dws, PSSI, 400A))
1145 frf_shift = __bf_shf(DW_PSSI_CTRLR0_SPI_FRF_MASK);
1146 else
1147 return 0;
1148
1149 tmp_ctrlr0 = dw_readl(dws, DW_SPI_CTRLR0);
1150 tmp_spi_ctrlr0 = dw_readl(dws, DW_SPI_SPI_CTRLR0);
1151 dw_spi_enable_chip(dws, 0);
1152
1153 /* test dual mode */
1154 tmp_val = DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI << frf_shift;
1155 dw_writel(dws, DW_SPI_CTRLR0, tmp_val);
1156 if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) == tmp_val)
1157 mode |= SPI_TX_DUAL | SPI_RX_DUAL;
1158
1159 /* test quad mode */
1160 tmp_val = DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI << frf_shift;
1161 dw_writel(dws, DW_SPI_CTRLR0, tmp_val);
1162 if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) == tmp_val)
1163 mode |= SPI_TX_QUAD | SPI_RX_QUAD;
1164
1165 /* test octal mode */
1166 tmp_val = DW_SPI_CTRLR0_SPI_FRF_OCT_SPI << frf_shift;
1167 dw_writel(dws, DW_SPI_CTRLR0, tmp_val);
1168 if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) == tmp_val)
1169 mode |= SPI_TX_OCTAL | SPI_RX_OCTAL;
1170
1171 if (!mode)
1172 goto disable_enh;
1173
1174 /* test clock stretching */
1175 dw_writel(dws, DW_SPI_SPI_CTRLR0, DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN);
1176 if ((DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN & dw_readl(dws, DW_SPI_SPI_CTRLR0)) !=
1177 DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN) {
1178 /*
1179 * If clock stretching is not enabled then do not use
1180 * enhanced mode.
1181 */
1182 mode = 0;
1183 goto disable_enh;
1184 }
1185
1186 dws->caps |= DW_SPI_CAP_EMODE;
1187
1188 disable_enh:
1189 dw_writel(dws, DW_SPI_CTRLR0, tmp_ctrlr0);
1190 dw_writel(dws, DW_SPI_SPI_CTRLR0, tmp_spi_ctrlr0);
1191 dw_spi_enable_chip(dws, 1);
1192
1193 return mode;
1194 }
1195
1196 /* Restart the controller, disable all interrupts, clean rx fifo */
dw_spi_hw_init(struct device * dev,struct dw_spi * dws)1197 static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
1198 {
1199 dw_spi_reset_chip(dws);
1200
1201 /*
1202 * Retrieve the Synopsys component version if it hasn't been specified
1203 * by the platform. CoreKit version ID is encoded as a 3-chars ASCII
1204 * code enclosed with '*' (typical for the most of Synopsys IP-cores).
1205 */
1206 if (!dws->ver) {
1207 dws->ver = dw_readl(dws, DW_SPI_VERSION);
1208
1209 dev_dbg(dev, "Synopsys DWC%sSSI v%c.%c%c\n",
1210 dw_spi_ip_is(dws, PSSI) ? " APB " : " ",
1211 DW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2),
1212 DW_SPI_GET_BYTE(dws->ver, 1));
1213 }
1214
1215 if (spi_controller_is_target(dws->ctlr)) {
1216 /* There is only one CS input signal in target mode */
1217 dws->num_cs = 1;
1218 } else {
1219 /*
1220 * Try to detect the number of native chip-selects if the platform
1221 * driver didn't set it up. There can be up to 16 lines configured.
1222 */
1223 if (!dws->num_cs) {
1224 u32 ser;
1225
1226 dw_writel(dws, DW_SPI_SER, 0xffff);
1227 ser = dw_readl(dws, DW_SPI_SER);
1228 dw_writel(dws, DW_SPI_SER, 0);
1229
1230 dws->num_cs = hweight16(ser);
1231 }
1232 }
1233
1234 /*
1235 * Try to detect the FIFO depth if not set by interface driver,
1236 * the depth could be from 2 to 256 from HW spec
1237 */
1238 if (!dws->fifo_len) {
1239 u32 fifo;
1240
1241 for (fifo = 1; fifo < 256; fifo++) {
1242 dw_writel(dws, DW_SPI_TXFTLR, fifo);
1243 if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
1244 break;
1245 }
1246 dw_writel(dws, DW_SPI_TXFTLR, 0);
1247
1248 dws->fifo_len = (fifo == 1) ? 0 : fifo;
1249 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
1250 }
1251
1252 /*
1253 * Detect CTRLR0.DFS field size and offset by testing the lowest bits
1254 * writability. Note DWC SSI controller also has the extended DFS, but
1255 * with zero offset.
1256 */
1257 if (dw_spi_ip_is(dws, PSSI)) {
1258 u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);
1259
1260 dw_spi_enable_chip(dws, 0);
1261 dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
1262 cr0 = dw_readl(dws, DW_SPI_CTRLR0);
1263 dw_writel(dws, DW_SPI_CTRLR0, tmp);
1264 dw_spi_enable_chip(dws, 1);
1265
1266 if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) {
1267 dws->caps |= DW_SPI_CAP_DFS32;
1268 dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);
1269 dev_dbg(dev, "Detected 32-bits max data frame size\n");
1270 }
1271 } else {
1272 dws->caps |= DW_SPI_CAP_DFS32;
1273 }
1274
1275 dws->ctlr->mode_bits |= SPI_CPOL | SPI_CPHA;
1276
1277 if (!spi_controller_is_target(dws->ctlr) && dw_spi_can_use_mem_ops(dws))
1278 dws->ctlr->mode_bits |= detect_enh_mode(dws);
1279
1280 /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
1281 if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
1282 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
1283 }
1284
1285 static const struct spi_controller_mem_caps dw_spi_mem_caps = {
1286 .per_op_freq = true,
1287 };
1288
dw_spi_add_controller(struct device * dev,struct dw_spi * dws)1289 int dw_spi_add_controller(struct device *dev, struct dw_spi *dws)
1290 {
1291 struct spi_controller *ctlr;
1292 bool target;
1293 int ret;
1294
1295 if (!dws)
1296 return -EINVAL;
1297
1298 target = device_property_read_bool(dev, "spi-slave");
1299 if (target)
1300 ctlr = spi_alloc_target(dev, 0);
1301 else
1302 ctlr = spi_alloc_host(dev, 0);
1303
1304 if (!ctlr)
1305 return -ENOMEM;
1306
1307 dws->ctlr = ctlr;
1308 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
1309
1310 spi_controller_set_devdata(ctlr, dws);
1311
1312 /* Basic HW init */
1313 dw_spi_hw_init(dev, dws);
1314
1315 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
1316 ctlr);
1317 if (ret < 0 && ret != -ENOTCONN) {
1318 dev_err(dev, "can not request IRQ\n");
1319 goto err_free_ctlr;
1320 }
1321
1322 dw_spi_init_mem_ops(dws);
1323
1324 if (dws->caps & DW_SPI_CAP_DFS32)
1325 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1326 else
1327 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1328 ctlr->bus_num = dws->bus_num;
1329 ctlr->num_chipselect = dws->num_cs;
1330 ctlr->setup = dw_spi_setup;
1331 ctlr->cleanup = dw_spi_cleanup;
1332 ctlr->transfer_one = dw_spi_transfer_one;
1333 ctlr->handle_err = dw_spi_handle_err;
1334 ctlr->auto_runtime_pm = true;
1335
1336 if (!target) {
1337 ctlr->use_gpio_descriptors = true;
1338 ctlr->mode_bits |= SPI_LOOP;
1339 if (dws->set_cs)
1340 ctlr->set_cs = dws->set_cs;
1341 else
1342 ctlr->set_cs = dw_spi_set_cs;
1343 if (dws->mem_ops.exec_op) {
1344 ctlr->mem_ops = &dws->mem_ops;
1345 ctlr->mem_caps = &dw_spi_mem_caps;
1346 }
1347 ctlr->max_speed_hz = dws->max_freq;
1348 ctlr->flags = SPI_CONTROLLER_GPIO_SS;
1349 } else {
1350 ctlr->target_abort = dw_spi_target_abort;
1351 }
1352
1353 /* Get default rx sample delay */
1354 device_property_read_u32(dev, "rx-sample-delay-ns",
1355 &dws->def_rx_sample_dly_ns);
1356
1357 if (dws->dma_ops && dws->dma_ops->dma_init) {
1358 ret = dws->dma_ops->dma_init(dev, dws);
1359 if (ret == -EPROBE_DEFER) {
1360 goto err_free_irq;
1361 } else if (ret) {
1362 dev_warn(dev, "DMA init failed\n");
1363 } else {
1364 ctlr->can_dma = dws->dma_ops->can_dma;
1365 ctlr->flags |= SPI_CONTROLLER_MUST_TX;
1366 }
1367 }
1368
1369 ret = spi_register_controller(ctlr);
1370 if (ret) {
1371 dev_err_probe(dev, ret, "problem registering spi controller\n");
1372 goto err_dma_exit;
1373 }
1374
1375 dw_spi_debugfs_init(dws);
1376 return 0;
1377
1378 err_dma_exit:
1379 if (dws->dma_ops && dws->dma_ops->dma_exit)
1380 dws->dma_ops->dma_exit(dws);
1381 dw_spi_enable_chip(dws, 0);
1382 err_free_irq:
1383 free_irq(dws->irq, ctlr);
1384 err_free_ctlr:
1385 spi_controller_put(ctlr);
1386 return ret;
1387 }
1388 EXPORT_SYMBOL_NS_GPL(dw_spi_add_controller, "SPI_DW_CORE");
1389
dw_spi_remove_controller(struct dw_spi * dws)1390 void dw_spi_remove_controller(struct dw_spi *dws)
1391 {
1392 dw_spi_debugfs_remove(dws);
1393
1394 spi_unregister_controller(dws->ctlr);
1395
1396 if (dws->dma_ops && dws->dma_ops->dma_exit)
1397 dws->dma_ops->dma_exit(dws);
1398
1399 dw_spi_shutdown_chip(dws);
1400
1401 free_irq(dws->irq, dws->ctlr);
1402
1403 spi_controller_put(dws->ctlr);
1404 }
1405 EXPORT_SYMBOL_NS_GPL(dw_spi_remove_controller, "SPI_DW_CORE");
1406
dw_spi_suspend_controller(struct dw_spi * dws)1407 int dw_spi_suspend_controller(struct dw_spi *dws)
1408 {
1409 int ret;
1410
1411 ret = spi_controller_suspend(dws->ctlr);
1412 if (ret)
1413 return ret;
1414
1415 dw_spi_shutdown_chip(dws);
1416 return 0;
1417 }
1418 EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_controller, "SPI_DW_CORE");
1419
dw_spi_resume_controller(struct dw_spi * dws)1420 int dw_spi_resume_controller(struct dw_spi *dws)
1421 {
1422 dw_spi_hw_init(&dws->ctlr->dev, dws);
1423 return spi_controller_resume(dws->ctlr);
1424 }
1425 EXPORT_SYMBOL_NS_GPL(dw_spi_resume_controller, "SPI_DW_CORE");
1426
1427 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1428 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1429 MODULE_LICENSE("GPL v2");
1430