1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99 #define SMU_13_0_6_DSCLK_THRESHOLD 140
100
101 #define MCA_BANK_IPID(_ip, _hwid, _type) \
102 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
103
104 struct mca_bank_ipid {
105 enum amdgpu_mca_ip ip;
106 uint16_t hwid;
107 uint16_t mcatype;
108 };
109
110 struct mca_ras_info {
111 enum amdgpu_ras_block blkid;
112 enum amdgpu_mca_ip ip;
113 int *err_code_array;
114 int err_code_count;
115 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
116 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
117 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
118 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
119 };
120
121 #define P2S_TABLE_ID_A 0x50325341
122 #define P2S_TABLE_ID_X 0x50325358
123 #define P2S_TABLE_ID_3 0x50325303
124
125 // clang-format off
126 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
127 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
128 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
129 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
130 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
131 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
132 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
133 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
134 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
135 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
136 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
137 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
138 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
139 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
140 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
144 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
145 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
146 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
148 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),
149 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
150 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
151 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
152 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
153 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
154 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
155 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
156 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
157 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
158 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
159 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
160 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
161 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
162 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
163 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
164 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
165 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
166 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
167 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
168 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
169 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
170 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
171 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
172 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
176 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
177 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
178 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
179 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
180 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1),
181 };
182
183 // clang-format on
184 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
185 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
186 CLK_MAP(FCLK, PPCLK_FCLK),
187 CLK_MAP(UCLK, PPCLK_UCLK),
188 CLK_MAP(MCLK, PPCLK_UCLK),
189 CLK_MAP(DCLK, PPCLK_DCLK),
190 CLK_MAP(VCLK, PPCLK_VCLK),
191 CLK_MAP(LCLK, PPCLK_LCLK),
192 };
193
194 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
195 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
222 };
223
224 #define TABLE_PMSTATUSLOG 0
225 #define TABLE_SMU_METRICS 1
226 #define TABLE_I2C_COMMANDS 2
227 #define TABLE_COUNT 3
228
229 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
230 TAB_MAP(PMSTATUSLOG),
231 TAB_MAP(SMU_METRICS),
232 TAB_MAP(I2C_COMMANDS),
233 };
234
235 static const uint8_t smu_v13_0_6_throttler_map[] = {
236 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
237 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
238 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
239 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
240 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
241 };
242
243 #define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
244 (metrics_v0->field) : (metrics_v2->field))
245 #define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
246 (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
247 #define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
248 sizeof(MetricsTableV1_t),\
249 sizeof(MetricsTableV2_t)))
250
251 struct smu_v13_0_6_dpm_map {
252 enum smu_clk_type clk_type;
253 uint32_t feature_num;
254 struct smu_13_0_dpm_table *dpm_table;
255 uint32_t *freq_table;
256 };
257
smu_v13_0_6_get_metrics_version(struct smu_context * smu)258 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
259 {
260 if ((smu->adev->flags & AMD_IS_APU) &&
261 smu->smc_fw_version <= 0x4556900)
262 return METRICS_VERSION_V1;
263 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
264 IP_VERSION(13, 0, 12))
265 return METRICS_VERSION_V2;
266
267 return METRICS_VERSION_V0;
268 }
269
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)270 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
271 enum smu_v13_0_6_caps cap)
272 {
273 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
274
275 dpm_context->caps |= BIT_ULL(cap);
276 }
277
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)278 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
279 enum smu_v13_0_6_caps cap)
280 {
281 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
282
283 dpm_context->caps &= ~BIT_ULL(cap);
284 }
285
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)286 bool smu_v13_0_6_cap_supported(struct smu_context *smu,
287 enum smu_v13_0_6_caps cap)
288 {
289 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
290
291 return !!(dpm_context->caps & BIT_ULL(cap));
292 }
293
smu_v13_0_14_init_caps(struct smu_context * smu)294 static void smu_v13_0_14_init_caps(struct smu_context *smu)
295 {
296 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
297 SMU_CAP(SET_UCLK_MAX),
298 SMU_CAP(DPM_POLICY),
299 SMU_CAP(PCIE_METRICS),
300 SMU_CAP(CTF_LIMIT),
301 SMU_CAP(MCA_DEBUG_MODE),
302 SMU_CAP(RMA_MSG),
303 SMU_CAP(ACA_SYND) };
304 uint32_t fw_ver = smu->smc_fw_version;
305
306 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
307 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
308
309 if (fw_ver >= 0x05550E00)
310 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
311 if (fw_ver >= 0x05550B00)
312 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
313 if (fw_ver >= 0x5551200)
314 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
315 if (fw_ver >= 0x5551800)
316 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
317 if (fw_ver >= 0x5551600) {
318 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
319 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
320 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
321 }
322 }
323
smu_v13_0_12_init_caps(struct smu_context * smu)324 static void smu_v13_0_12_init_caps(struct smu_context *smu)
325 {
326 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
327 SMU_CAP(PCIE_METRICS),
328 SMU_CAP(CTF_LIMIT),
329 SMU_CAP(MCA_DEBUG_MODE),
330 SMU_CAP(RMA_MSG),
331 SMU_CAP(ACA_SYND),
332 SMU_CAP(OTHER_END_METRICS),
333 SMU_CAP(PER_INST_METRICS) };
334 uint32_t fw_ver = smu->smc_fw_version;
335
336 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
337 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
338
339 if (fw_ver < 0x00561900)
340 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
341
342 if (fw_ver >= 0x00561700)
343 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
344
345 if (fw_ver >= 0x00561E00)
346 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
347
348 if (fw_ver >= 0x00562500)
349 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
350
351 if (fw_ver >= 0x04560100) {
352 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
353 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
354 }
355
356 if (fw_ver > 0x04560900)
357 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
358
359 if (fw_ver >= 0x04560700) {
360 if (fw_ver >= 0x04560900) {
361 smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
362 if (smu->adev->gmc.xgmi.physical_node_id == 0)
363 smu_v13_0_6_cap_set(smu, SMU_CAP(NPM_METRICS));
364 } else if (!amdgpu_sriov_vf(smu->adev))
365 smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
366 } else {
367 smu_v13_0_12_tables_fini(smu);
368 }
369 }
370
smu_v13_0_6_init_caps(struct smu_context * smu)371 static void smu_v13_0_6_init_caps(struct smu_context *smu)
372 {
373 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
374 SMU_CAP(SET_UCLK_MAX),
375 SMU_CAP(DPM_POLICY),
376 SMU_CAP(PCIE_METRICS),
377 SMU_CAP(CTF_LIMIT),
378 SMU_CAP(MCA_DEBUG_MODE),
379 SMU_CAP(RMA_MSG),
380 SMU_CAP(ACA_SYND) };
381 struct amdgpu_device *adev = smu->adev;
382 uint32_t fw_ver = smu->smc_fw_version;
383 uint32_t pgm = (fw_ver >> 24) & 0xFF;
384
385 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
386 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
387
388 if (fw_ver < 0x552F00)
389 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
390 if (fw_ver < 0x554500)
391 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
392
393 if (adev->flags & AMD_IS_APU) {
394 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
395 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
396 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
397 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
398
399 if (fw_ver >= 0x04556A00)
400 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
401 } else {
402 if (fw_ver >= 0x557600)
403 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
404 if (fw_ver < 0x00556000)
405 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
406 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
407 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
408 if (fw_ver < 0x556300)
409 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
410 if (fw_ver < 0x554800)
411 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
412 if (fw_ver >= 0x556F00)
413 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
414 if (fw_ver < 0x00555a00)
415 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
416 if (fw_ver < 0x00555600)
417 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
418 if ((pgm == 7 && fw_ver >= 0x7550E00) ||
419 (pgm == 0 && fw_ver >= 0x00557E00))
420 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
421
422 if (amdgpu_sriov_vf(adev)) {
423 if (fw_ver >= 0x00558200)
424 amdgpu_virt_attr_set(&adev->virt.virt_caps,
425 AMDGPU_VIRT_CAP_POWER_LIMIT,
426 AMDGPU_CAP_ATTR_RW);
427 if ((pgm == 0 && fw_ver >= 0x00558000) ||
428 (pgm == 7 && fw_ver >= 0x7551000)) {
429 smu_v13_0_6_cap_set(smu,
430 SMU_CAP(STATIC_METRICS));
431 smu_v13_0_6_cap_set(smu,
432 SMU_CAP(BOARD_VOLTAGE));
433 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
434 }
435 } else {
436 if ((pgm == 0 && fw_ver >= 0x00557F01) ||
437 (pgm == 7 && fw_ver >= 0x7551000)) {
438 smu_v13_0_6_cap_set(smu,
439 SMU_CAP(STATIC_METRICS));
440 smu_v13_0_6_cap_set(smu,
441 SMU_CAP(BOARD_VOLTAGE));
442 }
443 if ((pgm == 0 && fw_ver >= 0x00558000) ||
444 (pgm == 7 && fw_ver >= 0x7551000))
445 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
446 }
447 }
448 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
449 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
450 ((pgm == 4) && (fw_ver >= 0x4557000)))
451 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
452
453 if ((pgm == 0) && (fw_ver >= 0x00558200))
454 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
455 }
456
smu_v13_0_x_init_caps(struct smu_context * smu)457 static void smu_v13_0_x_init_caps(struct smu_context *smu)
458 {
459 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
460 case IP_VERSION(13, 0, 12):
461 return smu_v13_0_12_init_caps(smu);
462 case IP_VERSION(13, 0, 14):
463 return smu_v13_0_14_init_caps(smu);
464 default:
465 return smu_v13_0_6_init_caps(smu);
466 }
467 }
468
smu_v13_0_6_check_fw_version(struct smu_context * smu)469 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
470 {
471 int r;
472
473 r = smu_v13_0_check_fw_version(smu);
474 /* Initialize caps flags once fw version is fetched */
475 if (!r)
476 smu_v13_0_x_init_caps(smu);
477
478 return r;
479 }
480
smu_v13_0_6_init_microcode(struct smu_context * smu)481 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
482 {
483 const struct smc_firmware_header_v2_1 *v2_1;
484 const struct common_firmware_header *hdr;
485 struct amdgpu_firmware_info *ucode = NULL;
486 struct smc_soft_pptable_entry *entries;
487 struct amdgpu_device *adev = smu->adev;
488 uint32_t p2s_table_id = P2S_TABLE_ID_A;
489 int ret = 0, i, p2stable_count;
490 int var = (adev->pdev->device & 0xF);
491 char ucode_prefix[15];
492
493 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
494 if (amdgpu_sriov_vf(adev) ||
495 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
496 return 0;
497
498 if (!(adev->flags & AMD_IS_APU)) {
499 p2s_table_id = P2S_TABLE_ID_X;
500 if (var == 0x5)
501 p2s_table_id = P2S_TABLE_ID_3;
502 }
503
504 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
505 sizeof(ucode_prefix));
506 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
507 "amdgpu/%s.bin", ucode_prefix);
508 if (ret)
509 goto out;
510
511 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
512 amdgpu_ucode_print_smc_hdr(hdr);
513
514 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
515 * are used to carry p2s tables.
516 */
517 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
518 entries = (struct smc_soft_pptable_entry
519 *)((uint8_t *)v2_1 +
520 le32_to_cpu(v2_1->pptable_entry_offset));
521 p2stable_count = le32_to_cpu(v2_1->pptable_count);
522 for (i = 0; i < p2stable_count; i++) {
523 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
524 smu->pptable_firmware.data =
525 ((uint8_t *)v2_1 +
526 le32_to_cpu(entries[i].ppt_offset_bytes));
527 smu->pptable_firmware.size =
528 le32_to_cpu(entries[i].ppt_size_bytes);
529 break;
530 }
531 }
532
533 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
534 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
535 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
536 ucode->fw = &smu->pptable_firmware;
537 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
538 }
539
540 return 0;
541 out:
542 amdgpu_ucode_release(&adev->pm.fw);
543
544 return ret;
545 }
546
smu_v13_0_6_tables_init(struct smu_context * smu)547 static int smu_v13_0_6_tables_init(struct smu_context *smu)
548 {
549 struct smu_table_context *smu_table = &smu->smu_table;
550 struct smu_table *tables = smu_table->tables;
551 void *gpu_metrics_table __free(kfree) = NULL;
552 void *driver_pptable __free(kfree) = NULL;
553 void *metrics_table __free(kfree) = NULL;
554 struct amdgpu_device *adev = smu->adev;
555 int gpu_metrcs_size = METRICS_TABLE_SIZE;
556 int ret;
557
558 if (!(adev->flags & AMD_IS_APU))
559 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
560 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
561
562 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
563 max(gpu_metrcs_size,
564 smu_v13_0_12_get_max_metrics_size()),
565 PAGE_SIZE,
566 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
567
568 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
569 PAGE_SIZE,
570 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
571
572 SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS,
573 smu_v13_0_12_get_system_metrics_size(), PAGE_SIZE,
574 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
575
576 metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
577 if (!metrics_table)
578 return -ENOMEM;
579 smu_table->metrics_time = 0;
580
581 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8);
582 gpu_metrics_table =
583 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
584 if (!gpu_metrics_table)
585 return -ENOMEM;
586
587 driver_pptable = kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
588 if (!driver_pptable)
589 return -ENOMEM;
590
591 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
592 IP_VERSION(13, 0, 12)) {
593 ret = smu_v13_0_12_tables_init(smu);
594 if (ret)
595 return ret;
596 }
597
598 smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table);
599 smu_table->metrics_table = no_free_ptr(metrics_table);
600 smu_table->driver_pptable = no_free_ptr(driver_pptable);
601
602 return 0;
603 }
604
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)605 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
606 int policy)
607 {
608 struct amdgpu_device *adev = smu->adev;
609 int ret, param;
610
611 switch (policy) {
612 case SOC_PSTATE_DEFAULT:
613 param = 0;
614 break;
615 case SOC_PSTATE_0:
616 param = 1;
617 break;
618 case SOC_PSTATE_1:
619 param = 2;
620 break;
621 case SOC_PSTATE_2:
622 param = 3;
623 break;
624 default:
625 return -EINVAL;
626 }
627
628 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetThrottlingPolicy,
629 param, NULL);
630
631 if (ret)
632 dev_err(adev->dev, "select soc pstate policy %d failed",
633 policy);
634
635 return ret;
636 }
637
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)638 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
639 {
640 struct amdgpu_device *adev = smu->adev;
641 int ret, param;
642
643 switch (level) {
644 case XGMI_PLPD_DEFAULT:
645 param = PPSMC_PLPD_MODE_DEFAULT;
646 break;
647 case XGMI_PLPD_OPTIMIZED:
648 param = PPSMC_PLPD_MODE_OPTIMIZED;
649 break;
650 case XGMI_PLPD_DISALLOW:
651 param = 0;
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 if (level == XGMI_PLPD_DISALLOW)
658 ret = smu_cmn_send_smc_msg_with_param(
659 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
660 else
661 /* change xgmi per-link power down policy */
662 ret = smu_cmn_send_smc_msg_with_param(
663 smu, SMU_MSG_SelectPLPDMode, param, NULL);
664
665 if (ret)
666 dev_err(adev->dev,
667 "select xgmi per-link power down policy %d failed\n",
668 level);
669
670 return ret;
671 }
672
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)673 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
674 {
675 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
676 struct smu_dpm_policy *policy;
677
678 smu_dpm->dpm_context =
679 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
680 if (!smu_dpm->dpm_context)
681 return -ENOMEM;
682 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
683
684 smu_dpm->dpm_policies =
685 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
686 if (!smu_dpm->dpm_policies) {
687 kfree(smu_dpm->dpm_context);
688 return -ENOMEM;
689 }
690
691 if (!(smu->adev->flags & AMD_IS_APU)) {
692 policy = &(smu_dpm->dpm_policies->policies[0]);
693
694 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
695 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
696 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
697 BIT(SOC_PSTATE_2);
698 policy->current_level = SOC_PSTATE_DEFAULT;
699 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
700 smu_cmn_generic_soc_policy_desc(policy);
701 smu_dpm->dpm_policies->policy_mask |=
702 BIT(PP_PM_POLICY_SOC_PSTATE);
703 }
704 policy = &(smu_dpm->dpm_policies->policies[1]);
705
706 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
707 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
708 BIT(XGMI_PLPD_OPTIMIZED);
709 policy->current_level = XGMI_PLPD_DEFAULT;
710 policy->set_policy = smu_v13_0_6_select_plpd_policy;
711 smu_cmn_generic_plpd_policy_desc(policy);
712 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
713
714 return 0;
715 }
716
smu_v13_0_6_init_smc_tables(struct smu_context * smu)717 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
718 {
719 int ret = 0;
720
721 ret = smu_v13_0_6_tables_init(smu);
722 if (ret)
723 return ret;
724
725 ret = smu_v13_0_6_allocate_dpm_context(smu);
726
727 return ret;
728 }
729
smu_v13_0_6_fini_smc_tables(struct smu_context * smu)730 static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu)
731 {
732 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
733 smu_v13_0_12_tables_fini(smu);
734 return smu_v13_0_fini_smc_tables(smu);
735 }
736
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)737 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
738 uint32_t *feature_mask,
739 uint32_t num)
740 {
741 if (num > 2)
742 return -EINVAL;
743
744 /* pptable will handle the features to enable */
745 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
746
747 return 0;
748 }
749
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)750 int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table,
751 bool bypass_cache)
752 {
753 struct smu_table_context *smu_table = &smu->smu_table;
754 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
755 struct smu_table *table = &smu_table->driver_table;
756 int ret;
757
758 if (bypass_cache || !smu_table->metrics_time ||
759 time_after(jiffies,
760 smu_table->metrics_time + msecs_to_jiffies(1))) {
761 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
762 if (ret) {
763 dev_info(smu->adev->dev,
764 "Failed to export SMU metrics table!\n");
765 return ret;
766 }
767
768 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
769 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
770
771 smu_table->metrics_time = jiffies;
772 }
773
774 if (metrics_table)
775 memcpy(metrics_table, smu_table->metrics_table, table_size);
776
777 return 0;
778 }
779
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)780 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
781 void *metrics, size_t max_size)
782 {
783 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
784 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
785 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
786 struct amdgpu_pm_metrics *pm_metrics = metrics;
787 uint32_t pmfw_version;
788 int ret;
789
790 if (!pm_metrics || !max_size)
791 return -EINVAL;
792
793 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
794 return -EOVERFLOW;
795
796 /* Don't use cached metrics data */
797 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
798 if (ret)
799 return ret;
800
801 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
802
803 memset(&pm_metrics->common_header, 0,
804 sizeof(pm_metrics->common_header));
805 pm_metrics->common_header.mp1_ip_discovery_version =
806 amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
807 pm_metrics->common_header.pmfw_version = pmfw_version;
808 pm_metrics->common_header.pmmetrics_version = table_version;
809 pm_metrics->common_header.structure_size =
810 sizeof(pm_metrics->common_header) + table_size;
811
812 return pm_metrics->common_header.structure_size;
813 }
814
smu_v13_0_6_fill_static_metrics_table(struct smu_context * smu,StaticMetricsTable_t * static_metrics)815 static void smu_v13_0_6_fill_static_metrics_table(struct smu_context *smu,
816 StaticMetricsTable_t *static_metrics)
817 {
818 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
819
820 if (!static_metrics->InputTelemetryVoltageInmV) {
821 dev_warn(smu->adev->dev, "Invalid board voltage %d\n",
822 static_metrics->InputTelemetryVoltageInmV);
823 }
824
825 dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV;
826
827 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
828 static_metrics->pldmVersion[0] != 0xFFFFFFFF)
829 smu->adev->firmware.pldm_version =
830 static_metrics->pldmVersion[0];
831 }
832
smu_v13_0_6_get_static_metrics_table(struct smu_context * smu)833 int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
834 {
835 struct smu_table_context *smu_table = &smu->smu_table;
836 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
837 struct smu_table *table = &smu_table->driver_table;
838 int ret;
839
840 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL);
841 if (ret) {
842 dev_info(smu->adev->dev,
843 "Failed to export static metrics table!\n");
844 return ret;
845 }
846
847 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
848 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
849
850 return 0;
851 }
852
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)853 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
854 {
855 struct smu_table_context *smu_table = &smu->smu_table;
856 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table;
857 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
858 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
859 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
860 struct PPTable_t *pptable =
861 (struct PPTable_t *)smu_table->driver_pptable;
862 int version = smu_v13_0_6_get_metrics_version(smu);
863 int ret, i, retry = 100, n;
864 uint32_t table_version;
865 uint16_t max_speed;
866 uint8_t max_width;
867
868 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
869 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
870 return smu_v13_0_12_setup_driver_pptable(smu);
871
872 /* Store one-time values in driver PPTable */
873 if (!pptable->Init) {
874 while (--retry) {
875 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
876 if (ret)
877 return ret;
878
879 /* Ensure that metrics have been updated */
880 if (GET_METRIC_FIELD(AccumulationCounter, version))
881 break;
882
883 usleep_range(1000, 1100);
884 }
885
886 if (!retry)
887 return -ETIME;
888
889 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
890 &table_version);
891 if (ret)
892 return ret;
893 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
894 table_version;
895
896 pptable->MaxSocketPowerLimit =
897 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
898 pptable->MaxGfxclkFrequency =
899 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
900 pptable->MinGfxclkFrequency =
901 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
902 max_width = (uint8_t)GET_METRIC_FIELD(XgmiWidth, version);
903 max_speed = (uint16_t)GET_METRIC_FIELD(XgmiBitrate, version);
904 amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width);
905
906 for (i = 0; i < 4; ++i) {
907 pptable->FclkFrequencyTable[i] =
908 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
909 pptable->UclkFrequencyTable[i] =
910 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
911 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
912 GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
913 pptable->VclkFrequencyTable[i] =
914 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
915 pptable->DclkFrequencyTable[i] =
916 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
917 pptable->LclkFrequencyTable[i] =
918 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
919 }
920
921 /* use AID0 serial number by default */
922 pptable->PublicSerialNumber_AID =
923 GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
924
925 amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC,
926 0, pptable->PublicSerialNumber_AID);
927 n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_AID);
928 for (i = 0; i < n; i++) {
929 amdgpu_device_set_uid(
930 smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i,
931 GET_METRIC_FIELD(PublicSerialNumber_AID,
932 version)[i]);
933 }
934 n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_XCD);
935 for (i = 0; i < n; i++) {
936 amdgpu_device_set_uid(
937 smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i,
938 GET_METRIC_FIELD(PublicSerialNumber_XCD,
939 version)[i]);
940 }
941
942 pptable->Init = true;
943 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
944 ret = smu_v13_0_6_get_static_metrics_table(smu);
945 if (ret)
946 return ret;
947 smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
948 }
949 }
950
951 return 0;
952 }
953
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)954 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
955 enum smu_clk_type clk_type,
956 uint32_t *min, uint32_t *max)
957 {
958 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
959 struct smu_table_context *smu_table = &smu->smu_table;
960 struct PPTable_t *pptable =
961 (struct PPTable_t *)smu_table->driver_pptable;
962 struct smu_13_0_dpm_table *dpm_table;
963 uint32_t min_clk, max_clk, param;
964 int ret = 0, clk_id = 0;
965
966 /* Use dpm tables, if data is already fetched */
967 if (pptable->Init) {
968 switch (clk_type) {
969 case SMU_MCLK:
970 case SMU_UCLK:
971 dpm_table = &dpm_context->dpm_tables.uclk_table;
972 break;
973 case SMU_GFXCLK:
974 case SMU_SCLK:
975 dpm_table = &dpm_context->dpm_tables.gfx_table;
976 break;
977 case SMU_SOCCLK:
978 dpm_table = &dpm_context->dpm_tables.soc_table;
979 break;
980 case SMU_FCLK:
981 dpm_table = &dpm_context->dpm_tables.fclk_table;
982 break;
983 case SMU_VCLK:
984 dpm_table = &dpm_context->dpm_tables.vclk_table;
985 break;
986 case SMU_DCLK:
987 dpm_table = &dpm_context->dpm_tables.dclk_table;
988 break;
989 default:
990 return -EINVAL;
991 }
992
993 min_clk = dpm_table->min;
994 max_clk = dpm_table->max;
995
996 if (min)
997 *min = min_clk;
998 if (max)
999 *max = max_clk;
1000
1001 if (min_clk && max_clk)
1002 return 0;
1003 }
1004
1005 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
1006 clk_id = smu_cmn_to_asic_specific_index(
1007 smu, CMN2ASIC_MAPPING_CLK, clk_type);
1008 if (clk_id < 0) {
1009 ret = -EINVAL;
1010 goto failed;
1011 }
1012 param = (clk_id & 0xffff) << 16;
1013 }
1014
1015 if (max) {
1016 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
1017 ret = smu_cmn_send_smc_msg(
1018 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
1019 else
1020 ret = smu_cmn_send_smc_msg_with_param(
1021 smu, SMU_MSG_GetMaxDpmFreq, param, max);
1022 if (ret)
1023 goto failed;
1024 }
1025
1026 if (min) {
1027 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
1028 ret = smu_cmn_send_smc_msg(
1029 smu, SMU_MSG_GetMinGfxclkFrequency, min);
1030 else
1031 ret = smu_cmn_send_smc_msg_with_param(
1032 smu, SMU_MSG_GetMinDpmFreq, param, min);
1033 }
1034
1035 failed:
1036 return ret;
1037 }
1038
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)1039 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
1040 enum smu_clk_type clk_type,
1041 uint32_t *levels)
1042 {
1043 int ret;
1044
1045 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
1046 if (!ret)
1047 ++(*levels);
1048
1049 return ret;
1050 }
1051
smu_v13_0_6_pm_policy_init(struct smu_context * smu)1052 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
1053 {
1054 struct smu_dpm_policy *policy;
1055
1056 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
1057 if (policy)
1058 policy->current_level = SOC_PSTATE_DEFAULT;
1059 }
1060
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)1061 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
1062 {
1063 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1064 struct smu_table_context *smu_table = &smu->smu_table;
1065 struct smu_13_0_dpm_table *dpm_table = NULL;
1066 struct PPTable_t *pptable =
1067 (struct PPTable_t *)smu_table->driver_pptable;
1068 uint32_t gfxclkmin, gfxclkmax, levels;
1069 int ret = 0, i, j;
1070 struct smu_v13_0_6_dpm_map dpm_map[] = {
1071 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
1072 &dpm_context->dpm_tables.soc_table,
1073 pptable->SocclkFrequencyTable },
1074 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
1075 &dpm_context->dpm_tables.uclk_table,
1076 pptable->UclkFrequencyTable },
1077 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
1078 &dpm_context->dpm_tables.fclk_table,
1079 pptable->FclkFrequencyTable },
1080 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
1081 &dpm_context->dpm_tables.vclk_table,
1082 pptable->VclkFrequencyTable },
1083 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
1084 &dpm_context->dpm_tables.dclk_table,
1085 pptable->DclkFrequencyTable },
1086 };
1087
1088 smu_v13_0_6_setup_driver_pptable(smu);
1089
1090 /* DPM policy not supported in older firmwares */
1091 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
1092 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1093
1094 smu_dpm->dpm_policies->policy_mask &=
1095 ~BIT(PP_PM_POLICY_SOC_PSTATE);
1096 }
1097
1098 smu_v13_0_6_pm_policy_init(smu);
1099 /* gfxclk dpm table setup */
1100 dpm_table = &dpm_context->dpm_tables.gfx_table;
1101 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1102 /* In the case of gfxclk, only fine-grained dpm is honored.
1103 * Get min/max values from FW.
1104 */
1105 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
1106 &gfxclkmin, &gfxclkmax);
1107 if (ret)
1108 return ret;
1109
1110 dpm_table->count = 2;
1111 dpm_table->dpm_levels[0].value = gfxclkmin;
1112 dpm_table->dpm_levels[0].enabled = true;
1113 dpm_table->dpm_levels[1].value = gfxclkmax;
1114 dpm_table->dpm_levels[1].enabled = true;
1115 dpm_table->min = dpm_table->dpm_levels[0].value;
1116 dpm_table->max = dpm_table->dpm_levels[1].value;
1117 } else {
1118 dpm_table->count = 1;
1119 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
1120 dpm_table->dpm_levels[0].enabled = true;
1121 dpm_table->min = dpm_table->dpm_levels[0].value;
1122 dpm_table->max = dpm_table->dpm_levels[0].value;
1123 }
1124
1125 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
1126 dpm_table = dpm_map[j].dpm_table;
1127 levels = 1;
1128 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
1129 ret = smu_v13_0_6_get_dpm_level_count(
1130 smu, dpm_map[j].clk_type, &levels);
1131 if (ret)
1132 return ret;
1133 }
1134 dpm_table->count = levels;
1135 for (i = 0; i < dpm_table->count; ++i) {
1136 dpm_table->dpm_levels[i].value =
1137 dpm_map[j].freq_table[i];
1138 dpm_table->dpm_levels[i].enabled = true;
1139
1140 }
1141 dpm_table->min = dpm_table->dpm_levels[0].value;
1142 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
1143
1144 }
1145
1146 return 0;
1147 }
1148
smu_v13_0_6_setup_pptable(struct smu_context * smu)1149 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1150 {
1151 struct smu_table_context *table_context = &smu->smu_table;
1152
1153 /* TODO: PPTable is not available.
1154 * 1) Find an alternate way to get 'PPTable values' here.
1155 * 2) Check if there is SW CTF
1156 */
1157 table_context->thermal_controller_type = 0;
1158
1159 return 0;
1160 }
1161
smu_v13_0_6_check_fw_status(struct smu_context * smu)1162 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1163 {
1164 struct amdgpu_device *adev = smu->adev;
1165 uint32_t mp1_fw_flags;
1166
1167 mp1_fw_flags =
1168 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1169
1170 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1171 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1172 return 0;
1173
1174 return -EIO;
1175 }
1176
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1177 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1178 {
1179 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1180 struct smu_13_0_dpm_table *gfx_table =
1181 &dpm_context->dpm_tables.gfx_table;
1182 struct smu_13_0_dpm_table *mem_table =
1183 &dpm_context->dpm_tables.uclk_table;
1184 struct smu_13_0_dpm_table *soc_table =
1185 &dpm_context->dpm_tables.soc_table;
1186 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1187
1188 pstate_table->gfxclk_pstate.min = gfx_table->min;
1189 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1190 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1191 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1192
1193 pstate_table->uclk_pstate.min = mem_table->min;
1194 pstate_table->uclk_pstate.peak = mem_table->max;
1195 pstate_table->uclk_pstate.curr.min = mem_table->min;
1196 pstate_table->uclk_pstate.curr.max = mem_table->max;
1197
1198 pstate_table->socclk_pstate.min = soc_table->min;
1199 pstate_table->socclk_pstate.peak = soc_table->max;
1200 pstate_table->socclk_pstate.curr.min = soc_table->min;
1201 pstate_table->socclk_pstate.curr.max = soc_table->max;
1202
1203 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1204 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1205 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1206 pstate_table->gfxclk_pstate.standard =
1207 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1208 pstate_table->uclk_pstate.standard =
1209 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1210 pstate_table->socclk_pstate.standard =
1211 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1212 } else {
1213 pstate_table->gfxclk_pstate.standard =
1214 pstate_table->gfxclk_pstate.min;
1215 pstate_table->uclk_pstate.standard =
1216 pstate_table->uclk_pstate.min;
1217 pstate_table->socclk_pstate.standard =
1218 pstate_table->socclk_pstate.min;
1219 }
1220
1221 return 0;
1222 }
1223
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)1224 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
1225 struct pp_clock_levels_with_latency *clocks,
1226 struct smu_13_0_dpm_table *dpm_table)
1227 {
1228 int i, count;
1229
1230 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
1231 dpm_table->count;
1232 clocks->num_levels = count;
1233
1234 for (i = 0; i < count; i++) {
1235 clocks->data[i].clocks_in_khz =
1236 dpm_table->dpm_levels[i].value * 1000;
1237 clocks->data[i].latency_in_us = 0;
1238 }
1239
1240 return 0;
1241 }
1242
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)1243 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
1244 int32_t frequency2)
1245 {
1246 return (abs(frequency1 - frequency2) <= EPSILON);
1247 }
1248
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1249 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1250 {
1251 struct smu_power_context *smu_power = &smu->smu_power;
1252 struct smu_13_0_power_context *power_context = smu_power->power_context;
1253 uint32_t throttler_status = 0;
1254
1255 throttler_status = atomic_read(&power_context->throttle_status);
1256 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1257
1258 return throttler_status;
1259 }
1260
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1261 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1262 MetricsMember_t member,
1263 uint32_t *value)
1264 {
1265 struct smu_table_context *smu_table = &smu->smu_table;
1266 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
1267 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
1268 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
1269 int version = smu_v13_0_6_get_metrics_version(smu);
1270 struct amdgpu_device *adev = smu->adev;
1271 int ret = 0;
1272 int xcc_id;
1273
1274 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1275 if (ret)
1276 return ret;
1277
1278 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
1279 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
1280 return smu_v13_0_12_get_smu_metrics_data(smu, member, value);
1281
1282 /* For clocks with multiple instances, only report the first one */
1283 switch (member) {
1284 case METRICS_CURR_GFXCLK:
1285 case METRICS_AVERAGE_GFXCLK:
1286 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1287 xcc_id = GET_INST(GC, 0);
1288 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
1289 } else {
1290 *value = 0;
1291 }
1292 break;
1293 case METRICS_CURR_SOCCLK:
1294 case METRICS_AVERAGE_SOCCLK:
1295 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
1296 break;
1297 case METRICS_CURR_UCLK:
1298 case METRICS_AVERAGE_UCLK:
1299 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
1300 break;
1301 case METRICS_CURR_VCLK:
1302 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
1303 break;
1304 case METRICS_CURR_DCLK:
1305 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
1306 break;
1307 case METRICS_CURR_FCLK:
1308 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
1309 break;
1310 case METRICS_AVERAGE_GFXACTIVITY:
1311 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
1312 break;
1313 case METRICS_AVERAGE_MEMACTIVITY:
1314 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
1315 break;
1316 case METRICS_CURR_SOCKETPOWER:
1317 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
1318 break;
1319 case METRICS_TEMPERATURE_HOTSPOT:
1320 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
1321 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1322 break;
1323 case METRICS_TEMPERATURE_MEM:
1324 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
1325 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1326 break;
1327 /* This is the max of all VRs and not just SOC VR.
1328 * No need to define another data type for the same.
1329 */
1330 case METRICS_TEMPERATURE_VRSOC:
1331 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
1332 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1333 break;
1334 default:
1335 *value = UINT_MAX;
1336 break;
1337 }
1338
1339 return ret;
1340 }
1341
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1342 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1343 enum smu_clk_type clk_type,
1344 uint32_t *value)
1345 {
1346 MetricsMember_t member_type;
1347
1348 if (!value)
1349 return -EINVAL;
1350
1351 switch (clk_type) {
1352 case SMU_GFXCLK:
1353 member_type = METRICS_CURR_GFXCLK;
1354 break;
1355 case SMU_UCLK:
1356 member_type = METRICS_CURR_UCLK;
1357 break;
1358 case SMU_SOCCLK:
1359 member_type = METRICS_CURR_SOCCLK;
1360 break;
1361 case SMU_VCLK:
1362 member_type = METRICS_CURR_VCLK;
1363 break;
1364 case SMU_DCLK:
1365 member_type = METRICS_CURR_DCLK;
1366 break;
1367 case SMU_FCLK:
1368 member_type = METRICS_CURR_FCLK;
1369 break;
1370 default:
1371 return -EINVAL;
1372 }
1373
1374 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1375 }
1376
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1377 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1378 struct smu_13_0_dpm_table *single_dpm_table,
1379 uint32_t curr_clk, const char *clk_name)
1380 {
1381 struct pp_clock_levels_with_latency clocks;
1382 int i, ret, level = -1;
1383 uint32_t clk1, clk2;
1384
1385 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1386 if (ret) {
1387 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1388 clk_name);
1389 return ret;
1390 }
1391
1392 if (!clocks.num_levels)
1393 return -EINVAL;
1394
1395 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1396 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1397 for (i = 0; i < clocks.num_levels; i++)
1398 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1399 clocks.data[i].clocks_in_khz /
1400 1000);
1401
1402 } else {
1403 if ((clocks.num_levels == 1) ||
1404 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1405 level = 0;
1406 for (i = 0; i < clocks.num_levels; i++) {
1407 clk1 = clocks.data[i].clocks_in_khz / 1000;
1408
1409 if (i < (clocks.num_levels - 1))
1410 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1411
1412 if (curr_clk == clk1) {
1413 level = i;
1414 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1415 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1416 i :
1417 i + 1;
1418 }
1419
1420 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1421 clk1, (level == i) ? "*" : "");
1422 }
1423 }
1424
1425 return size;
1426 }
1427
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1428 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1429 enum smu_clk_type type, char *buf)
1430 {
1431 int now, size = 0;
1432 int ret = 0;
1433 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1434 struct smu_13_0_dpm_table *single_dpm_table;
1435 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1436 struct smu_13_0_dpm_context *dpm_context = NULL;
1437 uint32_t min_clk, max_clk;
1438
1439 smu_cmn_get_sysfs_buf(&buf, &size);
1440
1441 if (amdgpu_ras_intr_triggered()) {
1442 size += sysfs_emit_at(buf, size, "unavailable\n");
1443 return size;
1444 }
1445
1446 dpm_context = smu_dpm->dpm_context;
1447
1448 switch (type) {
1449 case SMU_OD_SCLK:
1450 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1451 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1452 pstate_table->gfxclk_pstate.curr.min,
1453 pstate_table->gfxclk_pstate.curr.max);
1454 break;
1455 case SMU_SCLK:
1456 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1457 &now);
1458 if (ret) {
1459 dev_err(smu->adev->dev,
1460 "Attempt to get current gfx clk Failed!");
1461 return ret;
1462 }
1463
1464 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1465 min_clk = single_dpm_table->min;
1466 max_clk = single_dpm_table->max;
1467
1468 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1469 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1470 now);
1471 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1472 min_clk);
1473 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1474 max_clk);
1475
1476 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1477 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1478 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1479 min_clk);
1480 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1481 now);
1482 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1483 max_clk);
1484 } else {
1485 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1486 min_clk,
1487 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1488 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1489 max_clk,
1490 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1491 }
1492
1493 break;
1494
1495 case SMU_OD_MCLK:
1496 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
1497 return 0;
1498
1499 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1500 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1501 pstate_table->uclk_pstate.curr.min,
1502 pstate_table->uclk_pstate.curr.max);
1503 break;
1504 case SMU_MCLK:
1505 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1506 &now);
1507 if (ret) {
1508 dev_err(smu->adev->dev,
1509 "Attempt to get current mclk Failed!");
1510 return ret;
1511 }
1512
1513 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1514
1515 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1516 now, "mclk");
1517
1518 case SMU_SOCCLK:
1519 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1520 &now);
1521 if (ret) {
1522 dev_err(smu->adev->dev,
1523 "Attempt to get current socclk Failed!");
1524 return ret;
1525 }
1526
1527 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1528
1529 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1530 now, "socclk");
1531
1532 case SMU_FCLK:
1533 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1534 &now);
1535 if (ret) {
1536 dev_err(smu->adev->dev,
1537 "Attempt to get current fclk Failed!");
1538 return ret;
1539 }
1540
1541 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1542
1543 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1544 now, "fclk");
1545
1546 case SMU_VCLK:
1547 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1548 &now);
1549 if (ret) {
1550 dev_err(smu->adev->dev,
1551 "Attempt to get current vclk Failed!");
1552 return ret;
1553 }
1554
1555 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1556
1557 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1558 now, "vclk");
1559
1560 case SMU_DCLK:
1561 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1562 &now);
1563 if (ret) {
1564 dev_err(smu->adev->dev,
1565 "Attempt to get current dclk Failed!");
1566 return ret;
1567 }
1568
1569 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1570
1571 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1572 now, "dclk");
1573
1574 default:
1575 break;
1576 }
1577
1578 return size;
1579 }
1580
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1581 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1582 uint32_t feature_mask, uint32_t level)
1583 {
1584 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1585 uint32_t freq;
1586 int ret = 0;
1587
1588 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1589 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1590 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1591 ret = smu_cmn_send_smc_msg_with_param(
1592 smu,
1593 (max ? SMU_MSG_SetSoftMaxGfxClk :
1594 SMU_MSG_SetSoftMinGfxclk),
1595 freq & 0xffff, NULL);
1596 if (ret) {
1597 dev_err(smu->adev->dev,
1598 "Failed to set soft %s gfxclk !\n",
1599 max ? "max" : "min");
1600 return ret;
1601 }
1602 }
1603
1604 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1605 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1606 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1607 .value;
1608 ret = smu_cmn_send_smc_msg_with_param(
1609 smu,
1610 (max ? SMU_MSG_SetSoftMaxByFreq :
1611 SMU_MSG_SetSoftMinByFreq),
1612 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1613 if (ret) {
1614 dev_err(smu->adev->dev,
1615 "Failed to set soft %s memclk !\n",
1616 max ? "max" : "min");
1617 return ret;
1618 }
1619 }
1620
1621 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1622 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1623 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1624 ret = smu_cmn_send_smc_msg_with_param(
1625 smu,
1626 (max ? SMU_MSG_SetSoftMaxByFreq :
1627 SMU_MSG_SetSoftMinByFreq),
1628 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1629 if (ret) {
1630 dev_err(smu->adev->dev,
1631 "Failed to set soft %s socclk !\n",
1632 max ? "max" : "min");
1633 return ret;
1634 }
1635 }
1636
1637 return ret;
1638 }
1639
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1640 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1641 enum smu_clk_type type, uint32_t mask)
1642 {
1643 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1644 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1645 uint32_t soft_min_level, soft_max_level;
1646 int ret = 0;
1647
1648 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1649 soft_max_level = mask ? (fls(mask) - 1) : 0;
1650
1651 switch (type) {
1652 case SMU_SCLK:
1653 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1654 if (soft_max_level >= single_dpm_table->count) {
1655 dev_err(smu->adev->dev,
1656 "Clock level specified %d is over max allowed %d\n",
1657 soft_max_level, single_dpm_table->count - 1);
1658 ret = -EINVAL;
1659 break;
1660 }
1661
1662 ret = smu_v13_0_6_upload_dpm_level(
1663 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1664 soft_min_level);
1665 if (ret) {
1666 dev_err(smu->adev->dev,
1667 "Failed to upload boot level to lowest!\n");
1668 break;
1669 }
1670
1671 ret = smu_v13_0_6_upload_dpm_level(
1672 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1673 soft_max_level);
1674 if (ret)
1675 dev_err(smu->adev->dev,
1676 "Failed to upload dpm max level to highest!\n");
1677
1678 break;
1679
1680 case SMU_MCLK:
1681 case SMU_SOCCLK:
1682 case SMU_FCLK:
1683 /*
1684 * Should not arrive here since smu_13_0_6 does not
1685 * support mclk/socclk/fclk softmin/softmax settings
1686 */
1687 ret = -EINVAL;
1688 break;
1689
1690 default:
1691 break;
1692 }
1693
1694 return ret;
1695 }
1696
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1697 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1698 enum amd_pp_sensors sensor,
1699 uint32_t *value)
1700 {
1701 int ret = 0;
1702
1703 if (!value)
1704 return -EINVAL;
1705
1706 switch (sensor) {
1707 case AMDGPU_PP_SENSOR_GPU_LOAD:
1708 ret = smu_v13_0_6_get_smu_metrics_data(
1709 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1710 break;
1711 case AMDGPU_PP_SENSOR_MEM_LOAD:
1712 ret = smu_v13_0_6_get_smu_metrics_data(
1713 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1714 break;
1715 default:
1716 dev_err(smu->adev->dev,
1717 "Invalid sensor for retrieving clock activity\n");
1718 return -EINVAL;
1719 }
1720
1721 return ret;
1722 }
1723
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1724 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1725 enum amd_pp_sensors sensor,
1726 uint32_t *value)
1727 {
1728 int ret = 0;
1729
1730 if (!value)
1731 return -EINVAL;
1732
1733 switch (sensor) {
1734 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1735 ret = smu_v13_0_6_get_smu_metrics_data(
1736 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1737 break;
1738 case AMDGPU_PP_SENSOR_MEM_TEMP:
1739 ret = smu_v13_0_6_get_smu_metrics_data(
1740 smu, METRICS_TEMPERATURE_MEM, value);
1741 break;
1742 default:
1743 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1744 return -EINVAL;
1745 }
1746
1747 return ret;
1748 }
1749
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1750 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1751 enum amd_pp_sensors sensor, void *data,
1752 uint32_t *size)
1753 {
1754 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1755 int ret = 0;
1756
1757 if (amdgpu_ras_intr_triggered())
1758 return 0;
1759
1760 if (!data || !size)
1761 return -EINVAL;
1762
1763 switch (sensor) {
1764 case AMDGPU_PP_SENSOR_MEM_LOAD:
1765 case AMDGPU_PP_SENSOR_GPU_LOAD:
1766 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1767 (uint32_t *)data);
1768 *size = 4;
1769 break;
1770 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1771 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1772 METRICS_CURR_SOCKETPOWER,
1773 (uint32_t *)data);
1774 *size = 4;
1775 break;
1776 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1777 case AMDGPU_PP_SENSOR_MEM_TEMP:
1778 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1779 (uint32_t *)data);
1780 *size = 4;
1781 break;
1782 case AMDGPU_PP_SENSOR_GFX_MCLK:
1783 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1784 smu, SMU_UCLK, (uint32_t *)data);
1785 /* the output clock frequency in 10K unit */
1786 *(uint32_t *)data *= 100;
1787 *size = 4;
1788 break;
1789 case AMDGPU_PP_SENSOR_GFX_SCLK:
1790 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1791 smu, SMU_GFXCLK, (uint32_t *)data);
1792 *(uint32_t *)data *= 100;
1793 *size = 4;
1794 break;
1795 case AMDGPU_PP_SENSOR_VDDGFX:
1796 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1797 *size = 4;
1798 break;
1799 case AMDGPU_PP_SENSOR_VDDBOARD:
1800 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
1801 *(uint32_t *)data = dpm_context->board_volt;
1802 *size = 4;
1803 break;
1804 } else {
1805 ret = -EOPNOTSUPP;
1806 break;
1807 }
1808 case AMDGPU_PP_SENSOR_NODEPOWERLIMIT:
1809 case AMDGPU_PP_SENSOR_NODEPOWER:
1810 case AMDGPU_PP_SENSOR_GPPTRESIDENCY:
1811 case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT:
1812 ret = smu_v13_0_12_get_npm_data(smu, sensor, (uint32_t *)data);
1813 if (ret)
1814 return ret;
1815 *size = 4;
1816 break;
1817 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1818 default:
1819 ret = -EOPNOTSUPP;
1820 break;
1821 }
1822
1823 return ret;
1824 }
1825
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1826 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1827 uint32_t *current_power_limit,
1828 uint32_t *default_power_limit,
1829 uint32_t *max_power_limit,
1830 uint32_t *min_power_limit)
1831 {
1832 struct smu_table_context *smu_table = &smu->smu_table;
1833 struct PPTable_t *pptable =
1834 (struct PPTable_t *)smu_table->driver_pptable;
1835 uint32_t power_limit = 0;
1836 int ret;
1837
1838 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1839
1840 if (ret) {
1841 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1842 return -EINVAL;
1843 }
1844
1845 if (current_power_limit)
1846 *current_power_limit = power_limit;
1847 if (default_power_limit)
1848 *default_power_limit = power_limit;
1849
1850 if (max_power_limit) {
1851 *max_power_limit = pptable->MaxSocketPowerLimit;
1852 }
1853
1854 if (min_power_limit)
1855 *min_power_limit = 0;
1856 return 0;
1857 }
1858
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1859 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1860 enum smu_ppt_limit_type limit_type,
1861 uint32_t limit)
1862 {
1863 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1864 }
1865
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1866 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1867 struct amdgpu_irq_src *source,
1868 struct amdgpu_iv_entry *entry)
1869 {
1870 struct smu_context *smu = adev->powerplay.pp_handle;
1871 struct smu_power_context *smu_power = &smu->smu_power;
1872 struct smu_13_0_power_context *power_context = smu_power->power_context;
1873 uint32_t client_id = entry->client_id;
1874 uint32_t ctxid = entry->src_data[0];
1875 uint32_t src_id = entry->src_id;
1876 uint32_t data;
1877
1878 if (client_id == SOC15_IH_CLIENTID_MP1) {
1879 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1880 /* ACK SMUToHost interrupt */
1881 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1882 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1883 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1884 /*
1885 * ctxid is used to distinguish different events for SMCToHost
1886 * interrupt.
1887 */
1888 switch (ctxid) {
1889 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1890 /*
1891 * Increment the throttle interrupt counter
1892 */
1893 atomic64_inc(&smu->throttle_int_counter);
1894
1895 if (!atomic_read(&adev->throttling_logging_enabled))
1896 return 0;
1897
1898 /* This uses the new method which fixes the
1899 * incorrect throttling status reporting
1900 * through metrics table. For older FWs,
1901 * it will be ignored.
1902 */
1903 if (__ratelimit(&adev->throttling_logging_rs)) {
1904 atomic_set(
1905 &power_context->throttle_status,
1906 entry->src_data[1]);
1907 schedule_work(&smu->throttling_logging_work);
1908 }
1909 break;
1910 default:
1911 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1912 ctxid, client_id);
1913 break;
1914 }
1915 }
1916 }
1917
1918 return 0;
1919 }
1920
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1921 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1922 struct amdgpu_irq_src *source,
1923 unsigned tyep,
1924 enum amdgpu_interrupt_state state)
1925 {
1926 uint32_t val = 0;
1927
1928 switch (state) {
1929 case AMDGPU_IRQ_STATE_DISABLE:
1930 /* For MP1 SW irqs */
1931 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1932 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1933 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1934
1935 break;
1936 case AMDGPU_IRQ_STATE_ENABLE:
1937 /* For MP1 SW irqs */
1938 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1939 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1940 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1941 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1942
1943 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1944 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1945 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1946
1947 break;
1948 default:
1949 break;
1950 }
1951
1952 return 0;
1953 }
1954
1955 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1956 .set = smu_v13_0_6_set_irq_state,
1957 .process = smu_v13_0_6_irq_process,
1958 };
1959
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1960 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1961 {
1962 struct amdgpu_device *adev = smu->adev;
1963 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1964 int ret = 0;
1965
1966 if (amdgpu_sriov_vf(adev))
1967 return 0;
1968
1969 irq_src->num_types = 1;
1970 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1971
1972 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1973 IH_INTERRUPT_ID_TO_DRIVER,
1974 irq_src);
1975 if (ret)
1976 return ret;
1977
1978 return ret;
1979 }
1980
smu_v13_0_6_notify_unload(struct smu_context * smu)1981 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1982 {
1983 if (amdgpu_in_reset(smu->adev))
1984 return 0;
1985
1986 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1987 /* Ignore return, just intimate FW that driver is not going to be there */
1988 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1989
1990 return 0;
1991 }
1992
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1993 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1994 {
1995 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1996 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1997 return 0;
1998
1999 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
2000 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
2001 NULL);
2002 }
2003
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)2004 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
2005 bool enable)
2006 {
2007 struct amdgpu_device *adev = smu->adev;
2008 int ret = 0;
2009
2010 if (amdgpu_sriov_vf(adev))
2011 return 0;
2012
2013 if (enable) {
2014 if (!(adev->flags & AMD_IS_APU))
2015 ret = smu_v13_0_system_features_control(smu, enable);
2016 } else {
2017 /* Notify FW that the device is no longer driver managed */
2018 smu_v13_0_6_notify_unload(smu);
2019 }
2020
2021 return ret;
2022 }
2023
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)2024 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
2025 uint32_t min,
2026 uint32_t max)
2027 {
2028 int ret;
2029
2030 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2031 max & 0xffff, NULL);
2032 if (ret)
2033 return ret;
2034
2035 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
2036 min & 0xffff, NULL);
2037
2038 return ret;
2039 }
2040
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)2041 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
2042 enum amd_dpm_forced_level level)
2043 {
2044 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2045 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2046 struct smu_13_0_dpm_table *gfx_table =
2047 &dpm_context->dpm_tables.gfx_table;
2048 struct smu_13_0_dpm_table *uclk_table =
2049 &dpm_context->dpm_tables.uclk_table;
2050 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2051 int ret;
2052
2053 /* Disable determinism if switching to another mode */
2054 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
2055 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
2056 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
2057 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
2058 }
2059
2060 switch (level) {
2061 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
2062 return 0;
2063
2064 case AMD_DPM_FORCED_LEVEL_AUTO:
2065 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
2066 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
2067 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2068 smu, gfx_table->min, gfx_table->max);
2069 if (ret)
2070 return ret;
2071
2072 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
2073 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
2074 }
2075
2076 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
2077 /* Min UCLK is not expected to be changed */
2078 ret = smu_v13_0_set_soft_freq_limited_range(
2079 smu, SMU_UCLK, 0, uclk_table->max, false);
2080 if (ret)
2081 return ret;
2082 pstate_table->uclk_pstate.curr.max = uclk_table->max;
2083 }
2084 smu_v13_0_reset_custom_level(smu);
2085
2086 return 0;
2087 case AMD_DPM_FORCED_LEVEL_MANUAL:
2088 return 0;
2089 default:
2090 break;
2091 }
2092
2093 return -EOPNOTSUPP;
2094 }
2095
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)2096 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
2097 enum smu_clk_type clk_type,
2098 uint32_t min, uint32_t max,
2099 bool automatic)
2100 {
2101 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2102 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2103 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2104 struct amdgpu_device *adev = smu->adev;
2105 uint32_t min_clk;
2106 uint32_t max_clk;
2107 int ret = 0;
2108
2109 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
2110 clk_type != SMU_UCLK)
2111 return -EINVAL;
2112
2113 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2114 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2115 return -EINVAL;
2116
2117 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
2118 if (min >= max) {
2119 dev_err(smu->adev->dev,
2120 "Minimum clk should be less than the maximum allowed clock\n");
2121 return -EINVAL;
2122 }
2123
2124 if (clk_type == SMU_GFXCLK) {
2125 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
2126 (max == pstate_table->gfxclk_pstate.curr.max))
2127 return 0;
2128
2129 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2130 smu, min, max);
2131 if (!ret) {
2132 pstate_table->gfxclk_pstate.curr.min = min;
2133 pstate_table->gfxclk_pstate.curr.max = max;
2134 }
2135 }
2136
2137 if (clk_type == SMU_UCLK) {
2138 if (max == pstate_table->uclk_pstate.curr.max)
2139 return 0;
2140 /* For VF, only allowed in FW versions 85.102 or greater */
2141 if (!smu_v13_0_6_cap_supported(smu,
2142 SMU_CAP(SET_UCLK_MAX)))
2143 return -EOPNOTSUPP;
2144 /* Only max clock limiting is allowed for UCLK */
2145 ret = smu_v13_0_set_soft_freq_limited_range(
2146 smu, SMU_UCLK, 0, max, false);
2147 if (!ret)
2148 pstate_table->uclk_pstate.curr.max = max;
2149 }
2150
2151 return ret;
2152 }
2153
2154 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2155 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
2156 (max > dpm_context->dpm_tables.gfx_table.max)) {
2157 dev_warn(
2158 adev->dev,
2159 "Invalid max frequency %d MHz specified for determinism\n",
2160 max);
2161 return -EINVAL;
2162 }
2163
2164 /* Restore default min/max clocks and enable determinism */
2165 min_clk = dpm_context->dpm_tables.gfx_table.min;
2166 max_clk = dpm_context->dpm_tables.gfx_table.max;
2167 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2168 max_clk);
2169 if (!ret) {
2170 usleep_range(500, 1000);
2171 ret = smu_cmn_send_smc_msg_with_param(
2172 smu, SMU_MSG_EnableDeterminism, max, NULL);
2173 if (ret) {
2174 dev_err(adev->dev,
2175 "Failed to enable determinism at GFX clock %d MHz\n",
2176 max);
2177 } else {
2178 pstate_table->gfxclk_pstate.curr.min = min_clk;
2179 pstate_table->gfxclk_pstate.curr.max = max;
2180 }
2181 }
2182 }
2183
2184 return ret;
2185 }
2186
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2187 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2188 enum PP_OD_DPM_TABLE_COMMAND type,
2189 long input[], uint32_t size)
2190 {
2191 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2192 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2193 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2194 uint32_t min_clk;
2195 uint32_t max_clk;
2196 int ret = 0;
2197
2198 /* Only allowed in manual or determinism mode */
2199 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2200 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2201 return -EINVAL;
2202
2203 switch (type) {
2204 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2205 if (size != 2) {
2206 dev_err(smu->adev->dev,
2207 "Input parameter number not correct\n");
2208 return -EINVAL;
2209 }
2210
2211 if (input[0] == 0) {
2212 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
2213 dev_warn(
2214 smu->adev->dev,
2215 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2216 input[1],
2217 dpm_context->dpm_tables.gfx_table.min);
2218 pstate_table->gfxclk_pstate.custom.min =
2219 pstate_table->gfxclk_pstate.curr.min;
2220 return -EINVAL;
2221 }
2222
2223 pstate_table->gfxclk_pstate.custom.min = input[1];
2224 } else if (input[0] == 1) {
2225 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
2226 dev_warn(
2227 smu->adev->dev,
2228 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2229 input[1],
2230 dpm_context->dpm_tables.gfx_table.max);
2231 pstate_table->gfxclk_pstate.custom.max =
2232 pstate_table->gfxclk_pstate.curr.max;
2233 return -EINVAL;
2234 }
2235
2236 pstate_table->gfxclk_pstate.custom.max = input[1];
2237 } else {
2238 return -EINVAL;
2239 }
2240 break;
2241 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2242 if (size != 2) {
2243 dev_err(smu->adev->dev,
2244 "Input parameter number not correct\n");
2245 return -EINVAL;
2246 }
2247
2248 if (!smu_cmn_feature_is_enabled(smu,
2249 SMU_FEATURE_DPM_UCLK_BIT)) {
2250 dev_warn(smu->adev->dev,
2251 "UCLK_LIMITS setting not supported!\n");
2252 return -EOPNOTSUPP;
2253 }
2254
2255 if (input[0] == 0) {
2256 dev_info(smu->adev->dev,
2257 "Setting min UCLK level is not supported");
2258 return -EINVAL;
2259 } else if (input[0] == 1) {
2260 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
2261 dev_warn(
2262 smu->adev->dev,
2263 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2264 input[1],
2265 dpm_context->dpm_tables.uclk_table.max);
2266 pstate_table->uclk_pstate.custom.max =
2267 pstate_table->uclk_pstate.curr.max;
2268 return -EINVAL;
2269 }
2270
2271 pstate_table->uclk_pstate.custom.max = input[1];
2272 }
2273 break;
2274
2275 case PP_OD_RESTORE_DEFAULT_TABLE:
2276 if (size != 0) {
2277 dev_err(smu->adev->dev,
2278 "Input parameter number not correct\n");
2279 return -EINVAL;
2280 } else {
2281 /* Use the default frequencies for manual and determinism mode */
2282 min_clk = dpm_context->dpm_tables.gfx_table.min;
2283 max_clk = dpm_context->dpm_tables.gfx_table.max;
2284
2285 ret = smu_v13_0_6_set_soft_freq_limited_range(
2286 smu, SMU_GFXCLK, min_clk, max_clk, false);
2287
2288 if (ret)
2289 return ret;
2290
2291 min_clk = dpm_context->dpm_tables.uclk_table.min;
2292 max_clk = dpm_context->dpm_tables.uclk_table.max;
2293 ret = smu_v13_0_6_set_soft_freq_limited_range(
2294 smu, SMU_UCLK, min_clk, max_clk, false);
2295 if (ret)
2296 return ret;
2297 smu_v13_0_reset_custom_level(smu);
2298 }
2299 break;
2300 case PP_OD_COMMIT_DPM_TABLE:
2301 if (size != 0) {
2302 dev_err(smu->adev->dev,
2303 "Input parameter number not correct\n");
2304 return -EINVAL;
2305 } else {
2306 if (!pstate_table->gfxclk_pstate.custom.min)
2307 pstate_table->gfxclk_pstate.custom.min =
2308 pstate_table->gfxclk_pstate.curr.min;
2309
2310 if (!pstate_table->gfxclk_pstate.custom.max)
2311 pstate_table->gfxclk_pstate.custom.max =
2312 pstate_table->gfxclk_pstate.curr.max;
2313
2314 min_clk = pstate_table->gfxclk_pstate.custom.min;
2315 max_clk = pstate_table->gfxclk_pstate.custom.max;
2316
2317 ret = smu_v13_0_6_set_soft_freq_limited_range(
2318 smu, SMU_GFXCLK, min_clk, max_clk, false);
2319
2320 if (ret)
2321 return ret;
2322
2323 if (!pstate_table->uclk_pstate.custom.max)
2324 return 0;
2325
2326 min_clk = pstate_table->uclk_pstate.curr.min;
2327 max_clk = pstate_table->uclk_pstate.custom.max;
2328 return smu_v13_0_6_set_soft_freq_limited_range(
2329 smu, SMU_UCLK, min_clk, max_clk, false);
2330 }
2331 break;
2332 default:
2333 return -ENOSYS;
2334 }
2335
2336 return ret;
2337 }
2338
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2339 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2340 uint64_t *feature_mask)
2341 {
2342 int ret;
2343
2344 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2345
2346 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2347 *feature_mask = 0;
2348 ret = 0;
2349 }
2350
2351 return ret;
2352 }
2353
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2354 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2355 {
2356 int ret;
2357 uint64_t feature_enabled;
2358
2359 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
2360 return smu_v13_0_12_is_dpm_running(smu);
2361
2362 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2363
2364 if (ret)
2365 return false;
2366
2367 return !!(feature_enabled & SMC_DPM_FEATURE);
2368 }
2369
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2370 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2371 void *table_data)
2372 {
2373 struct smu_table_context *smu_table = &smu->smu_table;
2374 struct smu_table *table = &smu_table->driver_table;
2375 struct amdgpu_device *adev = smu->adev;
2376 uint32_t table_size;
2377 int ret = 0;
2378
2379 if (!table_data)
2380 return -EINVAL;
2381
2382 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2383
2384 memcpy(table->cpu_addr, table_data, table_size);
2385 /* Flush hdp cache */
2386 amdgpu_asic_flush_hdp(adev, NULL);
2387 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2388 NULL);
2389
2390 return ret;
2391 }
2392
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2393 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2394 struct i2c_msg *msg, int num_msgs)
2395 {
2396 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2397 struct amdgpu_device *adev = smu_i2c->adev;
2398 struct smu_context *smu = adev->powerplay.pp_handle;
2399 struct smu_table_context *smu_table = &smu->smu_table;
2400 struct smu_table *table = &smu_table->driver_table;
2401 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2402 int i, j, r, c;
2403 u16 dir;
2404
2405 if (!adev->pm.dpm_enabled)
2406 return -EBUSY;
2407
2408 req = kzalloc(sizeof(*req), GFP_KERNEL);
2409 if (!req)
2410 return -ENOMEM;
2411
2412 req->I2CcontrollerPort = smu_i2c->port;
2413 req->I2CSpeed = I2C_SPEED_FAST_400K;
2414 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2415 dir = msg[0].flags & I2C_M_RD;
2416
2417 for (c = i = 0; i < num_msgs; i++) {
2418 for (j = 0; j < msg[i].len; j++, c++) {
2419 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2420
2421 if (!(msg[i].flags & I2C_M_RD)) {
2422 /* write */
2423 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2424 cmd->ReadWriteData = msg[i].buf[j];
2425 }
2426
2427 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2428 /* The direction changes.
2429 */
2430 dir = msg[i].flags & I2C_M_RD;
2431 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2432 }
2433
2434 req->NumCmds++;
2435
2436 /*
2437 * Insert STOP if we are at the last byte of either last
2438 * message for the transaction or the client explicitly
2439 * requires a STOP at this particular message.
2440 */
2441 if ((j == msg[i].len - 1) &&
2442 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2443 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2444 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2445 }
2446 }
2447 }
2448 mutex_lock(&adev->pm.mutex);
2449 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2450 if (r) {
2451 /* Retry once, in case of an i2c collision */
2452 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2453 if (r)
2454 goto fail;
2455 }
2456
2457 for (c = i = 0; i < num_msgs; i++) {
2458 if (!(msg[i].flags & I2C_M_RD)) {
2459 c += msg[i].len;
2460 continue;
2461 }
2462 for (j = 0; j < msg[i].len; j++, c++) {
2463 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2464
2465 msg[i].buf[j] = cmd->ReadWriteData;
2466 }
2467 }
2468 r = num_msgs;
2469 fail:
2470 mutex_unlock(&adev->pm.mutex);
2471 kfree(req);
2472 return r;
2473 }
2474
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2475 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2476 {
2477 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2478 }
2479
2480 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2481 .master_xfer = smu_v13_0_6_i2c_xfer,
2482 .functionality = smu_v13_0_6_i2c_func,
2483 };
2484
2485 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2486 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2487 .max_read_len = MAX_SW_I2C_COMMANDS,
2488 .max_write_len = MAX_SW_I2C_COMMANDS,
2489 .max_comb_1st_msg_len = 2,
2490 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2491 };
2492
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2493 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2494 {
2495 struct amdgpu_device *adev = smu->adev;
2496 int res, i;
2497
2498 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2499 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2500 struct i2c_adapter *control = &smu_i2c->adapter;
2501
2502 smu_i2c->adev = adev;
2503 smu_i2c->port = i;
2504 mutex_init(&smu_i2c->mutex);
2505 control->owner = THIS_MODULE;
2506 control->dev.parent = &adev->pdev->dev;
2507 control->algo = &smu_v13_0_6_i2c_algo;
2508 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2509 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2510 i2c_set_adapdata(control, smu_i2c);
2511
2512 res = devm_i2c_add_adapter(adev->dev, control);
2513 if (res) {
2514 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2515 return res;
2516 }
2517 }
2518
2519 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2520 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2521
2522 return 0;
2523 }
2524
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2525 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2526 {
2527 struct amdgpu_device *adev = smu->adev;
2528
2529 adev->pm.ras_eeprom_i2c_bus = NULL;
2530 adev->pm.fru_eeprom_i2c_bus = NULL;
2531 }
2532
smu_v13_0_6_get_unique_id(struct smu_context * smu)2533 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2534 {
2535 struct amdgpu_device *adev = smu->adev;
2536 struct smu_table_context *smu_table = &smu->smu_table;
2537 struct PPTable_t *pptable =
2538 (struct PPTable_t *)smu_table->driver_pptable;
2539
2540 adev->unique_id = pptable->PublicSerialNumber_AID;
2541 }
2542
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2543 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2544 {
2545 /* smu_13_0_6 does not support baco */
2546
2547 return 0;
2548 }
2549
2550 static const char *const throttling_logging_label[] = {
2551 [THROTTLER_PROCHOT_BIT] = "Prochot",
2552 [THROTTLER_PPT_BIT] = "PPT",
2553 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2554 [THROTTLER_THERMAL_VR_BIT] = "VR",
2555 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2556 };
2557
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2558 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2559 {
2560 int throttler_idx, throttling_events = 0, buf_idx = 0;
2561 struct amdgpu_device *adev = smu->adev;
2562 uint32_t throttler_status;
2563 char log_buf[256];
2564
2565 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2566 if (!throttler_status)
2567 return;
2568
2569 memset(log_buf, 0, sizeof(log_buf));
2570 for (throttler_idx = 0;
2571 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2572 throttler_idx++) {
2573 if (throttler_status & (1U << throttler_idx)) {
2574 throttling_events++;
2575 buf_idx += snprintf(
2576 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2577 "%s%s", throttling_events > 1 ? " and " : "",
2578 throttling_logging_label[throttler_idx]);
2579 if (buf_idx >= sizeof(log_buf)) {
2580 dev_err(adev->dev, "buffer overflow!\n");
2581 log_buf[sizeof(log_buf) - 1] = '\0';
2582 break;
2583 }
2584 }
2585 }
2586
2587 dev_warn(adev->dev,
2588 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2589 log_buf);
2590 kgd2kfd_smi_event_throttle(
2591 smu->adev->kfd.dev,
2592 smu_cmn_get_indep_throttler_status(throttler_status,
2593 smu_v13_0_6_throttler_map));
2594 }
2595
2596 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2597 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2598 {
2599 struct amdgpu_device *adev = smu->adev;
2600
2601 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2602 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2603 }
2604
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2605 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2606 {
2607 struct amdgpu_device *adev = smu->adev;
2608 uint32_t speed_level;
2609 uint32_t esm_ctrl;
2610
2611 /* TODO: confirm this on real target */
2612 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2613 if ((esm_ctrl >> 15) & 0x1)
2614 return (((esm_ctrl >> 8) & 0x7F) + 128);
2615
2616 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2617 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2618 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2619 if (speed_level > LINK_SPEED_MAX)
2620 speed_level = 0;
2621
2622 return pcie_gen_to_speed(speed_level + 1);
2623 }
2624
smu_v13_0_6_get_xcp_metrics(struct smu_context * smu,int xcp_id,void * table)2625 static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
2626 void *table)
2627 {
2628 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2629 int version = smu_v13_0_6_get_metrics_version(smu);
2630 struct amdgpu_partition_metrics_v1_0 *xcp_metrics;
2631 MetricsTableV0_t *metrics_v0 __free(kfree) = NULL;
2632 struct amdgpu_device *adev = smu->adev;
2633 int ret, inst, i, j, k, idx;
2634 MetricsTableV1_t *metrics_v1;
2635 MetricsTableV2_t *metrics_v2;
2636 struct amdgpu_xcp *xcp;
2637 u32 inst_mask;
2638 bool per_inst;
2639
2640 if (!table)
2641 return sizeof(*xcp_metrics);
2642
2643 for_each_xcp(adev->xcp_mgr, xcp, i) {
2644 if (xcp->id == xcp_id)
2645 break;
2646 }
2647 if (i == adev->xcp_mgr->num_xcps)
2648 return -EINVAL;
2649
2650 xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table;
2651 smu_cmn_init_partition_metrics(xcp_metrics, 1, 0);
2652
2653 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2654 if (!metrics_v0)
2655 return -ENOMEM;
2656
2657 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
2658 if (ret)
2659 return ret;
2660
2661 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
2662 IP_VERSION(13, 0, 12) &&
2663 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
2664 return smu_v13_0_12_get_xcp_metrics(smu, xcp, table,
2665 metrics_v0);
2666
2667 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2668 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2669
2670 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2671
2672 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2673 idx = 0;
2674 for_each_inst(k, inst_mask) {
2675 /* Both JPEG and VCN has same instances */
2676 inst = GET_INST(VCN, k);
2677
2678 for (j = 0; j < num_jpeg_rings; ++j) {
2679 xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
2680 SMUQ10_ROUND(GET_METRIC_FIELD(
2681 JpegBusy,
2682 version)[(inst * num_jpeg_rings) + j]);
2683 }
2684 xcp_metrics->vcn_busy[idx] =
2685 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2686
2687 xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND(
2688 GET_METRIC_FIELD(VclkFrequency, version)[inst]);
2689 xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND(
2690 GET_METRIC_FIELD(DclkFrequency, version)[inst]);
2691 xcp_metrics->current_socclk[idx] = SMUQ10_ROUND(
2692 GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
2693
2694 idx++;
2695 }
2696
2697 xcp_metrics->current_uclk =
2698 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2699
2700 if (per_inst) {
2701 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2702 idx = 0;
2703 for_each_inst(k, inst_mask) {
2704 inst = GET_INST(GC, k);
2705 xcp_metrics->current_gfxclk[idx] =
2706 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency,
2707 version)[inst]);
2708
2709 xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(
2710 GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2711 xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(
2712 GET_GPU_METRIC_FIELD(GfxBusyAcc,
2713 version)[inst]);
2714 if (smu_v13_0_6_cap_supported(
2715 smu, SMU_CAP(HST_LIMIT_METRICS))) {
2716 xcp_metrics->gfx_below_host_limit_ppt_acc
2717 [idx] = SMUQ10_ROUND(
2718 metrics_v0->GfxclkBelowHostLimitPptAcc
2719 [inst]);
2720 xcp_metrics->gfx_below_host_limit_thm_acc
2721 [idx] = SMUQ10_ROUND(
2722 metrics_v0->GfxclkBelowHostLimitThmAcc
2723 [inst]);
2724 xcp_metrics->gfx_low_utilization_acc
2725 [idx] = SMUQ10_ROUND(
2726 metrics_v0
2727 ->GfxclkLowUtilizationAcc[inst]);
2728 xcp_metrics->gfx_below_host_limit_total_acc
2729 [idx] = SMUQ10_ROUND(
2730 metrics_v0->GfxclkBelowHostLimitTotalAcc
2731 [inst]);
2732 }
2733 idx++;
2734 }
2735 }
2736
2737 return sizeof(*xcp_metrics);
2738 }
2739
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2740 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2741 {
2742 struct smu_table_context *smu_table = &smu->smu_table;
2743 struct gpu_metrics_v1_8 *gpu_metrics =
2744 (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table;
2745 int version = smu_v13_0_6_get_metrics_version(smu);
2746 MetricsTableV0_t *metrics_v0 __free(kfree) = NULL;
2747 int ret = 0, xcc_id, inst, i, j, k, idx;
2748 struct amdgpu_device *adev = smu->adev;
2749 MetricsTableV1_t *metrics_v1;
2750 MetricsTableV2_t *metrics_v2;
2751 struct amdgpu_xcp *xcp;
2752 u16 link_width_level;
2753 u8 num_jpeg_rings;
2754 u32 inst_mask;
2755 bool per_inst;
2756
2757 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2758 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
2759 if (ret)
2760 return ret;
2761
2762 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
2763 IP_VERSION(13, 0, 12) &&
2764 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
2765 return smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0);
2766
2767 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2768 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2769
2770 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8);
2771
2772 gpu_metrics->temperature_hotspot =
2773 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
2774 /* Individual HBM stack temperature is not reported */
2775 gpu_metrics->temperature_mem =
2776 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
2777 /* Reports max temperature of all voltage rails */
2778 gpu_metrics->temperature_vrsoc =
2779 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
2780
2781 gpu_metrics->average_gfx_activity =
2782 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
2783 gpu_metrics->average_umc_activity =
2784 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
2785
2786 gpu_metrics->mem_max_bandwidth =
2787 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
2788
2789 gpu_metrics->curr_socket_power =
2790 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
2791 /* Energy counter reported in 15.259uJ (2^-16) units */
2792 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
2793
2794 for (i = 0; i < MAX_GFX_CLKS; i++) {
2795 xcc_id = GET_INST(GC, i);
2796 if (xcc_id >= 0)
2797 gpu_metrics->current_gfxclk[i] =
2798 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
2799
2800 if (i < MAX_CLKS) {
2801 gpu_metrics->current_socclk[i] =
2802 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
2803 inst = GET_INST(VCN, i);
2804 if (inst >= 0) {
2805 gpu_metrics->current_vclk0[i] =
2806 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
2807 version)[inst]);
2808 gpu_metrics->current_dclk0[i] =
2809 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
2810 version)[inst]);
2811 }
2812 }
2813 }
2814
2815 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2816
2817 /* Total accumulated cycle counter */
2818 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2819
2820 /* Accumulated throttler residencies */
2821 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
2822 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
2823 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
2824 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
2825 gpu_metrics->hbm_thm_residency_acc =
2826 GET_METRIC_FIELD(HbmThmResidencyAcc, version);
2827
2828 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2829 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
2830 version) >> GET_INST(GC, 0);
2831
2832 if (!(adev->flags & AMD_IS_APU)) {
2833 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2834 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2835 * for pf from registers
2836 */
2837 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2838 gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
2839 gpu_metrics->pcie_link_speed =
2840 pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
2841 } else if (!amdgpu_sriov_vf(adev)) {
2842 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2843 if (link_width_level > MAX_LINK_WIDTH)
2844 link_width_level = 0;
2845
2846 gpu_metrics->pcie_link_width =
2847 DECODE_LANE_WIDTH(link_width_level);
2848 gpu_metrics->pcie_link_speed =
2849 smu_v13_0_6_get_current_pcie_link_speed(smu);
2850 }
2851
2852 gpu_metrics->pcie_bandwidth_acc =
2853 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
2854 gpu_metrics->pcie_bandwidth_inst =
2855 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
2856 gpu_metrics->pcie_l0_to_recov_count_acc =
2857 GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
2858 gpu_metrics->pcie_replay_count_acc =
2859 GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
2860 gpu_metrics->pcie_replay_rover_count_acc =
2861 GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
2862 gpu_metrics->pcie_nak_sent_count_acc =
2863 GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
2864 gpu_metrics->pcie_nak_rcvd_count_acc =
2865 GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
2866 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2867 gpu_metrics->pcie_lc_perf_other_end_recovery =
2868 GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
2869
2870 }
2871
2872 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2873
2874 gpu_metrics->gfx_activity_acc =
2875 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
2876 gpu_metrics->mem_activity_acc =
2877 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
2878
2879 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2880 j = amdgpu_xgmi_get_ext_link(adev, i);
2881 if (j < 0 || j >= NUM_XGMI_LINKS)
2882 continue;
2883 gpu_metrics->xgmi_read_data_acc[j] = SMUQ10_ROUND(
2884 GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
2885 gpu_metrics->xgmi_write_data_acc[j] = SMUQ10_ROUND(
2886 GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
2887 ret = amdgpu_get_xgmi_link_status(adev, i);
2888 if (ret >= 0)
2889 gpu_metrics->xgmi_link_status[j] = ret;
2890 }
2891
2892 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
2893
2894 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2895
2896 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2897 for_each_xcp(adev->xcp_mgr, xcp, i) {
2898 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2899 idx = 0;
2900 for_each_inst(k, inst_mask) {
2901 /* Both JPEG and VCN has same instances */
2902 inst = GET_INST(VCN, k);
2903
2904 for (j = 0; j < num_jpeg_rings; ++j) {
2905 gpu_metrics->xcp_stats[i].jpeg_busy
2906 [(idx * num_jpeg_rings) + j] =
2907 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
2908 [(inst * num_jpeg_rings) + j]);
2909 }
2910 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
2911 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2912 idx++;
2913
2914 }
2915
2916 if (per_inst) {
2917 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2918 idx = 0;
2919 for_each_inst(k, inst_mask) {
2920 inst = GET_INST(GC, k);
2921 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
2922 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2923 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2924 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
2925 version)[inst]);
2926 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) {
2927 gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] =
2928 SMUQ10_ROUND
2929 (metrics_v0->GfxclkBelowHostLimitPptAcc[inst]);
2930 gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] =
2931 SMUQ10_ROUND
2932 (metrics_v0->GfxclkBelowHostLimitThmAcc[inst]);
2933 gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] =
2934 SMUQ10_ROUND
2935 (metrics_v0->GfxclkLowUtilizationAcc[inst]);
2936 gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] =
2937 SMUQ10_ROUND
2938 (metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]);
2939 }
2940 idx++;
2941 }
2942 }
2943 }
2944
2945 gpu_metrics->xgmi_link_width = GET_METRIC_FIELD(XgmiWidth, version);
2946 gpu_metrics->xgmi_link_speed = GET_METRIC_FIELD(XgmiBitrate, version);
2947
2948 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2949
2950 *table = (void *)gpu_metrics;
2951
2952 return sizeof(*gpu_metrics);
2953 }
2954
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2955 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2956 {
2957 struct amdgpu_device *adev = smu->adev;
2958 int i;
2959
2960 for (i = 0; i < 16; i++)
2961 pci_write_config_dword(adev->pdev, i * 4,
2962 adev->pdev->saved_config_space[i]);
2963 pci_restore_msi_state(adev->pdev);
2964 }
2965
smu_v13_0_6_mode2_reset(struct smu_context * smu)2966 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2967 {
2968 int ret = 0, index;
2969 struct amdgpu_device *adev = smu->adev;
2970 int timeout = 10;
2971
2972 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2973 SMU_MSG_GfxDeviceDriverReset);
2974 if (index < 0)
2975 return index;
2976
2977 mutex_lock(&smu->message_lock);
2978
2979 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2980 SMU_RESET_MODE_2);
2981
2982 /* Reset takes a bit longer, wait for 200ms. */
2983 msleep(200);
2984
2985 dev_dbg(smu->adev->dev, "restore config space...\n");
2986 /* Restore the config space saved during init */
2987 amdgpu_device_load_pci_state(adev->pdev);
2988
2989 /* Certain platforms have switches which assign virtual BAR values to
2990 * devices. OS uses the virtual BAR values and device behind the switch
2991 * is assgined another BAR value. When device's config space registers
2992 * are queried, switch returns the virtual BAR values. When mode-2 reset
2993 * is performed, switch is unaware of it, and will continue to return
2994 * the same virtual values to the OS.This affects
2995 * pci_restore_config_space() API as it doesn't write the value saved if
2996 * the current value read from config space is the same as what is
2997 * saved. As a workaround, make sure the config space is restored
2998 * always.
2999 */
3000 if (!(adev->flags & AMD_IS_APU))
3001 smu_v13_0_6_restore_pci_config(smu);
3002
3003 dev_dbg(smu->adev->dev, "wait for reset ack\n");
3004 do {
3005 ret = smu_cmn_wait_for_response(smu);
3006 /* Wait a bit more time for getting ACK */
3007 if (ret == -ETIME) {
3008 --timeout;
3009 usleep_range(500, 1000);
3010 continue;
3011 }
3012
3013 if (ret)
3014 goto out;
3015
3016 } while (ret == -ETIME && timeout);
3017
3018 out:
3019 mutex_unlock(&smu->message_lock);
3020
3021 if (ret)
3022 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
3023 ret);
3024
3025 return ret;
3026 }
3027
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)3028 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
3029 struct smu_temperature_range *range)
3030 {
3031 struct amdgpu_device *adev = smu->adev;
3032 u32 aid_temp, xcd_temp, max_temp;
3033 u32 ccd_temp = 0;
3034 int ret;
3035
3036 if (amdgpu_sriov_vf(smu->adev))
3037 return 0;
3038
3039 if (!range)
3040 return -EINVAL;
3041
3042 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
3043 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
3044 return 0;
3045
3046 /* Get SOC Max operating temperature */
3047 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3048 PPSMC_AID_THM_TYPE, &aid_temp);
3049 if (ret)
3050 goto failed;
3051 if (adev->flags & AMD_IS_APU) {
3052 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3053 PPSMC_CCD_THM_TYPE, &ccd_temp);
3054 if (ret)
3055 goto failed;
3056 }
3057 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3058 PPSMC_XCD_THM_TYPE, &xcd_temp);
3059 if (ret)
3060 goto failed;
3061 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
3062 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3063
3064 /* Get HBM Max operating temperature */
3065 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3066 PPSMC_HBM_THM_TYPE, &max_temp);
3067 if (ret)
3068 goto failed;
3069 range->mem_emergency_max =
3070 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3071
3072 /* Get SOC thermal throttle limit */
3073 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3074 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
3075 &max_temp);
3076 if (ret)
3077 goto failed;
3078 range->hotspot_crit_max =
3079 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3080
3081 /* Get HBM thermal throttle limit */
3082 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3083 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
3084 &max_temp);
3085 if (ret)
3086 goto failed;
3087
3088 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3089
3090 failed:
3091 return ret;
3092 }
3093
smu_v13_0_6_mode1_reset(struct smu_context * smu)3094 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
3095 {
3096 struct amdgpu_device *adev = smu->adev;
3097 u32 fatal_err, param;
3098 int ret = 0;
3099
3100 fatal_err = 0;
3101 param = SMU_RESET_MODE_1;
3102
3103 /* fatal error triggered by ras, PMFW supports the flag */
3104 if (amdgpu_ras_get_fed_status(adev))
3105 fatal_err = 1;
3106
3107 param |= (fatal_err << 16);
3108 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3109 param, NULL);
3110
3111 if (!ret)
3112 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
3113
3114 return ret;
3115 }
3116
smu_v13_0_6_link_reset(struct smu_context * smu)3117 static int smu_v13_0_6_link_reset(struct smu_context *smu)
3118 {
3119 int ret = 0;
3120
3121 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3122 SMU_RESET_MODE_4, NULL);
3123 return ret;
3124 }
3125
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)3126 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
3127 {
3128 return true;
3129 }
3130
smu_v13_0_6_is_link_reset_supported(struct smu_context * smu)3131 static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu)
3132 {
3133 struct amdgpu_device *adev = smu->adev;
3134 int var = (adev->pdev->device & 0xF);
3135
3136 if (var == 0x0 || var == 0x1 || var == 0x3)
3137 return true;
3138
3139 return false;
3140 }
3141
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)3142 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
3143 uint32_t size)
3144 {
3145 int ret = 0;
3146
3147 /* message SMU to update the bad page number on SMUBUS */
3148 ret = smu_cmn_send_smc_msg_with_param(
3149 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
3150 if (ret)
3151 dev_err(smu->adev->dev,
3152 "[%s] failed to message SMU to update HBM bad pages number\n",
3153 __func__);
3154
3155 return ret;
3156 }
3157
smu_v13_0_6_send_rma_reason(struct smu_context * smu)3158 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
3159 {
3160 int ret;
3161
3162 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
3163 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
3164 return 0;
3165
3166 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
3167 if (ret)
3168 dev_err(smu->adev->dev,
3169 "[%s] failed to send BadPageThreshold event to SMU\n",
3170 __func__);
3171
3172 return ret;
3173 }
3174
3175 /**
3176 * smu_v13_0_6_reset_sdma_is_supported - Check if SDMA reset is supported
3177 * @smu: smu_context pointer
3178 *
3179 * This function checks if the SMU supports resetting the SDMA engine.
3180 * It returns false if the capability is not supported.
3181 */
smu_v13_0_6_reset_sdma_is_supported(struct smu_context * smu)3182 static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
3183 {
3184 bool ret = true;
3185
3186 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
3187 dev_info(smu->adev->dev,
3188 "SDMA reset capability is not supported\n");
3189 ret = false;
3190 }
3191
3192 return ret;
3193 }
3194
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)3195 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
3196 {
3197 int ret = 0;
3198
3199 if (!smu_v13_0_6_reset_sdma_is_supported(smu))
3200 return -EOPNOTSUPP;
3201
3202 ret = smu_cmn_send_smc_msg_with_param(smu,
3203 SMU_MSG_ResetSDMA, inst_mask, NULL);
3204 if (ret)
3205 dev_err(smu->adev->dev,
3206 "failed to send ResetSDMA event with mask 0x%x\n",
3207 inst_mask);
3208
3209 return ret;
3210 }
3211
smu_v13_0_6_reset_vcn_is_supported(struct smu_context * smu)3212 static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu)
3213 {
3214 return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET));
3215 }
3216
smu_v13_0_6_reset_vcn(struct smu_context * smu,uint32_t inst_mask)3217 static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
3218 {
3219 int ret = 0;
3220
3221 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ResetVCN, inst_mask, NULL);
3222 if (ret)
3223 dev_err(smu->adev->dev,
3224 "failed to send ResetVCN event with mask 0x%x\n",
3225 inst_mask);
3226 return ret;
3227 }
3228
3229
smu_v13_0_6_post_init(struct smu_context * smu)3230 static int smu_v13_0_6_post_init(struct smu_context *smu)
3231 {
3232 if (smu_v13_0_6_is_link_reset_supported(smu))
3233 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET);
3234
3235 if (smu_v13_0_6_reset_sdma_is_supported(smu))
3236 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET);
3237
3238 if (smu_v13_0_6_reset_vcn_is_supported(smu))
3239 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET);
3240
3241 return 0;
3242 }
3243
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3244 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3245 {
3246 struct smu_context *smu = adev->powerplay.pp_handle;
3247
3248 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3249 }
3250
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)3251 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
3252 {
3253 uint32_t msg;
3254 int ret;
3255
3256 if (!count)
3257 return -EINVAL;
3258
3259 switch (type) {
3260 case AMDGPU_MCA_ERROR_TYPE_UE:
3261 msg = SMU_MSG_QueryValidMcaCount;
3262 break;
3263 case AMDGPU_MCA_ERROR_TYPE_CE:
3264 msg = SMU_MSG_QueryValidMcaCeCount;
3265 break;
3266 default:
3267 return -EINVAL;
3268 }
3269
3270 ret = smu_cmn_send_smc_msg(smu, msg, count);
3271 if (ret) {
3272 *count = 0;
3273 return ret;
3274 }
3275
3276 return 0;
3277 }
3278
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)3279 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3280 int idx, int offset, uint32_t *val)
3281 {
3282 uint32_t msg, param;
3283
3284 switch (type) {
3285 case AMDGPU_MCA_ERROR_TYPE_UE:
3286 msg = SMU_MSG_McaBankDumpDW;
3287 break;
3288 case AMDGPU_MCA_ERROR_TYPE_CE:
3289 msg = SMU_MSG_McaBankCeDumpDW;
3290 break;
3291 default:
3292 return -EINVAL;
3293 }
3294
3295 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3296
3297 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
3298 }
3299
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)3300 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3301 int idx, int offset, uint32_t *val, int count)
3302 {
3303 int ret, i;
3304
3305 if (!val)
3306 return -EINVAL;
3307
3308 for (i = 0; i < count; i++) {
3309 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
3310 if (ret)
3311 return ret;
3312 }
3313
3314 return 0;
3315 }
3316
3317 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
3318 MCA_BANK_IPID(UMC, 0x96, 0x0),
3319 MCA_BANK_IPID(SMU, 0x01, 0x1),
3320 MCA_BANK_IPID(MP5, 0x01, 0x2),
3321 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
3322 };
3323
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)3324 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
3325 {
3326 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
3327 u32 instidhi, instid;
3328
3329 /* NOTE: All MCA IPID register share the same format,
3330 * so the driver can share the MCMP1 register header file.
3331 * */
3332
3333 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
3334 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
3335
3336 /*
3337 * Unfied DieID Format: SAASS. A:AID, S:Socket.
3338 * Unfied DieID[4] = InstanceId[0]
3339 * Unfied DieID[0:3] = InstanceIdHi[0:3]
3340 */
3341 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
3342 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
3343 info->aid = ((instidhi >> 2) & 0x03);
3344 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
3345 }
3346
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)3347 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3348 int idx, int reg_idx, uint64_t *val)
3349 {
3350 struct smu_context *smu = adev->powerplay.pp_handle;
3351 uint32_t data[2] = {0, 0};
3352 int ret;
3353
3354 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3355 return -EINVAL;
3356
3357 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3358 if (ret)
3359 return ret;
3360
3361 *val = (uint64_t)data[1] << 32 | data[0];
3362
3363 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3364 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3365
3366 return 0;
3367 }
3368
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3369 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3370 int idx, struct mca_bank_entry *entry)
3371 {
3372 int i, ret;
3373
3374 /* NOTE: populated all mca register by default */
3375 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3376 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3377 if (ret)
3378 return ret;
3379 }
3380
3381 entry->idx = idx;
3382 entry->type = type;
3383
3384 mca_bank_entry_info_decode(entry, &entry->info);
3385
3386 return 0;
3387 }
3388
mca_decode_ipid_to_hwip(uint64_t val)3389 static int mca_decode_ipid_to_hwip(uint64_t val)
3390 {
3391 const struct mca_bank_ipid *ipid;
3392 uint16_t hwid, mcatype;
3393 int i;
3394
3395 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3396 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3397
3398 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3399 ipid = &smu_v13_0_6_mca_ipid_table[i];
3400
3401 if (!ipid->hwid)
3402 continue;
3403
3404 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3405 return i;
3406 }
3407
3408 return AMDGPU_MCA_IP_UNKNOW;
3409 }
3410
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3411 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3412 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3413 {
3414 uint64_t status0;
3415 uint32_t ext_error_code;
3416 uint32_t odecc_err_cnt;
3417
3418 status0 = entry->regs[MCA_REG_IDX_STATUS];
3419 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3420 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3421
3422 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3423 *count = 0;
3424 return 0;
3425 }
3426
3427 if (umc_v12_0_is_deferred_error(adev, status0) ||
3428 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3429 umc_v12_0_is_correctable_error(adev, status0))
3430 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3431
3432 amdgpu_umc_update_ecc_status(adev,
3433 entry->regs[MCA_REG_IDX_STATUS],
3434 entry->regs[MCA_REG_IDX_IPID],
3435 entry->regs[MCA_REG_IDX_ADDR]);
3436
3437 return 0;
3438 }
3439
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3440 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3441 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3442 uint32_t *count)
3443 {
3444 u32 ext_error_code;
3445 u32 err_cnt;
3446
3447 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3448 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3449
3450 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3451 (ext_error_code == 0 || ext_error_code == 9))
3452 *count = err_cnt;
3453 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3454 *count = err_cnt;
3455
3456 return 0;
3457 }
3458
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3459 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3460 uint32_t errcode)
3461 {
3462 int i;
3463
3464 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3465 return true;
3466
3467 for (i = 0; i < mca_ras->err_code_count; i++) {
3468 if (errcode == mca_ras->err_code_array[i])
3469 return true;
3470 }
3471
3472 return false;
3473 }
3474
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3475 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3476 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3477 {
3478 uint64_t status0, misc0;
3479
3480 status0 = entry->regs[MCA_REG_IDX_STATUS];
3481 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3482 *count = 0;
3483 return 0;
3484 }
3485
3486 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3487 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3488 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3489 *count = 1;
3490 return 0;
3491 } else {
3492 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3493 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3494 }
3495
3496 return 0;
3497 }
3498
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3499 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3500 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3501 {
3502 uint64_t status0, misc0;
3503
3504 status0 = entry->regs[MCA_REG_IDX_STATUS];
3505 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3506 *count = 0;
3507 return 0;
3508 }
3509
3510 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3511 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3512 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3513 if (count)
3514 *count = 1;
3515 return 0;
3516 }
3517
3518 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3519 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3520
3521 return 0;
3522 }
3523
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3524 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3525 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3526 {
3527 uint32_t instlo;
3528
3529 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3530 instlo &= GENMASK(31, 1);
3531 switch (instlo) {
3532 case 0x36430400: /* SMNAID XCD 0 */
3533 case 0x38430400: /* SMNAID XCD 1 */
3534 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3535 return true;
3536 default:
3537 return false;
3538 }
3539
3540 return false;
3541 };
3542
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3543 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3544 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3545 {
3546 struct smu_context *smu = adev->powerplay.pp_handle;
3547 uint32_t errcode, instlo;
3548
3549 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3550 instlo &= GENMASK(31, 1);
3551 if (instlo != 0x03b30400)
3552 return false;
3553
3554 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3555 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3556 errcode &= 0xff;
3557 } else {
3558 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3559 }
3560
3561 return mca_smu_check_error_code(adev, mca_ras, errcode);
3562 }
3563
3564 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3565 static int mmhub_err_codes[] = {
3566 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3567 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3568 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3569 };
3570
3571 static int vcn_err_codes[] = {
3572 CODE_VIDD, CODE_VIDV,
3573 };
3574 static int jpeg_err_codes[] = {
3575 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3576 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3577 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3578 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3579 };
3580
3581 static const struct mca_ras_info mca_ras_table[] = {
3582 {
3583 .blkid = AMDGPU_RAS_BLOCK__UMC,
3584 .ip = AMDGPU_MCA_IP_UMC,
3585 .get_err_count = mca_umc_mca_get_err_count,
3586 }, {
3587 .blkid = AMDGPU_RAS_BLOCK__GFX,
3588 .ip = AMDGPU_MCA_IP_SMU,
3589 .get_err_count = mca_gfx_mca_get_err_count,
3590 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3591 }, {
3592 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3593 .ip = AMDGPU_MCA_IP_SMU,
3594 .err_code_array = sdma_err_codes,
3595 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3596 .get_err_count = mca_smu_mca_get_err_count,
3597 .bank_is_valid = mca_smu_bank_is_valid,
3598 }, {
3599 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3600 .ip = AMDGPU_MCA_IP_SMU,
3601 .err_code_array = mmhub_err_codes,
3602 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3603 .get_err_count = mca_smu_mca_get_err_count,
3604 .bank_is_valid = mca_smu_bank_is_valid,
3605 }, {
3606 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3607 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3608 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3609 }, {
3610 .blkid = AMDGPU_RAS_BLOCK__VCN,
3611 .ip = AMDGPU_MCA_IP_SMU,
3612 .err_code_array = vcn_err_codes,
3613 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3614 .get_err_count = mca_smu_mca_get_err_count,
3615 .bank_is_valid = mca_smu_bank_is_valid,
3616 }, {
3617 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3618 .ip = AMDGPU_MCA_IP_SMU,
3619 .err_code_array = jpeg_err_codes,
3620 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3621 .get_err_count = mca_smu_mca_get_err_count,
3622 .bank_is_valid = mca_smu_bank_is_valid,
3623 },
3624 };
3625
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3626 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3627 {
3628 int i;
3629
3630 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3631 if (mca_ras_table[i].blkid == blkid)
3632 return &mca_ras_table[i];
3633 }
3634
3635 return NULL;
3636 }
3637
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3638 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3639 {
3640 struct smu_context *smu = adev->powerplay.pp_handle;
3641 int ret;
3642
3643 switch (type) {
3644 case AMDGPU_MCA_ERROR_TYPE_UE:
3645 case AMDGPU_MCA_ERROR_TYPE_CE:
3646 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3647 break;
3648 default:
3649 ret = -EINVAL;
3650 break;
3651 }
3652
3653 return ret;
3654 }
3655
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3656 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3657 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3658 {
3659 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3660 return false;
3661
3662 if (mca_ras->bank_is_valid)
3663 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3664
3665 return true;
3666 }
3667
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3668 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3669 struct mca_bank_entry *entry, uint32_t *count)
3670 {
3671 const struct mca_ras_info *mca_ras;
3672
3673 if (!entry || !count)
3674 return -EINVAL;
3675
3676 mca_ras = mca_get_mca_ras_info(adev, blk);
3677 if (!mca_ras)
3678 return -EOPNOTSUPP;
3679
3680 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3681 *count = 0;
3682 return 0;
3683 }
3684
3685 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3686 }
3687
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3688 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3689 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3690 {
3691 return mca_get_mca_entry(adev, type, idx, entry);
3692 }
3693
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3694 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3695 enum amdgpu_mca_error_type type, uint32_t *count)
3696 {
3697 return mca_get_valid_mca_count(adev, type, count);
3698 }
3699
3700 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3701 .max_ue_count = 12,
3702 .max_ce_count = 12,
3703 .mca_set_debug_mode = mca_smu_set_debug_mode,
3704 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3705 .mca_get_mca_entry = mca_smu_get_mca_entry,
3706 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3707 };
3708
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3709 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3710 {
3711 struct smu_context *smu = adev->powerplay.pp_handle;
3712
3713 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3714 }
3715
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3716 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3717 {
3718 uint32_t msg;
3719 int ret;
3720
3721 if (!count)
3722 return -EINVAL;
3723
3724 switch (type) {
3725 case ACA_SMU_TYPE_UE:
3726 msg = SMU_MSG_QueryValidMcaCount;
3727 break;
3728 case ACA_SMU_TYPE_CE:
3729 msg = SMU_MSG_QueryValidMcaCeCount;
3730 break;
3731 default:
3732 return -EINVAL;
3733 }
3734
3735 ret = smu_cmn_send_smc_msg(smu, msg, count);
3736 if (ret) {
3737 *count = 0;
3738 return ret;
3739 }
3740
3741 return 0;
3742 }
3743
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3744 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3745 enum aca_smu_type type, u32 *count)
3746 {
3747 struct smu_context *smu = adev->powerplay.pp_handle;
3748 int ret;
3749
3750 switch (type) {
3751 case ACA_SMU_TYPE_UE:
3752 case ACA_SMU_TYPE_CE:
3753 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3754 break;
3755 default:
3756 ret = -EINVAL;
3757 break;
3758 }
3759
3760 return ret;
3761 }
3762
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3763 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3764 int idx, int offset, u32 *val)
3765 {
3766 uint32_t msg, param;
3767
3768 switch (type) {
3769 case ACA_SMU_TYPE_UE:
3770 msg = SMU_MSG_McaBankDumpDW;
3771 break;
3772 case ACA_SMU_TYPE_CE:
3773 msg = SMU_MSG_McaBankCeDumpDW;
3774 break;
3775 default:
3776 return -EINVAL;
3777 }
3778
3779 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3780
3781 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3782 }
3783
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3784 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3785 int idx, int offset, u32 *val, int count)
3786 {
3787 int ret, i;
3788
3789 if (!val)
3790 return -EINVAL;
3791
3792 for (i = 0; i < count; i++) {
3793 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3794 if (ret)
3795 return ret;
3796 }
3797
3798 return 0;
3799 }
3800
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3801 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3802 int idx, int reg_idx, u64 *val)
3803 {
3804 struct smu_context *smu = adev->powerplay.pp_handle;
3805 u32 data[2] = {0, 0};
3806 int ret;
3807
3808 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3809 return -EINVAL;
3810
3811 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3812 if (ret)
3813 return ret;
3814
3815 *val = (u64)data[1] << 32 | data[0];
3816
3817 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3818 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3819
3820 return 0;
3821 }
3822
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3823 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3824 enum aca_smu_type type, int idx, struct aca_bank *bank)
3825 {
3826 int i, ret, count;
3827
3828 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3829 for (i = 0; i < count; i++) {
3830 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3831 if (ret)
3832 return ret;
3833 }
3834
3835 return 0;
3836 }
3837
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3838 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3839 {
3840 struct smu_context *smu = adev->powerplay.pp_handle;
3841 int error_code;
3842
3843 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3844 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3845 else
3846 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3847
3848 return error_code & 0xff;
3849 }
3850
3851 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3852 .max_ue_bank_count = 12,
3853 .max_ce_bank_count = 12,
3854 .set_debug_mode = aca_smu_set_debug_mode,
3855 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3856 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3857 .parse_error_code = aca_smu_parse_error_code,
3858 };
3859
smu_v13_0_6_set_temp_funcs(struct smu_context * smu)3860 static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu)
3861 {
3862 smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)
3863 == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL;
3864 }
3865
3866 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3867 /* init dpm */
3868 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3869 /* dpm/clk tables */
3870 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3871 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3872 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3873 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3874 .read_sensor = smu_v13_0_6_read_sensor,
3875 .set_performance_level = smu_v13_0_6_set_performance_level,
3876 .get_power_limit = smu_v13_0_6_get_power_limit,
3877 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3878 .get_unique_id = smu_v13_0_6_get_unique_id,
3879 .init_microcode = smu_v13_0_6_init_microcode,
3880 .fini_microcode = smu_v13_0_fini_microcode,
3881 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3882 .fini_smc_tables = smu_v13_0_6_fini_smc_tables,
3883 .init_power = smu_v13_0_init_power,
3884 .fini_power = smu_v13_0_fini_power,
3885 .check_fw_status = smu_v13_0_6_check_fw_status,
3886 /* pptable related */
3887 .check_fw_version = smu_v13_0_6_check_fw_version,
3888 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3889 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3890 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3891 .system_features_control = smu_v13_0_6_system_features_control,
3892 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3893 .send_smc_msg = smu_cmn_send_smc_msg,
3894 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3895 .feature_is_enabled = smu_cmn_feature_is_enabled,
3896 .set_power_limit = smu_v13_0_6_set_power_limit,
3897 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3898 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3899 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3900 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3901 .setup_pptable = smu_v13_0_6_setup_pptable,
3902 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3903 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3904 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3905 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3906 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3907 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3908 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3909 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3910 .get_xcp_metrics = smu_v13_0_6_get_xcp_metrics,
3911 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3912 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3913 .mode1_reset = smu_v13_0_6_mode1_reset,
3914 .mode2_reset = smu_v13_0_6_mode2_reset,
3915 .link_reset = smu_v13_0_6_link_reset,
3916 .wait_for_event = smu_v13_0_wait_for_event,
3917 .i2c_init = smu_v13_0_6_i2c_control_init,
3918 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3919 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3920 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3921 .reset_sdma = smu_v13_0_6_reset_sdma,
3922 .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
3923 .post_init = smu_v13_0_6_post_init,
3924 };
3925
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3926 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3927 {
3928 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3929 smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3930 smu_v13_0_12_message_map : smu_v13_0_6_message_map;
3931 smu->clock_map = smu_v13_0_6_clk_map;
3932 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3933 smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
3934 smu->table_map = smu_v13_0_6_table_map;
3935 smu->smc_driver_if_version = SMU_IGNORE_IF_VERSION;
3936 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3937 smu_v13_0_set_smu_mailbox_registers(smu);
3938 smu_v13_0_6_set_temp_funcs(smu);
3939 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3940 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3941 }
3942
3943