1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This file is part of wl1271
4 *
5 * Copyright (C) 2008-2010 Nokia Corporation
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10
11 #include <linux/err.h>
12
13 #include "../wlcore/wlcore.h"
14 #include "../wlcore/debug.h"
15 #include "../wlcore/io.h"
16 #include "../wlcore/acx.h"
17 #include "../wlcore/tx.h"
18 #include "../wlcore/rx.h"
19 #include "../wlcore/boot.h"
20
21 #include "wl12xx.h"
22 #include "reg.h"
23 #include "cmd.h"
24 #include "acx.h"
25 #include "scan.h"
26 #include "event.h"
27 #include "debugfs.h"
28 #include "conf.h"
29
30 static char *fref_param;
31 static char *tcxo_param;
32
33 static struct wlcore_conf wl12xx_conf = {
34 .sg = {
35 .params = {
36 [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
37 [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
38 [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
39 [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
40 [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
41 [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
42 [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
43 [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
44 [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
45 [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
46 [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
47 [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
48 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
49 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
50 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
51 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
52 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
53 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
54 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
55 [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
56 [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
57 [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
58 [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
59 [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
60 [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
61 [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
62 /* active scan params */
63 [WL12XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
64 [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
65 [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
66 /* passive scan params */
67 [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_BR] = 800,
68 [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_EDR] = 200,
69 [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_HV3] = 200,
70 /* passive scan in dual antenna params */
71 [WL12XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
72 [WL12XX_CONF_SG_BCN_HV3_COLL_THR_IN_PASSIVE_SCAN] = 0,
73 [WL12XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
74 /* general params */
75 [WL12XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
76 [WL12XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
77 [WL12XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
78 [WL12XX_CONF_SG_DHCP_TIME] = 5000,
79 [WL12XX_CONF_SG_RXT] = 1200,
80 [WL12XX_CONF_SG_TXT] = 1000,
81 [WL12XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
82 [WL12XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
83 [WL12XX_CONF_SG_HV3_MAX_SERVED] = 6,
84 [WL12XX_CONF_SG_PS_POLL_TIMEOUT] = 10,
85 [WL12XX_CONF_SG_UPSD_TIMEOUT] = 10,
86 [WL12XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
87 [WL12XX_CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
88 [WL12XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
89 /* AP params */
90 [WL12XX_CONF_AP_BEACON_MISS_TX] = 3,
91 [WL12XX_CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
92 [WL12XX_CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
93 [WL12XX_CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
94 [WL12XX_CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
95 [WL12XX_CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
96 /* CTS Diluting params */
97 [WL12XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
98 [WL12XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
99 },
100 .state = CONF_SG_PROTECTIVE,
101 },
102 .rx = {
103 .rx_msdu_life_time = 512000,
104 .packet_detection_threshold = 0,
105 .ps_poll_timeout = 15,
106 .upsd_timeout = 15,
107 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
108 .rx_cca_threshold = 0,
109 .irq_blk_threshold = 0xFFFF,
110 .irq_pkt_threshold = 0,
111 .irq_timeout = 600,
112 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
113 },
114 .tx = {
115 .tx_energy_detection = 0,
116 .sta_rc_conf = {
117 .enabled_rates = 0,
118 .short_retry_limit = 10,
119 .long_retry_limit = 10,
120 .aflags = 0,
121 },
122 .ac_conf_count = 4,
123 .ac_conf = {
124 [CONF_TX_AC_BE] = {
125 .ac = CONF_TX_AC_BE,
126 .cw_min = 15,
127 .cw_max = 63,
128 .aifsn = 3,
129 .tx_op_limit = 0,
130 },
131 [CONF_TX_AC_BK] = {
132 .ac = CONF_TX_AC_BK,
133 .cw_min = 15,
134 .cw_max = 63,
135 .aifsn = 7,
136 .tx_op_limit = 0,
137 },
138 [CONF_TX_AC_VI] = {
139 .ac = CONF_TX_AC_VI,
140 .cw_min = 15,
141 .cw_max = 63,
142 .aifsn = CONF_TX_AIFS_PIFS,
143 .tx_op_limit = 3008,
144 },
145 [CONF_TX_AC_VO] = {
146 .ac = CONF_TX_AC_VO,
147 .cw_min = 15,
148 .cw_max = 63,
149 .aifsn = CONF_TX_AIFS_PIFS,
150 .tx_op_limit = 1504,
151 },
152 },
153 .max_tx_retries = 100,
154 .ap_aging_period = 300,
155 .tid_conf_count = 4,
156 .tid_conf = {
157 [CONF_TX_AC_BE] = {
158 .queue_id = CONF_TX_AC_BE,
159 .channel_type = CONF_CHANNEL_TYPE_EDCF,
160 .tsid = CONF_TX_AC_BE,
161 .ps_scheme = CONF_PS_SCHEME_LEGACY,
162 .ack_policy = CONF_ACK_POLICY_LEGACY,
163 .apsd_conf = {0, 0},
164 },
165 [CONF_TX_AC_BK] = {
166 .queue_id = CONF_TX_AC_BK,
167 .channel_type = CONF_CHANNEL_TYPE_EDCF,
168 .tsid = CONF_TX_AC_BK,
169 .ps_scheme = CONF_PS_SCHEME_LEGACY,
170 .ack_policy = CONF_ACK_POLICY_LEGACY,
171 .apsd_conf = {0, 0},
172 },
173 [CONF_TX_AC_VI] = {
174 .queue_id = CONF_TX_AC_VI,
175 .channel_type = CONF_CHANNEL_TYPE_EDCF,
176 .tsid = CONF_TX_AC_VI,
177 .ps_scheme = CONF_PS_SCHEME_LEGACY,
178 .ack_policy = CONF_ACK_POLICY_LEGACY,
179 .apsd_conf = {0, 0},
180 },
181 [CONF_TX_AC_VO] = {
182 .queue_id = CONF_TX_AC_VO,
183 .channel_type = CONF_CHANNEL_TYPE_EDCF,
184 .tsid = CONF_TX_AC_VO,
185 .ps_scheme = CONF_PS_SCHEME_LEGACY,
186 .ack_policy = CONF_ACK_POLICY_LEGACY,
187 .apsd_conf = {0, 0},
188 },
189 },
190 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
191 .tx_compl_timeout = 700,
192 .tx_compl_threshold = 4,
193 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
194 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
195 .tmpl_short_retry_limit = 10,
196 .tmpl_long_retry_limit = 10,
197 .tx_watchdog_timeout = 5000,
198 .slow_link_thold = 3,
199 .fast_link_thold = 10,
200 },
201 .conn = {
202 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
203 .listen_interval = 1,
204 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
205 .suspend_listen_interval = 3,
206 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
207 .bcn_filt_ie_count = 3,
208 .bcn_filt_ie = {
209 [0] = {
210 .ie = WLAN_EID_CHANNEL_SWITCH,
211 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
212 },
213 [1] = {
214 .ie = WLAN_EID_HT_OPERATION,
215 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
216 },
217 [2] = {
218 .ie = WLAN_EID_ERP_INFO,
219 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
220 },
221 },
222 .synch_fail_thold = 12,
223 .bss_lose_timeout = 400,
224 .beacon_rx_timeout = 10000,
225 .broadcast_timeout = 20000,
226 .rx_broadcast_in_ps = 1,
227 .ps_poll_threshold = 10,
228 .bet_enable = CONF_BET_MODE_ENABLE,
229 .bet_max_consecutive = 50,
230 .psm_entry_retries = 8,
231 .psm_exit_retries = 16,
232 .psm_entry_nullfunc_retries = 3,
233 .dynamic_ps_timeout = 1500,
234 .forced_ps = false,
235 .keep_alive_interval = 55000,
236 .max_listen_interval = 20,
237 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
238 .suspend_rx_ba_activity = 0,
239 },
240 .itrim = {
241 .enable = false,
242 .timeout = 50000,
243 },
244 .pm_config = {
245 .host_clk_settling_time = 5000,
246 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
247 },
248 .roam_trigger = {
249 .trigger_pacing = 1,
250 .avg_weight_rssi_beacon = 20,
251 .avg_weight_rssi_data = 10,
252 .avg_weight_snr_beacon = 20,
253 .avg_weight_snr_data = 10,
254 },
255 .scan = {
256 .min_dwell_time_active = 7500,
257 .max_dwell_time_active = 30000,
258 .min_dwell_time_active_long = 25000,
259 .max_dwell_time_active_long = 50000,
260 .dwell_time_passive = 100000,
261 .dwell_time_dfs = 150000,
262 .num_probe_reqs = 2,
263 .split_scan_timeout = 50000,
264 },
265 .sched_scan = {
266 /*
267 * Values are in TU/1000 but since sched scan FW command
268 * params are in TUs rounding up may occur.
269 */
270 .base_dwell_time = 7500,
271 .max_dwell_time_delta = 22500,
272 /* based on 250bits per probe @1Mbps */
273 .dwell_time_delta_per_probe = 2000,
274 /* based on 250bits per probe @6Mbps (plus a bit more) */
275 .dwell_time_delta_per_probe_5 = 350,
276 .dwell_time_passive = 100000,
277 .dwell_time_dfs = 150000,
278 .num_probe_reqs = 2,
279 .rssi_threshold = -90,
280 .snr_threshold = 0,
281 },
282 .ht = {
283 .rx_ba_win_size = 8,
284 .tx_ba_win_size = 64,
285 .inactivity_timeout = 10000,
286 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
287 },
288 /*
289 * Memory config for wl127x chips is given in the
290 * wl12xx_default_priv_conf struct. The below configuration is
291 * for wl128x chips.
292 */
293 .mem = {
294 .num_stations = 1,
295 .ssid_profiles = 1,
296 .rx_block_num = 40,
297 .tx_min_block_num = 40,
298 .dynamic_memory = 1,
299 .min_req_tx_blocks = 45,
300 .min_req_rx_blocks = 22,
301 .tx_min = 27,
302 },
303 .fm_coex = {
304 .enable = true,
305 .swallow_period = 5,
306 .n_divider_fref_set_1 = 0xff, /* default */
307 .n_divider_fref_set_2 = 12,
308 .m_divider_fref_set_1 = 0xffff,
309 .m_divider_fref_set_2 = 148, /* default */
310 .coex_pll_stabilization_time = 0xffffffff, /* default */
311 .ldo_stabilization_time = 0xffff, /* default */
312 .fm_disturbed_band_margin = 0xff, /* default */
313 .swallow_clk_diff = 0xff, /* default */
314 },
315 .rx_streaming = {
316 .duration = 150,
317 .queues = 0x1,
318 .interval = 20,
319 .always = 0,
320 },
321 .fwlog = {
322 .mode = WL12XX_FWLOG_CONTINUOUS,
323 .mem_blocks = 2,
324 .severity = 0,
325 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
326 .output = WL12XX_FWLOG_OUTPUT_DBG_PINS,
327 .threshold = 0,
328 },
329 .rate = {
330 .rate_retry_score = 32000,
331 .per_add = 8192,
332 .per_th1 = 2048,
333 .per_th2 = 4096,
334 .max_per = 8100,
335 .inverse_curiosity_factor = 5,
336 .tx_fail_low_th = 4,
337 .tx_fail_high_th = 10,
338 .per_alpha_shift = 4,
339 .per_add_shift = 13,
340 .per_beta1_shift = 10,
341 .per_beta2_shift = 8,
342 .rate_check_up = 2,
343 .rate_check_down = 12,
344 .rate_retry_policy = {
345 0x00, 0x00, 0x00, 0x00, 0x00,
346 0x00, 0x00, 0x00, 0x00, 0x00,
347 0x00, 0x00, 0x00,
348 },
349 },
350 .hangover = {
351 .recover_time = 0,
352 .hangover_period = 20,
353 .dynamic_mode = 1,
354 .early_termination_mode = 1,
355 .max_period = 20,
356 .min_period = 1,
357 .increase_delta = 1,
358 .decrease_delta = 2,
359 .quiet_time = 4,
360 .increase_time = 1,
361 .window_size = 16,
362 },
363 .recovery = {
364 .bug_on_recovery = 0,
365 .no_recovery = 0,
366 },
367 };
368
369 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
370 .rf = {
371 .tx_per_channel_power_compensation_2 = {
372 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
373 },
374 .tx_per_channel_power_compensation_5 = {
375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
378 },
379 },
380 .mem_wl127x = {
381 .num_stations = 1,
382 .ssid_profiles = 1,
383 .rx_block_num = 70,
384 .tx_min_block_num = 40,
385 .dynamic_memory = 1,
386 .min_req_tx_blocks = 100,
387 .min_req_rx_blocks = 22,
388 .tx_min = 27,
389 },
390
391 };
392
393 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
394 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
395 #define WL12XX_TX_HW_BLOCK_SIZE 252
396
397 static const u8 wl12xx_rate_to_idx_2ghz[] = {
398 /* MCS rates are used only with 11n */
399 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
400 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
401 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
402 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
403 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
404 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
405 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
406 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
407 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
408
409 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
410 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
411 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
412 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
413
414 /* TI-specific rate */
415 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
416
417 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
418 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
419 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
420 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
421 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
422 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
423 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
424 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
425 };
426
427 static const u8 wl12xx_rate_to_idx_5ghz[] = {
428 /* MCS rates are used only with 11n */
429 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
430 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
431 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
432 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
433 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
434 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
435 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
436 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
437 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
438
439 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
440 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
441 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
442 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
443
444 /* TI-specific rate */
445 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
446
447 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
448 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
449 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
450 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
451 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
452 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
453 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
454 CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
455 };
456
457 static const u8 *wl12xx_band_rate_to_idx[] = {
458 [NL80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
459 [NL80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
460 };
461
462 enum wl12xx_hw_rates {
463 WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
464 WL12XX_CONF_HW_RXTX_RATE_MCS7,
465 WL12XX_CONF_HW_RXTX_RATE_MCS6,
466 WL12XX_CONF_HW_RXTX_RATE_MCS5,
467 WL12XX_CONF_HW_RXTX_RATE_MCS4,
468 WL12XX_CONF_HW_RXTX_RATE_MCS3,
469 WL12XX_CONF_HW_RXTX_RATE_MCS2,
470 WL12XX_CONF_HW_RXTX_RATE_MCS1,
471 WL12XX_CONF_HW_RXTX_RATE_MCS0,
472 WL12XX_CONF_HW_RXTX_RATE_54,
473 WL12XX_CONF_HW_RXTX_RATE_48,
474 WL12XX_CONF_HW_RXTX_RATE_36,
475 WL12XX_CONF_HW_RXTX_RATE_24,
476 WL12XX_CONF_HW_RXTX_RATE_22,
477 WL12XX_CONF_HW_RXTX_RATE_18,
478 WL12XX_CONF_HW_RXTX_RATE_12,
479 WL12XX_CONF_HW_RXTX_RATE_11,
480 WL12XX_CONF_HW_RXTX_RATE_9,
481 WL12XX_CONF_HW_RXTX_RATE_6,
482 WL12XX_CONF_HW_RXTX_RATE_5_5,
483 WL12XX_CONF_HW_RXTX_RATE_2,
484 WL12XX_CONF_HW_RXTX_RATE_1,
485 WL12XX_CONF_HW_RXTX_RATE_MAX,
486 };
487
488 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
489 [PART_DOWN] = {
490 .mem = {
491 .start = 0x00000000,
492 .size = 0x000177c0
493 },
494 .reg = {
495 .start = REGISTERS_BASE,
496 .size = 0x00008800
497 },
498 .mem2 = {
499 .start = 0x00000000,
500 .size = 0x00000000
501 },
502 .mem3 = {
503 .start = 0x00000000,
504 .size = 0x00000000
505 },
506 },
507
508 [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
509 * partition here */
510 .mem = {
511 .start = 0x00040000,
512 .size = 0x00014fc0
513 },
514 .reg = {
515 .start = REGISTERS_BASE,
516 .size = 0x00008800
517 },
518 .mem2 = {
519 .start = 0x00000000,
520 .size = 0x00000000
521 },
522 .mem3 = {
523 .start = 0x00000000,
524 .size = 0x00000000
525 },
526 },
527
528 [PART_WORK] = {
529 .mem = {
530 .start = 0x00040000,
531 .size = 0x00014fc0
532 },
533 .reg = {
534 .start = REGISTERS_BASE,
535 .size = 0x0000a000
536 },
537 .mem2 = {
538 .start = 0x003004f8,
539 .size = 0x00000004
540 },
541 .mem3 = {
542 .start = 0x00000000,
543 .size = 0x00040404
544 },
545 },
546
547 [PART_DRPW] = {
548 .mem = {
549 .start = 0x00040000,
550 .size = 0x00014fc0
551 },
552 .reg = {
553 .start = DRPW_BASE,
554 .size = 0x00006000
555 },
556 .mem2 = {
557 .start = 0x00000000,
558 .size = 0x00000000
559 },
560 .mem3 = {
561 .start = 0x00000000,
562 .size = 0x00000000
563 }
564 }
565 };
566
567 static const int wl12xx_rtable[REG_TABLE_LEN] = {
568 [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
569 [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
570 [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
571 [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
572 [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
573 [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
574 [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
575 [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
576 [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
577 [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
578
579 /* data access memory addresses, used with partition translation */
580 [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
581 [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
582
583 /* raw data access memory addresses */
584 [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
585 };
586
587 /* TODO: maybe move to a new header file? */
588 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
589 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
590 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
591
592 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
593 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
594 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
595
wl127x_prepare_read(struct wl1271 * wl,u32 rx_desc,u32 len)596 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
597 {
598 int ret;
599
600 if (wl->chip.id != CHIP_ID_128X_PG20) {
601 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
602 struct wl12xx_priv *priv = wl->priv;
603
604 /*
605 * Choose the block we want to read
606 * For aggregated packets, only the first memory block
607 * should be retrieved. The FW takes care of the rest.
608 */
609 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
610
611 priv->rx_mem_addr->addr = (mem_block << 8) +
612 le32_to_cpu(wl_mem_map->packet_memory_pool_start);
613
614 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
615
616 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
617 sizeof(*priv->rx_mem_addr), false);
618 if (ret < 0)
619 return ret;
620 }
621
622 return 0;
623 }
624
wl12xx_identify_chip(struct wl1271 * wl)625 static int wl12xx_identify_chip(struct wl1271 *wl)
626 {
627 int ret = 0;
628
629 switch (wl->chip.id) {
630 case CHIP_ID_127X_PG10:
631 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
632 wl->chip.id);
633
634 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
635 WLCORE_QUIRK_DUAL_PROBE_TMPL |
636 WLCORE_QUIRK_TKIP_HEADER_SPACE |
637 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
638 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
639 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
640 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
641 sizeof(wl->conf.mem));
642
643 /* read data preparation is only needed by wl127x */
644 wl->ops->prepare_read = wl127x_prepare_read;
645
646 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
647 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
648 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
649 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
650 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
651 break;
652
653 case CHIP_ID_127X_PG20:
654 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
655 wl->chip.id);
656
657 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
658 WLCORE_QUIRK_DUAL_PROBE_TMPL |
659 WLCORE_QUIRK_TKIP_HEADER_SPACE |
660 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
661 wl->plt_fw_name = WL127X_PLT_FW_NAME;
662 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
663 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
664 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
665 sizeof(wl->conf.mem));
666
667 /* read data preparation is only needed by wl127x */
668 wl->ops->prepare_read = wl127x_prepare_read;
669
670 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
671 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
672 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
673 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
674 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
675 break;
676
677 case CHIP_ID_128X_PG20:
678 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
679 wl->chip.id);
680 wl->plt_fw_name = WL128X_PLT_FW_NAME;
681 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
682 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
683
684 /* wl128x requires TX blocksize alignment */
685 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
686 WLCORE_QUIRK_DUAL_PROBE_TMPL |
687 WLCORE_QUIRK_TKIP_HEADER_SPACE |
688 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
689
690 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
691 WL128X_IFTYPE_SR_VER, WL128X_MAJOR_SR_VER,
692 WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
693 WL128X_IFTYPE_MR_VER, WL128X_MAJOR_MR_VER,
694 WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
695 break;
696 case CHIP_ID_128X_PG10:
697 default:
698 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
699 ret = -ENODEV;
700 goto out;
701 }
702
703 wl->fw_mem_block_size = 256;
704 wl->fwlog_end = 0x2000000;
705
706 /* common settings */
707 wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
708 wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
709 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
710 wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
711 wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
712 wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
713 out:
714 return ret;
715 }
716
wl12xx_top_reg_write(struct wl1271 * wl,int addr,u16 val)717 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
718 u16 val)
719 {
720 int ret;
721
722 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
723 addr = (addr >> 1) + 0x30000;
724 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
725 if (ret < 0)
726 goto out;
727
728 /* write value to OCP_POR_WDATA */
729 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
730 if (ret < 0)
731 goto out;
732
733 /* write 1 to OCP_CMD */
734 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
735 if (ret < 0)
736 goto out;
737
738 out:
739 return ret;
740 }
741
wl12xx_top_reg_read(struct wl1271 * wl,int addr,u16 * out)742 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
743 u16 *out)
744 {
745 u32 val;
746 int timeout = OCP_CMD_LOOP;
747 int ret;
748
749 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
750 addr = (addr >> 1) + 0x30000;
751 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
752 if (ret < 0)
753 return ret;
754
755 /* write 2 to OCP_CMD */
756 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
757 if (ret < 0)
758 return ret;
759
760 /* poll for data ready */
761 do {
762 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
763 if (ret < 0)
764 return ret;
765 } while (!(val & OCP_READY_MASK) && --timeout);
766
767 if (!timeout) {
768 wl1271_warning("Top register access timed out.");
769 return -ETIMEDOUT;
770 }
771
772 /* check data status and return if OK */
773 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
774 wl1271_warning("Top register access returned error.");
775 return -EIO;
776 }
777
778 if (out)
779 *out = val & 0xffff;
780
781 return 0;
782 }
783
wl128x_switch_tcxo_to_fref(struct wl1271 * wl)784 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
785 {
786 u16 spare_reg;
787 int ret;
788
789 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
790 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
791 if (ret < 0)
792 return ret;
793
794 if (spare_reg == 0xFFFF)
795 return -EFAULT;
796 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
797 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
798 if (ret < 0)
799 return ret;
800
801 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
802 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
803 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
804 if (ret < 0)
805 return ret;
806
807 /* Delay execution for 15msec, to let the HW settle */
808 mdelay(15);
809
810 return 0;
811 }
812
wl128x_is_tcxo_valid(struct wl1271 * wl)813 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
814 {
815 u16 tcxo_detection;
816 int ret;
817
818 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
819 if (ret < 0)
820 return false;
821
822 if (tcxo_detection & TCXO_DET_FAILED)
823 return false;
824
825 return true;
826 }
827
wl128x_is_fref_valid(struct wl1271 * wl)828 static bool wl128x_is_fref_valid(struct wl1271 *wl)
829 {
830 u16 fref_detection;
831 int ret;
832
833 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
834 if (ret < 0)
835 return false;
836
837 if (fref_detection & FREF_CLK_DETECT_FAIL)
838 return false;
839
840 return true;
841 }
842
wl128x_manually_configure_mcs_pll(struct wl1271 * wl)843 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
844 {
845 int ret;
846
847 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
848 if (ret < 0)
849 goto out;
850
851 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
852 if (ret < 0)
853 goto out;
854
855 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
856 MCS_PLL_CONFIG_REG_VAL);
857
858 out:
859 return ret;
860 }
861
wl128x_configure_mcs_pll(struct wl1271 * wl,int clk)862 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
863 {
864 u16 spare_reg;
865 u16 pll_config;
866 u8 input_freq;
867 struct wl12xx_priv *priv = wl->priv;
868 int ret;
869
870 /* Mask bits [3:1] in the sys_clk_cfg register */
871 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
872 if (ret < 0)
873 return ret;
874
875 if (spare_reg == 0xFFFF)
876 return -EFAULT;
877 spare_reg |= BIT(2);
878 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
879 if (ret < 0)
880 return ret;
881
882 /* Handle special cases of the TCXO clock */
883 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
884 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
885 return wl128x_manually_configure_mcs_pll(wl);
886
887 /* Set the input frequency according to the selected clock source */
888 input_freq = (clk & 1) + 1;
889
890 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
891 if (ret < 0)
892 return ret;
893
894 if (pll_config == 0xFFFF)
895 return -EFAULT;
896 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
897 pll_config |= MCS_PLL_ENABLE_HP;
898 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
899
900 return ret;
901 }
902
903 /*
904 * WL128x has two clocks input - TCXO and FREF.
905 * TCXO is the main clock of the device, while FREF is used to sync
906 * between the GPS and the cellular modem.
907 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
908 * as the WLAN/BT main clock.
909 */
wl128x_boot_clk(struct wl1271 * wl,int * selected_clock)910 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
911 {
912 struct wl12xx_priv *priv = wl->priv;
913 u16 sys_clk_cfg;
914 int ret;
915
916 /* For XTAL-only modes, FREF will be used after switching from TCXO */
917 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
918 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
919 if (!wl128x_switch_tcxo_to_fref(wl))
920 return -EINVAL;
921 goto fref_clk;
922 }
923
924 /* Query the HW, to determine which clock source we should use */
925 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
926 if (ret < 0)
927 return ret;
928
929 if (sys_clk_cfg == 0xFFFF)
930 return -EINVAL;
931 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
932 goto fref_clk;
933
934 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
935 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
936 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
937 if (!wl128x_switch_tcxo_to_fref(wl))
938 return -EINVAL;
939 goto fref_clk;
940 }
941
942 /* TCXO clock is selected */
943 if (!wl128x_is_tcxo_valid(wl))
944 return -EINVAL;
945 *selected_clock = priv->tcxo_clock;
946 goto config_mcs_pll;
947
948 fref_clk:
949 /* FREF clock is selected */
950 if (!wl128x_is_fref_valid(wl))
951 return -EINVAL;
952 *selected_clock = priv->ref_clock;
953
954 config_mcs_pll:
955 return wl128x_configure_mcs_pll(wl, *selected_clock);
956 }
957
wl127x_boot_clk(struct wl1271 * wl)958 static int wl127x_boot_clk(struct wl1271 *wl)
959 {
960 struct wl12xx_priv *priv = wl->priv;
961 u32 pause;
962 u32 clk;
963 int ret;
964
965 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
966 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
967
968 if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
969 priv->ref_clock == CONF_REF_CLK_38_4_E ||
970 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
971 /* ref clk: 19.2/38.4/38.4-XTAL */
972 clk = 0x3;
973 else if (priv->ref_clock == CONF_REF_CLK_26_E ||
974 priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
975 priv->ref_clock == CONF_REF_CLK_52_E)
976 /* ref clk: 26/52 */
977 clk = 0x5;
978 else
979 return -EINVAL;
980
981 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
982 u16 val;
983 /* Set clock type (open drain) */
984 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
985 if (ret < 0)
986 goto out;
987
988 val &= FREF_CLK_TYPE_BITS;
989 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
990 if (ret < 0)
991 goto out;
992
993 /* Set clock pull mode (no pull) */
994 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
995 if (ret < 0)
996 goto out;
997
998 val |= NO_PULL;
999 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1000 if (ret < 0)
1001 goto out;
1002 } else {
1003 u16 val;
1004 /* Set clock polarity */
1005 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1006 if (ret < 0)
1007 goto out;
1008
1009 val &= FREF_CLK_POLARITY_BITS;
1010 val |= CLK_REQ_OUTN_SEL;
1011 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1012 if (ret < 0)
1013 goto out;
1014 }
1015
1016 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1017 if (ret < 0)
1018 goto out;
1019
1020 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1021 if (ret < 0)
1022 goto out;
1023
1024 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1025
1026 pause &= ~(WU_COUNTER_PAUSE_VAL);
1027 pause |= WU_COUNTER_PAUSE_VAL;
1028 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1029
1030 out:
1031 return ret;
1032 }
1033
wl1271_boot_soft_reset(struct wl1271 * wl)1034 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1035 {
1036 unsigned long timeout;
1037 u32 boot_data;
1038 int ret = 0;
1039
1040 /* perform soft reset */
1041 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1042 if (ret < 0)
1043 goto out;
1044
1045 /* SOFT_RESET is self clearing */
1046 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1047 while (1) {
1048 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1049 if (ret < 0)
1050 goto out;
1051
1052 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1053 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1054 break;
1055
1056 if (time_after(jiffies, timeout)) {
1057 /* 1.2 check pWhalBus->uSelfClearTime if the
1058 * timeout was reached */
1059 wl1271_error("soft reset timeout");
1060 return -1;
1061 }
1062
1063 udelay(SOFT_RESET_STALL_TIME);
1064 }
1065
1066 /* disable Rx/Tx */
1067 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1068 if (ret < 0)
1069 goto out;
1070
1071 /* disable auto calibration on start*/
1072 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1073
1074 out:
1075 return ret;
1076 }
1077
wl12xx_pre_boot(struct wl1271 * wl)1078 static int wl12xx_pre_boot(struct wl1271 *wl)
1079 {
1080 struct wl12xx_priv *priv = wl->priv;
1081 int ret = 0;
1082 u32 clk;
1083 int selected_clock = -1;
1084
1085 if (wl->chip.id == CHIP_ID_128X_PG20) {
1086 ret = wl128x_boot_clk(wl, &selected_clock);
1087 if (ret < 0)
1088 goto out;
1089 } else {
1090 ret = wl127x_boot_clk(wl);
1091 if (ret < 0)
1092 goto out;
1093 }
1094
1095 /* Continue the ELP wake up sequence */
1096 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1097 if (ret < 0)
1098 goto out;
1099
1100 udelay(500);
1101
1102 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1103 if (ret < 0)
1104 goto out;
1105
1106 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1107 to be used by DRPw FW. The RTRIM value will be added by the FW
1108 before taking DRPw out of reset */
1109
1110 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1111 if (ret < 0)
1112 goto out;
1113
1114 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1115
1116 if (wl->chip.id == CHIP_ID_128X_PG20)
1117 clk |= ((selected_clock & 0x3) << 1) << 4;
1118 else
1119 clk |= (priv->ref_clock << 1) << 4;
1120
1121 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1122 if (ret < 0)
1123 goto out;
1124
1125 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1126 if (ret < 0)
1127 goto out;
1128
1129 /* Disable interrupts */
1130 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1131 if (ret < 0)
1132 goto out;
1133
1134 ret = wl1271_boot_soft_reset(wl);
1135 if (ret < 0)
1136 goto out;
1137
1138 out:
1139 return ret;
1140 }
1141
wl12xx_pre_upload(struct wl1271 * wl)1142 static int wl12xx_pre_upload(struct wl1271 *wl)
1143 {
1144 u32 tmp;
1145 u16 polarity;
1146 int ret;
1147
1148 /* write firmware's last address (ie. it's length) to
1149 * ACX_EEPROMLESS_IND_REG */
1150 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1151
1152 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1153 if (ret < 0)
1154 goto out;
1155
1156 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1157 if (ret < 0)
1158 goto out;
1159
1160 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1161
1162 /* 6. read the EEPROM parameters */
1163 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1164 if (ret < 0)
1165 goto out;
1166
1167 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1168 * to upload_fw) */
1169
1170 if (wl->chip.id == CHIP_ID_128X_PG20) {
1171 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1172 if (ret < 0)
1173 goto out;
1174 }
1175
1176 /* polarity must be set before the firmware is loaded */
1177 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1178 if (ret < 0)
1179 goto out;
1180
1181 /* We use HIGH polarity, so unset the LOW bit */
1182 polarity &= ~POLARITY_LOW;
1183 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1184
1185 out:
1186 return ret;
1187 }
1188
wl12xx_enable_interrupts(struct wl1271 * wl)1189 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1190 {
1191 int ret;
1192
1193 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1194 WL12XX_ACX_ALL_EVENTS_VECTOR);
1195 if (ret < 0)
1196 goto out;
1197
1198 wlcore_enable_interrupts(wl);
1199 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1200 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1201 if (ret < 0)
1202 goto disable_interrupts;
1203
1204 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1205 if (ret < 0)
1206 goto disable_interrupts;
1207
1208 return ret;
1209
1210 disable_interrupts:
1211 wlcore_disable_interrupts(wl);
1212
1213 out:
1214 return ret;
1215 }
1216
wl12xx_boot(struct wl1271 * wl)1217 static int wl12xx_boot(struct wl1271 *wl)
1218 {
1219 int ret;
1220
1221 ret = wl12xx_pre_boot(wl);
1222 if (ret < 0)
1223 goto out;
1224
1225 ret = wlcore_boot_upload_nvs(wl);
1226 if (ret < 0)
1227 goto out;
1228
1229 ret = wl12xx_pre_upload(wl);
1230 if (ret < 0)
1231 goto out;
1232
1233 ret = wlcore_boot_upload_firmware(wl);
1234 if (ret < 0)
1235 goto out;
1236
1237 wl->event_mask = BSS_LOSE_EVENT_ID |
1238 REGAINED_BSS_EVENT_ID |
1239 SCAN_COMPLETE_EVENT_ID |
1240 ROLE_STOP_COMPLETE_EVENT_ID |
1241 RSSI_SNR_TRIGGER_0_EVENT_ID |
1242 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1243 SOFT_GEMINI_SENSE_EVENT_ID |
1244 PERIODIC_SCAN_REPORT_EVENT_ID |
1245 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1246 DUMMY_PACKET_EVENT_ID |
1247 PEER_REMOVE_COMPLETE_EVENT_ID |
1248 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1249 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1250 INACTIVE_STA_EVENT_ID |
1251 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1252
1253 wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1254
1255 ret = wlcore_boot_run_firmware(wl);
1256 if (ret < 0)
1257 goto out;
1258
1259 ret = wl12xx_enable_interrupts(wl);
1260
1261 out:
1262 return ret;
1263 }
1264
wl12xx_trigger_cmd(struct wl1271 * wl,int cmd_box_addr,void * buf,size_t len)1265 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1266 void *buf, size_t len)
1267 {
1268 int ret;
1269
1270 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1271 if (ret < 0)
1272 return ret;
1273
1274 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1275
1276 return ret;
1277 }
1278
wl12xx_ack_event(struct wl1271 * wl)1279 static int wl12xx_ack_event(struct wl1271 *wl)
1280 {
1281 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1282 WL12XX_INTR_TRIG_EVENT_ACK);
1283 }
1284
wl12xx_calc_tx_blocks(struct wl1271 * wl,u32 len,u32 spare_blks)1285 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1286 {
1287 u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1288 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1289
1290 return (align_len + blk_size - 1) / blk_size + spare_blks;
1291 }
1292
1293 static void
wl12xx_set_tx_desc_blocks(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,u32 blks,u32 spare_blks)1294 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1295 u32 blks, u32 spare_blks)
1296 {
1297 if (wl->chip.id == CHIP_ID_128X_PG20) {
1298 desc->wl128x_mem.total_mem_blocks = blks;
1299 } else {
1300 desc->wl127x_mem.extra_blocks = spare_blks;
1301 desc->wl127x_mem.total_mem_blocks = blks;
1302 }
1303 }
1304
1305 static void
wl12xx_set_tx_desc_data_len(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1306 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1307 struct sk_buff *skb)
1308 {
1309 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1310
1311 if (wl->chip.id == CHIP_ID_128X_PG20) {
1312 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1313 desc->length = cpu_to_le16(aligned_len >> 2);
1314
1315 wl1271_debug(DEBUG_TX,
1316 "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1317 desc->hlid,
1318 le16_to_cpu(desc->length),
1319 le16_to_cpu(desc->life_time),
1320 desc->wl128x_mem.total_mem_blocks,
1321 desc->wl128x_mem.extra_bytes);
1322 } else {
1323 /* calculate number of padding bytes */
1324 int pad = aligned_len - skb->len;
1325 desc->tx_attr |=
1326 cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1327
1328 /* Store the aligned length in terms of words */
1329 desc->length = cpu_to_le16(aligned_len >> 2);
1330
1331 wl1271_debug(DEBUG_TX,
1332 "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1333 pad, desc->hlid,
1334 le16_to_cpu(desc->length),
1335 le16_to_cpu(desc->life_time),
1336 desc->wl127x_mem.total_mem_blocks);
1337 }
1338 }
1339
1340 static enum wl_rx_buf_align
wl12xx_get_rx_buf_align(struct wl1271 * wl,u32 rx_desc)1341 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1342 {
1343 if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1344 return WLCORE_RX_BUF_UNALIGNED;
1345
1346 return WLCORE_RX_BUF_ALIGNED;
1347 }
1348
wl12xx_get_rx_packet_len(struct wl1271 * wl,void * rx_data,u32 data_len)1349 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1350 u32 data_len)
1351 {
1352 struct wl1271_rx_descriptor *desc = rx_data;
1353
1354 /* invalid packet */
1355 if (data_len < sizeof(*desc) ||
1356 data_len < sizeof(*desc) + desc->pad_len)
1357 return 0;
1358
1359 return data_len - sizeof(*desc) - desc->pad_len;
1360 }
1361
wl12xx_tx_delayed_compl(struct wl1271 * wl)1362 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1363 {
1364 if (wl->fw_status->tx_results_counter ==
1365 (wl->tx_results_count & 0xff))
1366 return 0;
1367
1368 return wlcore_tx_complete(wl);
1369 }
1370
wl12xx_hw_init(struct wl1271 * wl)1371 static int wl12xx_hw_init(struct wl1271 *wl)
1372 {
1373 int ret;
1374
1375 if (wl->chip.id == CHIP_ID_128X_PG20) {
1376 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1377
1378 ret = wl128x_cmd_general_parms(wl);
1379 if (ret < 0)
1380 goto out;
1381
1382 /*
1383 * If we are in calibrator based auto detect then we got the FEM nr
1384 * in wl->fem_manuf. No need to continue further
1385 */
1386 if (wl->plt_mode == PLT_FEM_DETECT)
1387 goto out;
1388
1389 ret = wl128x_cmd_radio_parms(wl);
1390 if (ret < 0)
1391 goto out;
1392
1393 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1394 /* Enable SDIO padding */
1395 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1396
1397 /* Must be before wl1271_acx_init_mem_config() */
1398 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1399 if (ret < 0)
1400 goto out;
1401 } else {
1402 ret = wl1271_cmd_general_parms(wl);
1403 if (ret < 0)
1404 goto out;
1405
1406 /*
1407 * If we are in calibrator based auto detect then we got the FEM nr
1408 * in wl->fem_manuf. No need to continue further
1409 */
1410 if (wl->plt_mode == PLT_FEM_DETECT)
1411 goto out;
1412
1413 ret = wl1271_cmd_radio_parms(wl);
1414 if (ret < 0)
1415 goto out;
1416 ret = wl1271_cmd_ext_radio_parms(wl);
1417 if (ret < 0)
1418 goto out;
1419 }
1420 out:
1421 return ret;
1422 }
1423
wl12xx_convert_fw_status(struct wl1271 * wl,void * raw_fw_status,struct wl_fw_status * fw_status)1424 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1425 struct wl_fw_status *fw_status)
1426 {
1427 struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1428
1429 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1430 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1431 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1432 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1433 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1434
1435 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1436 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1437 fw_status->link_fast_bitmap =
1438 le32_to_cpu(int_fw_status->link_fast_bitmap);
1439 fw_status->total_released_blks =
1440 le32_to_cpu(int_fw_status->total_released_blks);
1441 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1442
1443 fw_status->counters.tx_released_pkts =
1444 int_fw_status->counters.tx_released_pkts;
1445 fw_status->counters.tx_lnk_free_pkts =
1446 int_fw_status->counters.tx_lnk_free_pkts;
1447 fw_status->counters.tx_voice_released_blks =
1448 int_fw_status->counters.tx_voice_released_blks;
1449 fw_status->counters.tx_last_rate =
1450 int_fw_status->counters.tx_last_rate;
1451
1452 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1453 }
1454
wl12xx_sta_get_ap_rate_mask(struct wl1271 * wl,struct wl12xx_vif * wlvif)1455 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1456 struct wl12xx_vif *wlvif)
1457 {
1458 return wlvif->rate_set;
1459 }
1460
wl12xx_conf_init(struct wl1271 * wl)1461 static void wl12xx_conf_init(struct wl1271 *wl)
1462 {
1463 struct wl12xx_priv *priv = wl->priv;
1464
1465 /* apply driver default configuration */
1466 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1467
1468 /* apply default private configuration */
1469 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1470 }
1471
wl12xx_mac_in_fuse(struct wl1271 * wl)1472 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1473 {
1474 bool supported = false;
1475 u8 major, minor;
1476
1477 if (wl->chip.id == CHIP_ID_128X_PG20) {
1478 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1479 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1480
1481 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1482 if (major > 2 || (major == 2 && minor >= 1))
1483 supported = true;
1484 } else {
1485 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1486 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1487
1488 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1489 if (major == 3 && minor >= 1)
1490 supported = true;
1491 }
1492
1493 wl1271_debug(DEBUG_PROBE,
1494 "PG Ver major = %d minor = %d, MAC %s present",
1495 major, minor, supported ? "is" : "is not");
1496
1497 return supported;
1498 }
1499
wl12xx_get_fuse_mac(struct wl1271 * wl)1500 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1501 {
1502 u32 mac1, mac2;
1503 int ret;
1504
1505 /* Device may be in ELP from the bootloader or kexec */
1506 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1507 if (ret < 0)
1508 goto out;
1509
1510 usleep_range(500000, 700000);
1511
1512 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1513 if (ret < 0)
1514 goto out;
1515
1516 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1517 if (ret < 0)
1518 goto out;
1519
1520 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1521 if (ret < 0)
1522 goto out;
1523
1524 /* these are the two parts of the BD_ADDR */
1525 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1526 ((mac1 & 0xff000000) >> 24);
1527 wl->fuse_nic_addr = mac1 & 0xffffff;
1528
1529 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1530
1531 out:
1532 return ret;
1533 }
1534
wl12xx_get_pg_ver(struct wl1271 * wl,s8 * ver)1535 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1536 {
1537 u16 die_info;
1538 int ret;
1539
1540 if (wl->chip.id == CHIP_ID_128X_PG20)
1541 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1542 &die_info);
1543 else
1544 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1545 &die_info);
1546
1547 if (ret >= 0 && ver)
1548 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1549
1550 return ret;
1551 }
1552
wl12xx_get_mac(struct wl1271 * wl)1553 static int wl12xx_get_mac(struct wl1271 *wl)
1554 {
1555 if (wl12xx_mac_in_fuse(wl))
1556 return wl12xx_get_fuse_mac(wl);
1557
1558 return 0;
1559 }
1560
wl12xx_set_tx_desc_csum(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1561 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1562 struct wl1271_tx_hw_descr *desc,
1563 struct sk_buff *skb)
1564 {
1565 desc->wl12xx_reserved = 0;
1566 }
1567
wl12xx_plt_init(struct wl1271 * wl)1568 static int wl12xx_plt_init(struct wl1271 *wl)
1569 {
1570 int ret;
1571
1572 ret = wl->ops->boot(wl);
1573 if (ret < 0)
1574 goto out;
1575
1576 ret = wl->ops->hw_init(wl);
1577 if (ret < 0)
1578 goto out_irq_disable;
1579
1580 /*
1581 * If we are in calibrator based auto detect then we got the FEM nr
1582 * in wl->fem_manuf. No need to continue further
1583 */
1584 if (wl->plt_mode == PLT_FEM_DETECT)
1585 goto out;
1586
1587 ret = wl1271_acx_init_mem_config(wl);
1588 if (ret < 0)
1589 goto out_irq_disable;
1590
1591 ret = wl12xx_acx_mem_cfg(wl);
1592 if (ret < 0)
1593 goto out_free_memmap;
1594
1595 /* Enable data path */
1596 ret = wl1271_cmd_data_path(wl, 1);
1597 if (ret < 0)
1598 goto out_free_memmap;
1599
1600 /* Configure for CAM power saving (ie. always active) */
1601 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1602 if (ret < 0)
1603 goto out_free_memmap;
1604
1605 /* configure PM */
1606 ret = wl1271_acx_pm_config(wl);
1607 if (ret < 0)
1608 goto out_free_memmap;
1609
1610 goto out;
1611
1612 out_free_memmap:
1613 kfree(wl->target_mem_map);
1614 wl->target_mem_map = NULL;
1615
1616 out_irq_disable:
1617 mutex_unlock(&wl->mutex);
1618 /* Unlocking the mutex in the middle of handling is
1619 inherently unsafe. In this case we deem it safe to do,
1620 because we need to let any possibly pending IRQ out of
1621 the system (and while we are WL1271_STATE_OFF the IRQ
1622 work function will not do anything.) Also, any other
1623 possible concurrent operations will fail due to the
1624 current state, hence the wl1271 struct should be safe. */
1625 wlcore_disable_interrupts(wl);
1626 mutex_lock(&wl->mutex);
1627 out:
1628 return ret;
1629 }
1630
wl12xx_get_spare_blocks(struct wl1271 * wl,bool is_gem)1631 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1632 {
1633 if (is_gem)
1634 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1635
1636 return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1637 }
1638
wl12xx_set_key(struct wl1271 * wl,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key_conf)1639 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1640 struct ieee80211_vif *vif,
1641 struct ieee80211_sta *sta,
1642 struct ieee80211_key_conf *key_conf)
1643 {
1644 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1645 }
1646
wl12xx_set_peer_cap(struct wl1271 * wl,struct ieee80211_sta_ht_cap * ht_cap,bool allow_ht_operation,u32 rate_set,u8 hlid)1647 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1648 struct ieee80211_sta_ht_cap *ht_cap,
1649 bool allow_ht_operation,
1650 u32 rate_set, u8 hlid)
1651 {
1652 return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1653 hlid);
1654 }
1655
wl12xx_lnk_high_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1656 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1657 struct wl1271_link *lnk)
1658 {
1659 u8 thold;
1660
1661 if (test_bit(hlid, &wl->fw_fast_lnk_map))
1662 thold = wl->conf.tx.fast_link_thold;
1663 else
1664 thold = wl->conf.tx.slow_link_thold;
1665
1666 return lnk->allocated_pkts < thold;
1667 }
1668
wl12xx_lnk_low_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1669 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1670 struct wl1271_link *lnk)
1671 {
1672 /* any link is good for low priority */
1673 return true;
1674 }
1675
wl12xx_convert_hwaddr(struct wl1271 * wl,u32 hwaddr)1676 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1677 {
1678 return hwaddr << 5;
1679 }
1680
1681 static int wl12xx_setup(struct wl1271 *wl);
1682
1683 static struct wlcore_ops wl12xx_ops = {
1684 .setup = wl12xx_setup,
1685 .identify_chip = wl12xx_identify_chip,
1686 .boot = wl12xx_boot,
1687 .plt_init = wl12xx_plt_init,
1688 .trigger_cmd = wl12xx_trigger_cmd,
1689 .ack_event = wl12xx_ack_event,
1690 .wait_for_event = wl12xx_wait_for_event,
1691 .process_mailbox_events = wl12xx_process_mailbox_events,
1692 .calc_tx_blocks = wl12xx_calc_tx_blocks,
1693 .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1694 .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1695 .get_rx_buf_align = wl12xx_get_rx_buf_align,
1696 .get_rx_packet_len = wl12xx_get_rx_packet_len,
1697 .tx_immediate_compl = NULL,
1698 .tx_delayed_compl = wl12xx_tx_delayed_compl,
1699 .hw_init = wl12xx_hw_init,
1700 .init_vif = NULL,
1701 .convert_fw_status = wl12xx_convert_fw_status,
1702 .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1703 .get_pg_ver = wl12xx_get_pg_ver,
1704 .get_mac = wl12xx_get_mac,
1705 .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1706 .set_rx_csum = NULL,
1707 .ap_get_mimo_wide_rate_mask = NULL,
1708 .debugfs_init = wl12xx_debugfs_add_files,
1709 .scan_start = wl12xx_scan_start,
1710 .scan_stop = wl12xx_scan_stop,
1711 .sched_scan_start = wl12xx_sched_scan_start,
1712 .sched_scan_stop = wl12xx_scan_sched_scan_stop,
1713 .get_spare_blocks = wl12xx_get_spare_blocks,
1714 .set_key = wl12xx_set_key,
1715 .channel_switch = wl12xx_cmd_channel_switch,
1716 .pre_pkt_send = NULL,
1717 .set_peer_cap = wl12xx_set_peer_cap,
1718 .convert_hwaddr = wl12xx_convert_hwaddr,
1719 .lnk_high_prio = wl12xx_lnk_high_prio,
1720 .lnk_low_prio = wl12xx_lnk_low_prio,
1721 .interrupt_notify = NULL,
1722 .rx_ba_filter = NULL,
1723 .ap_sleep = NULL,
1724 };
1725
1726 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1727 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1728 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1729 .ht_supported = true,
1730 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1731 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1732 .mcs = {
1733 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1734 .rx_highest = cpu_to_le16(72),
1735 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1736 },
1737 };
1738
1739 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1740 {
1741 .max = 3,
1742 .types = BIT(NL80211_IFTYPE_STATION),
1743 },
1744 {
1745 .max = 1,
1746 .types = BIT(NL80211_IFTYPE_AP) |
1747 BIT(NL80211_IFTYPE_P2P_GO) |
1748 BIT(NL80211_IFTYPE_P2P_CLIENT),
1749 },
1750 };
1751
1752 static const struct ieee80211_iface_combination
1753 wl12xx_iface_combinations[] = {
1754 {
1755 .max_interfaces = 3,
1756 .limits = wl12xx_iface_limits,
1757 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1758 .num_different_channels = 1,
1759 },
1760 };
1761
1762 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1763 { 19200000, false, WL12XX_REFCLOCK_19 },
1764 { 26000000, false, WL12XX_REFCLOCK_26 },
1765 { 26000000, true, WL12XX_REFCLOCK_26_XTAL },
1766 { 38400000, false, WL12XX_REFCLOCK_38 },
1767 { 38400000, true, WL12XX_REFCLOCK_38_XTAL },
1768 { 52000000, false, WL12XX_REFCLOCK_52 },
1769 { 0, false, 0 }
1770 };
1771
1772 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1773 { 16368000, true, WL12XX_TCXOCLOCK_16_368 },
1774 { 16800000, true, WL12XX_TCXOCLOCK_16_8 },
1775 { 19200000, true, WL12XX_TCXOCLOCK_19_2 },
1776 { 26000000, true, WL12XX_TCXOCLOCK_26 },
1777 { 32736000, true, WL12XX_TCXOCLOCK_32_736 },
1778 { 33600000, true, WL12XX_TCXOCLOCK_33_6 },
1779 { 38400000, true, WL12XX_TCXOCLOCK_38_4 },
1780 { 52000000, true, WL12XX_TCXOCLOCK_52 },
1781 { 0, false, 0 }
1782 };
1783
wl12xx_get_clock_idx(const struct wl12xx_clock * table,u32 freq,bool xtal)1784 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1785 u32 freq, bool xtal)
1786 {
1787 int i;
1788
1789 for (i = 0; table[i].freq != 0; i++)
1790 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1791 return table[i].hw_idx;
1792
1793 return -EINVAL;
1794 }
1795
wl12xx_setup(struct wl1271 * wl)1796 static int wl12xx_setup(struct wl1271 *wl)
1797 {
1798 struct wl12xx_priv *priv = wl->priv;
1799 struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1800
1801 BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1802 BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1803 BUILD_BUG_ON(WL12XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1804
1805 wl->rtable = wl12xx_rtable;
1806 wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1807 wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1808 wl->num_links = WL12XX_MAX_LINKS;
1809 wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1810 wl->iface_combinations = wl12xx_iface_combinations;
1811 wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1812 wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1813 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1814 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1815 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1816 wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1817 wl->fw_status_priv_len = 0;
1818 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1819 wl->ofdm_only_ap = true;
1820 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, &wl12xx_ht_cap);
1821 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, &wl12xx_ht_cap);
1822 wl12xx_conf_init(wl);
1823
1824 if (!fref_param) {
1825 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1826 pdev_data->ref_clock_freq,
1827 pdev_data->ref_clock_xtal);
1828 if (priv->ref_clock < 0) {
1829 wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1830 pdev_data->ref_clock_freq,
1831 pdev_data->ref_clock_xtal ?
1832 "XTAL" : "not XTAL");
1833
1834 return priv->ref_clock;
1835 }
1836 } else {
1837 if (!strcmp(fref_param, "19.2"))
1838 priv->ref_clock = WL12XX_REFCLOCK_19;
1839 else if (!strcmp(fref_param, "26"))
1840 priv->ref_clock = WL12XX_REFCLOCK_26;
1841 else if (!strcmp(fref_param, "26x"))
1842 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1843 else if (!strcmp(fref_param, "38.4"))
1844 priv->ref_clock = WL12XX_REFCLOCK_38;
1845 else if (!strcmp(fref_param, "38.4x"))
1846 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1847 else if (!strcmp(fref_param, "52"))
1848 priv->ref_clock = WL12XX_REFCLOCK_52;
1849 else
1850 wl1271_error("Invalid fref parameter %s", fref_param);
1851 }
1852
1853 if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1854 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1855 pdev_data->tcxo_clock_freq,
1856 true);
1857 if (priv->tcxo_clock < 0) {
1858 wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1859 pdev_data->tcxo_clock_freq);
1860
1861 return priv->tcxo_clock;
1862 }
1863 } else if (tcxo_param) {
1864 if (!strcmp(tcxo_param, "19.2"))
1865 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1866 else if (!strcmp(tcxo_param, "26"))
1867 priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1868 else if (!strcmp(tcxo_param, "38.4"))
1869 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1870 else if (!strcmp(tcxo_param, "52"))
1871 priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1872 else if (!strcmp(tcxo_param, "16.368"))
1873 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1874 else if (!strcmp(tcxo_param, "32.736"))
1875 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1876 else if (!strcmp(tcxo_param, "16.8"))
1877 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1878 else if (!strcmp(tcxo_param, "33.6"))
1879 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1880 else
1881 wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1882 }
1883
1884 priv->rx_mem_addr = kmalloc_obj(*priv->rx_mem_addr);
1885 if (!priv->rx_mem_addr)
1886 return -ENOMEM;
1887
1888 return 0;
1889 }
1890
wl12xx_probe(struct platform_device * pdev)1891 static int wl12xx_probe(struct platform_device *pdev)
1892 {
1893 struct wl1271 *wl;
1894 struct ieee80211_hw *hw;
1895 int ret;
1896
1897 hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1898 WL12XX_AGGR_BUFFER_SIZE,
1899 sizeof(struct wl12xx_event_mailbox));
1900 if (IS_ERR(hw)) {
1901 wl1271_error("can't allocate hw");
1902 ret = PTR_ERR(hw);
1903 goto out;
1904 }
1905
1906 wl = hw->priv;
1907 wl->ops = &wl12xx_ops;
1908 wl->ptable = wl12xx_ptable;
1909 ret = wlcore_probe(wl, pdev);
1910 if (ret)
1911 goto out_free;
1912
1913 return ret;
1914
1915 out_free:
1916 wlcore_free_hw(wl);
1917 out:
1918 return ret;
1919 }
1920
wl12xx_remove(struct platform_device * pdev)1921 static void wl12xx_remove(struct platform_device *pdev)
1922 {
1923 struct wl1271 *wl = platform_get_drvdata(pdev);
1924 struct wl12xx_priv *priv;
1925
1926 priv = wl->priv;
1927
1928 kfree(priv->rx_mem_addr);
1929
1930 wlcore_remove(pdev);
1931 }
1932
1933 static const struct platform_device_id wl12xx_id_table[] = {
1934 { "wl12xx", 0 },
1935 { } /* Terminating Entry */
1936 };
1937 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1938
1939 static struct platform_driver wl12xx_driver = {
1940 .probe = wl12xx_probe,
1941 .remove = wl12xx_remove,
1942 .id_table = wl12xx_id_table,
1943 .driver = {
1944 .name = "wl12xx_driver",
1945 }
1946 };
1947
1948 module_platform_driver(wl12xx_driver);
1949
1950 module_param_named(fref, fref_param, charp, 0);
1951 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1952
1953 module_param_named(tcxo, tcxo_param, charp, 0);
1954 MODULE_PARM_DESC(tcxo,
1955 "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1956
1957 MODULE_DESCRIPTION("TI WL12xx wireless driver");
1958 MODULE_LICENSE("GPL v2");
1959 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1960 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1961 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1962 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1963 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1964 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1965 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);
1966