1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020, MIPI Alliance, Inc. 4 * 5 * Author: Nicolas Pitre <npitre@baylibre.com> 6 * 7 * Common HCI stuff 8 */ 9 10 #ifndef HCI_H 11 #define HCI_H 12 13 #include <linux/io.h> 14 #include <linux/jiffies.h> 15 16 /* 32-bit word aware bit and mask macros */ 17 #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) 18 #define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32) 19 #define W2_MASK(h, l) GENMASK((h) - 64, (l) - 64) 20 #define W3_MASK(h, l) GENMASK((h) - 96, (l) - 96) 21 22 /* Same for single bit macros (trailing _ to align with W*_MASK width) */ 23 #define W0_BIT_(x) BIT((x) - 0) 24 #define W1_BIT_(x) BIT((x) - 32) 25 #define W2_BIT_(x) BIT((x) - 64) 26 #define W3_BIT_(x) BIT((x) - 96) 27 28 #define reg_read(r) readl(hci->base_regs + (r)) 29 #define reg_write(r, v) writel(v, hci->base_regs + (r)) 30 #define reg_set(r, v) reg_write(r, reg_read(r) | (v)) 31 #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) 32 33 struct hci_cmd_ops; 34 35 struct dat_words { 36 u32 w0; 37 u32 w1; 38 }; 39 40 /* Our main structure */ 41 struct i3c_hci { 42 struct i3c_master_controller master; 43 void __iomem *base_regs; 44 void __iomem *DAT_regs; 45 void __iomem *DCT_regs; 46 void __iomem *RHS_regs; 47 void __iomem *PIO_regs; 48 void __iomem *EXTCAPS_regs; 49 void __iomem *AUTOCMD_regs; 50 void __iomem *DEBUG_regs; 51 const struct hci_io_ops *io; 52 void *io_data; 53 const struct hci_cmd_ops *cmd; 54 spinlock_t lock; 55 struct mutex control_mutex; 56 atomic_t next_cmd_tid; 57 bool irq_inactive; 58 bool enqueue_blocked; 59 bool recovery_needed; 60 bool hj_init_done; 61 wait_queue_head_t enqueue_wait_queue; 62 u32 caps; 63 unsigned int quirks; 64 unsigned int DAT_entries; 65 unsigned int DAT_entry_size; 66 void *DAT_data; 67 struct dat_words *DAT; 68 struct i3c_dev_desc **ibi_devs; 69 unsigned int DCT_entries; 70 unsigned int DCT_entry_size; 71 u8 version_major; 72 u8 version_minor; 73 u8 revision; 74 u8 dyn_addr; 75 u32 vendor_mipi_id; 76 u32 vendor_version_id; 77 u32 vendor_product_id; 78 void *vendor_data; 79 }; 80 81 /* 82 * Structure to represent a master initiated transfer. 83 * The rnw, data and data_len fields must be initialized before calling any 84 * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and 85 * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can 86 * be augmented with CMD_0_ROC and/or CMD_0_TOC. 87 * The completion field needs to be initialized before queueing with 88 * hci->io->queue_xfer(), and requires CMD_0_ROC to be set. 89 */ 90 struct hci_xfer { 91 u32 cmd_desc[4]; 92 u32 response; 93 bool rnw; 94 bool started; 95 void *data; 96 unsigned int data_len; 97 unsigned int cmd_tid; 98 struct completion *completion; 99 unsigned long timeout; 100 unsigned long start_jiffies; 101 union { 102 struct { 103 /* PIO specific */ 104 struct hci_xfer *next_xfer; 105 struct hci_xfer *next_data; 106 struct hci_xfer *next_resp; 107 unsigned int data_left; 108 u32 data_word_before_partial; 109 }; 110 struct { 111 /* DMA specific */ 112 struct i3c_dma *dma; 113 struct hci_xfer *final_xfer; 114 int ring_number; 115 int ring_entry; 116 int xfer_list_pos; 117 }; 118 }; 119 }; 120 121 static inline struct hci_xfer *hci_alloc_xfer(unsigned int n) 122 { 123 return kzalloc_objs(struct hci_xfer, n); 124 } 125 126 static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n) 127 { 128 kfree(xfer); 129 } 130 131 static inline void hci_start_xfer(struct hci_xfer *xfer) 132 { 133 if (!xfer->started) { 134 xfer->started = true; 135 xfer->start_jiffies = jiffies; 136 } 137 } 138 139 /* This abstracts PIO vs DMA operations */ 140 struct hci_io_ops { 141 bool (*irq_handler)(struct i3c_hci *hci); 142 int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 143 bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 144 int (*handle_error)(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 145 int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev, 146 const struct i3c_ibi_setup *req); 147 void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev); 148 void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev, 149 struct i3c_ibi_slot *slot); 150 int (*init)(struct i3c_hci *hci); 151 void (*cleanup)(struct i3c_hci *hci); 152 void (*suspend)(struct i3c_hci *hci); 153 void (*resume)(struct i3c_hci *hci); 154 }; 155 156 extern const struct hci_io_ops mipi_i3c_hci_pio; 157 extern const struct hci_io_ops mipi_i3c_hci_dma; 158 159 /* Our per device master private data */ 160 struct i3c_hci_dev_data { 161 int dat_idx; 162 void *ibi_data; 163 }; 164 165 /* list of quirks */ 166 #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ 167 #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ 168 #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ 169 #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ 170 #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ 171 #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed while runtime suspended */ 172 #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by parent device */ 173 #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW resets after DMA abort */ 174 #define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT to abort DMA */ 175 176 /* global functions */ 177 void mipi_i3c_hci_resume(struct i3c_hci *hci); 178 void mipi_i3c_hci_abort(struct i3c_hci *hci); 179 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); 180 void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); 181 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); 182 void amd_set_od_pp_timing(struct i3c_hci *hci); 183 void amd_set_resp_buf_thld(struct i3c_hci *hci); 184 void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); 185 int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 186 187 #define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 188 189 int i3c_hci_rpm_suspend(struct device *dev); 190 int i3c_hci_rpm_resume(struct device *dev); 191 192 int i3c_hci_reset_and_restore(struct i3c_hci *hci); 193 194 #endif 195