1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Cirrus Logic CS48L32 audio DSP. 4 // 5 // Copyright (C) 2016-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <dt-bindings/sound/cs48l32.h> 9 #include <linux/array_size.h> 10 #include <linux/build_bug.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/container_of.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/gcd.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/minmax.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/spi/spi.h> 27 #include <linux/string_choices.h> 28 #include <sound/cs48l32.h> 29 #include <sound/cs48l32_registers.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-component.h> 34 #include <sound/soc-dai.h> 35 #include <sound/soc-dapm.h> 36 #include <sound/tlv.h> 37 38 #include "cs48l32.h" 39 40 static const char * const cs48l32_core_supplies[] = { "vdd-a", "vdd-io" }; 41 42 static const struct cs_dsp_region cs48l32_dsp1_regions[] = { 43 { .type = WMFW_HALO_PM_PACKED, .base = 0x3800000 }, 44 { .type = WMFW_HALO_XM_PACKED, .base = 0x2000000 }, 45 { .type = WMFW_ADSP2_XM, .base = 0x2800000 }, 46 { .type = WMFW_HALO_YM_PACKED, .base = 0x2C00000 }, 47 { .type = WMFW_ADSP2_YM, .base = 0x3400000 }, 48 }; 49 50 static const struct cs48l32_dsp_power_reg_block cs48l32_dsp1_sram_ext_regs[] = { 51 { CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 }, 52 { CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 }, 53 { CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 }, 54 }; 55 56 static const unsigned int cs48l32_dsp1_sram_pwd_regs[] = { 57 CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0, 58 CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0, 59 CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0, 60 }; 61 62 static const struct cs48l32_dsp_power_regs cs48l32_dsp_sram_regs = { 63 .ext = cs48l32_dsp1_sram_ext_regs, 64 .n_ext = ARRAY_SIZE(cs48l32_dsp1_sram_ext_regs), 65 .pwd = cs48l32_dsp1_sram_pwd_regs, 66 .n_pwd = ARRAY_SIZE(cs48l32_dsp1_sram_pwd_regs), 67 }; 68 69 static const char * const cs48l32_mixer_texts[] = { 70 "None", 71 "Tone Generator 1", 72 "Tone Generator 2", 73 "Noise Generator", 74 "IN1L", 75 "IN1R", 76 "IN2L", 77 "IN2R", 78 "ASP1RX1", 79 "ASP1RX2", 80 "ASP1RX3", 81 "ASP1RX4", 82 "ASP1RX5", 83 "ASP1RX6", 84 "ASP1RX7", 85 "ASP1RX8", 86 "ASP2RX1", 87 "ASP2RX2", 88 "ASP2RX3", 89 "ASP2RX4", 90 "ISRC1INT1", 91 "ISRC1INT2", 92 "ISRC1INT3", 93 "ISRC1INT4", 94 "ISRC1DEC1", 95 "ISRC1DEC2", 96 "ISRC1DEC3", 97 "ISRC1DEC4", 98 "ISRC2INT1", 99 "ISRC2INT2", 100 "ISRC2DEC1", 101 "ISRC2DEC2", 102 "ISRC3INT1", 103 "ISRC3INT2", 104 "ISRC3DEC1", 105 "ISRC3DEC2", 106 "EQ1", 107 "EQ2", 108 "EQ3", 109 "EQ4", 110 "DRC1L", 111 "DRC1R", 112 "DRC2L", 113 "DRC2R", 114 "LHPF1", 115 "LHPF2", 116 "LHPF3", 117 "LHPF4", 118 "Ultrasonic 1", 119 "Ultrasonic 2", 120 "DSP1.1", 121 "DSP1.2", 122 "DSP1.3", 123 "DSP1.4", 124 "DSP1.5", 125 "DSP1.6", 126 "DSP1.7", 127 "DSP1.8", 128 }; 129 130 static unsigned int cs48l32_mixer_values[] = { 131 0x000, /* Silence (mute) */ 132 0x004, /* Tone generator 1 */ 133 0x005, /* Tone generator 2 */ 134 0x00C, /* Noise Generator */ 135 0x010, /* IN1L signal path */ 136 0x011, /* IN1R signal path */ 137 0x012, /* IN2L signal path */ 138 0x013, /* IN2R signal path */ 139 0x020, /* ASP1 RX1 */ 140 0x021, /* ASP1 RX2 */ 141 0x022, /* ASP1 RX3 */ 142 0x023, /* ASP1 RX4 */ 143 0x024, /* ASP1 RX5 */ 144 0x025, /* ASP1 RX6 */ 145 0x026, /* ASP1 RX7 */ 146 0x027, /* ASP1 RX8 */ 147 0x030, /* ASP2 RX1 */ 148 0x031, /* ASP2 RX2 */ 149 0x032, /* ASP2 RX3 */ 150 0x033, /* ASP2 RX4 */ 151 0x098, /* ISRC1 INT1 */ 152 0x099, /* ISRC1 INT2 */ 153 0x09a, /* ISRC1 INT3 */ 154 0x09b, /* ISRC1 INT4 */ 155 0x09C, /* ISRC1 DEC1 */ 156 0x09D, /* ISRC1 DEC2 */ 157 0x09e, /* ISRC1 DEC3 */ 158 0x09f, /* ISRC1 DEC4 */ 159 0x0A0, /* ISRC2 INT1 */ 160 0x0A1, /* ISRC2 INT2 */ 161 0x0A4, /* ISRC2 DEC1 */ 162 0x0A5, /* ISRC2 DEC2 */ 163 0x0A8, /* ISRC3 INT1 */ 164 0x0A9, /* ISRC3 INT2 */ 165 0x0AC, /* ISRC3 DEC1 */ 166 0x0AD, /* ISRC3 DEC2 */ 167 0x0B8, /* EQ1 */ 168 0x0B9, /* EQ2 */ 169 0x0BA, /* EQ3 */ 170 0x0BB, /* EQ4 */ 171 0x0C0, /* DRC1 Left */ 172 0x0C1, /* DRC1 Right */ 173 0x0C2, /* DRC2 Left */ 174 0x0C3, /* DRC2 Right */ 175 0x0C8, /* LHPF1 */ 176 0x0C9, /* LHPF2 */ 177 0x0CA, /* LHPF3 */ 178 0x0CB, /* LHPF4 */ 179 0x0D8, /* Ultrasonic 1 */ 180 0x0D9, /* Ultrasonic 2 */ 181 0x100, /* DSP1 channel 1 */ 182 0x101, /* DSP1 channel 2 */ 183 0x102, /* DSP1 channel 3 */ 184 0x103, /* DSP1 channel 4 */ 185 0x104, /* DSP1 channel 5 */ 186 0x105, /* DSP1 channel 6 */ 187 0x106, /* DSP1 channel 7 */ 188 0x107, /* DSP1 channel 8 */ 189 }; 190 static_assert(ARRAY_SIZE(cs48l32_mixer_texts) == ARRAY_SIZE(cs48l32_mixer_values)); 191 #define CS48L32_NUM_MIXER_INPUTS ARRAY_SIZE(cs48l32_mixer_values) 192 193 static const DECLARE_TLV_DB_SCALE(cs48l32_ana_tlv, 0, 100, 0); 194 static const DECLARE_TLV_DB_SCALE(cs48l32_eq_tlv, -1200, 100, 0); 195 static const DECLARE_TLV_DB_SCALE(cs48l32_digital_tlv, -6400, 50, 0); 196 static const DECLARE_TLV_DB_SCALE(cs48l32_noise_tlv, -10800, 600, 0); 197 static const DECLARE_TLV_DB_SCALE(cs48l32_mixer_tlv, -3200, 100, 0); 198 static const DECLARE_TLV_DB_SCALE(cs48l32_us_tlv, 0, 600, 0); 199 200 static void cs48l32_spin_sysclk(struct cs48l32_codec *cs48l32_codec) 201 { 202 struct cs48l32 *cs48l32 = &cs48l32_codec->core; 203 unsigned int val; 204 int ret, i; 205 206 /* Skip this if the chip is down */ 207 if (pm_runtime_suspended(cs48l32->dev)) 208 return; 209 210 /* 211 * Just read a register a few times to ensure the internal 212 * oscillator sends out some clocks. 213 */ 214 for (i = 0; i < 4; i++) { 215 ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &val); 216 if (ret) 217 dev_err(cs48l32_codec->core.dev, "%s Failed to read register: %d (%d)\n", 218 __func__, ret, i); 219 } 220 221 udelay(300); 222 } 223 224 static const char * const cs48l32_rate_text[] = { 225 "Sample Rate 1", "Sample Rate 2", "Sample Rate 3", "Sample Rate 4", 226 }; 227 228 static const unsigned int cs48l32_rate_val[] = { 229 0x0, 0x1, 0x2, 0x3, 230 }; 231 static_assert(ARRAY_SIZE(cs48l32_rate_val) == ARRAY_SIZE(cs48l32_rate_text)); 232 233 static int cs48l32_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 234 { 235 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 236 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 237 int ret; 238 239 /* Prevent any mixer mux changes while we do this */ 240 guard(mutex)(&cs48l32_codec->rate_lock); 241 242 /* The write must be guarded by a number of SYSCLK cycles */ 243 cs48l32_spin_sysclk(cs48l32_codec); 244 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 245 cs48l32_spin_sysclk(cs48l32_codec); 246 247 return ret; 248 } 249 250 static const char * const cs48l32_sample_rate_text[] = { 251 "12kHz", 252 "24kHz", 253 "48kHz", 254 "96kHz", 255 "192kHz", 256 "384kHz", 257 "768kHz", 258 "11.025kHz", 259 "22.05kHz", 260 "44.1kHz", 261 "88.2kHz", 262 "176.4kHz", 263 "352.8kHz", 264 "705.6kHz", 265 "8kHz", 266 "16kHz", 267 "32kHz", 268 }; 269 270 static const unsigned int cs48l32_sample_rate_val[] = { 271 0x01, /* 12kHz */ 272 0x02, /* 24kHz */ 273 0x03, /* 48kHz */ 274 0x04, /* 96kHz */ 275 0x05, /* 192kHz */ 276 0x06, /* 384kHz */ 277 0x07, /* 768kHz */ 278 0x09, /* 11.025kHz */ 279 0x0a, /* 22.05kHz */ 280 0x0b, /* 44.1kHz */ 281 0x0c, /* 88.2kHz */ 282 0x0d, /* 176.4kHz */ 283 0x0e, /* 352.8kHz */ 284 0x0f, /* 705.6kHz */ 285 0x11, /* 8kHz */ 286 0x12, /* 16kHz */ 287 0x13, /* 32kHz */ 288 }; 289 static_assert(ARRAY_SIZE(cs48l32_sample_rate_val) == ARRAY_SIZE(cs48l32_sample_rate_text)); 290 #define CS48L32_SAMPLE_RATE_ENUM_SIZE ARRAY_SIZE(cs48l32_sample_rate_val) 291 292 static const struct soc_enum cs48l32_sample_rate[] = { 293 SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE1, 294 CS48L32_SAMPLE_RATE_1_SHIFT, 295 CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, 296 CS48L32_SAMPLE_RATE_ENUM_SIZE, 297 cs48l32_sample_rate_text, 298 cs48l32_sample_rate_val), 299 SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE2, 300 CS48L32_SAMPLE_RATE_1_SHIFT, 301 CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, 302 CS48L32_SAMPLE_RATE_ENUM_SIZE, 303 cs48l32_sample_rate_text, 304 cs48l32_sample_rate_val), 305 SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE3, 306 CS48L32_SAMPLE_RATE_1_SHIFT, 307 CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, 308 CS48L32_SAMPLE_RATE_ENUM_SIZE, 309 cs48l32_sample_rate_text, 310 cs48l32_sample_rate_val), 311 SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE4, 312 CS48L32_SAMPLE_RATE_1_SHIFT, 313 CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, 314 CS48L32_SAMPLE_RATE_ENUM_SIZE, 315 cs48l32_sample_rate_text, 316 cs48l32_sample_rate_val), 317 }; 318 319 static int cs48l32_inmux_put(struct snd_kcontrol *kcontrol, 320 struct snd_ctl_elem_value *ucontrol) 321 { 322 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 323 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 324 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 325 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 326 unsigned int mux, src_val, in_type; 327 int ret; 328 329 mux = ucontrol->value.enumerated.item[0]; 330 if (mux > 1) 331 return -EINVAL; 332 333 switch (e->reg) { 334 case CS48L32_IN1L_CONTROL1: 335 in_type = cs48l32_codec->in_type[0][mux]; 336 break; 337 case CS48L32_IN1R_CONTROL1: 338 in_type = cs48l32_codec->in_type[1][mux]; 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 src_val = mux << e->shift_l; 345 346 if (in_type == CS48L32_IN_TYPE_SE) 347 src_val |= 1 << CS48L32_INx_SRC_SHIFT; 348 349 ret = snd_soc_component_update_bits(component, 350 e->reg, 351 CS48L32_INx_SRC_MASK, 352 src_val); 353 if (ret > 0) 354 snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL); 355 356 return ret; 357 } 358 359 static const char * const cs48l32_inmux_texts[] = { 360 "Analog 1", "Analog 2", 361 }; 362 363 static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxl_enum, 364 CS48L32_IN1L_CONTROL1, 365 CS48L32_INx_SRC_SHIFT + 1, 366 cs48l32_inmux_texts); 367 368 static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxr_enum, 369 CS48L32_IN1R_CONTROL1, 370 CS48L32_INx_SRC_SHIFT + 1, 371 cs48l32_inmux_texts); 372 373 static const struct snd_kcontrol_new cs48l32_inmux[] = { 374 SOC_DAPM_ENUM_EXT("IN1L Mux", cs48l32_in1muxl_enum, 375 snd_soc_dapm_get_enum_double, cs48l32_inmux_put), 376 SOC_DAPM_ENUM_EXT("IN1R Mux", cs48l32_in1muxr_enum, 377 snd_soc_dapm_get_enum_double, cs48l32_inmux_put), 378 }; 379 380 static const char * const cs48l32_dmode_texts[] = { 381 "Analog", "Digital", 382 }; 383 384 static int cs48l32_dmode_put(struct snd_kcontrol *kcontrol, 385 struct snd_ctl_elem_value *ucontrol) 386 { 387 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 388 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 389 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 390 unsigned int mode; 391 int ret, result; 392 393 mode = ucontrol->value.enumerated.item[0]; 394 switch (mode) { 395 case 0: 396 ret = snd_soc_component_update_bits(component, 397 CS48L32_ADC1L_ANA_CONTROL1, 398 CS48L32_ADC1x_INT_ENA_FRC_MASK, 399 CS48L32_ADC1x_INT_ENA_FRC_MASK); 400 if (ret < 0) { 401 dev_err(component->dev, 402 "Failed to set ADC1L_INT_ENA_FRC: %d\n", ret); 403 return ret; 404 } 405 406 ret = snd_soc_component_update_bits(component, 407 CS48L32_ADC1R_ANA_CONTROL1, 408 CS48L32_ADC1x_INT_ENA_FRC_MASK, 409 CS48L32_ADC1x_INT_ENA_FRC_MASK); 410 if (ret < 0) { 411 dev_err(component->dev, 412 "Failed to set ADC1R_INT_ENA_FRC: %d\n", ret); 413 return ret; 414 } 415 416 result = snd_soc_component_update_bits(component, 417 e->reg, 418 BIT(CS48L32_IN1_MODE_SHIFT), 419 0); 420 if (result < 0) { 421 dev_err(component->dev, "Failed to set input mode: %d\n", result); 422 return result; 423 } 424 425 usleep_range(200, 300); 426 427 ret = snd_soc_component_update_bits(component, 428 CS48L32_ADC1L_ANA_CONTROL1, 429 CS48L32_ADC1x_INT_ENA_FRC_MASK, 430 0); 431 if (ret < 0) { 432 dev_err(component->dev, 433 "Failed to clear ADC1L_INT_ENA_FRC: %d\n", ret); 434 return ret; 435 } 436 437 ret = snd_soc_component_update_bits(component, 438 CS48L32_ADC1R_ANA_CONTROL1, 439 CS48L32_ADC1x_INT_ENA_FRC_MASK, 440 0); 441 if (ret < 0) { 442 dev_err(component->dev, 443 "Failed to clear ADC1R_INT_ENA_FRC: %d\n", ret); 444 return ret; 445 } 446 447 if (result > 0) 448 snd_soc_dapm_mux_update_power(dapm, kcontrol, mode, e, NULL); 449 450 return result; 451 case 1: 452 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 453 default: 454 return -EINVAL; 455 } 456 } 457 458 static SOC_ENUM_SINGLE_DECL(cs48l32_in1dmode_enum, 459 CS48L32_INPUT1_CONTROL1, 460 CS48L32_IN1_MODE_SHIFT, 461 cs48l32_dmode_texts); 462 463 static const struct snd_kcontrol_new cs48l32_dmode_mux[] = { 464 SOC_DAPM_ENUM_EXT("IN1 Mode", cs48l32_in1dmode_enum, 465 snd_soc_dapm_get_enum_double, cs48l32_dmode_put), 466 }; 467 468 static const char * const cs48l32_in_texts[] = { 469 "IN1L", "IN1R", "IN2L", "IN2R", 470 }; 471 static_assert(ARRAY_SIZE(cs48l32_in_texts) == CS48L32_MAX_INPUT); 472 473 static const char * const cs48l32_us_freq_texts[] = { 474 "16-24kHz", "20-28kHz", 475 }; 476 477 static const unsigned int cs48l32_us_freq_val[] = { 478 0x2, 0x3, 479 }; 480 481 static const struct soc_enum cs48l32_us_freq[] = { 482 SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, 483 CS48L32_US1_FREQ_SHIFT, 484 CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, 485 ARRAY_SIZE(cs48l32_us_freq_val), 486 cs48l32_us_freq_texts, 487 cs48l32_us_freq_val), 488 SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, 489 CS48L32_US1_FREQ_SHIFT, 490 CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, 491 ARRAY_SIZE(cs48l32_us_freq_val), 492 cs48l32_us_freq_texts, 493 cs48l32_us_freq_val), 494 }; 495 496 static const unsigned int cs48l32_us_in_val[] = { 497 0x0, 0x1, 0x2, 0x3, 498 }; 499 500 static const struct soc_enum cs48l32_us_inmux_enum[] = { 501 SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, 502 CS48L32_US1_SRC_SHIFT, 503 CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, 504 ARRAY_SIZE(cs48l32_us_in_val), 505 cs48l32_in_texts, 506 cs48l32_us_in_val), 507 SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, 508 CS48L32_US1_SRC_SHIFT, 509 CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, 510 ARRAY_SIZE(cs48l32_us_in_val), 511 cs48l32_in_texts, 512 cs48l32_us_in_val), 513 }; 514 515 static const struct snd_kcontrol_new cs48l32_us_inmux[] = { 516 SOC_DAPM_ENUM("Ultrasonic 1 Input", cs48l32_us_inmux_enum[0]), 517 SOC_DAPM_ENUM("Ultrasonic 2 Input", cs48l32_us_inmux_enum[1]), 518 }; 519 520 static const char * const cs48l32_us_det_thr_texts[] = { 521 "-6dB", "-9dB", "-12dB", "-15dB", "-18dB", "-21dB", "-24dB", "-27dB", 522 }; 523 524 static const struct soc_enum cs48l32_us_det_thr[] = { 525 SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, 526 CS48L32_US1_DET_THR_SHIFT, 527 ARRAY_SIZE(cs48l32_us_det_thr_texts), 528 cs48l32_us_det_thr_texts), 529 SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, 530 CS48L32_US1_DET_THR_SHIFT, 531 ARRAY_SIZE(cs48l32_us_det_thr_texts), 532 cs48l32_us_det_thr_texts), 533 }; 534 535 static const char * const cs48l32_us_det_num_texts[] = { 536 "1 Sample", 537 "2 Samples", 538 "4 Samples", 539 "8 Samples", 540 "16 Samples", 541 "32 Samples", 542 "64 Samples", 543 "128 Samples", 544 "256 Samples", 545 "512 Samples", 546 "1024 Samples", 547 "2048 Samples", 548 "4096 Samples", 549 "8192 Samples", 550 "16384 Samples", 551 "32768 Samples", 552 }; 553 554 static const struct soc_enum cs48l32_us_det_num[] = { 555 SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, 556 CS48L32_US1_DET_NUM_SHIFT, 557 ARRAY_SIZE(cs48l32_us_det_num_texts), 558 cs48l32_us_det_num_texts), 559 SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, 560 CS48L32_US1_DET_NUM_SHIFT, 561 ARRAY_SIZE(cs48l32_us_det_num_texts), 562 cs48l32_us_det_num_texts), 563 }; 564 565 static const char * const cs48l32_us_det_hold_texts[] = { 566 "0 Samples", 567 "31 Samples", 568 "63 Samples", 569 "127 Samples", 570 "255 Samples", 571 "511 Samples", 572 "1023 Samples", 573 "2047 Samples", 574 "4095 Samples", 575 "8191 Samples", 576 "16383 Samples", 577 "32767 Samples", 578 "65535 Samples", 579 "131071 Samples", 580 "262143 Samples", 581 "524287 Samples", 582 }; 583 584 static const struct soc_enum cs48l32_us_det_hold[] = { 585 SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, 586 CS48L32_US1_DET_HOLD_SHIFT, 587 ARRAY_SIZE(cs48l32_us_det_hold_texts), 588 cs48l32_us_det_hold_texts), 589 SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, 590 CS48L32_US1_DET_HOLD_SHIFT, 591 ARRAY_SIZE(cs48l32_us_det_hold_texts), 592 cs48l32_us_det_hold_texts), 593 }; 594 595 static const struct soc_enum cs48l32_us_output_rate[] = { 596 SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, 597 CS48L32_US1_RATE_SHIFT, 598 CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, 599 ARRAY_SIZE(cs48l32_rate_text), 600 cs48l32_rate_text, 601 cs48l32_rate_val), 602 SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, 603 CS48L32_US1_RATE_SHIFT, 604 CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, 605 ARRAY_SIZE(cs48l32_rate_text), 606 cs48l32_rate_text, 607 cs48l32_rate_val), 608 }; 609 610 static const char * const cs48l32_us_det_lpf_cut_texts[] = { 611 "1722Hz", "833Hz", "408Hz", "203Hz", 612 }; 613 614 static const struct soc_enum cs48l32_us_det_lpf_cut[] = { 615 SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, 616 CS48L32_US1_DET_LPF_CUT_SHIFT, 617 ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), 618 cs48l32_us_det_lpf_cut_texts), 619 SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, 620 CS48L32_US1_DET_LPF_CUT_SHIFT, 621 ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), 622 cs48l32_us_det_lpf_cut_texts), 623 }; 624 625 static const char * const cs48l32_us_det_dcy_texts[] = { 626 "0 ms", "0.79 ms", "1.58 ms", "3.16 ms", "6.33 ms", "12.67 ms", "25.34 ms", "50.69 ms", 627 }; 628 629 static const struct soc_enum cs48l32_us_det_dcy[] = { 630 SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, 631 CS48L32_US1_DET_DCY_SHIFT, 632 ARRAY_SIZE(cs48l32_us_det_dcy_texts), 633 cs48l32_us_det_dcy_texts), 634 SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, 635 CS48L32_US1_DET_DCY_SHIFT, 636 ARRAY_SIZE(cs48l32_us_det_dcy_texts), 637 cs48l32_us_det_dcy_texts), 638 }; 639 640 static const struct snd_kcontrol_new cs48l32_us_switch[] = { 641 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 642 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 643 }; 644 645 static const char * const cs48l32_vol_ramp_text[] = { 646 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", "16ms/6dB", "32ms/6dB", 647 }; 648 649 static SOC_ENUM_SINGLE_DECL(cs48l32_in_vd_ramp, 650 CS48L32_INPUT_VOL_CONTROL, 651 CS48L32_IN_VD_RAMP_SHIFT, 652 cs48l32_vol_ramp_text); 653 654 static SOC_ENUM_SINGLE_DECL(cs48l32_in_vi_ramp, 655 CS48L32_INPUT_VOL_CONTROL, 656 CS48L32_IN_VI_RAMP_SHIFT, 657 cs48l32_vol_ramp_text); 658 659 static const char * const cs48l32_in_hpf_cut_text[] = { 660 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz" 661 }; 662 663 static SOC_ENUM_SINGLE_DECL(cs48l32_in_hpf_cut_enum, 664 CS48L32_INPUT_HPF_CONTROL, 665 CS48L32_IN_HPF_CUT_SHIFT, 666 cs48l32_in_hpf_cut_text); 667 668 static const char * const cs48l32_in_dmic_osr_text[] = { 669 "384kHz", "768kHz", "1.536MHz", "2.048MHz", "2.4576MHz", "3.072MHz", "6.144MHz", 670 }; 671 672 static const struct soc_enum cs48l32_in_dmic_osr[] = { 673 SOC_ENUM_SINGLE(CS48L32_INPUT1_CONTROL1, 674 CS48L32_IN1_OSR_SHIFT, 675 ARRAY_SIZE(cs48l32_in_dmic_osr_text), 676 cs48l32_in_dmic_osr_text), 677 SOC_ENUM_SINGLE(CS48L32_INPUT2_CONTROL1, 678 CS48L32_IN1_OSR_SHIFT, 679 ARRAY_SIZE(cs48l32_in_dmic_osr_text), 680 cs48l32_in_dmic_osr_text), 681 }; 682 683 static bool cs48l32_is_input_enabled(struct snd_soc_component *component, 684 unsigned int reg) 685 { 686 unsigned int input_active; 687 688 input_active = snd_soc_component_read(component, CS48L32_INPUT_CONTROL); 689 switch (reg) { 690 case CS48L32_IN1L_CONTROL1: 691 return input_active & BIT(CS48L32_IN1L_EN_SHIFT); 692 case CS48L32_IN1R_CONTROL1: 693 return input_active & BIT(CS48L32_IN1R_EN_SHIFT); 694 case CS48L32_IN2L_CONTROL1: 695 return input_active & BIT(CS48L32_IN2L_EN_SHIFT); 696 case CS48L32_IN2R_CONTROL1: 697 return input_active & BIT(CS48L32_IN2R_EN_SHIFT); 698 default: 699 return false; 700 } 701 } 702 703 static int cs48l32_in_rate_put(struct snd_kcontrol *kcontrol, 704 struct snd_ctl_elem_value *ucontrol) 705 { 706 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 707 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 708 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 709 int ret; 710 711 snd_soc_dapm_mutex_lock(dapm); 712 713 /* Cannot change rate on an active input */ 714 if (cs48l32_is_input_enabled(component, e->reg)) { 715 ret = -EBUSY; 716 goto exit; 717 } 718 719 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 720 exit: 721 snd_soc_dapm_mutex_unlock(dapm); 722 723 return ret; 724 } 725 726 static const struct soc_enum cs48l32_input_rate[] = { 727 SOC_VALUE_ENUM_SINGLE(CS48L32_IN1L_CONTROL1, 728 CS48L32_INx_RATE_SHIFT, 729 CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, 730 ARRAY_SIZE(cs48l32_rate_text), 731 cs48l32_rate_text, 732 cs48l32_rate_val), 733 SOC_VALUE_ENUM_SINGLE(CS48L32_IN1R_CONTROL1, 734 CS48L32_INx_RATE_SHIFT, 735 CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, 736 ARRAY_SIZE(cs48l32_rate_text), 737 cs48l32_rate_text, 738 cs48l32_rate_val), 739 SOC_VALUE_ENUM_SINGLE(CS48L32_IN2L_CONTROL1, 740 CS48L32_INx_RATE_SHIFT, 741 CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, 742 ARRAY_SIZE(cs48l32_rate_text), 743 cs48l32_rate_text, 744 cs48l32_rate_val), 745 SOC_VALUE_ENUM_SINGLE(CS48L32_IN2R_CONTROL1, 746 CS48L32_INx_RATE_SHIFT, 747 CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, 748 ARRAY_SIZE(cs48l32_rate_text), 749 cs48l32_rate_text, 750 cs48l32_rate_val), 751 }; 752 753 static int cs48l32_low_power_mode_put(struct snd_kcontrol *kcontrol, 754 struct snd_ctl_elem_value *ucontrol) 755 { 756 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 757 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 758 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 759 int ret; 760 761 snd_soc_dapm_mutex_lock(dapm); 762 763 /* Cannot change rate on an active input */ 764 if (cs48l32_is_input_enabled(component, mc->reg)) { 765 ret = -EBUSY; 766 goto exit; 767 } 768 769 ret = snd_soc_put_volsw(kcontrol, ucontrol); 770 771 exit: 772 snd_soc_dapm_mutex_unlock(dapm); 773 return ret; 774 } 775 776 static const struct soc_enum noise_gen_rate = 777 SOC_VALUE_ENUM_SINGLE(CS48L32_COMFORT_NOISE_GENERATOR, 778 CS48L32_NOISE_GEN_RATE_SHIFT, 779 CS48L32_NOISE_GEN_RATE_MASK >> CS48L32_NOISE_GEN_RATE_SHIFT, 780 ARRAY_SIZE(cs48l32_rate_text), 781 cs48l32_rate_text, 782 cs48l32_rate_val); 783 784 static const char * const cs48l32_auxpdm_freq_texts[] = { 785 "3.072MHz", "2.048MHz", "1.536MHz", "768kHz", 786 }; 787 788 static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_freq, 789 CS48L32_AUXPDM1_CONTROL1, 790 CS48L32_AUXPDM1_FREQ_SHIFT, 791 cs48l32_auxpdm_freq_texts); 792 793 static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_freq, 794 CS48L32_AUXPDM2_CONTROL1, 795 CS48L32_AUXPDM1_FREQ_SHIFT, 796 cs48l32_auxpdm_freq_texts); 797 798 static const char * const cs48l32_auxpdm_src_texts[] = { 799 "Analog", "IN1 Digital", "IN2 Digital", 800 }; 801 802 static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_in, 803 CS48L32_AUXPDM_CTRL2, 804 CS48L32_AUXPDMDAT1_SRC_SHIFT, 805 cs48l32_auxpdm_src_texts); 806 807 static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_in, 808 CS48L32_AUXPDM_CTRL2, 809 CS48L32_AUXPDMDAT2_SRC_SHIFT, 810 cs48l32_auxpdm_src_texts); 811 812 static const struct snd_kcontrol_new cs48l32_auxpdm_inmux[] = { 813 SOC_DAPM_ENUM("AUXPDM1 Input", cs48l32_auxpdm1_in), 814 SOC_DAPM_ENUM("AUXPDM2 Input", cs48l32_auxpdm2_in), 815 }; 816 817 static const unsigned int cs48l32_auxpdm_analog_in_val[] = { 818 0x0, 0x1, 819 }; 820 821 static const struct soc_enum cs48l32_auxpdm_analog_inmux_enum[] = { 822 SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM1_CONTROL1, 823 CS48L32_AUXPDM1_SRC_SHIFT, 824 CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, 825 ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), 826 cs48l32_in_texts, 827 cs48l32_auxpdm_analog_in_val), 828 SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM2_CONTROL1, 829 CS48L32_AUXPDM1_SRC_SHIFT, 830 CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, 831 ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), 832 cs48l32_in_texts, 833 cs48l32_auxpdm_analog_in_val), 834 }; 835 836 static const struct snd_kcontrol_new cs48l32_auxpdm_analog_inmux[] = { 837 SOC_DAPM_ENUM("AUXPDM1 Analog Input", cs48l32_auxpdm_analog_inmux_enum[0]), 838 SOC_DAPM_ENUM("AUXPDM2 Analog Input", cs48l32_auxpdm_analog_inmux_enum[1]), 839 }; 840 841 static const struct snd_kcontrol_new cs48l32_auxpdm_switch[] = { 842 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 843 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 844 }; 845 846 static const struct soc_enum cs48l32_isrc_fsh[] = { 847 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, 848 CS48L32_ISRC1_FSH_SHIFT, 849 CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, 850 ARRAY_SIZE(cs48l32_rate_text), 851 cs48l32_rate_text, 852 cs48l32_rate_val), 853 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, 854 CS48L32_ISRC1_FSH_SHIFT, 855 CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, 856 ARRAY_SIZE(cs48l32_rate_text), 857 cs48l32_rate_text, 858 cs48l32_rate_val), 859 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, 860 CS48L32_ISRC1_FSH_SHIFT, 861 CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, 862 ARRAY_SIZE(cs48l32_rate_text), 863 cs48l32_rate_text, 864 cs48l32_rate_val), 865 }; 866 867 static const struct soc_enum cs48l32_isrc_fsl[] = { 868 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, 869 CS48L32_ISRC1_FSL_SHIFT, 870 CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, 871 ARRAY_SIZE(cs48l32_rate_text), 872 cs48l32_rate_text, 873 cs48l32_rate_val), 874 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, 875 CS48L32_ISRC1_FSL_SHIFT, 876 CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, 877 ARRAY_SIZE(cs48l32_rate_text), 878 cs48l32_rate_text, 879 cs48l32_rate_val), 880 SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, 881 CS48L32_ISRC1_FSL_SHIFT, 882 CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, 883 ARRAY_SIZE(cs48l32_rate_text), 884 cs48l32_rate_text, 885 cs48l32_rate_val), 886 }; 887 888 static const struct soc_enum cs48l32_fx_rate = 889 SOC_VALUE_ENUM_SINGLE(CS48L32_FX_SAMPLE_RATE, 890 CS48L32_FX_RATE_SHIFT, 891 CS48L32_FX_RATE_MASK >> CS48L32_FX_RATE_SHIFT, 892 ARRAY_SIZE(cs48l32_rate_text), 893 cs48l32_rate_text, 894 cs48l32_rate_val); 895 896 static const char * const cs48l32_lhpf_mode_text[] = { 897 "Low-pass", "High-pass" 898 }; 899 900 static const struct soc_enum cs48l32_lhpf_mode[] = { 901 SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 0, 902 ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), 903 SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 1, 904 ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), 905 SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 2, 906 ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), 907 SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 3, 908 ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), 909 }; 910 911 static int cs48l32_lhpf_coeff_put(struct snd_kcontrol *kcontrol, 912 struct snd_ctl_elem_value *ucontrol) 913 { 914 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 915 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 916 __be32 *data = (__be32 *)ucontrol->value.bytes.data; 917 s16 val = (s16)be32_to_cpu(*data); 918 919 if (abs(val) > CS48L32_LHPF_MAX_COEFF) { 920 dev_err(cs48l32_codec->core.dev, "Rejecting unstable LHPF coefficients\n"); 921 return -EINVAL; 922 } 923 924 return snd_soc_bytes_put(kcontrol, ucontrol); 925 } 926 927 static const char * const cs48l32_eq_mode_text[] = { 928 "Low-pass", "High-pass", 929 }; 930 931 static const struct soc_enum cs48l32_eq_mode[] = { 932 SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 0, 933 ARRAY_SIZE(cs48l32_eq_mode_text), 934 cs48l32_eq_mode_text), 935 SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 1, 936 ARRAY_SIZE(cs48l32_eq_mode_text), 937 cs48l32_eq_mode_text), 938 SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 2, 939 ARRAY_SIZE(cs48l32_eq_mode_text), 940 cs48l32_eq_mode_text), 941 SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 3, 942 ARRAY_SIZE(cs48l32_eq_mode_text), 943 cs48l32_eq_mode_text), 944 }; 945 946 static int cs48l32_eq_mode_get(struct snd_kcontrol *kcontrol, 947 struct snd_ctl_elem_value *ucontrol) 948 { 949 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 950 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 951 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 952 unsigned int item; 953 954 item = snd_soc_enum_val_to_item(e, cs48l32_codec->eq_mode[e->shift_l]); 955 ucontrol->value.enumerated.item[0] = item; 956 957 return 0; 958 } 959 960 static int cs48l32_eq_mode_put(struct snd_kcontrol *kcontrol, 961 struct snd_ctl_elem_value *ucontrol) 962 { 963 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 964 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 965 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 966 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 967 unsigned int *item = ucontrol->value.enumerated.item; 968 unsigned int val; 969 bool changed = false; 970 971 if (item[0] >= e->items) 972 return -EINVAL; 973 974 val = snd_soc_enum_item_to_val(e, item[0]); 975 976 snd_soc_dapm_mutex_lock(dapm); 977 if (cs48l32_codec->eq_mode[e->shift_l] != val) { 978 cs48l32_codec->eq_mode[e->shift_l] = val; 979 changed = true; 980 } 981 snd_soc_dapm_mutex_unlock(dapm); 982 983 return changed; 984 } 985 986 static int cs48l32_eq_coeff_info(struct snd_kcontrol *kcontrol, 987 struct snd_ctl_elem_info *uinfo) 988 { 989 struct cs48l32_eq_control *ctl = (void *) kcontrol->private_value; 990 991 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 992 uinfo->count = 1; 993 uinfo->value.integer.min = 0; 994 uinfo->value.integer.max = ctl->max; 995 996 return 0; 997 } 998 999 static int cs48l32_eq_coeff_get(struct snd_kcontrol *kcontrol, 1000 struct snd_ctl_elem_value *ucontrol) 1001 { 1002 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1003 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1004 struct cs48l32_eq_control *params = (void *)kcontrol->private_value; 1005 __be16 *coeffs; 1006 unsigned int coeff_idx; 1007 int block_idx; 1008 1009 block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); 1010 block_idx /= (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1); 1011 1012 coeffs = &cs48l32_codec->eq_coefficients[block_idx][0]; 1013 coeff_idx = (params->reg - params->block_base) / 2; 1014 1015 /* High __be16 is in [coeff_idx] and low __be16 in [coeff_idx + 1] */ 1016 if (params->shift == 0) 1017 coeff_idx++; 1018 1019 ucontrol->value.integer.value[0] = be16_to_cpu(coeffs[coeff_idx]); 1020 1021 return 0; 1022 } 1023 1024 static int cs48l32_eq_coeff_put(struct snd_kcontrol *kcontrol, 1025 struct snd_ctl_elem_value *ucontrol) 1026 { 1027 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1028 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1029 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1030 struct cs48l32_eq_control *params = (void *)kcontrol->private_value; 1031 __be16 *coeffs; 1032 unsigned int coeff_idx; 1033 int block_idx; 1034 1035 block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); 1036 block_idx /= (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1); 1037 1038 coeffs = &cs48l32_codec->eq_coefficients[block_idx][0]; 1039 coeff_idx = (params->reg - params->block_base) / 2; 1040 1041 /* Put high __be16 in [coeff_idx] and low __be16 in [coeff_idx + 1] */ 1042 if (params->shift == 0) 1043 coeff_idx++; 1044 1045 snd_soc_dapm_mutex_lock(dapm); 1046 coeffs[coeff_idx] = cpu_to_be16(ucontrol->value.integer.value[0]); 1047 snd_soc_dapm_mutex_unlock(dapm); 1048 1049 return 0; 1050 } 1051 1052 static const struct snd_kcontrol_new cs48l32_drc_activity_output_mux[] = { 1053 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 1054 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 1055 }; 1056 1057 static const struct snd_kcontrol_new cs48l32_dsp_trigger_output_mux[] = { 1058 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 1059 }; 1060 1061 static int cs48l32_dsp_rate_get(struct snd_kcontrol *kcontrol, 1062 struct snd_ctl_elem_value *ucontrol) 1063 { 1064 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1065 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1066 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 1067 unsigned int cached_rate; 1068 const unsigned int rate_num = e->mask; 1069 int item; 1070 1071 if (rate_num >= ARRAY_SIZE(cs48l32_codec->dsp_dma_rates)) 1072 return -EINVAL; 1073 1074 cached_rate = cs48l32_codec->dsp_dma_rates[rate_num]; 1075 item = snd_soc_enum_val_to_item(e, cached_rate); 1076 ucontrol->value.enumerated.item[0] = item; 1077 1078 return 0; 1079 } 1080 1081 static int cs48l32_dsp_rate_put(struct snd_kcontrol *kcontrol, 1082 struct snd_ctl_elem_value *ucontrol) 1083 { 1084 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1085 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1086 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1087 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; 1088 const unsigned int rate_num = e->mask; 1089 const unsigned int item = ucontrol->value.enumerated.item[0]; 1090 unsigned int val; 1091 bool changed = false; 1092 1093 if (item >= e->items) 1094 return -EINVAL; 1095 1096 if (rate_num >= ARRAY_SIZE(cs48l32_codec->dsp_dma_rates)) 1097 return -EINVAL; 1098 1099 val = snd_soc_enum_item_to_val(e, item); 1100 1101 snd_soc_dapm_mutex_lock(dapm); 1102 if (cs48l32_codec->dsp_dma_rates[rate_num] != val) { 1103 cs48l32_codec->dsp_dma_rates[rate_num] = val; 1104 changed = true; 1105 } 1106 snd_soc_dapm_mutex_unlock(dapm); 1107 1108 return changed; 1109 } 1110 1111 static const struct soc_enum cs48l32_dsp_rate_enum[] = { 1112 /* RX rates */ 1113 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1114 0, 1115 ARRAY_SIZE(cs48l32_rate_text), 1116 cs48l32_rate_text, cs48l32_rate_val), 1117 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1118 1, 1119 ARRAY_SIZE(cs48l32_rate_text), 1120 cs48l32_rate_text, cs48l32_rate_val), 1121 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1122 2, 1123 ARRAY_SIZE(cs48l32_rate_text), 1124 cs48l32_rate_text, cs48l32_rate_val), 1125 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1126 3, 1127 ARRAY_SIZE(cs48l32_rate_text), 1128 cs48l32_rate_text, cs48l32_rate_val), 1129 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1130 4, 1131 ARRAY_SIZE(cs48l32_rate_text), 1132 cs48l32_rate_text, cs48l32_rate_val), 1133 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1134 5, 1135 ARRAY_SIZE(cs48l32_rate_text), 1136 cs48l32_rate_text, cs48l32_rate_val), 1137 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1138 6, 1139 ARRAY_SIZE(cs48l32_rate_text), 1140 cs48l32_rate_text, cs48l32_rate_val), 1141 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1142 7, 1143 ARRAY_SIZE(cs48l32_rate_text), 1144 cs48l32_rate_text, cs48l32_rate_val), 1145 /* TX rates */ 1146 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1147 8, 1148 ARRAY_SIZE(cs48l32_rate_text), 1149 cs48l32_rate_text, cs48l32_rate_val), 1150 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1151 9, 1152 ARRAY_SIZE(cs48l32_rate_text), 1153 cs48l32_rate_text, cs48l32_rate_val), 1154 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1155 10, 1156 ARRAY_SIZE(cs48l32_rate_text), 1157 cs48l32_rate_text, cs48l32_rate_val), 1158 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1159 11, 1160 ARRAY_SIZE(cs48l32_rate_text), 1161 cs48l32_rate_text, cs48l32_rate_val), 1162 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1163 12, 1164 ARRAY_SIZE(cs48l32_rate_text), 1165 cs48l32_rate_text, cs48l32_rate_val), 1166 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1167 13, 1168 ARRAY_SIZE(cs48l32_rate_text), 1169 cs48l32_rate_text, cs48l32_rate_val), 1170 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1171 14, 1172 ARRAY_SIZE(cs48l32_rate_text), 1173 cs48l32_rate_text, cs48l32_rate_val), 1174 SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 1175 15, 1176 ARRAY_SIZE(cs48l32_rate_text), 1177 cs48l32_rate_text, cs48l32_rate_val), 1178 }; 1179 1180 static int cs48l32_dsp_pre_run(struct wm_adsp *dsp) 1181 { 1182 struct cs48l32_codec *cs48l32_codec = container_of(dsp, struct cs48l32_codec, dsp); 1183 unsigned int reg; 1184 const u8 *rate = cs48l32_codec->dsp_dma_rates; 1185 int i; 1186 1187 reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_RX1; 1188 for (i = 0; i < CS48L32_DSP_N_RX_CHANNELS; ++i) { 1189 regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); 1190 reg += 8; 1191 rate++; 1192 } 1193 1194 reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_TX1; 1195 for (i = 0; i < CS48L32_DSP_N_TX_CHANNELS; ++i) { 1196 regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); 1197 reg += 8; 1198 rate++; 1199 } 1200 1201 usleep_range(300, 600); 1202 1203 return 0; 1204 } 1205 1206 static void cs48l32_dsp_memory_disable(struct cs48l32_codec *cs48l32_codec, 1207 const struct cs48l32_dsp_power_regs *regs) 1208 { 1209 struct regmap *regmap = cs48l32_codec->core.regmap; 1210 int i, j, ret; 1211 1212 for (i = 0; i < regs->n_pwd; ++i) { 1213 ret = regmap_write(regmap, regs->pwd[i], 0); 1214 if (ret) 1215 goto err; 1216 } 1217 1218 for (i = 0; i < regs->n_ext; ++i) { 1219 for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { 1220 ret = regmap_write(regmap, j, 0); 1221 if (ret) 1222 goto err; 1223 } 1224 } 1225 1226 return; 1227 1228 err: 1229 dev_warn(cs48l32_codec->core.dev, "Failed to write SRAM enables (%d)\n", ret); 1230 } 1231 1232 static int cs48l32_dsp_memory_enable(struct cs48l32_codec *cs48l32_codec, 1233 const struct cs48l32_dsp_power_regs *regs) 1234 { 1235 struct regmap *regmap = cs48l32_codec->core.regmap; 1236 int i, j, ret; 1237 1238 /* disable power-off */ 1239 for (i = 0; i < regs->n_ext; ++i) { 1240 for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { 1241 ret = regmap_write(regmap, j, 0x3); 1242 if (ret) 1243 goto err; 1244 } 1245 } 1246 1247 /* power-up the banks in sequence */ 1248 for (i = 0; i < regs->n_pwd; ++i) { 1249 ret = regmap_write(regmap, regs->pwd[i], 0x1); 1250 if (ret) 1251 goto err; 1252 1253 udelay(1); /* allow bank to power-up */ 1254 1255 ret = regmap_write(regmap, regs->pwd[i], 0x3); 1256 if (ret) 1257 goto err; 1258 1259 udelay(1); /* allow bank to power-up */ 1260 } 1261 1262 return 0; 1263 1264 err: 1265 dev_err(cs48l32_codec->core.dev, "Failed to write SRAM enables (%d)\n", ret); 1266 cs48l32_dsp_memory_disable(cs48l32_codec, regs); 1267 1268 return ret; 1269 } 1270 1271 static int cs48l32_dsp_freq_update(struct snd_soc_dapm_widget *w, unsigned int freq_reg, 1272 unsigned int freqsel_reg) 1273 { 1274 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1275 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1276 struct regmap *regmap = cs48l32_codec->core.regmap; 1277 struct wm_adsp *dsp = &cs48l32_codec->dsp; 1278 int ret; 1279 unsigned int freq, freq_sel, freq_sts; 1280 1281 if (!freq_reg) 1282 return -EINVAL; 1283 1284 ret = regmap_read(regmap, freq_reg, &freq); 1285 if (ret) { 1286 dev_err(component->dev, "Failed to read #%x: %d\n", freq_reg, ret); 1287 return ret; 1288 } 1289 1290 if (freqsel_reg) { 1291 freq_sts = (freq & CS48L32_SYSCLK_FREQ_STS_MASK) >> CS48L32_SYSCLK_FREQ_STS_SHIFT; 1292 1293 ret = regmap_read(regmap, freqsel_reg, &freq_sel); 1294 if (ret) { 1295 dev_err(component->dev, "Failed to read #%x: %d\n", freqsel_reg, ret); 1296 return ret; 1297 } 1298 freq_sel = (freq_sel & CS48L32_SYSCLK_FREQ_MASK) >> CS48L32_SYSCLK_FREQ_SHIFT; 1299 1300 if (freq_sts != freq_sel) { 1301 dev_err(component->dev, "SYSCLK FREQ (#%x) != FREQ STS (#%x)\n", 1302 freq_sel, freq_sts); 1303 return -ETIMEDOUT; 1304 } 1305 } 1306 1307 freq &= CS48L32_DSP_CLK_FREQ_MASK; 1308 freq >>= CS48L32_DSP_CLK_FREQ_SHIFT; 1309 1310 ret = regmap_write(dsp->cs_dsp.regmap, 1311 dsp->cs_dsp.base + CS48L32_DSP_CLOCK_FREQ_OFFS, freq); 1312 if (ret) { 1313 dev_err(component->dev, "Failed to set HALO clock freq: %d\n", ret); 1314 return ret; 1315 } 1316 1317 return 0; 1318 } 1319 1320 static int cs48l32_dsp_freq_ev(struct snd_soc_dapm_widget *w, 1321 struct snd_kcontrol *kcontrol, int event) 1322 { 1323 switch (event) { 1324 case SND_SOC_DAPM_POST_PMU: 1325 return cs48l32_dsp_freq_update(w, CS48L32_SYSTEM_CLOCK2, CS48L32_SYSTEM_CLOCK1); 1326 default: 1327 return 0; 1328 } 1329 } 1330 1331 static irqreturn_t cs48l32_irq(int irq, void *data) 1332 { 1333 static const unsigned int eint1_regs[] = { 1334 CS48L32_IRQ1_EINT_9, CS48L32_IRQ1_MASK_9, 1335 CS48L32_IRQ1_EINT_7, CS48L32_IRQ1_MASK_7 1336 }; 1337 u32 reg_vals[4]; 1338 struct cs48l32_codec *cs48l32_codec = data; 1339 struct regmap *regmap = cs48l32_codec->core.regmap; 1340 irqreturn_t result = IRQ_NONE; 1341 unsigned int eint_pending; 1342 int i, ret; 1343 1344 static_assert(ARRAY_SIZE(eint1_regs) == ARRAY_SIZE(reg_vals)); 1345 1346 ret = pm_runtime_resume_and_get(cs48l32_codec->core.dev); 1347 if (ret) { 1348 dev_warn(cs48l32_codec->core.dev, "irq could not get pm runtime: %d\n", ret); 1349 return IRQ_NONE; 1350 } 1351 1352 ret = regmap_read(regmap, CS48L32_IRQ1_STATUS, &eint_pending); 1353 if (ret) { 1354 dev_warn(cs48l32_codec->core.dev, "Read IRQ1_STATUS failed: %d\n", ret); 1355 return IRQ_NONE; 1356 } 1357 if ((eint_pending & CS48L32_IRQ1_STS_MASK) == 0) 1358 goto out; 1359 1360 ret = regmap_multi_reg_read(regmap, eint1_regs, reg_vals, ARRAY_SIZE(reg_vals)); 1361 if (ret) { 1362 dev_warn(cs48l32_codec->core.dev, "Read IRQ regs failed: %d\n", ret); 1363 return IRQ_NONE; 1364 } 1365 1366 for (i = 0; i < ARRAY_SIZE(reg_vals); i += 2) { 1367 reg_vals[i] &= ~reg_vals[i + 1]; 1368 regmap_write(regmap, eint1_regs[i], reg_vals[i]); 1369 } 1370 1371 if (reg_vals[0] & CS48L32_DSP1_IRQ0_EINT1_MASK) 1372 wm_adsp_compr_handle_irq(&cs48l32_codec->dsp); 1373 1374 if (reg_vals[2] & CS48L32_DSP1_MPU_ERR_EINT1_MASK) { 1375 dev_warn(cs48l32_codec->core.dev, "MPU err IRQ\n"); 1376 wm_halo_bus_error(irq, &cs48l32_codec->dsp); 1377 } 1378 1379 if (reg_vals[2] & CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK) { 1380 dev_warn(cs48l32_codec->core.dev, "WDT expire IRQ\n"); 1381 wm_halo_wdt_expire(irq, &cs48l32_codec->dsp); 1382 } 1383 1384 result = IRQ_HANDLED; 1385 1386 out: 1387 pm_runtime_put_autosuspend(cs48l32_codec->core.dev); 1388 1389 return result; 1390 } 1391 1392 static int cs48l32_get_dspclk_setting(struct cs48l32_codec *cs48l32_codec, unsigned int freq, 1393 int src, unsigned int *val) 1394 { 1395 freq /= 15625; /* convert to 1/64ths of 1MHz */ 1396 *val |= freq << CS48L32_DSP_CLK_FREQ_SHIFT; 1397 1398 return 0; 1399 } 1400 1401 static int cs48l32_get_sysclk_setting(unsigned int freq) 1402 { 1403 switch (freq) { 1404 case 0: 1405 case 5644800: 1406 case 6144000: 1407 return CS48L32_SYSCLK_RATE_6MHZ; 1408 case 11289600: 1409 case 12288000: 1410 return CS48L32_SYSCLK_RATE_12MHZ << CS48L32_SYSCLK_FREQ_SHIFT; 1411 case 22579200: 1412 case 24576000: 1413 return CS48L32_SYSCLK_RATE_24MHZ << CS48L32_SYSCLK_FREQ_SHIFT; 1414 case 45158400: 1415 case 49152000: 1416 return CS48L32_SYSCLK_RATE_49MHZ << CS48L32_SYSCLK_FREQ_SHIFT; 1417 case 90316800: 1418 case 98304000: 1419 return CS48L32_SYSCLK_RATE_98MHZ << CS48L32_SYSCLK_FREQ_SHIFT; 1420 default: 1421 return -EINVAL; 1422 } 1423 } 1424 1425 static int cs48l32_set_pdm_fllclk(struct snd_soc_component *component, int source) 1426 { 1427 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1428 struct regmap *regmap = cs48l32_codec->core.regmap; 1429 unsigned int val; 1430 1431 switch (source) { 1432 case CS48L32_PDMCLK_SRC_IN1_PDMCLK: 1433 case CS48L32_PDMCLK_SRC_IN2_PDMCLK: 1434 case CS48L32_PDMCLK_SRC_IN3_PDMCLK: 1435 case CS48L32_PDMCLK_SRC_IN4_PDMCLK: 1436 case CS48L32_PDMCLK_SRC_AUXPDM1_CLK: 1437 case CS48L32_PDMCLK_SRC_AUXPDM2_CLK: 1438 val = source << CS48L32_PDM_FLLCLK_SRC_SHIFT; 1439 break; 1440 default: 1441 dev_err(cs48l32_codec->core.dev, "Invalid PDM FLLCLK src %d\n", source); 1442 return -EINVAL; 1443 } 1444 1445 return regmap_update_bits(regmap, CS48L32_INPUT_CONTROL2, 1446 CS48L32_PDM_FLLCLK_SRC_MASK, val); 1447 } 1448 1449 static int cs48l32_set_sysclk(struct snd_soc_component *component, int clk_id, int source, 1450 unsigned int freq, int dir) 1451 { 1452 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1453 struct regmap *regmap = cs48l32_codec->core.regmap; 1454 char *name; 1455 unsigned int reg; 1456 unsigned int mask = CS48L32_SYSCLK_SRC_MASK; 1457 unsigned int val = source << CS48L32_SYSCLK_SRC_SHIFT; 1458 int clk_freq_sel, *clk; 1459 1460 switch (clk_id) { 1461 case CS48L32_CLK_SYSCLK_1: 1462 name = "SYSCLK"; 1463 reg = CS48L32_SYSTEM_CLOCK1; 1464 clk = &cs48l32_codec->sysclk; 1465 clk_freq_sel = cs48l32_get_sysclk_setting(freq); 1466 mask |= CS48L32_SYSCLK_FREQ_MASK | CS48L32_SYSCLK_FRAC_MASK; 1467 break; 1468 case CS48L32_CLK_DSPCLK: 1469 name = "DSPCLK"; 1470 reg = CS48L32_DSP_CLOCK1; 1471 clk = &cs48l32_codec->dspclk; 1472 clk_freq_sel = cs48l32_get_dspclk_setting(cs48l32_codec, freq, source, &val); 1473 mask |= CS48L32_DSP_CLK_FREQ_MASK; 1474 break; 1475 case CS48L32_CLK_PDM_FLLCLK: 1476 return cs48l32_set_pdm_fllclk(component, source); 1477 default: 1478 return -EINVAL; 1479 } 1480 1481 if (clk_freq_sel < 0) { 1482 dev_err(cs48l32_codec->core.dev, "Failed to get %s setting for %dHZ\n", name, freq); 1483 return clk_freq_sel; 1484 } 1485 1486 *clk = freq; 1487 1488 if (freq == 0) { 1489 dev_dbg(cs48l32_codec->core.dev, "%s cleared\n", name); 1490 return 0; 1491 } 1492 1493 val |= clk_freq_sel; 1494 1495 if (freq % 6144000) 1496 val |= CS48L32_SYSCLK_FRAC_MASK; 1497 1498 dev_dbg(cs48l32_codec->core.dev, "%s set to %uHz", name, freq); 1499 1500 return regmap_update_bits(regmap, reg, mask, val); 1501 } 1502 1503 static int cs48l32_is_enabled_fll(struct cs48l32_fll *fll, int base) 1504 { 1505 struct regmap *regmap = fll->codec->core.regmap; 1506 unsigned int reg; 1507 int ret; 1508 1509 ret = regmap_read(regmap, base + CS48L32_FLL_CONTROL1_OFFS, ®); 1510 if (ret != 0) { 1511 cs48l32_fll_err(fll, "Failed to read current state: %d\n", ret); 1512 return ret; 1513 } 1514 1515 return reg & CS48L32_FLL_EN_MASK; 1516 } 1517 1518 static int cs48l32_wait_for_fll(struct cs48l32_fll *fll, bool requested) 1519 { 1520 struct regmap *regmap = fll->codec->core.regmap; 1521 unsigned int val = 0; 1522 int i; 1523 1524 cs48l32_fll_dbg(fll, "Waiting for FLL...\n"); 1525 1526 for (i = 0; i < 30; i++) { 1527 regmap_read(regmap, fll->sts_addr, &val); 1528 if (!!(val & fll->sts_mask) == requested) 1529 return 0; 1530 1531 switch (i) { 1532 case 0 ... 5: 1533 usleep_range(75, 125); 1534 break; 1535 case 6 ... 20: 1536 usleep_range(750, 1250); 1537 break; 1538 default: 1539 fsleep(20000); 1540 break; 1541 } 1542 } 1543 1544 cs48l32_fll_warn(fll, "Timed out waiting for %s\n", requested ? "lock" : "unlock"); 1545 1546 return -ETIMEDOUT; 1547 } 1548 1549 static int cs48l32_fllhj_disable(struct cs48l32_fll *fll) 1550 { 1551 struct cs48l32 *cs48l32 = &fll->codec->core; 1552 bool change; 1553 1554 cs48l32_fll_dbg(fll, "Disabling FLL\n"); 1555 1556 /* 1557 * Disable lockdet, but don't set ctrl_upd update bit. This allows the 1558 * lock status bit to clear as normal, but should the FLL be enabled 1559 * again due to a control clock being required, the lock won't re-assert 1560 * as the FLL config registers are automatically applied when the FLL 1561 * enables. 1562 */ 1563 regmap_set_bits(cs48l32->regmap, 1564 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1565 CS48L32_FLL_HOLD_MASK); 1566 regmap_clear_bits(cs48l32->regmap, 1567 fll->base + CS48L32_FLL_CONTROL2_OFFS, 1568 CS48L32_FLL_LOCKDET_MASK); 1569 regmap_set_bits(cs48l32->regmap, 1570 fll->base + CS48L32_FLL_CONTROL5_OFFS, 1571 CS48L32_FLL_FRC_INTEG_UPD_MASK); 1572 regmap_update_bits_check(cs48l32->regmap, 1573 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1574 CS48L32_FLL_EN_MASK, 1575 0, 1576 &change); 1577 1578 cs48l32_wait_for_fll(fll, false); 1579 1580 /* 1581 * ctrl_up gates the writes to all the fll's registers, setting it to 0 1582 * here ensures that after a runtime suspend/resume cycle when one 1583 * enables the fll then ctrl_up is the last bit that is configured 1584 * by the fll enable code rather than the cache sync operation which 1585 * would have updated it much earlier before writing out all fll 1586 * registers 1587 */ 1588 regmap_clear_bits(cs48l32->regmap, 1589 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1590 CS48L32_FLL_CTRL_UPD_MASK); 1591 1592 if (change) 1593 pm_runtime_put_autosuspend(cs48l32->dev); 1594 1595 return 0; 1596 } 1597 1598 static int cs48l32_fllhj_apply(struct cs48l32_fll *fll, int fin) 1599 { 1600 struct regmap *regmap = fll->codec->core.regmap; 1601 int refdiv, fref, fout, lockdet_thr, fbdiv, fllgcd; 1602 bool frac = false; 1603 unsigned int fll_n, min_n, max_n, ratio, theta, lambda, hp; 1604 unsigned int gains, num; 1605 1606 cs48l32_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout); 1607 1608 for (refdiv = 0; refdiv < 4; refdiv++) { 1609 if ((fin / (1 << refdiv)) <= CS48L32_FLLHJ_MAX_THRESH) 1610 break; 1611 } 1612 1613 fref = fin / (1 << refdiv); 1614 fout = fll->fout; 1615 frac = fout % fref; 1616 1617 /* 1618 * Use simple heuristic approach to find a configuration that 1619 * should work for most input clocks. 1620 */ 1621 if (fref < CS48L32_FLLHJ_LOW_THRESH) { 1622 lockdet_thr = 2; 1623 gains = CS48L32_FLLHJ_LOW_GAINS; 1624 1625 if (frac) 1626 fbdiv = 256; 1627 else 1628 fbdiv = 4; 1629 } else if (fref < CS48L32_FLLHJ_MID_THRESH) { 1630 lockdet_thr = 8; 1631 gains = CS48L32_FLLHJ_MID_GAINS; 1632 fbdiv = (frac) ? 16 : 2; 1633 } else { 1634 lockdet_thr = 8; 1635 gains = CS48L32_FLLHJ_HIGH_GAINS; 1636 fbdiv = 1; 1637 } 1638 /* Use high performance mode for fractional configurations. */ 1639 if (frac) { 1640 hp = 3; 1641 min_n = CS48L32_FLLHJ_FRAC_MIN_N; 1642 max_n = CS48L32_FLLHJ_FRAC_MAX_N; 1643 } else { 1644 if (fref < CS48L32_FLLHJ_LP_INT_MODE_THRESH) 1645 hp = 0; 1646 else 1647 hp = 1; 1648 1649 min_n = CS48L32_FLLHJ_INT_MIN_N; 1650 max_n = CS48L32_FLLHJ_INT_MAX_N; 1651 } 1652 1653 ratio = fout / fref; 1654 1655 cs48l32_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n", refdiv, fref, frac); 1656 1657 while (ratio / fbdiv < min_n) { 1658 fbdiv /= 2; 1659 if (fbdiv < min_n) { 1660 cs48l32_fll_err(fll, "FBDIV (%u) < minimum N (%u)\n", fbdiv, min_n); 1661 return -EINVAL; 1662 } 1663 } 1664 while (frac && (ratio / fbdiv > max_n)) { 1665 fbdiv *= 2; 1666 if (fbdiv >= 1024) { 1667 cs48l32_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv); 1668 return -EINVAL; 1669 } 1670 } 1671 1672 cs48l32_fll_dbg(fll, "lockdet=%d, hp=#%x, fbdiv:%d\n", lockdet_thr, hp, fbdiv); 1673 1674 /* Calculate N.K values */ 1675 fllgcd = gcd(fout, fbdiv * fref); 1676 num = fout / fllgcd; 1677 lambda = (fref * fbdiv) / fllgcd; 1678 fll_n = num / lambda; 1679 theta = num % lambda; 1680 1681 cs48l32_fll_dbg(fll, "fll_n=%d, gcd=%d, theta=%d, lambda=%d\n", 1682 fll_n, fllgcd, theta, lambda); 1683 1684 /* Some sanity checks before any registers are written. */ 1685 if (fll_n < min_n || fll_n > max_n) { 1686 cs48l32_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n", 1687 frac ? "fractional" : "integer", min_n, max_n, fll_n); 1688 return -EINVAL; 1689 } 1690 if (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) { 1691 cs48l32_fll_err(fll, "Invalid fbdiv for %s mode (%u)\n", 1692 frac ? "fractional" : "integer", fbdiv); 1693 return -EINVAL; 1694 } 1695 1696 /* clear the ctrl_upd bit to guarantee we write to it later. */ 1697 regmap_update_bits(regmap, 1698 fll->base + CS48L32_FLL_CONTROL2_OFFS, 1699 CS48L32_FLL_LOCKDET_THR_MASK | 1700 CS48L32_FLL_PHASEDET_MASK | 1701 CS48L32_FLL_REFCLK_DIV_MASK | 1702 CS48L32_FLL_N_MASK | 1703 CS48L32_FLL_CTRL_UPD_MASK, 1704 (lockdet_thr << CS48L32_FLL_LOCKDET_THR_SHIFT) | 1705 (1 << CS48L32_FLL_PHASEDET_SHIFT) | 1706 (refdiv << CS48L32_FLL_REFCLK_DIV_SHIFT) | 1707 (fll_n << CS48L32_FLL_N_SHIFT)); 1708 1709 regmap_update_bits(regmap, 1710 fll->base + CS48L32_FLL_CONTROL3_OFFS, 1711 CS48L32_FLL_LAMBDA_MASK | 1712 CS48L32_FLL_THETA_MASK, 1713 (lambda << CS48L32_FLL_LAMBDA_SHIFT) | 1714 (theta << CS48L32_FLL_THETA_SHIFT)); 1715 1716 regmap_update_bits(regmap, 1717 fll->base + CS48L32_FLL_CONTROL4_OFFS, 1718 (0xffff << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | 1719 CS48L32_FLL_HP_MASK | 1720 CS48L32_FLL_FB_DIV_MASK, 1721 (gains << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | 1722 (hp << CS48L32_FLL_HP_SHIFT) | 1723 (fbdiv << CS48L32_FLL_FB_DIV_SHIFT)); 1724 1725 return 0; 1726 } 1727 1728 static int cs48l32_fllhj_enable(struct cs48l32_fll *fll) 1729 { 1730 struct cs48l32 *cs48l32 = &fll->codec->core; 1731 int already_enabled = cs48l32_is_enabled_fll(fll, fll->base); 1732 int ret; 1733 1734 if (already_enabled < 0) 1735 return already_enabled; 1736 1737 if (!already_enabled) 1738 pm_runtime_get_sync(cs48l32->dev); 1739 1740 cs48l32_fll_dbg(fll, "Enabling FLL, initially %s\n", 1741 str_enabled_disabled(already_enabled)); 1742 1743 /* FLLn_HOLD must be set before configuring any registers */ 1744 regmap_set_bits(cs48l32->regmap, 1745 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1746 CS48L32_FLL_HOLD_MASK); 1747 1748 /* Apply refclk */ 1749 ret = cs48l32_fllhj_apply(fll, fll->ref_freq); 1750 if (ret) { 1751 cs48l32_fll_err(fll, "Failed to set FLL: %d\n", ret); 1752 goto out; 1753 } 1754 regmap_update_bits(cs48l32->regmap, 1755 fll->base + CS48L32_FLL_CONTROL2_OFFS, 1756 CS48L32_FLL_REFCLK_SRC_MASK, 1757 fll->ref_src << CS48L32_FLL_REFCLK_SRC_SHIFT); 1758 1759 regmap_set_bits(cs48l32->regmap, 1760 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1761 CS48L32_FLL_EN_MASK); 1762 1763 out: 1764 regmap_set_bits(cs48l32->regmap, 1765 fll->base + CS48L32_FLL_CONTROL2_OFFS, 1766 CS48L32_FLL_LOCKDET_MASK); 1767 1768 regmap_set_bits(cs48l32->regmap, 1769 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1770 CS48L32_FLL_CTRL_UPD_MASK); 1771 1772 /* Release the hold so that flln locks to external frequency */ 1773 regmap_clear_bits(cs48l32->regmap, 1774 fll->base + CS48L32_FLL_CONTROL1_OFFS, 1775 CS48L32_FLL_HOLD_MASK); 1776 1777 if (!already_enabled) 1778 cs48l32_wait_for_fll(fll, true); 1779 1780 return 0; 1781 } 1782 1783 static int cs48l32_fllhj_validate(struct cs48l32_fll *fll, 1784 unsigned int ref_in, 1785 unsigned int fout) 1786 { 1787 if (fout && !ref_in) { 1788 cs48l32_fll_err(fll, "fllout set without valid input clk\n"); 1789 return -EINVAL; 1790 } 1791 1792 if (fll->fout && fout != fll->fout) { 1793 cs48l32_fll_err(fll, "Can't change output on active FLL\n"); 1794 return -EINVAL; 1795 } 1796 1797 if (ref_in / CS48L32_FLL_MAX_REFDIV > CS48L32_FLLHJ_MAX_THRESH) { 1798 cs48l32_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in); 1799 return -EINVAL; 1800 } 1801 1802 if (fout > CS48L32_FLL_MAX_FOUT) { 1803 cs48l32_fll_err(fll, "Fout=%dMHz exceeds maximum %dMHz\n", 1804 fout, CS48L32_FLL_MAX_FOUT); 1805 return -EINVAL; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int cs48l32_fllhj_set_refclk(struct cs48l32_fll *fll, int source, 1812 unsigned int fin, unsigned int fout) 1813 { 1814 int ret = 0; 1815 1816 if (fll->ref_src == source && fll->ref_freq == fin && fll->fout == fout) 1817 return 0; 1818 1819 if (fin && fout && cs48l32_fllhj_validate(fll, fin, fout)) 1820 return -EINVAL; 1821 1822 fll->ref_src = source; 1823 fll->ref_freq = fin; 1824 fll->fout = fout; 1825 1826 if (fout) 1827 ret = cs48l32_fllhj_enable(fll); 1828 else 1829 cs48l32_fllhj_disable(fll); 1830 1831 return ret; 1832 } 1833 1834 static int cs48l32_init_fll(struct cs48l32_fll *fll) 1835 { 1836 fll->ref_src = CS48L32_FLL_SRC_NONE; 1837 1838 return 0; 1839 } 1840 1841 static int cs48l32_set_fll(struct snd_soc_component *component, int fll_id, 1842 int source, unsigned int fref, unsigned int fout) 1843 { 1844 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1845 1846 switch (fll_id) { 1847 case CS48L32_FLL1_REFCLK: 1848 break; 1849 default: 1850 return -EINVAL; 1851 } 1852 1853 return cs48l32_fllhj_set_refclk(&cs48l32_codec->fll, source, fref, fout); 1854 } 1855 1856 static int cs48l32_asp_dai_probe(struct snd_soc_dai *dai) 1857 { 1858 struct snd_soc_component *component = dai->component; 1859 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1860 struct regmap *regmap = cs48l32_codec->core.regmap; 1861 unsigned int pin_reg, last_pin_reg, hiz_reg; 1862 1863 switch (dai->id) { 1864 case 1: 1865 pin_reg = CS48L32_GPIO3_CTRL1; 1866 hiz_reg = CS48L32_ASP1_CONTROL3; 1867 break; 1868 case 2: 1869 pin_reg = CS48L32_GPIO7_CTRL1; 1870 hiz_reg = CS48L32_ASP2_CONTROL3; 1871 break; 1872 default: 1873 return -EINVAL; 1874 } 1875 1876 for (last_pin_reg = pin_reg + 12; pin_reg <= last_pin_reg; ++pin_reg) 1877 regmap_clear_bits(regmap, pin_reg, CS48L32_GPIOX_CTRL1_FN_MASK); 1878 1879 /* DOUT high-impendance when not transmitting */ 1880 regmap_set_bits(regmap, hiz_reg, CS48L32_ASP_DOUT_HIZ_MASK); 1881 1882 return 0; 1883 } 1884 1885 static int cs48l32_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1886 { 1887 struct snd_soc_component *component = dai->component; 1888 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 1889 struct regmap *regmap = cs48l32_codec->core.regmap; 1890 unsigned int val = 0U; 1891 unsigned int base = dai->driver->base; 1892 unsigned int mask = CS48L32_ASP_FMT_MASK | CS48L32_ASP_BCLK_INV_MASK | 1893 CS48L32_ASP_BCLK_MSTR_MASK | 1894 CS48L32_ASP_FSYNC_INV_MASK | 1895 CS48L32_ASP_FSYNC_MSTR_MASK; 1896 1897 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1898 case SND_SOC_DAIFMT_DSP_A: 1899 val |= (CS48L32_ASP_FMT_DSP_MODE_A << CS48L32_ASP_FMT_SHIFT); 1900 break; 1901 case SND_SOC_DAIFMT_DSP_B: 1902 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { 1903 cs48l32_asp_err(dai, "DSP_B cannot be clock consumer\n"); 1904 return -EINVAL; 1905 } 1906 val |= (CS48L32_ASP_FMT_DSP_MODE_B << CS48L32_ASP_FMT_SHIFT); 1907 break; 1908 case SND_SOC_DAIFMT_I2S: 1909 val |= (CS48L32_ASP_FMT_I2S_MODE << CS48L32_ASP_FMT_SHIFT); 1910 break; 1911 case SND_SOC_DAIFMT_LEFT_J: 1912 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { 1913 cs48l32_asp_err(dai, "LEFT_J cannot be clock consumer\n"); 1914 return -EINVAL; 1915 } 1916 val |= (CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE << CS48L32_ASP_FMT_SHIFT); 1917 break; 1918 default: 1919 cs48l32_asp_err(dai, "Unsupported DAI format %d\n", 1920 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1921 return -EINVAL; 1922 } 1923 1924 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1925 case SND_SOC_DAIFMT_BC_FC: 1926 break; 1927 case SND_SOC_DAIFMT_BC_FP: 1928 val |= CS48L32_ASP_FSYNC_MSTR_MASK; 1929 break; 1930 case SND_SOC_DAIFMT_BP_FC: 1931 val |= CS48L32_ASP_BCLK_MSTR_MASK; 1932 break; 1933 case SND_SOC_DAIFMT_BP_FP: 1934 val |= CS48L32_ASP_BCLK_MSTR_MASK; 1935 val |= CS48L32_ASP_FSYNC_MSTR_MASK; 1936 break; 1937 default: 1938 cs48l32_asp_err(dai, "Unsupported clock direction %d\n", 1939 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 1940 return -EINVAL; 1941 } 1942 1943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1944 case SND_SOC_DAIFMT_NB_NF: 1945 break; 1946 case SND_SOC_DAIFMT_IB_IF: 1947 val |= CS48L32_ASP_BCLK_INV_MASK; 1948 val |= CS48L32_ASP_FSYNC_INV_MASK; 1949 break; 1950 case SND_SOC_DAIFMT_IB_NF: 1951 val |= CS48L32_ASP_BCLK_INV_MASK; 1952 break; 1953 case SND_SOC_DAIFMT_NB_IF: 1954 val |= CS48L32_ASP_FSYNC_INV_MASK; 1955 break; 1956 default: 1957 return -EINVAL; 1958 } 1959 1960 regmap_update_bits(regmap, base + CS48L32_ASP_CONTROL2, mask, val); 1961 1962 return 0; 1963 } 1964 1965 static const struct { 1966 u32 freq; 1967 u32 id; 1968 } cs48l32_sclk_rates[] = { 1969 { 128000, 12 }, 1970 { 176400, 13 }, 1971 { 192000, 14 }, 1972 { 256000, 15 }, 1973 { 352800, 16 }, 1974 { 384000, 17 }, 1975 { 512000, 18 }, 1976 { 705600, 19 }, 1977 { 768000, 21 }, 1978 { 1024000, 23 }, 1979 { 1411200, 25 }, 1980 { 1536000, 27 }, 1981 { 2048000, 29 }, 1982 { 2822400, 31 }, 1983 { 3072000, 33 }, 1984 { 4096000, 36 }, 1985 { 5644800, 38 }, 1986 { 6144000, 40 }, 1987 { 8192000, 47 }, 1988 { 11289600, 49 }, 1989 { 12288000, 51 }, 1990 { 22579200, 57 }, 1991 { 24576000, 59 }, 1992 }; 1993 1994 #define CS48L32_48K_RATE_MASK 0x0e00fe 1995 #define CS48L32_44K1_RATE_MASK 0x00fe00 1996 #define CS48L32_RATE_MASK (CS48L32_48K_RATE_MASK | CS48L32_44K1_RATE_MASK) 1997 1998 static const unsigned int cs48l32_sr_vals[] = { 1999 0, 2000 12000, /* CS48L32_48K_RATE_MASK */ 2001 24000, /* CS48L32_48K_RATE_MASK */ 2002 48000, /* CS48L32_48K_RATE_MASK */ 2003 96000, /* CS48L32_48K_RATE_MASK */ 2004 192000, /* CS48L32_48K_RATE_MASK */ 2005 384000, /* CS48L32_48K_RATE_MASK */ 2006 768000, /* CS48L32_48K_RATE_MASK */ 2007 0, 2008 11025, /* CS48L32_44K1_RATE_MASK */ 2009 22050, /* CS48L32_44K1_RATE_MASK */ 2010 44100, /* CS48L32_44K1_RATE_MASK */ 2011 88200, /* CS48L32_44K1_RATE_MASK */ 2012 176400, /* CS48L32_44K1_RATE_MASK */ 2013 352800, /* CS48L32_44K1_RATE_MASK */ 2014 705600, /* CS48L32_44K1_RATE_MASK */ 2015 0, 2016 8000, /* CS48L32_48K_RATE_MASK */ 2017 16000, /* CS48L32_48K_RATE_MASK */ 2018 32000, /* CS48L32_48K_RATE_MASK */ 2019 }; 2020 2021 static const struct snd_pcm_hw_constraint_list cs48l32_constraint = { 2022 .count = ARRAY_SIZE(cs48l32_sr_vals), 2023 .list = cs48l32_sr_vals, 2024 }; 2025 2026 static int cs48l32_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 2027 { 2028 struct snd_soc_component *component = dai->component; 2029 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2030 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1]; 2031 unsigned int base_rate; 2032 2033 if (!substream->runtime) 2034 return 0; 2035 2036 switch (dai_priv->clk) { 2037 case CS48L32_CLK_SYSCLK_1: 2038 case CS48L32_CLK_SYSCLK_2: 2039 case CS48L32_CLK_SYSCLK_3: 2040 case CS48L32_CLK_SYSCLK_4: 2041 base_rate = cs48l32_codec->sysclk; 2042 break; 2043 default: 2044 return 0; 2045 } 2046 2047 if (base_rate == 0) 2048 dai_priv->constraint.mask = CS48L32_RATE_MASK; 2049 else if (base_rate % 4000) 2050 dai_priv->constraint.mask = CS48L32_44K1_RATE_MASK; 2051 else 2052 dai_priv->constraint.mask = CS48L32_48K_RATE_MASK; 2053 2054 return snd_pcm_hw_constraint_list(substream->runtime, 0, 2055 SNDRV_PCM_HW_PARAM_RATE, 2056 &dai_priv->constraint); 2057 } 2058 2059 static int cs48l32_hw_params_rate(struct snd_pcm_substream *substream, 2060 struct snd_pcm_hw_params *params, 2061 struct snd_soc_dai *dai) 2062 { 2063 struct snd_soc_component *component = dai->component; 2064 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2065 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1]; 2066 unsigned int sr_val, sr_reg, rate; 2067 2068 rate = params_rate(params); 2069 for (sr_val = 0; sr_val < ARRAY_SIZE(cs48l32_sr_vals); sr_val++) 2070 if (cs48l32_sr_vals[sr_val] == rate) 2071 break; 2072 2073 if (sr_val == ARRAY_SIZE(cs48l32_sr_vals)) { 2074 cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); 2075 return -EINVAL; 2076 } 2077 2078 switch (dai_priv->clk) { 2079 case CS48L32_CLK_SYSCLK_1: 2080 sr_reg = CS48L32_SAMPLE_RATE1; 2081 break; 2082 case CS48L32_CLK_SYSCLK_2: 2083 sr_reg = CS48L32_SAMPLE_RATE2; 2084 break; 2085 case CS48L32_CLK_SYSCLK_3: 2086 sr_reg = CS48L32_SAMPLE_RATE3; 2087 break; 2088 case CS48L32_CLK_SYSCLK_4: 2089 sr_reg = CS48L32_SAMPLE_RATE4; 2090 break; 2091 default: 2092 return -EINVAL; 2093 } 2094 2095 snd_soc_component_update_bits(component, sr_reg, CS48L32_SAMPLE_RATE_1_MASK, sr_val); 2096 2097 return 0; 2098 } 2099 2100 static bool cs48l32_asp_cfg_changed(struct snd_soc_component *component, 2101 unsigned int base, unsigned int sclk, 2102 unsigned int slotws, unsigned int dataw) 2103 { 2104 unsigned int val; 2105 2106 val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL1); 2107 if (sclk != (val & CS48L32_ASP_BCLK_FREQ_MASK)) 2108 return true; 2109 2110 val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); 2111 if (slotws != (val & (CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK))) 2112 return true; 2113 2114 val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL1); 2115 if (dataw != (val & (CS48L32_ASP_TX_WL_MASK))) 2116 return true; 2117 2118 val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL5); 2119 if (dataw != (val & (CS48L32_ASP_RX_WL_MASK))) 2120 return true; 2121 2122 return false; 2123 } 2124 2125 static int cs48l32_hw_params(struct snd_pcm_substream *substream, 2126 struct snd_pcm_hw_params *params, 2127 struct snd_soc_dai *dai) 2128 { 2129 struct snd_soc_component *component = dai->component; 2130 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2131 struct regmap *regmap = cs48l32_codec->core.regmap; 2132 int base = dai->driver->base; 2133 int dai_id = dai->id - 1; 2134 unsigned int rate = params_rate(params); 2135 unsigned int dataw = snd_pcm_format_width(params_format(params)); 2136 unsigned int asp_state = 0; 2137 int sclk, sclk_target; 2138 unsigned int slotw, n_slots, n_slots_multiple, val; 2139 int i, ret; 2140 2141 cs48l32_asp_dbg(dai, "hwparams in: ch:%u dataw:%u rate:%u\n", 2142 params_channels(params), dataw, rate); 2143 /* 2144 * The following calculations hold only under the assumption that 2145 * symmetric_[rates|channels|samplebits] are set to 1 2146 */ 2147 if (cs48l32_codec->tdm_slots[dai_id]) { 2148 n_slots = cs48l32_codec->tdm_slots[dai_id]; 2149 slotw = cs48l32_codec->tdm_width[dai_id]; 2150 } else { 2151 n_slots = params_channels(params); 2152 slotw = dataw; 2153 } 2154 2155 val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); 2156 val = (val & CS48L32_ASP_FMT_MASK) >> CS48L32_ASP_FMT_SHIFT; 2157 if (val == CS48L32_ASP_FMT_I2S_MODE) 2158 n_slots_multiple = 2; 2159 else 2160 n_slots_multiple = 1; 2161 2162 sclk_target = snd_soc_tdm_params_to_bclk(params, slotw, n_slots, n_slots_multiple); 2163 if (sclk_target < 0) { 2164 cs48l32_asp_err(dai, "Invalid parameters\n"); 2165 return sclk_target; 2166 } 2167 2168 for (i = 0; i < ARRAY_SIZE(cs48l32_sclk_rates); i++) { 2169 if ((cs48l32_sclk_rates[i].freq >= sclk_target) && 2170 (cs48l32_sclk_rates[i].freq % rate == 0)) { 2171 sclk = cs48l32_sclk_rates[i].id; 2172 break; 2173 } 2174 } 2175 if (i == ARRAY_SIZE(cs48l32_sclk_rates)) { 2176 cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); 2177 return -EINVAL; 2178 } 2179 2180 cs48l32_asp_dbg(dai, "hwparams out: n_slots:%u dataw:%u slotw:%u bclk:%u bclkid:%u\n", 2181 n_slots, dataw, slotw, sclk_target, sclk); 2182 2183 slotw = (slotw << CS48L32_ASP_TX_WIDTH_SHIFT) | 2184 (slotw << CS48L32_ASP_RX_WIDTH_SHIFT); 2185 2186 if (!cs48l32_asp_cfg_changed(component, base, sclk, slotw, dataw)) 2187 return cs48l32_hw_params_rate(substream, params, dai); 2188 2189 /* ASP must be disabled while changing configuration */ 2190 asp_state = snd_soc_component_read(component, base + CS48L32_ASP_ENABLES1); 2191 regmap_clear_bits(regmap, base + CS48L32_ASP_ENABLES1, 0xff00ff); 2192 2193 ret = cs48l32_hw_params_rate(substream, params, dai); 2194 if (ret != 0) 2195 goto restore_asp; 2196 2197 regmap_update_bits_async(regmap, 2198 base + CS48L32_ASP_CONTROL1, 2199 CS48L32_ASP_BCLK_FREQ_MASK, 2200 sclk); 2201 regmap_update_bits_async(regmap, 2202 base + CS48L32_ASP_CONTROL2, 2203 CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK, 2204 slotw); 2205 regmap_update_bits_async(regmap, 2206 base + CS48L32_ASP_DATA_CONTROL1, 2207 CS48L32_ASP_TX_WL_MASK, 2208 dataw); 2209 regmap_update_bits(regmap, 2210 base + CS48L32_ASP_DATA_CONTROL5, 2211 CS48L32_ASP_RX_WL_MASK, 2212 dataw); 2213 2214 restore_asp: 2215 /* Restore ASP TX/RX enable state */ 2216 regmap_update_bits(regmap, 2217 base + CS48L32_ASP_ENABLES1, 2218 0xff00ff, 2219 asp_state); 2220 return ret; 2221 } 2222 2223 static const char *cs48l32_dai_clk_str(int clk_id) 2224 { 2225 switch (clk_id) { 2226 case CS48L32_CLK_SYSCLK_1: 2227 case CS48L32_CLK_SYSCLK_2: 2228 case CS48L32_CLK_SYSCLK_3: 2229 case CS48L32_CLK_SYSCLK_4: 2230 return "SYSCLK"; 2231 default: 2232 return "Unknown clock"; 2233 } 2234 } 2235 2236 static int cs48l32_dai_set_sysclk(struct snd_soc_dai *dai, 2237 int clk_id, unsigned int freq, int dir) 2238 { 2239 struct snd_soc_component *component = dai->component; 2240 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2241 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1]; 2242 unsigned int base = dai->driver->base; 2243 unsigned int current_asp_rate, target_asp_rate; 2244 int ret; 2245 2246 if (clk_id == dai_priv->clk) 2247 return 0; 2248 2249 if (snd_soc_dai_active(dai)) { 2250 cs48l32_asp_err(dai, "Can't change clock on active DAI\n"); 2251 return -EBUSY; 2252 } 2253 2254 switch (clk_id) { 2255 case CS48L32_CLK_SYSCLK_1: 2256 target_asp_rate = 0U << CS48L32_ASP_RATE_SHIFT; 2257 break; 2258 case CS48L32_CLK_SYSCLK_2: 2259 target_asp_rate = 1U << CS48L32_ASP_RATE_SHIFT; 2260 break; 2261 case CS48L32_CLK_SYSCLK_3: 2262 target_asp_rate = 2U << CS48L32_ASP_RATE_SHIFT; 2263 break; 2264 case CS48L32_CLK_SYSCLK_4: 2265 target_asp_rate = 3U << CS48L32_ASP_RATE_SHIFT; 2266 break; 2267 default: 2268 return -EINVAL; 2269 } 2270 2271 dai_priv->clk = clk_id; 2272 cs48l32_asp_dbg(dai, "Setting to %s\n", cs48l32_dai_clk_str(clk_id)); 2273 2274 if (base) { 2275 ret = regmap_read(cs48l32_codec->core.regmap, 2276 base + CS48L32_ASP_CONTROL1, 2277 ¤t_asp_rate); 2278 if (ret != 0) { 2279 cs48l32_asp_err(dai, "Failed to check rate: %d\n", ret); 2280 return ret; 2281 } 2282 2283 if ((current_asp_rate & CS48L32_ASP_RATE_MASK) != 2284 (target_asp_rate & CS48L32_ASP_RATE_MASK)) { 2285 /* Guard the rate change with SYSCLK cycles */ 2286 scoped_guard(mutex, &cs48l32_codec->rate_lock) { 2287 cs48l32_spin_sysclk(cs48l32_codec); 2288 snd_soc_component_update_bits(component, 2289 base + CS48L32_ASP_CONTROL1, 2290 CS48L32_ASP_RATE_MASK, 2291 target_asp_rate); 2292 cs48l32_spin_sysclk(cs48l32_codec); 2293 } 2294 } 2295 } 2296 2297 return 0; 2298 } 2299 2300 static void cs48l32_set_channels_to_mask(struct snd_soc_dai *dai, 2301 unsigned int base, 2302 int channels, unsigned int mask) 2303 { 2304 struct snd_soc_component *component = dai->component; 2305 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2306 struct regmap *regmap = cs48l32_codec->core.regmap; 2307 int slot, i, j = 0, shift; 2308 unsigned int frame_ctls[2] = {0, 0}; 2309 2310 for (i = 0; i < channels; ++i) { 2311 slot = ffs(mask) - 1; 2312 if (slot < 0) 2313 return; 2314 2315 if (i - (j * 4) >= 4) { 2316 ++j; 2317 if (j >= 2) 2318 break; 2319 } 2320 2321 shift = (8 * (i - j * 4)); 2322 2323 frame_ctls[j] |= slot << shift; 2324 2325 mask &= ~(1 << slot); /* ? mask ^= 1 << slot ? */ 2326 } 2327 2328 regmap_write(regmap, base, frame_ctls[0]); 2329 regmap_write(regmap, base + 0x4, frame_ctls[1]); 2330 2331 if (mask) 2332 cs48l32_asp_warn(dai, "Too many channels in TDM mask\n"); 2333 } 2334 2335 static int cs48l32_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2336 unsigned int rx_mask, int slots, int slot_width) 2337 { 2338 struct snd_soc_component *component = dai->component; 2339 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2340 int base = dai->driver->base; 2341 int rx_max_chan = dai->driver->playback.channels_max; 2342 int tx_max_chan = dai->driver->capture.channels_max; 2343 2344 /* Only support TDM for the physical ASPs */ 2345 if (dai->id > CS48L32_MAX_ASP) 2346 return -EINVAL; 2347 2348 if (slots == 0) { 2349 tx_mask = (1 << tx_max_chan) - 1; 2350 rx_mask = (1 << rx_max_chan) - 1; 2351 } 2352 2353 cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL1, 2354 tx_max_chan, tx_mask); 2355 cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL5, 2356 rx_max_chan, rx_mask); 2357 2358 cs48l32_codec->tdm_width[dai->id - 1] = slot_width; 2359 cs48l32_codec->tdm_slots[dai->id - 1] = slots; 2360 2361 return 0; 2362 } 2363 2364 static const struct snd_soc_dai_ops cs48l32_dai_ops = { 2365 .probe = &cs48l32_asp_dai_probe, 2366 .startup = &cs48l32_startup, 2367 .set_fmt = &cs48l32_set_fmt, 2368 .set_tdm_slot = &cs48l32_set_tdm_slot, 2369 .hw_params = &cs48l32_hw_params, 2370 .set_sysclk = &cs48l32_dai_set_sysclk, 2371 }; 2372 2373 static int cs48l32_sysclk_ev(struct snd_soc_dapm_widget *w, 2374 struct snd_kcontrol *kcontrol, int event) 2375 { 2376 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2377 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2378 2379 cs48l32_spin_sysclk(cs48l32_codec); 2380 2381 return 0; 2382 } 2383 2384 static int cs48l32_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) 2385 { 2386 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2387 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2388 unsigned int reg; 2389 2390 if (w->shift % 2) 2391 reg = CS48L32_IN1L_CONTROL2; 2392 else 2393 reg = CS48L32_IN1R_CONTROL2; 2394 2395 reg += (w->shift / 2) * (CS48L32_IN2L_CONTROL2 - CS48L32_IN1L_CONTROL2); 2396 2397 switch (event) { 2398 case SND_SOC_DAPM_PRE_PMU: 2399 switch (w->shift) { 2400 case CS48L32_IN1L_EN_SHIFT: 2401 snd_soc_component_update_bits(component, 2402 CS48L32_ADC1L_ANA_CONTROL1, 2403 CS48L32_ADC1x_INT_ENA_FRC_MASK, 2404 CS48L32_ADC1x_INT_ENA_FRC_MASK); 2405 break; 2406 case CS48L32_IN1R_EN_SHIFT: 2407 snd_soc_component_update_bits(component, 2408 CS48L32_ADC1R_ANA_CONTROL1, 2409 CS48L32_ADC1x_INT_ENA_FRC_MASK, 2410 CS48L32_ADC1x_INT_ENA_FRC_MASK); 2411 break; 2412 default: 2413 break; 2414 } 2415 cs48l32_codec->in_up_pending++; 2416 break; 2417 case SND_SOC_DAPM_POST_PMU: 2418 usleep_range(200, 300); 2419 2420 switch (w->shift) { 2421 case CS48L32_IN1L_EN_SHIFT: 2422 snd_soc_component_update_bits(component, 2423 CS48L32_ADC1L_ANA_CONTROL1, 2424 CS48L32_ADC1x_INT_ENA_FRC_MASK, 2425 0); 2426 break; 2427 case CS48L32_IN1R_EN_SHIFT: 2428 snd_soc_component_update_bits(component, 2429 CS48L32_ADC1R_ANA_CONTROL1, 2430 CS48L32_ADC1x_INT_ENA_FRC_MASK, 2431 0); 2432 break; 2433 2434 default: 2435 break; 2436 } 2437 cs48l32_codec->in_up_pending--; 2438 snd_soc_component_update_bits(component, reg, CS48L32_INx_MUTE_MASK, 0); 2439 2440 /* Uncached write-only register, no need for update_bits */ 2441 if (!cs48l32_codec->in_up_pending) { 2442 snd_soc_component_write(component, cs48l32_codec->in_vu_reg, 2443 CS48L32_IN_VU_MASK); 2444 } 2445 break; 2446 case SND_SOC_DAPM_PRE_PMD: 2447 snd_soc_component_update_bits(component, reg, 2448 CS48L32_INx_MUTE_MASK, CS48L32_INx_MUTE_MASK); 2449 snd_soc_component_write(component, cs48l32_codec->in_vu_reg, 2450 CS48L32_IN_VU_MASK); 2451 break; 2452 default: 2453 break; 2454 } 2455 2456 return 0; 2457 } 2458 2459 static int cs48l32_in_put_volsw(struct snd_kcontrol *kcontrol, 2460 struct snd_ctl_elem_value *ucontrol) 2461 { 2462 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2463 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2464 int ret; 2465 2466 ret = snd_soc_put_volsw(kcontrol, ucontrol); 2467 if (ret < 0) 2468 return ret; 2469 2470 /* 2471 * Uncached write-only register, no need for update_bits. 2472 * Will fail if codec is off but that will be handled by cs48l32_in_ev 2473 */ 2474 snd_soc_component_write(component, cs48l32_codec->in_vu_reg, CS48L32_IN_VU); 2475 2476 return ret; 2477 } 2478 2479 static bool cs48l32_eq_filter_unstable(bool mode, __be16 in_a, __be16 in_b) 2480 { 2481 s16 a = be16_to_cpu(in_a); 2482 s16 b = be16_to_cpu(in_b); 2483 2484 if (!mode) 2485 return abs(a) > CS48L32_EQ_MAX_COEFF; 2486 2487 if (abs(b) > CS48L32_EQ_MAX_COEFF) 2488 return true; 2489 2490 if (abs((a << 16) / (CS48L32_EQ_MAX_COEFF + 1 - b)) >= ((CS48L32_EQ_MAX_COEFF + 1) << 4)) 2491 return true; 2492 2493 return false; 2494 } 2495 2496 static int cs48l32_eq_ev(struct snd_soc_dapm_widget *w, 2497 struct snd_kcontrol *kcontrol, int event) 2498 { 2499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2500 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2501 struct regmap *regmap = cs48l32_codec->core.regmap; 2502 unsigned int mode = cs48l32_codec->eq_mode[w->shift]; 2503 unsigned int reg; 2504 __be16 *data = &cs48l32_codec->eq_coefficients[w->shift][0]; 2505 int ret = 0; 2506 2507 reg = CS48L32_EQ1_BAND1_COEFF1; 2508 reg += w->shift * (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1); 2509 2510 switch (event) { 2511 case SND_SOC_DAPM_PRE_PMU: 2512 if (cs48l32_eq_filter_unstable(!!mode, data[1], data[0]) || 2513 cs48l32_eq_filter_unstable(true, data[7], data[6]) || 2514 cs48l32_eq_filter_unstable(true, data[13], data[12]) || 2515 cs48l32_eq_filter_unstable(true, data[19], data[18]) || 2516 cs48l32_eq_filter_unstable(false, data[25], data[24])) { 2517 dev_err(cs48l32_codec->core.dev, "Rejecting unstable EQ coefficients.\n"); 2518 ret = -EINVAL; 2519 } else { 2520 ret = regmap_raw_write(regmap, reg, data, CS48L32_EQ_BLOCK_SZ); 2521 if (ret < 0) { 2522 dev_err(cs48l32_codec->core.dev, 2523 "Error writing EQ coefficients: %d\n", ret); 2524 goto out; 2525 } 2526 2527 ret = snd_soc_component_update_bits(component, 2528 CS48L32_EQ_CONTROL2, 2529 w->mask, 2530 mode << w->shift); 2531 if (ret < 0) { 2532 dev_err(cs48l32_codec->core.dev, 2533 "Error writing EQ mode: %d\n", ret); 2534 } 2535 } 2536 break; 2537 default: 2538 break; 2539 } 2540 2541 out: 2542 return ret; 2543 } 2544 2545 static const struct snd_kcontrol_new cs48l32_snd_controls[] = { 2546 SOC_ENUM("IN1 OSR", cs48l32_in_dmic_osr[0]), 2547 SOC_ENUM("IN2 OSR", cs48l32_in_dmic_osr[1]), 2548 2549 SOC_SINGLE_RANGE_TLV("IN1L Volume", CS48L32_IN1L_CONTROL2, 2550 CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), 2551 SOC_SINGLE_RANGE_TLV("IN1R Volume", CS48L32_IN1R_CONTROL2, 2552 CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), 2553 2554 SOC_ENUM("IN HPF Cutoff Frequency", cs48l32_in_hpf_cut_enum), 2555 2556 SOC_SINGLE_EXT("IN1L LP Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, 2557 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), 2558 SOC_SINGLE_EXT("IN1R LP Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, 2559 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), 2560 2561 SOC_SINGLE("IN1L HPF Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), 2562 SOC_SINGLE("IN1R HPF Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), 2563 SOC_SINGLE("IN2L HPF Switch", CS48L32_IN2L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), 2564 SOC_SINGLE("IN2R HPF Switch", CS48L32_IN2R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), 2565 2566 SOC_SINGLE_EXT_TLV("IN1L Digital Volume", CS48L32_IN1L_CONTROL2, 2567 CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, 2568 cs48l32_in_put_volsw, cs48l32_digital_tlv), 2569 SOC_SINGLE_EXT_TLV("IN1R Digital Volume", CS48L32_IN1R_CONTROL2, 2570 CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, 2571 cs48l32_in_put_volsw, cs48l32_digital_tlv), 2572 SOC_SINGLE_EXT_TLV("IN2L Digital Volume", CS48L32_IN2L_CONTROL2, 2573 CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, 2574 cs48l32_in_put_volsw, cs48l32_digital_tlv), 2575 SOC_SINGLE_EXT_TLV("IN2R Digital Volume", CS48L32_IN2R_CONTROL2, 2576 CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, 2577 cs48l32_in_put_volsw, cs48l32_digital_tlv), 2578 2579 SOC_ENUM("Input Ramp Up", cs48l32_in_vi_ramp), 2580 SOC_ENUM("Input Ramp Down", cs48l32_in_vd_ramp), 2581 2582 CS48L32_RATE_ENUM("Ultrasonic 1 Rate", cs48l32_us_output_rate[0]), 2583 CS48L32_RATE_ENUM("Ultrasonic 2 Rate", cs48l32_us_output_rate[1]), 2584 2585 SOC_ENUM("Ultrasonic 1 Freq", cs48l32_us_freq[0]), 2586 SOC_ENUM("Ultrasonic 2 Freq", cs48l32_us_freq[1]), 2587 2588 SOC_SINGLE_TLV("Ultrasonic 1 Volume", CS48L32_US1_CONTROL, CS48L32_US1_GAIN_SHIFT, 2589 3, 0, cs48l32_us_tlv), 2590 SOC_SINGLE_TLV("Ultrasonic 2 Volume", CS48L32_US2_CONTROL, CS48L32_US1_GAIN_SHIFT, 2591 3, 0, cs48l32_us_tlv), 2592 2593 SOC_ENUM("Ultrasonic 1 Detect Threshold", cs48l32_us_det_thr[0]), 2594 SOC_ENUM("Ultrasonic 2 Detect Threshold", cs48l32_us_det_thr[1]), 2595 2596 SOC_ENUM("Ultrasonic 1 Detect Pulse Length", cs48l32_us_det_num[0]), 2597 SOC_ENUM("Ultrasonic 2 Detect Pulse Length", cs48l32_us_det_num[1]), 2598 2599 SOC_ENUM("Ultrasonic 1 Detect Hold", cs48l32_us_det_hold[0]), 2600 SOC_ENUM("Ultrasonic 2 Detect Hold", cs48l32_us_det_hold[1]), 2601 2602 SOC_ENUM("Ultrasonic 1 Detect Decay", cs48l32_us_det_dcy[0]), 2603 SOC_ENUM("Ultrasonic 2 Detect Decay", cs48l32_us_det_dcy[1]), 2604 2605 SOC_SINGLE("Ultrasonic 1 Detect LPF Switch", 2606 CS48L32_US1_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), 2607 SOC_SINGLE("Ultrasonic 2 Detect LPF Switch", 2608 CS48L32_US2_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), 2609 2610 SOC_ENUM("Ultrasonic 1 Detect LPF Cut-off", cs48l32_us_det_lpf_cut[0]), 2611 SOC_ENUM("Ultrasonic 2 Detect LPF Cut-off", cs48l32_us_det_lpf_cut[1]), 2612 2613 CS48L32_MIXER_CONTROLS("EQ1", CS48L32_EQ1_INPUT1), 2614 CS48L32_MIXER_CONTROLS("EQ2", CS48L32_EQ2_INPUT1), 2615 CS48L32_MIXER_CONTROLS("EQ3", CS48L32_EQ3_INPUT1), 2616 CS48L32_MIXER_CONTROLS("EQ4", CS48L32_EQ4_INPUT1), 2617 2618 SOC_ENUM_EXT("EQ1 Mode", cs48l32_eq_mode[0], cs48l32_eq_mode_get, cs48l32_eq_mode_put), 2619 2620 CS48L32_EQ_COEFF_CONTROLS(EQ1), 2621 2622 SOC_SINGLE_TLV("EQ1 B1 Volume", CS48L32_EQ1_GAIN1, 0, 24, 0, cs48l32_eq_tlv), 2623 SOC_SINGLE_TLV("EQ1 B2 Volume", CS48L32_EQ1_GAIN1, 8, 24, 0, cs48l32_eq_tlv), 2624 SOC_SINGLE_TLV("EQ1 B3 Volume", CS48L32_EQ1_GAIN1, 16, 24, 0, cs48l32_eq_tlv), 2625 SOC_SINGLE_TLV("EQ1 B4 Volume", CS48L32_EQ1_GAIN1, 24, 24, 0, cs48l32_eq_tlv), 2626 SOC_SINGLE_TLV("EQ1 B5 Volume", CS48L32_EQ1_GAIN2, 0, 24, 0, cs48l32_eq_tlv), 2627 2628 SOC_ENUM_EXT("EQ2 Mode", cs48l32_eq_mode[1], cs48l32_eq_mode_get, cs48l32_eq_mode_put), 2629 CS48L32_EQ_COEFF_CONTROLS(EQ2), 2630 SOC_SINGLE_TLV("EQ2 B1 Volume", CS48L32_EQ2_GAIN1, 0, 24, 0, cs48l32_eq_tlv), 2631 SOC_SINGLE_TLV("EQ2 B2 Volume", CS48L32_EQ2_GAIN1, 8, 24, 0, cs48l32_eq_tlv), 2632 SOC_SINGLE_TLV("EQ2 B3 Volume", CS48L32_EQ2_GAIN1, 16, 24, 0, cs48l32_eq_tlv), 2633 SOC_SINGLE_TLV("EQ2 B4 Volume", CS48L32_EQ2_GAIN1, 24, 24, 0, cs48l32_eq_tlv), 2634 SOC_SINGLE_TLV("EQ2 B5 Volume", CS48L32_EQ2_GAIN2, 0, 24, 0, cs48l32_eq_tlv), 2635 2636 SOC_ENUM_EXT("EQ3 Mode", cs48l32_eq_mode[2], cs48l32_eq_mode_get, cs48l32_eq_mode_put), 2637 CS48L32_EQ_COEFF_CONTROLS(EQ3), 2638 SOC_SINGLE_TLV("EQ3 B1 Volume", CS48L32_EQ3_GAIN1, 0, 24, 0, cs48l32_eq_tlv), 2639 SOC_SINGLE_TLV("EQ3 B2 Volume", CS48L32_EQ3_GAIN1, 8, 24, 0, cs48l32_eq_tlv), 2640 SOC_SINGLE_TLV("EQ3 B3 Volume", CS48L32_EQ3_GAIN1, 16, 24, 0, cs48l32_eq_tlv), 2641 SOC_SINGLE_TLV("EQ3 B4 Volume", CS48L32_EQ3_GAIN1, 24, 24, 0, cs48l32_eq_tlv), 2642 SOC_SINGLE_TLV("EQ3 B5 Volume", CS48L32_EQ3_GAIN2, 0, 24, 0, cs48l32_eq_tlv), 2643 2644 SOC_ENUM_EXT("EQ4 Mode", cs48l32_eq_mode[3], cs48l32_eq_mode_get, cs48l32_eq_mode_put), 2645 CS48L32_EQ_COEFF_CONTROLS(EQ4), 2646 SOC_SINGLE_TLV("EQ4 B1 Volume", CS48L32_EQ4_GAIN1, 0, 24, 0, cs48l32_eq_tlv), 2647 SOC_SINGLE_TLV("EQ4 B2 Volume", CS48L32_EQ4_GAIN1, 8, 24, 0, cs48l32_eq_tlv), 2648 SOC_SINGLE_TLV("EQ4 B3 Volume", CS48L32_EQ4_GAIN1, 16, 24, 0, cs48l32_eq_tlv), 2649 SOC_SINGLE_TLV("EQ4 B4 Volume", CS48L32_EQ4_GAIN1, 24, 24, 0, cs48l32_eq_tlv), 2650 SOC_SINGLE_TLV("EQ4 B5 Volume", CS48L32_EQ4_GAIN2, 0, 24, 0, cs48l32_eq_tlv), 2651 2652 CS48L32_MIXER_CONTROLS("DRC1L", CS48L32_DRC1L_INPUT1), 2653 CS48L32_MIXER_CONTROLS("DRC1R", CS48L32_DRC1R_INPUT1), 2654 CS48L32_MIXER_CONTROLS("DRC2L", CS48L32_DRC2L_INPUT1), 2655 CS48L32_MIXER_CONTROLS("DRC2R", CS48L32_DRC2R_INPUT1), 2656 2657 SND_SOC_BYTES_MASK("DRC1 Coefficients", CS48L32_DRC1_CONTROL1, 4, 2658 BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), 2659 SND_SOC_BYTES_MASK("DRC2 Coefficients", CS48L32_DRC2_CONTROL1, 4, 2660 BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), 2661 2662 CS48L32_MIXER_CONTROLS("LHPF1", CS48L32_LHPF1_INPUT1), 2663 CS48L32_MIXER_CONTROLS("LHPF2", CS48L32_LHPF2_INPUT1), 2664 CS48L32_MIXER_CONTROLS("LHPF3", CS48L32_LHPF3_INPUT1), 2665 CS48L32_MIXER_CONTROLS("LHPF4", CS48L32_LHPF4_INPUT1), 2666 2667 CS48L32_LHPF_CONTROL("LHPF1 Coefficients", CS48L32_LHPF1_COEFF), 2668 CS48L32_LHPF_CONTROL("LHPF2 Coefficients", CS48L32_LHPF2_COEFF), 2669 CS48L32_LHPF_CONTROL("LHPF3 Coefficients", CS48L32_LHPF3_COEFF), 2670 CS48L32_LHPF_CONTROL("LHPF4 Coefficients", CS48L32_LHPF4_COEFF), 2671 2672 SOC_ENUM("LHPF1 Mode", cs48l32_lhpf_mode[0]), 2673 SOC_ENUM("LHPF2 Mode", cs48l32_lhpf_mode[1]), 2674 SOC_ENUM("LHPF3 Mode", cs48l32_lhpf_mode[2]), 2675 SOC_ENUM("LHPF4 Mode", cs48l32_lhpf_mode[3]), 2676 2677 CS48L32_RATE_CONTROL("Sample Rate 1", 1), 2678 CS48L32_RATE_CONTROL("Sample Rate 2", 2), 2679 CS48L32_RATE_CONTROL("Sample Rate 3", 3), 2680 CS48L32_RATE_CONTROL("Sample Rate 4", 4), 2681 2682 CS48L32_RATE_ENUM("FX Rate", cs48l32_fx_rate), 2683 2684 CS48L32_RATE_ENUM("ISRC1 FSL", cs48l32_isrc_fsl[0]), 2685 CS48L32_RATE_ENUM("ISRC2 FSL", cs48l32_isrc_fsl[1]), 2686 CS48L32_RATE_ENUM("ISRC3 FSL", cs48l32_isrc_fsl[2]), 2687 CS48L32_RATE_ENUM("ISRC1 FSH", cs48l32_isrc_fsh[0]), 2688 CS48L32_RATE_ENUM("ISRC2 FSH", cs48l32_isrc_fsh[1]), 2689 CS48L32_RATE_ENUM("ISRC3 FSH", cs48l32_isrc_fsh[2]), 2690 2691 SOC_ENUM("AUXPDM1 Rate", cs48l32_auxpdm1_freq), 2692 SOC_ENUM("AUXPDM2 Rate", cs48l32_auxpdm2_freq), 2693 2694 SOC_ENUM_EXT("IN1L Rate", cs48l32_input_rate[0], snd_soc_get_enum_double, cs48l32_in_rate_put), 2695 SOC_ENUM_EXT("IN1R Rate", cs48l32_input_rate[1], snd_soc_get_enum_double, cs48l32_in_rate_put), 2696 SOC_ENUM_EXT("IN2L Rate", cs48l32_input_rate[2], snd_soc_get_enum_double, cs48l32_in_rate_put), 2697 SOC_ENUM_EXT("IN2R Rate", cs48l32_input_rate[3], snd_soc_get_enum_double, cs48l32_in_rate_put), 2698 2699 CS48L32_RATE_ENUM("Noise Generator Rate", noise_gen_rate), 2700 2701 SOC_SINGLE_TLV("Noise Generator Volume", CS48L32_COMFORT_NOISE_GENERATOR, 2702 CS48L32_NOISE_GEN_GAIN_SHIFT, 0x12, 0, cs48l32_noise_tlv), 2703 2704 CS48L32_MIXER_CONTROLS("ASP1TX1", CS48L32_ASP1TX1_INPUT1), 2705 CS48L32_MIXER_CONTROLS("ASP1TX2", CS48L32_ASP1TX2_INPUT1), 2706 CS48L32_MIXER_CONTROLS("ASP1TX3", CS48L32_ASP1TX3_INPUT1), 2707 CS48L32_MIXER_CONTROLS("ASP1TX4", CS48L32_ASP1TX4_INPUT1), 2708 CS48L32_MIXER_CONTROLS("ASP1TX5", CS48L32_ASP1TX5_INPUT1), 2709 CS48L32_MIXER_CONTROLS("ASP1TX6", CS48L32_ASP1TX6_INPUT1), 2710 CS48L32_MIXER_CONTROLS("ASP1TX7", CS48L32_ASP1TX7_INPUT1), 2711 CS48L32_MIXER_CONTROLS("ASP1TX8", CS48L32_ASP1TX8_INPUT1), 2712 2713 CS48L32_MIXER_CONTROLS("ASP2TX1", CS48L32_ASP2TX1_INPUT1), 2714 CS48L32_MIXER_CONTROLS("ASP2TX2", CS48L32_ASP2TX2_INPUT1), 2715 CS48L32_MIXER_CONTROLS("ASP2TX3", CS48L32_ASP2TX3_INPUT1), 2716 CS48L32_MIXER_CONTROLS("ASP2TX4", CS48L32_ASP2TX4_INPUT1), 2717 2718 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 2719 2720 CS48L32_MIXER_CONTROLS("DSP1RX1", CS48L32_DSP1RX1_INPUT1), 2721 CS48L32_MIXER_CONTROLS("DSP1RX2", CS48L32_DSP1RX2_INPUT1), 2722 CS48L32_MIXER_CONTROLS("DSP1RX3", CS48L32_DSP1RX3_INPUT1), 2723 CS48L32_MIXER_CONTROLS("DSP1RX4", CS48L32_DSP1RX4_INPUT1), 2724 CS48L32_MIXER_CONTROLS("DSP1RX5", CS48L32_DSP1RX5_INPUT1), 2725 CS48L32_MIXER_CONTROLS("DSP1RX6", CS48L32_DSP1RX6_INPUT1), 2726 CS48L32_MIXER_CONTROLS("DSP1RX7", CS48L32_DSP1RX7_INPUT1), 2727 CS48L32_MIXER_CONTROLS("DSP1RX8", CS48L32_DSP1RX8_INPUT1), 2728 2729 WM_ADSP_FW_CONTROL("DSP1", 0), 2730 2731 CS48L32_DSP_RATE_CONTROL("DSP1RX1", 0), 2732 CS48L32_DSP_RATE_CONTROL("DSP1RX2", 1), 2733 CS48L32_DSP_RATE_CONTROL("DSP1RX3", 2), 2734 CS48L32_DSP_RATE_CONTROL("DSP1RX4", 3), 2735 CS48L32_DSP_RATE_CONTROL("DSP1RX5", 4), 2736 CS48L32_DSP_RATE_CONTROL("DSP1RX6", 5), 2737 CS48L32_DSP_RATE_CONTROL("DSP1RX7", 6), 2738 CS48L32_DSP_RATE_CONTROL("DSP1RX8", 7), 2739 CS48L32_DSP_RATE_CONTROL("DSP1TX1", 8), 2740 CS48L32_DSP_RATE_CONTROL("DSP1TX2", 9), 2741 CS48L32_DSP_RATE_CONTROL("DSP1TX3", 10), 2742 CS48L32_DSP_RATE_CONTROL("DSP1TX4", 11), 2743 CS48L32_DSP_RATE_CONTROL("DSP1TX5", 12), 2744 CS48L32_DSP_RATE_CONTROL("DSP1TX6", 13), 2745 CS48L32_DSP_RATE_CONTROL("DSP1TX7", 14), 2746 CS48L32_DSP_RATE_CONTROL("DSP1TX8", 15), 2747 }; 2748 2749 CS48L32_MIXER_ENUMS(EQ1, CS48L32_EQ1_INPUT1); 2750 CS48L32_MIXER_ENUMS(EQ2, CS48L32_EQ2_INPUT1); 2751 CS48L32_MIXER_ENUMS(EQ3, CS48L32_EQ3_INPUT1); 2752 CS48L32_MIXER_ENUMS(EQ4, CS48L32_EQ4_INPUT1); 2753 2754 CS48L32_MIXER_ENUMS(DRC1L, CS48L32_DRC1L_INPUT1); 2755 CS48L32_MIXER_ENUMS(DRC1R, CS48L32_DRC1R_INPUT1); 2756 CS48L32_MIXER_ENUMS(DRC2L, CS48L32_DRC2L_INPUT1); 2757 CS48L32_MIXER_ENUMS(DRC2R, CS48L32_DRC2R_INPUT1); 2758 2759 CS48L32_MIXER_ENUMS(LHPF1, CS48L32_LHPF1_INPUT1); 2760 CS48L32_MIXER_ENUMS(LHPF2, CS48L32_LHPF2_INPUT1); 2761 CS48L32_MIXER_ENUMS(LHPF3, CS48L32_LHPF3_INPUT1); 2762 CS48L32_MIXER_ENUMS(LHPF4, CS48L32_LHPF4_INPUT1); 2763 2764 CS48L32_MIXER_ENUMS(ASP1TX1, CS48L32_ASP1TX1_INPUT1); 2765 CS48L32_MIXER_ENUMS(ASP1TX2, CS48L32_ASP1TX2_INPUT1); 2766 CS48L32_MIXER_ENUMS(ASP1TX3, CS48L32_ASP1TX3_INPUT1); 2767 CS48L32_MIXER_ENUMS(ASP1TX4, CS48L32_ASP1TX4_INPUT1); 2768 CS48L32_MIXER_ENUMS(ASP1TX5, CS48L32_ASP1TX5_INPUT1); 2769 CS48L32_MIXER_ENUMS(ASP1TX6, CS48L32_ASP1TX6_INPUT1); 2770 CS48L32_MIXER_ENUMS(ASP1TX7, CS48L32_ASP1TX7_INPUT1); 2771 CS48L32_MIXER_ENUMS(ASP1TX8, CS48L32_ASP1TX8_INPUT1); 2772 2773 CS48L32_MIXER_ENUMS(ASP2TX1, CS48L32_ASP2TX1_INPUT1); 2774 CS48L32_MIXER_ENUMS(ASP2TX2, CS48L32_ASP2TX2_INPUT1); 2775 CS48L32_MIXER_ENUMS(ASP2TX3, CS48L32_ASP2TX3_INPUT1); 2776 CS48L32_MIXER_ENUMS(ASP2TX4, CS48L32_ASP2TX4_INPUT1); 2777 2778 CS48L32_MUX_ENUMS(ISRC1INT1, CS48L32_ISRC1INT1_INPUT1); 2779 CS48L32_MUX_ENUMS(ISRC1INT2, CS48L32_ISRC1INT2_INPUT1); 2780 CS48L32_MUX_ENUMS(ISRC1INT3, CS48L32_ISRC1INT3_INPUT1); 2781 CS48L32_MUX_ENUMS(ISRC1INT4, CS48L32_ISRC1INT4_INPUT1); 2782 2783 CS48L32_MUX_ENUMS(ISRC1DEC1, CS48L32_ISRC1DEC1_INPUT1); 2784 CS48L32_MUX_ENUMS(ISRC1DEC2, CS48L32_ISRC1DEC2_INPUT1); 2785 CS48L32_MUX_ENUMS(ISRC1DEC3, CS48L32_ISRC1DEC3_INPUT1); 2786 CS48L32_MUX_ENUMS(ISRC1DEC4, CS48L32_ISRC1DEC4_INPUT1); 2787 2788 CS48L32_MUX_ENUMS(ISRC2INT1, CS48L32_ISRC2INT1_INPUT1); 2789 CS48L32_MUX_ENUMS(ISRC2INT2, CS48L32_ISRC2INT2_INPUT1); 2790 2791 CS48L32_MUX_ENUMS(ISRC2DEC1, CS48L32_ISRC2DEC1_INPUT1); 2792 CS48L32_MUX_ENUMS(ISRC2DEC2, CS48L32_ISRC2DEC2_INPUT1); 2793 2794 CS48L32_MUX_ENUMS(ISRC3INT1, CS48L32_ISRC3INT1_INPUT1); 2795 CS48L32_MUX_ENUMS(ISRC3INT2, CS48L32_ISRC3INT2_INPUT1); 2796 2797 CS48L32_MUX_ENUMS(ISRC3DEC1, CS48L32_ISRC3DEC1_INPUT1); 2798 CS48L32_MUX_ENUMS(ISRC3DEC2, CS48L32_ISRC3DEC2_INPUT1); 2799 2800 CS48L32_MIXER_ENUMS(DSP1RX1, CS48L32_DSP1RX1_INPUT1); 2801 CS48L32_MIXER_ENUMS(DSP1RX2, CS48L32_DSP1RX2_INPUT1); 2802 CS48L32_MIXER_ENUMS(DSP1RX3, CS48L32_DSP1RX3_INPUT1); 2803 CS48L32_MIXER_ENUMS(DSP1RX4, CS48L32_DSP1RX4_INPUT1); 2804 CS48L32_MIXER_ENUMS(DSP1RX5, CS48L32_DSP1RX5_INPUT1); 2805 CS48L32_MIXER_ENUMS(DSP1RX6, CS48L32_DSP1RX6_INPUT1); 2806 CS48L32_MIXER_ENUMS(DSP1RX7, CS48L32_DSP1RX7_INPUT1); 2807 CS48L32_MIXER_ENUMS(DSP1RX8, CS48L32_DSP1RX8_INPUT1); 2808 2809 static int cs48l32_dsp_mem_ev(struct snd_soc_dapm_widget *w, 2810 struct snd_kcontrol *kcontrol, int event) 2811 { 2812 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2813 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 2814 2815 switch (event) { 2816 case SND_SOC_DAPM_POST_PMU: 2817 return cs48l32_dsp_memory_enable(cs48l32_codec, &cs48l32_dsp_sram_regs); 2818 case SND_SOC_DAPM_PRE_PMD: 2819 cs48l32_dsp_memory_disable(cs48l32_codec, &cs48l32_dsp_sram_regs); 2820 return 0; 2821 default: 2822 return 0; 2823 } 2824 } 2825 2826 static const struct snd_soc_dapm_widget cs48l32_dapm_widgets[] = { 2827 SND_SOC_DAPM_SUPPLY("SYSCLK", CS48L32_SYSTEM_CLOCK1, CS48L32_SYSCLK_EN_SHIFT, 0, 2828 cs48l32_sysclk_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2829 2830 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-cp", 20, 0), 2831 2832 SND_SOC_DAPM_SUPPLY("VOUT_MIC", CS48L32_CHARGE_PUMP1, CS48L32_CP2_EN_SHIFT, 0, NULL, 0), 2833 SND_SOC_DAPM_SUPPLY("VOUT_MIC_REGULATED", CS48L32_CHARGE_PUMP1, CS48L32_CP2_BYPASS_SHIFT, 2834 1, NULL, 0), 2835 SND_SOC_DAPM_SUPPLY("MICBIAS1", CS48L32_MICBIAS_CTRL1, CS48L32_MICB1_EN_SHIFT, 0, NULL, 0), 2836 SND_SOC_DAPM_SUPPLY("MICBIAS1A", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1A_EN_SHIFT, 0, NULL, 0), 2837 SND_SOC_DAPM_SUPPLY("MICBIAS1B", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1B_EN_SHIFT, 0, NULL, 0), 2838 SND_SOC_DAPM_SUPPLY("MICBIAS1C", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1C_EN_SHIFT, 0, NULL, 0), 2839 2840 SND_SOC_DAPM_SUPPLY("DSP1MEM", SND_SOC_NOPM, 0, 0, cs48l32_dsp_mem_ev, 2841 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2842 2843 CS48L32_DSP_FREQ_WIDGET_EV("DSP1", 0, cs48l32_dsp_freq_ev), 2844 2845 SND_SOC_DAPM_SIGGEN("TONE"), 2846 SND_SOC_DAPM_SIGGEN("NOISE"), 2847 2848 SND_SOC_DAPM_INPUT("IN1LN_1"), 2849 SND_SOC_DAPM_INPUT("IN1LN_2"), 2850 SND_SOC_DAPM_INPUT("IN1LP_1"), 2851 SND_SOC_DAPM_INPUT("IN1LP_2"), 2852 SND_SOC_DAPM_INPUT("IN1RN_1"), 2853 SND_SOC_DAPM_INPUT("IN1RN_2"), 2854 SND_SOC_DAPM_INPUT("IN1RP_1"), 2855 SND_SOC_DAPM_INPUT("IN1RP_2"), 2856 SND_SOC_DAPM_INPUT("IN1_PDMCLK"), 2857 SND_SOC_DAPM_INPUT("IN1_PDMDATA"), 2858 2859 SND_SOC_DAPM_INPUT("IN2_PDMCLK"), 2860 SND_SOC_DAPM_INPUT("IN2_PDMDATA"), 2861 2862 SND_SOC_DAPM_MUX("Ultrasonic 1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[0]), 2863 SND_SOC_DAPM_MUX("Ultrasonic 2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[1]), 2864 2865 SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), 2866 SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), 2867 2868 SND_SOC_DAPM_OUTPUT("DSP Trigger Out"), 2869 2870 SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[0]), 2871 SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[1]), 2872 2873 SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), 2874 SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), 2875 2876 SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS48L32_ASP1_ENABLES1, 0, 0), 2877 SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS48L32_ASP1_ENABLES1, 1, 0), 2878 SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS48L32_ASP1_ENABLES1, 2, 0), 2879 SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS48L32_ASP1_ENABLES1, 3, 0), 2880 SND_SOC_DAPM_AIF_OUT("ASP1TX5", NULL, 4, CS48L32_ASP1_ENABLES1, 4, 0), 2881 SND_SOC_DAPM_AIF_OUT("ASP1TX6", NULL, 5, CS48L32_ASP1_ENABLES1, 5, 0), 2882 SND_SOC_DAPM_AIF_OUT("ASP1TX7", NULL, 6, CS48L32_ASP1_ENABLES1, 6, 0), 2883 SND_SOC_DAPM_AIF_OUT("ASP1TX8", NULL, 7, CS48L32_ASP1_ENABLES1, 7, 0), 2884 2885 SND_SOC_DAPM_AIF_OUT("ASP2TX1", NULL, 0, CS48L32_ASP2_ENABLES1, 0, 0), 2886 SND_SOC_DAPM_AIF_OUT("ASP2TX2", NULL, 1, CS48L32_ASP2_ENABLES1, 1, 0), 2887 SND_SOC_DAPM_AIF_OUT("ASP2TX3", NULL, 2, CS48L32_ASP2_ENABLES1, 2, 0), 2888 SND_SOC_DAPM_AIF_OUT("ASP2TX4", NULL, 3, CS48L32_ASP2_ENABLES1, 3, 0), 2889 2890 SND_SOC_DAPM_SWITCH("AUXPDM1 Output", CS48L32_AUXPDM_CONTROL1, 0, 0, &cs48l32_auxpdm_switch[0]), 2891 SND_SOC_DAPM_SWITCH("AUXPDM2 Output", CS48L32_AUXPDM_CONTROL1, 1, 0, &cs48l32_auxpdm_switch[1]), 2892 2893 SND_SOC_DAPM_MUX("AUXPDM1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[0]), 2894 SND_SOC_DAPM_MUX("AUXPDM2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[1]), 2895 2896 SND_SOC_DAPM_MUX("AUXPDM1 Analog Input", SND_SOC_NOPM, 0, 0, 2897 &cs48l32_auxpdm_analog_inmux[0]), 2898 SND_SOC_DAPM_MUX("AUXPDM2 Analog Input", SND_SOC_NOPM, 0, 0, 2899 &cs48l32_auxpdm_analog_inmux[1]), 2900 2901 SND_SOC_DAPM_SWITCH("Ultrasonic 1 Detect", CS48L32_US_CONTROL, 2902 CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[0]), 2903 SND_SOC_DAPM_SWITCH("Ultrasonic 2 Detect", CS48L32_US_CONTROL, 2904 CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[1]), 2905 2906 /* 2907 * mux_in widgets : arranged in the order of sources 2908 * specified in CS48L32_MIXER_INPUT_ROUTES 2909 */ 2910 SND_SOC_DAPM_PGA("Tone Generator 1", CS48L32_TONE_GENERATOR1, 0, 0, NULL, 0), 2911 SND_SOC_DAPM_PGA("Tone Generator 2", CS48L32_TONE_GENERATOR1, 1, 0, NULL, 0), 2912 2913 SND_SOC_DAPM_PGA("Noise Generator", CS48L32_COMFORT_NOISE_GENERATOR, 2914 CS48L32_NOISE_GEN_EN_SHIFT, 0, NULL, 0), 2915 2916 SND_SOC_DAPM_PGA_E("IN1L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1L_EN_SHIFT, 2917 0, NULL, 0, cs48l32_in_ev, 2918 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2919 SND_SOC_DAPM_PGA_E("IN1R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1R_EN_SHIFT, 2920 0, NULL, 0, cs48l32_in_ev, 2921 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2922 SND_SOC_DAPM_PGA_E("IN2L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2L_EN_SHIFT, 2923 0, NULL, 0, cs48l32_in_ev, 2924 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2925 SND_SOC_DAPM_PGA_E("IN2R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2R_EN_SHIFT, 2926 0, NULL, 0, cs48l32_in_ev, 2927 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2928 2929 SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS48L32_ASP1_ENABLES1, 16, 0), 2930 SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS48L32_ASP1_ENABLES1, 17, 0), 2931 SND_SOC_DAPM_AIF_IN("ASP1RX3", NULL, 2, CS48L32_ASP1_ENABLES1, 18, 0), 2932 SND_SOC_DAPM_AIF_IN("ASP1RX4", NULL, 3, CS48L32_ASP1_ENABLES1, 19, 0), 2933 SND_SOC_DAPM_AIF_IN("ASP1RX5", NULL, 4, CS48L32_ASP1_ENABLES1, 20, 0), 2934 SND_SOC_DAPM_AIF_IN("ASP1RX6", NULL, 5, CS48L32_ASP1_ENABLES1, 21, 0), 2935 SND_SOC_DAPM_AIF_IN("ASP1RX7", NULL, 6, CS48L32_ASP1_ENABLES1, 22, 0), 2936 SND_SOC_DAPM_AIF_IN("ASP1RX8", NULL, 7, CS48L32_ASP1_ENABLES1, 23, 0), 2937 2938 SND_SOC_DAPM_AIF_IN("ASP2RX1", NULL, 0, CS48L32_ASP2_ENABLES1, 16, 0), 2939 SND_SOC_DAPM_AIF_IN("ASP2RX2", NULL, 1, CS48L32_ASP2_ENABLES1, 17, 0), 2940 SND_SOC_DAPM_AIF_IN("ASP2RX3", NULL, 2, CS48L32_ASP2_ENABLES1, 18, 0), 2941 SND_SOC_DAPM_AIF_IN("ASP2RX4", NULL, 3, CS48L32_ASP2_ENABLES1, 19, 0), 2942 2943 SND_SOC_DAPM_PGA("ISRC1DEC1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), 2944 SND_SOC_DAPM_PGA("ISRC1DEC2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), 2945 SND_SOC_DAPM_PGA("ISRC1DEC3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC3_EN_SHIFT, 0, NULL, 0), 2946 SND_SOC_DAPM_PGA("ISRC1DEC4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC4_EN_SHIFT, 0, NULL, 0), 2947 2948 SND_SOC_DAPM_PGA("ISRC1INT1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), 2949 SND_SOC_DAPM_PGA("ISRC1INT2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), 2950 SND_SOC_DAPM_PGA("ISRC1INT3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT3_EN_SHIFT, 0, NULL, 0), 2951 SND_SOC_DAPM_PGA("ISRC1INT4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT4_EN_SHIFT, 0, NULL, 0), 2952 2953 SND_SOC_DAPM_PGA("ISRC2DEC1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), 2954 SND_SOC_DAPM_PGA("ISRC2DEC2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), 2955 2956 SND_SOC_DAPM_PGA("ISRC2INT1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), 2957 SND_SOC_DAPM_PGA("ISRC2INT2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), 2958 2959 SND_SOC_DAPM_PGA("ISRC3DEC1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), 2960 SND_SOC_DAPM_PGA("ISRC3DEC2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), 2961 2962 SND_SOC_DAPM_PGA("ISRC3INT1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), 2963 SND_SOC_DAPM_PGA("ISRC3INT2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), 2964 2965 SND_SOC_DAPM_PGA_E("EQ1", CS48L32_EQ_CONTROL1, 0, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), 2966 SND_SOC_DAPM_PGA_E("EQ2", CS48L32_EQ_CONTROL1, 1, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), 2967 SND_SOC_DAPM_PGA_E("EQ3", CS48L32_EQ_CONTROL1, 2, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), 2968 SND_SOC_DAPM_PGA_E("EQ4", CS48L32_EQ_CONTROL1, 3, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), 2969 2970 SND_SOC_DAPM_PGA("DRC1L", CS48L32_DRC1_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), 2971 SND_SOC_DAPM_PGA("DRC1R", CS48L32_DRC1_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), 2972 SND_SOC_DAPM_PGA("DRC2L", CS48L32_DRC2_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), 2973 SND_SOC_DAPM_PGA("DRC2R", CS48L32_DRC2_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), 2974 2975 SND_SOC_DAPM_PGA("LHPF1", CS48L32_LHPF_CONTROL1, 0, 0, NULL, 0), 2976 SND_SOC_DAPM_PGA("LHPF2", CS48L32_LHPF_CONTROL1, 1, 0, NULL, 0), 2977 SND_SOC_DAPM_PGA("LHPF3", CS48L32_LHPF_CONTROL1, 2, 0, NULL, 0), 2978 SND_SOC_DAPM_PGA("LHPF4", CS48L32_LHPF_CONTROL1, 3, 0, NULL, 0), 2979 2980 SND_SOC_DAPM_PGA("Ultrasonic 1", CS48L32_US_CONTROL, 0, 0, NULL, 0), 2981 SND_SOC_DAPM_PGA("Ultrasonic 2", CS48L32_US_CONTROL, 1, 0, NULL, 0), 2982 2983 WM_ADSP2("DSP1", 0, wm_adsp_early_event), 2984 2985 /* end of ordered widget list */ 2986 2987 CS48L32_MIXER_WIDGETS(EQ1, "EQ1"), 2988 CS48L32_MIXER_WIDGETS(EQ2, "EQ2"), 2989 CS48L32_MIXER_WIDGETS(EQ3, "EQ3"), 2990 CS48L32_MIXER_WIDGETS(EQ4, "EQ4"), 2991 2992 CS48L32_MIXER_WIDGETS(DRC1L, "DRC1L"), 2993 CS48L32_MIXER_WIDGETS(DRC1R, "DRC1R"), 2994 CS48L32_MIXER_WIDGETS(DRC2L, "DRC2L"), 2995 CS48L32_MIXER_WIDGETS(DRC2R, "DRC2R"), 2996 2997 SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0, 2998 &cs48l32_drc_activity_output_mux[0]), 2999 SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0, 3000 &cs48l32_drc_activity_output_mux[1]), 3001 3002 CS48L32_MIXER_WIDGETS(LHPF1, "LHPF1"), 3003 CS48L32_MIXER_WIDGETS(LHPF2, "LHPF2"), 3004 CS48L32_MIXER_WIDGETS(LHPF3, "LHPF3"), 3005 CS48L32_MIXER_WIDGETS(LHPF4, "LHPF4"), 3006 3007 CS48L32_MIXER_WIDGETS(ASP1TX1, "ASP1TX1"), 3008 CS48L32_MIXER_WIDGETS(ASP1TX2, "ASP1TX2"), 3009 CS48L32_MIXER_WIDGETS(ASP1TX3, "ASP1TX3"), 3010 CS48L32_MIXER_WIDGETS(ASP1TX4, "ASP1TX4"), 3011 CS48L32_MIXER_WIDGETS(ASP1TX5, "ASP1TX5"), 3012 CS48L32_MIXER_WIDGETS(ASP1TX6, "ASP1TX6"), 3013 CS48L32_MIXER_WIDGETS(ASP1TX7, "ASP1TX7"), 3014 CS48L32_MIXER_WIDGETS(ASP1TX8, "ASP1TX8"), 3015 3016 CS48L32_MIXER_WIDGETS(ASP2TX1, "ASP2TX1"), 3017 CS48L32_MIXER_WIDGETS(ASP2TX2, "ASP2TX2"), 3018 CS48L32_MIXER_WIDGETS(ASP2TX3, "ASP2TX3"), 3019 CS48L32_MIXER_WIDGETS(ASP2TX4, "ASP2TX4"), 3020 3021 CS48L32_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), 3022 CS48L32_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), 3023 CS48L32_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), 3024 CS48L32_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), 3025 3026 CS48L32_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), 3027 CS48L32_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), 3028 CS48L32_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), 3029 CS48L32_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), 3030 3031 CS48L32_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), 3032 CS48L32_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), 3033 3034 CS48L32_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), 3035 CS48L32_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), 3036 3037 CS48L32_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), 3038 CS48L32_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), 3039 3040 CS48L32_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), 3041 CS48L32_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), 3042 3043 CS48L32_MIXER_WIDGETS(DSP1RX1, "DSP1RX1"), 3044 CS48L32_MIXER_WIDGETS(DSP1RX2, "DSP1RX2"), 3045 CS48L32_MIXER_WIDGETS(DSP1RX3, "DSP1RX3"), 3046 CS48L32_MIXER_WIDGETS(DSP1RX4, "DSP1RX4"), 3047 CS48L32_MIXER_WIDGETS(DSP1RX5, "DSP1RX5"), 3048 CS48L32_MIXER_WIDGETS(DSP1RX6, "DSP1RX6"), 3049 CS48L32_MIXER_WIDGETS(DSP1RX7, "DSP1RX7"), 3050 CS48L32_MIXER_WIDGETS(DSP1RX8, "DSP1RX8"), 3051 3052 SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0, 3053 &cs48l32_dsp_trigger_output_mux[0]), 3054 3055 SND_SOC_DAPM_OUTPUT("AUXPDM1_CLK"), 3056 SND_SOC_DAPM_OUTPUT("AUXPDM1_DOUT"), 3057 SND_SOC_DAPM_OUTPUT("AUXPDM2_CLK"), 3058 SND_SOC_DAPM_OUTPUT("AUXPDM2_DOUT"), 3059 3060 SND_SOC_DAPM_OUTPUT("MICSUPP"), 3061 3062 SND_SOC_DAPM_OUTPUT("Ultrasonic Dummy Output"), 3063 }; 3064 3065 static const struct snd_soc_dapm_route cs48l32_dapm_routes[] = { 3066 { "IN1LN_1", NULL, "SYSCLK" }, 3067 { "IN1LN_2", NULL, "SYSCLK" }, 3068 { "IN1LP_1", NULL, "SYSCLK" }, 3069 { "IN1LP_2", NULL, "SYSCLK" }, 3070 { "IN1RN_1", NULL, "SYSCLK" }, 3071 { "IN1RN_2", NULL, "SYSCLK" }, 3072 { "IN1RP_1", NULL, "SYSCLK" }, 3073 { "IN1RP_2", NULL, "SYSCLK" }, 3074 3075 { "IN1_PDMCLK", NULL, "SYSCLK" }, 3076 { "IN1_PDMDATA", NULL, "SYSCLK" }, 3077 { "IN2_PDMCLK", NULL, "SYSCLK" }, 3078 { "IN2_PDMDATA", NULL, "SYSCLK" }, 3079 3080 { "DSP1 Preloader", NULL, "DSP1MEM" }, 3081 { "DSP1", NULL, "DSP1FREQ" }, 3082 3083 { "Audio Trace DSP", NULL, "DSP1" }, 3084 { "Voice Ctrl DSP", NULL, "DSP1" }, 3085 3086 { "VOUT_MIC_REGULATED", NULL, "VOUT_MIC" }, 3087 { "MICBIAS1", NULL, "VOUT_MIC_REGULATED" }, 3088 { "MICBIAS1A", NULL, "MICBIAS1" }, 3089 { "MICBIAS1B", NULL, "MICBIAS1" }, 3090 { "MICBIAS1C", NULL, "MICBIAS1" }, 3091 3092 { "Tone Generator 1", NULL, "SYSCLK" }, 3093 { "Tone Generator 2", NULL, "SYSCLK" }, 3094 { "Noise Generator", NULL, "SYSCLK" }, 3095 3096 { "Tone Generator 1", NULL, "TONE" }, 3097 { "Tone Generator 2", NULL, "TONE" }, 3098 { "Noise Generator", NULL, "NOISE" }, 3099 3100 { "ASP1 Capture", NULL, "ASP1TX1" }, 3101 { "ASP1 Capture", NULL, "ASP1TX2" }, 3102 { "ASP1 Capture", NULL, "ASP1TX3" }, 3103 { "ASP1 Capture", NULL, "ASP1TX4" }, 3104 { "ASP1 Capture", NULL, "ASP1TX5" }, 3105 { "ASP1 Capture", NULL, "ASP1TX6" }, 3106 { "ASP1 Capture", NULL, "ASP1TX7" }, 3107 { "ASP1 Capture", NULL, "ASP1TX8" }, 3108 3109 { "ASP1RX1", NULL, "ASP1 Playback" }, 3110 { "ASP1RX2", NULL, "ASP1 Playback" }, 3111 { "ASP1RX3", NULL, "ASP1 Playback" }, 3112 { "ASP1RX4", NULL, "ASP1 Playback" }, 3113 { "ASP1RX5", NULL, "ASP1 Playback" }, 3114 { "ASP1RX6", NULL, "ASP1 Playback" }, 3115 { "ASP1RX7", NULL, "ASP1 Playback" }, 3116 { "ASP1RX8", NULL, "ASP1 Playback" }, 3117 3118 { "ASP2 Capture", NULL, "ASP2TX1" }, 3119 { "ASP2 Capture", NULL, "ASP2TX2" }, 3120 { "ASP2 Capture", NULL, "ASP2TX3" }, 3121 { "ASP2 Capture", NULL, "ASP2TX4" }, 3122 3123 { "ASP2RX1", NULL, "ASP2 Playback" }, 3124 { "ASP2RX2", NULL, "ASP2 Playback" }, 3125 { "ASP2RX3", NULL, "ASP2 Playback" }, 3126 { "ASP2RX4", NULL, "ASP2 Playback" }, 3127 3128 { "ASP1 Playback", NULL, "SYSCLK" }, 3129 { "ASP2 Playback", NULL, "SYSCLK" }, 3130 3131 { "ASP1 Capture", NULL, "SYSCLK" }, 3132 { "ASP2 Capture", NULL, "SYSCLK" }, 3133 3134 { "IN1L Mux", "Analog 1", "IN1LN_1" }, 3135 { "IN1L Mux", "Analog 2", "IN1LN_2" }, 3136 { "IN1L Mux", "Analog 1", "IN1LP_1" }, 3137 { "IN1L Mux", "Analog 2", "IN1LP_2" }, 3138 { "IN1R Mux", "Analog 1", "IN1RN_1" }, 3139 { "IN1R Mux", "Analog 2", "IN1RN_2" }, 3140 { "IN1R Mux", "Analog 1", "IN1RP_1" }, 3141 { "IN1R Mux", "Analog 2", "IN1RP_2" }, 3142 3143 { "IN1L PGA", NULL, "IN1L Mode" }, 3144 { "IN1R PGA", NULL, "IN1R Mode" }, 3145 3146 { "IN1L Mode", "Analog", "IN1L Mux" }, 3147 { "IN1R Mode", "Analog", "IN1R Mux" }, 3148 3149 { "IN1L Mode", "Digital", "IN1_PDMCLK" }, 3150 { "IN1L Mode", "Digital", "IN1_PDMDATA" }, 3151 { "IN1R Mode", "Digital", "IN1_PDMCLK" }, 3152 { "IN1R Mode", "Digital", "IN1_PDMDATA" }, 3153 3154 { "IN1L PGA", NULL, "VOUT_MIC" }, 3155 { "IN1R PGA", NULL, "VOUT_MIC" }, 3156 3157 { "IN2L PGA", NULL, "VOUT_MIC" }, 3158 { "IN2R PGA", NULL, "VOUT_MIC" }, 3159 3160 { "IN2L PGA", NULL, "IN2_PDMCLK" }, 3161 { "IN2R PGA", NULL, "IN2_PDMCLK" }, 3162 { "IN2L PGA", NULL, "IN2_PDMDATA" }, 3163 { "IN2R PGA", NULL, "IN2_PDMDATA" }, 3164 3165 { "Ultrasonic 1", NULL, "Ultrasonic 1 Input" }, 3166 { "Ultrasonic 2", NULL, "Ultrasonic 2 Input" }, 3167 3168 { "Ultrasonic 1 Input", "IN1L", "IN1L PGA" }, 3169 { "Ultrasonic 1 Input", "IN1R", "IN1R PGA" }, 3170 { "Ultrasonic 1 Input", "IN2L", "IN2L PGA" }, 3171 { "Ultrasonic 1 Input", "IN2R", "IN2R PGA" }, 3172 3173 { "Ultrasonic 2 Input", "IN1L", "IN1L PGA" }, 3174 { "Ultrasonic 2 Input", "IN1R", "IN1R PGA" }, 3175 { "Ultrasonic 2 Input", "IN2L", "IN2L PGA" }, 3176 { "Ultrasonic 2 Input", "IN2R", "IN2R PGA" }, 3177 3178 { "Ultrasonic 1 Detect", "Switch", "Ultrasonic 1 Input" }, 3179 { "Ultrasonic 2 Detect", "Switch", "Ultrasonic 2 Input" }, 3180 3181 { "Ultrasonic Dummy Output", NULL, "Ultrasonic 1 Detect" }, 3182 { "Ultrasonic Dummy Output", NULL, "Ultrasonic 2 Detect" }, 3183 3184 CS48L32_MIXER_ROUTES("ASP1TX1", "ASP1TX1"), 3185 CS48L32_MIXER_ROUTES("ASP1TX2", "ASP1TX2"), 3186 CS48L32_MIXER_ROUTES("ASP1TX3", "ASP1TX3"), 3187 CS48L32_MIXER_ROUTES("ASP1TX4", "ASP1TX4"), 3188 CS48L32_MIXER_ROUTES("ASP1TX5", "ASP1TX5"), 3189 CS48L32_MIXER_ROUTES("ASP1TX6", "ASP1TX6"), 3190 CS48L32_MIXER_ROUTES("ASP1TX7", "ASP1TX7"), 3191 CS48L32_MIXER_ROUTES("ASP1TX8", "ASP1TX8"), 3192 3193 CS48L32_MIXER_ROUTES("ASP2TX1", "ASP2TX1"), 3194 CS48L32_MIXER_ROUTES("ASP2TX2", "ASP2TX2"), 3195 CS48L32_MIXER_ROUTES("ASP2TX3", "ASP2TX3"), 3196 CS48L32_MIXER_ROUTES("ASP2TX4", "ASP2TX4"), 3197 3198 CS48L32_MIXER_ROUTES("EQ1", "EQ1"), 3199 CS48L32_MIXER_ROUTES("EQ2", "EQ2"), 3200 CS48L32_MIXER_ROUTES("EQ3", "EQ3"), 3201 CS48L32_MIXER_ROUTES("EQ4", "EQ4"), 3202 3203 CS48L32_MIXER_ROUTES("DRC1L", "DRC1L"), 3204 CS48L32_MIXER_ROUTES("DRC1R", "DRC1R"), 3205 CS48L32_MIXER_ROUTES("DRC2L", "DRC2L"), 3206 CS48L32_MIXER_ROUTES("DRC2R", "DRC2R"), 3207 3208 CS48L32_MIXER_ROUTES("LHPF1", "LHPF1"), 3209 CS48L32_MIXER_ROUTES("LHPF2", "LHPF2"), 3210 CS48L32_MIXER_ROUTES("LHPF3", "LHPF3"), 3211 CS48L32_MIXER_ROUTES("LHPF4", "LHPF4"), 3212 3213 CS48L32_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 3214 CS48L32_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 3215 CS48L32_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), 3216 CS48L32_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), 3217 3218 CS48L32_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 3219 CS48L32_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 3220 CS48L32_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), 3221 CS48L32_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), 3222 3223 CS48L32_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 3224 CS48L32_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 3225 3226 CS48L32_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 3227 CS48L32_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 3228 3229 CS48L32_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), 3230 CS48L32_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), 3231 3232 CS48L32_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), 3233 CS48L32_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), 3234 3235 CS48L32_DSP_ROUTES_1_8_SYSCLK("DSP1"), 3236 3237 { "DSP Trigger Out", NULL, "DSP1 Trigger Output" }, 3238 3239 { "DSP1 Trigger Output", "Switch", "DSP1" }, 3240 3241 { "AUXPDM1 Analog Input", "IN1L", "IN1L PGA" }, 3242 { "AUXPDM1 Analog Input", "IN1R", "IN1R PGA" }, 3243 3244 { "AUXPDM2 Analog Input", "IN1L", "IN1L PGA" }, 3245 { "AUXPDM2 Analog Input", "IN1R", "IN1R PGA" }, 3246 3247 { "AUXPDM1 Input", "Analog", "AUXPDM1 Analog Input" }, 3248 { "AUXPDM1 Input", "IN1 Digital", "IN1L PGA" }, 3249 { "AUXPDM1 Input", "IN1 Digital", "IN1R PGA" }, 3250 { "AUXPDM1 Input", "IN2 Digital", "IN2L PGA" }, 3251 { "AUXPDM1 Input", "IN2 Digital", "IN2R PGA" }, 3252 3253 { "AUXPDM2 Input", "Analog", "AUXPDM2 Analog Input" }, 3254 { "AUXPDM2 Input", "IN1 Digital", "IN1L PGA" }, 3255 { "AUXPDM2 Input", "IN1 Digital", "IN1R PGA" }, 3256 { "AUXPDM2 Input", "IN2 Digital", "IN2L PGA" }, 3257 { "AUXPDM2 Input", "IN2 Digital", "IN2R PGA" }, 3258 3259 { "AUXPDM1 Output", "Switch", "AUXPDM1 Input" }, 3260 { "AUXPDM1_CLK", NULL, "AUXPDM1 Output" }, 3261 { "AUXPDM1_DOUT", NULL, "AUXPDM1 Output" }, 3262 3263 { "AUXPDM2 Output", "Switch", "AUXPDM2 Input" }, 3264 { "AUXPDM2_CLK", NULL, "AUXPDM2 Output" }, 3265 { "AUXPDM2_DOUT", NULL, "AUXPDM2 Output" }, 3266 3267 { "MICSUPP", NULL, "SYSCLK" }, 3268 3269 { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" }, 3270 { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" }, 3271 { "DRC1 Activity Output", "Switch", "DRC1L" }, 3272 { "DRC1 Activity Output", "Switch", "DRC1R" }, 3273 { "DRC2 Activity Output", "Switch", "DRC2L" }, 3274 { "DRC2 Activity Output", "Switch", "DRC2R" }, 3275 }; 3276 3277 static int cs48l32_compr_open(struct snd_soc_component *component, 3278 struct snd_compr_stream *stream) 3279 { 3280 struct snd_soc_pcm_runtime *rtd = stream->private_data; 3281 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 3282 3283 if (strcmp(snd_soc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-trace") && 3284 strcmp(snd_soc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-voicectrl")) { 3285 dev_err(cs48l32_codec->core.dev, "No suitable compressed stream for DAI '%s'\n", 3286 snd_soc_rtd_to_codec(rtd, 0)->name); 3287 return -EINVAL; 3288 } 3289 3290 return wm_adsp_compr_open(&cs48l32_codec->dsp, stream); 3291 } 3292 3293 static const struct snd_compress_ops cs48l32_compress_ops = { 3294 .open = &cs48l32_compr_open, 3295 .free = &wm_adsp_compr_free, 3296 .set_params = &wm_adsp_compr_set_params, 3297 .get_caps = &wm_adsp_compr_get_caps, 3298 .trigger = &wm_adsp_compr_trigger, 3299 .pointer = &wm_adsp_compr_pointer, 3300 .copy = &wm_adsp_compr_copy, 3301 }; 3302 3303 static const struct snd_soc_dai_ops cs48l32_compress_dai_ops = { 3304 .compress_new = snd_soc_new_compress, 3305 }; 3306 3307 static struct snd_soc_dai_driver cs48l32_dai[] = { 3308 { 3309 .name = "cs48l32-asp1", 3310 .id = 1, 3311 .base = CS48L32_ASP1_ENABLES1, 3312 .playback = { 3313 .stream_name = "ASP1 Playback", 3314 .channels_min = 1, 3315 .channels_max = 8, 3316 .rates = CS48L32_RATES, 3317 .formats = CS48L32_FORMATS, 3318 }, 3319 .capture = { 3320 .stream_name = "ASP1 Capture", 3321 .channels_min = 1, 3322 .channels_max = 8, 3323 .rates = CS48L32_RATES, 3324 .formats = CS48L32_FORMATS, 3325 }, 3326 .ops = &cs48l32_dai_ops, 3327 .symmetric_rate = 1, 3328 .symmetric_sample_bits = 1, 3329 }, 3330 { 3331 .name = "cs48l32-asp2", 3332 .id = 2, 3333 .base = CS48L32_ASP2_ENABLES1, 3334 .playback = { 3335 .stream_name = "ASP2 Playback", 3336 .channels_min = 1, 3337 .channels_max = 4, 3338 .rates = CS48L32_RATES, 3339 .formats = CS48L32_FORMATS, 3340 }, 3341 .capture = { 3342 .stream_name = "ASP2 Capture", 3343 .channels_min = 1, 3344 .channels_max = 4, 3345 .rates = CS48L32_RATES, 3346 .formats = CS48L32_FORMATS, 3347 }, 3348 .ops = &cs48l32_dai_ops, 3349 .symmetric_rate = 1, 3350 .symmetric_sample_bits = 1, 3351 }, 3352 { 3353 .name = "cs48l32-cpu-trace", 3354 .id = 3, 3355 .capture = { 3356 .stream_name = "Audio Trace CPU", 3357 .channels_min = 1, 3358 .channels_max = 8, 3359 .rates = CS48L32_RATES, 3360 .formats = CS48L32_FORMATS, 3361 }, 3362 .ops = &cs48l32_compress_dai_ops, 3363 }, 3364 { 3365 .name = "cs48l32-dsp-trace", 3366 .id = 4, 3367 .capture = { 3368 .stream_name = "Audio Trace DSP", 3369 .channels_min = 1, 3370 .channels_max = 8, 3371 .rates = CS48L32_RATES, 3372 .formats = CS48L32_FORMATS, 3373 }, 3374 }, 3375 { 3376 .name = "cs48l32-cpu-voicectrl", 3377 .id = 5, 3378 .capture = { 3379 .stream_name = "Voice Ctrl CPU", 3380 .channels_min = 1, 3381 .channels_max = 8, 3382 .rates = CS48L32_RATES, 3383 .formats = CS48L32_FORMATS, 3384 }, 3385 .ops = &cs48l32_compress_dai_ops, 3386 }, 3387 { 3388 .name = "cs48l32-dsp-voicectrl", 3389 .id = 6, 3390 .capture = { 3391 .stream_name = "Voice Ctrl DSP", 3392 .channels_min = 1, 3393 .channels_max = 8, 3394 .rates = CS48L32_RATES, 3395 .formats = CS48L32_FORMATS, 3396 }, 3397 }, 3398 }; 3399 3400 static int cs48l32_init_inputs(struct snd_soc_component *component) 3401 { 3402 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 3403 struct regmap *regmap = cs48l32_codec->core.regmap; 3404 unsigned int ana_mode_l, ana_mode_r, dig_mode; 3405 int i; 3406 3407 /* 3408 * Initialize input modes from the A settings. For muxed inputs the 3409 * B settings will be applied if the mux is changed 3410 */ 3411 switch (cs48l32_codec->in_type[0][0]) { 3412 default: 3413 case CS48L32_IN_TYPE_DIFF: 3414 ana_mode_l = 0; 3415 break; 3416 case CS48L32_IN_TYPE_SE: 3417 ana_mode_l = 1 << CS48L32_INx_SRC_SHIFT; 3418 break; 3419 } 3420 3421 switch (cs48l32_codec->in_type[1][0]) { 3422 default: 3423 case CS48L32_IN_TYPE_DIFF: 3424 ana_mode_r = 0; 3425 break; 3426 case CS48L32_IN_TYPE_SE: 3427 ana_mode_r = 1 << CS48L32_INx_SRC_SHIFT; 3428 break; 3429 } 3430 3431 dev_dbg(cs48l32_codec->core.dev, "IN1_1 Analogue mode=#%x,#%x\n", 3432 ana_mode_l, ana_mode_r); 3433 3434 regmap_update_bits(regmap, 3435 CS48L32_IN1L_CONTROL1, 3436 CS48L32_INx_SRC_MASK, 3437 ana_mode_l); 3438 3439 regmap_update_bits(regmap, 3440 CS48L32_IN1R_CONTROL1, 3441 CS48L32_INx_SRC_MASK, 3442 ana_mode_r); 3443 3444 for (i = 0; i < ARRAY_SIZE(cs48l32_codec->pdm_sup); i++) { 3445 dig_mode = cs48l32_codec->pdm_sup[i] << CS48L32_IN1_PDM_SUP_SHIFT; 3446 3447 dev_dbg(cs48l32_codec->core.dev, "IN%d PDM_SUP=#%x\n", i + 1, dig_mode); 3448 3449 regmap_update_bits(regmap, 3450 CS48L32_INPUT1_CONTROL1 + (i * 0x40), 3451 CS48L32_IN1_PDM_SUP_MASK, dig_mode); 3452 } 3453 3454 return 0; 3455 } 3456 3457 static int cs48l32_init_dai(struct cs48l32_codec *cs48l32_codec, int id) 3458 { 3459 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[id]; 3460 3461 dai_priv->clk = CS48L32_CLK_SYSCLK_1; 3462 dai_priv->constraint = cs48l32_constraint; 3463 3464 return 0; 3465 } 3466 3467 static int cs48l32_init_eq(struct cs48l32_codec *cs48l32_codec) 3468 { 3469 struct regmap *regmap = cs48l32_codec->core.regmap; 3470 unsigned int reg = CS48L32_EQ1_BAND1_COEFF1, mode; 3471 __be16 *data; 3472 int i, ret; 3473 3474 ret = regmap_read(regmap, CS48L32_EQ_CONTROL2, &mode); 3475 if (ret < 0) { 3476 dev_err(cs48l32_codec->core.dev, "Error reading EQ mode: %d\n", ret); 3477 goto out; 3478 } 3479 3480 for (i = 0; i < 4; ++i) { 3481 cs48l32_codec->eq_mode[i] = (mode >> i) & 0x1; 3482 3483 data = &cs48l32_codec->eq_coefficients[i][0]; 3484 ret = regmap_raw_read(regmap, reg + (i * 68), data, 3485 CS48L32_EQ_BLOCK_SZ); 3486 if (ret < 0) { 3487 dev_err(cs48l32_codec->core.dev, 3488 "Error reading EQ coefficients: %d\n", ret); 3489 goto out; 3490 } 3491 } 3492 3493 out: 3494 return ret; 3495 } 3496 3497 static int cs48l32_component_probe(struct snd_soc_component *component) 3498 { 3499 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 3500 int i, ret; 3501 3502 snd_soc_component_init_regmap(component, cs48l32_codec->core.regmap); 3503 3504 ret = cs48l32_init_inputs(component); 3505 if (ret) 3506 return ret; 3507 3508 for (i = 0; i < ARRAY_SIZE(cs48l32_dai); i++) 3509 cs48l32_init_dai(cs48l32_codec, i); 3510 3511 ret = cs48l32_init_eq(cs48l32_codec); 3512 if (ret) 3513 return ret; 3514 3515 wm_adsp2_component_probe(&cs48l32_codec->dsp, component); 3516 3517 /* Unmask DSP IRQs */ 3518 regmap_clear_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_7, 3519 CS48L32_DSP1_MPU_ERR_EINT1_MASK | CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK); 3520 regmap_clear_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_9, 3521 CS48L32_DSP1_IRQ0_EINT1_MASK); 3522 3523 return 0; 3524 } 3525 3526 static void cs48l32_component_remove(struct snd_soc_component *component) 3527 { 3528 struct cs48l32_codec *cs48l32_codec = snd_soc_component_get_drvdata(component); 3529 3530 /* Mask DSP IRQs */ 3531 regmap_set_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_7, 3532 CS48L32_DSP1_MPU_ERR_EINT1_MASK | CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK); 3533 regmap_set_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_9, 3534 CS48L32_DSP1_IRQ0_EINT1_MASK); 3535 3536 wm_adsp2_component_remove(&cs48l32_codec->dsp, component); 3537 } 3538 3539 static const struct snd_soc_component_driver cs48l32_soc_component_drv = { 3540 .probe = &cs48l32_component_probe, 3541 .remove = &cs48l32_component_remove, 3542 .set_sysclk = &cs48l32_set_sysclk, 3543 .set_pll = &cs48l32_set_fll, 3544 .name = "cs48l32-codec", 3545 .compress_ops = &cs48l32_compress_ops, 3546 .controls = cs48l32_snd_controls, 3547 .num_controls = ARRAY_SIZE(cs48l32_snd_controls), 3548 .dapm_widgets = cs48l32_dapm_widgets, 3549 .num_dapm_widgets = ARRAY_SIZE(cs48l32_dapm_widgets), 3550 .dapm_routes = cs48l32_dapm_routes, 3551 .num_dapm_routes = ARRAY_SIZE(cs48l32_dapm_routes), 3552 .use_pmdown_time = 1, 3553 .endianness = 1, 3554 }; 3555 3556 static int cs48l32_prop_read_u32_array(struct cs48l32_codec *cs48l32_codec, 3557 const char *propname, 3558 u32 *dest, 3559 int n_max) 3560 { 3561 struct cs48l32 *cs48l32 = &cs48l32_codec->core; 3562 int ret; 3563 3564 ret = device_property_read_u32_array(cs48l32->dev, propname, dest, n_max); 3565 if (ret == -EINVAL) 3566 return -ENOENT; 3567 3568 if (ret < 0) 3569 return dev_err_probe(cs48l32->dev, ret, "%s malformed\n", propname); 3570 3571 return 0; 3572 } 3573 3574 static void cs48l32_prop_get_in_type(struct cs48l32_codec *cs48l32_codec) 3575 { 3576 const char *propname = "cirrus,in-type"; 3577 u32 tmp[CS48L32_MAX_ANALOG_INPUT * CS48L32_MAX_IN_MUX_WAYS]; 3578 int i, in_idx, mux_way_idx, ret; 3579 3580 static_assert(ARRAY_SIZE(tmp) == 3581 ARRAY_SIZE(cs48l32_codec->in_type) * ARRAY_SIZE(cs48l32_codec->in_type[0])); 3582 3583 ret = cs48l32_prop_read_u32_array(cs48l32_codec, propname, tmp, ARRAY_SIZE(tmp)); 3584 if (ret < 0) 3585 return; 3586 3587 in_idx = 0; 3588 mux_way_idx = 0; 3589 for (i = 0; i < ARRAY_SIZE(tmp); ++i) { 3590 switch (tmp[i]) { 3591 case CS48L32_IN_TYPE_DIFF: 3592 case CS48L32_IN_TYPE_SE: 3593 cs48l32_codec->in_type[in_idx][mux_way_idx] = tmp[i]; 3594 break; 3595 default: 3596 dev_warn(cs48l32_codec->core.dev, "Illegal %s value %d ignored\n", 3597 propname, tmp[i]); 3598 break; 3599 } 3600 3601 /* 3602 * Property array is [mux_way][in_channel]. Swap to 3603 * [in_channel][mux_way] for convenience. 3604 */ 3605 if (++in_idx == ARRAY_SIZE(cs48l32_codec->in_type)) { 3606 in_idx = 0; 3607 ++mux_way_idx; 3608 } 3609 } 3610 } 3611 3612 static void cs48l32_prop_get_pdm_sup(struct cs48l32_codec *cs48l32_codec) 3613 { 3614 const char *propname = "cirrus,pdm-sup"; 3615 u32 tmp[CS48L32_MAX_ANALOG_INPUT]; 3616 int i; 3617 3618 static_assert(ARRAY_SIZE(tmp) == ARRAY_SIZE(cs48l32_codec->pdm_sup)); 3619 3620 cs48l32_prop_read_u32_array(cs48l32_codec, propname, tmp, ARRAY_SIZE(tmp)); 3621 3622 for (i = 0; i < ARRAY_SIZE(cs48l32_codec->pdm_sup); i++) { 3623 switch (tmp[i]) { 3624 case CS48L32_PDM_SUP_VOUT_MIC: 3625 case CS48L32_PDM_SUP_MICBIAS1: 3626 cs48l32_codec->pdm_sup[i] = tmp[i]; 3627 break; 3628 default: 3629 dev_warn(cs48l32_codec->core.dev, "Illegal %s value %d ignored\n", 3630 propname, cs48l32_codec->pdm_sup[i]); 3631 break; 3632 } 3633 } 3634 } 3635 3636 static void cs48l32_handle_properties(struct cs48l32_codec *cs48l32_codec) 3637 { 3638 cs48l32_prop_get_in_type(cs48l32_codec); 3639 cs48l32_prop_get_pdm_sup(cs48l32_codec); 3640 } 3641 3642 static int cs48l32_request_interrupt(struct cs48l32_codec *cs48l32_codec) 3643 { 3644 int irq = cs48l32_codec->core.irq; 3645 int ret; 3646 3647 if (irq < 1) 3648 return 0; 3649 3650 /* 3651 * Don't use devm because this must be freed before destroying the 3652 * rest of the driver 3653 */ 3654 ret = request_threaded_irq(irq, NULL, cs48l32_irq, 3655 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 3656 "cs48l32", cs48l32_codec); 3657 if (ret) 3658 return dev_err_probe(cs48l32_codec->core.dev, ret, "Failed to get IRQ\n"); 3659 3660 return 0; 3661 } 3662 3663 static int cs48l32_create_codec_component(struct cs48l32_codec *cs48l32_codec) 3664 { 3665 struct wm_adsp *dsp; 3666 int ret; 3667 3668 ASSERT_STRUCT_OFFSET(struct cs48l32_codec, dsp, 0); 3669 static_assert(ARRAY_SIZE(cs48l32_dai) == ARRAY_SIZE(cs48l32_codec->dai)); 3670 3671 cs48l32_handle_properties(cs48l32_codec); 3672 3673 dsp = &cs48l32_codec->dsp; 3674 dsp->part = "cs48l32"; 3675 dsp->cs_dsp.num = 1; 3676 dsp->cs_dsp.type = WMFW_HALO; 3677 dsp->cs_dsp.rev = 0; 3678 dsp->cs_dsp.dev = cs48l32_codec->core.dev; 3679 dsp->cs_dsp.regmap = cs48l32_codec->core.regmap; 3680 dsp->cs_dsp.base = CS48L32_DSP1_CLOCK_FREQ; 3681 dsp->cs_dsp.base_sysinfo = CS48L32_DSP1_SYS_INFO_ID; 3682 dsp->cs_dsp.mem = cs48l32_dsp1_regions; 3683 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs48l32_dsp1_regions); 3684 dsp->pre_run = cs48l32_dsp_pre_run; 3685 3686 ret = wm_halo_init(dsp); 3687 if (ret != 0) 3688 return ret; 3689 3690 cs48l32_codec->fll.codec = cs48l32_codec; 3691 cs48l32_codec->fll.id = 1; 3692 cs48l32_codec->fll.base = CS48L32_FLL1_CONTROL1; 3693 cs48l32_codec->fll.sts_addr = CS48L32_IRQ1_STS_6; 3694 cs48l32_codec->fll.sts_mask = CS48L32_FLL1_LOCK_STS1_MASK; 3695 cs48l32_init_fll(&cs48l32_codec->fll); 3696 3697 ret = cs48l32_request_interrupt(cs48l32_codec); 3698 if (ret) 3699 goto err_dsp; 3700 3701 ret = devm_snd_soc_register_component(cs48l32_codec->core.dev, 3702 &cs48l32_soc_component_drv, 3703 cs48l32_dai, 3704 ARRAY_SIZE(cs48l32_dai)); 3705 if (ret < 0) { 3706 dev_err_probe(cs48l32_codec->core.dev, ret, "Failed to register component\n"); 3707 goto err_dsp; 3708 } 3709 3710 return 0; 3711 3712 err_dsp: 3713 wm_adsp2_remove(&cs48l32_codec->dsp); 3714 3715 return ret; 3716 } 3717 3718 static int cs48l32_wait_for_boot(struct cs48l32 *cs48l32) 3719 { 3720 unsigned int val; 3721 int ret; 3722 3723 ret = regmap_read_poll_timeout(cs48l32->regmap, CS48L32_IRQ1_EINT_2, val, 3724 ((val < 0xffffffff) && (val & CS48L32_BOOT_DONE_EINT1_MASK)), 3725 1000, CS48L32_BOOT_TIMEOUT_US); 3726 if (ret) { 3727 dev_err(cs48l32->dev, "BOOT_DONE timed out\n"); 3728 return -ETIMEDOUT; 3729 } 3730 3731 ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val); 3732 if (ret) { 3733 dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret); 3734 return ret; 3735 } 3736 3737 if (val & BIT(CS48L32_MCU_STS_SHIFT)) { 3738 dev_err(cs48l32->dev, "MCU boot failed\n"); 3739 return -EIO; 3740 } 3741 3742 pm_runtime_mark_last_busy(cs48l32->dev); 3743 3744 return 0; 3745 } 3746 3747 static int cs48l32_soft_reset(struct cs48l32 *cs48l32) 3748 { 3749 int ret; 3750 3751 ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC); 3752 if (ret != 0) { 3753 dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret); 3754 return ret; 3755 } 3756 3757 usleep_range(CS48L32_SOFT_RESET_US, CS48L32_SOFT_RESET_US + 1000); 3758 3759 return 0; 3760 } 3761 3762 static void cs48l32_enable_hard_reset(struct cs48l32 *cs48l32) 3763 { 3764 if (cs48l32->reset_gpio) 3765 gpiod_set_raw_value_cansleep(cs48l32->reset_gpio, 0); 3766 } 3767 3768 static void cs48l32_disable_hard_reset(struct cs48l32 *cs48l32) 3769 { 3770 if (cs48l32->reset_gpio) { 3771 gpiod_set_raw_value_cansleep(cs48l32->reset_gpio, 1); 3772 usleep_range(CS48L32_HARD_RESET_MIN_US, CS48L32_HARD_RESET_MIN_US + 1000); 3773 } 3774 } 3775 3776 static int cs48l32_runtime_resume(struct device *dev) 3777 { 3778 struct cs48l32_codec *cs48l32_codec = dev_get_drvdata(dev); 3779 struct cs48l32 *cs48l32 = &cs48l32_codec->core; 3780 unsigned int val; 3781 int ret; 3782 3783 ret = regulator_enable(cs48l32->vdd_d); 3784 if (ret) { 3785 dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret); 3786 return ret; 3787 } 3788 3789 usleep_range(CS48L32_SOFT_RESET_US, CS48L32_SOFT_RESET_US + 1000); 3790 3791 regcache_cache_only(cs48l32->regmap, false); 3792 3793 ret = cs48l32_wait_for_boot(cs48l32); 3794 if (ret) 3795 goto err; 3796 3797 /* Check whether registers reset during suspend */ 3798 regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val); 3799 if (!val) 3800 regcache_mark_dirty(cs48l32->regmap); 3801 else 3802 dev_dbg(cs48l32->dev, "Did not reset during suspend\n"); 3803 3804 ret = regcache_sync(cs48l32->regmap); 3805 if (ret) { 3806 dev_err(cs48l32->dev, "Failed to restore register cache\n"); 3807 goto err; 3808 } 3809 3810 return 0; 3811 3812 err: 3813 regcache_cache_only(cs48l32->regmap, true); 3814 regulator_disable(cs48l32->vdd_d); 3815 3816 return ret; 3817 } 3818 3819 static int cs48l32_runtime_suspend(struct device *dev) 3820 { 3821 struct cs48l32_codec *cs48l32_codec = dev_get_drvdata(dev); 3822 struct cs48l32 *cs48l32 = &cs48l32_codec->core; 3823 3824 /* Flag to detect if the registers reset during suspend */ 3825 regmap_write(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, 1); 3826 3827 regcache_cache_only(cs48l32->regmap, true); 3828 regulator_disable(cs48l32->vdd_d); 3829 3830 return 0; 3831 } 3832 3833 static const struct dev_pm_ops cs48l32_pm_ops = { 3834 RUNTIME_PM_OPS(cs48l32_runtime_suspend, cs48l32_runtime_resume, NULL) 3835 }; 3836 3837 static int cs48l32_configure_clk32k(struct cs48l32 *cs48l32) 3838 { 3839 int ret = 0; 3840 3841 ret = clk_prepare_enable(cs48l32->mclk1); 3842 if (ret) 3843 return dev_err_probe(cs48l32->dev, ret, "Failed to enable 32k clock\n"); 3844 3845 ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K, 3846 CS48L32_CLK_32K_EN_MASK | CS48L32_CLK_32K_SRC_MASK, 3847 CS48L32_CLK_32K_EN_MASK | CS48L32_32K_MCLK1); 3848 if (ret) { 3849 clk_disable_unprepare(cs48l32->mclk1); 3850 return dev_err_probe(cs48l32->dev, ret, "Failed to init 32k clock\n"); 3851 } 3852 3853 return 0; 3854 } 3855 3856 static int cs48l32_get_clocks(struct cs48l32 *cs48l32) 3857 { 3858 cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1"); 3859 if (IS_ERR(cs48l32->mclk1)) 3860 return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1), 3861 "Failed to get mclk1\n"); 3862 3863 return 0; 3864 } 3865 3866 static int cs48l32_get_reset_gpio(struct cs48l32 *cs48l32) 3867 { 3868 struct gpio_desc *reset; 3869 3870 reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW); 3871 if (IS_ERR(reset)) 3872 return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n"); 3873 3874 /* ACPI can override the GPIOD_OUT_LOW so ensure it starts low */ 3875 gpiod_set_raw_value_cansleep(reset, 0); 3876 3877 cs48l32->reset_gpio = reset; 3878 3879 return 0; 3880 } 3881 3882 static int cs48l32_spi_probe(struct spi_device *spi) 3883 { 3884 struct device *dev = &spi->dev; 3885 struct cs48l32_codec *cs48l32_codec; 3886 struct cs48l32 *cs48l32; 3887 unsigned int hwid, rev, otp_rev; 3888 int i, ret; 3889 3890 cs48l32_codec = devm_kzalloc(&spi->dev, sizeof(*cs48l32_codec), GFP_KERNEL); 3891 if (!cs48l32_codec) 3892 return -ENOMEM; 3893 3894 cs48l32 = &cs48l32_codec->core; 3895 cs48l32->dev = dev; 3896 cs48l32->irq = spi->irq; 3897 mutex_init(&cs48l32_codec->rate_lock); 3898 cs48l32_codec->in_vu_reg = CS48L32_INPUT_CONTROL3; 3899 3900 dev_set_drvdata(cs48l32->dev, cs48l32_codec); 3901 3902 ret = cs48l32_create_regmap(spi, cs48l32); 3903 if (ret) 3904 return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n"); 3905 3906 regcache_cache_only(cs48l32->regmap, true); 3907 3908 ret = cs48l32_get_reset_gpio(cs48l32); 3909 if (ret) 3910 return ret; 3911 3912 ret = cs48l32_get_clocks(cs48l32); 3913 if (ret) 3914 return ret; 3915 3916 static_assert(ARRAY_SIZE(cs48l32_core_supplies) == ARRAY_SIZE(cs48l32->core_supplies)); 3917 for (i = 0; i < ARRAY_SIZE(cs48l32->core_supplies); i++) 3918 cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i]; 3919 3920 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs48l32->core_supplies), 3921 cs48l32->core_supplies); 3922 if (ret) 3923 return dev_err_probe(dev, ret, "Failed to request core supplies\n"); 3924 3925 cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "vdd-d"); 3926 if (IS_ERR(cs48l32->vdd_d)) 3927 return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request vdd-d\n"); 3928 3929 ret = regulator_bulk_enable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies); 3930 if (ret) 3931 return dev_err_probe(dev, ret, "Failed to enable core supplies\n"); 3932 3933 ret = regulator_enable(cs48l32->vdd_d); 3934 if (ret) { 3935 dev_err(dev, "Failed to enable vdd-d: %d\n", ret); 3936 goto err_enable; 3937 } 3938 3939 cs48l32_disable_hard_reset(cs48l32); 3940 3941 regcache_cache_only(cs48l32->regmap, false); 3942 3943 /* If we don't have a reset GPIO use a soft reset */ 3944 if (!cs48l32->reset_gpio) { 3945 ret = cs48l32_soft_reset(cs48l32); 3946 if (ret) 3947 goto err_reset; 3948 } 3949 3950 ret = cs48l32_wait_for_boot(cs48l32); 3951 if (ret) { 3952 dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret); 3953 goto err_reset; 3954 } 3955 3956 ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid); 3957 if (ret) { 3958 dev_err(dev, "Failed to read ID register: %d\n", ret); 3959 goto err_reset; 3960 } 3961 hwid &= CS48L32_DEVID_MASK; 3962 3963 switch (hwid) { 3964 case CS48L32_SILICON_ID: 3965 break; 3966 default: 3967 ret = -ENODEV; 3968 dev_err_probe(cs48l32->dev, ret, "Unknown device ID: %#x\n", hwid); 3969 goto err_reset; 3970 } 3971 3972 ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev); 3973 if (ret) { 3974 dev_err(dev, "Failed to read revision register: %d\n", ret); 3975 goto err_reset; 3976 } 3977 rev &= CS48L32_AREVID_MASK | CS48L32_MTLREVID_MASK; 3978 3979 ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev); 3980 if (ret) { 3981 dev_err(dev, "Failed to read OTP revision register: %d\n", ret); 3982 goto err_reset; 3983 } 3984 otp_rev &= CS48L32_OTPID_MASK; 3985 3986 dev_info(dev, "CS48L%x revision %X%u OTP%u\n", hwid & 0xff, 3987 rev >> CS48L32_AREVID_SHIFT, rev & CS48L32_MTLREVID_MASK, otp_rev); 3988 3989 /* Apply hardware patch */ 3990 ret = cs48l32_apply_patch(cs48l32); 3991 if (ret) { 3992 dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret); 3993 goto err_reset; 3994 } 3995 3996 /* BOOT_DONE interrupt is unmasked by default, so mask it */ 3997 ret = regmap_set_bits(cs48l32->regmap, CS48L32_IRQ1_MASK_2, CS48L32_BOOT_DONE_EINT1_MASK); 3998 3999 ret = cs48l32_configure_clk32k(cs48l32); 4000 if (ret) 4001 goto err_reset; 4002 4003 pm_runtime_set_active(cs48l32->dev); 4004 pm_runtime_set_autosuspend_delay(cs48l32->dev, 100); 4005 pm_runtime_use_autosuspend(cs48l32->dev); 4006 pm_runtime_enable(cs48l32->dev); 4007 4008 ret = cs48l32_create_codec_component(cs48l32_codec); 4009 if (ret) 4010 goto err_clk32k; 4011 4012 return 0; 4013 4014 err_clk32k: 4015 clk_disable_unprepare(cs48l32->mclk1); 4016 err_reset: 4017 cs48l32_enable_hard_reset(cs48l32); 4018 regulator_disable(cs48l32->vdd_d); 4019 err_enable: 4020 regulator_bulk_disable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies); 4021 4022 return ret; 4023 } 4024 4025 static void cs48l32_spi_remove(struct spi_device *spi) 4026 { 4027 struct cs48l32_codec *cs48l32_codec = spi_get_drvdata(spi); 4028 struct cs48l32 *cs48l32 = &cs48l32_codec->core; 4029 4030 /* Remove IRQ handler before destroying anything else */ 4031 if (cs48l32->irq >= 1) 4032 free_irq(cs48l32->irq, cs48l32_codec); 4033 4034 pm_runtime_disable(cs48l32->dev); 4035 regulator_disable(cs48l32->vdd_d); 4036 clk_disable_unprepare(cs48l32->mclk1); 4037 cs48l32_enable_hard_reset(cs48l32); 4038 regulator_bulk_disable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies); 4039 4040 mutex_destroy(&cs48l32_codec->rate_lock); 4041 } 4042 4043 static const struct of_device_id cs48l32_of_match[] = { 4044 { .compatible = "cirrus,cs48l32", }, 4045 {}, 4046 }; 4047 4048 static const struct spi_device_id cs48l32_spi_ids[] = { 4049 { "cs48l32", }, 4050 { }, 4051 }; 4052 MODULE_DEVICE_TABLE(spi, cs48l32_spi_ids); 4053 4054 static struct spi_driver cs48l32_spi_driver = { 4055 .driver = { 4056 .name = "cs48l32", 4057 .pm = pm_ptr(&cs48l32_pm_ops), 4058 .of_match_table = cs48l32_of_match, 4059 }, 4060 .probe = &cs48l32_spi_probe, 4061 .remove = &cs48l32_spi_remove, 4062 .id_table = cs48l32_spi_ids, 4063 }; 4064 module_spi_driver(cs48l32_spi_driver); 4065 4066 MODULE_DESCRIPTION("CS48L32 ASoC codec driver"); 4067 MODULE_AUTHOR("Stuart Henderson <stuarth@opensource.cirrus.com>"); 4068 MODULE_AUTHOR("Piotr Stankiewicz <piotrs@opensource.cirrus.com>"); 4069 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 4070 MODULE_LICENSE("GPL"); 4071