1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the OV7251 camera sensor.
4 *
5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2017-2018, Linaro Ltd.
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
24
25 #define OV7251_SC_MODE_SELECT 0x0100
26 #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0
27 #define OV7251_SC_MODE_SELECT_STREAMING 0x1
28
29 #define OV7251_CHIP_ID_HIGH 0x300a
30 #define OV7251_CHIP_ID_HIGH_BYTE 0x77
31 #define OV7251_CHIP_ID_LOW 0x300b
32 #define OV7251_CHIP_ID_LOW_BYTE 0x50
33 #define OV7251_SC_GP_IO_IN1 0x3029
34 #define OV7251_AEC_EXPO_0 0x3500
35 #define OV7251_AEC_EXPO_1 0x3501
36 #define OV7251_AEC_EXPO_2 0x3502
37 #define OV7251_AEC_AGC_ADJ_0 0x350a
38 #define OV7251_AEC_AGC_ADJ_1 0x350b
39 #define OV7251_TIMING_FORMAT1 0x3820
40 #define OV7251_TIMING_FORMAT1_VFLIP BIT(2)
41 #define OV7251_TIMING_FORMAT2 0x3821
42 #define OV7251_TIMING_FORMAT2_MIRROR BIT(2)
43 #define OV7251_PRE_ISP_00 0x5e00
44 #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7)
45 #define OV7251_PLL1_PRE_DIV_REG 0x30b4
46 #define OV7251_PLL1_MULT_REG 0x30b3
47 #define OV7251_PLL1_DIVIDER_REG 0x30b1
48 #define OV7251_PLL1_PIX_DIV_REG 0x30b0
49 #define OV7251_PLL1_MIPI_DIV_REG 0x30b5
50 #define OV7251_PLL2_PRE_DIV_REG 0x3098
51 #define OV7251_PLL2_MULT_REG 0x3099
52 #define OV7251_PLL2_DIVIDER_REG 0x309d
53 #define OV7251_PLL2_SYS_DIV_REG 0x309a
54 #define OV7251_PLL2_ADC_DIV_REG 0x309b
55
56 #define OV7251_NATIVE_WIDTH 656
57 #define OV7251_NATIVE_HEIGHT 496
58 #define OV7251_ACTIVE_START_LEFT 4
59 #define OV7251_ACTIVE_START_TOP 4
60 #define OV7251_ACTIVE_WIDTH 648
61 #define OV7251_ACTIVE_HEIGHT 488
62
63 #define OV7251_FIXED_PPL 928
64 #define OV7251_TIMING_VTS_REG 0x380e
65 #define OV7251_TIMING_MIN_VTS 1
66 #define OV7251_TIMING_MAX_VTS 0xffff
67 #define OV7251_INTEGRATION_MARGIN 20
68
69 struct reg_value {
70 u16 reg;
71 u8 val;
72 };
73
74 struct ov7251_mode_info {
75 u32 width;
76 u32 height;
77 u32 vts;
78 const struct reg_value *data;
79 u32 data_size;
80 u32 pixel_clock;
81 u32 link_freq;
82 u16 exposure_max;
83 u16 exposure_def;
84 struct v4l2_fract timeperframe;
85 };
86
87 struct ov7251_pll1_cfg {
88 unsigned int pre_div;
89 unsigned int mult;
90 unsigned int div;
91 unsigned int pix_div;
92 unsigned int mipi_div;
93 };
94
95 struct ov7251_pll2_cfg {
96 unsigned int pre_div;
97 unsigned int mult;
98 unsigned int div;
99 unsigned int sys_div;
100 unsigned int adc_div;
101 };
102
103 /*
104 * Rubbish ordering, but only PLL1 needs to have a separate configuration per
105 * link frequency and the array member needs to be last.
106 */
107 struct ov7251_pll_cfgs {
108 const struct ov7251_pll2_cfg *pll2;
109 const struct ov7251_pll1_cfg *pll1[];
110 };
111
112 enum xclk_rate {
113 OV7251_19_2_MHZ,
114 OV7251_24_MHZ,
115 OV7251_NUM_SUPPORTED_RATES
116 };
117
118 enum supported_link_freqs {
119 OV7251_LINK_FREQ_240_MHZ,
120 OV7251_LINK_FREQ_319_2_MHZ,
121 OV7251_NUM_SUPPORTED_LINK_FREQS
122 };
123
124 struct ov7251 {
125 struct i2c_client *i2c_client;
126 struct device *dev;
127 struct v4l2_subdev sd;
128 struct media_pad pad;
129 struct v4l2_fwnode_endpoint ep;
130 struct v4l2_mbus_framefmt fmt;
131 struct v4l2_rect crop;
132 struct clk *xclk;
133 u32 xclk_freq;
134
135 struct regulator *io_regulator;
136 struct regulator *core_regulator;
137 struct regulator *analog_regulator;
138
139 const struct ov7251_pll_cfgs *pll_cfgs;
140 enum supported_link_freqs link_freq_idx;
141 const struct ov7251_mode_info *current_mode;
142
143 struct v4l2_ctrl_handler ctrls;
144 struct v4l2_ctrl *pixel_clock;
145 struct v4l2_ctrl *link_freq;
146 struct v4l2_ctrl *exposure;
147 struct v4l2_ctrl *gain;
148 struct v4l2_ctrl *hblank;
149 struct v4l2_ctrl *vblank;
150
151 /* Cached register values */
152 u8 aec_pk_manual;
153 u8 pre_isp_00;
154 u8 timing_format1;
155 u8 timing_format2;
156
157 struct mutex lock; /* lock to protect power state, ctrls and mode */
158 bool power_on;
159
160 struct gpio_desc *enable_gpio;
161 };
162
to_ov7251(struct v4l2_subdev * sd)163 static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
164 {
165 return container_of(sd, struct ov7251, sd);
166 }
167
168 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = {
169 .pre_div = 0x03,
170 .mult = 0x4b,
171 .div = 0x01,
172 .pix_div = 0x0a,
173 .mipi_div = 0x05,
174 };
175
176 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = {
177 .pre_div = 0x01,
178 .mult = 0x85,
179 .div = 0x04,
180 .pix_div = 0x0a,
181 .mipi_div = 0x05,
182 };
183
184 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = {
185 .pre_div = 0x03,
186 .mult = 0x64,
187 .div = 0x01,
188 .pix_div = 0x0a,
189 .mipi_div = 0x05,
190 };
191
192 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = {
193 .pre_div = 0x05,
194 .mult = 0x85,
195 .div = 0x02,
196 .pix_div = 0x0a,
197 .mipi_div = 0x05,
198 };
199
200 static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = {
201 .pre_div = 0x04,
202 .mult = 0x32,
203 .div = 0x00,
204 .sys_div = 0x05,
205 .adc_div = 0x04,
206 };
207
208 static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = {
209 .pre_div = 0x04,
210 .mult = 0x28,
211 .div = 0x00,
212 .sys_div = 0x05,
213 .adc_div = 0x04,
214 };
215
216 static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = {
217 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
218 .pll1 = {
219 [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz,
220 [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz,
221 },
222 };
223
224 static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = {
225 .pll2 = &ov7251_pll2_cfg_24_mhz,
226 .pll1 = {
227 [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz,
228 [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz,
229 },
230 };
231
232 static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = {
233 [OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz,
234 [OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz,
235 };
236
237 static const struct reg_value ov7251_global_init_setting[] = {
238 { 0x0103, 0x01 },
239 { 0x303b, 0x02 },
240 };
241
242 static const struct reg_value ov7251_setting_vga_30fps[] = {
243 { 0x3005, 0x00 },
244 { 0x3012, 0xc0 },
245 { 0x3013, 0xd2 },
246 { 0x3014, 0x04 },
247 { 0x3016, 0xf0 },
248 { 0x3017, 0xf0 },
249 { 0x3018, 0xf0 },
250 { 0x301a, 0xf0 },
251 { 0x301b, 0xf0 },
252 { 0x301c, 0xf0 },
253 { 0x3023, 0x05 },
254 { 0x3037, 0xf0 },
255 { 0x3106, 0xda },
256 { 0x3503, 0x07 },
257 { 0x3509, 0x10 },
258 { 0x3600, 0x1c },
259 { 0x3602, 0x62 },
260 { 0x3620, 0xb7 },
261 { 0x3622, 0x04 },
262 { 0x3626, 0x21 },
263 { 0x3627, 0x30 },
264 { 0x3630, 0x44 },
265 { 0x3631, 0x35 },
266 { 0x3634, 0x60 },
267 { 0x3636, 0x00 },
268 { 0x3662, 0x01 },
269 { 0x3663, 0x70 },
270 { 0x3664, 0x50 },
271 { 0x3666, 0x0a },
272 { 0x3669, 0x1a },
273 { 0x366a, 0x00 },
274 { 0x366b, 0x50 },
275 { 0x3673, 0x01 },
276 { 0x3674, 0xff },
277 { 0x3675, 0x03 },
278 { 0x3705, 0xc1 },
279 { 0x3709, 0x40 },
280 { 0x373c, 0x08 },
281 { 0x3742, 0x00 },
282 { 0x3757, 0xb3 },
283 { 0x3788, 0x00 },
284 { 0x37a8, 0x01 },
285 { 0x37a9, 0xc0 },
286 { 0x3800, 0x00 },
287 { 0x3801, 0x04 },
288 { 0x3802, 0x00 },
289 { 0x3803, 0x04 },
290 { 0x3804, 0x02 },
291 { 0x3805, 0x8b },
292 { 0x3806, 0x01 },
293 { 0x3807, 0xeb },
294 { 0x3808, 0x02 }, /* width high */
295 { 0x3809, 0x80 }, /* width low */
296 { 0x380a, 0x01 }, /* height high */
297 { 0x380b, 0xe0 }, /* height low */
298 { 0x380c, 0x03 }, /* total horiz timing high */
299 { 0x380d, 0xa0 }, /* total horiz timing low */
300 { 0x380e, 0x06 }, /* total vertical timing high */
301 { 0x380f, 0xbc }, /* total vertical timing low */
302 { 0x3810, 0x00 },
303 { 0x3811, 0x04 },
304 { 0x3812, 0x00 },
305 { 0x3813, 0x05 },
306 { 0x3814, 0x11 },
307 { 0x3815, 0x11 },
308 { 0x3820, 0x40 },
309 { 0x3821, 0x00 },
310 { 0x382f, 0x0e },
311 { 0x3832, 0x00 },
312 { 0x3833, 0x05 },
313 { 0x3834, 0x00 },
314 { 0x3835, 0x0c },
315 { 0x3837, 0x00 },
316 { 0x3b80, 0x00 },
317 { 0x3b81, 0xa5 },
318 { 0x3b82, 0x10 },
319 { 0x3b83, 0x00 },
320 { 0x3b84, 0x08 },
321 { 0x3b85, 0x00 },
322 { 0x3b86, 0x01 },
323 { 0x3b87, 0x00 },
324 { 0x3b88, 0x00 },
325 { 0x3b89, 0x00 },
326 { 0x3b8a, 0x00 },
327 { 0x3b8b, 0x05 },
328 { 0x3b8c, 0x00 },
329 { 0x3b8d, 0x00 },
330 { 0x3b8e, 0x00 },
331 { 0x3b8f, 0x1a },
332 { 0x3b94, 0x05 },
333 { 0x3b95, 0xf2 },
334 { 0x3b96, 0x40 },
335 { 0x3c00, 0x89 },
336 { 0x3c01, 0x63 },
337 { 0x3c02, 0x01 },
338 { 0x3c03, 0x00 },
339 { 0x3c04, 0x00 },
340 { 0x3c05, 0x03 },
341 { 0x3c06, 0x00 },
342 { 0x3c07, 0x06 },
343 { 0x3c0c, 0x01 },
344 { 0x3c0d, 0xd0 },
345 { 0x3c0e, 0x02 },
346 { 0x3c0f, 0x0a },
347 { 0x4001, 0x42 },
348 { 0x4004, 0x04 },
349 { 0x4005, 0x00 },
350 { 0x404e, 0x01 },
351 { 0x4300, 0xff },
352 { 0x4301, 0x00 },
353 { 0x4315, 0x00 },
354 { 0x4501, 0x48 },
355 { 0x4600, 0x00 },
356 { 0x4601, 0x4e },
357 { 0x4801, 0x0f },
358 { 0x4806, 0x0f },
359 { 0x4819, 0xaa },
360 { 0x4823, 0x3e },
361 { 0x4837, 0x19 },
362 { 0x4a0d, 0x00 },
363 { 0x4a47, 0x7f },
364 { 0x4a49, 0xf0 },
365 { 0x4a4b, 0x30 },
366 { 0x5000, 0x85 },
367 { 0x5001, 0x80 },
368 };
369
370 static const struct reg_value ov7251_setting_vga_60fps[] = {
371 { 0x3005, 0x00 },
372 { 0x3012, 0xc0 },
373 { 0x3013, 0xd2 },
374 { 0x3014, 0x04 },
375 { 0x3016, 0x10 },
376 { 0x3017, 0x00 },
377 { 0x3018, 0x00 },
378 { 0x301a, 0x00 },
379 { 0x301b, 0x00 },
380 { 0x301c, 0x00 },
381 { 0x3023, 0x05 },
382 { 0x3037, 0xf0 },
383 { 0x3106, 0xda },
384 { 0x3503, 0x07 },
385 { 0x3509, 0x10 },
386 { 0x3600, 0x1c },
387 { 0x3602, 0x62 },
388 { 0x3620, 0xb7 },
389 { 0x3622, 0x04 },
390 { 0x3626, 0x21 },
391 { 0x3627, 0x30 },
392 { 0x3630, 0x44 },
393 { 0x3631, 0x35 },
394 { 0x3634, 0x60 },
395 { 0x3636, 0x00 },
396 { 0x3662, 0x01 },
397 { 0x3663, 0x70 },
398 { 0x3664, 0x50 },
399 { 0x3666, 0x0a },
400 { 0x3669, 0x1a },
401 { 0x366a, 0x00 },
402 { 0x366b, 0x50 },
403 { 0x3673, 0x01 },
404 { 0x3674, 0xff },
405 { 0x3675, 0x03 },
406 { 0x3705, 0xc1 },
407 { 0x3709, 0x40 },
408 { 0x373c, 0x08 },
409 { 0x3742, 0x00 },
410 { 0x3757, 0xb3 },
411 { 0x3788, 0x00 },
412 { 0x37a8, 0x01 },
413 { 0x37a9, 0xc0 },
414 { 0x3800, 0x00 },
415 { 0x3801, 0x04 },
416 { 0x3802, 0x00 },
417 { 0x3803, 0x04 },
418 { 0x3804, 0x02 },
419 { 0x3805, 0x8b },
420 { 0x3806, 0x01 },
421 { 0x3807, 0xeb },
422 { 0x3808, 0x02 }, /* width high */
423 { 0x3809, 0x80 }, /* width low */
424 { 0x380a, 0x01 }, /* height high */
425 { 0x380b, 0xe0 }, /* height low */
426 { 0x380c, 0x03 }, /* total horiz timing high */
427 { 0x380d, 0xa0 }, /* total horiz timing low */
428 { 0x380e, 0x03 }, /* total vertical timing high */
429 { 0x380f, 0x5c }, /* total vertical timing low */
430 { 0x3810, 0x00 },
431 { 0x3811, 0x04 },
432 { 0x3812, 0x00 },
433 { 0x3813, 0x05 },
434 { 0x3814, 0x11 },
435 { 0x3815, 0x11 },
436 { 0x3820, 0x40 },
437 { 0x3821, 0x00 },
438 { 0x382f, 0x0e },
439 { 0x3832, 0x00 },
440 { 0x3833, 0x05 },
441 { 0x3834, 0x00 },
442 { 0x3835, 0x0c },
443 { 0x3837, 0x00 },
444 { 0x3b80, 0x00 },
445 { 0x3b81, 0xa5 },
446 { 0x3b82, 0x10 },
447 { 0x3b83, 0x00 },
448 { 0x3b84, 0x08 },
449 { 0x3b85, 0x00 },
450 { 0x3b86, 0x01 },
451 { 0x3b87, 0x00 },
452 { 0x3b88, 0x00 },
453 { 0x3b89, 0x00 },
454 { 0x3b8a, 0x00 },
455 { 0x3b8b, 0x05 },
456 { 0x3b8c, 0x00 },
457 { 0x3b8d, 0x00 },
458 { 0x3b8e, 0x00 },
459 { 0x3b8f, 0x1a },
460 { 0x3b94, 0x05 },
461 { 0x3b95, 0xf2 },
462 { 0x3b96, 0x40 },
463 { 0x3c00, 0x89 },
464 { 0x3c01, 0x63 },
465 { 0x3c02, 0x01 },
466 { 0x3c03, 0x00 },
467 { 0x3c04, 0x00 },
468 { 0x3c05, 0x03 },
469 { 0x3c06, 0x00 },
470 { 0x3c07, 0x06 },
471 { 0x3c0c, 0x01 },
472 { 0x3c0d, 0xd0 },
473 { 0x3c0e, 0x02 },
474 { 0x3c0f, 0x0a },
475 { 0x4001, 0x42 },
476 { 0x4004, 0x04 },
477 { 0x4005, 0x00 },
478 { 0x404e, 0x01 },
479 { 0x4300, 0xff },
480 { 0x4301, 0x00 },
481 { 0x4315, 0x00 },
482 { 0x4501, 0x48 },
483 { 0x4600, 0x00 },
484 { 0x4601, 0x4e },
485 { 0x4801, 0x0f },
486 { 0x4806, 0x0f },
487 { 0x4819, 0xaa },
488 { 0x4823, 0x3e },
489 { 0x4837, 0x19 },
490 { 0x4a0d, 0x00 },
491 { 0x4a47, 0x7f },
492 { 0x4a49, 0xf0 },
493 { 0x4a4b, 0x30 },
494 { 0x5000, 0x85 },
495 { 0x5001, 0x80 },
496 };
497
498 static const struct reg_value ov7251_setting_vga_90fps[] = {
499 { 0x3005, 0x00 },
500 { 0x3012, 0xc0 },
501 { 0x3013, 0xd2 },
502 { 0x3014, 0x04 },
503 { 0x3016, 0x10 },
504 { 0x3017, 0x00 },
505 { 0x3018, 0x00 },
506 { 0x301a, 0x00 },
507 { 0x301b, 0x00 },
508 { 0x301c, 0x00 },
509 { 0x3023, 0x05 },
510 { 0x3037, 0xf0 },
511 { 0x3106, 0xda },
512 { 0x3503, 0x07 },
513 { 0x3509, 0x10 },
514 { 0x3600, 0x1c },
515 { 0x3602, 0x62 },
516 { 0x3620, 0xb7 },
517 { 0x3622, 0x04 },
518 { 0x3626, 0x21 },
519 { 0x3627, 0x30 },
520 { 0x3630, 0x44 },
521 { 0x3631, 0x35 },
522 { 0x3634, 0x60 },
523 { 0x3636, 0x00 },
524 { 0x3662, 0x01 },
525 { 0x3663, 0x70 },
526 { 0x3664, 0x50 },
527 { 0x3666, 0x0a },
528 { 0x3669, 0x1a },
529 { 0x366a, 0x00 },
530 { 0x366b, 0x50 },
531 { 0x3673, 0x01 },
532 { 0x3674, 0xff },
533 { 0x3675, 0x03 },
534 { 0x3705, 0xc1 },
535 { 0x3709, 0x40 },
536 { 0x373c, 0x08 },
537 { 0x3742, 0x00 },
538 { 0x3757, 0xb3 },
539 { 0x3788, 0x00 },
540 { 0x37a8, 0x01 },
541 { 0x37a9, 0xc0 },
542 { 0x3800, 0x00 },
543 { 0x3801, 0x04 },
544 { 0x3802, 0x00 },
545 { 0x3803, 0x04 },
546 { 0x3804, 0x02 },
547 { 0x3805, 0x8b },
548 { 0x3806, 0x01 },
549 { 0x3807, 0xeb },
550 { 0x3808, 0x02 }, /* width high */
551 { 0x3809, 0x80 }, /* width low */
552 { 0x380a, 0x01 }, /* height high */
553 { 0x380b, 0xe0 }, /* height low */
554 { 0x380c, 0x03 }, /* total horiz timing high */
555 { 0x380d, 0xa0 }, /* total horiz timing low */
556 { 0x380e, 0x02 }, /* total vertical timing high */
557 { 0x380f, 0x3c }, /* total vertical timing low */
558 { 0x3810, 0x00 },
559 { 0x3811, 0x04 },
560 { 0x3812, 0x00 },
561 { 0x3813, 0x05 },
562 { 0x3814, 0x11 },
563 { 0x3815, 0x11 },
564 { 0x3820, 0x40 },
565 { 0x3821, 0x00 },
566 { 0x382f, 0x0e },
567 { 0x3832, 0x00 },
568 { 0x3833, 0x05 },
569 { 0x3834, 0x00 },
570 { 0x3835, 0x0c },
571 { 0x3837, 0x00 },
572 { 0x3b80, 0x00 },
573 { 0x3b81, 0xa5 },
574 { 0x3b82, 0x10 },
575 { 0x3b83, 0x00 },
576 { 0x3b84, 0x08 },
577 { 0x3b85, 0x00 },
578 { 0x3b86, 0x01 },
579 { 0x3b87, 0x00 },
580 { 0x3b88, 0x00 },
581 { 0x3b89, 0x00 },
582 { 0x3b8a, 0x00 },
583 { 0x3b8b, 0x05 },
584 { 0x3b8c, 0x00 },
585 { 0x3b8d, 0x00 },
586 { 0x3b8e, 0x00 },
587 { 0x3b8f, 0x1a },
588 { 0x3b94, 0x05 },
589 { 0x3b95, 0xf2 },
590 { 0x3b96, 0x40 },
591 { 0x3c00, 0x89 },
592 { 0x3c01, 0x63 },
593 { 0x3c02, 0x01 },
594 { 0x3c03, 0x00 },
595 { 0x3c04, 0x00 },
596 { 0x3c05, 0x03 },
597 { 0x3c06, 0x00 },
598 { 0x3c07, 0x06 },
599 { 0x3c0c, 0x01 },
600 { 0x3c0d, 0xd0 },
601 { 0x3c0e, 0x02 },
602 { 0x3c0f, 0x0a },
603 { 0x4001, 0x42 },
604 { 0x4004, 0x04 },
605 { 0x4005, 0x00 },
606 { 0x404e, 0x01 },
607 { 0x4300, 0xff },
608 { 0x4301, 0x00 },
609 { 0x4315, 0x00 },
610 { 0x4501, 0x48 },
611 { 0x4600, 0x00 },
612 { 0x4601, 0x4e },
613 { 0x4801, 0x0f },
614 { 0x4806, 0x0f },
615 { 0x4819, 0xaa },
616 { 0x4823, 0x3e },
617 { 0x4837, 0x19 },
618 { 0x4a0d, 0x00 },
619 { 0x4a47, 0x7f },
620 { 0x4a49, 0xf0 },
621 { 0x4a4b, 0x30 },
622 { 0x5000, 0x85 },
623 { 0x5001, 0x80 },
624 };
625
626 static const unsigned long supported_xclk_rates[] = {
627 [OV7251_19_2_MHZ] = 19200000,
628 [OV7251_24_MHZ] = 24000000,
629 };
630
631 static const s64 link_freq[] = {
632 [OV7251_LINK_FREQ_240_MHZ] = 240000000,
633 [OV7251_LINK_FREQ_319_2_MHZ] = 319200000,
634 };
635
636 static const s64 pixel_rates[] = {
637 [OV7251_LINK_FREQ_240_MHZ] = 48000000,
638 [OV7251_LINK_FREQ_319_2_MHZ] = 63840000,
639 };
640
641 static const struct ov7251_mode_info ov7251_mode_info_data[] = {
642 {
643 .width = 640,
644 .height = 480,
645 .vts = 1724,
646 .data = ov7251_setting_vga_30fps,
647 .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
648 .exposure_max = 1704,
649 .exposure_def = 504,
650 .timeperframe = {
651 .numerator = 100,
652 .denominator = 3000
653 }
654 },
655 {
656 .width = 640,
657 .height = 480,
658 .vts = 860,
659 .data = ov7251_setting_vga_60fps,
660 .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
661 .exposure_max = 840,
662 .exposure_def = 504,
663 .timeperframe = {
664 .numerator = 100,
665 .denominator = 6014
666 }
667 },
668 {
669 .width = 640,
670 .height = 480,
671 .vts = 572,
672 .data = ov7251_setting_vga_90fps,
673 .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
674 .exposure_max = 552,
675 .exposure_def = 504,
676 .timeperframe = {
677 .numerator = 100,
678 .denominator = 9043
679 }
680 },
681 };
682
ov7251_regulators_enable(struct ov7251 * ov7251)683 static int ov7251_regulators_enable(struct ov7251 *ov7251)
684 {
685 int ret;
686
687 /* OV7251 power up sequence requires core regulator
688 * to be enabled not earlier than io regulator
689 */
690
691 ret = regulator_enable(ov7251->io_regulator);
692 if (ret < 0) {
693 dev_err(ov7251->dev, "set io voltage failed\n");
694 return ret;
695 }
696
697 ret = regulator_enable(ov7251->analog_regulator);
698 if (ret) {
699 dev_err(ov7251->dev, "set analog voltage failed\n");
700 goto err_disable_io;
701 }
702
703 ret = regulator_enable(ov7251->core_regulator);
704 if (ret) {
705 dev_err(ov7251->dev, "set core voltage failed\n");
706 goto err_disable_analog;
707 }
708
709 return 0;
710
711 err_disable_analog:
712 regulator_disable(ov7251->analog_regulator);
713
714 err_disable_io:
715 regulator_disable(ov7251->io_regulator);
716
717 return ret;
718 }
719
ov7251_regulators_disable(struct ov7251 * ov7251)720 static void ov7251_regulators_disable(struct ov7251 *ov7251)
721 {
722 int ret;
723
724 ret = regulator_disable(ov7251->core_regulator);
725 if (ret < 0)
726 dev_err(ov7251->dev, "core regulator disable failed\n");
727
728 ret = regulator_disable(ov7251->analog_regulator);
729 if (ret < 0)
730 dev_err(ov7251->dev, "analog regulator disable failed\n");
731
732 ret = regulator_disable(ov7251->io_regulator);
733 if (ret < 0)
734 dev_err(ov7251->dev, "io regulator disable failed\n");
735 }
736
ov7251_write_reg(struct ov7251 * ov7251,u16 reg,u8 val)737 static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
738 {
739 u8 regbuf[3];
740 int ret;
741
742 regbuf[0] = reg >> 8;
743 regbuf[1] = reg & 0xff;
744 regbuf[2] = val;
745
746 ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
747 if (ret < 0) {
748 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
749 __func__, ret, reg, val);
750 return ret;
751 }
752
753 return 0;
754 }
755
ov7251_write_seq_regs(struct ov7251 * ov7251,u16 reg,u8 * val,u8 num)756 static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
757 u8 num)
758 {
759 u8 regbuf[5];
760 u8 nregbuf = sizeof(reg) + num * sizeof(*val);
761 int ret = 0;
762
763 if (nregbuf > sizeof(regbuf))
764 return -EINVAL;
765
766 regbuf[0] = reg >> 8;
767 regbuf[1] = reg & 0xff;
768
769 memcpy(regbuf + 2, val, num);
770
771 ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
772 if (ret < 0) {
773 dev_err(ov7251->dev,
774 "%s: write seq regs error %d: first reg=%x\n",
775 __func__, ret, reg);
776 return ret;
777 }
778
779 return 0;
780 }
781
ov7251_read_reg(struct ov7251 * ov7251,u16 reg,u8 * val)782 static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
783 {
784 u8 regbuf[2];
785 int ret;
786
787 regbuf[0] = reg >> 8;
788 regbuf[1] = reg & 0xff;
789
790 ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
791 if (ret < 0) {
792 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
793 __func__, ret, reg);
794 return ret;
795 }
796
797 ret = i2c_master_recv(ov7251->i2c_client, val, 1);
798 if (ret < 0) {
799 dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
800 __func__, ret, reg);
801 return ret;
802 }
803
804 return 0;
805 }
806
ov7251_pll_configure(struct ov7251 * ov7251)807 static int ov7251_pll_configure(struct ov7251 *ov7251)
808 {
809 const struct ov7251_pll_cfgs *configs;
810 int ret;
811
812 configs = ov7251->pll_cfgs;
813
814 ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
815 configs->pll1[ov7251->link_freq_idx]->pre_div);
816 if (ret < 0)
817 return ret;
818
819 ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
820 configs->pll1[ov7251->link_freq_idx]->mult);
821 if (ret < 0)
822 return ret;
823 ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
824 configs->pll1[ov7251->link_freq_idx]->div);
825 if (ret < 0)
826 return ret;
827
828 ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
829 configs->pll1[ov7251->link_freq_idx]->pix_div);
830 if (ret < 0)
831 return ret;
832
833 ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
834 configs->pll1[ov7251->link_freq_idx]->mipi_div);
835 if (ret < 0)
836 return ret;
837
838 ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
839 configs->pll2->pre_div);
840 if (ret < 0)
841 return ret;
842
843 ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
844 configs->pll2->mult);
845 if (ret < 0)
846 return ret;
847
848 ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
849 configs->pll2->div);
850 if (ret < 0)
851 return ret;
852
853 ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
854 configs->pll2->sys_div);
855 if (ret < 0)
856 return ret;
857
858 ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
859 configs->pll2->adc_div);
860
861 return ret;
862 }
863
ov7251_set_exposure(struct ov7251 * ov7251,s32 exposure)864 static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
865 {
866 u16 reg;
867 u8 val[3];
868
869 reg = OV7251_AEC_EXPO_0;
870 val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
871 val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */
872 val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */
873
874 return ov7251_write_seq_regs(ov7251, reg, val, 3);
875 }
876
ov7251_set_gain(struct ov7251 * ov7251,s32 gain)877 static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
878 {
879 u16 reg;
880 u8 val[2];
881
882 reg = OV7251_AEC_AGC_ADJ_0;
883 val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
884 val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */
885
886 return ov7251_write_seq_regs(ov7251, reg, val, 2);
887 }
888
ov7251_set_register_array(struct ov7251 * ov7251,const struct reg_value * settings,unsigned int num_settings)889 static int ov7251_set_register_array(struct ov7251 *ov7251,
890 const struct reg_value *settings,
891 unsigned int num_settings)
892 {
893 unsigned int i;
894 int ret;
895
896 for (i = 0; i < num_settings; ++i, ++settings) {
897 ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
898 if (ret < 0)
899 return ret;
900 }
901
902 return 0;
903 }
904
ov7251_set_power_on(struct device * dev)905 static int ov7251_set_power_on(struct device *dev)
906 {
907 struct i2c_client *client = container_of(dev, struct i2c_client, dev);
908 struct v4l2_subdev *sd = i2c_get_clientdata(client);
909 struct ov7251 *ov7251 = to_ov7251(sd);
910 int ret;
911 u32 wait_us;
912
913 ret = ov7251_regulators_enable(ov7251);
914 if (ret < 0)
915 return ret;
916
917 ret = clk_prepare_enable(ov7251->xclk);
918 if (ret < 0) {
919 dev_err(ov7251->dev, "clk prepare enable failed\n");
920 ov7251_regulators_disable(ov7251);
921 return ret;
922 }
923
924 usleep_range(1000, 1100);
925
926 gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
927
928 /* wait at least 65536 external clock cycles */
929 wait_us = DIV_ROUND_UP(65536 * 1000,
930 DIV_ROUND_UP(ov7251->xclk_freq, 1000));
931 usleep_range(wait_us, wait_us + 1000);
932
933 ret = ov7251_set_register_array(ov7251,
934 ov7251_global_init_setting,
935 ARRAY_SIZE(ov7251_global_init_setting));
936 if (ret < 0) {
937 dev_err(ov7251->dev, "error during global init\n");
938 gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
939 clk_disable_unprepare(ov7251->xclk);
940 ov7251_regulators_disable(ov7251);
941 return ret;
942 }
943
944 return ret;
945 }
946
ov7251_set_power_off(struct device * dev)947 static int ov7251_set_power_off(struct device *dev)
948 {
949 struct i2c_client *client = container_of(dev, struct i2c_client, dev);
950 struct v4l2_subdev *sd = i2c_get_clientdata(client);
951 struct ov7251 *ov7251 = to_ov7251(sd);
952
953 clk_disable_unprepare(ov7251->xclk);
954 gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
955 ov7251_regulators_disable(ov7251);
956
957 return 0;
958 }
959
ov7251_set_hflip(struct ov7251 * ov7251,s32 value)960 static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
961 {
962 u8 val = ov7251->timing_format2;
963 int ret;
964
965 if (value)
966 val |= OV7251_TIMING_FORMAT2_MIRROR;
967 else
968 val &= ~OV7251_TIMING_FORMAT2_MIRROR;
969
970 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
971 if (!ret)
972 ov7251->timing_format2 = val;
973
974 return ret;
975 }
976
ov7251_set_vflip(struct ov7251 * ov7251,s32 value)977 static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
978 {
979 u8 val = ov7251->timing_format1;
980 int ret;
981
982 if (value)
983 val |= OV7251_TIMING_FORMAT1_VFLIP;
984 else
985 val &= ~OV7251_TIMING_FORMAT1_VFLIP;
986
987 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
988 if (!ret)
989 ov7251->timing_format1 = val;
990
991 return ret;
992 }
993
ov7251_set_test_pattern(struct ov7251 * ov7251,s32 value)994 static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
995 {
996 u8 val = ov7251->pre_isp_00;
997 int ret;
998
999 if (value)
1000 val |= OV7251_PRE_ISP_00_TEST_PATTERN;
1001 else
1002 val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
1003
1004 ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
1005 if (!ret)
1006 ov7251->pre_isp_00 = val;
1007
1008 return ret;
1009 }
1010
1011 static const char * const ov7251_test_pattern_menu[] = {
1012 "Disabled",
1013 "Vertical Pattern Bars",
1014 };
1015
ov7251_vts_configure(struct ov7251 * ov7251,s32 vblank)1016 static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank)
1017 {
1018 u8 vts[2];
1019
1020 vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8;
1021 vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff);
1022
1023 return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2);
1024 }
1025
ov7251_s_ctrl(struct v4l2_ctrl * ctrl)1026 static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
1027 {
1028 struct ov7251 *ov7251 = container_of(ctrl->handler,
1029 struct ov7251, ctrls);
1030 int ret;
1031
1032 /* If VBLANK is altered we need to update exposure to compensate */
1033 if (ctrl->id == V4L2_CID_VBLANK) {
1034 int exposure_max;
1035
1036 exposure_max = ov7251->current_mode->height + ctrl->val -
1037 OV7251_INTEGRATION_MARGIN;
1038 __v4l2_ctrl_modify_range(ov7251->exposure,
1039 ov7251->exposure->minimum,
1040 exposure_max,
1041 ov7251->exposure->step,
1042 min(ov7251->exposure->val,
1043 exposure_max));
1044 }
1045
1046 /* v4l2_ctrl_lock() locks our mutex */
1047
1048 if (!pm_runtime_get_if_in_use(ov7251->dev))
1049 return 0;
1050
1051 switch (ctrl->id) {
1052 case V4L2_CID_EXPOSURE:
1053 ret = ov7251_set_exposure(ov7251, ctrl->val);
1054 break;
1055 case V4L2_CID_GAIN:
1056 ret = ov7251_set_gain(ov7251, ctrl->val);
1057 break;
1058 case V4L2_CID_TEST_PATTERN:
1059 ret = ov7251_set_test_pattern(ov7251, ctrl->val);
1060 break;
1061 case V4L2_CID_HFLIP:
1062 ret = ov7251_set_hflip(ov7251, ctrl->val);
1063 break;
1064 case V4L2_CID_VFLIP:
1065 ret = ov7251_set_vflip(ov7251, ctrl->val);
1066 break;
1067 case V4L2_CID_VBLANK:
1068 ret = ov7251_vts_configure(ov7251, ctrl->val);
1069 break;
1070 default:
1071 ret = -EINVAL;
1072 break;
1073 }
1074
1075 pm_runtime_put(ov7251->dev);
1076
1077 return ret;
1078 }
1079
1080 static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
1081 .s_ctrl = ov7251_s_ctrl,
1082 };
1083
ov7251_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1084 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
1085 struct v4l2_subdev_state *sd_state,
1086 struct v4l2_subdev_mbus_code_enum *code)
1087 {
1088 if (code->index > 0)
1089 return -EINVAL;
1090
1091 code->code = MEDIA_BUS_FMT_Y10_1X10;
1092
1093 return 0;
1094 }
1095
ov7251_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1096 static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
1097 struct v4l2_subdev_state *sd_state,
1098 struct v4l2_subdev_frame_size_enum *fse)
1099 {
1100 if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
1101 return -EINVAL;
1102
1103 if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
1104 return -EINVAL;
1105
1106 fse->min_width = ov7251_mode_info_data[fse->index].width;
1107 fse->max_width = ov7251_mode_info_data[fse->index].width;
1108 fse->min_height = ov7251_mode_info_data[fse->index].height;
1109 fse->max_height = ov7251_mode_info_data[fse->index].height;
1110
1111 return 0;
1112 }
1113
ov7251_enum_frame_ival(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)1114 static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
1115 struct v4l2_subdev_state *sd_state,
1116 struct v4l2_subdev_frame_interval_enum *fie)
1117 {
1118 unsigned int index = fie->index;
1119 unsigned int i;
1120
1121 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1122 if (fie->width != ov7251_mode_info_data[i].width ||
1123 fie->height != ov7251_mode_info_data[i].height)
1124 continue;
1125
1126 if (index-- == 0) {
1127 fie->interval = ov7251_mode_info_data[i].timeperframe;
1128 return 0;
1129 }
1130 }
1131
1132 return -EINVAL;
1133 }
1134
1135 static struct v4l2_mbus_framefmt *
__ov7251_get_pad_format(struct ov7251 * ov7251,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)1136 __ov7251_get_pad_format(struct ov7251 *ov7251,
1137 struct v4l2_subdev_state *sd_state,
1138 unsigned int pad,
1139 enum v4l2_subdev_format_whence which)
1140 {
1141 switch (which) {
1142 case V4L2_SUBDEV_FORMAT_TRY:
1143 return v4l2_subdev_state_get_format(sd_state, pad);
1144 case V4L2_SUBDEV_FORMAT_ACTIVE:
1145 return &ov7251->fmt;
1146 default:
1147 return NULL;
1148 }
1149 }
1150
ov7251_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1151 static int ov7251_get_format(struct v4l2_subdev *sd,
1152 struct v4l2_subdev_state *sd_state,
1153 struct v4l2_subdev_format *format)
1154 {
1155 struct ov7251 *ov7251 = to_ov7251(sd);
1156
1157 mutex_lock(&ov7251->lock);
1158 format->format = *__ov7251_get_pad_format(ov7251, sd_state,
1159 format->pad,
1160 format->which);
1161 mutex_unlock(&ov7251->lock);
1162
1163 return 0;
1164 }
1165
1166 static struct v4l2_rect *
__ov7251_get_pad_crop(struct ov7251 * ov7251,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)1167 __ov7251_get_pad_crop(struct ov7251 *ov7251,
1168 struct v4l2_subdev_state *sd_state,
1169 unsigned int pad, enum v4l2_subdev_format_whence which)
1170 {
1171 switch (which) {
1172 case V4L2_SUBDEV_FORMAT_TRY:
1173 return v4l2_subdev_state_get_crop(sd_state, pad);
1174 case V4L2_SUBDEV_FORMAT_ACTIVE:
1175 return &ov7251->crop;
1176 default:
1177 return NULL;
1178 }
1179 }
1180
avg_fps(const struct v4l2_fract * t)1181 static inline u32 avg_fps(const struct v4l2_fract *t)
1182 {
1183 return (t->denominator + (t->numerator >> 1)) / t->numerator;
1184 }
1185
1186 static const struct ov7251_mode_info *
ov7251_find_mode_by_ival(struct ov7251 * ov7251,struct v4l2_fract * timeperframe)1187 ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1188 {
1189 const struct ov7251_mode_info *mode = ov7251->current_mode;
1190 unsigned int fps_req = avg_fps(timeperframe);
1191 unsigned int max_dist_match = (unsigned int) -1;
1192 unsigned int i, n = 0;
1193
1194 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1195 unsigned int dist;
1196 unsigned int fps_tmp;
1197
1198 if (mode->width != ov7251_mode_info_data[i].width ||
1199 mode->height != ov7251_mode_info_data[i].height)
1200 continue;
1201
1202 fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1203
1204 dist = abs(fps_req - fps_tmp);
1205
1206 if (dist < max_dist_match) {
1207 n = i;
1208 max_dist_match = dist;
1209 }
1210 }
1211
1212 return &ov7251_mode_info_data[n];
1213 }
1214
ov7251_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1215 static int ov7251_set_format(struct v4l2_subdev *sd,
1216 struct v4l2_subdev_state *sd_state,
1217 struct v4l2_subdev_format *format)
1218 {
1219 struct ov7251 *ov7251 = to_ov7251(sd);
1220 struct v4l2_mbus_framefmt *__format;
1221 int vblank_max, vblank_def;
1222 struct v4l2_rect *__crop;
1223 const struct ov7251_mode_info *new_mode;
1224 int ret = 0;
1225
1226 mutex_lock(&ov7251->lock);
1227
1228 __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
1229 format->which);
1230
1231 new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1232 ARRAY_SIZE(ov7251_mode_info_data),
1233 width, height,
1234 format->format.width, format->format.height);
1235
1236 __crop->width = new_mode->width;
1237 __crop->height = new_mode->height;
1238
1239 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1240 ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1241 1, new_mode->exposure_max,
1242 1, new_mode->exposure_def);
1243 if (ret < 0)
1244 goto exit;
1245
1246 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1247 new_mode->exposure_def);
1248 if (ret < 0)
1249 goto exit;
1250
1251 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1252 if (ret < 0)
1253 goto exit;
1254
1255 vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height;
1256 vblank_def = new_mode->vts - new_mode->height;
1257 ret = __v4l2_ctrl_modify_range(ov7251->vblank,
1258 OV7251_TIMING_MIN_VTS,
1259 vblank_max, 1, vblank_def);
1260 if (ret < 0)
1261 goto exit;
1262
1263 ov7251->current_mode = new_mode;
1264 }
1265
1266 __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
1267 format->which);
1268 __format->width = __crop->width;
1269 __format->height = __crop->height;
1270 __format->code = MEDIA_BUS_FMT_Y10_1X10;
1271 __format->field = V4L2_FIELD_NONE;
1272 __format->colorspace = V4L2_COLORSPACE_SRGB;
1273 __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1274 __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1275 __format->colorspace, __format->ycbcr_enc);
1276 __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1277
1278 format->format = *__format;
1279
1280 exit:
1281 mutex_unlock(&ov7251->lock);
1282
1283 return ret;
1284 }
1285
ov7251_init_state(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state)1286 static int ov7251_init_state(struct v4l2_subdev *subdev,
1287 struct v4l2_subdev_state *sd_state)
1288 {
1289 struct v4l2_subdev_format fmt = {
1290 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
1291 : V4L2_SUBDEV_FORMAT_ACTIVE,
1292 .format = {
1293 .width = 640,
1294 .height = 480
1295 }
1296 };
1297
1298 ov7251_set_format(subdev, sd_state, &fmt);
1299
1300 return 0;
1301 }
1302
ov7251_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1303 static int ov7251_get_selection(struct v4l2_subdev *sd,
1304 struct v4l2_subdev_state *sd_state,
1305 struct v4l2_subdev_selection *sel)
1306 {
1307 struct ov7251 *ov7251 = to_ov7251(sd);
1308
1309 switch (sel->target) {
1310 case V4L2_SEL_TGT_CROP_DEFAULT:
1311 case V4L2_SEL_TGT_CROP:
1312 mutex_lock(&ov7251->lock);
1313 sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
1314 sel->which);
1315 mutex_unlock(&ov7251->lock);
1316 break;
1317 case V4L2_SEL_TGT_NATIVE_SIZE:
1318 sel->r.top = 0;
1319 sel->r.left = 0;
1320 sel->r.width = OV7251_NATIVE_WIDTH;
1321 sel->r.height = OV7251_NATIVE_HEIGHT;
1322 break;
1323 case V4L2_SEL_TGT_CROP_BOUNDS:
1324 sel->r.top = OV7251_ACTIVE_START_TOP;
1325 sel->r.left = OV7251_ACTIVE_START_LEFT;
1326 sel->r.width = OV7251_ACTIVE_WIDTH;
1327 sel->r.height = OV7251_ACTIVE_HEIGHT;
1328 break;
1329 default:
1330 return -EINVAL;
1331 }
1332
1333 return 0;
1334 }
1335
ov7251_s_stream(struct v4l2_subdev * subdev,int enable)1336 static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1337 {
1338 struct ov7251 *ov7251 = to_ov7251(subdev);
1339 int ret;
1340
1341 mutex_lock(&ov7251->lock);
1342
1343 if (enable) {
1344 ret = pm_runtime_resume_and_get(ov7251->dev);
1345 if (ret) {
1346 mutex_unlock(&ov7251->lock);
1347 return ret;
1348 }
1349
1350 ret = ov7251_pll_configure(ov7251);
1351 if (ret) {
1352 dev_err(ov7251->dev, "error configuring PLLs\n");
1353 goto err_power_down;
1354 }
1355
1356 ret = ov7251_set_register_array(ov7251,
1357 ov7251->current_mode->data,
1358 ov7251->current_mode->data_size);
1359 if (ret < 0) {
1360 dev_err(ov7251->dev, "could not set mode %dx%d\n",
1361 ov7251->current_mode->width,
1362 ov7251->current_mode->height);
1363 goto err_power_down;
1364 }
1365 ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1366 if (ret < 0) {
1367 dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1368 goto err_power_down;
1369 }
1370 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1371 OV7251_SC_MODE_SELECT_STREAMING);
1372 if (ret)
1373 goto err_power_down;
1374 } else {
1375 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1376 OV7251_SC_MODE_SELECT_SW_STANDBY);
1377 pm_runtime_put(ov7251->dev);
1378 }
1379
1380 mutex_unlock(&ov7251->lock);
1381 return ret;
1382
1383 err_power_down:
1384 pm_runtime_put(ov7251->dev);
1385 mutex_unlock(&ov7251->lock);
1386 return ret;
1387 }
1388
ov7251_get_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1389 static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1390 struct v4l2_subdev_state *sd_state,
1391 struct v4l2_subdev_frame_interval *fi)
1392 {
1393 struct ov7251 *ov7251 = to_ov7251(subdev);
1394
1395 /*
1396 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1397 * subdev active state API.
1398 */
1399 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1400 return -EINVAL;
1401
1402 mutex_lock(&ov7251->lock);
1403 fi->interval = ov7251->current_mode->timeperframe;
1404 mutex_unlock(&ov7251->lock);
1405
1406 return 0;
1407 }
1408
ov7251_set_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1409 static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1410 struct v4l2_subdev_state *sd_state,
1411 struct v4l2_subdev_frame_interval *fi)
1412 {
1413 struct ov7251 *ov7251 = to_ov7251(subdev);
1414 const struct ov7251_mode_info *new_mode;
1415 int ret = 0;
1416
1417 /*
1418 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1419 * subdev active state API.
1420 */
1421 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1422 return -EINVAL;
1423
1424 mutex_lock(&ov7251->lock);
1425 new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1426
1427 if (new_mode != ov7251->current_mode) {
1428 ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1429 1, new_mode->exposure_max,
1430 1, new_mode->exposure_def);
1431 if (ret < 0)
1432 goto exit;
1433
1434 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1435 new_mode->exposure_def);
1436 if (ret < 0)
1437 goto exit;
1438
1439 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1440 if (ret < 0)
1441 goto exit;
1442
1443 ov7251->current_mode = new_mode;
1444 }
1445
1446 fi->interval = ov7251->current_mode->timeperframe;
1447
1448 exit:
1449 mutex_unlock(&ov7251->lock);
1450
1451 return ret;
1452 }
1453
1454 static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1455 .s_stream = ov7251_s_stream,
1456 };
1457
1458 static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1459 .enum_mbus_code = ov7251_enum_mbus_code,
1460 .enum_frame_size = ov7251_enum_frame_size,
1461 .enum_frame_interval = ov7251_enum_frame_ival,
1462 .get_fmt = ov7251_get_format,
1463 .set_fmt = ov7251_set_format,
1464 .get_selection = ov7251_get_selection,
1465 .get_frame_interval = ov7251_get_frame_interval,
1466 .set_frame_interval = ov7251_set_frame_interval,
1467 };
1468
1469 static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1470 .video = &ov7251_video_ops,
1471 .pad = &ov7251_subdev_pad_ops,
1472 };
1473
1474 static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {
1475 .init_state = ov7251_init_state,
1476 };
1477
ov7251_check_hwcfg(struct ov7251 * ov7251)1478 static int ov7251_check_hwcfg(struct ov7251 *ov7251)
1479 {
1480 struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev);
1481 struct v4l2_fwnode_endpoint bus_cfg = {
1482 .bus_type = V4L2_MBUS_CSI2_DPHY,
1483 };
1484 struct fwnode_handle *endpoint;
1485 unsigned int i, j;
1486 int ret;
1487
1488 /*
1489 * Sometimes the fwnode graph is initialized by the bridge driver
1490 * Bridge drivers doing this may also add GPIO mappings, wait for this.
1491 */
1492 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
1493 if (!endpoint)
1494 return dev_err_probe(ov7251->dev, -EPROBE_DEFER,
1495 "waiting for fwnode graph endpoint\n");
1496
1497 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1498 fwnode_handle_put(endpoint);
1499 if (ret)
1500 return dev_err_probe(ov7251->dev, ret,
1501 "parsing endpoint node failed\n");
1502
1503 if (!bus_cfg.nr_of_link_frequencies) {
1504 ret = dev_err_probe(ov7251->dev, -EINVAL,
1505 "no link frequencies defined\n");
1506 goto out_free_bus_cfg;
1507 }
1508
1509 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1510 for (j = 0; j < ARRAY_SIZE(link_freq); j++)
1511 if (bus_cfg.link_frequencies[i] == link_freq[j])
1512 break;
1513
1514 if (j < ARRAY_SIZE(link_freq))
1515 break;
1516 }
1517
1518 if (i == bus_cfg.nr_of_link_frequencies) {
1519 ret = dev_err_probe(ov7251->dev, -EINVAL,
1520 "no supported link freq found\n");
1521 goto out_free_bus_cfg;
1522 }
1523
1524 ov7251->link_freq_idx = i;
1525
1526 out_free_bus_cfg:
1527 v4l2_fwnode_endpoint_free(&bus_cfg);
1528
1529 return ret;
1530 }
1531
ov7251_detect_chip(struct ov7251 * ov7251)1532 static int ov7251_detect_chip(struct ov7251 *ov7251)
1533 {
1534 u8 chip_id_high, chip_id_low, chip_rev;
1535 int ret;
1536
1537 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1538 if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE)
1539 return dev_err_probe(ov7251->dev, -ENODEV,
1540 "could not read ID high\n");
1541
1542 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1543 if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE)
1544 return dev_err_probe(ov7251->dev, -ENODEV,
1545 "could not read ID low\n");
1546
1547 ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1548 if (ret < 0)
1549 return dev_err_probe(ov7251->dev, -ENODEV,
1550 "could not read revision\n");
1551 chip_rev >>= 4;
1552
1553 dev_info(ov7251->dev,
1554 "OV7251 revision %x (%s) detected at address 0x%02x\n",
1555 chip_rev,
1556 chip_rev == 0x4 ? "1A / 1B" :
1557 chip_rev == 0x5 ? "1C / 1D" :
1558 chip_rev == 0x6 ? "1E" :
1559 chip_rev == 0x7 ? "1F" : "unknown",
1560 ov7251->i2c_client->addr);
1561
1562 return 0;
1563 }
1564
ov7251_init_ctrls(struct ov7251 * ov7251)1565 static int ov7251_init_ctrls(struct ov7251 *ov7251)
1566 {
1567 int vblank_max, vblank_def;
1568 s64 pixel_rate;
1569 int hblank;
1570
1571 v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
1572 ov7251->ctrls.lock = &ov7251->lock;
1573
1574 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1575 V4L2_CID_HFLIP, 0, 1, 1, 0);
1576 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1577 V4L2_CID_VFLIP, 0, 1, 1, 0);
1578 ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1579 V4L2_CID_EXPOSURE, 1, 32, 1, 32);
1580 ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1581 V4L2_CID_GAIN, 16, 1023, 1, 16);
1582 v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
1583 V4L2_CID_TEST_PATTERN,
1584 ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1585 0, 0, ov7251_test_pattern_menu);
1586
1587 pixel_rate = pixel_rates[ov7251->link_freq_idx];
1588 ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
1589 &ov7251_ctrl_ops,
1590 V4L2_CID_PIXEL_RATE,
1591 pixel_rate, INT_MAX,
1592 pixel_rate, pixel_rate);
1593 ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
1594 &ov7251_ctrl_ops,
1595 V4L2_CID_LINK_FREQ,
1596 ARRAY_SIZE(link_freq) - 1,
1597 ov7251->link_freq_idx,
1598 link_freq);
1599 if (ov7251->link_freq)
1600 ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1601 if (ov7251->pixel_clock)
1602 ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1603
1604 hblank = OV7251_FIXED_PPL - ov7251->current_mode->width;
1605 ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1606 V4L2_CID_HBLANK, hblank, hblank, 1,
1607 hblank);
1608 if (ov7251->hblank)
1609 ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1610
1611 vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height;
1612 vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height;
1613 ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1614 V4L2_CID_VBLANK,
1615 OV7251_TIMING_MIN_VTS, vblank_max, 1,
1616 vblank_def);
1617
1618 ov7251->sd.ctrl_handler = &ov7251->ctrls;
1619
1620 if (ov7251->ctrls.error) {
1621 v4l2_ctrl_handler_free(&ov7251->ctrls);
1622 return ov7251->ctrls.error;
1623 }
1624
1625 return 0;
1626 }
1627
ov7251_probe(struct i2c_client * client)1628 static int ov7251_probe(struct i2c_client *client)
1629 {
1630 struct device *dev = &client->dev;
1631 struct ov7251 *ov7251;
1632 int ret;
1633 int i;
1634
1635 ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1636 if (!ov7251)
1637 return -ENOMEM;
1638
1639 ov7251->i2c_client = client;
1640 ov7251->dev = dev;
1641
1642 ret = ov7251_check_hwcfg(ov7251);
1643 if (ret)
1644 return ret;
1645
1646 /* get system clock (xclk) */
1647 ov7251->xclk = devm_v4l2_sensor_clk_get(dev, NULL);
1648 if (IS_ERR(ov7251->xclk))
1649 return dev_err_probe(dev, PTR_ERR(ov7251->xclk),
1650 "could not get xclk");
1651
1652 ov7251->xclk_freq = clk_get_rate(ov7251->xclk);
1653
1654 for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
1655 if (ov7251->xclk_freq == supported_xclk_rates[i])
1656 break;
1657
1658 if (i == ARRAY_SIZE(supported_xclk_rates))
1659 return dev_err_probe(dev, -EINVAL,
1660 "clock rate %u Hz is unsupported\n",
1661 ov7251->xclk_freq);
1662
1663 ov7251->pll_cfgs = ov7251_pll_cfgs[i];
1664
1665 ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1666 if (IS_ERR(ov7251->io_regulator)) {
1667 dev_err(dev, "cannot get io regulator\n");
1668 return PTR_ERR(ov7251->io_regulator);
1669 }
1670
1671 ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1672 if (IS_ERR(ov7251->core_regulator)) {
1673 dev_err(dev, "cannot get core regulator\n");
1674 return PTR_ERR(ov7251->core_regulator);
1675 }
1676
1677 ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1678 if (IS_ERR(ov7251->analog_regulator)) {
1679 dev_err(dev, "cannot get analog regulator\n");
1680 return PTR_ERR(ov7251->analog_regulator);
1681 }
1682
1683 ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
1684 if (IS_ERR(ov7251->enable_gpio)) {
1685 dev_err(dev, "cannot get enable gpio\n");
1686 return PTR_ERR(ov7251->enable_gpio);
1687 }
1688
1689 mutex_init(&ov7251->lock);
1690
1691 ov7251->current_mode = &ov7251_mode_info_data[0];
1692 ret = ov7251_init_ctrls(ov7251);
1693 if (ret) {
1694 dev_err_probe(dev, ret, "error during v4l2 ctrl init\n");
1695 goto destroy_mutex;
1696 }
1697
1698 v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
1699 ov7251->sd.internal_ops = &ov7251_internal_ops;
1700 ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1701 ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1702 ov7251->sd.dev = &client->dev;
1703 ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1704
1705 ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1706 if (ret < 0) {
1707 dev_err(dev, "could not register media entity\n");
1708 goto free_ctrl;
1709 }
1710
1711 ret = ov7251_set_power_on(ov7251->dev);
1712 if (ret)
1713 goto free_entity;
1714
1715 ret = ov7251_detect_chip(ov7251);
1716 if (ret)
1717 goto power_down;
1718
1719 pm_runtime_set_active(&client->dev);
1720 pm_runtime_get_noresume(&client->dev);
1721 pm_runtime_enable(&client->dev);
1722
1723 ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1724 &ov7251->pre_isp_00);
1725 if (ret < 0) {
1726 dev_err(dev, "could not read test pattern value\n");
1727 ret = -ENODEV;
1728 goto err_pm_runtime;
1729 }
1730
1731 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1732 &ov7251->timing_format1);
1733 if (ret < 0) {
1734 dev_err(dev, "could not read vflip value\n");
1735 ret = -ENODEV;
1736 goto err_pm_runtime;
1737 }
1738
1739 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1740 &ov7251->timing_format2);
1741 if (ret < 0) {
1742 dev_err(dev, "could not read hflip value\n");
1743 ret = -ENODEV;
1744 goto err_pm_runtime;
1745 }
1746
1747 pm_runtime_set_autosuspend_delay(&client->dev, 1000);
1748 pm_runtime_use_autosuspend(&client->dev);
1749 pm_runtime_put_autosuspend(&client->dev);
1750
1751 ret = v4l2_async_register_subdev(&ov7251->sd);
1752 if (ret < 0) {
1753 dev_err(dev, "could not register v4l2 device\n");
1754 goto free_entity;
1755 }
1756
1757 ov7251_init_state(&ov7251->sd, NULL);
1758
1759 return 0;
1760
1761 err_pm_runtime:
1762 pm_runtime_disable(ov7251->dev);
1763 pm_runtime_put_noidle(ov7251->dev);
1764 power_down:
1765 ov7251_set_power_off(ov7251->dev);
1766 free_entity:
1767 media_entity_cleanup(&ov7251->sd.entity);
1768 free_ctrl:
1769 v4l2_ctrl_handler_free(&ov7251->ctrls);
1770 destroy_mutex:
1771 mutex_destroy(&ov7251->lock);
1772
1773 return ret;
1774 }
1775
ov7251_remove(struct i2c_client * client)1776 static void ov7251_remove(struct i2c_client *client)
1777 {
1778 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1779 struct ov7251 *ov7251 = to_ov7251(sd);
1780
1781 v4l2_async_unregister_subdev(&ov7251->sd);
1782 media_entity_cleanup(&ov7251->sd.entity);
1783 v4l2_ctrl_handler_free(&ov7251->ctrls);
1784 mutex_destroy(&ov7251->lock);
1785
1786 pm_runtime_disable(ov7251->dev);
1787 if (!pm_runtime_status_suspended(ov7251->dev))
1788 ov7251_set_power_off(ov7251->dev);
1789 pm_runtime_set_suspended(ov7251->dev);
1790 }
1791
1792 static const struct dev_pm_ops ov7251_pm_ops = {
1793 SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL)
1794 };
1795
1796 static const struct of_device_id ov7251_of_match[] = {
1797 { .compatible = "ovti,ov7251" },
1798 { /* sentinel */ }
1799 };
1800 MODULE_DEVICE_TABLE(of, ov7251_of_match);
1801
1802 static const struct acpi_device_id ov7251_acpi_match[] = {
1803 { "INT347E" },
1804 { }
1805 };
1806 MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match);
1807
1808 static struct i2c_driver ov7251_i2c_driver = {
1809 .driver = {
1810 .of_match_table = ov7251_of_match,
1811 .acpi_match_table = ov7251_acpi_match,
1812 .name = "ov7251",
1813 .pm = &ov7251_pm_ops,
1814 },
1815 .probe = ov7251_probe,
1816 .remove = ov7251_remove,
1817 };
1818
1819 module_i2c_driver(ov7251_i2c_driver);
1820
1821 MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1822 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1823 MODULE_LICENSE("GPL v2");
1824