1/* 2 * Copyright 2014 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26 27/ { 28 #address-cells = <1>; 29 #size-cells = <1>; 30 model = "ARM RealView PB1176"; 31 compatible = "arm,realview-pb1176"; 32 33 chosen { }; 34 35 aliases { 36 serial0 = &pb1176_serial0; 37 serial1 = &pb1176_serial1; 38 serial2 = &pb1176_serial2; 39 serial3 = &pb1176_serial3; 40 serial4 = &fpga_serial; 41 }; 42 43 memory { 44 device_type = "memory"; 45 /* 128 MiB memory @ 0x0 */ 46 reg = <0x00000000 0x08000000>; 47 }; 48 49 /* The voltage to the MMC card is hardwired at 3.3V */ 50 vmmc: regulator-vmmc { 51 compatible = "regulator-fixed"; 52 regulator-name = "vmmc"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-boot-on; 56 }; 57 58 veth: regulator-veth { 59 compatible = "regulator-fixed"; 60 regulator-name = "veth"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-boot-on; 64 }; 65 66 xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <24000000>; 70 }; 71 72 timclk: clock-1000000 { 73 #clock-cells = <0>; 74 compatible = "fixed-factor-clock"; 75 clock-div = <24>; 76 clock-mult = <1>; 77 clocks = <&xtal24mhz>; 78 }; 79 80 /* FIXME: this actually hangs off the PLL clocks */ 81 pclk: clock-pclk { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <0>; 85 }; 86 87 flash@30000000 { 88 compatible = "arm,versatile-flash", "cfi-flash"; 89 reg = <0x30000000 0x4000000>; 90 bank-width = <4>; 91 partitions { 92 compatible = "arm,arm-firmware-suite"; 93 }; 94 }; 95 96 fpga_flash@38000000 { 97 compatible = "arm,versatile-flash", "cfi-flash"; 98 reg = <0x38000000 0x800000>; 99 bank-width = <4>; 100 partitions { 101 compatible = "arm,arm-firmware-suite"; 102 }; 103 }; 104 105 /* 106 * The "secure flash" contains things like the boot 107 * monitor so we don't want people to accidentally 108 * screw this up. Mark the device tree node disabled 109 * by default. 110 */ 111 secflash@3c000000 { 112 compatible = "arm,versatile-flash", "cfi-flash"; 113 reg = <0x3c000000 0x4000000>; 114 bank-width = <4>; 115 status = "disabled"; 116 }; 117 118 /* SMSC 9118 ethernet with PHY and EEPROM */ 119 ethernet@3a000000 { 120 compatible = "smsc,lan9118", "smsc,lan9115"; 121 reg = <0x3a000000 0x10000>; 122 interrupt-parent = <&intc_fpga1176>; 123 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 124 phy-mode = "mii"; 125 reg-io-width = <4>; 126 smsc,irq-active-high; 127 smsc,irq-push-pull; 128 vdd33a-supply = <&veth>; 129 vddvario-supply = <&veth>; 130 }; 131 132 usb@3b000000 { 133 compatible = "nxp,usb-isp1761"; 134 reg = <0x3b000000 0x20000>; 135 interrupt-parent = <&intc_fpga1176>; 136 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 137 dr_mode = "peripheral"; 138 }; 139 140 bridge { 141 compatible = "ti,ths8134a", "ti,ths8134"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 ports { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 port@0 { 150 reg = <0>; 151 152 vga_bridge_in: endpoint { 153 remote-endpoint = <&clcd_pads>; 154 }; 155 }; 156 157 port@1 { 158 reg = <1>; 159 160 vga_bridge_out: endpoint { 161 remote-endpoint = <&vga_con_in>; 162 }; 163 }; 164 }; 165 }; 166 167 vga { 168 compatible = "vga-connector"; 169 170 port { 171 vga_con_in: endpoint { 172 remote-endpoint = <&vga_bridge_out>; 173 }; 174 }; 175 }; 176 177 soc { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 compatible = "arm,realview-pb1176-soc", "simple-bus"; 181 regmap = <&syscon>; 182 ranges; 183 184 syscon: syscon@10000000 { 185 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; 186 reg = <0x10000000 0x1000>; 187 ranges = <0x0 0x10000000 0x1000>; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 191 led@8,0 { 192 compatible = "register-bit-led"; 193 reg = <0x08 0x04>; 194 offset = <0x08>; 195 mask = <0x01>; 196 label = "versatile:0"; 197 linux,default-trigger = "heartbeat"; 198 default-state = "on"; 199 }; 200 led@8,1 { 201 compatible = "register-bit-led"; 202 reg = <0x08 0x04>; 203 offset = <0x08>; 204 mask = <0x02>; 205 label = "versatile:1"; 206 linux,default-trigger = "mmc0"; 207 default-state = "off"; 208 }; 209 led@8,2 { 210 compatible = "register-bit-led"; 211 reg = <0x08 0x04>; 212 offset = <0x08>; 213 mask = <0x04>; 214 label = "versatile:2"; 215 linux,default-trigger = "cpu0"; 216 default-state = "off"; 217 }; 218 led@8,3 { 219 compatible = "register-bit-led"; 220 reg = <0x08 0x04>; 221 offset = <0x08>; 222 mask = <0x08>; 223 label = "versatile:3"; 224 default-state = "off"; 225 }; 226 led@8,4 { 227 compatible = "register-bit-led"; 228 reg = <0x08 0x04>; 229 offset = <0x08>; 230 mask = <0x10>; 231 label = "versatile:4"; 232 default-state = "off"; 233 }; 234 led@8,5 { 235 compatible = "register-bit-led"; 236 reg = <0x08 0x04>; 237 offset = <0x08>; 238 mask = <0x20>; 239 label = "versatile:5"; 240 default-state = "off"; 241 }; 242 led@8,6 { 243 compatible = "register-bit-led"; 244 reg = <0x08 0x04>; 245 offset = <0x08>; 246 mask = <0x40>; 247 label = "versatile:6"; 248 default-state = "off"; 249 }; 250 led@8,7 { 251 compatible = "register-bit-led"; 252 reg = <0x08 0x04>; 253 offset = <0x08>; 254 mask = <0x80>; 255 label = "versatile:7"; 256 default-state = "off"; 257 }; 258 oscclk0: clock-controller@c { 259 compatible = "arm,syscon-icst307"; 260 reg = <0x0c 0x04>; 261 #clock-cells = <0>; 262 lock-offset = <0x20>; 263 vco-offset = <0x0C>; 264 clocks = <&xtal24mhz>; 265 }; 266 oscclk1: clock-controller@10 { 267 compatible = "arm,syscon-icst307"; 268 reg = <0x10 0x04>; 269 #clock-cells = <0>; 270 lock-offset = <0x20>; 271 vco-offset = <0x10>; 272 clocks = <&xtal24mhz>; 273 }; 274 oscclk2: clock-controller@14 { 275 compatible = "arm,syscon-icst307"; 276 reg = <0x14 0x04>; 277 #clock-cells = <0>; 278 lock-offset = <0x20>; 279 vco-offset = <0x14>; 280 clocks = <&xtal24mhz>; 281 }; 282 oscclk3: clock-controller@18 { 283 compatible = "arm,syscon-icst307"; 284 reg = <0x18 0x04>; 285 #clock-cells = <0>; 286 lock-offset = <0x20>; 287 vco-offset = <0x18>; 288 clocks = <&xtal24mhz>; 289 }; 290 oscclk4: clock-controller@1c { 291 compatible = "arm,syscon-icst307"; 292 reg = <0x1c 0x04>; 293 #clock-cells = <0>; 294 lock-offset = <0x20>; 295 vco-offset = <0x1c>; 296 clocks = <&xtal24mhz>; 297 }; 298 }; 299 300 /* Primary DevChip GIC synthesized with the CPU */ 301 intc_dc1176: interrupt-controller@10120000 { 302 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 303 #interrupt-cells = <3>; 304 #address-cells = <1>; 305 interrupt-controller; 306 reg = <0x10121000 0x1000>, 307 <0x10120000 0x100>; 308 }; 309 310 L2: cache-controller { 311 compatible = "arm,l220-cache"; 312 reg = <0x10110000 0x1000>; 313 interrupt-parent = <&intc_dc1176>; 314 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 315 cache-unified; 316 cache-level = <2>; 317 /* 318 * Override default cache size, sets and 319 * associativity as these may be erroneously set 320 * up by boot loader(s). 321 */ 322 arm,override-auxreg; 323 cache-size = <131072>; // 128kB 324 cache-sets = <512>; 325 cache-line-size = <32>; 326 }; 327 328 pmu { 329 compatible = "arm,arm1176-pmu"; 330 interrupt-parent = <&intc_dc1176>; 331 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 332 }; 333 334 timer01: timer@10104000 { 335 compatible = "arm,sp804", "arm,primecell"; 336 reg = <0x10104000 0x1000>; 337 interrupt-parent = <&intc_dc1176>; 338 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&timclk>, <&timclk>, <&pclk>; 340 clock-names = "timer1", "timer2", "apb_pclk"; 341 }; 342 343 timer23: timer@10105000 { 344 compatible = "arm,sp804", "arm,primecell"; 345 reg = <0x10105000 0x1000>; 346 interrupt-parent = <&intc_dc1176>; 347 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 348 arm,sp804-has-irq = <1>; 349 clocks = <&timclk>, <&timclk>, <&pclk>; 350 clock-names = "timer1", "timer2", "apb_pclk"; 351 }; 352 353 pb1176_rtc: rtc@10108000 { 354 compatible = "arm,pl031", "arm,primecell"; 355 reg = <0x10108000 0x1000>; 356 interrupt-parent = <&intc_dc1176>; 357 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&pclk>; 359 clock-names = "apb_pclk"; 360 }; 361 362 pb1176_gpio0: gpio@1010a000 { 363 compatible = "arm,pl061", "arm,primecell"; 364 reg = <0x1010a000 0x1000>; 365 gpio-controller; 366 interrupt-parent = <&intc_dc1176>; 367 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 368 #gpio-cells = <2>; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 clocks = <&pclk>; 372 clock-names = "apb_pclk"; 373 }; 374 375 pb1176_ssp: spi@1010b000 { 376 compatible = "arm,pl022", "arm,primecell"; 377 reg = <0x1010b000 0x1000>; 378 interrupt-parent = <&intc_dc1176>; 379 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&sspclk>, <&pclk>; 381 clock-names = "sspclk", "apb_pclk"; 382 }; 383 384 pb1176_serial0: serial@1010c000 { 385 compatible = "arm,pl011", "arm,primecell"; 386 reg = <0x1010c000 0x1000>; 387 interrupt-parent = <&intc_dc1176>; 388 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&uartclk>, <&pclk>; 390 clock-names = "uartclk", "apb_pclk"; 391 }; 392 393 pb1176_serial1: serial@1010d000 { 394 compatible = "arm,pl011", "arm,primecell"; 395 reg = <0x1010d000 0x1000>; 396 interrupt-parent = <&intc_dc1176>; 397 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&uartclk>, <&pclk>; 399 clock-names = "uartclk", "apb_pclk"; 400 }; 401 402 pb1176_serial2: serial@1010e000 { 403 compatible = "arm,pl011", "arm,primecell"; 404 reg = <0x1010e000 0x1000>; 405 interrupt-parent = <&intc_dc1176>; 406 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&uartclk>, <&pclk>; 408 clock-names = "uartclk", "apb_pclk"; 409 }; 410 411 pb1176_serial3: serial@1010f000 { 412 compatible = "arm,pl011", "arm,primecell"; 413 reg = <0x1010f000 0x1000>; 414 interrupt-parent = <&intc_dc1176>; 415 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&uartclk>, <&pclk>; 417 clock-names = "uartclk", "apb_pclk"; 418 }; 419 420 /* Direct-mapped development chip ROM */ 421 pb1176_rom@10200000 { 422 compatible = "mtd-rom"; 423 reg = <0x10200000 0x4000>; 424 bank-width = <1>; 425 }; 426 427 clcd@10112000 { 428 compatible = "arm,pl111", "arm,primecell"; 429 reg = <0x10112000 0x1000>; 430 interrupt-parent = <&intc_dc1176>; 431 interrupt-names = "combined"; 432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&oscclk0>, <&pclk>; 434 clock-names = "clcdclk", "apb_pclk"; 435 /* 1024x768 16bpp @65MHz works fine */ 436 max-memory-bandwidth = <95000000>; 437 438 port { 439 clcd_pads: endpoint { 440 remote-endpoint = <&vga_bridge_in>; 441 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 442 }; 443 }; 444 }; 445 }; 446 447 /* These peripherals are inside the FPGA rather than the DevChip */ 448 fpga { 449 #address-cells = <1>; 450 #size-cells = <1>; 451 compatible = "simple-bus"; 452 ranges; 453 454 i2c0: i2c@10002000 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "arm,versatile-i2c"; 458 reg = <0x10002000 0x1000>; 459 460 rtc@68 { 461 compatible = "dallas,ds1338"; 462 reg = <0x68>; 463 }; 464 }; 465 466 fpga_aaci: aaci@10004000 { 467 compatible = "arm,pl041", "arm,primecell"; 468 reg = <0x10004000 0x1000>; 469 interrupt-parent = <&intc_fpga1176>; 470 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&pclk>; 472 clock-names = "apb_pclk"; 473 }; 474 475 fpga_mci: mmcsd@10005000 { 476 compatible = "arm,pl18x", "arm,primecell"; 477 reg = <0x10005000 0x1000>; 478 interrupt-parent = <&intc_fpga1176>; 479 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, 480 <0 2 IRQ_TYPE_LEVEL_HIGH>; 481 /* Due to frequent FIFO overruns, use just 500 kHz */ 482 max-frequency = <500000>; 483 bus-width = <4>; 484 cap-sd-highspeed; 485 cap-mmc-highspeed; 486 clocks = <&mclk>, <&pclk>; 487 clock-names = "mclk", "apb_pclk"; 488 vmmc-supply = <&vmmc>; 489 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; 490 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; 491 }; 492 493 fpga_kmi0: kmi@10006000 { 494 compatible = "arm,pl050", "arm,primecell"; 495 reg = <0x10006000 0x1000>; 496 interrupt-parent = <&intc_fpga1176>; 497 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&kmiclk>, <&pclk>; 499 clock-names = "KMIREFCLK", "apb_pclk"; 500 }; 501 502 fpga_kmi1: kmi@10007000 { 503 compatible = "arm,pl050", "arm,primecell"; 504 reg = <0x10007000 0x1000>; 505 interrupt-parent = <&intc_fpga1176>; 506 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&kmiclk>, <&pclk>; 508 clock-names = "KMIREFCLK", "apb_pclk"; 509 }; 510 511 fpga_charlcd: charlcd@10008000 { 512 compatible = "arm,versatile-lcd"; 513 reg = <0x10008000 0x1000>; 514 interrupt-parent = <&intc_fpga1176>; 515 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&pclk>; 517 clock-names = "apb_pclk"; 518 }; 519 520 fpga_serial: serial@10009000 { 521 compatible = "arm,pl011", "arm,primecell"; 522 reg = <0x10009000 0x1000>; 523 interrupt-parent = <&intc_fpga1176>; 524 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&uartclk>, <&pclk>; 526 clock-names = "uartclk", "apb_pclk"; 527 }; 528 529 /* This GIC on the board is cascaded off the DevChip GIC */ 530 intc_fpga1176: interrupt-controller@10040000 { 531 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 532 #interrupt-cells = <3>; 533 #address-cells = <1>; 534 interrupt-controller; 535 reg = <0x10041000 0x1000>, 536 <0x10040000 0x100>; 537 interrupt-parent = <&intc_dc1176>; 538 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 541 fpga_gpio0: gpio@10014000 { 542 compatible = "arm,pl061", "arm,primecell"; 543 reg = <0x10014000 0x1000>; 544 gpio-controller; 545 interrupt-parent = <&intc_fpga1176>; 546 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 547 #gpio-cells = <2>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 clocks = <&pclk>; 551 clock-names = "apb_pclk"; 552 }; 553 554 fpga_gpio1: gpio@10015000 { 555 compatible = "arm,pl061", "arm,primecell"; 556 reg = <0x10015000 0x1000>; 557 gpio-controller; 558 interrupt-parent = <&intc_fpga1176>; 559 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 clocks = <&pclk>; 564 clock-names = "apb_pclk"; 565 }; 566 567 fpga_rtc: rtc@10017000 { 568 compatible = "arm,pl031", "arm,primecell"; 569 reg = <0x10017000 0x1000>; 570 interrupt-parent = <&intc_fpga1176>; 571 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&pclk>; 573 clock-names = "apb_pclk"; 574 }; 575 }; 576}; 577