1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Check for KVM_GET_REG_LIST regressions. 4 * 5 * Copyright (c) 2023 Intel Corporation 6 * 7 */ 8 #include <stdio.h> 9 #include "kvm_util.h" 10 #include "test_util.h" 11 #include "processor.h" 12 13 #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK) 14 15 enum { 16 VCPU_FEATURE_ISA_EXT = 0, 17 VCPU_FEATURE_SBI_EXT, 18 }; 19 20 enum { 21 KVM_RISC_V_REG_OFFSET_VSTART = 0, 22 KVM_RISC_V_REG_OFFSET_VL, 23 KVM_RISC_V_REG_OFFSET_VTYPE, 24 KVM_RISC_V_REG_OFFSET_VCSR, 25 KVM_RISC_V_REG_OFFSET_VLENB, 26 KVM_RISC_V_REG_OFFSET_MAX, 27 }; 28 29 static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; 30 static bool sbi_ext_enabled[KVM_RISCV_SBI_EXT_MAX]; 31 32 bool filter_reg(__u64 reg) 33 { 34 switch (reg & ~REG_MASK) { 35 /* 36 * Same set of ISA_EXT registers are not present on all host because 37 * ISA_EXT registers are visible to the KVM user space based on the 38 * ISA extensions available on the host. Also, disabling an ISA 39 * extension using corresponding ISA_EXT register does not affect 40 * the visibility of the ISA_EXT register itself. 41 * 42 * Based on above, we should filter-out all ISA_EXT registers. 43 * 44 * Note: The below list is alphabetically sorted. 45 */ 46 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A: 47 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C: 48 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D: 49 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F: 50 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H: 51 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I: 52 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M: 53 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V: 54 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMNPM: 55 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: 56 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: 57 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: 58 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM: 59 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: 60 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE: 61 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: 62 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: 63 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: 64 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: 65 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC: 66 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO: 67 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA: 68 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS: 69 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALASR: 70 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC: 71 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS: 72 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA: 73 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB: 74 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC: 75 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB: 76 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: 77 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: 78 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: 79 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: 80 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: 81 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: 82 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: 83 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD: 84 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: 85 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: 86 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN: 87 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: 88 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: 89 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM: 90 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP: 91 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ: 92 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE: 93 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFILP: 94 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS: 95 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR: 96 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND: 97 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR: 98 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI: 99 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL: 100 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: 101 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM: 102 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD: 103 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP: 104 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND: 105 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE: 106 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH: 107 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR: 108 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED: 109 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH: 110 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT: 111 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO: 112 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB: 113 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC: 114 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN: 115 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA: 116 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH: 117 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN: 118 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB: 119 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG: 120 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED: 121 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA: 122 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB: 123 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED: 124 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH: 125 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT: 126 /* 127 * Like ISA_EXT registers, SBI_EXT registers are only visible when the 128 * host supports them and disabling them does not affect the visibility 129 * of the SBI_EXT register itself. 130 */ 131 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01: 132 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME: 133 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI: 134 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE: 135 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST: 136 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM: 137 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU: 138 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN: 139 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SUSP: 140 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA: 141 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT: 142 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_MPXY: 143 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL: 144 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR: 145 return true; 146 /* AIA registers are always available when Ssaia can't be disabled */ 147 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): 148 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): 149 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): 150 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): 151 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): 152 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 153 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 154 return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; 155 /* 156 * FWFT misaligned delegation registers are always visible when the SBI FWFT 157 * extension is enable and the host supports the misaligned delegation. 158 */ 159 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable): 160 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags): 161 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value): 162 return sbi_ext_enabled[KVM_RISCV_SBI_EXT_FWFT]; 163 default: 164 break; 165 } 166 167 return false; 168 } 169 170 bool check_reject_set(int err) 171 { 172 return err == EINVAL; 173 } 174 175 static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, 176 u64 feature) 177 { 178 unsigned long vlenb_reg = 0; 179 int rc; 180 u64 reg, size; 181 182 /* Enable V extension so that we can get the vlenb register */ 183 rc = __vcpu_set_reg(vcpu, feature, 1); 184 if (rc) 185 return rc; 186 187 vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]); 188 if (!vlenb_reg) { 189 TEST_FAIL("Can't compute vector register size from zero vlenb\n"); 190 return -EPERM; 191 } 192 193 size = __builtin_ctzl(vlenb_reg); 194 size <<= KVM_REG_SIZE_SHIFT; 195 196 for (int i = 0; i < 32; i++) { 197 reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | KVM_REG_RISCV_VECTOR_REG(i); 198 s->regs[KVM_RISC_V_REG_OFFSET_MAX + i] = reg; 199 } 200 201 /* We should assert if disabling failed here while enabling succeeded before */ 202 vcpu_set_reg(vcpu, feature, 0); 203 204 return 0; 205 } 206 207 void check_fwft_feature(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, u64 feature) 208 { 209 unsigned long value; 210 int rc; 211 212 /* Enable SBI FWFT extension so that we can check the supported register */ 213 rc = __vcpu_set_reg(vcpu, feature, 1); 214 if (rc) 215 return; 216 217 for (int i = 0; i < s->regs_n; i++) { 218 if ((s->regs[i] & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE) { 219 rc = __vcpu_get_reg(vcpu, s->regs[i], &value); 220 __TEST_REQUIRE(!rc, "%s not available, skipping tests", s->name); 221 } 222 } 223 224 /* We should assert if disabling failed here while enabling succeeded before */ 225 vcpu_set_reg(vcpu, feature, 0); 226 } 227 228 void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) 229 { 230 unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; 231 struct vcpu_reg_sublist *s; 232 u64 feature; 233 int rc; 234 235 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) 236 __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); 237 238 /* 239 * Disable all extensions which were enabled by default 240 * if they were available in the risc-v host. 241 */ 242 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { 243 rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); 244 if (rc && isa_ext_state[i]) 245 isa_ext_cant_disable[i] = true; 246 } 247 248 for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 249 rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0); 250 TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error"); 251 } 252 253 for_each_sublist(c, s) { 254 if (!s->feature) 255 continue; 256 257 if (s->feature == KVM_RISCV_ISA_EXT_V) { 258 feature = RISCV_ISA_EXT_REG(s->feature); 259 rc = override_vector_reg_size(vcpu, s, feature); 260 if (rc) 261 goto skip; 262 } 263 264 switch (s->feature_type) { 265 case VCPU_FEATURE_ISA_EXT: 266 feature = RISCV_ISA_EXT_REG(s->feature); 267 break; 268 case VCPU_FEATURE_SBI_EXT: 269 feature = RISCV_SBI_EXT_REG(s->feature); 270 if (s->feature == KVM_RISCV_SBI_EXT_FWFT) 271 check_fwft_feature(vcpu, s, feature); 272 sbi_ext_enabled[s->feature] = true; 273 break; 274 default: 275 TEST_FAIL("Unknown feature type"); 276 } 277 278 /* Try to enable the desired extension */ 279 __vcpu_set_reg(vcpu, feature, 1); 280 281 skip: 282 /* Double check whether the desired extension was enabled */ 283 __TEST_REQUIRE(__vcpu_has_ext(vcpu, feature), 284 "%s not available, skipping tests", s->name); 285 } 286 } 287 288 static const char *config_id_to_str(const char *prefix, __u64 id) 289 { 290 /* reg_off is the offset into struct kvm_riscv_config */ 291 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); 292 293 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG); 294 295 switch (reg_off) { 296 case KVM_REG_RISCV_CONFIG_REG(isa): 297 return "KVM_REG_RISCV_CONFIG_REG(isa)"; 298 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): 299 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)"; 300 case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): 301 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)"; 302 case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size): 303 return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)"; 304 case KVM_REG_RISCV_CONFIG_REG(mvendorid): 305 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)"; 306 case KVM_REG_RISCV_CONFIG_REG(marchid): 307 return "KVM_REG_RISCV_CONFIG_REG(marchid)"; 308 case KVM_REG_RISCV_CONFIG_REG(mimpid): 309 return "KVM_REG_RISCV_CONFIG_REG(mimpid)"; 310 case KVM_REG_RISCV_CONFIG_REG(satp_mode): 311 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)"; 312 } 313 314 return strdup_printf("%lld /* UNKNOWN */", reg_off); 315 } 316 317 static const char *core_id_to_str(const char *prefix, __u64 id) 318 { 319 /* reg_off is the offset into struct kvm_riscv_core */ 320 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); 321 322 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE); 323 324 switch (reg_off) { 325 case KVM_REG_RISCV_CORE_REG(regs.pc): 326 return "KVM_REG_RISCV_CORE_REG(regs.pc)"; 327 case KVM_REG_RISCV_CORE_REG(regs.ra): 328 return "KVM_REG_RISCV_CORE_REG(regs.ra)"; 329 case KVM_REG_RISCV_CORE_REG(regs.sp): 330 return "KVM_REG_RISCV_CORE_REG(regs.sp)"; 331 case KVM_REG_RISCV_CORE_REG(regs.gp): 332 return "KVM_REG_RISCV_CORE_REG(regs.gp)"; 333 case KVM_REG_RISCV_CORE_REG(regs.tp): 334 return "KVM_REG_RISCV_CORE_REG(regs.tp)"; 335 case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2): 336 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 337 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); 338 case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1): 339 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 340 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); 341 case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7): 342 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)", 343 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0)); 344 case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11): 345 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 346 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2); 347 case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6): 348 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 349 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3); 350 case KVM_REG_RISCV_CORE_REG(mode): 351 return "KVM_REG_RISCV_CORE_REG(mode)"; 352 } 353 354 return strdup_printf("%lld /* UNKNOWN */", reg_off); 355 } 356 357 #define RISCV_CSR_GENERAL(csr) \ 358 "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" 359 #define RISCV_CSR_AIA(csr) \ 360 "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" 361 #define RISCV_CSR_SMSTATEEN(csr) \ 362 "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" 363 #define RISCV_CSR_ZICFISS(csr) \ 364 "KVM_REG_RISCV_CSR_ZICFISS | KVM_REG_RISCV_CSR_ZICFISS_REG(" #csr ")" 365 366 static const char *general_csr_id_to_str(__u64 reg_off) 367 { 368 /* reg_off is the offset into struct kvm_riscv_csr */ 369 switch (reg_off) { 370 case KVM_REG_RISCV_CSR_REG(sstatus): 371 return RISCV_CSR_GENERAL(sstatus); 372 case KVM_REG_RISCV_CSR_REG(sie): 373 return RISCV_CSR_GENERAL(sie); 374 case KVM_REG_RISCV_CSR_REG(stvec): 375 return RISCV_CSR_GENERAL(stvec); 376 case KVM_REG_RISCV_CSR_REG(sscratch): 377 return RISCV_CSR_GENERAL(sscratch); 378 case KVM_REG_RISCV_CSR_REG(sepc): 379 return RISCV_CSR_GENERAL(sepc); 380 case KVM_REG_RISCV_CSR_REG(scause): 381 return RISCV_CSR_GENERAL(scause); 382 case KVM_REG_RISCV_CSR_REG(stval): 383 return RISCV_CSR_GENERAL(stval); 384 case KVM_REG_RISCV_CSR_REG(sip): 385 return RISCV_CSR_GENERAL(sip); 386 case KVM_REG_RISCV_CSR_REG(satp): 387 return RISCV_CSR_GENERAL(satp); 388 case KVM_REG_RISCV_CSR_REG(scounteren): 389 return RISCV_CSR_GENERAL(scounteren); 390 case KVM_REG_RISCV_CSR_REG(senvcfg): 391 return RISCV_CSR_GENERAL(senvcfg); 392 } 393 394 return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off); 395 } 396 397 static const char *aia_csr_id_to_str(__u64 reg_off) 398 { 399 /* reg_off is the offset into struct kvm_riscv_aia_csr */ 400 switch (reg_off) { 401 case KVM_REG_RISCV_CSR_AIA_REG(siselect): 402 return RISCV_CSR_AIA(siselect); 403 case KVM_REG_RISCV_CSR_AIA_REG(iprio1): 404 return RISCV_CSR_AIA(iprio1); 405 case KVM_REG_RISCV_CSR_AIA_REG(iprio2): 406 return RISCV_CSR_AIA(iprio2); 407 case KVM_REG_RISCV_CSR_AIA_REG(sieh): 408 return RISCV_CSR_AIA(sieh); 409 case KVM_REG_RISCV_CSR_AIA_REG(siph): 410 return RISCV_CSR_AIA(siph); 411 case KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 412 return RISCV_CSR_AIA(iprio1h); 413 case KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 414 return RISCV_CSR_AIA(iprio2h); 415 } 416 417 return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off); 418 } 419 420 static const char *smstateen_csr_id_to_str(__u64 reg_off) 421 { 422 /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ 423 switch (reg_off) { 424 case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): 425 return RISCV_CSR_SMSTATEEN(sstateen0); 426 } 427 428 TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); 429 return NULL; 430 } 431 432 static const char *zicfiss_csr_id_to_str(__u64 reg_off) 433 { 434 /* reg_off is the offset into struct kvm_riscv_zicfiss_csr */ 435 switch (reg_off) { 436 case KVM_REG_RISCV_CSR_ZICFISS_REG(ssp): 437 return RISCV_CSR_ZICFISS(ssp); 438 } 439 440 TEST_FAIL("Unknown zicfiss csr reg: 0x%llx", reg_off); 441 return NULL; 442 } 443 444 static const char *csr_id_to_str(const char *prefix, __u64 id) 445 { 446 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); 447 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 448 449 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); 450 451 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 452 453 switch (reg_subtype) { 454 case KVM_REG_RISCV_CSR_GENERAL: 455 return general_csr_id_to_str(reg_off); 456 case KVM_REG_RISCV_CSR_AIA: 457 return aia_csr_id_to_str(reg_off); 458 case KVM_REG_RISCV_CSR_SMSTATEEN: 459 return smstateen_csr_id_to_str(reg_off); 460 case KVM_REG_RISCV_CSR_ZICFISS: 461 return zicfiss_csr_id_to_str(reg_off); 462 } 463 464 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 465 } 466 467 static const char *timer_id_to_str(const char *prefix, __u64 id) 468 { 469 /* reg_off is the offset into struct kvm_riscv_timer */ 470 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); 471 472 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER); 473 474 switch (reg_off) { 475 case KVM_REG_RISCV_TIMER_REG(frequency): 476 return "KVM_REG_RISCV_TIMER_REG(frequency)"; 477 case KVM_REG_RISCV_TIMER_REG(time): 478 return "KVM_REG_RISCV_TIMER_REG(time)"; 479 case KVM_REG_RISCV_TIMER_REG(compare): 480 return "KVM_REG_RISCV_TIMER_REG(compare)"; 481 case KVM_REG_RISCV_TIMER_REG(state): 482 return "KVM_REG_RISCV_TIMER_REG(state)"; 483 } 484 485 return strdup_printf("%lld /* UNKNOWN */", reg_off); 486 } 487 488 static const char *fp_f_id_to_str(const char *prefix, __u64 id) 489 { 490 /* reg_off is the offset into struct __riscv_f_ext_state */ 491 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); 492 493 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F); 494 495 switch (reg_off) { 496 case KVM_REG_RISCV_FP_F_REG(f[0]) ... 497 KVM_REG_RISCV_FP_F_REG(f[31]): 498 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off); 499 case KVM_REG_RISCV_FP_F_REG(fcsr): 500 return "KVM_REG_RISCV_FP_F_REG(fcsr)"; 501 } 502 503 return strdup_printf("%lld /* UNKNOWN */", reg_off); 504 } 505 506 static const char *fp_d_id_to_str(const char *prefix, __u64 id) 507 { 508 /* reg_off is the offset into struct __riscv_d_ext_state */ 509 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); 510 511 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D); 512 513 switch (reg_off) { 514 case KVM_REG_RISCV_FP_D_REG(f[0]) ... 515 KVM_REG_RISCV_FP_D_REG(f[31]): 516 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off); 517 case KVM_REG_RISCV_FP_D_REG(fcsr): 518 return "KVM_REG_RISCV_FP_D_REG(fcsr)"; 519 } 520 521 return strdup_printf("%lld /* UNKNOWN */", reg_off); 522 } 523 524 static const char *vector_id_to_str(const char *prefix, __u64 id) 525 { 526 /* reg_off is the offset into struct __riscv_v_ext_state */ 527 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR); 528 int reg_index = 0; 529 530 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_VECTOR); 531 532 if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0)) 533 reg_index = reg_off - KVM_REG_RISCV_VECTOR_REG(0); 534 switch (reg_off) { 535 case KVM_REG_RISCV_VECTOR_REG(0) ... 536 KVM_REG_RISCV_VECTOR_REG(31): 537 return strdup_printf("KVM_REG_RISCV_VECTOR_REG(%d)", reg_index); 538 case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): 539 return "KVM_REG_RISCV_VECTOR_CSR_REG(vstart)"; 540 case KVM_REG_RISCV_VECTOR_CSR_REG(vl): 541 return "KVM_REG_RISCV_VECTOR_CSR_REG(vl)"; 542 case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): 543 return "KVM_REG_RISCV_VECTOR_CSR_REG(vtype)"; 544 case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): 545 return "KVM_REG_RISCV_VECTOR_CSR_REG(vcsr)"; 546 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): 547 return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)"; 548 } 549 550 return strdup_printf("%lld /* UNKNOWN */", reg_off); 551 } 552 553 #define KVM_ISA_EXT_ARR(ext) \ 554 [KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext 555 556 static const char *isa_ext_single_id_to_str(__u64 reg_off) 557 { 558 static const char * const kvm_isa_ext_reg_name[] = { 559 KVM_ISA_EXT_ARR(A), 560 KVM_ISA_EXT_ARR(C), 561 KVM_ISA_EXT_ARR(D), 562 KVM_ISA_EXT_ARR(F), 563 KVM_ISA_EXT_ARR(H), 564 KVM_ISA_EXT_ARR(I), 565 KVM_ISA_EXT_ARR(M), 566 KVM_ISA_EXT_ARR(V), 567 KVM_ISA_EXT_ARR(SMNPM), 568 KVM_ISA_EXT_ARR(SMSTATEEN), 569 KVM_ISA_EXT_ARR(SSAIA), 570 KVM_ISA_EXT_ARR(SSCOFPMF), 571 KVM_ISA_EXT_ARR(SSNPM), 572 KVM_ISA_EXT_ARR(SSTC), 573 KVM_ISA_EXT_ARR(SVADE), 574 KVM_ISA_EXT_ARR(SVADU), 575 KVM_ISA_EXT_ARR(SVINVAL), 576 KVM_ISA_EXT_ARR(SVNAPOT), 577 KVM_ISA_EXT_ARR(SVPBMT), 578 KVM_ISA_EXT_ARR(SVVPTC), 579 KVM_ISA_EXT_ARR(ZAAMO), 580 KVM_ISA_EXT_ARR(ZABHA), 581 KVM_ISA_EXT_ARR(ZACAS), 582 KVM_ISA_EXT_ARR(ZALASR), 583 KVM_ISA_EXT_ARR(ZALRSC), 584 KVM_ISA_EXT_ARR(ZAWRS), 585 KVM_ISA_EXT_ARR(ZBA), 586 KVM_ISA_EXT_ARR(ZBB), 587 KVM_ISA_EXT_ARR(ZBC), 588 KVM_ISA_EXT_ARR(ZBKB), 589 KVM_ISA_EXT_ARR(ZBKC), 590 KVM_ISA_EXT_ARR(ZBKX), 591 KVM_ISA_EXT_ARR(ZBS), 592 KVM_ISA_EXT_ARR(ZCA), 593 KVM_ISA_EXT_ARR(ZCB), 594 KVM_ISA_EXT_ARR(ZCD), 595 KVM_ISA_EXT_ARR(ZCF), 596 KVM_ISA_EXT_ARR(ZCLSD), 597 KVM_ISA_EXT_ARR(ZCMOP), 598 KVM_ISA_EXT_ARR(ZFA), 599 KVM_ISA_EXT_ARR(ZFBFMIN), 600 KVM_ISA_EXT_ARR(ZFH), 601 KVM_ISA_EXT_ARR(ZFHMIN), 602 KVM_ISA_EXT_ARR(ZICBOM), 603 KVM_ISA_EXT_ARR(ZICBOP), 604 KVM_ISA_EXT_ARR(ZICBOZ), 605 KVM_ISA_EXT_ARR(ZICCRSE), 606 KVM_ISA_EXT_ARR(ZICFILP), 607 KVM_ISA_EXT_ARR(ZICFISS), 608 KVM_ISA_EXT_ARR(ZICNTR), 609 KVM_ISA_EXT_ARR(ZICOND), 610 KVM_ISA_EXT_ARR(ZICSR), 611 KVM_ISA_EXT_ARR(ZIFENCEI), 612 KVM_ISA_EXT_ARR(ZIHINTNTL), 613 KVM_ISA_EXT_ARR(ZIHINTPAUSE), 614 KVM_ISA_EXT_ARR(ZIHPM), 615 KVM_ISA_EXT_ARR(ZILSD), 616 KVM_ISA_EXT_ARR(ZIMOP), 617 KVM_ISA_EXT_ARR(ZKND), 618 KVM_ISA_EXT_ARR(ZKNE), 619 KVM_ISA_EXT_ARR(ZKNH), 620 KVM_ISA_EXT_ARR(ZKR), 621 KVM_ISA_EXT_ARR(ZKSED), 622 KVM_ISA_EXT_ARR(ZKSH), 623 KVM_ISA_EXT_ARR(ZKT), 624 KVM_ISA_EXT_ARR(ZTSO), 625 KVM_ISA_EXT_ARR(ZVBB), 626 KVM_ISA_EXT_ARR(ZVBC), 627 KVM_ISA_EXT_ARR(ZVFBFMIN), 628 KVM_ISA_EXT_ARR(ZVFBFWMA), 629 KVM_ISA_EXT_ARR(ZVFH), 630 KVM_ISA_EXT_ARR(ZVFHMIN), 631 KVM_ISA_EXT_ARR(ZVKB), 632 KVM_ISA_EXT_ARR(ZVKG), 633 KVM_ISA_EXT_ARR(ZVKNED), 634 KVM_ISA_EXT_ARR(ZVKNHA), 635 KVM_ISA_EXT_ARR(ZVKNHB), 636 KVM_ISA_EXT_ARR(ZVKSED), 637 KVM_ISA_EXT_ARR(ZVKSH), 638 KVM_ISA_EXT_ARR(ZVKT), 639 }; 640 641 if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) 642 return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off); 643 644 return kvm_isa_ext_reg_name[reg_off]; 645 } 646 647 static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 648 { 649 const char *unknown = ""; 650 651 if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST) 652 unknown = " /* UNKNOWN */"; 653 654 switch (reg_subtype) { 655 case KVM_REG_RISCV_ISA_MULTI_EN: 656 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown); 657 case KVM_REG_RISCV_ISA_MULTI_DIS: 658 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown); 659 } 660 661 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 662 } 663 664 static const char *isa_ext_id_to_str(const char *prefix, __u64 id) 665 { 666 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); 667 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 668 669 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT); 670 671 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 672 673 switch (reg_subtype) { 674 case KVM_REG_RISCV_ISA_SINGLE: 675 return isa_ext_single_id_to_str(reg_off); 676 case KVM_REG_RISCV_ISA_MULTI_EN: 677 case KVM_REG_RISCV_ISA_MULTI_DIS: 678 return isa_ext_multi_id_to_str(reg_subtype, reg_off); 679 } 680 681 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 682 } 683 684 #define KVM_SBI_EXT_ARR(ext) \ 685 [ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext 686 687 static const char *sbi_ext_single_id_to_str(__u64 reg_off) 688 { 689 /* reg_off is KVM_RISCV_SBI_EXT_ID */ 690 static const char * const kvm_sbi_ext_reg_name[] = { 691 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01), 692 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME), 693 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI), 694 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE), 695 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST), 696 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM), 697 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), 698 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), 699 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP), 700 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA), 701 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT), 702 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_MPXY), 703 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), 704 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), 705 }; 706 707 if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) 708 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off); 709 710 return kvm_sbi_ext_reg_name[reg_off]; 711 } 712 713 static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 714 { 715 const char *unknown = ""; 716 717 if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) 718 unknown = " /* UNKNOWN */"; 719 720 switch (reg_subtype) { 721 case KVM_REG_RISCV_SBI_MULTI_EN: 722 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown); 723 case KVM_REG_RISCV_SBI_MULTI_DIS: 724 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown); 725 } 726 727 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 728 } 729 730 static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) 731 { 732 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); 733 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 734 735 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT); 736 737 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 738 739 switch (reg_subtype) { 740 case KVM_REG_RISCV_SBI_SINGLE: 741 return sbi_ext_single_id_to_str(reg_off); 742 case KVM_REG_RISCV_SBI_MULTI_EN: 743 case KVM_REG_RISCV_SBI_MULTI_DIS: 744 return sbi_ext_multi_id_to_str(reg_subtype, reg_off); 745 } 746 747 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 748 } 749 750 static const char *sbi_sta_id_to_str(__u64 reg_off) 751 { 752 switch (reg_off) { 753 case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)"; 754 case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)"; 755 } 756 return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off); 757 } 758 759 static const char *sbi_fwft_id_to_str(__u64 reg_off) 760 { 761 switch (reg_off) { 762 case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable)"; 763 case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags)"; 764 case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value)"; 765 case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)"; 766 case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)"; 767 case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)"; 768 case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable)"; 769 case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags)"; 770 case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value)"; 771 case 9: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable)"; 772 case 10: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags)"; 773 case 11: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value)"; 774 case 12: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable)"; 775 case 13: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags)"; 776 case 14: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value)"; 777 } 778 return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off); 779 } 780 781 static const char *sbi_id_to_str(const char *prefix, __u64 id) 782 { 783 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); 784 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 785 786 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE); 787 788 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 789 790 switch (reg_subtype) { 791 case KVM_REG_RISCV_SBI_STA: 792 return sbi_sta_id_to_str(reg_off); 793 case KVM_REG_RISCV_SBI_FWFT: 794 return sbi_fwft_id_to_str(reg_off); 795 } 796 797 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 798 } 799 800 void print_reg(const char *prefix, __u64 id) 801 { 802 const char *reg_size = NULL; 803 804 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV, 805 "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id); 806 807 switch (id & KVM_REG_SIZE_MASK) { 808 case KVM_REG_SIZE_U32: 809 reg_size = "KVM_REG_SIZE_U32"; 810 break; 811 case KVM_REG_SIZE_U64: 812 reg_size = "KVM_REG_SIZE_U64"; 813 break; 814 case KVM_REG_SIZE_U128: 815 reg_size = "KVM_REG_SIZE_U128"; 816 break; 817 case KVM_REG_SIZE_U256: 818 reg_size = "KVM_REG_SIZE_U256"; 819 break; 820 default: 821 printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n", 822 (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK); 823 return; 824 } 825 826 switch (id & KVM_REG_RISCV_TYPE_MASK) { 827 case KVM_REG_RISCV_CONFIG: 828 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n", 829 reg_size, config_id_to_str(prefix, id)); 830 break; 831 case KVM_REG_RISCV_CORE: 832 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n", 833 reg_size, core_id_to_str(prefix, id)); 834 break; 835 case KVM_REG_RISCV_CSR: 836 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n", 837 reg_size, csr_id_to_str(prefix, id)); 838 break; 839 case KVM_REG_RISCV_TIMER: 840 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n", 841 reg_size, timer_id_to_str(prefix, id)); 842 break; 843 case KVM_REG_RISCV_FP_F: 844 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n", 845 reg_size, fp_f_id_to_str(prefix, id)); 846 break; 847 case KVM_REG_RISCV_FP_D: 848 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n", 849 reg_size, fp_d_id_to_str(prefix, id)); 850 break; 851 case KVM_REG_RISCV_VECTOR: 852 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_VECTOR | %s,\n", 853 reg_size, vector_id_to_str(prefix, id)); 854 break; 855 case KVM_REG_RISCV_ISA_EXT: 856 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n", 857 reg_size, isa_ext_id_to_str(prefix, id)); 858 break; 859 case KVM_REG_RISCV_SBI_EXT: 860 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n", 861 reg_size, sbi_ext_id_to_str(prefix, id)); 862 break; 863 case KVM_REG_RISCV_SBI_STATE: 864 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n", 865 reg_size, sbi_id_to_str(prefix, id)); 866 break; 867 default: 868 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n", 869 reg_size, id & ~REG_MASK); 870 return; 871 } 872 } 873 874 /* 875 * The current blessed list was primed with the output of kernel version 876 * v6.5-rc3 and then later updated with new registers. 877 */ 878 static __u64 base_regs[] = { 879 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa), 880 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 881 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid), 882 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid), 883 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid), 884 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 885 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode), 886 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 887 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc), 888 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra), 889 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp), 890 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp), 891 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp), 892 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0), 893 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1), 894 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2), 895 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0), 896 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1), 897 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0), 898 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1), 899 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2), 900 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3), 901 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4), 902 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5), 903 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6), 904 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7), 905 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2), 906 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3), 907 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4), 908 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5), 909 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6), 910 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7), 911 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8), 912 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9), 913 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10), 914 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11), 915 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3), 916 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4), 917 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5), 918 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6), 919 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode), 920 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus), 921 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie), 922 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec), 923 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch), 924 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc), 925 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause), 926 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval), 927 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), 928 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), 929 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), 930 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), 931 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), 932 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), 933 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), 934 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 935 }; 936 937 /* 938 * The skips_set list registers that should skip set test. 939 * - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly. 940 */ 941 static __u64 base_skips_set[] = { 942 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 943 }; 944 945 static __u64 sbi_base_regs[] = { 946 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01, 947 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME, 948 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI, 949 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE, 950 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST, 951 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM, 952 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, 953 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, 954 }; 955 956 static __u64 sbi_sta_regs[] = { 957 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA, 958 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo), 959 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), 960 }; 961 962 static __u64 sbi_fwft_misaligned_deleg_regs[] = { 963 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 964 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable), 965 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), 966 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), 967 }; 968 969 static __u64 sbi_fwft_pointer_masking_regs[] = { 970 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 971 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), 972 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), 973 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), 974 }; 975 976 static __u64 sbi_fwft_pte_ad_hw_updating_regs[] = { 977 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 978 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable), 979 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags), 980 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value), 981 }; 982 983 static __u64 sbi_fwft_landing_pad_regs[] = { 984 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 985 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable), 986 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags), 987 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value), 988 }; 989 990 static __u64 sbi_fwft_shadow_stack_regs[] = { 991 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 992 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable), 993 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags), 994 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value), 995 }; 996 997 static __u64 zicbom_regs[] = { 998 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 999 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, 1000 }; 1001 1002 static __u64 zicbop_regs[] = { 1003 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 1004 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP, 1005 }; 1006 1007 static __u64 zicboz_regs[] = { 1008 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 1009 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ, 1010 }; 1011 1012 static __u64 zicfiss_regs[] = { 1013 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_ZICFISS | KVM_REG_RISCV_CSR_ZICFISS_REG(ssp), 1014 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS, 1015 }; 1016 1017 static __u64 aia_regs[] = { 1018 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), 1019 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), 1020 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2), 1021 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh), 1022 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph), 1023 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h), 1024 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h), 1025 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA, 1026 }; 1027 1028 static __u64 smstateen_regs[] = { 1029 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), 1030 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN, 1031 }; 1032 1033 static __u64 fp_f_regs[] = { 1034 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), 1035 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), 1036 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]), 1037 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]), 1038 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]), 1039 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]), 1040 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]), 1041 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]), 1042 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]), 1043 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]), 1044 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]), 1045 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]), 1046 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]), 1047 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]), 1048 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]), 1049 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]), 1050 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]), 1051 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]), 1052 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]), 1053 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]), 1054 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]), 1055 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]), 1056 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]), 1057 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]), 1058 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]), 1059 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]), 1060 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]), 1061 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]), 1062 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]), 1063 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]), 1064 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]), 1065 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]), 1066 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr), 1067 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F, 1068 }; 1069 1070 static __u64 fp_d_regs[] = { 1071 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]), 1072 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]), 1073 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]), 1074 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]), 1075 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]), 1076 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]), 1077 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]), 1078 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]), 1079 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]), 1080 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]), 1081 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]), 1082 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]), 1083 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]), 1084 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]), 1085 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]), 1086 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]), 1087 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]), 1088 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]), 1089 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]), 1090 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]), 1091 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]), 1092 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]), 1093 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]), 1094 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]), 1095 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]), 1096 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]), 1097 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]), 1098 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]), 1099 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]), 1100 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]), 1101 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]), 1102 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]), 1103 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr), 1104 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D, 1105 }; 1106 1107 /* Define a default vector registers with length. This will be overwritten at runtime */ 1108 static __u64 v_regs[] = { 1109 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vstart), 1110 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vl), 1111 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vtype), 1112 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vcsr), 1113 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb), 1114 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(0), 1115 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(1), 1116 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(2), 1117 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(3), 1118 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(4), 1119 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(5), 1120 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(6), 1121 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(7), 1122 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(8), 1123 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(9), 1124 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(10), 1125 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(11), 1126 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(12), 1127 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(13), 1128 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(14), 1129 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(15), 1130 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(16), 1131 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(17), 1132 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(18), 1133 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(19), 1134 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(20), 1135 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(21), 1136 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(22), 1137 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(23), 1138 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(24), 1139 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(25), 1140 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(26), 1141 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(27), 1142 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(28), 1143 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(29), 1144 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(30), 1145 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(31), 1146 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V, 1147 }; 1148 1149 #define SUBLIST_BASE \ 1150 {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \ 1151 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),} 1152 1153 #define SUBLIST_ISA(ext, extu) \ 1154 { \ 1155 .name = #ext, \ 1156 .feature = KVM_RISCV_ISA_EXT_##extu, \ 1157 .regs = ext##_regs, \ 1158 .regs_n = ARRAY_SIZE(ext##_regs), \ 1159 } 1160 1161 #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \ 1162 static __u64 ext##_regs[] = { \ 1163 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1164 KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \ 1165 KVM_RISCV_ISA_EXT_##extu, \ 1166 }; \ 1167 static struct vcpu_reg_list config_##ext = { \ 1168 .sublists = { \ 1169 SUBLIST_BASE, \ 1170 SUBLIST_ISA(ext, extu), \ 1171 {0}, \ 1172 }, \ 1173 } \ 1174 1175 #define SUBLIST_SBI(ext, extu) \ 1176 { \ 1177 .name = "sbi-"#ext, \ 1178 .feature_type = VCPU_FEATURE_SBI_EXT, \ 1179 .feature = KVM_RISCV_SBI_EXT_##extu, \ 1180 .regs = sbi_##ext##_regs, \ 1181 .regs_n = ARRAY_SIZE(sbi_##ext##_regs), \ 1182 } 1183 1184 #define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \ 1185 static __u64 sbi_##ext##_regs[] = { \ 1186 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1187 KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \ 1188 KVM_RISCV_SBI_EXT_##extu, \ 1189 }; \ 1190 static struct vcpu_reg_list config_sbi_##ext = { \ 1191 .sublists = { \ 1192 SUBLIST_BASE, \ 1193 SUBLIST_SBI(ext, extu), \ 1194 {0}, \ 1195 }, \ 1196 } \ 1197 1198 #define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \ 1199 static struct vcpu_reg_list config_##ext = { \ 1200 .sublists = { \ 1201 SUBLIST_BASE, \ 1202 SUBLIST_ISA(ext, extu), \ 1203 {0}, \ 1204 }, \ 1205 } \ 1206 1207 #define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu) \ 1208 static struct vcpu_reg_list config_sbi_##ext = { \ 1209 .sublists = { \ 1210 SUBLIST_BASE, \ 1211 SUBLIST_SBI(ext, extu), \ 1212 {0}, \ 1213 }, \ 1214 } \ 1215 1216 /* Note: The below list is alphabetically sorted. */ 1217 1218 KVM_SBI_EXT_SUBLIST_CONFIG(base, V01); 1219 KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA); 1220 KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); 1221 KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); 1222 KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); 1223 KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY); 1224 1225 KVM_ISA_EXT_SUBLIST_CONFIG(aia, SSAIA); 1226 KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, F); 1227 KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, D); 1228 KVM_ISA_EXT_SUBLIST_CONFIG(v, V); 1229 KVM_ISA_EXT_SIMPLE_CONFIG(h, H); 1230 KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM); 1231 KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); 1232 KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); 1233 KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM); 1234 KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); 1235 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); 1236 KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); 1237 KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); 1238 KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); 1239 KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); 1240 KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC); 1241 KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO); 1242 KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA); 1243 KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS); 1244 KVM_ISA_EXT_SIMPLE_CONFIG(zalasr, ZALASR); 1245 KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC); 1246 KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS); 1247 KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA); 1248 KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB); 1249 KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC); 1250 KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); 1251 KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); 1252 KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); 1253 KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); 1254 KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA); 1255 KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB); 1256 KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD); 1257 KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF); 1258 KVM_ISA_EXT_SIMPLE_CONFIG(zclsd, ZCLSD); 1259 KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); 1260 KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); 1261 KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN); 1262 KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); 1263 KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); 1264 KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM); 1265 KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP); 1266 KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ); 1267 KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE); 1268 KVM_ISA_EXT_SIMPLE_CONFIG(zicfilp, ZICFILP); 1269 KVM_ISA_EXT_SUBLIST_CONFIG(zicfiss, ZICFISS); 1270 KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR); 1271 KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND); 1272 KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR); 1273 KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI); 1274 KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL); 1275 KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE); 1276 KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM); 1277 KVM_ISA_EXT_SIMPLE_CONFIG(zilsd, ZILSD); 1278 KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP); 1279 KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND); 1280 KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE); 1281 KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH); 1282 KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR); 1283 KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED); 1284 KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH); 1285 KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT); 1286 KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO); 1287 KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB); 1288 KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC); 1289 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN); 1290 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA); 1291 KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH); 1292 KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN); 1293 KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB); 1294 KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG); 1295 KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED); 1296 KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA); 1297 KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB); 1298 KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED); 1299 KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH); 1300 KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT); 1301 1302 static struct vcpu_reg_list config_sbi_fwft_misaligned_deleg = { 1303 .sublists = { 1304 SUBLIST_BASE, 1305 SUBLIST_SBI(fwft_misaligned_deleg, FWFT), 1306 {0}, 1307 }, 1308 }; 1309 1310 static struct vcpu_reg_list config_sbi_fwft_pointer_masking = { 1311 .sublists = { 1312 SUBLIST_BASE, 1313 SUBLIST_ISA(smnpm, SMNPM), 1314 SUBLIST_SBI(fwft_pointer_masking, FWFT), 1315 {0}, 1316 }, 1317 }; 1318 1319 static struct vcpu_reg_list config_sbi_fwft_pte_ad_hw_updating = { 1320 .sublists = { 1321 SUBLIST_BASE, 1322 SUBLIST_ISA(svade, SVADE), 1323 SUBLIST_ISA(svadu, SVADU), 1324 SUBLIST_SBI(fwft_pte_ad_hw_updating, FWFT), 1325 {0}, 1326 }, 1327 }; 1328 1329 static struct vcpu_reg_list config_sbi_fwft_landing_pad = { 1330 .sublists = { 1331 SUBLIST_BASE, 1332 SUBLIST_ISA(zicfilp, ZICFILP), 1333 SUBLIST_SBI(fwft_landing_pad, FWFT), 1334 {0}, 1335 }, 1336 }; 1337 1338 static struct vcpu_reg_list config_sbi_fwft_shadow_stack = { 1339 .sublists = { 1340 SUBLIST_BASE, 1341 SUBLIST_ISA(zicfiss, ZICFISS), 1342 SUBLIST_SBI(fwft_shadow_stack, FWFT), 1343 {0}, 1344 }, 1345 }; 1346 1347 struct vcpu_reg_list *vcpu_configs[] = { 1348 &config_sbi_base, 1349 &config_sbi_sta, 1350 &config_sbi_pmu, 1351 &config_sbi_dbcn, 1352 &config_sbi_susp, 1353 &config_sbi_mpxy, 1354 &config_sbi_fwft_misaligned_deleg, 1355 &config_sbi_fwft_pointer_masking, 1356 &config_sbi_fwft_pte_ad_hw_updating, 1357 &config_sbi_fwft_landing_pad, 1358 &config_sbi_fwft_shadow_stack, 1359 &config_aia, 1360 &config_fp_f, 1361 &config_fp_d, 1362 &config_h, 1363 &config_v, 1364 &config_smnpm, 1365 &config_smstateen, 1366 &config_sscofpmf, 1367 &config_ssnpm, 1368 &config_sstc, 1369 &config_svade, 1370 &config_svadu, 1371 &config_svinval, 1372 &config_svnapot, 1373 &config_svpbmt, 1374 &config_svvptc, 1375 &config_zaamo, 1376 &config_zabha, 1377 &config_zacas, 1378 &config_zalrsc, 1379 &config_zalasr, 1380 &config_zawrs, 1381 &config_zba, 1382 &config_zbb, 1383 &config_zbc, 1384 &config_zbkb, 1385 &config_zbkc, 1386 &config_zbkx, 1387 &config_zbs, 1388 &config_zca, 1389 &config_zcb, 1390 &config_zcd, 1391 &config_zcf, 1392 &config_zclsd, 1393 &config_zcmop, 1394 &config_zfa, 1395 &config_zfbfmin, 1396 &config_zfh, 1397 &config_zfhmin, 1398 &config_zicbom, 1399 &config_zicbop, 1400 &config_zicboz, 1401 &config_ziccrse, 1402 &config_zicfilp, 1403 &config_zicfiss, 1404 &config_zicntr, 1405 &config_zicond, 1406 &config_zicsr, 1407 &config_zifencei, 1408 &config_zihintntl, 1409 &config_zihintpause, 1410 &config_zihpm, 1411 &config_zilsd, 1412 &config_zimop, 1413 &config_zknd, 1414 &config_zkne, 1415 &config_zknh, 1416 &config_zkr, 1417 &config_zksed, 1418 &config_zksh, 1419 &config_zkt, 1420 &config_ztso, 1421 &config_zvbb, 1422 &config_zvbc, 1423 &config_zvfbfmin, 1424 &config_zvfbfwma, 1425 &config_zvfh, 1426 &config_zvfhmin, 1427 &config_zvkb, 1428 &config_zvkg, 1429 &config_zvkned, 1430 &config_zvknha, 1431 &config_zvknhb, 1432 &config_zvksed, 1433 &config_zvksh, 1434 &config_zvkt, 1435 }; 1436 int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); 1437