1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare MIPI CSI-2 Receiver Driver 4 * 5 * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 6 * Copyright (C) 2025 Michael Riesch <michael.riesch@wolfvision.net> 7 * Copyright (C) 2026 Collabora, Ltd. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/reset.h> 22 23 #include <media/mipi-csi2.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-fwnode.h> 26 #include <media/v4l2-mc.h> 27 #include <media/v4l2-subdev.h> 28 29 #define SW_CPHY_EN(x) ((x) << 0) 30 #define SW_DSI_EN(x) ((x) << 4) 31 #define SW_DATATYPE_FS(x) ((x) << 8) 32 #define SW_DATATYPE_FE(x) ((x) << 14) 33 #define SW_DATATYPE_LS(x) ((x) << 20) 34 #define SW_DATATYPE_LE(x) ((x) << 26) 35 36 #define DW_REG_EXIST BIT(31) 37 #define DW_REG(x) (DW_REG_EXIST | (x)) 38 39 #define DPHY_STOPSTATE_CLK_LANE BIT(16) 40 41 #define DPHY_TEST_CTRL0_TEST_CLR BIT(0) 42 43 #define IPI_VCID_VC(x) FIELD_PREP(GENMASK(1, 0), (x)) 44 #define IPI_VCID_VC_0_1(x) FIELD_PREP(GENMASK(3, 2), (x)) 45 #define IPI_VCID_VC_2 BIT(4) 46 47 #define IPI_DATA_TYPE_DT(x) FIELD_PREP(GENMASK(5, 0), (x)) 48 #define IPI_DATA_TYPE_EMB_DATA_EN BIT(8) 49 50 #define IPI_MODE_CONTROLLER BIT(1) 51 #define IPI_MODE_COLOR_MODE16 BIT(8) 52 #define IPI_MODE_CUT_THROUGH BIT(16) 53 #define IPI_MODE_ENABLE BIT(24) 54 55 #define IPI_MEM_FLUSH_AUTO BIT(8) 56 57 enum dw_mipi_csi2rx_regs_index { 58 DW_MIPI_CSI2RX_N_LANES, 59 DW_MIPI_CSI2RX_RESETN, 60 DW_MIPI_CSI2RX_PHY_STATE, 61 DW_MIPI_CSI2RX_ERR1, 62 DW_MIPI_CSI2RX_ERR2, 63 DW_MIPI_CSI2RX_MSK1, 64 DW_MIPI_CSI2RX_MSK2, 65 DW_MIPI_CSI2RX_CONTROL, 66 /* imx93 (v150) new register */ 67 DW_MIPI_CSI2RX_DPHY_RSTZ, 68 DW_MIPI_CSI2RX_PHY_TST_CTRL0, 69 DW_MIPI_CSI2RX_PHY_TST_CTRL1, 70 DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 71 DW_MIPI_CSI2RX_PHY_STOPSTATE, 72 DW_MIPI_CSI2RX_IPI_DATATYPE, 73 DW_MIPI_CSI2RX_IPI_MEM_FLUSH, 74 DW_MIPI_CSI2RX_IPI_MODE, 75 DW_MIPI_CSI2RX_IPI_SOFTRSTN, 76 DW_MIPI_CSI2RX_IPI_VCID, 77 78 DW_MIPI_CSI2RX_MAX, 79 }; 80 81 enum { 82 DW_MIPI_CSI2RX_PAD_SINK, 83 DW_MIPI_CSI2RX_PAD_SRC, 84 DW_MIPI_CSI2RX_PAD_MAX, 85 }; 86 87 struct dw_mipi_csi2rx_device; 88 89 struct dw_mipi_csi2rx_drvdata { 90 const u32 *regs; 91 void (*dphy_assert_reset)(struct dw_mipi_csi2rx_device *csi2); 92 void (*dphy_deassert_reset)(struct dw_mipi_csi2rx_device *csi2); 93 void (*ipi_enable)(struct dw_mipi_csi2rx_device *csi2); 94 int (*wait_for_phy_stopstate)(struct dw_mipi_csi2rx_device *csi2); 95 }; 96 97 struct dw_mipi_csi2rx_format { 98 u32 code; 99 u8 depth; 100 u8 csi_dt; 101 }; 102 103 struct dw_mipi_csi2rx_device { 104 struct device *dev; 105 106 void __iomem *base_addr; 107 struct clk_bulk_data *clks; 108 unsigned int clks_num; 109 struct phy *phy; 110 struct reset_control *reset; 111 112 const struct dw_mipi_csi2rx_format *formats; 113 unsigned int formats_num; 114 115 struct media_pad pads[DW_MIPI_CSI2RX_PAD_MAX]; 116 struct v4l2_async_notifier notifier; 117 struct v4l2_subdev sd; 118 119 enum v4l2_mbus_type bus_type; 120 u32 lanes_num; 121 u64 enabled_streams; 122 123 const struct dw_mipi_csi2rx_drvdata *drvdata; 124 }; 125 126 static const u32 rk3568_regs[DW_MIPI_CSI2RX_MAX] = { 127 [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4), 128 [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x10), 129 [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x14), 130 [DW_MIPI_CSI2RX_ERR1] = DW_REG(0x20), 131 [DW_MIPI_CSI2RX_ERR2] = DW_REG(0x24), 132 [DW_MIPI_CSI2RX_MSK1] = DW_REG(0x28), 133 [DW_MIPI_CSI2RX_MSK2] = DW_REG(0x2c), 134 [DW_MIPI_CSI2RX_CONTROL] = DW_REG(0x40), 135 }; 136 137 static const struct dw_mipi_csi2rx_drvdata rk3568_drvdata = { 138 .regs = rk3568_regs, 139 }; 140 141 static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = { 142 [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4), 143 [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8), 144 [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40), 145 [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44), 146 [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48), 147 [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c), 148 [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50), 149 [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54), 150 [DW_MIPI_CSI2RX_IPI_MODE] = DW_REG(0x80), 151 [DW_MIPI_CSI2RX_IPI_VCID] = DW_REG(0x84), 152 [DW_MIPI_CSI2RX_IPI_DATATYPE] = DW_REG(0x88), 153 [DW_MIPI_CSI2RX_IPI_MEM_FLUSH] = DW_REG(0x8c), 154 [DW_MIPI_CSI2RX_IPI_SOFTRSTN] = DW_REG(0xa0), 155 }; 156 157 static const u32 imx95_regs[DW_MIPI_CSI2RX_MAX] = { 158 [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4), 159 [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8), 160 [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40), 161 [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44), 162 [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48), 163 [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c), 164 [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50), 165 [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54), 166 }; 167 168 static const struct v4l2_mbus_framefmt default_format = { 169 .width = 3840, 170 .height = 2160, 171 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 172 .field = V4L2_FIELD_NONE, 173 .colorspace = V4L2_COLORSPACE_RAW, 174 .ycbcr_enc = V4L2_YCBCR_ENC_601, 175 .quantization = V4L2_QUANTIZATION_FULL_RANGE, 176 .xfer_func = V4L2_XFER_FUNC_NONE, 177 }; 178 179 static const struct dw_mipi_csi2rx_format formats[] = { 180 /* YUV formats */ 181 { 182 .code = MEDIA_BUS_FMT_YUYV8_1X16, 183 .depth = 16, 184 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 185 }, 186 { 187 .code = MEDIA_BUS_FMT_UYVY8_1X16, 188 .depth = 16, 189 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 190 }, 191 { 192 .code = MEDIA_BUS_FMT_YVYU8_1X16, 193 .depth = 16, 194 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 195 }, 196 { 197 .code = MEDIA_BUS_FMT_VYUY8_1X16, 198 .depth = 16, 199 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 200 }, 201 /* RGB formats */ 202 { 203 .code = MEDIA_BUS_FMT_RGB888_1X24, 204 .depth = 24, 205 .csi_dt = MIPI_CSI2_DT_RGB888, 206 }, 207 { 208 .code = MEDIA_BUS_FMT_BGR888_1X24, 209 .depth = 24, 210 .csi_dt = MIPI_CSI2_DT_RGB888, 211 }, 212 /* Bayer formats */ 213 { 214 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 215 .depth = 8, 216 .csi_dt = MIPI_CSI2_DT_RAW8, 217 }, 218 { 219 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 220 .depth = 8, 221 .csi_dt = MIPI_CSI2_DT_RAW8, 222 }, 223 { 224 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 225 .depth = 8, 226 .csi_dt = MIPI_CSI2_DT_RAW8, 227 }, 228 { 229 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 230 .depth = 8, 231 .csi_dt = MIPI_CSI2_DT_RAW8, 232 }, 233 { 234 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 235 .depth = 10, 236 .csi_dt = MIPI_CSI2_DT_RAW10, 237 }, 238 { 239 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 240 .depth = 10, 241 .csi_dt = MIPI_CSI2_DT_RAW10, 242 }, 243 { 244 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 245 .depth = 10, 246 .csi_dt = MIPI_CSI2_DT_RAW10, 247 }, 248 { 249 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 250 .depth = 10, 251 .csi_dt = MIPI_CSI2_DT_RAW10, 252 }, 253 { 254 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 255 .depth = 12, 256 .csi_dt = MIPI_CSI2_DT_RAW12, 257 }, 258 { 259 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 260 .depth = 12, 261 .csi_dt = MIPI_CSI2_DT_RAW12, 262 }, 263 { 264 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 265 .depth = 12, 266 .csi_dt = MIPI_CSI2_DT_RAW12, 267 }, 268 { 269 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 270 .depth = 12, 271 .csi_dt = MIPI_CSI2_DT_RAW12, 272 }, 273 { 274 .code = MEDIA_BUS_FMT_SBGGR16_1X16, 275 .depth = 16, 276 .csi_dt = MIPI_CSI2_DT_RAW16, 277 }, 278 { 279 .code = MEDIA_BUS_FMT_SGBRG16_1X16, 280 .depth = 16, 281 .csi_dt = MIPI_CSI2_DT_RAW16, 282 }, 283 { 284 .code = MEDIA_BUS_FMT_SGRBG16_1X16, 285 .depth = 16, 286 .csi_dt = MIPI_CSI2_DT_RAW16, 287 }, 288 { 289 .code = MEDIA_BUS_FMT_SRGGB16_1X16, 290 .depth = 16, 291 .csi_dt = MIPI_CSI2_DT_RAW16, 292 }, 293 }; 294 295 static inline struct dw_mipi_csi2rx_device *to_csi2(struct v4l2_subdev *sd) 296 { 297 return container_of(sd, struct dw_mipi_csi2rx_device, sd); 298 } 299 300 static bool dw_mipi_csi2rx_has_reg(struct dw_mipi_csi2rx_device *csi2, 301 enum dw_mipi_csi2rx_regs_index index) 302 { 303 if (index < DW_MIPI_CSI2RX_MAX && 304 (csi2->drvdata->regs[index] & DW_REG_EXIST)) 305 return true; 306 307 return false; 308 } 309 310 static void __iomem * 311 dw_mipi_csi2rx_get_regaddr(struct dw_mipi_csi2rx_device *csi2, 312 enum dw_mipi_csi2rx_regs_index index) 313 { 314 u32 off = (~DW_REG_EXIST) & csi2->drvdata->regs[index]; 315 316 return csi2->base_addr + off; 317 } 318 319 static inline void dw_mipi_csi2rx_write(struct dw_mipi_csi2rx_device *csi2, 320 enum dw_mipi_csi2rx_regs_index index, 321 u32 val) 322 { 323 if (!dw_mipi_csi2rx_has_reg(csi2, index)) { 324 dev_err_once(csi2->dev, 325 "write to non-existent register index: %d\n", 326 index); 327 return; 328 } 329 330 writel(val, dw_mipi_csi2rx_get_regaddr(csi2, index)); 331 } 332 333 static inline u32 dw_mipi_csi2rx_read(struct dw_mipi_csi2rx_device *csi2, 334 enum dw_mipi_csi2rx_regs_index index) 335 { 336 if (!dw_mipi_csi2rx_has_reg(csi2, index)) { 337 dev_err_once(csi2->dev, 338 "read non-existent register index: %d\n", index); 339 /* return 0 for non-existent registers */ 340 return 0; 341 } 342 343 return readl(dw_mipi_csi2rx_get_regaddr(csi2, index)); 344 } 345 346 static const struct dw_mipi_csi2rx_format * 347 dw_mipi_csi2rx_find_format(struct dw_mipi_csi2rx_device *csi2, u32 mbus_code) 348 { 349 WARN_ON(csi2->formats_num == 0); 350 351 for (unsigned int i = 0; i < csi2->formats_num; i++) { 352 const struct dw_mipi_csi2rx_format *format = &formats[i]; 353 354 if (format->code == mbus_code) 355 return format; 356 } 357 358 return NULL; 359 } 360 361 static int dw_mipi_csi2rx_start(struct dw_mipi_csi2rx_device *csi2) 362 { 363 struct media_pad *source_pad; 364 union phy_configure_opts opts; 365 u32 lanes = csi2->lanes_num; 366 u32 control = 0; 367 s64 link_freq; 368 int ret; 369 370 if (lanes < 1 || lanes > 4) 371 return -EINVAL; 372 373 source_pad = media_pad_remote_pad_unique( 374 &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]); 375 if (IS_ERR(source_pad)) 376 return PTR_ERR(source_pad); 377 378 /* set mult and div to 0, thus completely rely on V4L2_CID_LINK_FREQ */ 379 link_freq = v4l2_get_link_freq(source_pad, 0, 0); 380 if (link_freq < 0) 381 return link_freq; 382 383 switch (csi2->bus_type) { 384 case V4L2_MBUS_CSI2_DPHY: 385 ret = phy_mipi_dphy_get_default_config_for_hsclk(link_freq * 2, 386 lanes, &opts.mipi_dphy); 387 if (ret) 388 return ret; 389 390 ret = phy_set_mode(csi2->phy, PHY_MODE_MIPI_DPHY); 391 if (ret) 392 return ret; 393 394 ret = phy_configure(csi2->phy, &opts); 395 if (ret) 396 return ret; 397 398 control |= SW_CPHY_EN(0); 399 break; 400 401 case V4L2_MBUS_CSI2_CPHY: 402 /* TODO: implement CPHY configuration */ 403 return -EOPNOTSUPP; 404 default: 405 return -EINVAL; 406 } 407 408 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); 409 410 if (csi2->drvdata->dphy_assert_reset) 411 csi2->drvdata->dphy_assert_reset(csi2); 412 413 control |= SW_DATATYPE_FS(0x00) | SW_DATATYPE_FE(0x01) | 414 SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03); 415 416 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_N_LANES, lanes - 1); 417 418 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_CONTROL)) 419 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_CONTROL, control); 420 421 ret = phy_power_on(csi2->phy); 422 if (ret) 423 return ret; 424 425 if (csi2->drvdata->dphy_deassert_reset) 426 csi2->drvdata->dphy_deassert_reset(csi2); 427 428 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 1); 429 430 if (csi2->drvdata->ipi_enable) 431 csi2->drvdata->ipi_enable(csi2); 432 433 return 0; 434 } 435 436 static void dw_mipi_csi2rx_stop(struct dw_mipi_csi2rx_device *csi2) 437 { 438 phy_power_off(csi2->phy); 439 440 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); 441 442 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK1)) 443 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK1, ~0); 444 445 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK2)) 446 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK2, ~0); 447 } 448 449 static const struct media_entity_operations dw_mipi_csi2rx_media_ops = { 450 .link_validate = v4l2_subdev_link_validate, 451 }; 452 453 static int 454 dw_mipi_csi2rx_enum_mbus_code(struct v4l2_subdev *sd, 455 struct v4l2_subdev_state *sd_state, 456 struct v4l2_subdev_mbus_code_enum *code) 457 { 458 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 459 460 switch (code->pad) { 461 case DW_MIPI_CSI2RX_PAD_SRC: 462 if (code->index) 463 return -EINVAL; 464 465 code->code = 466 v4l2_subdev_state_get_format(sd_state, 467 DW_MIPI_CSI2RX_PAD_SINK)->code; 468 469 return 0; 470 case DW_MIPI_CSI2RX_PAD_SINK: 471 if (code->index >= csi2->formats_num) 472 return -EINVAL; 473 474 code->code = formats[code->index].code; 475 return 0; 476 default: 477 return -EINVAL; 478 } 479 } 480 481 static int dw_mipi_csi2rx_set_fmt(struct v4l2_subdev *sd, 482 struct v4l2_subdev_state *state, 483 struct v4l2_subdev_format *format) 484 { 485 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 486 const struct dw_mipi_csi2rx_format *fmt; 487 struct v4l2_mbus_framefmt *sink, *src; 488 489 /* the format on the source pad always matches the sink pad */ 490 if (format->pad == DW_MIPI_CSI2RX_PAD_SRC) 491 return v4l2_subdev_get_fmt(sd, state, format); 492 493 sink = v4l2_subdev_state_get_format(state, format->pad, format->stream); 494 if (!sink) 495 return -EINVAL; 496 497 fmt = dw_mipi_csi2rx_find_format(csi2, format->format.code); 498 if (!fmt) 499 format->format = default_format; 500 501 *sink = format->format; 502 503 /* propagate the format to the source pad */ 504 src = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 505 format->stream); 506 if (!src) 507 return -EINVAL; 508 509 *src = *sink; 510 511 /* Store the CSIS format descriptor for active formats. */ 512 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 513 csi2->formats = fmt ? : 514 dw_mipi_csi2rx_find_format(csi2, default_format.code); 515 516 if (!csi2->formats) { 517 dev_err(csi2->dev, "Failed to find valid format\n"); 518 return -EINVAL; 519 } 520 } 521 522 return 0; 523 } 524 525 static int dw_mipi_csi2rx_set_routing(struct v4l2_subdev *sd, 526 struct v4l2_subdev_state *state, 527 enum v4l2_subdev_format_whence which, 528 struct v4l2_subdev_krouting *routing) 529 { 530 int ret; 531 532 ret = v4l2_subdev_routing_validate(sd, routing, 533 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 534 if (ret) 535 return ret; 536 537 return v4l2_subdev_set_routing_with_fmt(sd, state, routing, 538 &default_format); 539 } 540 541 static int dw_mipi_csi2rx_enable_streams(struct v4l2_subdev *sd, 542 struct v4l2_subdev_state *state, 543 u32 pad, u64 streams_mask) 544 { 545 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 546 struct v4l2_subdev *remote_sd; 547 struct media_pad *sink_pad, *remote_pad; 548 struct device *dev = csi2->dev; 549 u64 mask; 550 int ret; 551 552 sink_pad = &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; 553 remote_pad = media_pad_remote_pad_first(sink_pad); 554 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 555 556 mask = v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, 557 DW_MIPI_CSI2RX_PAD_SRC, 558 &streams_mask); 559 560 if (!csi2->enabled_streams) { 561 ret = pm_runtime_resume_and_get(dev); 562 if (ret) 563 goto err; 564 565 ret = dw_mipi_csi2rx_start(csi2); 566 if (ret) { 567 dev_err(dev, "failed to enable CSI hardware\n"); 568 goto err_pm_runtime_put; 569 } 570 } 571 572 ret = v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); 573 if (ret) 574 goto err_csi_stop; 575 576 if (!csi2->enabled_streams && 577 csi2->drvdata->wait_for_phy_stopstate) { 578 ret = csi2->drvdata->wait_for_phy_stopstate(csi2); 579 if (ret) 580 goto err_disable_streams; 581 } 582 583 csi2->enabled_streams |= streams_mask; 584 585 return 0; 586 587 err_disable_streams: 588 v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); 589 err_csi_stop: 590 /* Stop CSI hardware if no streams are enabled */ 591 if (!csi2->enabled_streams) 592 dw_mipi_csi2rx_stop(csi2); 593 err_pm_runtime_put: 594 if (!csi2->enabled_streams) 595 pm_runtime_put(dev); 596 err: 597 return ret; 598 } 599 600 static int dw_mipi_csi2rx_disable_streams(struct v4l2_subdev *sd, 601 struct v4l2_subdev_state *state, 602 u32 pad, u64 streams_mask) 603 { 604 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 605 struct v4l2_subdev *remote_sd; 606 struct media_pad *sink_pad, *remote_pad; 607 struct device *dev = csi2->dev; 608 u64 mask; 609 int ret; 610 611 sink_pad = &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; 612 remote_pad = media_pad_remote_pad_first(sink_pad); 613 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 614 615 mask = v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, 616 DW_MIPI_CSI2RX_PAD_SRC, 617 &streams_mask); 618 619 ret = v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); 620 if (ret) 621 dev_err(dev, "failed to disable streams on remote subdev: %d\n", ret); 622 623 csi2->enabled_streams &= ~streams_mask; 624 625 if (!csi2->enabled_streams) { 626 dw_mipi_csi2rx_stop(csi2); 627 pm_runtime_put(dev); 628 } 629 630 return ret; 631 } 632 633 static int 634 dw_mipi_csi2rx_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 635 struct v4l2_mbus_frame_desc *fd) 636 { 637 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 638 struct v4l2_subdev *remote_sd; 639 struct media_pad *remote_pad; 640 641 remote_pad = media_pad_remote_pad_unique(&csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]); 642 if (IS_ERR(remote_pad)) { 643 dev_err(csi2->dev, "can't get remote source pad\n"); 644 return PTR_ERR(remote_pad); 645 } 646 647 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 648 649 return v4l2_subdev_call(remote_sd, pad, get_frame_desc, 650 remote_pad->index, fd); 651 } 652 653 static const struct v4l2_subdev_pad_ops dw_mipi_csi2rx_pad_ops = { 654 .enum_mbus_code = dw_mipi_csi2rx_enum_mbus_code, 655 .get_fmt = v4l2_subdev_get_fmt, 656 .set_fmt = dw_mipi_csi2rx_set_fmt, 657 .get_frame_desc = dw_mipi_csi2rx_get_frame_desc, 658 .set_routing = dw_mipi_csi2rx_set_routing, 659 .enable_streams = dw_mipi_csi2rx_enable_streams, 660 .disable_streams = dw_mipi_csi2rx_disable_streams, 661 }; 662 663 static const struct v4l2_subdev_ops dw_mipi_csi2rx_ops = { 664 .pad = &dw_mipi_csi2rx_pad_ops, 665 }; 666 667 static int dw_mipi_csi2rx_init_state(struct v4l2_subdev *sd, 668 struct v4l2_subdev_state *state) 669 { 670 struct v4l2_subdev_route routes[] = { 671 { 672 .sink_pad = DW_MIPI_CSI2RX_PAD_SINK, 673 .sink_stream = 0, 674 .source_pad = DW_MIPI_CSI2RX_PAD_SRC, 675 .source_stream = 0, 676 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 677 }, 678 }; 679 struct v4l2_subdev_krouting routing = { 680 .len_routes = ARRAY_SIZE(routes), 681 .num_routes = ARRAY_SIZE(routes), 682 .routes = routes, 683 }; 684 685 return v4l2_subdev_set_routing_with_fmt(sd, state, &routing, 686 &default_format); 687 } 688 689 static const struct v4l2_subdev_internal_ops dw_mipi_csi2rx_internal_ops = { 690 .init_state = dw_mipi_csi2rx_init_state, 691 }; 692 693 static int dw_mipi_csi2rx_notifier_bound(struct v4l2_async_notifier *notifier, 694 struct v4l2_subdev *sd, 695 struct v4l2_async_connection *asd) 696 { 697 struct dw_mipi_csi2rx_device *csi2 = 698 container_of(notifier, struct dw_mipi_csi2rx_device, notifier); 699 struct media_pad *sink_pad = &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]; 700 int ret; 701 702 ret = v4l2_create_fwnode_links_to_pad(sd, sink_pad, 703 MEDIA_LNK_FL_ENABLED); 704 if (ret) { 705 dev_err(csi2->dev, "failed to link source pad of %s\n", 706 sd->name); 707 return ret; 708 } 709 710 return 0; 711 } 712 713 static const struct v4l2_async_notifier_operations dw_mipi_csi2rx_notifier_ops = { 714 .bound = dw_mipi_csi2rx_notifier_bound, 715 }; 716 717 static int dw_mipi_csi2rx_register_notifier(struct dw_mipi_csi2rx_device *csi2) 718 { 719 struct v4l2_async_connection *asd; 720 struct v4l2_async_notifier *ntf = &csi2->notifier; 721 struct v4l2_fwnode_endpoint vep; 722 struct v4l2_subdev *sd = &csi2->sd; 723 struct device *dev = csi2->dev; 724 int ret; 725 726 struct fwnode_handle *ep __free(fwnode_handle) = 727 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); 728 if (!ep) 729 return dev_err_probe(dev, -ENODEV, "failed to get endpoint\n"); 730 731 vep.bus_type = V4L2_MBUS_UNKNOWN; 732 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 733 if (ret) 734 return dev_err_probe(dev, ret, "failed to parse endpoint\n"); 735 736 if (vep.bus_type != V4L2_MBUS_CSI2_DPHY && 737 vep.bus_type != V4L2_MBUS_CSI2_CPHY) 738 return dev_err_probe(dev, -EINVAL, 739 "invalid bus type of endpoint\n"); 740 741 csi2->bus_type = vep.bus_type; 742 csi2->lanes_num = vep.bus.mipi_csi2.num_data_lanes; 743 744 v4l2_async_subdev_nf_init(ntf, sd); 745 ntf->ops = &dw_mipi_csi2rx_notifier_ops; 746 747 asd = v4l2_async_nf_add_fwnode_remote(ntf, ep, 748 struct v4l2_async_connection); 749 if (IS_ERR(asd)) { 750 ret = PTR_ERR(asd); 751 goto err_nf_cleanup; 752 } 753 754 ret = v4l2_async_nf_register(ntf); 755 if (ret) { 756 ret = dev_err_probe(dev, ret, "failed to register notifier\n"); 757 goto err_nf_cleanup; 758 } 759 760 return 0; 761 762 err_nf_cleanup: 763 v4l2_async_nf_cleanup(ntf); 764 765 return ret; 766 } 767 768 static int dw_mipi_csi2rx_register(struct dw_mipi_csi2rx_device *csi2) 769 { 770 struct media_pad *pads = csi2->pads; 771 struct v4l2_subdev *sd = &csi2->sd; 772 int ret; 773 774 ret = dw_mipi_csi2rx_register_notifier(csi2); 775 if (ret) 776 goto err; 777 778 v4l2_subdev_init(sd, &dw_mipi_csi2rx_ops); 779 sd->dev = csi2->dev; 780 sd->entity.ops = &dw_mipi_csi2rx_media_ops; 781 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 782 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; 783 sd->internal_ops = &dw_mipi_csi2rx_internal_ops; 784 snprintf(sd->name, sizeof(sd->name), "dw-mipi-csi2rx %s", 785 dev_name(csi2->dev)); 786 787 pads[DW_MIPI_CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK | 788 MEDIA_PAD_FL_MUST_CONNECT; 789 pads[DW_MIPI_CSI2RX_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 790 ret = media_entity_pads_init(&sd->entity, DW_MIPI_CSI2RX_PAD_MAX, pads); 791 if (ret) 792 goto err_notifier_unregister; 793 794 ret = v4l2_subdev_init_finalize(sd); 795 if (ret) 796 goto err_entity_cleanup; 797 798 ret = v4l2_async_register_subdev(sd); 799 if (ret) { 800 dev_err(sd->dev, "failed to register CSI-2 subdev\n"); 801 goto err_subdev_cleanup; 802 } 803 804 return 0; 805 806 err_subdev_cleanup: 807 v4l2_subdev_cleanup(sd); 808 err_entity_cleanup: 809 media_entity_cleanup(&sd->entity); 810 err_notifier_unregister: 811 v4l2_async_nf_unregister(&csi2->notifier); 812 v4l2_async_nf_cleanup(&csi2->notifier); 813 err: 814 return ret; 815 } 816 817 static void dw_mipi_csi2rx_unregister(struct dw_mipi_csi2rx_device *csi2) 818 { 819 struct v4l2_subdev *sd = &csi2->sd; 820 821 v4l2_async_unregister_subdev(sd); 822 v4l2_subdev_cleanup(sd); 823 media_entity_cleanup(&sd->entity); 824 v4l2_async_nf_unregister(&csi2->notifier); 825 v4l2_async_nf_cleanup(&csi2->notifier); 826 } 827 828 static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *csi2) 829 { 830 u32 val; 831 832 /* Release Synopsys DPHY test codes from reset */ 833 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0); 834 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0); 835 836 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); 837 val &= ~DPHY_TEST_CTRL0_TEST_CLR; 838 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); 839 840 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); 841 /* Wait for at least 15ns */ 842 ndelay(15); 843 val |= DPHY_TEST_CTRL0_TEST_CLR; 844 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); 845 } 846 847 static void imx93_csi2rx_dphy_deassert_reset(struct dw_mipi_csi2rx_device *csi2) 848 { 849 /* Release PHY from reset */ 850 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0x1); 851 /* 852 * ndelay() is not necessary have MMIO operation, need dummy read to 853 * ensure that the write operation above reaches its target. 854 */ 855 dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ); 856 ndelay(5); 857 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0x1); 858 859 dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ); 860 ndelay(5); 861 } 862 863 static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi2) 864 { 865 int dt = csi2->formats->csi_dt; 866 u32 val; 867 868 /* Do IPI soft reset */ 869 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x0); 870 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x1); 871 872 /* Select virtual channel and data type to be processed by IPI */ 873 val = IPI_DATA_TYPE_DT(dt); 874 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_DATATYPE, val); 875 876 /* Set virtual channel 0 as default */ 877 val = IPI_VCID_VC(0); 878 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_VCID, val); 879 880 /* 881 * Select IPI camera timing mode and allow the pixel stream 882 * to be non-continuous when pixel interface FIFO is empty 883 */ 884 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); 885 val &= ~IPI_MODE_CONTROLLER; 886 val &= ~IPI_MODE_COLOR_MODE16; 887 val |= IPI_MODE_CUT_THROUGH; 888 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); 889 890 /* Memory is automatically flushed at each Frame Start */ 891 val = IPI_MEM_FLUSH_AUTO; 892 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MEM_FLUSH, val); 893 894 /* Enable IPI */ 895 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); 896 val |= IPI_MODE_ENABLE; 897 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); 898 } 899 900 static int imx93_csi2rx_wait_for_phy_stopstate(struct dw_mipi_csi2rx_device *csi2) 901 { 902 struct device *dev = csi2->dev; 903 u32 stopstate_mask; 904 u32 val; 905 int ret; 906 907 stopstate_mask = DPHY_STOPSTATE_CLK_LANE | GENMASK(csi2->lanes_num - 1, 0); 908 909 ret = read_poll_timeout(dw_mipi_csi2rx_read, val, 910 (val & stopstate_mask) == stopstate_mask, 911 10, 1000, true, 912 csi2, DW_MIPI_CSI2RX_PHY_STOPSTATE); 913 if (ret) 914 dev_err(dev, "lanes are not in stop state: %#x, expected %#x\n", 915 val, stopstate_mask); 916 917 return ret; 918 } 919 920 static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = { 921 .regs = imx93_regs, 922 .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset, 923 .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset, 924 .ipi_enable = imx93_csi2rx_dphy_ipi_enable, 925 .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate, 926 }; 927 928 static const struct dw_mipi_csi2rx_drvdata imx95_drvdata = { 929 .regs = imx95_regs, 930 .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset, 931 .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset, 932 .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate, 933 }; 934 935 static const struct of_device_id dw_mipi_csi2rx_of_match[] = { 936 { 937 .compatible = "fsl,imx93-mipi-csi2", 938 .data = &imx93_drvdata, 939 }, 940 { 941 .compatible = "fsl,imx95-mipi-csi2", 942 .data = &imx95_drvdata, 943 }, 944 { 945 .compatible = "rockchip,rk3568-mipi-csi2", 946 .data = &rk3568_drvdata, 947 }, 948 {} 949 }; 950 MODULE_DEVICE_TABLE(of, dw_mipi_csi2rx_of_match); 951 952 static int dw_mipi_csi2rx_probe(struct platform_device *pdev) 953 { 954 struct device *dev = &pdev->dev; 955 struct dw_mipi_csi2rx_device *csi2; 956 int ret; 957 958 csi2 = devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL); 959 if (!csi2) 960 return -ENOMEM; 961 csi2->dev = dev; 962 dev_set_drvdata(dev, csi2); 963 964 csi2->base_addr = devm_platform_ioremap_resource(pdev, 0); 965 if (IS_ERR(csi2->base_addr)) 966 return PTR_ERR(csi2->base_addr); 967 968 csi2->drvdata = device_get_match_data(dev); 969 if (!csi2->drvdata) 970 return dev_err_probe(dev, -EINVAL, 971 "failed to get driver data\n"); 972 973 ret = devm_clk_bulk_get_all(dev, &csi2->clks); 974 if (ret < 0) 975 return dev_err_probe(dev, -ENODEV, "failed to get clocks\n"); 976 csi2->clks_num = ret; 977 978 csi2->phy = devm_phy_get(dev, NULL); 979 if (IS_ERR(csi2->phy)) 980 return dev_err_probe(dev, PTR_ERR(csi2->phy), 981 "failed to get MIPI CSI-2 PHY\n"); 982 983 csi2->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 984 if (IS_ERR(csi2->reset)) 985 return dev_err_probe(dev, PTR_ERR(csi2->reset), 986 "failed to get reset\n"); 987 988 csi2->formats = formats; 989 csi2->formats_num = ARRAY_SIZE(formats); 990 991 ret = devm_pm_runtime_enable(dev); 992 if (ret) 993 return dev_err_probe(dev, ret, "failed to enable pm runtime\n"); 994 995 ret = phy_init(csi2->phy); 996 if (ret) 997 return dev_err_probe(dev, ret, 998 "failed to initialize MIPI CSI-2 PHY\n"); 999 1000 ret = dw_mipi_csi2rx_register(csi2); 1001 if (ret) 1002 goto err_phy_exit; 1003 1004 return 0; 1005 1006 err_phy_exit: 1007 phy_exit(csi2->phy); 1008 1009 return ret; 1010 } 1011 1012 static void dw_mipi_csi2rx_remove(struct platform_device *pdev) 1013 { 1014 struct dw_mipi_csi2rx_device *csi2 = platform_get_drvdata(pdev); 1015 1016 dw_mipi_csi2rx_unregister(csi2); 1017 phy_exit(csi2->phy); 1018 } 1019 1020 static int dw_mipi_csi2rx_runtime_suspend(struct device *dev) 1021 { 1022 struct dw_mipi_csi2rx_device *csi2 = dev_get_drvdata(dev); 1023 1024 clk_bulk_disable_unprepare(csi2->clks_num, csi2->clks); 1025 1026 return 0; 1027 } 1028 1029 static int dw_mipi_csi2rx_runtime_resume(struct device *dev) 1030 { 1031 struct dw_mipi_csi2rx_device *csi2 = dev_get_drvdata(dev); 1032 int ret; 1033 1034 reset_control_assert(csi2->reset); 1035 udelay(5); 1036 reset_control_deassert(csi2->reset); 1037 1038 ret = clk_bulk_prepare_enable(csi2->clks_num, csi2->clks); 1039 if (ret) { 1040 dev_err(dev, "failed to enable clocks\n"); 1041 return ret; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static DEFINE_RUNTIME_DEV_PM_OPS(dw_mipi_csi2rx_pm_ops, 1048 dw_mipi_csi2rx_runtime_suspend, 1049 dw_mipi_csi2rx_runtime_resume, NULL); 1050 1051 static struct platform_driver dw_mipi_csi2rx_drv = { 1052 .driver = { 1053 .name = "dw-mipi-csi2rx", 1054 .of_match_table = dw_mipi_csi2rx_of_match, 1055 .pm = pm_ptr(&dw_mipi_csi2rx_pm_ops), 1056 }, 1057 .probe = dw_mipi_csi2rx_probe, 1058 .remove = dw_mipi_csi2rx_remove, 1059 }; 1060 module_platform_driver(dw_mipi_csi2rx_drv); 1061 1062 MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Receiver platform driver"); 1063 MODULE_LICENSE("GPL"); 1064