1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/hwmon.h>
7 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_address.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/spinlock.h>
14 #include <linux/sysfs.h>
15 #include <linux/thermal.h>
16
17 /* NPCM7XX PWM registers */
18 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
19
20 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
21 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
22 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
23 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
24 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
25 #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
26 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
27 #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
28 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
29 #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
30 #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
31
32 #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
33 #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
34 #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
35 #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
36
37 #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
38 #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
39 #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
40 #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
41
42 #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
43 #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
44 #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
45 #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
46
47 /* Define the maximum PWM channel number */
48 #define NPCM7XX_PWM_MAX_CHN_NUM 12
49 #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
50 #define NPCM7XX_PWM_MAX_MODULES 3
51
52 /* Define the Counter Register, value = 100 for match 100% */
53 #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255
54 #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255
55 #define NPCM7XX_PWM_CMR_MAX 255
56
57 /* default all PWM channels PRESCALE2 = 1 */
58 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4
59 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40
60 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400
61 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000
62
63 #define PWM_OUTPUT_FREQ_25KHZ 25000
64 #define PWN_CNT_DEFAULT 256
65 #define MIN_PRESCALE1 2
66 #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
67
68 #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
69 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
72
73 #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
74 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
75 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
76 NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
77
78 /* NPCM7XX FAN Tacho registers */
79 #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
80
81 #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
82 #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
83 #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
84 #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
85 #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
86 #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
87 #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
88 #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
89 #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
90 #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
91 #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
92 #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
93 #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
94 #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
95 #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
96
97 #define NPCM7XX_FAN_TCKC_CLKX_NONE 0
98 #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)
99 #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)
100
101 #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)
102 #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)
103 #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)
104 #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)
105 #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)
106
107 #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
108 #define NPCM7XX_FAN_TICLR_TFCLR BIT(5)
109 #define NPCM7XX_FAN_TICLR_TECLR BIT(4)
110 #define NPCM7XX_FAN_TICLR_TDCLR BIT(3)
111 #define NPCM7XX_FAN_TICLR_TCCLR BIT(2)
112 #define NPCM7XX_FAN_TICLR_TBCLR BIT(1)
113 #define NPCM7XX_FAN_TICLR_TACLR BIT(0)
114
115 #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
116 #define NPCM7XX_FAN_TIEN_TFIEN BIT(5)
117 #define NPCM7XX_FAN_TIEN_TEIEN BIT(4)
118 #define NPCM7XX_FAN_TIEN_TDIEN BIT(3)
119 #define NPCM7XX_FAN_TIEN_TCIEN BIT(2)
120 #define NPCM7XX_FAN_TIEN_TBIEN BIT(1)
121 #define NPCM7XX_FAN_TIEN_TAIEN BIT(0)
122
123 #define NPCM7XX_FAN_TICTRL_TFPND BIT(5)
124 #define NPCM7XX_FAN_TICTRL_TEPND BIT(4)
125 #define NPCM7XX_FAN_TICTRL_TDPND BIT(3)
126 #define NPCM7XX_FAN_TICTRL_TCPND BIT(2)
127 #define NPCM7XX_FAN_TICTRL_TBPND BIT(1)
128 #define NPCM7XX_FAN_TICTRL_TAPND BIT(0)
129
130 #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)
131 #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)
132 #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)
133 #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)
134 #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)
135 #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)
136 #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)
137 #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)
138
139 /* FAN General Definition */
140 /* Define the maximum FAN channel number */
141 #define NPCM7XX_FAN_MAX_MODULE 8
142 #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
143 #define NPCM7XX_FAN_MAX_CHN_NUM 16
144
145 /*
146 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
147 * Timeout 94ms ~= 0x5000
148 * (The minimum FAN speed could to support ~640RPM/pulse 1,
149 * 320RPM/pulse 2, ...-- 10.6Hz)
150 */
151 #define NPCM7XX_FAN_TIMEOUT 0x5000
152 #define NPCM7XX_FAN_TCNT 0xFFFF
153 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
154 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155
156 #define NPCM7XX_FAN_POLL_TIMER_200MS 200
157 #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2
158 #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0
159 #define NPCM7XX_FAN_CLK_PRESCALE 255
160
161 #define NPCM7XX_FAN_CMPA 0
162 #define NPCM7XX_FAN_CMPB 1
163
164 /* Obtain the fan number */
165 #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))
166
167 /* fan sample status */
168 #define FAN_DISABLE 0xFF
169 #define FAN_INIT 0x00
170 #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01
171 #define FAN_ENOUGH_SAMPLE 0x02
172
173 struct npcm_hwmon_info {
174 u32 pwm_max_channel;
175 };
176
177 struct npcm7xx_fan_dev {
178 u8 fan_st_flg;
179 u8 fan_pls_per_rev;
180 u16 fan_cnt;
181 u32 fan_cnt_tmp;
182 };
183
184 struct npcm7xx_cooling_device {
185 char name[THERMAL_NAME_LENGTH];
186 struct npcm7xx_pwm_fan_data *data;
187 struct thermal_cooling_device *tcdev;
188 int pwm_port;
189 u8 *cooling_levels;
190 u8 max_state;
191 u8 cur_state;
192 };
193
194 struct npcm7xx_pwm_fan_data {
195 void __iomem *pwm_base;
196 void __iomem *fan_base;
197 int pwm_modules;
198 struct clk *pwm_clk;
199 struct clk *fan_clk;
200 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
201 int fan_irq[NPCM7XX_FAN_MAX_MODULE];
202 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
203 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
204 u32 input_clk_freq;
205 struct timer_list fan_timer;
206 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
207 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
208 const struct npcm_hwmon_info *info;
209 u8 fan_select;
210 };
211
npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data * data,int channel,u16 val)212 static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
213 int channel, u16 val)
214 {
215 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
216 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
217 u32 tmp_buf, ctrl_en_bit, env_bit;
218
219 /*
220 * Config PWM Comparator register for setting duty cycle
221 */
222
223 /* write new CMR value */
224 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
225 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
226
227 switch (pwm_ch) {
228 case 0:
229 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
230 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
231 break;
232 case 1:
233 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
234 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
235 break;
236 case 2:
237 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
238 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
239 break;
240 case 3:
241 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
242 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
243 break;
244 default:
245 return -ENODEV;
246 }
247
248 if (val == 0) {
249 /* Disable PWM */
250 tmp_buf &= ~ctrl_en_bit;
251 tmp_buf |= env_bit;
252 } else {
253 /* Enable PWM */
254 tmp_buf |= ctrl_en_bit;
255 tmp_buf &= ~env_bit;
256 }
257
258 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
259 return 0;
260 }
261
npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp)262 static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
263 u8 fan, u8 cmp)
264 {
265 u8 fan_id;
266 u8 reg_mode;
267 u8 reg_int;
268 unsigned long flags;
269
270 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
271
272 /* to check whether any fan tach is enable */
273 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
274 /* reset status */
275 spin_lock_irqsave(&data->fan_lock[fan], flags);
276
277 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
278 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
279
280 /*
281 * the interrupt enable bits do not need to be cleared before
282 * it sets, the interrupt enable bits are cleared only on reset.
283 * the clock unit control register is behaving in the same
284 * manner that the interrupt enable register behave.
285 */
286 if (cmp == NPCM7XX_FAN_CMPA) {
287 /* enable interrupt */
288 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
289 NPCM7XX_FAN_TIEN_TEIEN),
290 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
291
292 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
293 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
294 fan));
295
296 /* start to Capture */
297 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
298 fan));
299 } else {
300 /* enable interrupt */
301 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
302 NPCM7XX_FAN_TIEN_TFIEN),
303 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
304
305 reg_mode =
306 NPCM7XX_FAN_TCKC_CLK2_APB
307 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
308 fan));
309
310 /* start to Capture */
311 iowrite8(reg_mode,
312 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
313 }
314
315 spin_unlock_irqrestore(&data->fan_lock[fan], flags);
316 }
317 }
318
319 /*
320 * Enable a background timer to poll fan tach value, (200ms * 4)
321 * to polling all fan
322 */
npcm7xx_fan_polling(struct timer_list * t)323 static void npcm7xx_fan_polling(struct timer_list *t)
324 {
325 struct npcm7xx_pwm_fan_data *data;
326 int i;
327
328 data = timer_container_of(data, t, fan_timer);
329
330 /*
331 * Polling two module per one round,
332 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
333 */
334 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
335 i = i + 4) {
336 /* clear the flag and reset the counter (TCNT) */
337 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
338 NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
339
340 if (data->fan_present[i * 2]) {
341 iowrite16(NPCM7XX_FAN_TCNT,
342 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
343 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
344 }
345 if (data->fan_present[(i * 2) + 1]) {
346 iowrite16(NPCM7XX_FAN_TCNT,
347 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
348 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
349 }
350 }
351
352 data->fan_select++;
353 data->fan_select &= 0x3;
354
355 /* reset the timer interval */
356 data->fan_timer.expires = jiffies +
357 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
358 add_timer(&data->fan_timer);
359 }
360
npcm7xx_fan_cleanup(void * timer)361 static void npcm7xx_fan_cleanup(void *timer)
362 {
363 timer_shutdown_sync(timer);
364 }
365
npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp,u8 fan_id,u8 flag_int,u8 flag_mode,u8 flag_clear)366 static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
367 u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
368 u8 flag_mode, u8 flag_clear)
369 {
370 u8 reg_int;
371 u8 reg_mode;
372 u16 fan_cap;
373
374 if (cmp == NPCM7XX_FAN_CMPA)
375 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
376 else
377 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
378
379 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
380 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
381
382 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
383 /* First capture, drop it */
384 data->fan_dev[fan_id].fan_st_flg =
385 FAN_PREPARE_TO_GET_FIRST_CAPTURE;
386
387 /* reset counter */
388 data->fan_dev[fan_id].fan_cnt_tmp = 0;
389 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
390 /*
391 * collect the enough sample,
392 * (ex: 2 pulse fan need to get 2 sample)
393 */
394 data->fan_dev[fan_id].fan_cnt_tmp +=
395 (NPCM7XX_FAN_TCNT - fan_cap);
396
397 data->fan_dev[fan_id].fan_st_flg++;
398 } else {
399 /* get enough sample or fan disable */
400 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
401 data->fan_dev[fan_id].fan_cnt_tmp +=
402 (NPCM7XX_FAN_TCNT - fan_cap);
403
404 /* compute finial average cnt per pulse */
405 data->fan_dev[fan_id].fan_cnt =
406 data->fan_dev[fan_id].fan_cnt_tmp /
407 FAN_ENOUGH_SAMPLE;
408
409 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
410 }
411
412 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
413
414 /* disable interrupt */
415 iowrite8((reg_int & ~flag_int),
416 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
417 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
418
419 /* stop capturing */
420 iowrite8((reg_mode & ~flag_mode),
421 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
422 }
423 }
424
npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp,u8 flag)425 static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
426 u8 fan, u8 cmp, u8 flag)
427 {
428 u8 reg_int;
429 u8 reg_mode;
430 u8 flag_timeout;
431 u8 flag_cap;
432 u8 flag_clear;
433 u8 flag_int;
434 u8 flag_mode;
435 u8 fan_id;
436
437 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
438
439 if (cmp == NPCM7XX_FAN_CMPA) {
440 flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
441 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
442 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
443 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
444 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
445 } else {
446 flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
447 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
448 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
449 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
450 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
451 }
452
453 if (flag & flag_timeout) {
454 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
455
456 /* disable interrupt */
457 iowrite8((reg_int & ~flag_int),
458 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
459
460 /* clear interrupt flag */
461 iowrite8(flag_clear,
462 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
463
464 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
465
466 /* stop capturing */
467 iowrite8((reg_mode & ~flag_mode),
468 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
469
470 /*
471 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
472 * connect or speed is lower than 10.6Hz (320RPM/pulse2).
473 * In these situation, the RPM output should be zero.
474 */
475 data->fan_dev[fan_id].fan_cnt = 0;
476 } else {
477 /* input capture is occurred */
478 if (flag & flag_cap)
479 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
480 flag_mode, flag_clear);
481 }
482 }
483
npcm7xx_fan_isr(int irq,void * dev_id)484 static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
485 {
486 struct npcm7xx_pwm_fan_data *data = dev_id;
487 unsigned long flags;
488 int module;
489 u8 flag;
490
491 module = irq - data->fan_irq[0];
492 spin_lock_irqsave(&data->fan_lock[module], flags);
493
494 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
495 if (flag > 0) {
496 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
497 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
498 spin_unlock_irqrestore(&data->fan_lock[module], flags);
499 return IRQ_HANDLED;
500 }
501
502 spin_unlock_irqrestore(&data->fan_lock[module], flags);
503
504 return IRQ_NONE;
505 }
506
npcm7xx_read_pwm(struct device * dev,u32 attr,int channel,long * val)507 static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
508 long *val)
509 {
510 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
511 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
512 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
513
514 switch (attr) {
515 case hwmon_pwm_input:
516 *val = ioread32
517 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
518 return 0;
519 default:
520 return -EOPNOTSUPP;
521 }
522 }
523
npcm7xx_write_pwm(struct device * dev,u32 attr,int channel,long val)524 static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
525 long val)
526 {
527 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
528 int err;
529
530 switch (attr) {
531 case hwmon_pwm_input:
532 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
533 return -EINVAL;
534 err = npcm7xx_pwm_config_set(data, channel, (u16)val);
535 break;
536 default:
537 err = -EOPNOTSUPP;
538 break;
539 }
540
541 return err;
542 }
543
npcm7xx_pwm_is_visible(const void * _data,u32 attr,int channel)544 static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
545 {
546 const struct npcm7xx_pwm_fan_data *data = _data;
547
548 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel)
549 return 0;
550
551 switch (attr) {
552 case hwmon_pwm_input:
553 return 0644;
554 default:
555 return 0;
556 }
557 }
558
npcm7xx_read_fan(struct device * dev,u32 attr,int channel,long * val)559 static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
560 long *val)
561 {
562 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
563
564 switch (attr) {
565 case hwmon_fan_input:
566 *val = 0;
567 if (data->fan_dev[channel].fan_cnt <= 0)
568 return data->fan_dev[channel].fan_cnt;
569
570 /* Convert the raw reading to RPM */
571 if (data->fan_dev[channel].fan_cnt > 0 &&
572 data->fan_dev[channel].fan_pls_per_rev > 0)
573 *val = ((data->input_clk_freq * 60) /
574 (data->fan_dev[channel].fan_cnt *
575 data->fan_dev[channel].fan_pls_per_rev));
576 return 0;
577 default:
578 return -EOPNOTSUPP;
579 }
580 }
581
npcm7xx_fan_is_visible(const void * _data,u32 attr,int channel)582 static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
583 {
584 const struct npcm7xx_pwm_fan_data *data = _data;
585
586 if (!data->fan_present[channel])
587 return 0;
588
589 switch (attr) {
590 case hwmon_fan_input:
591 return 0444;
592 default:
593 return 0;
594 }
595 }
596
npcm7xx_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)597 static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
598 u32 attr, int channel, long *val)
599 {
600 switch (type) {
601 case hwmon_pwm:
602 return npcm7xx_read_pwm(dev, attr, channel, val);
603 case hwmon_fan:
604 return npcm7xx_read_fan(dev, attr, channel, val);
605 default:
606 return -EOPNOTSUPP;
607 }
608 }
609
npcm7xx_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)610 static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
611 u32 attr, int channel, long val)
612 {
613 switch (type) {
614 case hwmon_pwm:
615 return npcm7xx_write_pwm(dev, attr, channel, val);
616 default:
617 return -EOPNOTSUPP;
618 }
619 }
620
npcm7xx_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)621 static umode_t npcm7xx_is_visible(const void *data,
622 enum hwmon_sensor_types type,
623 u32 attr, int channel)
624 {
625 switch (type) {
626 case hwmon_pwm:
627 return npcm7xx_pwm_is_visible(data, attr, channel);
628 case hwmon_fan:
629 return npcm7xx_fan_is_visible(data, attr, channel);
630 default:
631 return 0;
632 }
633 }
634
635 static const struct hwmon_channel_info * const npcm7xx_info[] = {
636 HWMON_CHANNEL_INFO(pwm,
637 HWMON_PWM_INPUT,
638 HWMON_PWM_INPUT,
639 HWMON_PWM_INPUT,
640 HWMON_PWM_INPUT,
641 HWMON_PWM_INPUT,
642 HWMON_PWM_INPUT,
643 HWMON_PWM_INPUT,
644 HWMON_PWM_INPUT,
645 HWMON_PWM_INPUT,
646 HWMON_PWM_INPUT,
647 HWMON_PWM_INPUT,
648 HWMON_PWM_INPUT),
649 HWMON_CHANNEL_INFO(fan,
650 HWMON_F_INPUT,
651 HWMON_F_INPUT,
652 HWMON_F_INPUT,
653 HWMON_F_INPUT,
654 HWMON_F_INPUT,
655 HWMON_F_INPUT,
656 HWMON_F_INPUT,
657 HWMON_F_INPUT,
658 HWMON_F_INPUT,
659 HWMON_F_INPUT,
660 HWMON_F_INPUT,
661 HWMON_F_INPUT,
662 HWMON_F_INPUT,
663 HWMON_F_INPUT,
664 HWMON_F_INPUT,
665 HWMON_F_INPUT),
666 NULL
667 };
668
669 static const struct hwmon_ops npcm7xx_hwmon_ops = {
670 .is_visible = npcm7xx_is_visible,
671 .read = npcm7xx_read,
672 .write = npcm7xx_write,
673 };
674
675 static const struct hwmon_chip_info npcm7xx_chip_info = {
676 .ops = &npcm7xx_hwmon_ops,
677 .info = npcm7xx_info,
678 };
679
680 static const struct npcm_hwmon_info npxm7xx_hwmon_info = {
681 .pwm_max_channel = 8,
682 };
683
684 static const struct npcm_hwmon_info npxm8xx_hwmon_info = {
685 .pwm_max_channel = 12,
686 };
687
npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data * data)688 static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
689 {
690 int m, ch;
691 u32 prescale_val, output_freq;
692 unsigned long pwm_clk_freq;
693
694 pwm_clk_freq = clk_get_rate(data->pwm_clk);
695
696 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
697 output_freq = pwm_clk_freq / PWN_CNT_DEFAULT;
698 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
699
700 /* If prescale_val = 0, then the prescale output clock is stopped */
701 if (prescale_val < MIN_PRESCALE1)
702 prescale_val = MIN_PRESCALE1;
703 /*
704 * prescale_val need to decrement in one because in the PWM Prescale
705 * register the Prescale value increment by one
706 */
707 prescale_val--;
708
709 /* Setting PWM Prescale Register value register to both modules */
710 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
711
712 for (m = 0; m < data->pwm_modules; m++) {
713 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
714 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
715 NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
716 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
717 NPCM7XX_PWM_REG_CR(data->pwm_base, m));
718
719 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
720 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
721 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
722 }
723 }
724
725 return output_freq / ((prescale_val & 0xf) + 1);
726 }
727
npcm7xx_fan_init(struct npcm7xx_pwm_fan_data * data)728 static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
729 {
730 int md;
731 int ch;
732 int i;
733 u32 apb_clk_freq;
734
735 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
736 /* stop FAN0~7 clock */
737 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
738 NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
739
740 /* disable all interrupt */
741 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
742
743 /* clear all interrupt */
744 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
745 NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
746
747 /* set FAN0~7 clock prescaler */
748 iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
749 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
750
751 /* set FAN0~7 mode (high-to-low transition) */
752 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
753 NPCM7XX_FAN_TMCTRL_TAEN),
754 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
755
756 /* set FAN0~7 Initial Count/Cap */
757 iowrite16(NPCM7XX_FAN_TCNT,
758 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
759 iowrite16(NPCM7XX_FAN_TCNT,
760 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
761
762 /* set FAN0~7 compare (equal to count) */
763 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
764 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
765
766 /* set FAN0~7 compare value */
767 iowrite16(NPCM7XX_FAN_TCPA,
768 NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
769 iowrite16(NPCM7XX_FAN_TCPB,
770 NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
771
772 /* set FAN0~7 fan input FANIN 0~15 */
773 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
774 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
775 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
776 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
777
778 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
779 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
780 data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
781 data->fan_dev[ch].fan_pls_per_rev =
782 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
783 data->fan_dev[ch].fan_cnt = 0;
784 }
785 }
786
787 apb_clk_freq = clk_get_rate(data->fan_clk);
788
789 /* Fan tach input clock = APB clock / prescalar, default is 255. */
790 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
791 }
792
793 static int
npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device * tcdev,unsigned long * state)794 npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
795 unsigned long *state)
796 {
797 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
798
799 *state = cdev->max_state;
800
801 return 0;
802 }
803
804 static int
npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device * tcdev,unsigned long * state)805 npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
806 unsigned long *state)
807 {
808 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
809
810 *state = cdev->cur_state;
811
812 return 0;
813 }
814
815 static int
npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device * tcdev,unsigned long state)816 npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
817 unsigned long state)
818 {
819 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
820 int ret;
821
822 if (state > cdev->max_state)
823 return -EINVAL;
824
825 cdev->cur_state = state;
826 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
827 cdev->cooling_levels[cdev->cur_state]);
828
829 return ret;
830 }
831
832 static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
833 .get_max_state = npcm7xx_pwm_cz_get_max_state,
834 .get_cur_state = npcm7xx_pwm_cz_get_cur_state,
835 .set_cur_state = npcm7xx_pwm_cz_set_cur_state,
836 };
837
npcm7xx_create_pwm_cooling(struct device * dev,struct device_node * child,struct npcm7xx_pwm_fan_data * data,u32 pwm_port,u8 num_levels)838 static int npcm7xx_create_pwm_cooling(struct device *dev,
839 struct device_node *child,
840 struct npcm7xx_pwm_fan_data *data,
841 u32 pwm_port, u8 num_levels)
842 {
843 int ret;
844 struct npcm7xx_cooling_device *cdev;
845
846 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
847 if (!cdev)
848 return -ENOMEM;
849
850 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
851 if (!cdev->cooling_levels)
852 return -ENOMEM;
853
854 cdev->max_state = num_levels - 1;
855 ret = of_property_read_u8_array(child, "cooling-levels",
856 cdev->cooling_levels,
857 num_levels);
858 if (ret) {
859 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
860 return ret;
861 }
862 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
863 pwm_port);
864
865 cdev->tcdev = devm_thermal_of_child_cooling_device_register(dev, child,
866 cdev->name,
867 cdev,
868 &npcm7xx_pwm_cool_ops);
869 if (IS_ERR(cdev->tcdev))
870 return PTR_ERR(cdev->tcdev);
871
872 cdev->data = data;
873 cdev->pwm_port = pwm_port;
874
875 data->cdev[pwm_port] = cdev;
876
877 return 0;
878 }
879
npcm7xx_en_pwm_fan(struct device * dev,struct device_node * child,struct npcm7xx_pwm_fan_data * data)880 static int npcm7xx_en_pwm_fan(struct device *dev,
881 struct device_node *child,
882 struct npcm7xx_pwm_fan_data *data)
883 {
884 u8 *fan_ch;
885 u32 pwm_port;
886 int ret, fan_cnt;
887 u8 index, ch;
888
889 ret = of_property_read_u32(child, "reg", &pwm_port);
890 if (ret)
891 return ret;
892
893 data->pwm_present[pwm_port] = true;
894 ret = npcm7xx_pwm_config_set(data, pwm_port,
895 NPCM7XX_PWM_CMR_DEFAULT_NUM);
896 if (ret)
897 return ret;
898
899 ret = of_property_count_u8_elems(child, "cooling-levels");
900 if (ret > 0) {
901 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
902 ret);
903 if (ret)
904 return ret;
905 }
906
907 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
908 if (fan_cnt < 1)
909 return -EINVAL;
910
911 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
912 if (!fan_ch)
913 return -ENOMEM;
914
915 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
916 if (ret)
917 return ret;
918
919 for (ch = 0; ch < fan_cnt; ch++) {
920 index = fan_ch[ch];
921 data->fan_present[index] = true;
922 data->fan_dev[index].fan_st_flg = FAN_INIT;
923 }
924
925 return 0;
926 }
927
npcm7xx_pwm_fan_probe(struct platform_device * pdev)928 static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
929 {
930 struct device *dev = &pdev->dev;
931 struct device_node *np;
932 struct npcm7xx_pwm_fan_data *data;
933 struct resource *res;
934 struct device *hwmon;
935 char name[20];
936 u32 output_freq;
937 int ret;
938 u32 i;
939
940 np = dev->of_node;
941
942 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
943 if (!data)
944 return -ENOMEM;
945
946 data->info = device_get_match_data(dev);
947 if (!data->info)
948 return -EINVAL;
949
950 data->pwm_modules = data->info->pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE;
951
952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
953 if (!res) {
954 dev_err(dev, "pwm resource not found\n");
955 return -ENODEV;
956 }
957
958 data->pwm_base = devm_ioremap_resource(dev, res);
959 dev_dbg(dev, "pwm base resource is %pR\n", res);
960 if (IS_ERR(data->pwm_base))
961 return PTR_ERR(data->pwm_base);
962
963 data->pwm_clk = devm_clk_get(dev, "pwm");
964 if (IS_ERR(data->pwm_clk)) {
965 dev_err(dev, "couldn't get pwm clock\n");
966 return PTR_ERR(data->pwm_clk);
967 }
968
969 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
970 if (!res) {
971 dev_err(dev, "fan resource not found\n");
972 return -ENODEV;
973 }
974
975 data->fan_base = devm_ioremap_resource(dev, res);
976 dev_dbg(dev, "fan base resource is %pR\n", res);
977 if (IS_ERR(data->fan_base))
978 return PTR_ERR(data->fan_base);
979
980 data->fan_clk = devm_clk_get(dev, "fan");
981 if (IS_ERR(data->fan_clk)) {
982 dev_err(dev, "couldn't get fan clock\n");
983 return PTR_ERR(data->fan_clk);
984 }
985
986 output_freq = npcm7xx_pwm_init(data);
987 npcm7xx_fan_init(data);
988
989 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
990 spin_lock_init(&data->fan_lock[i]);
991
992 data->fan_irq[i] = platform_get_irq(pdev, i);
993 if (data->fan_irq[i] < 0)
994 return data->fan_irq[i];
995
996 sprintf(name, "NPCM7XX-FAN-MD%d", i);
997 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
998 0, name, (void *)data);
999 if (ret)
1000 return ret;
1001 }
1002
1003 for_each_child_of_node_scoped(np, child) {
1004 ret = npcm7xx_en_pwm_fan(dev, child, data);
1005 if (ret) {
1006 dev_err(dev, "enable pwm and fan failed\n");
1007 return ret;
1008 }
1009 }
1010
1011 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
1012 data, &npcm7xx_chip_info,
1013 NULL);
1014 if (IS_ERR(hwmon)) {
1015 dev_err(dev, "unable to register hwmon device\n");
1016 return PTR_ERR(hwmon);
1017 }
1018
1019 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
1020 if (data->fan_present[i]) {
1021 /* fan timer initialization */
1022 data->fan_timer.expires = jiffies +
1023 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
1024 timer_setup(&data->fan_timer,
1025 npcm7xx_fan_polling, 0);
1026 ret = devm_add_action_or_reset(dev,
1027 npcm7xx_fan_cleanup,
1028 &data->fan_timer);
1029 if (ret)
1030 return ret;
1031
1032 add_timer(&data->fan_timer);
1033 break;
1034 }
1035 }
1036
1037 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
1038 output_freq, data->input_clk_freq);
1039
1040 return 0;
1041 }
1042
1043 static const struct of_device_id of_pwm_fan_match_table[] = {
1044 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info},
1045 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info},
1046 {},
1047 };
1048 MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
1049
1050 static struct platform_driver npcm7xx_pwm_fan_driver = {
1051 .probe = npcm7xx_pwm_fan_probe,
1052 .driver = {
1053 .name = "npcm7xx_pwm_fan",
1054 .of_match_table = of_pwm_fan_match_table,
1055 },
1056 };
1057
1058 module_platform_driver(npcm7xx_pwm_fan_driver);
1059
1060 MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
1061 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
1062 MODULE_LICENSE("GPL v2");
1063