1 /*-
2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_inet.h"
30 #include "opt_inet6.h"
31 #include "opt_acpi.h"
32
33 #include <sys/param.h>
34 #include <sys/types.h>
35 #include <sys/bus.h>
36 #include <sys/eventhandler.h>
37 #include <sys/fail.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/module.h>
42 #include <sys/kobj.h>
43 #include <sys/proc.h>
44 #include <sys/rman.h>
45 #include <sys/sbuf.h>
46 #include <sys/sched.h>
47 #include <sys/smp.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
54
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_private.h>
58 #include <net/if_types.h>
59 #include <net/if_media.h>
60 #include <net/bpf.h>
61 #include <net/ethernet.h>
62 #include <net/mp_ring.h>
63 #include <net/debugnet.h>
64 #include <net/pfil.h>
65 #include <net/vnet.h>
66
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/udp.h>
76 #include <netinet/ip_var.h>
77 #include <netinet6/ip6_var.h>
78
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
81
82 #include <vm/vm.h>
83 #include <vm/pmap.h>
84
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
89
90 #include <net/iflib.h>
91
92 #include "ifdi_if.h"
93
94 #ifdef PCI_IOV
95 #include <dev/pci/pci_iov.h>
96 #endif
97
98 #include <sys/bitstring.h>
99 /*
100 * enable accounting of every mbuf as it comes in to and goes out of
101 * iflib's software descriptor references
102 */
103 #define MEMORY_LOGGING 0
104 /*
105 * Enable mbuf vectors for compressing long mbuf chains
106 */
107
108 /*
109 * NB:
110 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
111 * we prefetch needs to be determined by the time spent in m_free vis a vis
112 * the cost of a prefetch. This will of course vary based on the workload:
113 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
114 * is quite expensive, thus suggesting very little prefetch.
115 * - small packet forwarding which is just returning a single mbuf to
116 * UMA will typically be very fast vis a vis the cost of a memory
117 * access.
118 */
119
120 /*
121 * File organization:
122 * - private structures
123 * - iflib private utility functions
124 * - ifnet functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
127 *
128 *
129 */
130 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
134
135 struct iflib_txq;
136 typedef struct iflib_txq *iflib_txq_t;
137 struct iflib_rxq;
138 typedef struct iflib_rxq *iflib_rxq_t;
139 struct iflib_fl;
140 typedef struct iflib_fl *iflib_fl_t;
141
142 struct iflib_ctx;
143
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
146 static void iflib_tqg_detach(if_ctx_t ctx);
147 #ifndef ALTQ
148 static int iflib_simple_transmit(if_t ifp, struct mbuf *m);
149 #endif
150
151 typedef struct iflib_filter_info {
152 driver_filter_t *ifi_filter;
153 void *ifi_filter_arg;
154 struct grouptask *ifi_task;
155 void *ifi_ctx;
156 } *iflib_filter_info_t;
157
158 struct iflib_ctx {
159 KOBJ_FIELDS;
160 /*
161 * Pointer to hardware driver's softc
162 */
163 void *ifc_softc;
164 device_t ifc_dev;
165 if_t ifc_ifp;
166
167 cpuset_t ifc_cpus;
168 if_shared_ctx_t ifc_sctx;
169 struct if_softc_ctx ifc_softc_ctx;
170
171 struct sx ifc_ctx_sx;
172 struct mtx ifc_state_mtx;
173
174 iflib_txq_t ifc_txqs;
175 iflib_rxq_t ifc_rxqs;
176 uint32_t ifc_if_flags;
177 uint32_t ifc_flags;
178 uint32_t ifc_max_fl_buf_size;
179 uint32_t ifc_rx_mbuf_sz;
180
181 int ifc_link_state;
182 uint32_t ifc_tx_watchdog_events;
183 struct cdev *ifc_led_dev;
184 int ifc_led_state;
185 struct resource *ifc_msix_mem;
186
187 struct if_irq ifc_legacy_irq;
188 struct task ifc_admin_task;
189 struct task ifc_led_task;
190 struct task ifc_vflr_task;
191 struct taskqueue *ifc_tq;
192 struct iflib_filter_info ifc_filter_info;
193 struct ifmedia ifc_media;
194 struct ifmedia *ifc_mediap;
195
196 struct sysctl_ctx_list ifc_sysctl_ctx;
197 struct sysctl_oid *ifc_sysctl_node;
198 uint16_t ifc_sysctl_ntxqs;
199 uint16_t ifc_sysctl_nrxqs;
200 uint16_t ifc_sysctl_qs_eq_override;
201 uint16_t ifc_sysctl_rx_budget;
202 uint16_t ifc_sysctl_tx_abdicate;
203 uint16_t ifc_sysctl_core_offset;
204 #define CORE_OFFSET_UNSPECIFIED 0xffff
205 uint8_t ifc_sysctl_separate_txrx;
206 uint8_t ifc_sysctl_use_logical_cores;
207 uint16_t ifc_sysctl_extra_msix_vectors;
208 bool ifc_cpus_are_physical_cores;
209 bool ifc_core_offset_ref;
210 bool ifc_sysctl_simple_tx;
211 bool ifc_sysctl_tx_defer_mfree;
212 uint16_t ifc_sysctl_tx_reclaim_thresh;
213 uint16_t ifc_sysctl_tx_reclaim_ticks;
214
215 qidx_t ifc_sysctl_ntxds[8];
216 qidx_t ifc_sysctl_nrxds[8];
217 struct if_txrx ifc_txrx;
218 #define isc_txd_encap ifc_txrx.ift_txd_encap
219 #define isc_txd_flush ifc_txrx.ift_txd_flush
220 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
221 #define isc_rxd_available ifc_txrx.ift_rxd_available
222 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
223 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
224 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
225 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
226 #define isc_txq_select ifc_txrx.ift_txq_select
227 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2
228
229 eventhandler_tag ifc_vlan_attach_event;
230 eventhandler_tag ifc_vlan_detach_event;
231 struct ether_addr ifc_mac;
232 };
233
234 void *
iflib_get_softc(if_ctx_t ctx)235 iflib_get_softc(if_ctx_t ctx)
236 {
237
238 return (ctx->ifc_softc);
239 }
240
241 device_t
iflib_get_dev(if_ctx_t ctx)242 iflib_get_dev(if_ctx_t ctx)
243 {
244
245 return (ctx->ifc_dev);
246 }
247
248 if_t
iflib_get_ifp(if_ctx_t ctx)249 iflib_get_ifp(if_ctx_t ctx)
250 {
251
252 return (ctx->ifc_ifp);
253 }
254
255 struct ifmedia *
iflib_get_media(if_ctx_t ctx)256 iflib_get_media(if_ctx_t ctx)
257 {
258
259 return (ctx->ifc_mediap);
260 }
261
262 void
iflib_set_mac(if_ctx_t ctx,uint8_t mac[ETHER_ADDR_LEN])263 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
264 {
265
266 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
267 }
268
269 if_softc_ctx_t
iflib_get_softc_ctx(if_ctx_t ctx)270 iflib_get_softc_ctx(if_ctx_t ctx)
271 {
272
273 return (&ctx->ifc_softc_ctx);
274 }
275
276 if_shared_ctx_t
iflib_get_sctx(if_ctx_t ctx)277 iflib_get_sctx(if_ctx_t ctx)
278 {
279
280 return (ctx->ifc_sctx);
281 }
282
283 uint16_t
iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx)284 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx)
285 {
286
287 return (ctx->ifc_sysctl_extra_msix_vectors);
288 }
289
290 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
291 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *))
292 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE)))
293
294 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
295 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
296
297 typedef struct iflib_sw_rx_desc_array {
298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
299 struct mbuf **ifsd_m; /* pkthdr mbufs */
300 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
301 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
302 } iflib_rxsd_array_t;
303
304 typedef struct iflib_sw_tx_desc_array {
305 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
306 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
307 struct mbuf **ifsd_m; /* pkthdr mbufs */
308 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */
309 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */
310 } if_txsd_vec_t;
311
312 /* magic number that should be high enough for any hardware */
313 #define IFLIB_MAX_TX_SEGS 128
314 #define IFLIB_RX_COPY_THRESH 128
315 #define IFLIB_MAX_RX_REFRESH 32
316 /* The minimum descriptors per second before we start coalescing */
317 #define IFLIB_MIN_DESC_SEC 16384
318 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
319 /* maximum number of txqs that can share an rx interrupt */
320 #define IFLIB_MAX_TX_SHARED_INTR 4
321
322 /* this should really scale with ring size - this is a fairly arbitrary value */
323 #define TX_BATCH_SIZE 32
324
325 #define IFLIB_RESTART_BUDGET 8
326
327
328 /*
329 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as
330 * to avoid defref'ing the mbuf to determine the correct busdma resources
331 * to release
332 */
333 #define IFLIB_TSO (1ULL << 0)
334 #define IFLIB_NO_TSO (2ULL << 0)
335 #define IFLIB_FLAGS_MASK (0x3ULL)
336 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags))
337 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK)
338 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK))
339
340
341 #define IFC_LEGACY 0x001
342 #define IFC_QFLUSH 0x002
343 #define IFC_MULTISEG 0x004
344 #define IFC_INIT_FAILED 0x008
345 #define IFC_SC_ALLOCATED 0x010
346 #define IFC_INIT_DONE 0x020
347 #define IFC_PREFETCH 0x040
348 #define IFC_DO_RESET 0x080
349 #define IFC_DO_WATCHDOG 0x100
350 #define IFC_DO_RESET_IF_UP 0x200
351 #define IFC_SPARE2 0x400
352 #define IFC_IN_DETACH 0x800
353
354 #define IFC_NETMAP_TX_IRQ 0x80000000
355
356 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \
357 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \
358 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP)
359
360 struct iflib_txq {
361 qidx_t ift_in_use;
362 qidx_t ift_cidx;
363 qidx_t ift_cidx_processed;
364 qidx_t ift_pidx;
365 uint8_t ift_gen;
366 uint8_t ift_br_offset:1,
367 ift_defer_mfree:1,
368 ift_spare_bits0:6;
369 uint16_t ift_npending;
370 uint16_t ift_db_pending;
371 uint16_t ift_rs_pending;
372 uint32_t ift_last_reclaim;
373 uint16_t ift_reclaim_thresh;
374 uint16_t ift_reclaim_ticks;
375 uint8_t ift_txd_size[8];
376 uint64_t ift_processed;
377 uint64_t ift_cleaned;
378 uint64_t ift_processed_prev;
379 #if MEMORY_LOGGING
380 uint64_t ift_enqueued;
381 uint64_t ift_dequeued;
382 #endif
383 uint64_t ift_no_tx_dma_setup;
384 uint64_t ift_no_desc_avail;
385 uint64_t ift_mbuf_defrag_failed;
386 uint64_t ift_mbuf_defrag;
387 uint64_t ift_map_failed;
388 uint64_t ift_txd_encap_efbig;
389 uint64_t ift_pullups;
390 uint64_t ift_last_timer_tick;
391
392 struct mtx ift_mtx;
393 struct mtx ift_db_mtx;
394
395 /* constant values */
396 if_ctx_t ift_ctx;
397 struct ifmp_ring *ift_br;
398 struct grouptask ift_task;
399 qidx_t ift_size;
400 qidx_t ift_pad;
401 uint16_t ift_id;
402 struct callout ift_timer;
403 #ifdef DEV_NETMAP
404 struct callout ift_netmap_timer;
405 #endif /* DEV_NETMAP */
406
407 if_txsd_vec_t ift_sds;
408 /*
409 * TX watchdog state, updated once per iflib_timer period. The
410 * period count saturates instead of wrapping, and is 16 bits
411 * wide so that it still reaches any value
412 * net.iflib.tx_watchdog_periods is plausibly set to; an 8-bit
413 * counter would silently disable the check for a threshold
414 * above 255.
415 */
416 qidx_t ift_outstanding_prev;
417 uint16_t ift_wdog_armed;
418 uint8_t ift_closed;
419 uint8_t ift_update_freq;
420 uint8_t ift_spare0[2]; /* pad to the next pointer boundary */
421 struct iflib_filter_info ift_filter_info;
422 bus_dma_tag_t ift_buf_tag;
423 bus_dma_tag_t ift_tso_buf_tag;
424 iflib_dma_info_t ift_ifdi;
425 #define MTX_NAME_LEN 32
426 char ift_mtx_name[MTX_NAME_LEN];
427 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
428 #ifdef IFLIB_DIAGNOSTICS
429 uint64_t ift_cpu_exec_count[256];
430 #endif
431 } __aligned(CACHE_LINE_SIZE);
432
433 struct iflib_fl {
434 qidx_t ifl_cidx;
435 qidx_t ifl_pidx;
436 qidx_t ifl_credits;
437 uint8_t ifl_gen;
438 uint8_t ifl_rxd_size;
439 #if MEMORY_LOGGING
440 uint64_t ifl_m_enqueued;
441 uint64_t ifl_m_dequeued;
442 uint64_t ifl_cl_enqueued;
443 uint64_t ifl_cl_dequeued;
444 #endif
445 /* implicit pad */
446 bitstr_t *ifl_rx_bitmap;
447 qidx_t ifl_fragidx;
448 /* constant */
449 qidx_t ifl_size;
450 uint16_t ifl_buf_size;
451 uint16_t ifl_cltype;
452 uma_zone_t ifl_zone;
453 iflib_rxsd_array_t ifl_sds;
454 iflib_rxq_t ifl_rxq;
455 uint8_t ifl_id;
456 bus_dma_tag_t ifl_buf_tag;
457 iflib_dma_info_t ifl_ifdi;
458 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
459 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
460 } __aligned(CACHE_LINE_SIZE);
461
462 static inline qidx_t
get_inuse(int size,qidx_t cidx,qidx_t pidx,uint8_t gen)463 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
464 {
465 qidx_t used;
466
467 if (pidx > cidx)
468 used = pidx - cidx;
469 else if (pidx < cidx)
470 used = size - cidx + pidx;
471 else if (gen == 0 && pidx == cidx)
472 used = 0;
473 else if (gen == 1 && pidx == cidx)
474 used = size;
475 else
476 panic("bad state");
477
478 return (used);
479 }
480
481 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\
482 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
483
484 #define IDXDIFF(head, tail, wrap) \
485 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
486
487 struct iflib_rxq {
488 if_ctx_t ifr_ctx;
489 iflib_fl_t ifr_fl;
490 struct pfil_head *pfil;
491 /*
492 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
493 * the completion queue consumer index. Otherwise it's unused.
494 */
495 qidx_t ifr_cq_cidx;
496 uint16_t ifr_id;
497 uint8_t ifr_nfl;
498 uint8_t ifr_ntxqirq;
499 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
500 uint8_t ifr_fl_offset;
501 struct lro_ctrl ifr_lc;
502 struct grouptask ifr_task;
503 struct callout ifr_watchdog;
504 struct iflib_filter_info ifr_filter_info;
505 iflib_dma_info_t ifr_ifdi;
506
507 /* dynamically allocate if any drivers need a value substantially larger than this */
508 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
509 #ifdef IFLIB_DIAGNOSTICS
510 uint64_t ifr_cpu_exec_count[256];
511 #endif
512 } __aligned(CACHE_LINE_SIZE);
513
514 typedef struct if_rxsd {
515 caddr_t *ifsd_cl;
516 iflib_fl_t ifsd_fl;
517 } *if_rxsd_t;
518
519 /*
520 * Only allow a single packet to take up most 1/nth of the tx ring
521 */
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA ((bus_addr_t)-1)
524
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
526
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
531
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
536
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
539
540 /* Our boot-time initialization hook */
541 static int iflib_module_event_handler(module_t, int, void *);
542
543 static moduledata_t iflib_moduledata = {
544 "iflib",
545 iflib_module_event_handler,
546 NULL
547 };
548
549 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
550 MODULE_VERSION(iflib, 1);
551
552 MODULE_DEPEND(iflib, pci, 1, 1, 1);
553 MODULE_DEPEND(iflib, ether, 1, 1, 1);
554
555 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
556 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
557
558 #ifndef IFLIB_DEBUG_COUNTERS
559 #ifdef INVARIANTS
560 #define IFLIB_DEBUG_COUNTERS 1
561 #else
562 #define IFLIB_DEBUG_COUNTERS 0
563 #endif /* !INVARIANTS */
564 #endif
565
566 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
567 "iflib driver parameters");
568
569 static SYSCTL_NODE(_debug_fail_point, OID_AUTO, iflib,
570 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "iflib fail points");
571
572 static char iflib_register_fail_device[32];
573 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, register_device,
574 CTLFLAG_RW | CTLFLAG_MPSAFE,
575 iflib_register_fail_device, sizeof(iflib_register_fail_device),
576 "device name eligible for registration fail points");
577
578 static char iflib_admin_task_fail_device[32];
579 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, admin_task_device,
580 CTLFLAG_RW | CTLFLAG_MPSAFE,
581 iflib_admin_task_fail_device, sizeof(iflib_admin_task_fail_device),
582 "device name eligible for admin task fail points");
583
584 /*
585 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
586 */
587 static int iflib_min_tx_latency = 0;
588 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
589 &iflib_min_tx_latency, 0,
590 "minimize transmit latency at the possible expense of throughput");
591 static int iflib_no_tx_batch = 0;
592 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
593 &iflib_no_tx_batch, 0,
594 "minimize transmit latency at the possible expense of throughput");
595 static int iflib_timer_default = 1000;
596 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
597 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
598 /*
599 * Consecutive timer periods a TX queue must stay frozen - see
600 * iflib_timer(), which defines that state - before the hardware is
601 * asked whether it has completions pending. Four periods is roughly
602 * two seconds with the default timer interval: a healthy queue on
603 * hardware that coalesces completion reports (e.g. 8254x,
604 * TXDCTL.WTHRESH) stays frozen for at most two (measured on 82541PI),
605 * a wedged one until it is reset.
606 */
607 static int iflib_tx_watchdog_periods = 4;
608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_watchdog_periods, CTLFLAG_RWTUN,
609 &iflib_tx_watchdog_periods, 0,
610 "consecutive frozen timer periods before a TX queue is checked for "
611 "a hang (0 disables the check)");
612
613
614 #if IFLIB_DEBUG_COUNTERS
615
616 static int iflib_tx_seen;
617 static int iflib_tx_sent;
618 static int iflib_tx_encap;
619 static int iflib_rx_allocs;
620 static int iflib_fl_refills;
621 static int iflib_fl_refills_large;
622 static int iflib_tx_frees;
623
624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0,
625 "# TX mbufs seen");
626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0,
627 "# TX mbufs sent");
628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0,
629 "# TX mbufs encapped");
630 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0,
631 "# TX frees");
632 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0,
633 "# RX allocations");
634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0,
635 "# refills");
636 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
637 &iflib_fl_refills_large, 0, "# large refills");
638
639 static int iflib_txq_drain_flushing;
640 static int iflib_txq_drain_oactive;
641 static int iflib_txq_drain_notready;
642
643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
644 &iflib_txq_drain_flushing, 0, "# drain flushes");
645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
646 &iflib_txq_drain_oactive, 0, "# drain oactives");
647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
648 &iflib_txq_drain_notready, 0, "# drain notready");
649
650 static int iflib_encap_load_mbuf_fail;
651 static int iflib_encap_pad_mbuf_fail;
652 static int iflib_encap_txq_avail_fail;
653 static int iflib_encap_txd_encap_fail;
654
655 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
656 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
657 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
658 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
659 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
660 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
661 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
662 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
663
664 static int iflib_task_fn_rxs;
665 static int iflib_rx_intr_enables;
666 static int iflib_fast_intrs;
667 static int iflib_rx_unavail;
668 static int iflib_rx_ctx_inactive;
669 static int iflib_rx_if_input;
670 static int iflib_rxd_flush;
671
672 static int iflib_verbose_debug;
673
674 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0,
675 "# task_fn_rx calls");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
677 &iflib_rx_intr_enables, 0, "# RX intr enables");
678 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0,
679 "# fast_intr calls");
680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0,
681 "# times rxeof called with no available data");
682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
683 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input,
685 0, "# times rxeof called if_input");
686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0,
687 "# times rxd_flush called");
688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
689 &iflib_verbose_debug, 0, "enable verbose debugging");
690
691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
692 static void
iflib_debug_reset(void)693 iflib_debug_reset(void)
694 {
695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
697 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
698 iflib_txq_drain_notready =
699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
702 iflib_rx_unavail =
703 iflib_rx_ctx_inactive = iflib_rx_if_input =
704 iflib_rxd_flush = 0;
705 }
706
707 #else
708 #define DBG_COUNTER_INC(name)
iflib_debug_reset(void)709 static void iflib_debug_reset(void) {}
710 #endif
711
712 #define IFLIB_DEBUG 0
713
714 static void iflib_tx_structures_free(if_ctx_t ctx);
715 static void iflib_rx_structures_free(if_ctx_t ctx);
716 static int iflib_queues_alloc(if_ctx_t ctx);
717 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
718 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
719 static int iflib_qset_structures_setup(if_ctx_t ctx);
720 static int iflib_msix_init(if_ctx_t ctx);
721 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
722 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
723 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
724 #ifdef ALTQ
725 static void iflib_altq_if_start(if_t ifp);
726 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
727 #endif
728 static void iflib_register(if_ctx_t);
729 static void iflib_deregister(if_ctx_t);
730 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
731 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
732 static void iflib_init_locked(if_ctx_t ctx);
733 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
734 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
735 static void iflib_ifmp_purge(iflib_txq_t txq);
736 static void _iflib_pre_assert(if_softc_ctx_t scctx);
737 static void iflib_stop(if_ctx_t ctx);
738 static void iflib_if_init_locked(if_ctx_t ctx);
739 static void iflib_free_intr_mem(if_ctx_t ctx);
740 #ifndef __NO_STRICT_ALIGNMENT
741 static struct mbuf *iflib_fixup_rx(struct mbuf *m);
742 #endif
743 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq,
744 struct mbuf **m_defer);
745 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq);
746
747 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
748 SLIST_HEAD_INITIALIZER(cpu_offsets);
749 struct cpu_offset {
750 SLIST_ENTRY(cpu_offset) entries;
751 cpuset_t set;
752 unsigned int refcount;
753 uint16_t next_cpuid;
754 };
755 static struct mtx cpu_offset_mtx;
756 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
757 MTX_DEF);
758
759 DEBUGNET_DEFINE(iflib);
760
761 static int
iflib_num_rx_descs(if_ctx_t ctx)762 iflib_num_rx_descs(if_ctx_t ctx)
763 {
764 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
765 if_shared_ctx_t sctx = ctx->ifc_sctx;
766 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
767
768 return (scctx->isc_nrxd[first_rxq]);
769 }
770
771 static int
iflib_num_tx_descs(if_ctx_t ctx)772 iflib_num_tx_descs(if_ctx_t ctx)
773 {
774 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
775 if_shared_ctx_t sctx = ctx->ifc_sctx;
776 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
777
778 return (scctx->isc_ntxd[first_txq]);
779 }
780
781 #ifdef DEV_NETMAP
782 #include <sys/selinfo.h>
783 #include <net/netmap.h>
784 #include <dev/netmap/netmap_kern.h>
785
786 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
787
788 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
789 static void iflib_netmap_timer(void *arg);
790
791 /*
792 * device-specific sysctl variables:
793 *
794 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
795 * During regular operations the CRC is stripped, but on some
796 * hardware reception of frames not multiple of 64 is slower,
797 * so using crcstrip=0 helps in benchmarks.
798 *
799 * iflib_rx_miss, iflib_rx_miss_bufs:
800 * count packets that might be missed due to lost interrupts.
801 */
802 SYSCTL_DECL(_dev_netmap);
803 /*
804 * The xl driver by default strips CRCs and we do not override it.
805 */
806
807 int iflib_crcstrip = 1;
808 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
809 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
810
811 int iflib_rx_miss, iflib_rx_miss_bufs;
812 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
813 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
814 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
815 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
816
817 /*
818 * Register/unregister. We are already under netmap lock.
819 * Only called on the first register or the last unregister.
820 */
821 static int
iflib_netmap_register(struct netmap_adapter * na,int onoff)822 iflib_netmap_register(struct netmap_adapter *na, int onoff)
823 {
824 if_t ifp = na->ifp;
825 if_ctx_t ctx = if_getsoftc(ifp);
826 int status;
827
828 CTX_LOCK(ctx);
829 if (!CTX_IS_VF(ctx))
830 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
831
832 iflib_stop(ctx);
833
834 /*
835 * Enable (or disable) netmap flags, and intercept (or restore)
836 * ifp->if_transmit. This is done once the device has been stopped
837 * to prevent race conditions. Also, this must be done after
838 * calling netmap_disable_all_rings() and before calling
839 * netmap_enable_all_rings(), so that these two functions see the
840 * updated state of the NAF_NETMAP_ON bit.
841 */
842 if (onoff) {
843 nm_set_native_flags(na);
844 } else {
845 nm_clear_native_flags(na);
846 }
847
848 iflib_init_locked(ctx);
849 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
850 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1;
851 if (status)
852 nm_clear_native_flags(na);
853 CTX_UNLOCK(ctx);
854 return (status);
855 }
856
857 static int
iflib_netmap_config(struct netmap_adapter * na,struct nm_config_info * info)858 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
859 {
860 if_t ifp = na->ifp;
861 if_ctx_t ctx = if_getsoftc(ifp);
862 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
863 iflib_fl_t fl = &rxq->ifr_fl[0];
864
865 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
866 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
867 info->num_tx_descs = iflib_num_tx_descs(ctx);
868 info->num_rx_descs = iflib_num_rx_descs(ctx);
869 info->rx_buf_maxsize = fl->ifl_buf_size;
870 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
871 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
872 info->num_rx_descs, info->rx_buf_maxsize);
873
874 return (0);
875 }
876
877 static int
netmap_fl_refill(iflib_rxq_t rxq,struct netmap_kring * kring,bool init)878 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
879 {
880 struct netmap_adapter *na = kring->na;
881 u_int const lim = kring->nkr_num_slots - 1;
882 struct netmap_ring *ring = kring->ring;
883 bus_dmamap_t *map;
884 struct if_rxd_update iru;
885 if_ctx_t ctx = rxq->ifr_ctx;
886 iflib_fl_t fl = &rxq->ifr_fl[0];
887 u_int nic_i_first, nic_i;
888 u_int nm_i;
889 int i, n;
890 #if IFLIB_DEBUG_COUNTERS
891 int rf_count = 0;
892 #endif
893
894 /*
895 * This function is used both at initialization and in rxsync.
896 * At initialization we need to prepare (with isc_rxd_refill())
897 * all the netmap buffers currently owned by the kernel, in
898 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
899 * (except for kring->nkr_hwofs). These may be less than
900 * kring->nkr_num_slots if netmap_reset() was called while
901 * an application using the kring that still owned some
902 * buffers.
903 * At rxsync time, both indexes point to the next buffer to be
904 * refilled.
905 * In any case we publish (with isc_rxd_flush()) up to
906 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
907 * pointer to overrun the head/cons pointer, although this is
908 * not necessary for some NICs (e.g. vmx).
909 */
910 if (__predict_false(init)) {
911 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
912 } else {
913 n = kring->rhead - kring->nr_hwcur;
914 if (n == 0)
915 return (0); /* Nothing to do. */
916 if (n < 0)
917 n += kring->nkr_num_slots;
918 }
919
920 iru_init(&iru, rxq, 0 /* flid */);
921 map = fl->ifl_sds.ifsd_map;
922 nic_i = fl->ifl_pidx;
923 nm_i = netmap_idx_n2k(kring, nic_i);
924 if (__predict_false(init)) {
925 /*
926 * On init/reset, nic_i must be 0, and we must
927 * start to refill from hwtail (see netmap_reset()).
928 */
929 MPASS(nic_i == 0);
930 MPASS(nm_i == kring->nr_hwtail);
931 } else
932 MPASS(nm_i == kring->nr_hwcur);
933 DBG_COUNTER_INC(fl_refills);
934 while (n > 0) {
935 #if IFLIB_DEBUG_COUNTERS
936 if (++rf_count == 9)
937 DBG_COUNTER_INC(fl_refills_large);
938 #endif
939 nic_i_first = nic_i;
940 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
941 struct netmap_slot *slot = &ring->slot[nm_i];
942 uint64_t paddr;
943 void *addr = PNMB(na, slot, &paddr);
944
945 MPASS(i < IFLIB_MAX_RX_REFRESH);
946
947 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
948 return (netmap_ring_reinit(kring));
949
950 fl->ifl_bus_addrs[i] = paddr +
951 nm_get_offset(kring, slot);
952 fl->ifl_rxd_idxs[i] = nic_i;
953
954 if (__predict_false(init)) {
955 netmap_load_map(na, fl->ifl_buf_tag,
956 map[nic_i], addr);
957 } else if (slot->flags & NS_BUF_CHANGED) {
958 /* buffer has changed, reload map */
959 netmap_reload_map(na, fl->ifl_buf_tag,
960 map[nic_i], addr);
961 }
962 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
963 BUS_DMASYNC_PREREAD);
964 slot->flags &= ~NS_BUF_CHANGED;
965
966 nm_i = nm_next(nm_i, lim);
967 nic_i = nm_next(nic_i, lim);
968 }
969
970 iru.iru_pidx = nic_i_first;
971 iru.iru_count = i;
972 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
973 }
974 fl->ifl_pidx = nic_i;
975 /*
976 * At the end of the loop we must have refilled everything
977 * we could possibly refill.
978 */
979 MPASS(nm_i == kring->rhead);
980 kring->nr_hwcur = nm_i;
981
982 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
983 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
984 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
985 nm_prev(nic_i, lim));
986 DBG_COUNTER_INC(rxd_flush);
987
988 return (0);
989 }
990
991 #define NETMAP_TX_TIMER_US 90
992
993 /*
994 * Reconcile kernel and user view of the transmit ring.
995 *
996 * All information is in the kring.
997 * Userspace wants to send packets up to the one before kring->rhead,
998 * kernel knows kring->nr_hwcur is the first unsent packet.
999 *
1000 * Here we push packets out (as many as possible), and possibly
1001 * reclaim buffers from previously completed transmission.
1002 *
1003 * The caller (netmap) guarantees that there is only one instance
1004 * running at any time. Any interference with other driver
1005 * methods should be handled by the individual drivers.
1006 */
1007 static int
iflib_netmap_txsync(struct netmap_kring * kring,int flags)1008 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
1009 {
1010 struct netmap_adapter *na = kring->na;
1011 if_t ifp = na->ifp;
1012 struct netmap_ring *ring = kring->ring;
1013 u_int nm_i; /* index into the netmap kring */
1014 u_int nic_i; /* index into the NIC ring */
1015 u_int const lim = kring->nkr_num_slots - 1;
1016 u_int const head = kring->rhead;
1017 struct if_pkt_info pi;
1018 int tx_pkts = 0, tx_bytes = 0;
1019
1020 /*
1021 * interrupts on every tx packet are expensive so request
1022 * them every half ring, or where NS_REPORT is set
1023 */
1024 u_int report_frequency = kring->nkr_num_slots >> 1;
1025 /* device-specific */
1026 if_ctx_t ctx = if_getsoftc(ifp);
1027 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1028
1029 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1030 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1031
1032 /*
1033 * First part: process new packets to send.
1034 * nm_i is the current index in the netmap kring,
1035 * nic_i is the corresponding index in the NIC ring.
1036 *
1037 * If we have packets to send (nm_i != head)
1038 * iterate over the netmap ring, fetch length and update
1039 * the corresponding slot in the NIC ring. Some drivers also
1040 * need to update the buffer's physical address in the NIC slot
1041 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1042 *
1043 * The netmap_reload_map() calls is especially expensive,
1044 * even when (as in this case) the tag is 0, so do only
1045 * when the buffer has actually changed.
1046 *
1047 * If possible do not set the report/intr bit on all slots,
1048 * but only a few times per ring or when NS_REPORT is set.
1049 *
1050 * Finally, on 10G and faster drivers, it might be useful
1051 * to prefetch the next slot and txr entry.
1052 */
1053
1054 nm_i = kring->nr_hwcur;
1055 if (nm_i != head) { /* we have new packets to send */
1056 uint32_t pkt_len = 0, seg_idx = 0;
1057 int nic_i_start = -1, flags = 0;
1058 memset(&pi, 0, sizeof(pi));
1059 pi.ipi_segs = txq->ift_segs;
1060 pi.ipi_qsidx = kring->ring_id;
1061 nic_i = netmap_idx_k2n(kring, nm_i);
1062
1063 __builtin_prefetch(&ring->slot[nm_i]);
1064 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1065 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1066
1067 while (nm_i != head) {
1068 struct netmap_slot *slot = &ring->slot[nm_i];
1069 uint64_t offset = nm_get_offset(kring, slot);
1070 u_int len = slot->len;
1071 uint64_t paddr;
1072 void *addr = PNMB(na, slot, &paddr);
1073
1074 flags |= (slot->flags & NS_REPORT ||
1075 nic_i == 0 || nic_i == report_frequency) ?
1076 IPI_TX_INTR : 0;
1077
1078 /*
1079 * If this is the first packet fragment, save the
1080 * index of the first NIC slot for later.
1081 */
1082 if (nic_i_start < 0)
1083 nic_i_start = nic_i;
1084
1085 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1086 pi.ipi_segs[seg_idx].ds_len = len;
1087 if (len) {
1088 pkt_len += len;
1089 seg_idx++;
1090 }
1091
1092 if (!(slot->flags & NS_MOREFRAG)) {
1093 pi.ipi_len = pkt_len;
1094 pi.ipi_nsegs = seg_idx;
1095 pi.ipi_pidx = nic_i_start;
1096 pi.ipi_ndescs = 0;
1097 pi.ipi_flags = flags;
1098
1099 /* Prepare the NIC TX ring. */
1100 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1101 DBG_COUNTER_INC(tx_encap);
1102
1103 /* Update transmit counters */
1104 tx_bytes += pi.ipi_len;
1105 tx_pkts++;
1106
1107 /* Reinit per-packet info for the next one. */
1108 flags = seg_idx = pkt_len = 0;
1109 nic_i_start = -1;
1110 }
1111
1112 /* prefetch for next round */
1113 __builtin_prefetch(&ring->slot[nm_i + 1]);
1114 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1115 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1116
1117 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1118
1119 if (slot->flags & NS_BUF_CHANGED) {
1120 /* buffer has changed, reload map */
1121 netmap_reload_map(na, txq->ift_buf_tag,
1122 txq->ift_sds.ifsd_map[nic_i], addr);
1123 }
1124 /* make sure changes to the buffer are synced */
1125 bus_dmamap_sync(txq->ift_buf_tag,
1126 txq->ift_sds.ifsd_map[nic_i],
1127 BUS_DMASYNC_PREWRITE);
1128
1129 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1130 nm_i = nm_next(nm_i, lim);
1131 nic_i = nm_next(nic_i, lim);
1132 }
1133 kring->nr_hwcur = nm_i;
1134
1135 /* synchronize the NIC ring */
1136 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1137 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1138
1139 /* (re)start the tx unit up to slot nic_i (excluded) */
1140 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1141 }
1142
1143 /*
1144 * Second part: reclaim buffers for completed transmissions.
1145 *
1146 * If there are unclaimed buffers, attempt to reclaim them.
1147 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1148 * trigger a per-tx-queue timer to try again later.
1149 */
1150 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1151 if (iflib_tx_credits_update(ctx, txq)) {
1152 /* some tx completed, increment avail */
1153 nic_i = txq->ift_cidx_processed;
1154 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1155 }
1156 }
1157
1158 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1159 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1160 callout_reset_sbt_on(&txq->ift_netmap_timer,
1161 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1162 iflib_netmap_timer, txq,
1163 txq->ift_netmap_timer.c_cpu, 0);
1164 }
1165
1166 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes);
1167 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts);
1168
1169 return (0);
1170 }
1171
1172 /*
1173 * Reconcile kernel and user view of the receive ring.
1174 * Same as for the txsync, this routine must be efficient.
1175 * The caller guarantees a single invocations, but races against
1176 * the rest of the driver should be handled here.
1177 *
1178 * On call, kring->rhead is the first packet that userspace wants
1179 * to keep, and kring->rcur is the wakeup point.
1180 * The kernel has previously reported packets up to kring->rtail.
1181 *
1182 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1183 * of whether or not we received an interrupt.
1184 */
1185 static int
iflib_netmap_rxsync(struct netmap_kring * kring,int flags)1186 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1187 {
1188 struct netmap_adapter *na = kring->na;
1189 struct netmap_ring *ring = kring->ring;
1190 if_t ifp = na->ifp;
1191 uint32_t nm_i; /* index into the netmap ring */
1192 uint32_t nic_i; /* index into the NIC ring */
1193 u_int n;
1194 u_int const lim = kring->nkr_num_slots - 1;
1195 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1196 int i = 0, rx_bytes = 0, rx_pkts = 0;
1197
1198 if_ctx_t ctx = if_getsoftc(ifp);
1199 if_shared_ctx_t sctx = ctx->ifc_sctx;
1200 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1201 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1202 iflib_fl_t fl = &rxq->ifr_fl[0];
1203 struct if_rxd_info ri;
1204 qidx_t *cidxp;
1205
1206 /*
1207 * netmap only uses free list 0, to avoid out of order consumption
1208 * of receive buffers
1209 */
1210
1211 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1212 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1213
1214 /*
1215 * First part: import newly received packets.
1216 *
1217 * nm_i is the index of the next free slot in the netmap ring,
1218 * nic_i is the index of the next received packet in the NIC ring
1219 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1220 * differ in case if_init() has been called while
1221 * in netmap mode. For the receive ring we have
1222 *
1223 * nic_i = fl->ifl_cidx;
1224 * nm_i = kring->nr_hwtail (previous)
1225 * and
1226 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1227 *
1228 * fl->ifl_cidx is set to 0 on a ring reinit
1229 */
1230 if (netmap_no_pendintr || force_update) {
1231 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1232 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1233 int crclen = iflib_crcstrip ? 0 : 4;
1234 int error, avail;
1235
1236 /*
1237 * For the free list consumer index, we use the same
1238 * logic as in iflib_rxeof().
1239 */
1240 if (have_rxcq)
1241 cidxp = &rxq->ifr_cq_cidx;
1242 else
1243 cidxp = &fl->ifl_cidx;
1244 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1245 rxq->ifr_id, *cidxp, USHRT_MAX);
1246
1247 nic_i = fl->ifl_cidx;
1248 nm_i = netmap_idx_n2k(kring, nic_i);
1249 MPASS(nm_i == kring->nr_hwtail);
1250 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1251 memset(&ri, 0, sizeof(ri));
1252 ri.iri_frags = rxq->ifr_frags;
1253 ri.iri_qsidx = kring->ring_id;
1254 ri.iri_ifp = ctx->ifc_ifp;
1255 ri.iri_cidx = *cidxp;
1256
1257 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1258 for (i = 0; i < ri.iri_nfrags; i++) {
1259 if (error) {
1260 ring->slot[nm_i].len = 0;
1261 ring->slot[nm_i].flags = 0;
1262 } else {
1263 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1264 if (i == (ri.iri_nfrags - 1)) {
1265 ring->slot[nm_i].len -= crclen;
1266 ring->slot[nm_i].flags = 0;
1267
1268 /* Update receive counters */
1269 rx_bytes += ri.iri_len;
1270 rx_pkts++;
1271 } else
1272 ring->slot[nm_i].flags = NS_MOREFRAG;
1273 }
1274
1275 bus_dmamap_sync(fl->ifl_buf_tag,
1276 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1277 nm_i = nm_next(nm_i, lim);
1278 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1279 }
1280
1281 if (have_rxcq) {
1282 *cidxp = ri.iri_cidx;
1283 while (*cidxp >= scctx->isc_nrxd[0])
1284 *cidxp -= scctx->isc_nrxd[0];
1285 }
1286
1287 }
1288 if (n) { /* update the state variables */
1289 if (netmap_no_pendintr && !force_update) {
1290 /* diagnostics */
1291 iflib_rx_miss++;
1292 iflib_rx_miss_bufs += n;
1293 }
1294 kring->nr_hwtail = nm_i;
1295 }
1296 kring->nr_kflags &= ~NKR_PENDINTR;
1297 }
1298 /*
1299 * Second part: skip past packets that userspace has released.
1300 * (kring->nr_hwcur to head excluded),
1301 * and make the buffers available for reception.
1302 * As usual nm_i is the index in the netmap ring,
1303 * nic_i is the index in the NIC ring, and
1304 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1305 */
1306 netmap_fl_refill(rxq, kring, false);
1307
1308 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
1309 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
1310
1311 return (0);
1312 }
1313
1314 static void
iflib_netmap_intr(struct netmap_adapter * na,int onoff)1315 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1316 {
1317 if_ctx_t ctx = if_getsoftc(na->ifp);
1318
1319 CTX_LOCK(ctx);
1320 if (onoff) {
1321 IFDI_INTR_ENABLE(ctx);
1322 } else {
1323 IFDI_INTR_DISABLE(ctx);
1324 }
1325 CTX_UNLOCK(ctx);
1326 }
1327
1328 static int
iflib_netmap_attach(if_ctx_t ctx)1329 iflib_netmap_attach(if_ctx_t ctx)
1330 {
1331 struct netmap_adapter na;
1332
1333 bzero(&na, sizeof(na));
1334
1335 na.ifp = ctx->ifc_ifp;
1336 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1337 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1338 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1339
1340 na.num_tx_desc = iflib_num_tx_descs(ctx);
1341 na.num_rx_desc = iflib_num_rx_descs(ctx);
1342 na.nm_txsync = iflib_netmap_txsync;
1343 na.nm_rxsync = iflib_netmap_rxsync;
1344 na.nm_register = iflib_netmap_register;
1345 na.nm_intr = iflib_netmap_intr;
1346 na.nm_config = iflib_netmap_config;
1347 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1348 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1349 return (netmap_attach(&na));
1350 }
1351
1352 static int
iflib_netmap_txq_init(if_ctx_t ctx,iflib_txq_t txq)1353 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1354 {
1355 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1356 struct netmap_slot *slot;
1357
1358 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1359 if (slot == NULL)
1360 return (0);
1361 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1362 /*
1363 * In netmap mode, set the map for the packet buffer.
1364 * NOTE: Some drivers (not this one) also need to set
1365 * the physical buffer address in the NIC ring.
1366 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1367 * netmap slot index, si
1368 */
1369 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1370 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1371 NMB(na, slot + si));
1372 }
1373 return (1);
1374 }
1375
1376 static int
iflib_netmap_rxq_init(if_ctx_t ctx,iflib_rxq_t rxq)1377 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1378 {
1379 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1380 struct netmap_kring *kring;
1381 struct netmap_slot *slot;
1382
1383 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1384 if (slot == NULL)
1385 return (0);
1386 kring = na->rx_rings[rxq->ifr_id];
1387 netmap_fl_refill(rxq, kring, true);
1388 return (1);
1389 }
1390
1391 static void
iflib_netmap_timer(void * arg)1392 iflib_netmap_timer(void *arg)
1393 {
1394 iflib_txq_t txq = arg;
1395 if_ctx_t ctx = txq->ift_ctx;
1396
1397 /*
1398 * Wake up the netmap application, to give it a chance to
1399 * call txsync and reclaim more completed TX buffers.
1400 */
1401 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1402 }
1403
1404 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1405
1406 #else
1407 #define iflib_netmap_txq_init(ctx, txq) (0)
1408 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1409 #define iflib_netmap_detach(ifp)
1410 #define netmap_enable_all_rings(ifp)
1411 #define netmap_disable_all_rings(ifp)
1412
1413 #define iflib_netmap_attach(ctx) (0)
1414 #define netmap_rx_irq(ifp, qid, budget) (0)
1415 #endif
1416
1417 #if defined(__i386__) || defined(__amd64__)
1418 static __inline void
prefetch(void * x)1419 prefetch(void *x)
1420 {
1421 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1422 }
1423
1424 static __inline void
prefetch2cachelines(void * x)1425 prefetch2cachelines(void *x)
1426 {
1427 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1428 #if (CACHE_LINE_SIZE < 128)
1429 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long)))));
1430 #endif
1431 }
1432 #else
1433 static __inline void
prefetch(void * x)1434 prefetch(void *x)
1435 {
1436 }
1437
1438 static __inline void
prefetch2cachelines(void * x)1439 prefetch2cachelines(void *x)
1440 {
1441 }
1442 #endif
1443
1444 static void
iru_init(if_rxd_update_t iru,iflib_rxq_t rxq,uint8_t flid)1445 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1446 {
1447 iflib_fl_t fl;
1448
1449 fl = &rxq->ifr_fl[flid];
1450 iru->iru_paddrs = fl->ifl_bus_addrs;
1451 iru->iru_idxs = fl->ifl_rxd_idxs;
1452 iru->iru_qsidx = rxq->ifr_id;
1453 iru->iru_buf_size = fl->ifl_buf_size;
1454 iru->iru_flidx = fl->ifl_id;
1455 }
1456
1457 static void
_iflib_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int err)1458 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1459 {
1460 if (err)
1461 return;
1462 *(bus_addr_t *) arg = segs[0].ds_addr;
1463 }
1464
1465 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1466 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1467 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1468
1469 int
iflib_dma_alloc_align(if_ctx_t ctx,int size,int align,iflib_dma_info_t dma,int mapflags)1470 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1471 {
1472 int err;
1473 device_t dev = ctx->ifc_dev;
1474 bus_addr_t lowaddr;
1475
1476 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1477
1478 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1479 align, 0, /* alignment, bounds */
1480 lowaddr, /* lowaddr */
1481 BUS_SPACE_MAXADDR, /* highaddr */
1482 NULL, NULL, /* filter, filterarg */
1483 size, /* maxsize */
1484 1, /* nsegments */
1485 size, /* maxsegsize */
1486 BUS_DMA_ALLOCNOW, /* flags */
1487 NULL, /* lockfunc */
1488 NULL, /* lockarg */
1489 &dma->idi_tag);
1490 if (err) {
1491 device_printf(dev,
1492 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n",
1493 __func__, err, size, align);
1494 goto fail_0;
1495 }
1496
1497 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr,
1498 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1499 if (err) {
1500 device_printf(dev,
1501 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1502 __func__, (uintmax_t)size, err);
1503 goto fail_1;
1504 }
1505
1506 dma->idi_paddr = IF_BAD_DMA;
1507 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1508 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1509 if (err || dma->idi_paddr == IF_BAD_DMA) {
1510 device_printf(dev,
1511 "%s: bus_dmamap_load failed: %d\n",
1512 __func__, err);
1513 goto fail_2;
1514 }
1515
1516 dma->idi_size = size;
1517 return (0);
1518
1519 fail_2:
1520 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1521 fail_1:
1522 bus_dma_tag_destroy(dma->idi_tag);
1523 fail_0:
1524 dma->idi_tag = NULL;
1525
1526 return (err);
1527 }
1528
1529 int
iflib_dma_alloc(if_ctx_t ctx,int size,iflib_dma_info_t dma,int mapflags)1530 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1531 {
1532 if_shared_ctx_t sctx = ctx->ifc_sctx;
1533
1534 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1535
1536 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1537 }
1538
1539 int
iflib_dma_alloc_multi(if_ctx_t ctx,int * sizes,iflib_dma_info_t * dmalist,int mapflags,int count)1540 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1541 {
1542 int i, err;
1543 iflib_dma_info_t *dmaiter;
1544
1545 dmaiter = dmalist;
1546 for (i = 0; i < count; i++, dmaiter++) {
1547 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1548 break;
1549 }
1550 if (err)
1551 iflib_dma_free_multi(dmalist, i);
1552 return (err);
1553 }
1554
1555 void
iflib_dma_free(iflib_dma_info_t dma)1556 iflib_dma_free(iflib_dma_info_t dma)
1557 {
1558 if (dma->idi_tag == NULL)
1559 return;
1560 if (dma->idi_paddr != IF_BAD_DMA) {
1561 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1562 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1564 dma->idi_paddr = IF_BAD_DMA;
1565 }
1566 if (dma->idi_vaddr != NULL) {
1567 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1568 dma->idi_vaddr = NULL;
1569 }
1570 bus_dma_tag_destroy(dma->idi_tag);
1571 dma->idi_tag = NULL;
1572 }
1573
1574 void
iflib_dma_free_multi(iflib_dma_info_t * dmalist,int count)1575 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1576 {
1577 int i;
1578 iflib_dma_info_t *dmaiter = dmalist;
1579
1580 for (i = 0; i < count; i++, dmaiter++)
1581 iflib_dma_free(*dmaiter);
1582 }
1583
1584 static int
iflib_fast_intr(void * arg)1585 iflib_fast_intr(void *arg)
1586 {
1587 iflib_filter_info_t info = arg;
1588 struct grouptask *gtask = info->ifi_task;
1589 int result;
1590
1591 DBG_COUNTER_INC(fast_intrs);
1592 if (info->ifi_filter != NULL) {
1593 result = info->ifi_filter(info->ifi_filter_arg);
1594 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1595 return (result);
1596 }
1597
1598 GROUPTASK_ENQUEUE(gtask);
1599 return (FILTER_HANDLED);
1600 }
1601
1602 static int
iflib_fast_intr_rxtx(void * arg)1603 iflib_fast_intr_rxtx(void *arg)
1604 {
1605 iflib_filter_info_t info = arg;
1606 struct grouptask *gtask = info->ifi_task;
1607 if_ctx_t ctx;
1608 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1609 iflib_txq_t txq;
1610 void *sc;
1611 int i, cidx, result;
1612 qidx_t txqid;
1613 bool intr_enable, intr_legacy;
1614
1615 DBG_COUNTER_INC(fast_intrs);
1616 if (info->ifi_filter != NULL) {
1617 result = info->ifi_filter(info->ifi_filter_arg);
1618 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1619 return (result);
1620 }
1621
1622 ctx = rxq->ifr_ctx;
1623 sc = ctx->ifc_softc;
1624 intr_enable = false;
1625 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1626 MPASS(rxq->ifr_ntxqirq);
1627 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1628 txqid = rxq->ifr_txqid[i];
1629 txq = &ctx->ifc_txqs[txqid];
1630 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1631 BUS_DMASYNC_POSTREAD);
1632 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1633 if (intr_legacy)
1634 intr_enable = true;
1635 else
1636 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1637 continue;
1638 }
1639 GROUPTASK_ENQUEUE(&txq->ift_task);
1640 }
1641 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1642 cidx = rxq->ifr_cq_cidx;
1643 else
1644 cidx = rxq->ifr_fl[0].ifl_cidx;
1645 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1646 GROUPTASK_ENQUEUE(gtask);
1647 else {
1648 if (intr_legacy)
1649 intr_enable = true;
1650 else
1651 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1652 DBG_COUNTER_INC(rx_intr_enables);
1653 }
1654 if (intr_enable)
1655 IFDI_INTR_ENABLE(ctx);
1656 return (FILTER_HANDLED);
1657 }
1658
1659 static int
iflib_fast_intr_ctx(void * arg)1660 iflib_fast_intr_ctx(void *arg)
1661 {
1662 iflib_filter_info_t info = arg;
1663 if_ctx_t ctx = info->ifi_ctx;
1664 int result;
1665
1666 DBG_COUNTER_INC(fast_intrs);
1667 if (info->ifi_filter != NULL) {
1668 result = info->ifi_filter(info->ifi_filter_arg);
1669 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1670 return (result);
1671 }
1672
1673 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task);
1674 return (FILTER_HANDLED);
1675 }
1676
1677 static int
_iflib_irq_alloc(if_ctx_t ctx,if_irq_t irq,int rid,driver_filter_t filter,driver_intr_t handler,void * arg,const char * name)1678 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1679 driver_filter_t filter, driver_intr_t handler, void *arg,
1680 const char *name)
1681 {
1682 struct resource *res;
1683 void *tag = NULL;
1684 device_t dev = ctx->ifc_dev;
1685 int flags, i, rc;
1686
1687 flags = RF_ACTIVE;
1688 if (ctx->ifc_flags & IFC_LEGACY)
1689 flags |= RF_SHAREABLE;
1690 MPASS(rid < 512);
1691 i = rid;
1692 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1693 if (res == NULL) {
1694 device_printf(dev,
1695 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1696 return (ENOMEM);
1697 }
1698 irq->ii_res = res;
1699 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1700 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1701 filter, handler, arg, &tag);
1702 if (rc != 0) {
1703 device_printf(dev,
1704 "failed to setup interrupt for rid %d, name %s: %d\n",
1705 rid, name ? name : "unknown", rc);
1706 return (rc);
1707 } else if (name)
1708 bus_describe_intr(dev, res, tag, "%s", name);
1709
1710 irq->ii_tag = tag;
1711 return (0);
1712 }
1713
1714 /*********************************************************************
1715 *
1716 * Allocate DMA resources for TX buffers as well as memory for the TX
1717 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1718 * iflib_sw_tx_desc_array structure, storing all the information that
1719 * is needed to transmit a packet on the wire. This is called only
1720 * once at attach, setup is done every reset.
1721 *
1722 **********************************************************************/
1723 static int
iflib_txsd_alloc(iflib_txq_t txq)1724 iflib_txsd_alloc(iflib_txq_t txq)
1725 {
1726 if_ctx_t ctx = txq->ift_ctx;
1727 if_shared_ctx_t sctx = ctx->ifc_sctx;
1728 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1729 device_t dev = ctx->ifc_dev;
1730 bus_size_t tsomaxsize;
1731 bus_addr_t lowaddr;
1732 int err, nsegments, ntsosegments;
1733 bool tso;
1734
1735 nsegments = scctx->isc_tx_nsegments;
1736 ntsosegments = scctx->isc_tx_tso_segments_max;
1737 tsomaxsize = scctx->isc_tx_tso_size_max;
1738 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1739 tsomaxsize += sizeof(struct ether_vlan_header);
1740 MPASS(scctx->isc_ntxd[0] > 0);
1741 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1742 MPASS(nsegments > 0);
1743 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1744 MPASS(ntsosegments > 0);
1745 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1746 }
1747
1748 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1749
1750 /*
1751 * Set up DMA tags for TX buffers.
1752 */
1753 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1754 1, 0, /* alignment, bounds */
1755 lowaddr, /* lowaddr */
1756 BUS_SPACE_MAXADDR, /* highaddr */
1757 NULL, NULL, /* filter, filterarg */
1758 sctx->isc_tx_maxsize, /* maxsize */
1759 nsegments, /* nsegments */
1760 sctx->isc_tx_maxsegsize, /* maxsegsize */
1761 0, /* flags */
1762 NULL, /* lockfunc */
1763 NULL, /* lockfuncarg */
1764 &txq->ift_buf_tag))) {
1765 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err);
1766 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1767 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1768 goto fail;
1769 }
1770 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1771 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1772 1, 0, /* alignment, bounds */
1773 lowaddr, /* lowaddr */
1774 BUS_SPACE_MAXADDR, /* highaddr */
1775 NULL, NULL, /* filter, filterarg */
1776 tsomaxsize, /* maxsize */
1777 ntsosegments, /* nsegments */
1778 sctx->isc_tso_maxsegsize, /* maxsegsize */
1779 0, /* flags */
1780 NULL, /* lockfunc */
1781 NULL, /* lockfuncarg */
1782 &txq->ift_tso_buf_tag))) {
1783 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1784 err);
1785 goto fail;
1786 }
1787
1788 /* Allocate memory for the TX mbuf map. */
1789 if (!(txq->ift_sds.ifsd_m =
1790 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1791 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1792 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1793 err = ENOMEM;
1794 goto fail;
1795 }
1796 if (ctx->ifc_sysctl_simple_tx) {
1797 if (!(txq->ift_sds.ifsd_m_defer =
1798 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1799 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1800 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1801 err = ENOMEM;
1802 goto fail;
1803 }
1804 }
1805 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer;
1806 /*
1807 * Create the DMA maps for TX buffers.
1808 */
1809 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1810 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1811 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1812 device_printf(dev,
1813 "Unable to allocate TX buffer DMA map memory\n");
1814 err = ENOMEM;
1815 goto fail;
1816 }
1817 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1818 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1819 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1820 device_printf(dev,
1821 "Unable to allocate TSO TX buffer map memory\n");
1822 err = ENOMEM;
1823 goto fail;
1824 }
1825 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1826 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1827 &txq->ift_sds.ifsd_map[i]);
1828 if (err != 0) {
1829 device_printf(dev, "Unable to create TX DMA map\n");
1830 goto fail;
1831 }
1832 if (!tso)
1833 continue;
1834 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1835 &txq->ift_sds.ifsd_tso_map[i]);
1836 if (err != 0) {
1837 device_printf(dev, "Unable to create TSO TX DMA map\n");
1838 goto fail;
1839 }
1840 }
1841 return (0);
1842 fail:
1843 /* We free all, it handles case where we are in the middle */
1844 iflib_tx_structures_free(ctx);
1845 return (err);
1846 }
1847
1848 static void
iflib_txsd_destroy(if_ctx_t ctx,iflib_txq_t txq,int i)1849 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1850 {
1851 bus_dmamap_t map;
1852
1853 if (txq->ift_sds.ifsd_map != NULL) {
1854 map = txq->ift_sds.ifsd_map[i];
1855 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1856 bus_dmamap_unload(txq->ift_buf_tag, map);
1857 bus_dmamap_destroy(txq->ift_buf_tag, map);
1858 txq->ift_sds.ifsd_map[i] = NULL;
1859 }
1860
1861 if (txq->ift_sds.ifsd_tso_map != NULL) {
1862 map = txq->ift_sds.ifsd_tso_map[i];
1863 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1864 BUS_DMASYNC_POSTWRITE);
1865 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1866 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1867 txq->ift_sds.ifsd_tso_map[i] = NULL;
1868 }
1869 }
1870
1871 static void
iflib_txq_destroy(iflib_txq_t txq)1872 iflib_txq_destroy(iflib_txq_t txq)
1873 {
1874 if_ctx_t ctx = txq->ift_ctx;
1875
1876 for (int i = 0; i < txq->ift_size; i++)
1877 iflib_txsd_destroy(ctx, txq, i);
1878
1879 if (txq->ift_br != NULL) {
1880 ifmp_ring_free(txq->ift_br);
1881 txq->ift_br = NULL;
1882 }
1883
1884 mtx_destroy(&txq->ift_mtx);
1885
1886 if (txq->ift_sds.ifsd_map != NULL) {
1887 free(txq->ift_sds.ifsd_map, M_IFLIB);
1888 txq->ift_sds.ifsd_map = NULL;
1889 }
1890 if (txq->ift_sds.ifsd_tso_map != NULL) {
1891 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1892 txq->ift_sds.ifsd_tso_map = NULL;
1893 }
1894 if (txq->ift_sds.ifsd_m != NULL) {
1895 free(txq->ift_sds.ifsd_m, M_IFLIB);
1896 txq->ift_sds.ifsd_m = NULL;
1897 }
1898 if (txq->ift_sds.ifsd_m_defer != NULL) {
1899 free(txq->ift_sds.ifsd_m_defer, M_IFLIB);
1900 txq->ift_sds.ifsd_m_defer = NULL;
1901 }
1902 if (txq->ift_buf_tag != NULL) {
1903 bus_dma_tag_destroy(txq->ift_buf_tag);
1904 txq->ift_buf_tag = NULL;
1905 }
1906 if (txq->ift_tso_buf_tag != NULL) {
1907 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1908 txq->ift_tso_buf_tag = NULL;
1909 }
1910 if (txq->ift_ifdi != NULL) {
1911 free(txq->ift_ifdi, M_IFLIB);
1912 }
1913 }
1914
1915 static void
iflib_txsd_free(if_ctx_t ctx,iflib_txq_t txq,int i)1916 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1917 {
1918 struct mbuf *m;
1919
1920 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]);
1921 if (m == NULL)
1922 return;
1923
1924 if (txq->ift_sds.ifsd_map != NULL) {
1925 bus_dmamap_sync(txq->ift_buf_tag,
1926 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1927 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1928 }
1929 if (txq->ift_sds.ifsd_tso_map != NULL) {
1930 bus_dmamap_sync(txq->ift_tso_buf_tag,
1931 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1932 bus_dmamap_unload(txq->ift_tso_buf_tag,
1933 txq->ift_sds.ifsd_tso_map[i]);
1934 }
1935 txq->ift_sds.ifsd_m[i] = NULL;
1936 m_freem(m);
1937 DBG_COUNTER_INC(tx_frees);
1938 }
1939
1940 static int
iflib_txq_setup(iflib_txq_t txq)1941 iflib_txq_setup(iflib_txq_t txq)
1942 {
1943 if_ctx_t ctx = txq->ift_ctx;
1944 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1945 if_shared_ctx_t sctx = ctx->ifc_sctx;
1946 iflib_dma_info_t di;
1947 int i;
1948
1949 /* XXX make configurable */
1950 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1951
1952 /* Reset indices */
1953 txq->ift_cidx_processed = 0;
1954 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1955 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1956 txq->ift_pad = scctx->isc_tx_pad;
1957
1958 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1959 bzero((void *)di->idi_vaddr, di->idi_size);
1960
1961 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1962 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1963 bus_dmamap_sync(di->idi_tag, di->idi_map,
1964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1965 return (0);
1966 }
1967
1968 /*********************************************************************
1969 *
1970 * Allocate DMA resources for RX buffers as well as memory for the RX
1971 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1972 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1973 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1974 * Since we use use one entry in iflib_sw_rx_desc_array per received
1975 * packet, the maximum number of entries we'll need is equal to the
1976 * number of hardware receive descriptors that we've allocated.
1977 *
1978 **********************************************************************/
1979 static int
iflib_rxsd_alloc(iflib_rxq_t rxq)1980 iflib_rxsd_alloc(iflib_rxq_t rxq)
1981 {
1982 if_ctx_t ctx = rxq->ifr_ctx;
1983 if_shared_ctx_t sctx = ctx->ifc_sctx;
1984 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1985 device_t dev = ctx->ifc_dev;
1986 iflib_fl_t fl;
1987 bus_addr_t lowaddr;
1988 int err;
1989
1990 MPASS(scctx->isc_nrxd[0] > 0);
1991 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1992
1993 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1994
1995 fl = rxq->ifr_fl;
1996 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1997 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1998 /* Set up DMA tag for RX buffers. */
1999 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2000 1, 0, /* alignment, bounds */
2001 lowaddr, /* lowaddr */
2002 BUS_SPACE_MAXADDR, /* highaddr */
2003 NULL, NULL, /* filter, filterarg */
2004 sctx->isc_rx_maxsize, /* maxsize */
2005 sctx->isc_rx_nsegments, /* nsegments */
2006 sctx->isc_rx_maxsegsize, /* maxsegsize */
2007 0, /* flags */
2008 NULL, /* lockfunc */
2009 NULL, /* lockarg */
2010 &fl->ifl_buf_tag);
2011 if (err) {
2012 device_printf(dev,
2013 "Unable to allocate RX DMA tag: %d\n", err);
2014 goto fail;
2015 }
2016
2017 /* Allocate memory for the RX mbuf map. */
2018 if (!(fl->ifl_sds.ifsd_m =
2019 (struct mbuf **) malloc(sizeof(struct mbuf *) *
2020 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2021 device_printf(dev,
2022 "Unable to allocate RX mbuf map memory\n");
2023 err = ENOMEM;
2024 goto fail;
2025 }
2026
2027 /* Allocate memory for the direct RX cluster pointer map. */
2028 if (!(fl->ifl_sds.ifsd_cl =
2029 (caddr_t *) malloc(sizeof(caddr_t) *
2030 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2031 device_printf(dev,
2032 "Unable to allocate RX cluster map memory\n");
2033 err = ENOMEM;
2034 goto fail;
2035 }
2036
2037 /* Allocate memory for the RX cluster bus address map. */
2038 if (!(fl->ifl_sds.ifsd_ba =
2039 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
2040 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2041 device_printf(dev,
2042 "Unable to allocate RX bus address map memory\n");
2043 err = ENOMEM;
2044 goto fail;
2045 }
2046
2047 /*
2048 * Create the DMA maps for RX buffers.
2049 */
2050 if (!(fl->ifl_sds.ifsd_map =
2051 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2052 device_printf(dev,
2053 "Unable to allocate RX buffer DMA map memory\n");
2054 err = ENOMEM;
2055 goto fail;
2056 }
2057 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
2058 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2059 &fl->ifl_sds.ifsd_map[i]);
2060 if (err != 0) {
2061 device_printf(dev, "Unable to create RX buffer DMA map\n");
2062 goto fail;
2063 }
2064 }
2065 }
2066 return (0);
2067
2068 fail:
2069 iflib_rx_structures_free(ctx);
2070 return (err);
2071 }
2072
2073 /*
2074 * Internal service routines
2075 */
2076
2077 struct rxq_refill_cb_arg {
2078 int error;
2079 bus_dma_segment_t seg;
2080 int nseg;
2081 };
2082
2083 static void
_rxq_refill_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)2084 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2085 {
2086 struct rxq_refill_cb_arg *cb_arg = arg;
2087
2088 cb_arg->error = error;
2089 cb_arg->seg = segs[0];
2090 cb_arg->nseg = nseg;
2091 }
2092
2093 /**
2094 * iflib_fl_refill - refill an rxq free-buffer list
2095 * @ctx: the iflib context
2096 * @fl: the free list to refill
2097 * @count: the number of new buffers to allocate
2098 *
2099 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2100 * The caller must assure that @count does not exceed the queue's capacity
2101 * minus one (since we always leave a descriptor unavailable).
2102 */
2103 static uint8_t
iflib_fl_refill(if_ctx_t ctx,iflib_fl_t fl,int count)2104 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2105 {
2106 struct if_rxd_update iru;
2107 struct rxq_refill_cb_arg cb_arg;
2108 struct mbuf *m;
2109 caddr_t cl, *sd_cl;
2110 struct mbuf **sd_m;
2111 bus_dmamap_t *sd_map;
2112 bus_addr_t bus_addr, *sd_ba;
2113 int err, frag_idx, i, idx, n, pidx;
2114 qidx_t credits;
2115
2116 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2117
2118 sd_m = fl->ifl_sds.ifsd_m;
2119 sd_map = fl->ifl_sds.ifsd_map;
2120 sd_cl = fl->ifl_sds.ifsd_cl;
2121 sd_ba = fl->ifl_sds.ifsd_ba;
2122 pidx = fl->ifl_pidx;
2123 idx = pidx;
2124 frag_idx = fl->ifl_fragidx;
2125 credits = fl->ifl_credits;
2126
2127 i = 0;
2128 n = count;
2129 MPASS(n > 0);
2130 MPASS(credits + n <= fl->ifl_size);
2131
2132 if (pidx < fl->ifl_cidx)
2133 MPASS(pidx + n <= fl->ifl_cidx);
2134 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2135 MPASS(fl->ifl_gen == 0);
2136 if (pidx > fl->ifl_cidx)
2137 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2138
2139 DBG_COUNTER_INC(fl_refills);
2140 if (n > 8)
2141 DBG_COUNTER_INC(fl_refills_large);
2142 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2143 while (n-- > 0) {
2144 /*
2145 * We allocate an uninitialized mbuf + cluster, mbuf is
2146 * initialized after rx.
2147 *
2148 * If the cluster is still set then we know a minimum sized
2149 * packet was received
2150 */
2151 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2152 &frag_idx);
2153 if (frag_idx < 0)
2154 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2155 MPASS(frag_idx >= 0);
2156 if ((cl = sd_cl[frag_idx]) == NULL) {
2157 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2158 if (__predict_false(cl == NULL))
2159 break;
2160
2161 cb_arg.error = 0;
2162 MPASS(sd_map != NULL);
2163 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2164 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2165 BUS_DMA_NOWAIT);
2166 if (__predict_false(err != 0 || cb_arg.error)) {
2167 uma_zfree(fl->ifl_zone, cl);
2168 break;
2169 }
2170
2171 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2172 sd_cl[frag_idx] = cl;
2173 #if MEMORY_LOGGING
2174 fl->ifl_cl_enqueued++;
2175 #endif
2176 } else {
2177 bus_addr = sd_ba[frag_idx];
2178 }
2179 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2180 BUS_DMASYNC_PREREAD);
2181
2182 if (sd_m[frag_idx] == NULL) {
2183 m = m_gethdr_raw(M_NOWAIT, 0);
2184 if (__predict_false(m == NULL))
2185 break;
2186 sd_m[frag_idx] = m;
2187 }
2188 bit_set(fl->ifl_rx_bitmap, frag_idx);
2189 #if MEMORY_LOGGING
2190 fl->ifl_m_enqueued++;
2191 #endif
2192
2193 DBG_COUNTER_INC(rx_allocs);
2194 fl->ifl_rxd_idxs[i] = frag_idx;
2195 fl->ifl_bus_addrs[i] = bus_addr;
2196 credits++;
2197 i++;
2198 MPASS(credits <= fl->ifl_size);
2199 if (++idx == fl->ifl_size) {
2200 #ifdef INVARIANTS
2201 fl->ifl_gen = 1;
2202 #endif
2203 idx = 0;
2204 }
2205 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2206 iru.iru_pidx = pidx;
2207 iru.iru_count = i;
2208 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2209 fl->ifl_pidx = idx;
2210 fl->ifl_credits = credits;
2211 pidx = idx;
2212 i = 0;
2213 }
2214 }
2215
2216 if (n < count - 1) {
2217 if (i != 0) {
2218 iru.iru_pidx = pidx;
2219 iru.iru_count = i;
2220 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2221 fl->ifl_pidx = idx;
2222 fl->ifl_credits = credits;
2223 }
2224 DBG_COUNTER_INC(rxd_flush);
2225 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2227 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2228 fl->ifl_id, fl->ifl_pidx);
2229 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2230 fl->ifl_fragidx = frag_idx + 1;
2231 if (fl->ifl_fragidx == fl->ifl_size)
2232 fl->ifl_fragidx = 0;
2233 } else {
2234 fl->ifl_fragidx = frag_idx;
2235 }
2236 }
2237
2238 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2239 }
2240
2241 static inline uint8_t
iflib_fl_refill_all(if_ctx_t ctx,iflib_fl_t fl)2242 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2243 {
2244 /*
2245 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2246 * This is important as it confuses most NICs. For instance,
2247 * Intel NICs have (per receive ring) RDH and RDT registers, where
2248 * RDH points to the next receive descriptor to be used by the NIC,
2249 * and RDT for the next receive descriptor to be published by the
2250 * driver to the NIC (RDT - 1 is thus the last valid one).
2251 * The condition RDH == RDT means no descriptors are available to
2252 * the NIC, and thus it would be ambiguous if it also meant that
2253 * all the descriptors are available to the NIC.
2254 */
2255 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2256 #ifdef INVARIANTS
2257 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2258 #endif
2259
2260 MPASS(fl->ifl_credits <= fl->ifl_size);
2261 MPASS(reclaimable == delta);
2262
2263 if (reclaimable > 0)
2264 return (iflib_fl_refill(ctx, fl, reclaimable));
2265 return (0);
2266 }
2267
2268 uint8_t
iflib_in_detach(if_ctx_t ctx)2269 iflib_in_detach(if_ctx_t ctx)
2270 {
2271 bool in_detach;
2272
2273 STATE_LOCK(ctx);
2274 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2275 STATE_UNLOCK(ctx);
2276 return (in_detach);
2277 }
2278
2279 static void
iflib_fl_bufs_free(iflib_fl_t fl)2280 iflib_fl_bufs_free(iflib_fl_t fl)
2281 {
2282 iflib_dma_info_t idi = fl->ifl_ifdi;
2283 bus_dmamap_t sd_map;
2284 uint32_t i;
2285
2286 for (i = 0; i < fl->ifl_size; i++) {
2287 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2288 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2289
2290 if (*sd_cl != NULL) {
2291 sd_map = fl->ifl_sds.ifsd_map[i];
2292 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2293 BUS_DMASYNC_POSTREAD);
2294 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2295 uma_zfree(fl->ifl_zone, *sd_cl);
2296 *sd_cl = NULL;
2297 if (*sd_m != NULL) {
2298 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2299 m_free_raw(*sd_m);
2300 *sd_m = NULL;
2301 }
2302 } else {
2303 MPASS(*sd_m == NULL);
2304 }
2305 #if MEMORY_LOGGING
2306 fl->ifl_m_dequeued++;
2307 fl->ifl_cl_dequeued++;
2308 #endif
2309 }
2310 #ifdef INVARIANTS
2311 for (i = 0; i < fl->ifl_size; i++) {
2312 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2313 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2314 }
2315 #endif
2316 /*
2317 * Reset free list values
2318 */
2319 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2320 bzero(idi->idi_vaddr, idi->idi_size);
2321 }
2322
2323 /*********************************************************************
2324 *
2325 * Initialize a free list and its buffers.
2326 *
2327 **********************************************************************/
2328 static int
iflib_fl_setup(iflib_fl_t fl)2329 iflib_fl_setup(iflib_fl_t fl)
2330 {
2331 iflib_rxq_t rxq = fl->ifl_rxq;
2332 if_ctx_t ctx = rxq->ifr_ctx;
2333 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2334 int qidx;
2335
2336 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2337 /*
2338 * Free current RX buffer structs and their mbufs
2339 */
2340 iflib_fl_bufs_free(fl);
2341 /* Now replenish the mbufs */
2342 MPASS(fl->ifl_credits == 0);
2343 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2344 if (scctx->isc_rxd_buf_size[qidx] != 0)
2345 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2346 else
2347 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2348 /*
2349 * ifl_buf_size may be a driver-supplied value, so pull it up
2350 * to the selected mbuf size.
2351 */
2352 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2353 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2354 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2355 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2356 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2357
2358 /*
2359 * Avoid pre-allocating zillions of clusters to an idle card
2360 * potentially speeding up attach. In any case make sure
2361 * to leave a descriptor unavailable. See the comment in
2362 * iflib_fl_refill_all().
2363 */
2364 MPASS(fl->ifl_size > 0);
2365 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2366 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2367 return (ENOBUFS);
2368 /*
2369 * handle failure
2370 */
2371 MPASS(rxq != NULL);
2372 MPASS(fl->ifl_ifdi != NULL);
2373 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2375 return (0);
2376 }
2377
2378 /*********************************************************************
2379 *
2380 * Free receive ring data structures
2381 *
2382 **********************************************************************/
2383 static void
iflib_rx_sds_free(iflib_rxq_t rxq)2384 iflib_rx_sds_free(iflib_rxq_t rxq)
2385 {
2386 iflib_fl_t fl;
2387 int i, j;
2388
2389 if (rxq->ifr_fl != NULL) {
2390 for (i = 0; i < rxq->ifr_nfl; i++) {
2391 fl = &rxq->ifr_fl[i];
2392 if (fl->ifl_buf_tag != NULL) {
2393 if (fl->ifl_sds.ifsd_map != NULL) {
2394 for (j = 0; j < fl->ifl_size; j++) {
2395 bus_dmamap_sync(
2396 fl->ifl_buf_tag,
2397 fl->ifl_sds.ifsd_map[j],
2398 BUS_DMASYNC_POSTREAD);
2399 bus_dmamap_unload(
2400 fl->ifl_buf_tag,
2401 fl->ifl_sds.ifsd_map[j]);
2402 bus_dmamap_destroy(
2403 fl->ifl_buf_tag,
2404 fl->ifl_sds.ifsd_map[j]);
2405 }
2406 }
2407 bus_dma_tag_destroy(fl->ifl_buf_tag);
2408 fl->ifl_buf_tag = NULL;
2409 }
2410 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2411 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2412 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2413 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2414 free(fl->ifl_rx_bitmap, M_IFLIB);
2415 fl->ifl_sds.ifsd_m = NULL;
2416 fl->ifl_sds.ifsd_cl = NULL;
2417 fl->ifl_sds.ifsd_ba = NULL;
2418 fl->ifl_sds.ifsd_map = NULL;
2419 fl->ifl_rx_bitmap = NULL;
2420 }
2421 free(rxq->ifr_fl, M_IFLIB);
2422 rxq->ifr_fl = NULL;
2423 free(rxq->ifr_ifdi, M_IFLIB);
2424 rxq->ifr_ifdi = NULL;
2425 rxq->ifr_cq_cidx = 0;
2426 }
2427 }
2428
2429 /*
2430 * Timer routine
2431 */
2432 static void
iflib_timer(void * arg)2433 iflib_timer(void *arg)
2434 {
2435 iflib_txq_t txq = arg;
2436 if_ctx_t ctx = txq->ift_ctx;
2437 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2438 uint64_t this_tick = ticks;
2439
2440 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2441 return;
2442
2443 /*
2444 * Check on the state of the TX queue(s); this can be done
2445 * without the lock: the counters the check reads are only
2446 * advanced by the queue's tx task and a stale read just
2447 * delays the verdict by one timer period.
2448 */
2449 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2450 qidx_t outstanding;
2451 bool frozen;
2452
2453 txq->ift_last_timer_tick = this_tick;
2454 IFDI_TIMER(ctx, txq->ift_id);
2455
2456 /*
2457 * Descriptors the hardware has not reported as
2458 * completed: neither harvested as credits
2459 * (ift_processed) nor reclaimed (ift_cleaned accounts
2460 * the difference to ift_in_use). The tail whose
2461 * report-status request is still deferred is never
2462 * reported and must not count (ift_rs_pending
2463 * over-counts it by one per packet).
2464 */
2465 outstanding = txq->ift_in_use -
2466 (qidx_t)(txq->ift_processed - txq->ift_cleaned);
2467
2468 /*
2469 * The queue is frozen while it has descriptors the
2470 * hardware has not reported as completed and none
2471 * were reclaimed over the period; the link must be
2472 * up, with no pause frames and no pending doorbell
2473 * (the laggard check below rings it).
2474 *
2475 * Being frozen is not a fault - the hardware may
2476 * defer marking descriptors as completed
2477 * indefinitely, and 8254x hardware does so for a
2478 * quiet queue - therefore the check arms only when a
2479 * frozen queue also takes on new work, and acts only
2480 * once it has stayed frozen for
2481 * net.iflib.tx_watchdog_periods consecutive periods.
2482 */
2483 frozen = outstanding > txq->ift_rs_pending &&
2484 txq->ift_processed == txq->ift_processed_prev &&
2485 txq->ift_db_pending == 0 &&
2486 sctx->isc_pause_frames == 0 &&
2487 ctx->ifc_link_state == LINK_STATE_UP;
2488 if (!frozen)
2489 txq->ift_wdog_armed = 0;
2490 else if (txq->ift_wdog_armed > 0 ||
2491 outstanding > txq->ift_outstanding_prev) {
2492 if (txq->ift_wdog_armed < UINT16_MAX)
2493 txq->ift_wdog_armed++;
2494 }
2495
2496 /*
2497 * Frozen long enough: ask the hardware. Completions
2498 * ready but unharvested for this long mean the
2499 * completion interrupt went missing - kick the
2500 * queue's task. Nothing ready, although the queue
2501 * kept taking on work, means it is hung.
2502 */
2503 if (iflib_tx_watchdog_periods > 0 &&
2504 txq->ift_wdog_armed >= iflib_tx_watchdog_periods) {
2505 bus_dmamap_sync(txq->ift_ifdi->idi_tag,
2506 txq->ift_ifdi->idi_map, BUS_DMASYNC_POSTREAD);
2507 if (ctx->isc_txd_credits_update(ctx->ifc_softc,
2508 txq->ift_id, false) == 0) {
2509 device_printf(ctx->ifc_dev,
2510 "Watchdog timeout (TX: %d desc "
2511 "avail: %d pidx: %d) -- resetting\n",
2512 txq->ift_id, TXQ_AVAIL(txq),
2513 txq->ift_pidx);
2514 STATE_LOCK(ctx);
2515 if_setdrvflagbits(ctx->ifc_ifp,
2516 IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2517 ctx->ifc_flags |=
2518 (IFC_DO_WATCHDOG | IFC_DO_RESET);
2519 iflib_admin_intr_deferred(ctx);
2520 STATE_UNLOCK(ctx);
2521 return;
2522 }
2523 GROUPTASK_ENQUEUE(&txq->ift_task);
2524 }
2525 txq->ift_outstanding_prev = outstanding;
2526 txq->ift_processed_prev = txq->ift_processed;
2527 }
2528 /* handle any laggards */
2529 if (txq->ift_db_pending)
2530 GROUPTASK_ENQUEUE(&txq->ift_task);
2531
2532 sctx->isc_pause_frames = 0;
2533 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2534 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2535 txq, txq->ift_timer.c_cpu);
2536 }
2537
2538 static uint16_t
iflib_get_mbuf_size_for(unsigned int size)2539 iflib_get_mbuf_size_for(unsigned int size)
2540 {
2541
2542 if (size <= MCLBYTES)
2543 return (MCLBYTES);
2544 else
2545 return (MJUMPAGESIZE);
2546 }
2547
2548 static void
iflib_calc_rx_mbuf_sz(if_ctx_t ctx)2549 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2550 {
2551 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2552
2553 /*
2554 * XXX don't set the max_frame_size to larger
2555 * than the hardware can handle
2556 */
2557 ctx->ifc_rx_mbuf_sz =
2558 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2559 }
2560
2561 uint32_t
iflib_get_rx_mbuf_sz(if_ctx_t ctx)2562 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2563 {
2564
2565 return (ctx->ifc_rx_mbuf_sz);
2566 }
2567
2568 static void
iflib_init_locked(if_ctx_t ctx)2569 iflib_init_locked(if_ctx_t ctx)
2570 {
2571 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2572 if_t ifp = ctx->ifc_ifp;
2573 iflib_fl_t fl;
2574 iflib_txq_t txq;
2575 iflib_rxq_t rxq;
2576 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2577 bool init_failed;
2578
2579 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2580 IFDI_INTR_DISABLE(ctx);
2581
2582 /*
2583 * See iflib_stop(). Useful in case iflib_init_locked() is
2584 * called without first calling iflib_stop().
2585 */
2586 netmap_disable_all_rings(ifp);
2587
2588 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2589 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2590 /* Set hardware offload abilities */
2591 if_clearhwassist(ifp);
2592 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2593 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2594 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2595 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2596 if (if_getcapenable(ifp) & IFCAP_TSO4)
2597 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2598 if (if_getcapenable(ifp) & IFCAP_TSO6)
2599 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2600
2601 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
2602 CALLOUT_LOCK(txq);
2603 callout_stop(&txq->ift_timer);
2604 #ifdef DEV_NETMAP
2605 callout_stop(&txq->ift_netmap_timer);
2606 #endif /* DEV_NETMAP */
2607 CALLOUT_UNLOCK(txq);
2608 (void)iflib_netmap_txq_init(ctx, txq);
2609 }
2610
2611 /*
2612 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2613 * that drivers can use the value when setting up the hardware receive
2614 * buffers.
2615 */
2616 iflib_calc_rx_mbuf_sz(ctx);
2617
2618 #ifdef INVARIANTS
2619 i = if_getdrvflags(ifp);
2620 #endif
2621 STATE_LOCK(ctx);
2622 ctx->ifc_flags &= ~IFC_INIT_FAILED;
2623 STATE_UNLOCK(ctx);
2624 IFDI_INIT(ctx);
2625 MPASS(if_getdrvflags(ifp) == i);
2626 STATE_LOCK(ctx);
2627 init_failed = (ctx->ifc_flags & IFC_INIT_FAILED) != 0;
2628 STATE_UNLOCK(ctx);
2629 if (init_failed)
2630 return;
2631 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
2632 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2633 /* This rxq is in netmap mode. Skip normal init. */
2634 continue;
2635 }
2636 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2637 if (iflib_fl_setup(fl)) {
2638 device_printf(ctx->ifc_dev,
2639 "setting up free list %d failed - "
2640 "check cluster settings\n", j);
2641 goto done;
2642 }
2643 }
2644 }
2645 done:
2646 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2647 IFDI_INTR_ENABLE(ctx);
2648 txq = ctx->ifc_txqs;
2649 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++)
2650 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2651 txq->ift_timer.c_cpu);
2652
2653 /* Re-enable txsync/rxsync. */
2654 netmap_enable_all_rings(ifp);
2655 }
2656
2657 static int
iflib_media_change(if_t ifp)2658 iflib_media_change(if_t ifp)
2659 {
2660 if_ctx_t ctx = if_getsoftc(ifp);
2661 int err;
2662
2663 CTX_LOCK(ctx);
2664 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2665 iflib_if_init_locked(ctx);
2666 CTX_UNLOCK(ctx);
2667 return (err);
2668 }
2669
2670 static void
iflib_media_status(if_t ifp,struct ifmediareq * ifmr)2671 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2672 {
2673 if_ctx_t ctx = if_getsoftc(ifp);
2674
2675 CTX_LOCK(ctx);
2676 IFDI_UPDATE_ADMIN_STATUS(ctx);
2677 IFDI_MEDIA_STATUS(ctx, ifmr);
2678 CTX_UNLOCK(ctx);
2679 }
2680
2681 static void
iflib_stop(if_ctx_t ctx)2682 iflib_stop(if_ctx_t ctx)
2683 {
2684 iflib_txq_t txq = ctx->ifc_txqs;
2685 iflib_rxq_t rxq = ctx->ifc_rxqs;
2686 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2687 if_shared_ctx_t sctx = ctx->ifc_sctx;
2688 iflib_dma_info_t di;
2689 iflib_fl_t fl;
2690 int i, j;
2691
2692 /* Tell the stack that the interface is no longer active */
2693 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2694
2695 IFDI_INTR_DISABLE(ctx);
2696 DELAY(1000);
2697 IFDI_STOP(ctx);
2698 DELAY(1000);
2699
2700 /*
2701 * Stop any pending txsync/rxsync and prevent new ones
2702 * form starting. Processes blocked in poll() will get
2703 * POLLERR.
2704 */
2705 netmap_disable_all_rings(ctx->ifc_ifp);
2706
2707 iflib_debug_reset();
2708 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2709 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2710 /* make sure all transmitters have completed before proceeding XXX */
2711
2712 CALLOUT_LOCK(txq);
2713 callout_stop(&txq->ift_timer);
2714 #ifdef DEV_NETMAP
2715 callout_stop(&txq->ift_netmap_timer);
2716 #endif /* DEV_NETMAP */
2717 CALLOUT_UNLOCK(txq);
2718
2719 if (!ctx->ifc_sysctl_simple_tx) {
2720 /* clean any enqueued buffers */
2721 iflib_ifmp_purge(txq);
2722 }
2723 /* Free any existing tx buffers. */
2724 for (j = 0; j < txq->ift_size; j++) {
2725 iflib_txsd_free(ctx, txq, j);
2726 }
2727 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2728 txq->ift_processed_prev = 0;
2729 txq->ift_outstanding_prev = 0;
2730 txq->ift_wdog_armed = 0;
2731 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0;
2732 txq->ift_npending = txq->ift_db_pending = 0;
2733 txq->ift_rs_pending = 0;
2734 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES)
2735 txq->ift_cidx = txq->ift_pidx;
2736 else
2737 txq->ift_cidx = txq->ift_pidx = 0;
2738
2739 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2740 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2741 txq->ift_pullups = 0;
2742 ifmp_ring_reset_stats(txq->ift_br);
2743 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2744 bzero((void *)di->idi_vaddr, di->idi_size);
2745 }
2746 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2747 if (rxq->ifr_task.gt_taskqueue != NULL)
2748 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue,
2749 &rxq->ifr_task.gt_task);
2750
2751 rxq->ifr_cq_cidx = 0;
2752 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2753 bzero((void *)di->idi_vaddr, di->idi_size);
2754 /* also resets the free lists pidx/cidx */
2755 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2756 iflib_fl_bufs_free(fl);
2757 }
2758 }
2759
2760 static inline caddr_t
calc_next_rxd(iflib_fl_t fl,int cidx)2761 calc_next_rxd(iflib_fl_t fl, int cidx)
2762 {
2763 qidx_t size;
2764 int nrxd;
2765 caddr_t start, end, cur, next;
2766
2767 nrxd = fl->ifl_size;
2768 size = fl->ifl_rxd_size;
2769 start = fl->ifl_ifdi->idi_vaddr;
2770
2771 if (__predict_false(size == 0))
2772 return (start);
2773 cur = start + size * cidx;
2774 end = start + size * nrxd;
2775 next = CACHE_PTR_NEXT(cur);
2776 return (next < end ? next : start);
2777 }
2778
2779 static inline void
prefetch_pkts(iflib_fl_t fl,int cidx)2780 prefetch_pkts(iflib_fl_t fl, int cidx)
2781 {
2782 int nextptr;
2783 int nrxd = fl->ifl_size;
2784 caddr_t next_rxd;
2785
2786 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1);
2787 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2788 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2789 next_rxd = calc_next_rxd(fl, cidx);
2790 prefetch(next_rxd);
2791 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]);
2792 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]);
2793 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]);
2794 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]);
2795 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]);
2796 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]);
2797 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]);
2798 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]);
2799 }
2800
2801 static struct mbuf *
rxd_frag_to_sd(iflib_rxq_t rxq,if_rxd_frag_t irf,bool unload,if_rxsd_t sd,int * pf_rv,if_rxd_info_t ri)2802 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2803 int *pf_rv, if_rxd_info_t ri)
2804 {
2805 bus_dmamap_t map;
2806 iflib_fl_t fl;
2807 caddr_t payload;
2808 struct mbuf *m;
2809 int flid, cidx, len, next;
2810
2811 map = NULL;
2812 flid = irf->irf_flid;
2813 cidx = irf->irf_idx;
2814 fl = &rxq->ifr_fl[flid];
2815 sd->ifsd_fl = fl;
2816 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2817 fl->ifl_credits--;
2818 #if MEMORY_LOGGING
2819 fl->ifl_m_dequeued++;
2820 #endif
2821 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2822 prefetch_pkts(fl, cidx);
2823 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1);
2824 prefetch(&fl->ifl_sds.ifsd_map[next]);
2825 map = fl->ifl_sds.ifsd_map[cidx];
2826
2827 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2828
2829 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2830 irf->irf_len != 0) {
2831 payload = *sd->ifsd_cl;
2832 payload += ri->iri_pad;
2833 len = ri->iri_len - ri->iri_pad;
2834 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m);
2835 switch (*pf_rv) {
2836 case PFIL_DROPPED:
2837 case PFIL_CONSUMED:
2838 /*
2839 * The filter ate it. Everything is recycled.
2840 */
2841 m = NULL;
2842 unload = 0;
2843 break;
2844 case PFIL_REALLOCED:
2845 /*
2846 * The filter copied it. Everything is recycled.
2847 * 'm' points at new mbuf.
2848 */
2849 unload = 0;
2850 break;
2851 case PFIL_PASS:
2852 /*
2853 * Filter said it was OK, so receive like
2854 * normal
2855 */
2856 m = fl->ifl_sds.ifsd_m[cidx];
2857 fl->ifl_sds.ifsd_m[cidx] = NULL;
2858 break;
2859 default:
2860 MPASS(0);
2861 }
2862 } else {
2863 m = fl->ifl_sds.ifsd_m[cidx];
2864 fl->ifl_sds.ifsd_m[cidx] = NULL;
2865 if (pf_rv != NULL)
2866 *pf_rv = PFIL_PASS;
2867 }
2868
2869 if (unload && irf->irf_len != 0)
2870 bus_dmamap_unload(fl->ifl_buf_tag, map);
2871 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1);
2872 if (__predict_false(fl->ifl_cidx == 0))
2873 fl->ifl_gen = 0;
2874 bit_clear(fl->ifl_rx_bitmap, cidx);
2875 return (m);
2876 }
2877
2878 static struct mbuf *
assemble_segments(iflib_rxq_t rxq,if_rxd_info_t ri,if_rxsd_t sd,int * pf_rv)2879 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2880 {
2881 struct mbuf *m, *mh, *mt;
2882 caddr_t cl;
2883 int *pf_rv_ptr, flags, i, padlen;
2884 bool consumed;
2885
2886 i = 0;
2887 mh = NULL;
2888 consumed = false;
2889 *pf_rv = PFIL_PASS;
2890 pf_rv_ptr = pf_rv;
2891 do {
2892 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2893 pf_rv_ptr, ri);
2894
2895 MPASS(*sd->ifsd_cl != NULL);
2896
2897 /*
2898 * Exclude zero-length frags & frags from
2899 * packets the filter has consumed or dropped
2900 */
2901 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2902 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2903 if (mh == NULL) {
2904 consumed = true;
2905 pf_rv_ptr = NULL;
2906 }
2907 /* XXX we can save the cluster here, but not the mbuf */
2908 if (m != NULL) {
2909 m_init(m, M_NOWAIT, MT_DATA, 0);
2910 m_free(m);
2911 }
2912 continue;
2913 }
2914 if (mh == NULL) {
2915 flags = M_PKTHDR | M_EXT;
2916 mh = mt = m;
2917 padlen = ri->iri_pad;
2918 } else {
2919 flags = M_EXT;
2920 mt->m_next = m;
2921 mt = m;
2922 /* assuming padding is only on the first fragment */
2923 padlen = 0;
2924 }
2925 cl = *sd->ifsd_cl;
2926 *sd->ifsd_cl = NULL;
2927
2928 /* Can these two be made one ? */
2929 m_init(m, M_NOWAIT, MT_DATA, flags);
2930 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2931 /*
2932 * These must follow m_init and m_cljset
2933 */
2934 m->m_data += padlen;
2935 ri->iri_len -= padlen;
2936 m->m_len = ri->iri_frags[i].irf_len;
2937 } while (++i < ri->iri_nfrags);
2938
2939 return (mh);
2940 }
2941
2942 /*
2943 * Process one software descriptor
2944 */
2945 static struct mbuf *
iflib_rxd_pkt_get(iflib_rxq_t rxq,if_rxd_info_t ri)2946 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2947 {
2948 struct if_rxsd sd;
2949 struct mbuf *m;
2950 int pf_rv;
2951
2952 /* should I merge this back in now that the two paths are basically duplicated? */
2953 if (ri->iri_nfrags == 1 &&
2954 ri->iri_frags[0].irf_len != 0 &&
2955 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2956 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2957 &pf_rv, ri);
2958 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2959 return (m);
2960 if (pf_rv == PFIL_PASS) {
2961 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2962 #ifndef __NO_STRICT_ALIGNMENT
2963 if (!IP_ALIGNED(m) && ri->iri_pad == 0)
2964 m->m_data += 2;
2965 #endif
2966 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2967 m->m_len = ri->iri_frags[0].irf_len;
2968 m->m_data += ri->iri_pad;
2969 ri->iri_len -= ri->iri_pad;
2970 }
2971 } else {
2972 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2973 if (m == NULL)
2974 return (NULL);
2975 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2976 return (m);
2977 }
2978 m->m_pkthdr.len = ri->iri_len;
2979 m->m_pkthdr.rcvif = ri->iri_ifp;
2980 m->m_flags |= ri->iri_flags;
2981 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2982 m->m_pkthdr.flowid = ri->iri_flowid;
2983 #ifdef NUMA
2984 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp);
2985 #endif
2986 M_HASHTYPE_SET(m, ri->iri_rsstype);
2987 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2988 m->m_pkthdr.csum_data = ri->iri_csum_data;
2989 return (m);
2990 }
2991
2992 static void
_task_fn_rx_watchdog(void * context)2993 _task_fn_rx_watchdog(void *context)
2994 {
2995 iflib_rxq_t rxq = context;
2996
2997 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2998 }
2999
3000 static uint8_t
iflib_rxeof(iflib_rxq_t rxq,qidx_t budget)3001 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
3002 {
3003 if_t ifp;
3004 if_ctx_t ctx = rxq->ifr_ctx;
3005 if_shared_ctx_t sctx = ctx->ifc_sctx;
3006 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
3007 int avail, i;
3008 qidx_t *cidxp;
3009 struct if_rxd_info ri;
3010 int err, budget_left, rx_bytes, rx_pkts;
3011 iflib_fl_t fl;
3012 #if defined(INET6) || defined(INET)
3013 int lro_enabled;
3014 #endif
3015 uint8_t retval = 0;
3016
3017 /*
3018 * XXX early demux data packets so that if_input processing only handles
3019 * acks in interrupt context
3020 */
3021 struct mbuf *m, *mh, *mt;
3022
3023 NET_EPOCH_ASSERT();
3024
3025 ifp = ctx->ifc_ifp;
3026 mh = mt = NULL;
3027 MPASS(budget > 0);
3028 rx_pkts = rx_bytes = 0;
3029 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
3030 cidxp = &rxq->ifr_cq_cidx;
3031 else
3032 cidxp = &rxq->ifr_fl[0].ifl_cidx;
3033 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
3034 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3035 retval |= iflib_fl_refill_all(ctx, fl);
3036 DBG_COUNTER_INC(rx_unavail);
3037 return (retval);
3038 }
3039
3040 #if defined(INET6) || defined(INET)
3041 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3042 #endif
3043
3044 /* pfil needs the vnet to be set */
3045 CURVNET_SET_QUIET(if_getvnet(ifp));
3046 for (budget_left = budget; budget_left > 0 && avail > 0;) {
3047 if (__predict_false(!CTX_ACTIVE(ctx))) {
3048 DBG_COUNTER_INC(rx_ctx_inactive);
3049 break;
3050 }
3051 /*
3052 * Reset client set fields to their default values
3053 */
3054 memset(&ri, 0, sizeof(ri));
3055 ri.iri_qsidx = rxq->ifr_id;
3056 ri.iri_cidx = *cidxp;
3057 ri.iri_ifp = ifp;
3058 ri.iri_frags = rxq->ifr_frags;
3059 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
3060
3061 if (err) {
3062 CURVNET_RESTORE();
3063 goto err;
3064 }
3065 rx_pkts += 1;
3066 rx_bytes += ri.iri_len;
3067 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
3068 *cidxp = ri.iri_cidx;
3069 /* Update our consumer index */
3070 /* XXX NB: shurd - check if this is still safe */
3071 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
3072 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
3073 /* was this only a completion queue message? */
3074 if (__predict_false(ri.iri_nfrags == 0))
3075 continue;
3076 }
3077 MPASS(ri.iri_nfrags != 0);
3078 MPASS(ri.iri_len != 0);
3079
3080 /* will advance the cidx on the corresponding free lists */
3081 m = iflib_rxd_pkt_get(rxq, &ri);
3082 avail--;
3083 budget_left--;
3084 if (avail == 0 && budget_left)
3085 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
3086
3087 if (__predict_false(m == NULL))
3088 continue;
3089
3090 #ifndef __NO_STRICT_ALIGNMENT
3091 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3092 continue;
3093 #endif
3094 #if defined(INET6) || defined(INET)
3095 if (lro_enabled) {
3096 tcp_lro_queue_mbuf(&rxq->ifr_lc, m);
3097 continue;
3098 }
3099 #endif
3100
3101 if (mh == NULL)
3102 mh = mt = m;
3103 else {
3104 mt->m_nextpkt = m;
3105 mt = m;
3106 }
3107 }
3108 CURVNET_RESTORE();
3109 /* make sure that we can refill faster than drain */
3110 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3111 retval |= iflib_fl_refill_all(ctx, fl);
3112
3113 if (mh != NULL) {
3114 if_input(ifp, mh);
3115 DBG_COUNTER_INC(rx_if_input);
3116 }
3117
3118 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3119 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3120
3121 /*
3122 * Flush any outstanding LRO work
3123 */
3124 #if defined(INET6) || defined(INET)
3125 tcp_lro_flush_all(&rxq->ifr_lc);
3126 #endif
3127 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3128 retval |= IFLIB_RXEOF_MORE;
3129 return (retval);
3130 err:
3131 STATE_LOCK(ctx);
3132 ctx->ifc_flags |= IFC_DO_RESET;
3133 iflib_admin_intr_deferred(ctx);
3134 STATE_UNLOCK(ctx);
3135 return (0);
3136 }
3137
3138 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1)
3139 static inline qidx_t
txq_max_db_deferred(iflib_txq_t txq,qidx_t in_use)3140 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3141 {
3142 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3143 qidx_t minthresh = txq->ift_size / 8;
3144 if (in_use > 4 * minthresh)
3145 return (notify_count);
3146 if (in_use > 2 * minthresh)
3147 return (notify_count >> 1);
3148 if (in_use > minthresh)
3149 return (notify_count >> 3);
3150 return (0);
3151 }
3152
3153 static inline qidx_t
txq_max_rs_deferred(iflib_txq_t txq)3154 txq_max_rs_deferred(iflib_txq_t txq)
3155 {
3156 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3157 qidx_t minthresh = txq->ift_size / 8;
3158 if (txq->ift_in_use > 4 * minthresh)
3159 return (notify_count);
3160 if (txq->ift_in_use > 2 * minthresh)
3161 return (notify_count >> 1);
3162 if (txq->ift_in_use > minthresh)
3163 return (notify_count >> 2);
3164 return (2);
3165 }
3166
3167 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3168 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3169
3170 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3171 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3172 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3173
3174 /* forward compatibility for cxgb */
3175 #define FIRST_QSET(ctx) 0
3176 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3177 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3178 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3179 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3180
3181 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3182 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3183
3184 static inline bool
iflib_txd_db_check(iflib_txq_t txq,int ring)3185 iflib_txd_db_check(iflib_txq_t txq, int ring)
3186 {
3187 if_ctx_t ctx = txq->ift_ctx;
3188 qidx_t dbval, max;
3189
3190 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3191
3192 /* force || threshold exceeded || at the edge of the ring */
3193 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) {
3194
3195 /*
3196 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3197 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3198 * producer index explicitly (INTC).
3199 */
3200 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3201 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3202 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3203 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3204
3205 /*
3206 * Absent bugs there are zero packets pending so reset pending counts to zero.
3207 */
3208 txq->ift_db_pending = txq->ift_npending = 0;
3209 return (true);
3210 }
3211 return (false);
3212 }
3213
3214 #ifdef PKT_DEBUG
3215 static void
print_pkt(if_pkt_info_t pi)3216 print_pkt(if_pkt_info_t pi)
3217 {
3218 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3219 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3220 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3221 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3222 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3223 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3224 }
3225 #endif
3226
3227 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3228 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3229 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3230 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3231
3232 /**
3233 * Parses out ethernet header information in the given mbuf.
3234 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length)
3235 *
3236 * This will account for the VLAN header if present.
3237 *
3238 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those
3239 * types of packets.
3240 */
3241 static int
iflib_parse_ether_header(if_pkt_info_t pi,struct mbuf ** mp,uint64_t * pullups)3242 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3243 {
3244 struct ether_vlan_header *eh;
3245 struct mbuf *m;
3246
3247 m = *mp;
3248 if (__predict_false(m->m_len < sizeof(*eh))) {
3249 (*pullups)++;
3250 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3251 return (ENOMEM);
3252 }
3253 eh = mtod(m, struct ether_vlan_header *);
3254 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3255 pi->ipi_etype = ntohs(eh->evl_proto);
3256 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3257 } else {
3258 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3259 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3260 }
3261 *mp = m;
3262
3263 return (0);
3264 }
3265
3266 /**
3267 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi.
3268 * Currently this information includes: IP ToS value, IP header version/presence
3269 *
3270 * This is missing some checks and doesn't edit the packet content as it goes,
3271 * unlike iflib_parse_header(), in order to keep the amount of code here minimal.
3272 */
3273 static int
iflib_parse_header_partial(if_pkt_info_t pi,struct mbuf ** mp,uint64_t * pullups)3274 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3275 {
3276 struct mbuf *m;
3277 int err;
3278
3279 *pullups = 0;
3280 m = *mp;
3281 if (!M_WRITABLE(m)) {
3282 m = m_dup(m, M_NOWAIT);
3283 m_freem(*mp);
3284 DBG_COUNTER_INC(tx_frees);
3285 *mp = m;
3286 if (m == NULL)
3287 return (ENOMEM);
3288 }
3289
3290 /* Fills out pi->ipi_etype */
3291 err = iflib_parse_ether_header(pi, mp, pullups);
3292 if (err)
3293 return (err);
3294 m = *mp;
3295
3296 switch (pi->ipi_etype) {
3297 #ifdef INET
3298 case ETHERTYPE_IP:
3299 {
3300 struct mbuf *n;
3301 struct ip *ip = NULL;
3302 int miniplen;
3303
3304 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip));
3305 if (__predict_false(m->m_len < miniplen)) {
3306 /*
3307 * Check for common case where the first mbuf only contains
3308 * the Ethernet header
3309 */
3310 if (m->m_len == pi->ipi_ehdrlen) {
3311 n = m->m_next;
3312 MPASS(n);
3313 /* If next mbuf contains at least the minimal IP header, then stop */
3314 if (n->m_len >= sizeof(*ip)) {
3315 ip = (struct ip *)n->m_data;
3316 } else {
3317 (*pullups)++;
3318 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3319 return (ENOMEM);
3320 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3321 }
3322 } else {
3323 (*pullups)++;
3324 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3325 return (ENOMEM);
3326 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3327 }
3328 } else {
3329 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3330 }
3331
3332 /* Have the IPv4 header w/ no options here */
3333 pi->ipi_ip_hlen = ip->ip_hl << 2;
3334 pi->ipi_ipproto = ip->ip_p;
3335 pi->ipi_ip_tos = ip->ip_tos;
3336 pi->ipi_flags |= IPI_TX_IPV4;
3337
3338 break;
3339 }
3340 #endif
3341 #ifdef INET6
3342 case ETHERTYPE_IPV6:
3343 {
3344 struct ip6_hdr *ip6;
3345
3346 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3347 (*pullups)++;
3348 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3349 return (ENOMEM);
3350 }
3351 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3352
3353 /* Have the IPv6 fixed header here */
3354 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3355 pi->ipi_ipproto = ip6->ip6_nxt;
3356 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3357 pi->ipi_flags |= IPI_TX_IPV6;
3358
3359 break;
3360 }
3361 #endif
3362 default:
3363 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3364 pi->ipi_ip_hlen = 0;
3365 break;
3366 }
3367 *mp = m;
3368
3369 return (0);
3370
3371 }
3372
3373 static int
iflib_parse_header(iflib_txq_t txq,if_pkt_info_t pi,struct mbuf ** mp)3374 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3375 {
3376 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3377 struct mbuf *m;
3378 int err;
3379
3380 m = *mp;
3381 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3382 M_WRITABLE(m) == 0) {
3383 m = m_dup(m, M_NOWAIT);
3384 m_freem(*mp);
3385 DBG_COUNTER_INC(tx_frees);
3386 *mp = m;
3387 if (m == NULL)
3388 return (ENOMEM);
3389 }
3390
3391 /* Fills out pi->ipi_etype */
3392 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups);
3393 if (__predict_false(err))
3394 return (err);
3395 m = *mp;
3396
3397 switch (pi->ipi_etype) {
3398 #ifdef INET
3399 case ETHERTYPE_IP:
3400 {
3401 struct ip *ip;
3402 struct tcphdr *th;
3403 uint8_t hlen;
3404
3405 hlen = pi->ipi_ehdrlen + sizeof(*ip);
3406 if (__predict_false(m->m_len < hlen)) {
3407 txq->ift_pullups++;
3408 if (__predict_false((m = m_pullup(m, hlen)) == NULL))
3409 return (ENOMEM);
3410 }
3411 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3412 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2);
3413 if (ip->ip_p == IPPROTO_TCP) {
3414 hlen += sizeof(*th);
3415 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2));
3416 } else if (ip->ip_p == IPPROTO_UDP) {
3417 hlen += sizeof(struct udphdr);
3418 }
3419 if (__predict_false(m->m_len < hlen)) {
3420 txq->ift_pullups++;
3421 if ((m = m_pullup(m, hlen)) == NULL)
3422 return (ENOMEM);
3423 /* reset pointers after pullup */
3424 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3425 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2));
3426 }
3427 pi->ipi_ip_hlen = ip->ip_hl << 2;
3428 pi->ipi_ipproto = ip->ip_p;
3429 pi->ipi_ip_tos = ip->ip_tos;
3430 pi->ipi_flags |= IPI_TX_IPV4;
3431
3432 /* TCP checksum offload may require TCP header length */
3433 if (IS_TX_OFFLOAD4(pi)) {
3434 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3435 pi->ipi_tcp_hflags = tcp_get_flags(th);
3436 pi->ipi_tcp_hlen = th->th_off << 2;
3437 pi->ipi_tcp_seq = th->th_seq;
3438 }
3439 if (IS_TSO4(pi)) {
3440 MPASS(ip->ip_p == IPPROTO_TCP);
3441 /*
3442 * TSO always requires hardware checksum offload.
3443 */
3444 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3445 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3446 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3447 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3448 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3449 ip->ip_sum = 0;
3450 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3451 }
3452 }
3453 }
3454 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3455 ip->ip_sum = 0;
3456
3457 break;
3458 }
3459 #endif
3460 #ifdef INET6
3461 case ETHERTYPE_IPV6:
3462 {
3463 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3464 struct tcphdr *th;
3465 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3466
3467 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3468 txq->ift_pullups++;
3469 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3470 return (ENOMEM);
3471 /* reset pointers after pullup */
3472 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3473 }
3474 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3475
3476 /* XXX-BZ this will go badly in case of ext hdrs. */
3477 pi->ipi_ipproto = ip6->ip6_nxt;
3478 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3479 pi->ipi_flags |= IPI_TX_IPV6;
3480
3481 /* TCP checksum offload may require TCP header length */
3482 if (IS_TX_OFFLOAD6(pi)) {
3483 if (pi->ipi_ipproto == IPPROTO_TCP) {
3484 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3485 txq->ift_pullups++;
3486 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3487 return (ENOMEM);
3488 /* reset pointers after pullup */
3489 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3490 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3491 }
3492 pi->ipi_tcp_hflags = tcp_get_flags(th);
3493 pi->ipi_tcp_hlen = th->th_off << 2;
3494 pi->ipi_tcp_seq = th->th_seq;
3495 }
3496 if (IS_TSO6(pi)) {
3497 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
3498 /*
3499 * TSO always requires hardware checksum offload.
3500 */
3501 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3502 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3503 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3504 }
3505 }
3506 break;
3507 }
3508 #endif
3509 default:
3510 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3511 pi->ipi_ip_hlen = 0;
3512 break;
3513 }
3514 *mp = m;
3515
3516 return (0);
3517 }
3518
3519 /*
3520 * If dodgy hardware rejects the scatter gather chain we've handed it
3521 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3522 * m_defrag'd mbufs
3523 */
3524 static __noinline struct mbuf *
iflib_remove_mbuf(iflib_txq_t txq)3525 iflib_remove_mbuf(iflib_txq_t txq)
3526 {
3527 int ntxd, pidx;
3528 struct mbuf *m, **ifsd_m;
3529
3530 ifsd_m = txq->ift_sds.ifsd_m;
3531 ntxd = txq->ift_size;
3532 pidx = txq->ift_pidx & (ntxd - 1);
3533 ifsd_m = txq->ift_sds.ifsd_m;
3534 m = IFLIB_GET_MBUF(ifsd_m[pidx]);
3535 ifsd_m[pidx] = NULL;
3536 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3537 if (txq->ift_sds.ifsd_tso_map != NULL)
3538 bus_dmamap_unload(txq->ift_tso_buf_tag,
3539 txq->ift_sds.ifsd_tso_map[pidx]);
3540 #if MEMORY_LOGGING
3541 txq->ift_dequeued++;
3542 #endif
3543 return (m);
3544 }
3545
3546 /*
3547 * Pad an mbuf to ensure a minimum ethernet frame size.
3548 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3549 */
3550 static __noinline int
iflib_ether_pad(device_t dev,struct mbuf ** m_head,uint16_t min_frame_size)3551 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3552 {
3553 /*
3554 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3555 * and ARP message is the smallest common payload I can think of
3556 */
3557 static char pad[18]; /* just zeros */
3558 int n;
3559 struct mbuf *new_head;
3560
3561 if (!M_WRITABLE(*m_head)) {
3562 new_head = m_dup(*m_head, M_NOWAIT);
3563 m_freem(*m_head);
3564 *m_head = new_head;
3565 if (new_head == NULL) {
3566 device_printf(dev, "cannot pad short frame, m_dup() failed");
3567 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3568 DBG_COUNTER_INC(tx_frees);
3569 return (ENOMEM);
3570 }
3571 }
3572
3573 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3574 n > 0; n -= sizeof(pad))
3575 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3576 break;
3577
3578 if (n > 0) {
3579 m_freem(*m_head);
3580 *m_head = NULL;
3581 device_printf(dev, "cannot pad short frame\n");
3582 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3583 DBG_COUNTER_INC(tx_frees);
3584 return (ENOMEM);
3585 }
3586
3587 return (0);
3588 }
3589
3590 static int
iflib_encap(iflib_txq_t txq,struct mbuf ** m_headp,int * obytes,int * opkts)3591 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts)
3592 {
3593 if_ctx_t ctx;
3594 if_shared_ctx_t sctx;
3595 if_softc_ctx_t scctx;
3596 bus_dma_tag_t buf_tag;
3597 bus_dma_segment_t *segs;
3598 struct mbuf *m_head, **ifsd_m;
3599 bus_dmamap_t map;
3600 struct if_pkt_info pi;
3601 uintptr_t flags;
3602 int remap = 0;
3603 int err, nsegs, ndesc, max_segs, pidx;
3604
3605 ctx = txq->ift_ctx;
3606 sctx = ctx->ifc_sctx;
3607 scctx = &ctx->ifc_softc_ctx;
3608 segs = txq->ift_segs;
3609 m_head = *m_headp;
3610 map = NULL;
3611
3612 /*
3613 * If we're doing TSO the next descriptor to clean may be quite far ahead
3614 */
3615 pidx = txq->ift_pidx;
3616 map = txq->ift_sds.ifsd_map[pidx];
3617 ifsd_m = txq->ift_sds.ifsd_m;
3618
3619 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3620 buf_tag = txq->ift_tso_buf_tag;
3621 max_segs = scctx->isc_tx_tso_segments_max;
3622 map = txq->ift_sds.ifsd_tso_map[pidx];
3623 MPASS(buf_tag != NULL);
3624 MPASS(max_segs > 0);
3625 flags = IFLIB_TSO;
3626 } else {
3627 buf_tag = txq->ift_buf_tag;
3628 max_segs = scctx->isc_tx_nsegments;
3629 map = txq->ift_sds.ifsd_map[pidx];
3630 flags = IFLIB_NO_TSO;
3631 }
3632 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3633 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3634 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3635 if (err) {
3636 DBG_COUNTER_INC(encap_txd_encap_fail);
3637 return (err);
3638 }
3639 }
3640 m_head = *m_headp;
3641
3642 memset(&pi, 0, sizeof(pi));
3643 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST));
3644 pi.ipi_pidx = pidx;
3645 pi.ipi_qsidx = txq->ift_id;
3646 pi.ipi_len = m_head->m_pkthdr.len;
3647 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3648 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3649
3650 /* deliberate bitwise OR to make one condition */
3651 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3652 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3653 DBG_COUNTER_INC(encap_txd_encap_fail);
3654 return (err);
3655 }
3656 m_head = *m_headp;
3657 }
3658
3659 retry:
3660 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3661 BUS_DMA_NOWAIT);
3662 defrag:
3663 if (__predict_false(err)) {
3664 switch (err) {
3665 case EFBIG:
3666 /* try collapse once and defrag once */
3667 if (remap == 0) {
3668 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3669 /* try defrag if collapsing fails */
3670 if (m_head == NULL)
3671 remap++;
3672 }
3673 if (remap == 1) {
3674 txq->ift_mbuf_defrag++;
3675 m_head = m_defrag(*m_headp, M_NOWAIT);
3676 }
3677 /*
3678 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3679 * failed to map an mbuf that was run through m_defrag
3680 */
3681 MPASS(remap <= 1);
3682 if (__predict_false(m_head == NULL || remap > 1))
3683 goto defrag_failed;
3684 remap++;
3685 *m_headp = m_head;
3686 goto retry;
3687 break;
3688 case ENOMEM:
3689 /* FALLTHROUGH */
3690 default:
3691 txq->ift_no_tx_dma_setup++;
3692 m_freem(*m_headp);
3693 DBG_COUNTER_INC(tx_frees);
3694 *m_headp = NULL;
3695 break;
3696 }
3697 txq->ift_map_failed++;
3698 DBG_COUNTER_INC(encap_load_mbuf_fail);
3699 DBG_COUNTER_INC(encap_txd_encap_fail);
3700 return (err);
3701 }
3702 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags);
3703 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG)
3704 pi.ipi_mbuf = m_head;
3705 else
3706 pi.ipi_mbuf = NULL;
3707 /*
3708 * XXX assumes a 1 to 1 relationship between segments and
3709 * descriptors - this does not hold true on all drivers, e.g.
3710 * cxgb
3711 */
3712 if (__predict_false(nsegs > TXQ_AVAIL(txq))) {
3713 iflib_completed_tx_reclaim_force(txq);
3714 if (__predict_false(nsegs > TXQ_AVAIL(txq))) {
3715 txq->ift_no_desc_avail++;
3716 bus_dmamap_unload(buf_tag, map);
3717 DBG_COUNTER_INC(encap_txq_avail_fail);
3718 DBG_COUNTER_INC(encap_txd_encap_fail);
3719 if (ctx->ifc_sysctl_simple_tx) {
3720 *m_headp = m_head = iflib_remove_mbuf(txq);
3721 m_freem(*m_headp);
3722 DBG_COUNTER_INC(tx_frees);
3723 *m_headp = NULL;
3724 }
3725 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3726 GROUPTASK_ENQUEUE(&txq->ift_task);
3727 return (ENOBUFS);
3728 }
3729 }
3730 /*
3731 * On Intel cards we can greatly reduce the number of TX interrupts
3732 * we see by only setting report status on every Nth descriptor.
3733 * However, this also means that the driver will need to keep track
3734 * of the descriptors that RS was set on to check them for the DD bit.
3735 */
3736 txq->ift_rs_pending += nsegs + 1;
3737 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3738 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) {
3739 pi.ipi_flags |= IPI_TX_INTR;
3740 txq->ift_rs_pending = 0;
3741 }
3742
3743 pi.ipi_segs = segs;
3744 pi.ipi_nsegs = nsegs;
3745
3746 MPASS(pidx >= 0 && pidx < txq->ift_size);
3747 #ifdef PKT_DEBUG
3748 print_pkt(&pi);
3749 #endif
3750 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3751 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3752 DBG_COUNTER_INC(tx_encap);
3753 MPASS(pi.ipi_new_pidx < txq->ift_size);
3754
3755 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3756 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3757 ndesc += txq->ift_size;
3758 txq->ift_gen = 1;
3759 }
3760 /*
3761 * drivers can need up to ift_pad sentinels
3762 */
3763 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad);
3764 MPASS(pi.ipi_new_pidx != pidx);
3765 MPASS(ndesc > 0);
3766 txq->ift_in_use += ndesc;
3767 txq->ift_db_pending += ndesc;
3768
3769 /*
3770 * We update the last software descriptor again here because there may
3771 * be a sentinel and/or there may be more mbufs than segments
3772 */
3773 txq->ift_pidx = pi.ipi_new_pidx;
3774 txq->ift_npending += pi.ipi_ndescs;
3775
3776 /*
3777 * Update packets / bytes sent
3778 */
3779 if (flags & IFLIB_TSO) {
3780 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen;
3781 int tsolen = pi.ipi_len - hlen;
3782 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz;
3783 *obytes += tsolen + nsegs * hlen;
3784 *opkts += nsegs;
3785 } else {
3786 *obytes += pi.ipi_len;
3787 *opkts += 1;
3788 }
3789 } else {
3790 *m_headp = m_head = iflib_remove_mbuf(txq);
3791 if (err == EFBIG) {
3792 txq->ift_txd_encap_efbig++;
3793 if (remap < 2) {
3794 remap = 1;
3795 goto defrag;
3796 }
3797 goto defrag_failed;
3798 }
3799 /* mp_ring assumes ENOBUFS means we didn't consume the mbuf */
3800 if (err == ENOBUFS && !ctx->ifc_sysctl_simple_tx)
3801 err = ENOMEM;
3802 goto out_with_error;
3803 }
3804 /*
3805 * err can't possibly be non-zero here, so we don't neet to test it
3806 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3807 */
3808 return (err);
3809
3810 defrag_failed:
3811 err = ENOMEM;
3812 txq->ift_mbuf_defrag_failed++;
3813 out_with_error:
3814 txq->ift_map_failed++;
3815 m_freem(*m_headp);
3816 DBG_COUNTER_INC(tx_frees);
3817 *m_headp = NULL;
3818 DBG_COUNTER_INC(encap_txd_encap_fail);
3819 return (err);
3820 }
3821
3822 static void
iflib_tx_desc_free(iflib_txq_t txq,int n,struct mbuf ** m_defer)3823 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer)
3824 {
3825 uint32_t qsize, cidx, gen;
3826 struct mbuf *m, **ifsd_m;
3827 uintptr_t flags;
3828
3829 cidx = txq->ift_cidx;
3830 gen = txq->ift_gen;
3831 qsize = txq->ift_size;
3832 ifsd_m =txq->ift_sds.ifsd_m;
3833
3834 while (n-- > 0) {
3835 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) {
3836 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]);
3837 MPASS(flags != 0);
3838 if (flags & IFLIB_TSO) {
3839 bus_dmamap_sync(txq->ift_tso_buf_tag,
3840 txq->ift_sds.ifsd_tso_map[cidx],
3841 BUS_DMASYNC_POSTWRITE);
3842 bus_dmamap_unload(txq->ift_tso_buf_tag,
3843 txq->ift_sds.ifsd_tso_map[cidx]);
3844 } else {
3845 bus_dmamap_sync(txq->ift_buf_tag,
3846 txq->ift_sds.ifsd_map[cidx],
3847 BUS_DMASYNC_POSTWRITE);
3848 bus_dmamap_unload(txq->ift_buf_tag,
3849 txq->ift_sds.ifsd_map[cidx]);
3850 }
3851 /* XXX we don't support any drivers that batch packets yet */
3852 MPASS(m->m_nextpkt == NULL);
3853 if (m_defer == NULL) {
3854 m_freem(m);
3855 } else if (m != NULL) {
3856 *m_defer = m;
3857 m_defer++;
3858 }
3859 ifsd_m[cidx] = NULL;
3860 #if MEMORY_LOGGING
3861 txq->ift_dequeued++;
3862 #endif
3863 DBG_COUNTER_INC(tx_frees);
3864 }
3865 if (__predict_false(++cidx == qsize)) {
3866 cidx = 0;
3867 gen = 0;
3868 }
3869 }
3870 txq->ift_cidx = cidx;
3871 txq->ift_gen = gen;
3872 }
3873
3874 static __inline int
iflib_txq_can_reclaim(iflib_txq_t txq)3875 iflib_txq_can_reclaim(iflib_txq_t txq)
3876 {
3877 int reclaim, thresh;
3878
3879 thresh = txq->ift_reclaim_thresh;
3880 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3881 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3882
3883 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) &&
3884 txq->ift_in_use < thresh)
3885 return (false);
3886 iflib_tx_credits_update(txq->ift_ctx, txq);
3887 reclaim = DESC_RECLAIMABLE(txq);
3888 if (reclaim <= thresh) {
3889 #ifdef INVARIANTS
3890 if (iflib_verbose_debug) {
3891 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__,
3892 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3893 reclaim, thresh);
3894 }
3895 #endif
3896 return (0);
3897 }
3898 return (reclaim);
3899 }
3900
3901 static __inline void
_iflib_completed_tx_reclaim(iflib_txq_t txq,struct mbuf ** m_defer,int reclaim)3902 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim)
3903 {
3904 txq->ift_last_reclaim = ticks;
3905 iflib_tx_desc_free(txq, reclaim, m_defer);
3906 txq->ift_cleaned += reclaim;
3907 txq->ift_in_use -= reclaim;
3908 }
3909
3910 static __inline int
iflib_completed_tx_reclaim(iflib_txq_t txq,struct mbuf ** m_defer)3911 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer)
3912 {
3913 int reclaim;
3914
3915 reclaim = iflib_txq_can_reclaim(txq);
3916 if (reclaim == 0)
3917 return (0);
3918 _iflib_completed_tx_reclaim(txq, m_defer, reclaim);
3919 return (reclaim);
3920 }
3921
3922 /*
3923 * Reclaim any transmit descriptors possible, ignoring coalescing
3924 */
3925 static __inline void
iflib_completed_tx_reclaim_force(iflib_txq_t txq)3926 iflib_completed_tx_reclaim_force(iflib_txq_t txq)
3927 {
3928 int reclaim;
3929
3930 iflib_tx_credits_update(txq->ift_ctx, txq);
3931 reclaim = DESC_RECLAIMABLE(txq);
3932 if (reclaim != 0)
3933 _iflib_completed_tx_reclaim(txq, NULL, reclaim);
3934 }
3935
3936 static struct mbuf **
_ring_peek_one(struct ifmp_ring * r,int cidx,int offset,int remaining)3937 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3938 {
3939 int next, size;
3940 struct mbuf **items;
3941
3942 size = r->size;
3943 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1);
3944 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3945
3946 prefetch(items[(cidx + offset) & (size - 1)]);
3947 if (remaining > 1) {
3948 prefetch2cachelines(&items[next]);
3949 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]);
3950 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]);
3951 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]);
3952 }
3953 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)]));
3954 }
3955
3956 static void
iflib_txq_check_drain(iflib_txq_t txq,int budget)3957 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3958 {
3959
3960 ifmp_ring_check_drainage(txq->ift_br, budget);
3961 }
3962
3963 static uint32_t
iflib_txq_can_drain(struct ifmp_ring * r)3964 iflib_txq_can_drain(struct ifmp_ring *r)
3965 {
3966 iflib_txq_t txq = r->cookie;
3967 if_ctx_t ctx = txq->ift_ctx;
3968
3969 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx))
3970 return (1);
3971 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3972 BUS_DMASYNC_POSTREAD);
3973 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3974 false));
3975 }
3976
3977 static uint32_t
iflib_txq_drain(struct ifmp_ring * r,uint32_t cidx,uint32_t pidx)3978 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3979 {
3980 iflib_txq_t txq = r->cookie;
3981 if_ctx_t ctx = txq->ift_ctx;
3982 if_t ifp = ctx->ifc_ifp;
3983 struct mbuf *m, **mp;
3984 int avail, bytes_sent, consumed, count, err, i;
3985 int mcast_sent, pkt_sent, reclaimed;
3986 bool do_prefetch, rang, ring;
3987
3988 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3989 !LINK_ACTIVE(ctx))) {
3990 DBG_COUNTER_INC(txq_drain_notready);
3991 return (0);
3992 }
3993 reclaimed = iflib_completed_tx_reclaim(txq, NULL);
3994 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3995 avail = IDXDIFF(pidx, cidx, r->size);
3996
3997 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3998 /*
3999 * The driver is unloading so we need to free all pending packets.
4000 */
4001 DBG_COUNTER_INC(txq_drain_flushing);
4002 for (i = 0; i < avail; i++) {
4003 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq))
4004 m_freem(r->items[(cidx + i) & (r->size - 1)]);
4005 r->items[(cidx + i) & (r->size - 1)] = NULL;
4006 }
4007 return (avail);
4008 }
4009
4010 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
4011 CALLOUT_LOCK(txq);
4012 callout_stop(&txq->ift_timer);
4013 CALLOUT_UNLOCK(txq);
4014 DBG_COUNTER_INC(txq_drain_oactive);
4015 return (0);
4016 }
4017
4018 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
4019 count = MIN(avail, TX_BATCH_SIZE);
4020 #ifdef INVARIANTS
4021 if (iflib_verbose_debug)
4022 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__,
4023 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
4024 #endif
4025 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
4026 err = 0;
4027 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) {
4028 int rem = do_prefetch ? count - i : 0;
4029
4030 mp = _ring_peek_one(r, cidx, i, rem);
4031 MPASS(mp != NULL && *mp != NULL);
4032
4033 /*
4034 * Completion interrupts will use the address of the txq
4035 * as a sentinel to enqueue _something_ in order to acquire
4036 * the lock on the mp_ring (there's no direct lock call).
4037 * We obviously whave to check for these sentinel cases
4038 * and skip them.
4039 */
4040 if (__predict_false(*mp == (struct mbuf *)txq)) {
4041 consumed++;
4042 continue;
4043 }
4044 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent);
4045 if (__predict_false(err)) {
4046 /* no room - bail out */
4047 if (err == ENOBUFS)
4048 break;
4049 consumed++;
4050 /* we can't send this packet - skip it */
4051 continue;
4052 }
4053 consumed++;
4054 m = *mp;
4055 DBG_COUNTER_INC(tx_sent);
4056 mcast_sent += !!(m->m_flags & M_MCAST);
4057
4058 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)))
4059 break;
4060 ETHER_BPF_MTAP(ifp, m);
4061 rang = iflib_txd_db_check(txq, false);
4062 }
4063
4064 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
4065 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh));
4066 iflib_txd_db_check(txq, ring);
4067 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
4068 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
4069 if (mcast_sent)
4070 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
4071 #ifdef INVARIANTS
4072 if (iflib_verbose_debug)
4073 printf("consumed=%d\n", consumed);
4074 #endif
4075 return (consumed);
4076 }
4077
4078 static uint32_t
iflib_txq_drain_always(struct ifmp_ring * r)4079 iflib_txq_drain_always(struct ifmp_ring *r)
4080 {
4081 return (1);
4082 }
4083
4084 static uint32_t
iflib_txq_drain_free(struct ifmp_ring * r,uint32_t cidx,uint32_t pidx)4085 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
4086 {
4087 int i, avail;
4088 struct mbuf **mp;
4089 iflib_txq_t txq;
4090
4091 txq = r->cookie;
4092
4093 CALLOUT_LOCK(txq);
4094 callout_stop(&txq->ift_timer);
4095 CALLOUT_UNLOCK(txq);
4096
4097 avail = IDXDIFF(pidx, cidx, r->size);
4098 for (i = 0; i < avail; i++) {
4099 mp = _ring_peek_one(r, cidx, i, avail - i);
4100 if (__predict_false(*mp == (struct mbuf *)txq))
4101 continue;
4102 m_freem(*mp);
4103 DBG_COUNTER_INC(tx_frees);
4104 }
4105 MPASS(ifmp_ring_is_stalled(r) == 0);
4106 return (avail);
4107 }
4108
4109 static void
iflib_ifmp_purge(iflib_txq_t txq)4110 iflib_ifmp_purge(iflib_txq_t txq)
4111 {
4112 struct ifmp_ring *r;
4113
4114 r = txq->ift_br;
4115 r->drain = iflib_txq_drain_free;
4116 r->can_drain = iflib_txq_drain_always;
4117
4118 ifmp_ring_check_drainage(r, r->size);
4119
4120 r->drain = iflib_txq_drain;
4121 r->can_drain = iflib_txq_can_drain;
4122 }
4123
4124 static void
_task_fn_tx(void * context)4125 _task_fn_tx(void *context)
4126 {
4127 iflib_txq_t txq = context;
4128 if_ctx_t ctx = txq->ift_ctx;
4129 if_t ifp = ctx->ifc_ifp;
4130 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4131
4132 #ifdef IFLIB_DIAGNOSTICS
4133 txq->ift_cpu_exec_count[curcpu]++;
4134 #endif
4135 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4136 return;
4137 #ifdef DEV_NETMAP
4138 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
4139 netmap_tx_irq(ifp, txq->ift_id))
4140 goto skip_ifmp;
4141 #endif
4142 if (ctx->ifc_sysctl_simple_tx) {
4143 mtx_lock(&txq->ift_mtx);
4144 (void)iflib_completed_tx_reclaim(txq, NULL);
4145 mtx_unlock(&txq->ift_mtx);
4146 goto skip_ifmp;
4147 }
4148 #ifdef ALTQ
4149 if (if_altq_is_enabled(ifp))
4150 iflib_altq_if_start(ifp);
4151 #endif
4152 if (txq->ift_db_pending)
4153 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
4154 else if (!abdicate)
4155 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4156 /*
4157 * When abdicating, we always need to check drainage, not just when we don't enqueue
4158 */
4159 if (abdicate)
4160 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4161
4162 skip_ifmp:
4163 if (ctx->ifc_flags & IFC_LEGACY)
4164 IFDI_INTR_ENABLE(ctx);
4165 else
4166 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
4167 }
4168
4169 static void
_task_fn_rx(void * context)4170 _task_fn_rx(void *context)
4171 {
4172 iflib_rxq_t rxq = context;
4173 if_ctx_t ctx = rxq->ifr_ctx;
4174 uint8_t more;
4175 uint16_t budget;
4176 #ifdef DEV_NETMAP
4177 u_int work = 0;
4178 int nmirq;
4179 #endif
4180
4181 #ifdef IFLIB_DIAGNOSTICS
4182 rxq->ifr_cpu_exec_count[curcpu]++;
4183 #endif
4184 DBG_COUNTER_INC(task_fn_rxs);
4185 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4186 return;
4187 #ifdef DEV_NETMAP
4188 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
4189 if (nmirq != NM_IRQ_PASS) {
4190 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
4191 goto skip_rxeof;
4192 }
4193 #endif
4194 budget = ctx->ifc_sysctl_rx_budget;
4195 if (budget == 0)
4196 budget = 16; /* XXX */
4197 more = iflib_rxeof(rxq, budget);
4198 #ifdef DEV_NETMAP
4199 skip_rxeof:
4200 #endif
4201 if ((more & IFLIB_RXEOF_MORE) == 0) {
4202 if (ctx->ifc_flags & IFC_LEGACY)
4203 IFDI_INTR_ENABLE(ctx);
4204 else
4205 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
4206 DBG_COUNTER_INC(rx_intr_enables);
4207 }
4208 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4209 return;
4210
4211 if (more & IFLIB_RXEOF_MORE)
4212 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4213 else if (more & IFLIB_RXEOF_EMPTY)
4214 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4215 }
4216
4217 static void
_task_fn_admin(void * context,int pending)4218 _task_fn_admin(void *context, int pending)
4219 {
4220 if_ctx_t ctx = context;
4221 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4222 iflib_txq_t txq;
4223 int i;
4224 bool oactive, running, do_reset, do_reset_if_up, do_watchdog;
4225 bool in_detach;
4226
4227 STATE_LOCK(ctx);
4228 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4229 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4230 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4231 do_reset_if_up = (ctx->ifc_flags & IFC_DO_RESET_IF_UP);
4232 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4233 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4234 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_RESET_IF_UP |
4235 IFC_DO_WATCHDOG);
4236 STATE_UNLOCK(ctx);
4237
4238 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4239 return;
4240 if (in_detach)
4241 return;
4242 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib,
4243 admin_task_after_detach_check,
4244 iflib_admin_task_fail_device[0] != '\0' &&
4245 strcmp(device_get_nameunit(ctx->ifc_dev),
4246 iflib_admin_task_fail_device) == 0, FAIL_POINT_NONSLEEPABLE, {});
4247
4248 CTX_LOCK(ctx);
4249 if (!do_reset && do_reset_if_up &&
4250 (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0)
4251 do_reset = true;
4252 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4253 CALLOUT_LOCK(txq);
4254 callout_stop(&txq->ift_timer);
4255 CALLOUT_UNLOCK(txq);
4256 }
4257 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4258 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4259 if (do_watchdog) {
4260 ctx->ifc_tx_watchdog_events++;
4261 IFDI_WATCHDOG_RESET(ctx);
4262 }
4263 IFDI_UPDATE_ADMIN_STATUS(ctx);
4264 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4265 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4266 txq->ift_timer.c_cpu);
4267 }
4268 IFDI_LINK_INTR_ENABLE(ctx);
4269 if (do_reset)
4270 iflib_if_init_locked(ctx);
4271 CTX_UNLOCK(ctx);
4272
4273 if (LINK_ACTIVE(ctx) == 0)
4274 return;
4275 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4276 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4277 }
4278
4279 static void
_task_fn_iov(void * context,int pending)4280 _task_fn_iov(void *context, int pending)
4281 {
4282 if_ctx_t ctx = context;
4283
4284 if (iflib_in_detach(ctx))
4285 return;
4286 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4287 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4288 return;
4289
4290 CTX_LOCK(ctx);
4291 IFDI_VFLR_HANDLE(ctx);
4292 CTX_UNLOCK(ctx);
4293 }
4294
4295 static int
iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)4296 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4297 {
4298 int err;
4299 if_int_delay_info_t info;
4300 if_ctx_t ctx;
4301
4302 info = (if_int_delay_info_t)arg1;
4303 ctx = info->iidi_ctx;
4304 info->iidi_req = req;
4305 info->iidi_oidp = oidp;
4306 CTX_LOCK(ctx);
4307 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4308 CTX_UNLOCK(ctx);
4309 return (err);
4310 }
4311
4312 /*********************************************************************
4313 *
4314 * IFNET FUNCTIONS
4315 *
4316 **********************************************************************/
4317
4318 static void
iflib_if_init_locked(if_ctx_t ctx)4319 iflib_if_init_locked(if_ctx_t ctx)
4320 {
4321 iflib_stop(ctx);
4322 iflib_init_locked(ctx);
4323 }
4324
4325 static void
iflib_if_init(void * arg)4326 iflib_if_init(void *arg)
4327 {
4328 if_ctx_t ctx = arg;
4329
4330 CTX_LOCK(ctx);
4331 iflib_if_init_locked(ctx);
4332 CTX_UNLOCK(ctx);
4333 }
4334
4335 static int
iflib_if_transmit(if_t ifp,struct mbuf * m)4336 iflib_if_transmit(if_t ifp, struct mbuf *m)
4337 {
4338 if_ctx_t ctx = if_getsoftc(ifp);
4339 iflib_txq_t txq;
4340 int err, qidx;
4341 int abdicate;
4342
4343 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4344 DBG_COUNTER_INC(tx_frees);
4345 m_freem(m);
4346 return (ENETDOWN);
4347 }
4348
4349 MPASS(m->m_nextpkt == NULL);
4350 /* ALTQ-enabled interfaces always use queue 0. */
4351 qidx = 0;
4352 /* Use driver-supplied queue selection method if it exists */
4353 if (ctx->isc_txq_select_v2) {
4354 struct if_pkt_info pi;
4355 uint64_t early_pullups = 0;
4356 memset(&pi, 0, sizeof(pi));
4357
4358 err = iflib_parse_header_partial(&pi, &m, &early_pullups);
4359 if (__predict_false(err != 0)) {
4360 /* Assign pullups for bad pkts to default queue */
4361 ctx->ifc_txqs[0].ift_pullups += early_pullups;
4362 DBG_COUNTER_INC(encap_txd_encap_fail);
4363 return (err);
4364 }
4365 /* Let driver make queueing decision */
4366 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi);
4367 ctx->ifc_txqs[qidx].ift_pullups += early_pullups;
4368 }
4369 /* Backwards compatibility w/ simpler queue select */
4370 else if (ctx->isc_txq_select)
4371 qidx = ctx->isc_txq_select(ctx->ifc_softc, m);
4372 /* If not, use iflib's standard method */
4373 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp))
4374 qidx = QIDX(ctx, m);
4375
4376 /* Set TX queue */
4377 txq = &ctx->ifc_txqs[qidx];
4378
4379 #ifdef DRIVER_BACKPRESSURE
4380 if (txq->ift_closed) {
4381 while (m != NULL) {
4382 next = m->m_nextpkt;
4383 m->m_nextpkt = NULL;
4384 m_freem(m);
4385 DBG_COUNTER_INC(tx_frees);
4386 m = next;
4387 }
4388 return (ENOBUFS);
4389 }
4390 #endif
4391 #ifdef notyet
4392 qidx = count = 0;
4393 mp = marr;
4394 next = m;
4395 do {
4396 count++;
4397 next = next->m_nextpkt;
4398 } while (next != NULL);
4399
4400 if (count > nitems(marr))
4401 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4402 /* XXX check nextpkt */
4403 m_freem(m);
4404 /* XXX simplify for now */
4405 DBG_COUNTER_INC(tx_frees);
4406 return (ENOBUFS);
4407 }
4408 for (next = m, i = 0; next != NULL; i++) {
4409 mp[i] = next;
4410 next = next->m_nextpkt;
4411 mp[i]->m_nextpkt = NULL;
4412 }
4413 #endif
4414 DBG_COUNTER_INC(tx_seen);
4415 abdicate = ctx->ifc_sysctl_tx_abdicate;
4416
4417 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4418
4419 if (abdicate)
4420 GROUPTASK_ENQUEUE(&txq->ift_task);
4421 if (err) {
4422 if (!abdicate)
4423 GROUPTASK_ENQUEUE(&txq->ift_task);
4424 /* support forthcoming later */
4425 #ifdef DRIVER_BACKPRESSURE
4426 txq->ift_closed = TRUE;
4427 #endif
4428 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4429 m_freem(m);
4430 DBG_COUNTER_INC(tx_frees);
4431 if (err == ENOBUFS)
4432 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
4433 else
4434 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
4435 }
4436
4437 return (err);
4438 }
4439
4440 #ifdef ALTQ
4441 /*
4442 * The overall approach to integrating iflib with ALTQ is to continue to use
4443 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4444 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4445 * is redundant/unnecessary, but doing so minimizes the amount of
4446 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4447 * redundantly queueing to an intermediate mp_ring is swamped by the
4448 * performance limitations inherent in using ALTQ.
4449 *
4450 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4451 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4452 * given interface. If ALTQ is enabled for an interface, then all
4453 * transmitted packets for that interface will be submitted to the ALTQ
4454 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4455 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4456 * update stats that the iflib machinery handles, and which is sensitve to
4457 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4458 * will be installed as the start routine for use by ALTQ facilities that
4459 * need to trigger queue drains on a scheduled basis.
4460 *
4461 */
4462 static void
iflib_altq_if_start(if_t ifp)4463 iflib_altq_if_start(if_t ifp)
4464 {
4465 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */
4466 struct mbuf *m;
4467
4468 IFQ_LOCK(ifq);
4469 IFQ_DEQUEUE_NOLOCK(ifq, m);
4470 while (m != NULL) {
4471 iflib_if_transmit(ifp, m);
4472 IFQ_DEQUEUE_NOLOCK(ifq, m);
4473 }
4474 IFQ_UNLOCK(ifq);
4475 }
4476
4477 static int
iflib_altq_if_transmit(if_t ifp,struct mbuf * m)4478 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4479 {
4480 int err;
4481
4482 if (if_altq_is_enabled(ifp)) {
4483 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */
4484 if (err == 0)
4485 iflib_altq_if_start(ifp);
4486 } else
4487 err = iflib_if_transmit(ifp, m);
4488
4489 return (err);
4490 }
4491 #endif /* ALTQ */
4492
4493 static void
iflib_if_qflush(if_t ifp)4494 iflib_if_qflush(if_t ifp)
4495 {
4496 if_ctx_t ctx = if_getsoftc(ifp);
4497 iflib_txq_t txq = ctx->ifc_txqs;
4498 int i;
4499
4500 STATE_LOCK(ctx);
4501 ctx->ifc_flags |= IFC_QFLUSH;
4502 STATE_UNLOCK(ctx);
4503 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4504 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4505 iflib_txq_check_drain(txq, 0);
4506 STATE_LOCK(ctx);
4507 ctx->ifc_flags &= ~IFC_QFLUSH;
4508 STATE_UNLOCK(ctx);
4509
4510 /*
4511 * When ALTQ is enabled, this will also take care of purging the
4512 * ALTQ queue(s).
4513 */
4514 if_qflush(ifp);
4515 }
4516
4517 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4518 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4519 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4520 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4521
4522 static int
iflib_if_ioctl(if_t ifp,u_long command,caddr_t data)4523 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4524 {
4525 if_ctx_t ctx = if_getsoftc(ifp);
4526 struct ifreq *ifr = (struct ifreq *)data;
4527 #if defined(INET) || defined(INET6)
4528 struct ifaddr *ifa = (struct ifaddr *)data;
4529 #endif
4530 bool avoid_reset = false;
4531 int err = 0, reinit = 0, bits;
4532
4533 switch (command) {
4534 case SIOCSIFADDR:
4535 #ifdef INET
4536 if (ifa->ifa_addr->sa_family == AF_INET)
4537 avoid_reset = true;
4538 #endif
4539 #ifdef INET6
4540 if (ifa->ifa_addr->sa_family == AF_INET6)
4541 avoid_reset = true;
4542 #endif
4543 /*
4544 * Calling init results in link renegotiation,
4545 * so we avoid doing it when possible.
4546 */
4547 if (avoid_reset) {
4548 if_setflagbits(ifp, IFF_UP, 0);
4549 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4550 reinit = 1;
4551 #ifdef INET
4552 if (!(if_getflags(ifp) & IFF_NOARP))
4553 arp_ifinit(ifp, ifa);
4554 #endif
4555 } else
4556 err = ether_ioctl(ifp, command, data);
4557 break;
4558 case SIOCSIFMTU:
4559 CTX_LOCK(ctx);
4560 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4561 CTX_UNLOCK(ctx);
4562 break;
4563 }
4564 bits = if_getdrvflags(ifp);
4565 /* stop the driver and free any clusters before proceeding */
4566 iflib_stop(ctx);
4567
4568 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4569 STATE_LOCK(ctx);
4570 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4571 ctx->ifc_flags |= IFC_MULTISEG;
4572 else
4573 ctx->ifc_flags &= ~IFC_MULTISEG;
4574 STATE_UNLOCK(ctx);
4575 err = if_setmtu(ifp, ifr->ifr_mtu);
4576 }
4577 iflib_init_locked(ctx);
4578 STATE_LOCK(ctx);
4579 /* Preserve the stopped state reported by iflib_init_failed(). */
4580 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0)
4581 if_setdrvflags(ifp, bits);
4582 STATE_UNLOCK(ctx);
4583 CTX_UNLOCK(ctx);
4584 break;
4585 case SIOCSIFFLAGS:
4586 CTX_LOCK(ctx);
4587 if (if_getflags(ifp) & IFF_UP) {
4588 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4589 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4590 (IFF_PROMISC | IFF_ALLMULTI)) {
4591 CTX_UNLOCK(ctx);
4592 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4593 CTX_LOCK(ctx);
4594 }
4595 } else
4596 reinit = 1;
4597 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4598 iflib_stop(ctx);
4599 }
4600 ctx->ifc_if_flags = if_getflags(ifp);
4601 CTX_UNLOCK(ctx);
4602 break;
4603 case SIOCADDMULTI:
4604 case SIOCDELMULTI:
4605 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4606 CTX_LOCK(ctx);
4607 IFDI_INTR_DISABLE(ctx);
4608 IFDI_MULTI_SET(ctx);
4609 IFDI_INTR_ENABLE(ctx);
4610 CTX_UNLOCK(ctx);
4611 }
4612 break;
4613 case SIOCSIFMEDIA:
4614 CTX_LOCK(ctx);
4615 IFDI_MEDIA_SET(ctx);
4616 CTX_UNLOCK(ctx);
4617 /* FALLTHROUGH */
4618 case SIOCGIFMEDIA:
4619 case SIOCGIFXMEDIA:
4620 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4621 break;
4622 case SIOCGI2C:
4623 /* FALLTHROUGH */
4624 case SIOCGI2CPB:
4625 {
4626 struct ifi2creq i2c;
4627 if_shared_ctx_t sctx = ctx->ifc_sctx;
4628
4629 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4630 if (err != 0)
4631 break;
4632 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4633 err = EINVAL;
4634 break;
4635 }
4636 if (i2c.len > sizeof(i2c.data)) {
4637 err = EINVAL;
4638 break;
4639 }
4640 if (command == SIOCGI2C) {
4641 i2c.page = i2c.bank = 0;
4642 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) {
4643 err = EINVAL;
4644 break;
4645 }
4646
4647 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4648 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4649 sizeof(i2c));
4650 break;
4651 }
4652 case SIOCSIFCAP:
4653 {
4654 int mask, setmask, oldmask;
4655
4656 oldmask = if_getcapenable(ifp);
4657 mask = ifr->ifr_reqcap ^ oldmask;
4658 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4659 setmask = 0;
4660 #ifdef TCP_OFFLOAD
4661 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6);
4662 #endif
4663 setmask |= (mask & IFCAP_FLAGS);
4664 setmask |= (mask & IFCAP_WOL);
4665
4666 /*
4667 * If any RX csum has changed, change all the ones that
4668 * are supported by the driver.
4669 */
4670 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4671 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4672 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4673 }
4674
4675 /*
4676 * want to ensure that traffic has stopped before we change any of the flags
4677 */
4678 if (setmask) {
4679 CTX_LOCK(ctx);
4680 bits = if_getdrvflags(ifp);
4681 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4682 iflib_stop(ctx);
4683 STATE_LOCK(ctx);
4684 if_togglecapenable(ifp, setmask);
4685 ctx->ifc_softc_ctx.isc_capenable ^= setmask;
4686 STATE_UNLOCK(ctx);
4687 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4688 iflib_init_locked(ctx);
4689 STATE_LOCK(ctx);
4690 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0)
4691 if_setdrvflags(ifp, bits);
4692 STATE_UNLOCK(ctx);
4693 CTX_UNLOCK(ctx);
4694 }
4695 if_vlancap(ifp);
4696 break;
4697 }
4698 case SIOCGPRIVATE_0:
4699 case SIOCSDRVSPEC:
4700 case SIOCGDRVSPEC:
4701 CTX_LOCK(ctx);
4702 err = IFDI_PRIV_IOCTL(ctx, command, data);
4703 CTX_UNLOCK(ctx);
4704 break;
4705 case SIOCGIFDOWNREASON:
4706 CTX_LOCK(ctx);
4707 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data);
4708 CTX_UNLOCK(ctx);
4709 break;
4710 default:
4711 err = ether_ioctl(ifp, command, data);
4712 break;
4713 }
4714 if (reinit)
4715 iflib_if_init(ctx);
4716 return (err);
4717 }
4718
4719 static uint64_t
iflib_if_get_counter(if_t ifp,ift_counter cnt)4720 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4721 {
4722 if_ctx_t ctx = if_getsoftc(ifp);
4723
4724 return (IFDI_GET_COUNTER(ctx, cnt));
4725 }
4726
4727 /*********************************************************************
4728 *
4729 * OTHER FUNCTIONS EXPORTED TO THE STACK
4730 *
4731 **********************************************************************/
4732
4733 static void
iflib_vlan_register(void * arg,if_t ifp,uint16_t vtag)4734 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4735 {
4736 if_ctx_t ctx = if_getsoftc(ifp);
4737
4738 if ((void *)ctx != arg)
4739 return;
4740
4741 if ((vtag == 0) || (vtag > 4095))
4742 return;
4743
4744 if (iflib_in_detach(ctx))
4745 return;
4746
4747 CTX_LOCK(ctx);
4748 /* Driver may need all untagged packets to be flushed */
4749 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4750 iflib_stop(ctx);
4751 IFDI_VLAN_REGISTER(ctx, vtag);
4752 /* Re-init to load the changes, if required */
4753 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4754 iflib_init_locked(ctx);
4755 CTX_UNLOCK(ctx);
4756 }
4757
4758 static void
iflib_vlan_unregister(void * arg,if_t ifp,uint16_t vtag)4759 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4760 {
4761 if_ctx_t ctx = if_getsoftc(ifp);
4762
4763 if ((void *)ctx != arg)
4764 return;
4765
4766 if ((vtag == 0) || (vtag > 4095))
4767 return;
4768
4769 CTX_LOCK(ctx);
4770 /* Driver may need all tagged packets to be flushed */
4771 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4772 iflib_stop(ctx);
4773 IFDI_VLAN_UNREGISTER(ctx, vtag);
4774 /* Re-init to load the changes, if required */
4775 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4776 iflib_init_locked(ctx);
4777 CTX_UNLOCK(ctx);
4778 }
4779
4780 static void
_task_fn_led(void * context,int pending __unused)4781 _task_fn_led(void *context, int pending __unused)
4782 {
4783 if_ctx_t ctx = context;
4784 bool in_detach;
4785 int onoff;
4786
4787 STATE_LOCK(ctx);
4788 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0;
4789 onoff = ctx->ifc_led_state;
4790 STATE_UNLOCK(ctx);
4791 if (in_detach)
4792 return;
4793
4794 CTX_LOCK(ctx);
4795 IFDI_LED_FUNC(ctx, onoff);
4796 CTX_UNLOCK(ctx);
4797 }
4798
4799 static void
iflib_led_func(void * arg,int onoff)4800 iflib_led_func(void *arg, int onoff)
4801 {
4802 if_ctx_t ctx = arg;
4803 bool in_detach;
4804
4805 /* led(4) may invoke this callback from a non-sleepable callout. */
4806 STATE_LOCK(ctx);
4807 ctx->ifc_led_state = onoff;
4808 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0;
4809 STATE_UNLOCK(ctx);
4810 if (!in_detach)
4811 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_led_task);
4812 }
4813
4814 /*********************************************************************
4815 *
4816 * BUS FUNCTION DEFINITIONS
4817 *
4818 **********************************************************************/
4819
4820 int
iflib_device_probe(device_t dev)4821 iflib_device_probe(device_t dev)
4822 {
4823 const pci_vendor_info_t *ent;
4824 if_shared_ctx_t sctx;
4825 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4826 uint16_t pci_vendor_id;
4827
4828 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4829 return (ENOTSUP);
4830
4831 pci_vendor_id = pci_get_vendor(dev);
4832 pci_device_id = pci_get_device(dev);
4833 pci_subvendor_id = pci_get_subvendor(dev);
4834 pci_subdevice_id = pci_get_subdevice(dev);
4835 pci_rev_id = pci_get_revid(dev);
4836 if (sctx->isc_parse_devinfo != NULL)
4837 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4838
4839 ent = sctx->isc_vendor_info;
4840 while (ent->pvi_vendor_id != 0) {
4841 if (pci_vendor_id != ent->pvi_vendor_id) {
4842 ent++;
4843 continue;
4844 }
4845 if ((pci_device_id == ent->pvi_device_id) &&
4846 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4847 (ent->pvi_subvendor_id == 0)) &&
4848 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4849 (ent->pvi_subdevice_id == 0)) &&
4850 ((pci_rev_id == ent->pvi_rev_id) ||
4851 (ent->pvi_rev_id == 0))) {
4852 device_set_desc_copy(dev, ent->pvi_name);
4853 /* this needs to be changed to zero if the bus probing code
4854 * ever stops re-probing on best match because the sctx
4855 * may have its values over written by register calls
4856 * in subsequent probes
4857 */
4858 return (BUS_PROBE_DEFAULT);
4859 }
4860 ent++;
4861 }
4862 return (ENXIO);
4863 }
4864
4865 int
iflib_device_probe_vendor(device_t dev)4866 iflib_device_probe_vendor(device_t dev)
4867 {
4868 int probe;
4869
4870 probe = iflib_device_probe(dev);
4871 if (probe == BUS_PROBE_DEFAULT)
4872 return (BUS_PROBE_VENDOR);
4873 else
4874 return (probe);
4875 }
4876
4877 static void
iflib_reset_qvalues(if_ctx_t ctx)4878 iflib_reset_qvalues(if_ctx_t ctx)
4879 {
4880 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4881 if_shared_ctx_t sctx = ctx->ifc_sctx;
4882 device_t dev = ctx->ifc_dev;
4883 int i;
4884
4885 if (ctx->ifc_sysctl_ntxqs != 0)
4886 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4887 if (ctx->ifc_sysctl_nrxqs != 0)
4888 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4889
4890 for (i = 0; i < sctx->isc_ntxqs; i++) {
4891 if (ctx->ifc_sysctl_ntxds[i] != 0)
4892 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4893 else
4894 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4895 }
4896
4897 for (i = 0; i < sctx->isc_nrxqs; i++) {
4898 if (ctx->ifc_sysctl_nrxds[i] != 0)
4899 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4900 else
4901 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4902 }
4903
4904 for (i = 0; i < sctx->isc_nrxqs; i++) {
4905 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4906 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4907 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4908 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4909 }
4910 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4911 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4912 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4913 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4914 }
4915 if (!powerof2(scctx->isc_nrxd[i])) {
4916 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4917 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4918 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4919 }
4920 }
4921
4922 for (i = 0; i < sctx->isc_ntxqs; i++) {
4923 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4924 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4925 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4926 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4927 }
4928 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4929 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4930 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4931 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4932 }
4933 if (!powerof2(scctx->isc_ntxd[i])) {
4934 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4935 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4936 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4937 }
4938 }
4939 scctx->isc_tx_pad = 2;
4940 }
4941
4942 static void
iflib_add_pfil(if_ctx_t ctx)4943 iflib_add_pfil(if_ctx_t ctx)
4944 {
4945 struct pfil_head *pfil;
4946 struct pfil_head_args pa;
4947 iflib_rxq_t rxq;
4948 int i;
4949
4950 pa.pa_version = PFIL_VERSION;
4951 pa.pa_flags = PFIL_IN;
4952 pa.pa_type = PFIL_TYPE_ETHERNET;
4953 pa.pa_headname = if_name(ctx->ifc_ifp);
4954 pfil = pfil_head_register(&pa);
4955
4956 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4957 rxq->pfil = pfil;
4958 }
4959 }
4960
4961 static void
iflib_rem_pfil(if_ctx_t ctx)4962 iflib_rem_pfil(if_ctx_t ctx)
4963 {
4964 struct pfil_head *pfil;
4965 iflib_rxq_t rxq;
4966 int i;
4967
4968 rxq = ctx->ifc_rxqs;
4969 pfil = rxq->pfil;
4970 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4971 rxq->pfil = NULL;
4972 }
4973 pfil_head_unregister(pfil);
4974 }
4975
4976
4977 /*
4978 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4979 * cpuid and wrapping as necessary.
4980 */
4981 static unsigned int
cpuid_advance(if_ctx_t ctx,unsigned int cpuid,unsigned int n)4982 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4983 {
4984 unsigned int first_valid;
4985 unsigned int last_valid;
4986
4987 /* cpuid should always be in the valid set */
4988 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4989
4990 /* valid set should never be empty */
4991 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4992
4993 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4994 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4995 n = n % CPU_COUNT(&ctx->ifc_cpus);
4996 while (n > 0) {
4997 do {
4998 cpuid++;
4999 if (cpuid > last_valid)
5000 cpuid = first_valid;
5001 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
5002 n--;
5003 }
5004
5005 return (cpuid);
5006 }
5007
5008 /*
5009 * CPU mapping behaviors
5010 * ---------------------
5011 * 'separate txrx' refers to the separate_txrx sysctl
5012 * 'use logical' refers to the use_logical_cores sysctl
5013 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
5014 *
5015 * separate use INTR
5016 * txrx logical CPUS result
5017 * ---------- --------- ------ ------------------------------------------------
5018 * - - X RX and TX queues mapped to consecutive physical
5019 * cores with RX/TX pairs on same core and excess
5020 * of either following
5021 * - X X RX and TX queues mapped to consecutive cores
5022 * of any type with RX/TX pairs on same core and
5023 * excess of either following
5024 * X - X RX and TX queues mapped to consecutive physical
5025 * cores; all RX then all TX
5026 * X X X RX queues mapped to consecutive physical cores
5027 * first, then TX queues mapped to L2 neighbor of
5028 * the corresponding RX queue if one exists,
5029 * otherwise to consecutive physical cores
5030 * - n/a - RX and TX queues mapped to consecutive cores of
5031 * any type with RX/TX pairs on same core and excess
5032 * of either following
5033 * X n/a - RX and TX queues mapped to consecutive cores of
5034 * any type; all RX then all TX
5035 */
5036 static unsigned int
get_cpuid_for_queue(if_ctx_t ctx,unsigned int base_cpuid,unsigned int qid,bool is_tx)5037 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
5038 bool is_tx)
5039 {
5040 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5041 unsigned int core_index;
5042
5043 if (ctx->ifc_sysctl_separate_txrx) {
5044 /*
5045 * When using separate CPUs for TX and RX, the assignment
5046 * will always be of a consecutive CPU out of the set of
5047 * context CPUs, except for the specific case where the
5048 * context CPUs are phsyical cores, the use of logical cores
5049 * has been enabled, the assignment is for TX, the TX qid
5050 * corresponds to an RX qid, and the CPU assigned to the
5051 * corresponding RX queue has an L2 neighbor.
5052 */
5053 if (ctx->ifc_sysctl_use_logical_cores &&
5054 ctx->ifc_cpus_are_physical_cores &&
5055 is_tx && qid < scctx->isc_nrxqsets) {
5056 int l2_neighbor;
5057 unsigned int rx_cpuid;
5058
5059 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
5060 l2_neighbor = sched_find_l2_neighbor(rx_cpuid);
5061 if (l2_neighbor != -1) {
5062 return (l2_neighbor);
5063 }
5064 /*
5065 * ... else fall through to the normal
5066 * consecutive-after-RX assignment scheme.
5067 *
5068 * Note that we are assuming that all RX queue CPUs
5069 * have an L2 neighbor, or all do not. If a mixed
5070 * scenario is possible, we will have to keep track
5071 * separately of how many queues prior to this one
5072 * were not able to be assigned to an L2 neighbor.
5073 */
5074 }
5075 if (is_tx)
5076 core_index = scctx->isc_nrxqsets + qid;
5077 else
5078 core_index = qid;
5079 } else {
5080 core_index = qid;
5081 }
5082
5083 return (cpuid_advance(ctx, base_cpuid, core_index));
5084 }
5085
5086 static uint16_t
get_ctx_core_offset(if_ctx_t ctx)5087 get_ctx_core_offset(if_ctx_t ctx)
5088 {
5089 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5090 struct cpu_offset *op;
5091 cpuset_t assigned_cpus;
5092 unsigned int cores_consumed;
5093 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
5094 unsigned int first_valid;
5095 unsigned int last_valid;
5096 unsigned int i;
5097
5098 MPASS(!ctx->ifc_core_offset_ref);
5099 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
5100 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
5101
5102 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
5103 /*
5104 * Align the user-chosen base CPU ID to the next valid CPU
5105 * for this device. If the chosen base CPU ID is smaller
5106 * than the first valid CPU or larger than the last valid
5107 * CPU, we assume the user does not know what the valid
5108 * range is for this device and is thinking in terms of a
5109 * zero-based reference frame, and so we shift the given
5110 * value into the valid range (and wrap accordingly) so the
5111 * intent is translated to the proper frame of reference.
5112 * If the base CPU ID is within the valid first/last, but
5113 * does not correspond to a valid CPU, it is advanced to the
5114 * next valid CPU (wrapping if necessary).
5115 */
5116 if (base_cpuid < first_valid || base_cpuid > last_valid) {
5117 /* shift from zero-based to first_valid-based */
5118 base_cpuid += first_valid;
5119 /* wrap to range [first_valid, last_valid] */
5120 base_cpuid = (base_cpuid - first_valid) %
5121 (last_valid - first_valid + 1);
5122 }
5123 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
5124 /*
5125 * base_cpuid is in [first_valid, last_valid], but
5126 * not a member of the valid set. In this case,
5127 * there will always be a member of the valid set
5128 * with a CPU ID that is greater than base_cpuid,
5129 * and we simply advance to it.
5130 */
5131 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
5132 base_cpuid++;
5133 }
5134 return (base_cpuid);
5135 }
5136
5137 /*
5138 * Determine how many cores will be consumed by performing the CPU
5139 * assignments and counting how many of the assigned CPUs correspond
5140 * to CPUs in the set of context CPUs. This is done using the CPU
5141 * ID first_valid as the base CPU ID, as the base CPU must be within
5142 * the set of context CPUs.
5143 *
5144 * Note not all assigned CPUs will be in the set of context CPUs
5145 * when separate CPUs are being allocated to TX and RX queues,
5146 * assignment to logical cores has been enabled, the set of context
5147 * CPUs contains only physical CPUs, and TX queues are mapped to L2
5148 * neighbors of CPUs that RX queues have been mapped to - in this
5149 * case we do only want to count how many CPUs in the set of context
5150 * CPUs have been consumed, as that determines the next CPU in that
5151 * set to start allocating at for the next device for which
5152 * core_offset is not set.
5153 */
5154 CPU_ZERO(&assigned_cpus);
5155 for (i = 0; i < scctx->isc_ntxqsets; i++)
5156 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
5157 &assigned_cpus);
5158 for (i = 0; i < scctx->isc_nrxqsets; i++)
5159 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
5160 &assigned_cpus);
5161 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus);
5162 cores_consumed = CPU_COUNT(&assigned_cpus);
5163
5164 mtx_lock(&cpu_offset_mtx);
5165 SLIST_FOREACH(op, &cpu_offsets, entries) {
5166 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5167 base_cpuid = op->next_cpuid;
5168 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
5169 cores_consumed);
5170 MPASS(op->refcount < UINT_MAX);
5171 op->refcount++;
5172 ctx->ifc_core_offset_ref = true;
5173 break;
5174 }
5175 }
5176 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
5177 base_cpuid = first_valid;
5178 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
5179 M_NOWAIT | M_ZERO);
5180 if (op == NULL) {
5181 device_printf(ctx->ifc_dev,
5182 "allocation for cpu offset failed.\n");
5183 } else {
5184 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
5185 cores_consumed);
5186 op->refcount = 1;
5187 CPU_COPY(&ctx->ifc_cpus, &op->set);
5188 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
5189 ctx->ifc_core_offset_ref = true;
5190 }
5191 }
5192 mtx_unlock(&cpu_offset_mtx);
5193
5194 return (base_cpuid);
5195 }
5196
5197 static void
unref_ctx_core_offset(if_ctx_t ctx)5198 unref_ctx_core_offset(if_ctx_t ctx)
5199 {
5200 struct cpu_offset *op, *top;
5201
5202 if (!ctx->ifc_core_offset_ref)
5203 return;
5204
5205 mtx_lock(&cpu_offset_mtx);
5206 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
5207 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5208 MPASS(op->refcount > 0);
5209 op->refcount--;
5210 if (op->refcount == 0) {
5211 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
5212 free(op, M_IFLIB);
5213 }
5214 ctx->ifc_core_offset_ref = false;
5215 break;
5216 }
5217 }
5218 mtx_unlock(&cpu_offset_mtx);
5219 MPASS(!ctx->ifc_core_offset_ref);
5220 }
5221
5222 static bool
iflib_register_fail_device_matches(device_t dev)5223 iflib_register_fail_device_matches(device_t dev)
5224 {
5225 const char *nameunit;
5226
5227 nameunit = device_get_nameunit(dev);
5228 return (iflib_register_fail_device[0] != '\0' && nameunit != NULL &&
5229 strcmp(nameunit, iflib_register_fail_device) == 0);
5230 }
5231
5232 #define IFLIB_REGISTER_FAIL_POINT(_dev, _name, _error, _label) do { \
5233 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib, _name, \
5234 iflib_register_fail_device_matches((_dev)), \
5235 FAIL_POINT_NONSLEEPABLE, { \
5236 (_error) = RETURN_VALUE; \
5237 if ((_error) <= 0) \
5238 (_error) = EIO; \
5239 device_printf((_dev), \
5240 "injecting iflib registration failure at %s: %d\n", \
5241 #_name, (_error)); \
5242 goto _label; \
5243 }); \
5244 } while (0)
5245
5246 int
iflib_device_register(device_t dev,void * sc,if_shared_ctx_t sctx,if_ctx_t * ctxp)5247 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5248 {
5249 if_ctx_t ctx;
5250 if_t ifp;
5251 if_softc_ctx_t scctx;
5252 kobjop_desc_t kobj_desc;
5253 kobj_method_t *kobj_method;
5254 bool attach_pre_succeeded, intr_allocated, queues_allocated;
5255 int err, msix, rid;
5256 #ifdef PCI_IOV
5257 int iov_error;
5258 #endif
5259 int num_txd, num_rxd;
5260 char namebuf[TASKQUEUE_NAMELEN];
5261
5262 attach_pre_succeeded = false;
5263 intr_allocated = false;
5264 queues_allocated = false;
5265 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO);
5266
5267 if (sc == NULL) {
5268 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO);
5269 device_set_softc(dev, ctx);
5270 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5271 }
5272
5273 ctx->ifc_sctx = sctx;
5274 ctx->ifc_dev = dev;
5275 ctx->ifc_softc = sc;
5276
5277 iflib_register(ctx);
5278 iflib_add_device_sysctl_pre(ctx);
5279
5280 scctx = &ctx->ifc_softc_ctx;
5281 ifp = ctx->ifc_ifp;
5282 if (ctx->ifc_sysctl_simple_tx) {
5283 #ifndef ALTQ
5284 if_settransmitfn(ifp, iflib_simple_transmit);
5285 device_printf(dev, "using simple if_transmit\n");
5286 #else
5287 device_printf(dev, "ALTQ prevents using simple if_transmit\n");
5288 ctx->ifc_sysctl_simple_tx = 0;
5289 #endif
5290 }
5291 iflib_reset_qvalues(ctx);
5292 IFNET_WLOCK();
5293 CTX_LOCK(ctx);
5294 IFLIB_REGISTER_FAIL_POINT(dev, register_before_attach_pre, err,
5295 fail_cleanup);
5296 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5297 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5298 goto fail_cleanup;
5299 }
5300 attach_pre_succeeded = true;
5301 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_pre, err,
5302 fail_cleanup);
5303 _iflib_pre_assert(scctx);
5304 ctx->ifc_txrx = *scctx->isc_txrx;
5305
5306 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
5307
5308 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5309 ctx->ifc_mediap = scctx->isc_media;
5310
5311 #ifdef INVARIANTS
5312 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5313 MPASS(scctx->isc_tx_csum_flags);
5314 #endif
5315
5316 if_setcapabilities(ifp,
5317 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5318 if_setcapenable(ifp,
5319 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5320
5321 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5322 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5323 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5324 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5325
5326 num_txd = iflib_num_tx_descs(ctx);
5327 num_rxd = iflib_num_rx_descs(ctx);
5328
5329 /* XXX change for per-queue sizes */
5330 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5331 num_txd, num_rxd);
5332
5333 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5334 scctx->isc_tx_nsegments = max(1, num_txd /
5335 MAX_SINGLE_PACKET_FRACTION);
5336 if (scctx->isc_tx_tso_segments_max > num_txd /
5337 MAX_SINGLE_PACKET_FRACTION)
5338 scctx->isc_tx_tso_segments_max = max(1,
5339 num_txd / MAX_SINGLE_PACKET_FRACTION);
5340
5341 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5342 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5343 /*
5344 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5345 * but some MACs do.
5346 */
5347 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5348 IP_MAXPACKET));
5349 /*
5350 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5351 * into account. In the worst case, each of these calls will
5352 * add another mbuf and, thus, the requirement for another DMA
5353 * segment. So for best performance, it doesn't make sense to
5354 * advertize a maximum of TSO segments that typically will
5355 * require defragmentation in iflib_encap().
5356 */
5357 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5358 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5359 }
5360 if (scctx->isc_rss_table_size == 0)
5361 scctx->isc_rss_table_size = 64;
5362 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1;
5363
5364 /* Create and start admin taskqueue */
5365 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev));
5366 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT,
5367 taskqueue_thread_enqueue, &ctx->ifc_tq);
5368 if (ctx->ifc_tq == NULL) {
5369 device_printf(dev, "Unable to create admin taskqueue\n");
5370 err = ENOMEM;
5371 goto fail_cleanup;
5372 }
5373
5374 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf);
5375 if (err) {
5376 device_printf(dev,
5377 "Unable to start admin taskqueue threads error: %d\n",
5378 err);
5379 taskqueue_free(ctx->ifc_tq);
5380 ctx->ifc_tq = NULL;
5381 goto fail_cleanup;
5382 }
5383
5384 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5385 TASK_INIT(&ctx->ifc_led_task, 0, _task_fn_led, ctx);
5386 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx);
5387 IFLIB_REGISTER_FAIL_POINT(dev, register_after_taskqueue, err,
5388 fail_cleanup);
5389
5390 /* Set up cpu set. If it fails, use the set of all CPUs. */
5391 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5392 device_printf(dev, "Unable to fetch CPU list\n");
5393 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5394 ctx->ifc_cpus_are_physical_cores = false;
5395 } else
5396 ctx->ifc_cpus_are_physical_cores = true;
5397 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5398
5399 /*
5400 * Now set up MSI or MSI-X, should return us the number of supported
5401 * vectors (will be 1 for a legacy interrupt and MSI).
5402 */
5403 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5404 msix = scctx->isc_vectors;
5405 } else if (scctx->isc_msix_bar != 0)
5406 /*
5407 * The simple fact that isc_msix_bar is not 0 does not mean we
5408 * we have a good value there that is known to work.
5409 */
5410 msix = iflib_msix_init(ctx);
5411 else {
5412 scctx->isc_vectors = 1;
5413 scctx->isc_ntxqsets = 1;
5414 scctx->isc_nrxqsets = 1;
5415 scctx->isc_intr = IFLIB_INTR_LEGACY;
5416 msix = 0;
5417 }
5418 intr_allocated = true;
5419 IFLIB_REGISTER_FAIL_POINT(dev, register_after_interrupts, err,
5420 fail_cleanup);
5421 /* Get memory for the station queues */
5422 if ((err = iflib_queues_alloc(ctx))) {
5423 device_printf(dev, "Unable to allocate queue memory\n");
5424 goto fail_cleanup;
5425 }
5426 queues_allocated = true;
5427
5428 if ((err = iflib_qset_structures_setup(ctx)))
5429 goto fail_cleanup;
5430
5431 /*
5432 * Now that we know how many queues there are, get the core offset.
5433 */
5434 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5435 IFLIB_REGISTER_FAIL_POINT(dev, register_after_queues, err,
5436 fail_cleanup);
5437
5438 if (msix > 1) {
5439 /*
5440 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5441 * aren't the default NULL implementation.
5442 */
5443 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5444 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5445 kobj_desc);
5446 if (kobj_method == &kobj_desc->deflt) {
5447 device_printf(dev,
5448 "MSI-X requires ifdi_rx_queue_intr_enable method");
5449 err = EOPNOTSUPP;
5450 goto fail_cleanup;
5451 }
5452 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5453 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5454 kobj_desc);
5455 if (kobj_method == &kobj_desc->deflt) {
5456 device_printf(dev,
5457 "MSI-X requires ifdi_tx_queue_intr_enable method");
5458 err = EOPNOTSUPP;
5459 goto fail_cleanup;
5460 }
5461
5462 /*
5463 * Assign the MSI-X vectors.
5464 * Note that the default NULL ifdi_msix_intr_assign method will
5465 * fail here, too.
5466 */
5467 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5468 if (err != 0) {
5469 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5470 err);
5471 goto fail_cleanup;
5472 }
5473 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5474 rid = 0;
5475 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5476 MPASS(msix == 1);
5477 rid = 1;
5478 }
5479 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5480 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5481 goto fail_cleanup;
5482 }
5483 } else {
5484 device_printf(dev,
5485 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5486 err = ENODEV;
5487 goto fail_cleanup;
5488 }
5489
5490 /*
5491 * It prevents a double-locking panic with iflib_media_status when
5492 * the driver loads.
5493 */
5494 CTX_UNLOCK(ctx);
5495 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5496 CTX_LOCK(ctx);
5497
5498 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5499 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5500 goto fail_detach;
5501 }
5502 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_post, err,
5503 fail_detach);
5504
5505 /*
5506 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5507 * This must appear after the call to ether_ifattach() because
5508 * ether_ifattach() sets if_hdrlen to the default value.
5509 */
5510 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5511 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5512
5513 if ((err = iflib_netmap_attach(ctx))) {
5514 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5515 goto fail_detach;
5516 }
5517 *ctxp = ctx;
5518
5519 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5520
5521 iflib_add_device_sysctl_post(ctx);
5522 iflib_add_pfil(ctx);
5523 ctx->ifc_flags |= IFC_INIT_DONE;
5524 CTX_UNLOCK(ctx);
5525 IFNET_WUNLOCK();
5526
5527 /* Create led(4) devices if the driver defined the method */
5528 kobj_desc = &ifdi_led_func_desc;
5529 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5530 kobj_desc);
5531 if (kobj_method != &kobj_desc->deflt && IFDI_LED_SUPPORTED(ctx))
5532 iflib_led_create(ctx);
5533
5534 return (0);
5535
5536 fail_detach:
5537 STATE_LOCK(ctx);
5538 ctx->ifc_flags |= IFC_IN_DETACH;
5539 STATE_UNLOCK(ctx);
5540 /* Tasks may need either lock; ether_ifdetach() takes ifnet_detach_sx. */
5541 CTX_UNLOCK(ctx);
5542 IFNET_WUNLOCK();
5543 taskqueue_drain_all(ctx->ifc_tq);
5544 #ifdef PCI_IOV
5545 /*
5546 * IFDI_ATTACH_POST may have registered an SR-IOV schema. Match the
5547 * normal deregistration order so a failed attach cannot leave a stale
5548 * /dev/iov node behind. device_attach() holds Giant throughout this
5549 * path, so an IOV configuration cannot race the detach.
5550 */
5551 if (!CTX_IS_VF(ctx)) {
5552 iov_error = pci_iov_detach(dev);
5553 if (iov_error != 0)
5554 device_printf(dev, "Could not detach SR-IOV after "
5555 "attach failure: %d\n", iov_error);
5556 }
5557 #endif
5558 ether_ifdetach(ctx->ifc_ifp);
5559 IFNET_WLOCK();
5560 CTX_LOCK(ctx);
5561 goto fail_cleanup_detaching;
5562
5563 fail_cleanup:
5564 STATE_LOCK(ctx);
5565 ctx->ifc_flags |= IFC_IN_DETACH;
5566 STATE_UNLOCK(ctx);
5567
5568 fail_cleanup_detaching:
5569 /*
5570 * The pre-attach sysctls contain pointers into ctx. Remove them on
5571 * every registration failure before iflib_deregister() frees ctx.
5572 */
5573 if (ctx->ifc_sysctl_node != NULL) {
5574 sysctl_ctx_free(&ctx->ifc_sysctl_ctx);
5575 ctx->ifc_sysctl_node = NULL;
5576 }
5577
5578 if (ctx->ifc_tq != NULL) {
5579 /*
5580 * Drain without holding the ifnet or context locks so configuration
5581 * tasks can run to completion. On fail_detach a second drain also
5582 * catches tasks queued during the first drain.
5583 */
5584 CTX_UNLOCK(ctx);
5585 IFNET_WUNLOCK();
5586 taskqueue_drain_all(ctx->ifc_tq);
5587 IFNET_WLOCK();
5588 CTX_LOCK(ctx);
5589 }
5590
5591 if (queues_allocated) {
5592 iflib_tqg_detach(ctx);
5593 iflib_tx_structures_free(ctx);
5594 iflib_rx_structures_free(ctx);
5595 }
5596
5597 /*
5598 * A successful IFDI_ATTACH_PRE must be matched by IFDI_DETACH, even
5599 * when registration fails before queue allocation. Match
5600 * iflib_device_deregister by detaching before taskqueue_free, and avoid
5601 * holding IFNET_WLOCK across driver detach (LinuxKPI workqueue drain).
5602 */
5603 if (attach_pre_succeeded) {
5604 IFNET_WUNLOCK();
5605 IFDI_DETACH(ctx);
5606 if (queues_allocated)
5607 IFDI_QUEUES_FREE(ctx);
5608 /* Reacquire the global lock before the context lock. */
5609 CTX_UNLOCK(ctx);
5610 IFNET_WLOCK();
5611 CTX_LOCK(ctx);
5612 }
5613 if (ctx->ifc_tq != NULL) {
5614 taskqueue_free(ctx->ifc_tq);
5615 ctx->ifc_tq = NULL;
5616 }
5617 if (intr_allocated)
5618 iflib_free_intr_mem(ctx);
5619
5620 CTX_UNLOCK(ctx);
5621 IFNET_WUNLOCK();
5622 iflib_deregister(ctx);
5623 device_set_softc(ctx->ifc_dev, NULL);
5624 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5625 free(ctx->ifc_softc, M_IFLIB);
5626 unref_ctx_core_offset(ctx);
5627 free(ctx, M_IFLIB);
5628 return (err);
5629 }
5630
5631 int
iflib_device_attach(device_t dev)5632 iflib_device_attach(device_t dev)
5633 {
5634 if_ctx_t ctx;
5635 if_shared_ctx_t sctx;
5636
5637 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5638 return (ENOTSUP);
5639
5640 pci_enable_busmaster(dev);
5641
5642 return (iflib_device_register(dev, NULL, sctx, &ctx));
5643 }
5644
5645 int
iflib_device_deregister(if_ctx_t ctx)5646 iflib_device_deregister(if_ctx_t ctx)
5647 {
5648 if_t ifp = ctx->ifc_ifp;
5649 device_t dev = ctx->ifc_dev;
5650
5651 sysctl_ctx_free(&ctx->ifc_sysctl_ctx);
5652 ctx->ifc_sysctl_node = NULL;
5653
5654 /* Make sure VLANS are not using driver */
5655 if (if_vlantrunkinuse(ifp)) {
5656 device_printf(dev, "Vlan in use, detach first\n");
5657 return (EBUSY);
5658 }
5659 #ifdef PCI_IOV
5660 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5661 device_printf(dev, "SR-IOV in use; detach first.\n");
5662 return (EBUSY);
5663 }
5664 #endif
5665
5666 STATE_LOCK(ctx);
5667 ctx->ifc_flags |= IFC_IN_DETACH;
5668 STATE_UNLOCK(ctx);
5669
5670 /* Unregister VLAN handlers before calling iflib_stop() */
5671 iflib_unregister_vlan_handlers(ctx);
5672
5673 iflib_netmap_detach(ifp);
5674 /*
5675 * A task that passed its IFC_IN_DETACH check before the flag was set
5676 * can still report a link change. Drain every private task before
5677 * ether_ifdetach() performs the final if_linktask drain. Drivers may
5678 * register their own link-related tasks on this taskqueue.
5679 */
5680 taskqueue_drain_all(ctx->ifc_tq);
5681 ether_ifdetach(ifp);
5682
5683 CTX_LOCK(ctx);
5684 iflib_stop(ctx);
5685 CTX_UNLOCK(ctx);
5686
5687 iflib_rem_pfil(ctx);
5688 if (ctx->ifc_led_dev != NULL) {
5689 led_destroy(ctx->ifc_led_dev);
5690 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_led_task);
5691 }
5692
5693 iflib_tqg_detach(ctx);
5694 iflib_tx_structures_free(ctx);
5695 iflib_rx_structures_free(ctx);
5696
5697 CTX_LOCK(ctx);
5698 IFDI_DETACH(ctx);
5699 IFDI_QUEUES_FREE(ctx);
5700 CTX_UNLOCK(ctx);
5701
5702 taskqueue_free(ctx->ifc_tq);
5703 ctx->ifc_tq = NULL;
5704
5705 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5706 iflib_free_intr_mem(ctx);
5707
5708 bus_generic_detach(dev);
5709
5710 iflib_deregister(ctx);
5711
5712 device_set_softc(ctx->ifc_dev, NULL);
5713 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5714 free(ctx->ifc_softc, M_IFLIB);
5715 unref_ctx_core_offset(ctx);
5716 free(ctx, M_IFLIB);
5717 return (0);
5718 }
5719
5720 static void
iflib_tqg_detach(if_ctx_t ctx)5721 iflib_tqg_detach(if_ctx_t ctx)
5722 {
5723 iflib_txq_t txq;
5724 iflib_rxq_t rxq;
5725 int i;
5726 struct taskqgroup *tqg;
5727
5728 /* XXX drain any dependent tasks */
5729 tqg = qgroup_if_io_tqg;
5730 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5731 callout_drain(&txq->ift_timer);
5732 #ifdef DEV_NETMAP
5733 callout_drain(&txq->ift_netmap_timer);
5734 #endif /* DEV_NETMAP */
5735 if (txq->ift_task.gt_uniq != NULL)
5736 taskqgroup_detach(tqg, &txq->ift_task);
5737 }
5738 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5739 if (rxq->ifr_task.gt_uniq != NULL)
5740 taskqgroup_detach(tqg, &rxq->ifr_task);
5741 }
5742 }
5743
5744 static void
iflib_free_intr_mem(if_ctx_t ctx)5745 iflib_free_intr_mem(if_ctx_t ctx)
5746 {
5747
5748 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5749 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5750 }
5751 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5752 pci_release_msi(ctx->ifc_dev);
5753 }
5754 if (ctx->ifc_msix_mem != NULL) {
5755 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5756 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5757 ctx->ifc_msix_mem = NULL;
5758 }
5759 }
5760
5761 int
iflib_device_detach(device_t dev)5762 iflib_device_detach(device_t dev)
5763 {
5764 if_ctx_t ctx = device_get_softc(dev);
5765
5766 return (iflib_device_deregister(ctx));
5767 }
5768
5769 int
iflib_device_suspend(device_t dev)5770 iflib_device_suspend(device_t dev)
5771 {
5772 if_ctx_t ctx = device_get_softc(dev);
5773
5774 CTX_LOCK(ctx);
5775 IFDI_SUSPEND(ctx);
5776 CTX_UNLOCK(ctx);
5777
5778 return (bus_generic_suspend(dev));
5779 }
5780 int
iflib_device_shutdown(device_t dev)5781 iflib_device_shutdown(device_t dev)
5782 {
5783 if_ctx_t ctx = device_get_softc(dev);
5784
5785 CTX_LOCK(ctx);
5786 IFDI_SHUTDOWN(ctx);
5787 CTX_UNLOCK(ctx);
5788
5789 return (bus_generic_suspend(dev));
5790 }
5791
5792 int
iflib_device_resume(device_t dev)5793 iflib_device_resume(device_t dev)
5794 {
5795 if_ctx_t ctx = device_get_softc(dev);
5796 iflib_txq_t txq = ctx->ifc_txqs;
5797
5798 CTX_LOCK(ctx);
5799 IFDI_RESUME(ctx);
5800 iflib_if_init_locked(ctx);
5801 CTX_UNLOCK(ctx);
5802 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5803 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5804
5805 return (bus_generic_resume(dev));
5806 }
5807
5808 int
iflib_device_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * params)5809 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5810 {
5811 int error;
5812 if_ctx_t ctx = device_get_softc(dev);
5813
5814 CTX_LOCK(ctx);
5815 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5816 CTX_UNLOCK(ctx);
5817
5818 return (error);
5819 }
5820
5821 int
iflib_device_iov_init_restart(device_t dev,uint16_t num_vfs,const nvlist_t * params)5822 iflib_device_iov_init_restart(device_t dev, uint16_t num_vfs,
5823 const nvlist_t *params)
5824 {
5825 if_ctx_t ctx;
5826 if_t ifp;
5827 bool restart, running;
5828 int error;
5829
5830 ctx = device_get_softc(dev);
5831 ifp = ctx->ifc_ifp;
5832
5833 CTX_LOCK(ctx);
5834 /*
5835 * Drivers which change the PF queue layout need the complete iflib
5836 * stop/init sequence around their IOV callback when the interface is
5837 * active. An administratively-down interface has no live queues to
5838 * quiesce, and must remain down after the new layout is installed.
5839 * Keep the transition within one context-lock critical section.
5840 */
5841 restart = (if_getflags(ifp) & IFF_UP) != 0;
5842 running = (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;
5843 if (restart || running)
5844 iflib_stop(ctx);
5845 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5846 if (restart)
5847 iflib_init_locked(ctx);
5848 CTX_UNLOCK(ctx);
5849 return (error);
5850 }
5851
5852 void
iflib_device_iov_uninit(device_t dev)5853 iflib_device_iov_uninit(device_t dev)
5854 {
5855 if_ctx_t ctx = device_get_softc(dev);
5856
5857 CTX_LOCK(ctx);
5858 IFDI_IOV_UNINIT(ctx);
5859 CTX_UNLOCK(ctx);
5860 }
5861
5862 void
iflib_device_iov_uninit_restart(device_t dev)5863 iflib_device_iov_uninit_restart(device_t dev)
5864 {
5865 if_ctx_t ctx;
5866 bool restart;
5867
5868 ctx = device_get_softc(dev);
5869
5870 CTX_LOCK(ctx);
5871 /*
5872 * RUNNING can be clear while a watchdog reset is pending but the
5873 * hardware is still live. Always stop before the driver changes its
5874 * queue layout, and use IFF_UP only to preserve administrative state.
5875 */
5876 restart = (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0;
5877 iflib_stop(ctx);
5878 IFDI_IOV_UNINIT(ctx);
5879 if (restart)
5880 iflib_init_locked(ctx);
5881 CTX_UNLOCK(ctx);
5882 }
5883
5884 int
iflib_device_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * params)5885 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5886 {
5887 int error;
5888 if_ctx_t ctx = device_get_softc(dev);
5889
5890 CTX_LOCK(ctx);
5891 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5892 CTX_UNLOCK(ctx);
5893
5894 return (error);
5895 }
5896
5897 /*********************************************************************
5898 *
5899 * MODULE FUNCTION DEFINITIONS
5900 *
5901 **********************************************************************/
5902
5903 /*
5904 * - Start a fast taskqueue thread for each core
5905 * - Start a taskqueue for control operations
5906 */
5907 static int
iflib_module_init(void)5908 iflib_module_init(void)
5909 {
5910 iflib_timer_default = hz / 2;
5911 return (0);
5912 }
5913
5914 static int
iflib_module_event_handler(module_t mod,int what,void * arg)5915 iflib_module_event_handler(module_t mod, int what, void *arg)
5916 {
5917 int err;
5918
5919 switch (what) {
5920 case MOD_LOAD:
5921 if ((err = iflib_module_init()) != 0)
5922 return (err);
5923 break;
5924 case MOD_UNLOAD:
5925 return (EBUSY);
5926 default:
5927 return (EOPNOTSUPP);
5928 }
5929
5930 return (0);
5931 }
5932
5933 /*********************************************************************
5934 *
5935 * PUBLIC FUNCTION DEFINITIONS
5936 * ordered as in iflib.h
5937 *
5938 **********************************************************************/
5939
5940 static void
_iflib_assert(if_shared_ctx_t sctx)5941 _iflib_assert(if_shared_ctx_t sctx)
5942 {
5943 int i;
5944
5945 MPASS(sctx->isc_tx_maxsize);
5946 MPASS(sctx->isc_tx_maxsegsize);
5947
5948 MPASS(sctx->isc_rx_maxsize);
5949 MPASS(sctx->isc_rx_nsegments);
5950 MPASS(sctx->isc_rx_maxsegsize);
5951
5952 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5953 for (i = 0; i < sctx->isc_nrxqs; i++) {
5954 MPASS(sctx->isc_nrxd_min[i]);
5955 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5956 MPASS(sctx->isc_nrxd_max[i]);
5957 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5958 MPASS(sctx->isc_nrxd_default[i]);
5959 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5960 }
5961
5962 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5963 for (i = 0; i < sctx->isc_ntxqs; i++) {
5964 MPASS(sctx->isc_ntxd_min[i]);
5965 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5966 MPASS(sctx->isc_ntxd_max[i]);
5967 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5968 MPASS(sctx->isc_ntxd_default[i]);
5969 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5970 }
5971 }
5972
5973 static void
_iflib_pre_assert(if_softc_ctx_t scctx)5974 _iflib_pre_assert(if_softc_ctx_t scctx)
5975 {
5976
5977 MPASS(scctx->isc_txrx->ift_txd_encap);
5978 MPASS(scctx->isc_txrx->ift_txd_flush);
5979 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5980 MPASS(scctx->isc_txrx->ift_rxd_available);
5981 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5982 MPASS(scctx->isc_txrx->ift_rxd_refill);
5983 MPASS(scctx->isc_txrx->ift_rxd_flush);
5984 }
5985
5986 static void
iflib_register(if_ctx_t ctx)5987 iflib_register(if_ctx_t ctx)
5988 {
5989 if_shared_ctx_t sctx = ctx->ifc_sctx;
5990 driver_t *driver = sctx->isc_driver;
5991 device_t dev = ctx->ifc_dev;
5992 if_t ifp;
5993
5994 _iflib_assert(sctx);
5995
5996 CTX_LOCK_INIT(ctx);
5997 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5998 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev);
5999
6000 /*
6001 * Initialize our context's device specific methods
6002 */
6003 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
6004 kobj_class_compile((kobj_class_t) driver);
6005
6006 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
6007 if_setsoftc(ifp, ctx);
6008 if_setdev(ifp, dev);
6009 if_setinitfn(ifp, iflib_if_init);
6010 if_setioctlfn(ifp, iflib_if_ioctl);
6011 #ifdef ALTQ
6012 if_setstartfn(ifp, iflib_altq_if_start);
6013 if_settransmitfn(ifp, iflib_altq_if_transmit);
6014 if_setsendqready(ifp);
6015 #else
6016 if_settransmitfn(ifp, iflib_if_transmit);
6017 #endif
6018 if_setqflushfn(ifp, iflib_if_qflush);
6019 if_setgetcounterfn(ifp, iflib_if_get_counter);
6020 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
6021 ctx->ifc_vlan_attach_event =
6022 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
6023 EVENTHANDLER_PRI_FIRST);
6024 ctx->ifc_vlan_detach_event =
6025 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
6026 EVENTHANDLER_PRI_FIRST);
6027
6028 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
6029 ctx->ifc_mediap = &ctx->ifc_media;
6030 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
6031 iflib_media_change, iflib_media_status);
6032 }
6033 }
6034
6035 static void
iflib_unregister_vlan_handlers(if_ctx_t ctx)6036 iflib_unregister_vlan_handlers(if_ctx_t ctx)
6037 {
6038 /* Unregister VLAN events */
6039 if (ctx->ifc_vlan_attach_event != NULL) {
6040 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
6041 ctx->ifc_vlan_attach_event = NULL;
6042 }
6043 if (ctx->ifc_vlan_detach_event != NULL) {
6044 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
6045 ctx->ifc_vlan_detach_event = NULL;
6046 }
6047
6048 }
6049
6050 static void
iflib_deregister(if_ctx_t ctx)6051 iflib_deregister(if_ctx_t ctx)
6052 {
6053 if_t ifp = ctx->ifc_ifp;
6054
6055 /* Remove all media */
6056 ifmedia_removeall(&ctx->ifc_media);
6057
6058 /* Ensure that VLAN event handlers are unregistered */
6059 iflib_unregister_vlan_handlers(ctx);
6060
6061 /* Release kobject reference */
6062 kobj_delete((kobj_t) ctx, NULL);
6063
6064 /* Free the ifnet structure */
6065 if_free(ifp);
6066
6067 STATE_LOCK_DESTROY(ctx);
6068
6069 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
6070 CTX_LOCK_DESTROY(ctx);
6071 }
6072
6073 static int
iflib_queues_alloc(if_ctx_t ctx)6074 iflib_queues_alloc(if_ctx_t ctx)
6075 {
6076 if_shared_ctx_t sctx = ctx->ifc_sctx;
6077 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6078 device_t dev = ctx->ifc_dev;
6079 int nrxqsets = scctx->isc_nrxqsets;
6080 int ntxqsets = scctx->isc_ntxqsets;
6081 iflib_txq_t txq;
6082 iflib_rxq_t rxq;
6083 iflib_fl_t fl = NULL;
6084 int i, j, cpu, err, txconf, rxconf;
6085 iflib_dma_info_t ifdip;
6086 uint32_t *rxqsizes = scctx->isc_rxqsizes;
6087 uint32_t *txqsizes = scctx->isc_txqsizes;
6088 uint8_t nrxqs = sctx->isc_nrxqs;
6089 uint8_t ntxqs = sctx->isc_ntxqs;
6090 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
6091 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
6092 caddr_t *vaddrs;
6093 uint64_t *paddrs;
6094
6095 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
6096 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
6097 KASSERT(nrxqs >= fl_offset + nfree_lists,
6098 ("there must be at least a rxq for each free list"));
6099
6100 /* Allocate the TX ring struct memory */
6101 if (!(ctx->ifc_txqs =
6102 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
6103 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
6104 device_printf(dev, "Unable to allocate TX ring memory\n");
6105 err = ENOMEM;
6106 goto fail;
6107 }
6108
6109 /* Now allocate the RX */
6110 if (!(ctx->ifc_rxqs =
6111 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
6112 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
6113 device_printf(dev, "Unable to allocate RX ring memory\n");
6114 err = ENOMEM;
6115 goto rx_fail;
6116 }
6117
6118 txq = ctx->ifc_txqs;
6119 rxq = ctx->ifc_rxqs;
6120
6121 /*
6122 * XXX handle allocation failure
6123 */
6124 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
6125 /* Set up some basics */
6126
6127 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
6128 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
6129 device_printf(dev,
6130 "Unable to allocate TX DMA info memory\n");
6131 err = ENOMEM;
6132 goto err_tx_desc;
6133 }
6134 txq->ift_ifdi = ifdip;
6135 for (j = 0; j < ntxqs; j++, ifdip++) {
6136 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
6137 device_printf(dev,
6138 "Unable to allocate TX descriptors\n");
6139 err = ENOMEM;
6140 goto err_tx_desc;
6141 }
6142 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
6143 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
6144 }
6145 txq->ift_ctx = ctx;
6146 txq->ift_id = i;
6147 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
6148 txq->ift_br_offset = 1;
6149 } else {
6150 txq->ift_br_offset = 0;
6151 }
6152
6153 if (iflib_txsd_alloc(txq)) {
6154 device_printf(dev, "Critical Failure setting up TX buffers\n");
6155 err = ENOMEM;
6156 goto err_tx_desc;
6157 }
6158
6159 /* Initialize the TX lock */
6160 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
6161 device_get_nameunit(dev), txq->ift_id);
6162 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
6163 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
6164 txq->ift_timer.c_cpu = cpu;
6165 #ifdef DEV_NETMAP
6166 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
6167 txq->ift_netmap_timer.c_cpu = cpu;
6168 #endif /* DEV_NETMAP */
6169
6170 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
6171 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
6172 if (err) {
6173 /* XXX free any allocated rings */
6174 device_printf(dev, "Unable to allocate buf_ring\n");
6175 goto err_tx_desc;
6176 }
6177 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
6178 }
6179
6180 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
6181 /* Set up some basics */
6182 callout_init(&rxq->ifr_watchdog, 1);
6183
6184 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
6185 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
6186 device_printf(dev,
6187 "Unable to allocate RX DMA info memory\n");
6188 err = ENOMEM;
6189 goto err_tx_desc;
6190 }
6191
6192 rxq->ifr_ifdi = ifdip;
6193 /* XXX this needs to be changed if #rx queues != #tx queues */
6194 rxq->ifr_ntxqirq = 1;
6195 rxq->ifr_txqid[0] = i;
6196 for (j = 0; j < nrxqs; j++, ifdip++) {
6197 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
6198 device_printf(dev,
6199 "Unable to allocate RX descriptors\n");
6200 err = ENOMEM;
6201 goto err_tx_desc;
6202 }
6203 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
6204 }
6205 rxq->ifr_ctx = ctx;
6206 rxq->ifr_id = i;
6207 rxq->ifr_fl_offset = fl_offset;
6208 rxq->ifr_nfl = nfree_lists;
6209 if (!(fl =
6210 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
6211 device_printf(dev, "Unable to allocate free list memory\n");
6212 err = ENOMEM;
6213 goto err_tx_desc;
6214 }
6215 rxq->ifr_fl = fl;
6216 for (j = 0; j < nfree_lists; j++) {
6217 fl[j].ifl_rxq = rxq;
6218 fl[j].ifl_id = j;
6219 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
6220 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
6221 }
6222 /* Allocate receive buffers for the ring */
6223 if (iflib_rxsd_alloc(rxq)) {
6224 device_printf(dev,
6225 "Critical Failure setting up receive buffers\n");
6226 err = ENOMEM;
6227 goto err_rx_desc;
6228 }
6229
6230 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
6231 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
6232 M_WAITOK);
6233 }
6234
6235 /* TXQs */
6236 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK);
6237 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK);
6238 for (i = 0; i < ntxqsets; i++) {
6239 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
6240
6241 for (j = 0; j < ntxqs; j++, di++) {
6242 vaddrs[i * ntxqs + j] = di->idi_vaddr;
6243 paddrs[i * ntxqs + j] = di->idi_paddr;
6244 }
6245 }
6246 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
6247 device_printf(ctx->ifc_dev,
6248 "Unable to allocate device TX queue\n");
6249 iflib_tx_structures_free(ctx);
6250 free(vaddrs, M_IFLIB);
6251 free(paddrs, M_IFLIB);
6252 goto err_rx_desc;
6253 }
6254 free(vaddrs, M_IFLIB);
6255 free(paddrs, M_IFLIB);
6256
6257 /* RXQs */
6258 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK);
6259 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK);
6260 for (i = 0; i < nrxqsets; i++) {
6261 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
6262
6263 for (j = 0; j < nrxqs; j++, di++) {
6264 vaddrs[i * nrxqs + j] = di->idi_vaddr;
6265 paddrs[i * nrxqs + j] = di->idi_paddr;
6266 }
6267 }
6268 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
6269 device_printf(ctx->ifc_dev,
6270 "Unable to allocate device RX queue\n");
6271 iflib_tx_structures_free(ctx);
6272 free(vaddrs, M_IFLIB);
6273 free(paddrs, M_IFLIB);
6274 goto err_rx_desc;
6275 }
6276 free(vaddrs, M_IFLIB);
6277 free(paddrs, M_IFLIB);
6278
6279 return (0);
6280
6281 /* XXX handle allocation failure changes */
6282 err_rx_desc:
6283 err_tx_desc:
6284 rx_fail:
6285 if (ctx->ifc_rxqs != NULL)
6286 free(ctx->ifc_rxqs, M_IFLIB);
6287 ctx->ifc_rxqs = NULL;
6288 if (ctx->ifc_txqs != NULL)
6289 free(ctx->ifc_txqs, M_IFLIB);
6290 ctx->ifc_txqs = NULL;
6291 fail:
6292 return (err);
6293 }
6294
6295 static int
iflib_tx_structures_setup(if_ctx_t ctx)6296 iflib_tx_structures_setup(if_ctx_t ctx)
6297 {
6298 iflib_txq_t txq = ctx->ifc_txqs;
6299 int i;
6300
6301 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
6302 iflib_txq_setup(txq);
6303
6304 return (0);
6305 }
6306
6307 static void
iflib_tx_structures_free(if_ctx_t ctx)6308 iflib_tx_structures_free(if_ctx_t ctx)
6309 {
6310 iflib_txq_t txq = ctx->ifc_txqs;
6311 if_shared_ctx_t sctx = ctx->ifc_sctx;
6312 int i, j;
6313
6314 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6315 for (j = 0; j < sctx->isc_ntxqs; j++)
6316 iflib_dma_free(&txq->ift_ifdi[j]);
6317 iflib_txq_destroy(txq);
6318 }
6319 free(ctx->ifc_txqs, M_IFLIB);
6320 ctx->ifc_txqs = NULL;
6321 }
6322
6323 /*********************************************************************
6324 *
6325 * Initialize all receive rings.
6326 *
6327 **********************************************************************/
6328 static int
iflib_rx_structures_setup(if_ctx_t ctx)6329 iflib_rx_structures_setup(if_ctx_t ctx)
6330 {
6331 iflib_rxq_t rxq = ctx->ifc_rxqs;
6332 int q;
6333 #if defined(INET6) || defined(INET)
6334 int err, i;
6335 #endif
6336
6337 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
6338 #if defined(INET6) || defined(INET)
6339 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
6340 TCP_LRO_ENTRIES, min(1024,
6341 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
6342 if (err != 0) {
6343 device_printf(ctx->ifc_dev,
6344 "LRO Initialization failed!\n");
6345 goto fail;
6346 }
6347 #endif
6348 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
6349 }
6350 return (0);
6351 #if defined(INET6) || defined(INET)
6352 fail:
6353 /*
6354 * Free LRO resources allocated so far, we will only handle
6355 * the rings that completed, the failing case will have
6356 * cleaned up for itself. 'q' failed, so its the terminus.
6357 */
6358 rxq = ctx->ifc_rxqs;
6359 for (i = 0; i < q; ++i, rxq++) {
6360 tcp_lro_free(&rxq->ifr_lc);
6361 }
6362 return (err);
6363 #endif
6364 }
6365
6366 /*********************************************************************
6367 *
6368 * Free all receive rings.
6369 *
6370 **********************************************************************/
6371 static void
iflib_rx_structures_free(if_ctx_t ctx)6372 iflib_rx_structures_free(if_ctx_t ctx)
6373 {
6374 iflib_rxq_t rxq = ctx->ifc_rxqs;
6375 if_shared_ctx_t sctx = ctx->ifc_sctx;
6376 int i, j;
6377
6378 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
6379 for (j = 0; j < sctx->isc_nrxqs; j++)
6380 iflib_dma_free(&rxq->ifr_ifdi[j]);
6381 iflib_rx_sds_free(rxq);
6382 #if defined(INET6) || defined(INET)
6383 tcp_lro_free(&rxq->ifr_lc);
6384 #endif
6385 }
6386 free(ctx->ifc_rxqs, M_IFLIB);
6387 ctx->ifc_rxqs = NULL;
6388 }
6389
6390 static int
iflib_qset_structures_setup(if_ctx_t ctx)6391 iflib_qset_structures_setup(if_ctx_t ctx)
6392 {
6393 int err;
6394
6395 /*
6396 * It is expected that the caller takes care of freeing queues if this
6397 * fails.
6398 */
6399 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6400 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6401 return (err);
6402 }
6403
6404 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6405 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6406
6407 return (err);
6408 }
6409
6410 int
iflib_irq_alloc(if_ctx_t ctx,if_irq_t irq,int rid,driver_filter_t filter,void * filter_arg,driver_intr_t handler,void * arg,const char * name)6411 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6412 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6413 {
6414
6415 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6416 }
6417
6418 /* Just to avoid copy/paste */
6419 static inline int
iflib_irq_set_affinity(if_ctx_t ctx,if_irq_t irq,iflib_intr_type_t type,int qid,struct grouptask * gtask,struct taskqgroup * tqg,void * uniq,const char * name)6420 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6421 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6422 const char *name)
6423 {
6424 device_t dev;
6425 unsigned int base_cpuid, cpuid;
6426 int err;
6427
6428 dev = ctx->ifc_dev;
6429 base_cpuid = ctx->ifc_sysctl_core_offset;
6430 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6431 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6432 irq ? irq->ii_res : NULL, name);
6433 if (err) {
6434 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6435 return (err);
6436 }
6437 #ifdef notyet
6438 if (cpuid > ctx->ifc_cpuid_highest)
6439 ctx->ifc_cpuid_highest = cpuid;
6440 #endif
6441 return (0);
6442 }
6443
6444 /*
6445 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware
6446 * resources.
6447 *
6448 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX
6449 * only.
6450 *
6451 * XXX: Could be removed if subctx's dev has its intr resource allocation
6452 * methods replaced with custom ones?
6453 */
6454 int
iflib_irq_alloc_generic_subctx(if_ctx_t ctx,if_ctx_t subctx,if_irq_t irq,int rid,iflib_intr_type_t type,driver_filter_t * filter,void * filter_arg,int qid,const char * name)6455 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq,
6456 int rid, iflib_intr_type_t type,
6457 driver_filter_t *filter, void *filter_arg,
6458 int qid, const char *name)
6459 {
6460 device_t dev, subdev;
6461 struct grouptask *gtask;
6462 struct taskqgroup *tqg;
6463 iflib_filter_info_t info;
6464 gtask_fn_t *fn;
6465 int tqrid, err;
6466 driver_filter_t *intr_fast;
6467 void *q;
6468
6469 MPASS(ctx != NULL);
6470 MPASS(subctx != NULL);
6471
6472 tqrid = rid;
6473 dev = ctx->ifc_dev;
6474 subdev = subctx->ifc_dev;
6475
6476 switch (type) {
6477 case IFLIB_INTR_RXTX:
6478 q = &subctx->ifc_rxqs[qid];
6479 info = &subctx->ifc_rxqs[qid].ifr_filter_info;
6480 gtask = &subctx->ifc_rxqs[qid].ifr_task;
6481 tqg = qgroup_if_io_tqg;
6482 fn = _task_fn_rx;
6483 intr_fast = iflib_fast_intr_rxtx;
6484 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6485 break;
6486 default:
6487 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n",
6488 __func__, device_get_nameunit(subdev), type);
6489 return (EINVAL);
6490 }
6491
6492 info->ifi_filter = filter;
6493 info->ifi_filter_arg = filter_arg;
6494 info->ifi_task = gtask;
6495 info->ifi_ctx = q;
6496
6497 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6498
6499 /* Allocate interrupts from hardware using parent context */
6500 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6501 if (err != 0) {
6502 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n",
6503 device_get_nameunit(subdev), err);
6504 return (err);
6505 }
6506
6507 if (tqrid != -1) {
6508 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6509 name);
6510 if (err)
6511 return (err);
6512 } else {
6513 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6514 }
6515
6516 return (0);
6517 }
6518
6519 int
iflib_irq_alloc_generic(if_ctx_t ctx,if_irq_t irq,int rid,iflib_intr_type_t type,driver_filter_t * filter,void * filter_arg,int qid,const char * name)6520 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6521 iflib_intr_type_t type, driver_filter_t *filter,
6522 void *filter_arg, int qid, const char *name)
6523 {
6524 device_t dev;
6525 struct grouptask *gtask;
6526 struct taskqgroup *tqg;
6527 iflib_filter_info_t info;
6528 gtask_fn_t *fn;
6529 int tqrid, err;
6530 driver_filter_t *intr_fast;
6531 void *q;
6532
6533 info = &ctx->ifc_filter_info;
6534 tqrid = rid;
6535
6536 switch (type) {
6537 /* XXX merge tx/rx for netmap? */
6538 case IFLIB_INTR_TX:
6539 q = &ctx->ifc_txqs[qid];
6540 info = &ctx->ifc_txqs[qid].ift_filter_info;
6541 gtask = &ctx->ifc_txqs[qid].ift_task;
6542 tqg = qgroup_if_io_tqg;
6543 fn = _task_fn_tx;
6544 intr_fast = iflib_fast_intr;
6545 GROUPTASK_INIT(gtask, 0, fn, q);
6546 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6547 break;
6548 case IFLIB_INTR_RX:
6549 q = &ctx->ifc_rxqs[qid];
6550 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6551 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6552 tqg = qgroup_if_io_tqg;
6553 fn = _task_fn_rx;
6554 intr_fast = iflib_fast_intr;
6555 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6556 break;
6557 case IFLIB_INTR_RXTX:
6558 q = &ctx->ifc_rxqs[qid];
6559 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6560 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6561 tqg = qgroup_if_io_tqg;
6562 fn = _task_fn_rx;
6563 intr_fast = iflib_fast_intr_rxtx;
6564 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6565 break;
6566 case IFLIB_INTR_ADMIN:
6567 q = ctx;
6568 tqrid = -1;
6569 info = &ctx->ifc_filter_info;
6570 gtask = NULL;
6571 intr_fast = iflib_fast_intr_ctx;
6572 break;
6573 default:
6574 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6575 __func__);
6576 return (EINVAL);
6577 }
6578
6579 info->ifi_filter = filter;
6580 info->ifi_filter_arg = filter_arg;
6581 info->ifi_task = gtask;
6582 info->ifi_ctx = q;
6583
6584 dev = ctx->ifc_dev;
6585 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6586 if (err != 0) {
6587 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6588 return (err);
6589 }
6590 if (type == IFLIB_INTR_ADMIN)
6591 return (0);
6592
6593 if (tqrid != -1) {
6594 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6595 name);
6596 if (err)
6597 return (err);
6598 } else {
6599 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6600 }
6601
6602 return (0);
6603 }
6604
6605 void
iflib_softirq_alloc_generic(if_ctx_t ctx,if_irq_t irq,iflib_intr_type_t type,void * arg,int qid,const char * name)6606 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6607 void *arg, int qid, const char *name)
6608 {
6609 device_t dev;
6610 struct grouptask *gtask;
6611 struct taskqgroup *tqg;
6612 gtask_fn_t *fn;
6613 void *q;
6614 int err;
6615
6616 switch (type) {
6617 case IFLIB_INTR_TX:
6618 q = &ctx->ifc_txqs[qid];
6619 gtask = &ctx->ifc_txqs[qid].ift_task;
6620 tqg = qgroup_if_io_tqg;
6621 fn = _task_fn_tx;
6622 GROUPTASK_INIT(gtask, 0, fn, q);
6623 break;
6624 case IFLIB_INTR_RX:
6625 q = &ctx->ifc_rxqs[qid];
6626 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6627 tqg = qgroup_if_io_tqg;
6628 fn = _task_fn_rx;
6629 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6630 break;
6631 case IFLIB_INTR_IOV:
6632 return;
6633 default:
6634 panic("unknown net intr type");
6635 }
6636 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6637 if (err) {
6638 dev = ctx->ifc_dev;
6639 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6640 name);
6641 }
6642 }
6643
6644 void
iflib_irq_free(if_ctx_t ctx,if_irq_t irq)6645 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6646 {
6647
6648 if (irq->ii_tag)
6649 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6650
6651 if (irq->ii_res)
6652 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6653 rman_get_rid(irq->ii_res), irq->ii_res);
6654 }
6655
6656 static int
iflib_legacy_setup(if_ctx_t ctx,driver_filter_t filter,void * filter_arg,int * rid,const char * name)6657 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6658 {
6659 iflib_txq_t txq = ctx->ifc_txqs;
6660 iflib_rxq_t rxq = ctx->ifc_rxqs;
6661 if_irq_t irq = &ctx->ifc_legacy_irq;
6662 iflib_filter_info_t info;
6663 device_t dev;
6664 struct grouptask *gtask;
6665 struct resource *res;
6666 int err, tqrid;
6667 bool rx_only;
6668
6669 info = &rxq->ifr_filter_info;
6670 gtask = &rxq->ifr_task;
6671 tqrid = *rid;
6672 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6673
6674 ctx->ifc_flags |= IFC_LEGACY;
6675 info->ifi_filter = filter;
6676 info->ifi_filter_arg = filter_arg;
6677 info->ifi_task = gtask;
6678 info->ifi_ctx = rxq;
6679
6680 dev = ctx->ifc_dev;
6681 /* We allocate a single interrupt resource */
6682 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr :
6683 iflib_fast_intr_rxtx, NULL, info, name);
6684 if (err != 0)
6685 return (err);
6686 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq);
6687 res = irq->ii_res;
6688 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name);
6689
6690 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6691 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6692 "tx");
6693 return (0);
6694 }
6695
6696 void
iflib_led_create(if_ctx_t ctx)6697 iflib_led_create(if_ctx_t ctx)
6698 {
6699
6700 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6701 device_get_nameunit(ctx->ifc_dev));
6702 }
6703
6704 void
iflib_tx_intr_deferred(if_ctx_t ctx,int txqid)6705 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6706 {
6707
6708 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6709 }
6710
6711 void
iflib_rx_intr_deferred(if_ctx_t ctx,int rxqid)6712 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6713 {
6714
6715 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6716 }
6717
6718 void
iflib_admin_intr_deferred(if_ctx_t ctx)6719 iflib_admin_intr_deferred(if_ctx_t ctx)
6720 {
6721
6722 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task);
6723 }
6724
6725 void
iflib_iov_intr_deferred(if_ctx_t ctx)6726 iflib_iov_intr_deferred(if_ctx_t ctx)
6727 {
6728
6729 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task);
6730 }
6731
6732 void
iflib_io_tqg_attach(struct grouptask * gt,void * uniq,int cpu,const char * name)6733 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6734 {
6735
6736 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6737 name);
6738 }
6739
6740 void
iflib_config_task_init(if_ctx_t ctx,struct task * config_task,task_fn_t * fn)6741 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn)
6742 {
6743 TASK_INIT(config_task, 0, fn, ctx);
6744 }
6745
6746 void
iflib_config_task_enqueue(if_ctx_t ctx,struct task * config_task)6747 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task)
6748 {
6749 taskqueue_enqueue(ctx->ifc_tq, config_task);
6750 }
6751
6752 void
iflib_link_state_change(if_ctx_t ctx,int link_state,uint64_t baudrate)6753 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6754 {
6755 if_t ifp = ctx->ifc_ifp;
6756
6757 if_setbaudrate(ifp, baudrate);
6758 if (baudrate >= IF_Gbps(10)) {
6759 STATE_LOCK(ctx);
6760 ctx->ifc_flags |= IFC_PREFETCH;
6761 STATE_UNLOCK(ctx);
6762 }
6763 ctx->ifc_link_state = link_state;
6764 if_link_state_change(ifp, link_state);
6765 }
6766
6767 static int
iflib_tx_credits_update(if_ctx_t ctx,iflib_txq_t txq)6768 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6769 {
6770 int credits;
6771 #ifdef INVARIANTS
6772 int credits_pre = txq->ift_cidx_processed;
6773 #endif
6774
6775 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6776 BUS_DMASYNC_POSTREAD);
6777 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6778 return (0);
6779
6780 txq->ift_processed += credits;
6781 txq->ift_cidx_processed += credits;
6782
6783 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6784 if (txq->ift_cidx_processed >= txq->ift_size)
6785 txq->ift_cidx_processed -= txq->ift_size;
6786 return (credits);
6787 }
6788
6789 static int
iflib_rxd_avail(if_ctx_t ctx,iflib_rxq_t rxq,qidx_t cidx,qidx_t budget)6790 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6791 {
6792 iflib_fl_t fl;
6793 u_int i;
6794
6795 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6796 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6797 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6798 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6799 budget));
6800 }
6801
6802 void
iflib_add_int_delay_sysctl(if_ctx_t ctx,const char * name,const char * description,if_int_delay_info_t info,int offset,int value)6803 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6804 const char *description, if_int_delay_info_t info,
6805 int offset, int value)
6806 {
6807 info->iidi_ctx = ctx;
6808 info->iidi_offset = offset;
6809 info->iidi_value = value;
6810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6811 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6812 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6813 info, 0, iflib_sysctl_int_delay, "I", description);
6814 }
6815
6816 struct sx *
iflib_ctx_lock_get(if_ctx_t ctx)6817 iflib_ctx_lock_get(if_ctx_t ctx)
6818 {
6819
6820 return (&ctx->ifc_ctx_sx);
6821 }
6822
6823 static int
iflib_msix_init(if_ctx_t ctx)6824 iflib_msix_init(if_ctx_t ctx)
6825 {
6826 device_t dev = ctx->ifc_dev;
6827 if_shared_ctx_t sctx = ctx->ifc_sctx;
6828 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6829 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6830 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6831
6832 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6833 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6834
6835 if (bootverbose)
6836 device_printf(dev, "msix_init qsets capped at %d\n",
6837 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6838
6839 /* Override by tuneable */
6840 if (scctx->isc_disable_msix)
6841 goto msi;
6842
6843 /* First try MSI-X */
6844 if ((msgs = pci_msix_count(dev)) == 0) {
6845 if (bootverbose)
6846 device_printf(dev, "MSI-X not supported or disabled\n");
6847 goto msi;
6848 }
6849
6850 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6851 /*
6852 * bar == -1 => "trust me I know what I'm doing"
6853 * Some drivers are for hardware that is so shoddily
6854 * documented that no one knows which bars are which
6855 * so the developer has to map all bars. This hack
6856 * allows shoddy garbage to use MSI-X in this framework.
6857 */
6858 if (bar != -1) {
6859 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6860 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6861 if (ctx->ifc_msix_mem == NULL) {
6862 device_printf(dev, "Unable to map MSI-X table\n");
6863 goto msi;
6864 }
6865 }
6866
6867 admincnt = sctx->isc_admin_intrcnt;
6868 #if IFLIB_DEBUG
6869 /* use only 1 qset in debug mode */
6870 queuemsgs = min(msgs - admincnt, 1);
6871 #else
6872 queuemsgs = msgs - admincnt;
6873 #endif
6874 #ifdef RSS
6875 queues = imin(queuemsgs, rss_getnumbuckets());
6876 #else
6877 queues = queuemsgs;
6878 #endif
6879 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6880 if (bootverbose)
6881 device_printf(dev,
6882 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6883 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6884 #ifdef RSS
6885 /* If we're doing RSS, clamp at the number of RSS buckets */
6886 if (queues > rss_getnumbuckets())
6887 queues = rss_getnumbuckets();
6888 #endif
6889 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6890 rx_queues = iflib_num_rx_queues;
6891 else
6892 rx_queues = queues;
6893
6894 if (rx_queues > scctx->isc_nrxqsets)
6895 rx_queues = scctx->isc_nrxqsets;
6896
6897 /*
6898 * We want this to be all logical CPUs by default
6899 */
6900 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6901 tx_queues = iflib_num_tx_queues;
6902 else
6903 tx_queues = mp_ncpus;
6904
6905 if (tx_queues > scctx->isc_ntxqsets)
6906 tx_queues = scctx->isc_ntxqsets;
6907
6908 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6909 #ifdef INVARIANTS
6910 if (tx_queues != rx_queues)
6911 device_printf(dev,
6912 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6913 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6914 #endif
6915 tx_queues = min(rx_queues, tx_queues);
6916 rx_queues = min(rx_queues, tx_queues);
6917 }
6918
6919 vectors = rx_queues + admincnt;
6920 if (msgs < vectors) {
6921 device_printf(dev,
6922 "insufficient number of MSI-X vectors "
6923 "(supported %d, need %d)\n", msgs, vectors);
6924 goto msi;
6925 }
6926
6927 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6928 tx_queues);
6929 msgs = vectors;
6930 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6931 if (vectors != msgs) {
6932 device_printf(dev,
6933 "Unable to allocate sufficient MSI-X vectors "
6934 "(got %d, need %d)\n", vectors, msgs);
6935 pci_release_msi(dev);
6936 if (bar != -1) {
6937 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6938 ctx->ifc_msix_mem);
6939 ctx->ifc_msix_mem = NULL;
6940 }
6941 goto msi;
6942 }
6943 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6944 vectors);
6945 scctx->isc_vectors = vectors;
6946 scctx->isc_nrxqsets = rx_queues;
6947 scctx->isc_ntxqsets = tx_queues;
6948 scctx->isc_intr = IFLIB_INTR_MSIX;
6949
6950 return (vectors);
6951 } else {
6952 device_printf(dev,
6953 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6954 err);
6955 if (bar != -1) {
6956 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6957 ctx->ifc_msix_mem);
6958 ctx->ifc_msix_mem = NULL;
6959 }
6960 }
6961
6962 msi:
6963 vectors = pci_msi_count(dev);
6964 scctx->isc_nrxqsets = 1;
6965 scctx->isc_ntxqsets = 1;
6966 scctx->isc_vectors = vectors;
6967 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6968 device_printf(dev, "Using an MSI interrupt\n");
6969 scctx->isc_intr = IFLIB_INTR_MSI;
6970 } else {
6971 scctx->isc_vectors = 1;
6972 device_printf(dev, "Using a Legacy interrupt\n");
6973 scctx->isc_intr = IFLIB_INTR_LEGACY;
6974 }
6975
6976 return (vectors);
6977 }
6978
6979 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6980
6981 static int
mp_ring_state_handler(SYSCTL_HANDLER_ARGS)6982 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6983 {
6984 int rc;
6985 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6986 struct sbuf *sb;
6987 const char *ring_state = "UNKNOWN";
6988
6989 /* XXX needed ? */
6990 rc = sysctl_wire_old_buffer(req, 0);
6991 MPASS(rc == 0);
6992 if (rc != 0)
6993 return (rc);
6994 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6995 MPASS(sb != NULL);
6996 if (sb == NULL)
6997 return (ENOMEM);
6998 if (state[3] <= 3)
6999 ring_state = ring_states[state[3]];
7000
7001 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
7002 state[0], state[1], state[2], ring_state);
7003 rc = sbuf_finish(sb);
7004 sbuf_delete(sb);
7005 return (rc);
7006 }
7007
7008 enum iflib_ndesc_handler {
7009 IFLIB_NTXD_HANDLER,
7010 IFLIB_NRXD_HANDLER,
7011 };
7012
7013 static int
mp_ndesc_handler(SYSCTL_HANDLER_ARGS)7014 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
7015 {
7016 if_ctx_t ctx = (void *)arg1;
7017 enum iflib_ndesc_handler type = arg2;
7018 char buf[256] = {0};
7019 qidx_t *ndesc;
7020 char *p, *next;
7021 int nqs, rc, i;
7022
7023 nqs = 8;
7024 switch (type) {
7025 case IFLIB_NTXD_HANDLER:
7026 ndesc = ctx->ifc_sysctl_ntxds;
7027 if (ctx->ifc_sctx)
7028 nqs = ctx->ifc_sctx->isc_ntxqs;
7029 break;
7030 case IFLIB_NRXD_HANDLER:
7031 ndesc = ctx->ifc_sysctl_nrxds;
7032 if (ctx->ifc_sctx)
7033 nqs = ctx->ifc_sctx->isc_nrxqs;
7034 break;
7035 default:
7036 printf("%s: unhandled type\n", __func__);
7037 return (EINVAL);
7038 }
7039 if (nqs == 0)
7040 nqs = 8;
7041
7042 for (i = 0; i < 8; i++) {
7043 if (i >= nqs)
7044 break;
7045 if (i)
7046 strcat(buf, ",");
7047 sprintf(strchr(buf, 0), "%d", ndesc[i]);
7048 }
7049
7050 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
7051 if (rc || req->newptr == NULL)
7052 return (rc);
7053
7054 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
7055 i++, p = strsep(&next, " ,")) {
7056 ndesc[i] = strtoul(p, NULL, 10);
7057 }
7058
7059 return (rc);
7060 }
7061
7062 static int
iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS)7063 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS)
7064 {
7065 if_ctx_t ctx = (void *)arg1;
7066 iflib_txq_t txq;
7067 int i, err;
7068 int thresh;
7069
7070 thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
7071 err = sysctl_handle_int(oidp, &thresh, arg2, req);
7072 if (err != 0) {
7073 return err;
7074 }
7075
7076 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh)
7077 return 0;
7078
7079 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) {
7080 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n",
7081 ctx->ifc_softc_ctx.isc_ntxd[0] / 2);
7082 return (EINVAL);
7083 }
7084
7085 ctx->ifc_sysctl_tx_reclaim_thresh = thresh;
7086 if (ctx->ifc_txqs == NULL)
7087 return (err);
7088
7089 txq = &ctx->ifc_txqs[0];
7090 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
7091 txq->ift_reclaim_thresh = thresh;
7092 }
7093 return (err);
7094 }
7095
7096 static int
iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS)7097 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS)
7098 {
7099 if_ctx_t ctx = (void *)arg1;
7100 iflib_txq_t txq;
7101 int i, err;
7102 int ticks;
7103
7104 ticks = ctx->ifc_sysctl_tx_reclaim_ticks;
7105 err = sysctl_handle_int(oidp, &ticks, arg2, req);
7106 if (err != 0) {
7107 return err;
7108 }
7109
7110 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks)
7111 return 0;
7112
7113 if (ticks > hz) {
7114 device_printf(ctx->ifc_dev,
7115 "TX Reclaim ticks must be <= hz (%d)\n", hz);
7116 return (EINVAL);
7117 }
7118
7119 ctx->ifc_sysctl_tx_reclaim_ticks = ticks;
7120 if (ctx->ifc_txqs == NULL)
7121 return (err);
7122
7123 txq = &ctx->ifc_txqs[0];
7124 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
7125 txq->ift_reclaim_ticks = ticks;
7126 }
7127 return (err);
7128 }
7129
7130 static int
iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS)7131 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS)
7132 {
7133 if_ctx_t ctx = (void *)arg1;
7134 iflib_txq_t txq;
7135 int i, err;
7136 int defer;
7137
7138 defer = ctx->ifc_sysctl_tx_defer_mfree;
7139 err = sysctl_handle_int(oidp, &defer, arg2, req);
7140 if (err != 0) {
7141 return err;
7142 }
7143
7144 if (defer == ctx->ifc_sysctl_tx_defer_mfree)
7145 return 0;
7146
7147 ctx->ifc_sysctl_tx_defer_mfree = defer;
7148 if (ctx->ifc_txqs == NULL)
7149 return (err);
7150
7151 txq = &ctx->ifc_txqs[0];
7152 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
7153 txq->ift_defer_mfree = defer;
7154 }
7155 return (err);
7156 }
7157
7158 #define NAME_BUFLEN 32
7159 static void
iflib_add_device_sysctl_pre(if_ctx_t ctx)7160 iflib_add_device_sysctl_pre(if_ctx_t ctx)
7161 {
7162 device_t dev = iflib_get_dev(ctx);
7163 struct sysctl_oid_list *child, *oid_list;
7164 struct sysctl_oid *node;
7165
7166 sysctl_ctx_init(&ctx->ifc_sysctl_ctx);
7167 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
7168 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child,
7169 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
7170 "IFLIB fields");
7171 oid_list = SYSCTL_CHILDREN(node);
7172
7173 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version",
7174 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version");
7175 SYSCTL_ADD_U32(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO,
7176 "tx_watchdog_events", CTLFLAG_RD, &ctx->ifc_tx_watchdog_events, 0,
7177 "TX watchdog resets initiated by iflib");
7178
7179 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx",
7180 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0,
7181 "use simple tx ring");
7182 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs",
7183 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
7184 "# of txqs to use, 0 => use default #");
7185 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs",
7186 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
7187 "# of rxqs to use, 0 => use default #");
7188 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable",
7189 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
7190 "permit #txq != #rxq");
7191 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix",
7192 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
7193 "disable MSI-X (default 0)");
7194 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget",
7195 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget");
7196 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate",
7197 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
7198 "cause TX to abdicate instead of running to completion");
7199 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
7200 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset",
7201 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
7202 "offset to start using cores at");
7203 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx",
7204 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
7205 "use separate cores for TX and RX");
7206 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores",
7207 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
7208 "try to make use of logical cores for TX and RX");
7209 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors",
7210 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0,
7211 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later");
7212 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors",
7213 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0,
7214 "total # of MSI-X vectors allocated by driver");
7215
7216 /* XXX change for per-queue sizes */
7217 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds",
7218 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
7219 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
7220 "list of # of TX descriptors to use, 0 = use default #");
7221 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds",
7222 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
7223 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
7224 "list of # of RX descriptors to use, 0 = use default #");
7225 }
7226
7227 static void
iflib_add_device_sysctl_post(if_ctx_t ctx)7228 iflib_add_device_sysctl_post(if_ctx_t ctx)
7229 {
7230 if_shared_ctx_t sctx = ctx->ifc_sctx;
7231 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
7232 struct sysctl_oid_list *child;
7233 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx;
7234 iflib_fl_t fl;
7235 iflib_txq_t txq;
7236 iflib_rxq_t rxq;
7237 int i, j;
7238 char namebuf[NAME_BUFLEN];
7239 char *qfmt;
7240 struct sysctl_oid *queue_node, *fl_node, *node;
7241 struct sysctl_oid_list *queue_list, *fl_list;
7242
7243 node = ctx->ifc_sysctl_node;
7244 child = SYSCTL_CHILDREN(node);
7245
7246 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh",
7247 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
7248 0, iflib_handle_tx_reclaim_thresh, "I",
7249 "Number of TX descs outstanding before reclaim is called");
7250
7251 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks",
7252 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
7253 0, iflib_handle_tx_reclaim_ticks, "I",
7254 "Number of ticks before a TX reclaim is forced");
7255
7256 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree",
7257 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
7258 0, iflib_handle_tx_defer_mfree, "I",
7259 "Free completed transmits outside of TX ring lock");
7260
7261 if (scctx->isc_ntxqsets > 100)
7262 qfmt = "txq%03d";
7263 else if (scctx->isc_ntxqsets > 10)
7264 qfmt = "txq%02d";
7265 else
7266 qfmt = "txq%d";
7267 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
7268 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
7269 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
7270 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
7271 queue_list = SYSCTL_CHILDREN(queue_node);
7272 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
7273 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0,
7274 "cpu this queue is bound to");
7275 #if MEMORY_LOGGING
7276 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
7277 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed");
7278 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
7279 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued");
7280 #endif
7281 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
7282 CTLFLAG_RD, &txq->ift_mbuf_defrag,
7283 "# of times m_defrag was called");
7284 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
7285 CTLFLAG_RD, &txq->ift_pullups,
7286 "# of times m_pullup was called");
7287 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7288 "mbuf_defrag_failed", CTLFLAG_RD,
7289 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
7290 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7291 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail,
7292 "# of times no descriptors were available");
7293 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7294 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed,
7295 "# of times DMA map failed");
7296 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7297 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig,
7298 "# of times txd_encap returned EFBIG");
7299 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7300 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup,
7301 "# of times map failed for other than EFBIG");
7302 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
7303 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index");
7304 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
7305 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index");
7306 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
7307 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed,
7308 1, "Consumer Index seen by credit update");
7309 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
7310 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use");
7311 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
7312 "txq_processed", CTLFLAG_RD, &txq->ift_processed,
7313 "descriptors procesed for clean");
7314 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
7315 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned");
7316 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
7317 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
7318 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
7319 mp_ring_state_handler, "A", "soft ring state");
7320 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7321 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues,
7322 "# of enqueues to the mp_ring for this queue");
7323 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7324 "r_drops", CTLFLAG_RD, &txq->ift_br->drops,
7325 "# of drops in the mp_ring for this queue");
7326 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7327 "r_starts", CTLFLAG_RD, &txq->ift_br->starts,
7328 "# of normal consumer starts in mp_ring for this queue");
7329 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7330 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls,
7331 "# of consumer stalls in the mp_ring for this queue");
7332 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7333 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts,
7334 "# of consumer restarts in the mp_ring for this queue");
7335 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
7336 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications,
7337 "# of consumer abdications in the mp_ring for this queue");
7338 }
7339
7340 if (scctx->isc_nrxqsets > 100)
7341 qfmt = "rxq%03d";
7342 else if (scctx->isc_nrxqsets > 10)
7343 qfmt = "rxq%02d";
7344 else
7345 qfmt = "rxq%d";
7346 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
7347 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
7348 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
7349 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
7350 queue_list = SYSCTL_CHILDREN(queue_node);
7351 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
7352 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0,
7353 "cpu this queue is bound to");
7354 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
7355 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
7356 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1,
7357 "Consumer Index");
7358 }
7359
7360 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
7361 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
7362 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list,
7363 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE,
7364 NULL, "freelist Name");
7365 fl_list = SYSCTL_CHILDREN(fl_node);
7366 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
7367 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index");
7368 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
7369 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index");
7370 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
7371 CTLFLAG_RD, &fl->ifl_credits, 1,
7372 "credits available");
7373 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
7374 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size");
7375 #if MEMORY_LOGGING
7376 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
7377 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued,
7378 "mbufs allocated");
7379 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
7380 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued,
7381 "mbufs freed");
7382 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
7383 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued,
7384 "clusters allocated");
7385 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
7386 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued,
7387 "clusters freed");
7388 #endif
7389 }
7390 }
7391
7392 }
7393
7394 void
iflib_request_reset(if_ctx_t ctx)7395 iflib_request_reset(if_ctx_t ctx)
7396 {
7397
7398 STATE_LOCK(ctx);
7399 ctx->ifc_flags |= IFC_DO_RESET;
7400 STATE_UNLOCK(ctx);
7401 }
7402
7403 void
iflib_request_reset_if_up(if_ctx_t ctx)7404 iflib_request_reset_if_up(if_ctx_t ctx)
7405 {
7406
7407 STATE_LOCK(ctx);
7408 ctx->ifc_flags |= IFC_DO_RESET_IF_UP;
7409 STATE_UNLOCK(ctx);
7410 }
7411
7412 void
iflib_init_failed(if_ctx_t ctx)7413 iflib_init_failed(if_ctx_t ctx)
7414 {
7415
7416 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED);
7417 STATE_LOCK(ctx);
7418 ctx->ifc_flags |= IFC_INIT_FAILED;
7419 STATE_UNLOCK(ctx);
7420 }
7421
7422 #ifndef __NO_STRICT_ALIGNMENT
7423 static struct mbuf *
iflib_fixup_rx(struct mbuf * m)7424 iflib_fixup_rx(struct mbuf *m)
7425 {
7426 struct mbuf *n;
7427
7428 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
7429 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
7430 m->m_data += ETHER_HDR_LEN;
7431 n = m;
7432 } else {
7433 MGETHDR(n, M_NOWAIT, MT_DATA);
7434 if (n == NULL) {
7435 m_freem(m);
7436 return (NULL);
7437 }
7438 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
7439 m->m_data += ETHER_HDR_LEN;
7440 m->m_len -= ETHER_HDR_LEN;
7441 n->m_len = ETHER_HDR_LEN;
7442 M_MOVE_PKTHDR(n, m);
7443 n->m_next = m;
7444 }
7445 return (n);
7446 }
7447 #endif
7448
7449 #ifdef DEBUGNET
7450 static void
iflib_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)7451 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7452 {
7453 if_ctx_t ctx;
7454
7455 ctx = if_getsoftc(ifp);
7456 CTX_LOCK(ctx);
7457 *nrxr = NRXQSETS(ctx);
7458 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7459 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7460 CTX_UNLOCK(ctx);
7461 }
7462
7463 static void
iflib_debugnet_event(if_t ifp,enum debugnet_ev event)7464 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7465 {
7466 if_ctx_t ctx;
7467 if_softc_ctx_t scctx;
7468 iflib_fl_t fl;
7469 iflib_rxq_t rxq;
7470 int i, j;
7471
7472 ctx = if_getsoftc(ifp);
7473 scctx = &ctx->ifc_softc_ctx;
7474
7475 switch (event) {
7476 case DEBUGNET_START:
7477 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7478 rxq = &ctx->ifc_rxqs[i];
7479 for (j = 0; j < rxq->ifr_nfl; j++) {
7480 fl = rxq->ifr_fl;
7481 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7482 }
7483 }
7484 iflib_no_tx_batch = 1;
7485 break;
7486 default:
7487 break;
7488 }
7489 }
7490
7491 static int
iflib_debugnet_transmit(if_t ifp,struct mbuf * m)7492 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7493 {
7494 if_ctx_t ctx;
7495 iflib_txq_t txq;
7496 int error;
7497 int bytes_sent = 0;
7498 int pkt_sent = 0;
7499
7500 ctx = if_getsoftc(ifp);
7501 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7502 IFF_DRV_RUNNING)
7503 return (EBUSY);
7504
7505 txq = &ctx->ifc_txqs[0];
7506 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent);
7507 if (error == 0)
7508 (void)iflib_txd_db_check(txq, true);
7509 return (error);
7510 }
7511
7512 static int
iflib_debugnet_poll(if_t ifp,int count)7513 iflib_debugnet_poll(if_t ifp, int count)
7514 {
7515 struct epoch_tracker et;
7516 if_ctx_t ctx;
7517 if_softc_ctx_t scctx;
7518 iflib_txq_t txq;
7519 int i;
7520
7521 ctx = if_getsoftc(ifp);
7522 scctx = &ctx->ifc_softc_ctx;
7523
7524 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7525 IFF_DRV_RUNNING)
7526 return (EBUSY);
7527
7528 txq = &ctx->ifc_txqs[0];
7529 (void)iflib_completed_tx_reclaim(txq, NULL);
7530
7531 NET_EPOCH_ENTER(et);
7532 for (i = 0; i < scctx->isc_nrxqsets; i++)
7533 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7534 NET_EPOCH_EXIT(et);
7535 return (0);
7536 }
7537 #endif /* DEBUGNET */
7538
7539 #ifndef ALTQ
7540 static inline iflib_txq_t
iflib_simple_select_queue(if_ctx_t ctx,struct mbuf * m)7541 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m)
7542 {
7543 int qidx;
7544
7545 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
7546 qidx = QIDX(ctx, m);
7547 else
7548 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1;
7549 return (&ctx->ifc_txqs[qidx]);
7550 }
7551
7552 static int
iflib_simple_transmit(if_t ifp,struct mbuf * m)7553 iflib_simple_transmit(if_t ifp, struct mbuf *m)
7554 {
7555 if_ctx_t ctx;
7556 iflib_txq_t txq;
7557 struct mbuf **m_defer;
7558 int error, i, reclaimable;
7559 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0;
7560
7561
7562 ctx = if_getsoftc(ifp);
7563 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0
7564 || !LINK_ACTIVE(ctx))) {
7565 DBG_COUNTER_INC(tx_frees);
7566 m_freem(m);
7567 return (ENETDOWN);
7568 }
7569
7570 txq = iflib_simple_select_queue(ctx, m);
7571 mtx_lock(&txq->ift_mtx);
7572 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent);
7573 if (error == 0) {
7574 mcast_sent += !!(m->m_flags & M_MCAST);
7575 (void)iflib_txd_db_check(txq, true);
7576 } else {
7577 if (error == ENOBUFS)
7578 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
7579 else
7580 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
7581 }
7582 m_defer = NULL;
7583 reclaimable = iflib_txq_can_reclaim(txq);
7584 if (reclaimable != 0) {
7585 /*
7586 * Try to set m_defer to the deferred mbuf reclaim array. If
7587 * we can, the frees will happen outside the tx lock. If we
7588 * can't, it means another thread is still proccessing frees.
7589 */
7590 if (txq->ift_defer_mfree &&
7591 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer,
7592 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) {
7593 m_defer = txq->ift_sds.ifsd_m_deferb;
7594 }
7595 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable);
7596 }
7597 mtx_unlock(&txq->ift_mtx);
7598
7599 /*
7600 * Process mbuf frees outside the tx lock
7601 */
7602 if (m_defer != NULL) {
7603 for (i = 0; m_defer[i] != NULL; i++) {
7604 m_freem(m_defer[i]);
7605 m_defer[i] = NULL;
7606 }
7607 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer,
7608 (uintptr_t)m_defer);
7609 }
7610 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
7611 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
7612 if (mcast_sent)
7613 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
7614
7615 return (error);
7616 }
7617 #endif
7618