1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/fpu/xstate.h>
18 #include <asm/intel_ds.h>
19 #include <asm/cpu.h>
20 #include <asm/msr.h>
21
22 /* To enable MSR tracing please use the generic trace points. */
23
24 /*
25 * | NHM/WSM | SNB |
26 * register -------------------------------
27 * | HT | no HT | HT | no HT |
28 *-----------------------------------------
29 * offcore | core | core | cpu | core |
30 * lbr_sel | core | core | cpu | core |
31 * ld_lat | cpu | core | cpu | core |
32 *-----------------------------------------
33 *
34 * Given that there is a small number of shared regs,
35 * we can pre-allocate their slot in the per-cpu
36 * per-core reg tables.
37 */
38 enum extra_reg_type {
39 EXTRA_REG_NONE = -1, /* not used */
40
41 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
42 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
43 EXTRA_REG_LBR = 2, /* lbr_select */
44 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
45 EXTRA_REG_FE = 4, /* fe_* */
46 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */
47 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */
48 EXTRA_REG_OMR_0 = 7, /* OMR 0 */
49 EXTRA_REG_OMR_1 = 8, /* OMR 1 */
50 EXTRA_REG_OMR_2 = 9, /* OMR 2 */
51 EXTRA_REG_OMR_3 = 10, /* OMR 3 */
52
53 EXTRA_REG_MAX /* number of entries needed */
54 };
55
56 struct event_constraint {
57 union {
58 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
59 u64 idxmsk64;
60 };
61 u64 code;
62 u64 cmask;
63 int weight;
64 int overlap;
65 int flags;
66 unsigned int size;
67 };
68
constraint_match(struct event_constraint * c,u64 ecode)69 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
70 {
71 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
72 }
73
74 #define PERF_ARCH(name, val) \
75 PERF_X86_EVENT_##name = val,
76
77 /*
78 * struct hw_perf_event.flags flags
79 */
80 enum {
81 #include "perf_event_flags.h"
82 };
83
84 #undef PERF_ARCH
85
86 #define PERF_ARCH(name, val) \
87 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \
88 PERF_X86_EVENT_##name);
89
90 #include "perf_event_flags.h"
91
92 #undef PERF_ARCH
93
is_topdown_count(struct perf_event * event)94 static inline bool is_topdown_count(struct perf_event *event)
95 {
96 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
97 }
98
is_metric_event(struct perf_event * event)99 static inline bool is_metric_event(struct perf_event *event)
100 {
101 u64 config = event->attr.config;
102
103 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
104 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
105 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
106 }
107
is_slots_event(struct perf_event * event)108 static inline bool is_slots_event(struct perf_event *event)
109 {
110 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
111 }
112
is_topdown_event(struct perf_event * event)113 static inline bool is_topdown_event(struct perf_event *event)
114 {
115 return is_metric_event(event) || is_slots_event(event);
116 }
117
118 int is_x86_event(struct perf_event *event);
119
check_leader_group(struct perf_event * leader,int flags)120 static inline bool check_leader_group(struct perf_event *leader, int flags)
121 {
122 return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
123 }
124
is_branch_counters_group(struct perf_event * event)125 static inline bool is_branch_counters_group(struct perf_event *event)
126 {
127 return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS);
128 }
129
is_pebs_counter_event_group(struct perf_event * event)130 static inline bool is_pebs_counter_event_group(struct perf_event *event)
131 {
132 return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
133 }
134
is_acr_event_group(struct perf_event * event)135 static inline bool is_acr_event_group(struct perf_event *event)
136 {
137 return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
138 }
139
140 struct amd_nb {
141 int nb_id; /* NorthBridge id */
142 int refcnt; /* reference count */
143 struct perf_event *owners[X86_PMC_IDX_MAX];
144 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
145 };
146
147 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
148 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
149 #define PEBS_OUTPUT_OFFSET 61
150 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
151 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
152 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
153
154 /*
155 * Flags PEBS can handle without an PMI.
156 *
157 * TID can only be handled by flushing at context switch.
158 * REGS_USER can be handled for events limited to ring 3.
159 *
160 */
161 #define LARGE_PEBS_FLAGS \
162 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
163 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
164 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
165 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
166 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
167 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
168 PERF_SAMPLE_WEIGHT_TYPE)
169
170 #define PEBS_GP_REGS \
171 ((1ULL << PERF_REG_X86_AX) | \
172 (1ULL << PERF_REG_X86_BX) | \
173 (1ULL << PERF_REG_X86_CX) | \
174 (1ULL << PERF_REG_X86_DX) | \
175 (1ULL << PERF_REG_X86_DI) | \
176 (1ULL << PERF_REG_X86_SI) | \
177 (1ULL << PERF_REG_X86_SP) | \
178 (1ULL << PERF_REG_X86_BP) | \
179 (1ULL << PERF_REG_X86_IP) | \
180 (1ULL << PERF_REG_X86_FLAGS) | \
181 (1ULL << PERF_REG_X86_R8) | \
182 (1ULL << PERF_REG_X86_R9) | \
183 (1ULL << PERF_REG_X86_R10) | \
184 (1ULL << PERF_REG_X86_R11) | \
185 (1ULL << PERF_REG_X86_R12) | \
186 (1ULL << PERF_REG_X86_R13) | \
187 (1ULL << PERF_REG_X86_R14) | \
188 (1ULL << PERF_REG_X86_R15))
189
190 /* user space rdpmc control values */
191 enum {
192 X86_USER_RDPMC_NEVER_ENABLE = 0,
193 X86_USER_RDPMC_CONDITIONAL_ENABLE = 1,
194 X86_USER_RDPMC_ALWAYS_ENABLE = 2,
195 };
196
197 /*
198 * Per register state.
199 */
200 struct er_account {
201 raw_spinlock_t lock; /* per-core: protect structure */
202 u64 config; /* extra MSR config */
203 u64 reg; /* extra MSR number */
204 atomic_t ref; /* reference count */
205 };
206
207 /*
208 * Per core/cpu state
209 *
210 * Used to coordinate shared registers between HT threads or
211 * among events on a single PMU.
212 */
213 struct intel_shared_regs {
214 struct er_account regs[EXTRA_REG_MAX];
215 int refcnt; /* per-core: #HT threads */
216 unsigned core_id; /* per-core: core id */
217 };
218
219 enum intel_excl_state_type {
220 INTEL_EXCL_UNUSED = 0, /* counter is unused */
221 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
222 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
223 };
224
225 struct intel_excl_states {
226 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
227 bool sched_started; /* true if scheduling has started */
228 };
229
230 struct intel_excl_cntrs {
231 raw_spinlock_t lock;
232
233 struct intel_excl_states states[2];
234
235 union {
236 u16 has_exclusive[2];
237 u32 exclusive_present;
238 };
239
240 int refcnt; /* per-core: #HT threads */
241 unsigned core_id; /* per-core: core id */
242 };
243
244 struct x86_perf_task_context;
245 #define MAX_LBR_ENTRIES 32
246
247 enum {
248 LBR_FORMAT_32 = 0x00,
249 LBR_FORMAT_LIP = 0x01,
250 LBR_FORMAT_EIP = 0x02,
251 LBR_FORMAT_EIP_FLAGS = 0x03,
252 LBR_FORMAT_EIP_FLAGS2 = 0x04,
253 LBR_FORMAT_INFO = 0x05,
254 LBR_FORMAT_TIME = 0x06,
255 LBR_FORMAT_INFO2 = 0x07,
256 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2,
257 };
258
259 enum {
260 X86_PERF_KFREE_SHARED = 0,
261 X86_PERF_KFREE_EXCL = 1,
262 X86_PERF_KFREE_MAX
263 };
264
265 struct cpu_hw_events {
266 /*
267 * Generic x86 PMC bits
268 */
269 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
270 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
271 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
272 int enabled;
273
274 int n_events; /* the # of events in the below arrays */
275 int n_added; /* the # last events in the below arrays;
276 they've never been enabled yet */
277 int n_txn; /* the # last events in the below arrays;
278 added in the current transaction */
279 int n_txn_pair;
280 int n_txn_metric;
281 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
282 u64 tags[X86_PMC_IDX_MAX];
283
284 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
285 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
286
287 int n_excl; /* the number of exclusive events */
288 int n_late_setup; /* the num of events needs late setup */
289
290 unsigned int txn_flags;
291 int is_fake;
292
293 /*
294 * Intel DebugStore bits
295 */
296 struct debug_store *ds;
297 void *ds_bts_vaddr;
298 /* DS based PEBS or arch-PEBS buffer address */
299 void *pebs_vaddr;
300 u64 pebs_enabled;
301 int n_pebs;
302 int n_large_pebs;
303 int n_pebs_via_pt;
304 int pebs_output;
305
306 /* Current super set of events hardware configuration */
307 u64 pebs_data_cfg;
308 u64 active_pebs_data_cfg;
309 int pebs_record_size;
310
311 /* Intel Fixed counter configuration */
312 u64 fixed_ctrl_val;
313 u64 active_fixed_ctrl_val;
314
315 /* Intel ACR configuration */
316 u64 acr_cfg_b[X86_PMC_IDX_MAX];
317 u64 acr_cfg_c[X86_PMC_IDX_MAX];
318 /* Cached CFG_C values */
319 u64 cfg_c_val[X86_PMC_IDX_MAX];
320
321 /*
322 * Intel LBR bits
323 */
324 int lbr_users;
325 int lbr_pebs_users;
326 struct perf_branch_stack lbr_stack;
327 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
328 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */
329 union {
330 struct er_account *lbr_sel;
331 struct er_account *lbr_ctl;
332 };
333 u64 br_sel;
334 void *last_task_ctx;
335 int last_log_id;
336 int lbr_select;
337 void *lbr_xsave;
338
339 /*
340 * Intel host/guest exclude bits
341 */
342 u64 intel_ctrl_guest_mask;
343 u64 intel_ctrl_host_mask;
344 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
345
346 /*
347 * Intel checkpoint mask
348 */
349 u64 intel_cp_status;
350
351 /*
352 * manage shared (per-core, per-cpu) registers
353 * used on Intel NHM/WSM/SNB
354 */
355 struct intel_shared_regs *shared_regs;
356 /*
357 * manage exclusive counter access between hyperthread
358 */
359 struct event_constraint *constraint_list; /* in enable order */
360 struct intel_excl_cntrs *excl_cntrs;
361 int excl_thread_id; /* 0 or 1 */
362
363 /*
364 * SKL TSX_FORCE_ABORT shadow
365 */
366 u64 tfa_shadow;
367
368 /*
369 * Perf Metrics
370 */
371 /* number of accepted metrics events */
372 int n_metric;
373
374 /*
375 * AMD specific bits
376 */
377 struct amd_nb *amd_nb;
378 int brs_active; /* BRS is enabled */
379
380 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
381 u64 perf_ctr_virt_mask;
382 int n_pair; /* Large increment events */
383
384 void *kfree_on_online[X86_PERF_KFREE_MAX];
385
386 struct pmu *pmu;
387 };
388
389 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
390 { .idxmsk64 = (n) }, \
391 .code = (c), \
392 .size = (e) - (c), \
393 .cmask = (m), \
394 .weight = (w), \
395 .overlap = (o), \
396 .flags = f, \
397 }
398
399 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
400 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
401
402 #define EVENT_CONSTRAINT(c, n, m) \
403 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
404
405 /*
406 * The constraint_match() function only works for 'simple' event codes
407 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
408 */
409 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
410 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
411
412 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
413 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
414 0, PERF_X86_EVENT_EXCL)
415
416 /*
417 * The overlap flag marks event constraints with overlapping counter
418 * masks. This is the case if the counter mask of such an event is not
419 * a subset of any other counter mask of a constraint with an equal or
420 * higher weight, e.g.:
421 *
422 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
423 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
424 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
425 *
426 * The event scheduler may not select the correct counter in the first
427 * cycle because it needs to know which subsequent events will be
428 * scheduled. It may fail to schedule the events then. So we set the
429 * overlap flag for such constraints to give the scheduler a hint which
430 * events to select for counter rescheduling.
431 *
432 * Care must be taken as the rescheduling algorithm is O(n!) which
433 * will increase scheduling cycles for an over-committed system
434 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
435 * and its counter masks must be kept at a minimum.
436 */
437 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
438 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
439
440 /*
441 * Constraint on the Event code.
442 */
443 #define INTEL_EVENT_CONSTRAINT(c, n) \
444 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
445
446 /*
447 * Constraint on a range of Event codes
448 */
449 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
450 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
451
452 /*
453 * Constraint on the Event code + UMask + fixed-mask
454 *
455 * filter mask to validate fixed counter events.
456 * the following filters disqualify for fixed counters:
457 * - inv
458 * - edge
459 * - cnt-mask
460 * - in_tx
461 * - in_tx_checkpointed
462 * The other filters are supported by fixed counters.
463 * The any-thread option is supported starting with v3.
464 */
465 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
466 #define FIXED_EVENT_CONSTRAINT(c, n) \
467 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
468
469 /*
470 * The special metric counters do not actually exist. They are calculated from
471 * the combination of the FxCtr3 + MSR_PERF_METRICS.
472 *
473 * The special metric counters are mapped to a dummy offset for the scheduler.
474 * The sharing between multiple users of the same metric without multiplexing
475 * is not allowed, even though the hardware supports that in principle.
476 */
477
478 #define METRIC_EVENT_CONSTRAINT(c, n) \
479 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
480 INTEL_ARCH_EVENT_MASK)
481
482 /*
483 * Constraint on the Event code + UMask
484 */
485 #define INTEL_UEVENT_CONSTRAINT(c, n) \
486 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
487
488 /* Constraint on specific umask bit only + event */
489 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
490 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
491
492 /* Like UEVENT_CONSTRAINT, but match flags too */
493 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
494 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
495
496 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
497 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
498 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
499
500 #define INTEL_PLD_CONSTRAINT(c, n) \
501 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
502 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
503
504 #define INTEL_PSD_CONSTRAINT(c, n) \
505 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
506 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
507
508 #define INTEL_PST_CONSTRAINT(c, n) \
509 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
510 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
511
512 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \
513 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
514 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID)
515
516 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \
517 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
518 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW)
519
520 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \
521 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
522 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW)
523
524 /* Event constraint, but match on all event flags too. */
525 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
526 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
527
528 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
529 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
530
531 /* Check only flags, but allow all event/umask */
532 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
533 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
534
535 /* Check flags and event code, and set the HSW store flag */
536 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
537 __EVENT_CONSTRAINT(code, n, \
538 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
539 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
540
541 /* Check flags and event code, and set the HSW load flag */
542 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
543 __EVENT_CONSTRAINT(code, n, \
544 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
545 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
546
547 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
548 __EVENT_CONSTRAINT_RANGE(code, end, n, \
549 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
550 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
551
552 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
553 __EVENT_CONSTRAINT(code, n, \
554 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
555 HWEIGHT(n), 0, \
556 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
557
558 /* Check flags and event code/umask, and set the HSW store flag */
559 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
560 __EVENT_CONSTRAINT(code, n, \
561 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
562 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
563
564 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
565 __EVENT_CONSTRAINT(code, n, \
566 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
567 HWEIGHT(n), 0, \
568 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
569
570 /* Check flags and event code/umask, and set the HSW load flag */
571 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
572 __EVENT_CONSTRAINT(code, n, \
573 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
574 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
575
576 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
577 __EVENT_CONSTRAINT(code, n, \
578 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
579 HWEIGHT(n), 0, \
580 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
581
582 /* Check flags and event code/umask, and set the HSW N/A flag */
583 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
584 __EVENT_CONSTRAINT(code, n, \
585 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
586 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
587
588
589 /*
590 * We define the end marker as having a weight of -1
591 * to enable blacklisting of events using a counter bitmask
592 * of zero and thus a weight of zero.
593 * The end marker has a weight that cannot possibly be
594 * obtained from counting the bits in the bitmask.
595 */
596 #define EVENT_CONSTRAINT_END { .weight = -1 }
597
598 /*
599 * Check for end marker with weight == -1
600 */
601 #define for_each_event_constraint(e, c) \
602 for ((e) = (c); (e)->weight != -1; (e)++)
603
604 /*
605 * Extra registers for specific events.
606 *
607 * Some events need large masks and require external MSRs.
608 * Those extra MSRs end up being shared for all events on
609 * a PMU and sometimes between PMU of sibling HT threads.
610 * In either case, the kernel needs to handle conflicting
611 * accesses to those extra, shared, regs. The data structure
612 * to manage those registers is stored in cpu_hw_event.
613 */
614 struct extra_reg {
615 unsigned int event;
616 unsigned int msr;
617 u64 config_mask;
618 u64 valid_mask;
619 int idx; /* per_xxx->regs[] reg index */
620 bool extra_msr_access;
621 };
622
623 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
624 .event = (e), \
625 .msr = (ms), \
626 .config_mask = (m), \
627 .valid_mask = (vm), \
628 .idx = EXTRA_REG_##i, \
629 .extra_msr_access = true, \
630 }
631
632 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
633 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
634
635 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
636 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
637 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
638
639 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
640 INTEL_UEVENT_EXTRA_REG(c, \
641 MSR_PEBS_LD_LAT_THRESHOLD, \
642 0xffff, \
643 LDLAT)
644
645 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
646
647 union perf_capabilities {
648 struct {
649 u64 lbr_format:6;
650 u64 pebs_trap:1;
651 u64 pebs_arch_reg:1;
652 u64 pebs_format:4;
653 u64 smm_freeze:1;
654 /*
655 * PMU supports separate counter range for writing
656 * values > 32bit.
657 */
658 u64 full_width_write:1;
659 u64 pebs_baseline:1;
660 u64 perf_metrics:1;
661 u64 pebs_output_pt_available:1;
662 u64 pebs_timing_info:1;
663 u64 anythread_deprecated:1;
664 u64 rdpmc_metrics_clear:1;
665 };
666 u64 capabilities;
667 };
668
669 struct x86_pmu_quirk {
670 struct x86_pmu_quirk *next;
671 void (*func)(void);
672 };
673
674 union x86_pmu_config {
675 struct {
676 u64 event:8,
677 umask:8,
678 usr:1,
679 os:1,
680 edge:1,
681 pc:1,
682 interrupt:1,
683 __reserved1:1,
684 en:1,
685 inv:1,
686 cmask:8,
687 event2:4,
688 __reserved2:4,
689 go:1,
690 ho:1;
691 } bits;
692 u64 value;
693 };
694
695 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
696
697 enum {
698 x86_lbr_exclusive_lbr,
699 x86_lbr_exclusive_bts,
700 x86_lbr_exclusive_pt,
701 x86_lbr_exclusive_max,
702 };
703
704 #define PERF_PEBS_DATA_SOURCE_MAX 0x100
705 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1)
706 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10
707 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1)
708
709 #define X86_HYBRID_PMU_ATOM_IDX 0
710 #define X86_HYBRID_PMU_CORE_IDX 1
711 #define X86_HYBRID_PMU_TINY_IDX 2
712
713 enum hybrid_pmu_type {
714 not_hybrid,
715 hybrid_small = BIT(X86_HYBRID_PMU_ATOM_IDX),
716 hybrid_big = BIT(X86_HYBRID_PMU_CORE_IDX),
717 hybrid_tiny = BIT(X86_HYBRID_PMU_TINY_IDX),
718
719 /* The belows are only used for matching */
720 hybrid_big_small = hybrid_big | hybrid_small,
721 hybrid_small_tiny = hybrid_small | hybrid_tiny,
722 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny,
723 };
724
725 struct arch_pebs_cap {
726 u64 caps;
727 u64 counters;
728 u64 pdists;
729 };
730
731 struct x86_hybrid_pmu {
732 struct pmu pmu;
733 const char *name;
734 enum hybrid_pmu_type pmu_type;
735 cpumask_t supported_cpus;
736 union perf_capabilities intel_cap;
737 u64 intel_ctrl;
738 u64 pebs_events_mask;
739 u64 config_mask;
740 union {
741 u64 cntr_mask64;
742 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
743 };
744 union {
745 u64 fixed_cntr_mask64;
746 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
747 };
748
749 union {
750 u64 acr_cntr_mask64;
751 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
752 };
753 union {
754 u64 acr_cause_mask64;
755 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
756 };
757 struct event_constraint unconstrained;
758
759 u64 hw_cache_event_ids
760 [PERF_COUNT_HW_CACHE_MAX]
761 [PERF_COUNT_HW_CACHE_OP_MAX]
762 [PERF_COUNT_HW_CACHE_RESULT_MAX];
763 u64 hw_cache_extra_regs
764 [PERF_COUNT_HW_CACHE_MAX]
765 [PERF_COUNT_HW_CACHE_OP_MAX]
766 [PERF_COUNT_HW_CACHE_RESULT_MAX];
767 struct event_constraint *event_constraints;
768 struct event_constraint *pebs_constraints;
769 struct extra_reg *extra_regs;
770
771 unsigned int late_ack :1,
772 mid_ack :1,
773 enabled_ack :1;
774
775 struct arch_pebs_cap arch_pebs_cap;
776
777 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
778 };
779
hybrid_pmu(struct pmu * pmu)780 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
781 {
782 return container_of(pmu, struct x86_hybrid_pmu, pmu);
783 }
784
785 extern struct static_key_false perf_is_hybrid;
786 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
787
788 #define hybrid(_pmu, _field) \
789 (*({ \
790 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
791 \
792 if (is_hybrid() && (_pmu)) \
793 __Fp = &hybrid_pmu(_pmu)->_field; \
794 \
795 __Fp; \
796 }))
797
798 #define hybrid_var(_pmu, _var) \
799 (*({ \
800 typeof(&_var) __Fp = &_var; \
801 \
802 if (is_hybrid() && (_pmu)) \
803 __Fp = &hybrid_pmu(_pmu)->_var; \
804 \
805 __Fp; \
806 }))
807
808 #define hybrid_bit(_pmu, _field) \
809 ({ \
810 bool __Fp = x86_pmu._field; \
811 \
812 if (is_hybrid() && (_pmu)) \
813 __Fp = hybrid_pmu(_pmu)->_field; \
814 \
815 __Fp; \
816 })
817
818 /*
819 * struct x86_pmu - generic x86 pmu
820 */
821 struct x86_pmu {
822 /*
823 * Generic x86 PMC bits
824 */
825 const char *name;
826 int version;
827 int (*handle_irq)(struct pt_regs *);
828 void (*disable_all)(void);
829 void (*enable_all)(int added);
830 void (*enable)(struct perf_event *);
831 void (*disable)(struct perf_event *);
832 void (*assign)(struct perf_event *event, int idx);
833 void (*add)(struct perf_event *);
834 void (*del)(struct perf_event *);
835 void (*read)(struct perf_event *event);
836 int (*set_period)(struct perf_event *event);
837 u64 (*update)(struct perf_event *event);
838 int (*hw_config)(struct perf_event *event);
839 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
840 void (*late_setup)(void);
841 void (*pebs_enable)(struct perf_event *event);
842 void (*pebs_disable)(struct perf_event *event);
843 void (*pebs_enable_all)(void);
844 void (*pebs_disable_all)(void);
845 unsigned eventsel;
846 unsigned perfctr;
847 unsigned fixedctr;
848 int (*addr_offset)(int index, bool eventsel);
849 int (*rdpmc_index)(int index);
850 u64 (*event_map)(int);
851 int max_events;
852 u64 config_mask;
853 union {
854 u64 cntr_mask64;
855 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
856 };
857 union {
858 u64 fixed_cntr_mask64;
859 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
860 };
861 union {
862 u64 acr_cntr_mask64;
863 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
864 };
865 union {
866 u64 acr_cause_mask64;
867 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
868 };
869 int cntval_bits;
870 u64 cntval_mask;
871 union {
872 unsigned long events_maskl;
873 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
874 };
875 int events_mask_len;
876 int apic;
877 u64 max_period;
878 struct event_constraint *
879 (*get_event_constraints)(struct cpu_hw_events *cpuc,
880 int idx,
881 struct perf_event *event);
882
883 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
884 struct perf_event *event);
885
886 void (*start_scheduling)(struct cpu_hw_events *cpuc);
887
888 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
889
890 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
891
892 struct event_constraint *event_constraints;
893 struct x86_pmu_quirk *quirks;
894 void (*limit_period)(struct perf_event *event, s64 *l);
895
896 /* PMI handler bits */
897 unsigned int late_ack :1,
898 mid_ack :1,
899 enabled_ack :1;
900 /*
901 * sysfs attrs
902 */
903 int attr_rdpmc_broken;
904 int attr_rdpmc;
905 struct attribute **format_attrs;
906
907 ssize_t (*events_sysfs_show)(char *page, u64 config);
908 const struct attribute_group **attr_update;
909
910 unsigned long attr_freeze_on_smi;
911
912 /*
913 * CPU Hotplug hooks
914 */
915 int (*cpu_prepare)(int cpu);
916 void (*cpu_starting)(int cpu);
917 void (*cpu_dying)(int cpu);
918 void (*cpu_dead)(int cpu);
919
920 void (*check_microcode)(void);
921 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx,
922 struct task_struct *task, bool sched_in);
923
924 /*
925 * Intel Arch Perfmon v2+
926 */
927 u64 intel_ctrl;
928 union perf_capabilities intel_cap;
929
930 /*
931 * Intel DebugStore and PEBS bits
932 */
933 unsigned int bts :1,
934 bts_active :1,
935 ds_pebs :1,
936 pebs_active :1,
937 pebs_broken :1,
938 pebs_prec_dist :1,
939 pebs_no_tlb :1,
940 pebs_no_isolation :1,
941 pebs_block :1,
942 pebs_ept :1,
943 arch_pebs :1;
944 int pebs_record_size;
945 int pebs_buffer_size;
946 u64 pebs_events_mask;
947 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
948 struct event_constraint *pebs_constraints;
949 void (*pebs_aliases)(struct perf_event *event);
950 u64 (*pebs_latency_data)(struct perf_event *event, u64 status);
951 unsigned long large_pebs_flags;
952 u64 rtm_abort_event;
953 u64 pebs_capable;
954
955 /*
956 * Intel Architectural PEBS
957 */
958 struct arch_pebs_cap arch_pebs_cap;
959
960 /*
961 * Intel LBR
962 */
963 unsigned int lbr_tos, lbr_from, lbr_to,
964 lbr_info, lbr_nr; /* LBR base regs and size */
965 union {
966 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
967 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
968 };
969 union {
970 const int *lbr_sel_map; /* lbr_select mappings */
971 int *lbr_ctl_map; /* LBR_CTL mappings */
972 };
973 u64 lbr_callstack_users; /* lbr callstack system wide users */
974 bool lbr_double_abort; /* duplicated lbr aborts */
975 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
976
977 unsigned int lbr_has_info:1;
978 unsigned int lbr_has_tsx:1;
979 unsigned int lbr_from_flags:1;
980 unsigned int lbr_to_cycles:1;
981
982 /*
983 * Intel Architectural LBR CPUID Enumeration
984 */
985 unsigned int lbr_depth_mask:8;
986 unsigned int lbr_deep_c_reset:1;
987 unsigned int lbr_lip:1;
988 unsigned int lbr_cpl:1;
989 unsigned int lbr_filter:1;
990 unsigned int lbr_call_stack:1;
991 unsigned int lbr_mispred:1;
992 unsigned int lbr_timed_lbr:1;
993 unsigned int lbr_br_type:1;
994 unsigned int lbr_counters:4;
995
996 void (*lbr_reset)(void);
997 void (*lbr_read)(struct cpu_hw_events *cpuc);
998 void (*lbr_save)(void *ctx);
999 void (*lbr_restore)(void *ctx);
1000
1001 /*
1002 * Intel PT/LBR/BTS are exclusive
1003 */
1004 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
1005
1006 /*
1007 * Intel perf metrics
1008 */
1009 int num_topdown_events;
1010
1011 /*
1012 * AMD bits
1013 */
1014 unsigned int amd_nb_constraints : 1;
1015 u64 perf_ctr_pair_en;
1016
1017 /*
1018 * Extra registers for events
1019 */
1020 struct extra_reg *extra_regs;
1021 unsigned int flags;
1022
1023 /*
1024 * Intel host/guest support (KVM)
1025 */
1026 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data);
1027
1028 /*
1029 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
1030 */
1031 int (*check_period) (struct perf_event *event, u64 period);
1032
1033 int (*aux_output_match) (struct perf_event *event);
1034
1035 void (*filter)(struct pmu *pmu, int cpu, bool *ret);
1036 /*
1037 * Hybrid support
1038 *
1039 * Most PMU capabilities are the same among different hybrid PMUs.
1040 * The global x86_pmu saves the architecture capabilities, which
1041 * are available for all PMUs. The hybrid_pmu only includes the
1042 * unique capabilities.
1043 */
1044 int num_hybrid_pmus;
1045 struct x86_hybrid_pmu *hybrid_pmu;
1046 enum intel_cpu_type (*get_hybrid_cpu_type) (void);
1047 };
1048
1049 struct x86_perf_task_context_opt {
1050 int lbr_callstack_users;
1051 int lbr_stack_state;
1052 int log_id;
1053 };
1054
1055 struct x86_perf_task_context {
1056 u64 lbr_sel;
1057 int tos;
1058 int valid_lbrs;
1059 struct x86_perf_task_context_opt opt;
1060 struct lbr_entry lbr[MAX_LBR_ENTRIES];
1061 };
1062
1063 struct x86_perf_task_context_arch_lbr {
1064 struct x86_perf_task_context_opt opt;
1065 struct lbr_entry entries[];
1066 };
1067
1068 /*
1069 * Add padding to guarantee the 64-byte alignment of the state buffer.
1070 *
1071 * The structure is dynamically allocated. The size of the LBR state may vary
1072 * based on the number of LBR registers.
1073 *
1074 * Do not put anything after the LBR state.
1075 */
1076 struct x86_perf_task_context_arch_lbr_xsave {
1077 struct x86_perf_task_context_opt opt;
1078
1079 union {
1080 struct xregs_state xsave;
1081 struct {
1082 struct fxregs_state i387;
1083 struct xstate_header header;
1084 struct arch_lbr_state lbr;
1085 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
1086 };
1087 };
1088
1089 #define x86_add_quirk(func_) \
1090 do { \
1091 static struct x86_pmu_quirk __quirk __initdata = { \
1092 .func = func_, \
1093 }; \
1094 __quirk.next = x86_pmu.quirks; \
1095 x86_pmu.quirks = &__quirk; \
1096 } while (0)
1097
1098 /*
1099 * x86_pmu flags
1100 */
1101 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
1102 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
1103 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
1104 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
1105 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
1106 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
1107 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
1108 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
1109 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
1110 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */
1111 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */
1112 #define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */
1113 #define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */
1114
1115 #define EVENT_VAR(_id) event_attr_##_id
1116 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
1117
1118 #define EVENT_ATTR(_name, _id) \
1119 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
1120 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1121 .id = PERF_COUNT_HW_##_id, \
1122 .event_str = NULL, \
1123 };
1124
1125 #define EVENT_ATTR_STR(_name, v, str) \
1126 static struct perf_pmu_events_attr event_attr_##v = { \
1127 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1128 .id = 0, \
1129 .event_str = str, \
1130 };
1131
1132 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
1133 static struct perf_pmu_events_ht_attr event_attr_##v = { \
1134 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
1135 .id = 0, \
1136 .event_str_noht = noht, \
1137 .event_str_ht = ht, \
1138 }
1139
1140 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
1141 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
1142 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\
1143 .id = 0, \
1144 .event_str = str, \
1145 .pmu_type = _pmu, \
1146 }
1147
1148 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
1149
1150 #define FORMAT_ATTR_HYBRID(_name, _pmu) \
1151 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
1152 .attr = __ATTR_RO(_name), \
1153 .pmu_type = _pmu, \
1154 }
1155
1156 struct pmu *x86_get_pmu(unsigned int cpu);
1157 extern struct x86_pmu x86_pmu __read_mostly;
1158
1159 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
1160 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
1161 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
1162 DECLARE_STATIC_CALL(x86_pmu_late_setup, *x86_pmu.late_setup);
1163 DECLARE_STATIC_CALL(x86_pmu_pebs_enable, *x86_pmu.pebs_enable);
1164 DECLARE_STATIC_CALL(x86_pmu_pebs_disable, *x86_pmu.pebs_disable);
1165 DECLARE_STATIC_CALL(x86_pmu_pebs_enable_all, *x86_pmu.pebs_enable_all);
1166 DECLARE_STATIC_CALL(x86_pmu_pebs_disable_all, *x86_pmu.pebs_disable_all);
1167
task_context_opt(void * ctx)1168 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
1169 {
1170 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
1171 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
1172
1173 return &((struct x86_perf_task_context *)ctx)->opt;
1174 }
1175
x86_pmu_has_lbr_callstack(void)1176 static inline bool x86_pmu_has_lbr_callstack(void)
1177 {
1178 return x86_pmu.lbr_sel_map &&
1179 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
1180 }
1181
1182 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
1183 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1184
1185 int x86_perf_event_set_period(struct perf_event *event);
1186
1187 /*
1188 * Generalized hw caching related hw_event table, filled
1189 * in on a per model basis. A value of 0 means
1190 * 'not supported', -1 means 'hw_event makes no sense on
1191 * this CPU', any other value means the raw hw_event
1192 * ID.
1193 */
1194
1195 #define C(x) PERF_COUNT_HW_CACHE_##x
1196
1197 extern u64 __read_mostly hw_cache_event_ids
1198 [PERF_COUNT_HW_CACHE_MAX]
1199 [PERF_COUNT_HW_CACHE_OP_MAX]
1200 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1201 extern u64 __read_mostly hw_cache_extra_regs
1202 [PERF_COUNT_HW_CACHE_MAX]
1203 [PERF_COUNT_HW_CACHE_OP_MAX]
1204 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1205
1206 u64 x86_perf_event_update(struct perf_event *event);
1207
intel_pmu_topdown_event_update(struct perf_event * event,u64 * val)1208 static inline u64 intel_pmu_topdown_event_update(struct perf_event *event, u64 *val)
1209 {
1210 return x86_perf_event_update(event);
1211 }
1212 DECLARE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
1213
x86_pmu_config_addr(int index)1214 static inline unsigned int x86_pmu_config_addr(int index)
1215 {
1216 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
1217 x86_pmu.addr_offset(index, true) : index);
1218 }
1219
x86_pmu_event_addr(int index)1220 static inline unsigned int x86_pmu_event_addr(int index)
1221 {
1222 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
1223 x86_pmu.addr_offset(index, false) : index);
1224 }
1225
x86_pmu_fixed_ctr_addr(int index)1226 static inline unsigned int x86_pmu_fixed_ctr_addr(int index)
1227 {
1228 return x86_pmu.fixedctr + (x86_pmu.addr_offset ?
1229 x86_pmu.addr_offset(index, false) : index);
1230 }
1231
x86_pmu_rdpmc_index(int index)1232 static inline int x86_pmu_rdpmc_index(int index)
1233 {
1234 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
1235 }
1236
1237 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1238 unsigned long *fixed_cntr_mask);
1239
1240 int x86_add_exclusive(unsigned int what);
1241
1242 void x86_del_exclusive(unsigned int what);
1243
1244 int x86_reserve_hardware(void);
1245
1246 void x86_release_hardware(void);
1247
1248 int x86_pmu_max_precise(struct pmu *pmu);
1249
1250 void hw_perf_lbr_event_destroy(struct perf_event *event);
1251
1252 int x86_setup_perfctr(struct perf_event *event);
1253
1254 int x86_pmu_hw_config(struct perf_event *event);
1255
1256 void x86_pmu_disable_all(void);
1257
has_amd_brs(struct hw_perf_event * hwc)1258 static inline bool has_amd_brs(struct hw_perf_event *hwc)
1259 {
1260 return hwc->flags & PERF_X86_EVENT_AMD_BRS;
1261 }
1262
is_counter_pair(struct hw_perf_event * hwc)1263 static inline bool is_counter_pair(struct hw_perf_event *hwc)
1264 {
1265 return hwc->flags & PERF_X86_EVENT_PAIR;
1266 }
1267
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)1268 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
1269 u64 enable_mask)
1270 {
1271 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1272
1273 if (hwc->extra_reg.reg)
1274 wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config);
1275
1276 /*
1277 * Add enabled Merge event on next counter
1278 * if large increment event being enabled on this counter
1279 */
1280 if (is_counter_pair(hwc))
1281 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1282
1283 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1284 }
1285
1286 void x86_pmu_enable_all(int added);
1287
1288 int perf_assign_events(struct event_constraint **constraints, int n,
1289 int wmin, int wmax, int gpmax, int *assign);
1290 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1291
1292 void x86_pmu_stop(struct perf_event *event, int flags);
1293
x86_pmu_disable_event(struct perf_event * event)1294 static inline void x86_pmu_disable_event(struct perf_event *event)
1295 {
1296 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1297 struct hw_perf_event *hwc = &event->hw;
1298
1299 wrmsrq(hwc->config_base, hwc->config & ~disable_mask);
1300
1301 if (is_counter_pair(hwc))
1302 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0);
1303 }
1304
1305 void x86_pmu_enable_event(struct perf_event *event);
1306
1307 int x86_pmu_handle_irq(struct pt_regs *regs);
1308
1309 void x86_pmu_show_pmu_cap(struct pmu *pmu);
1310
x86_pmu_num_counters(struct pmu * pmu)1311 static inline int x86_pmu_num_counters(struct pmu *pmu)
1312 {
1313 return hweight64(hybrid(pmu, cntr_mask64));
1314 }
1315
x86_pmu_max_num_counters(struct pmu * pmu)1316 static inline int x86_pmu_max_num_counters(struct pmu *pmu)
1317 {
1318 return fls64(hybrid(pmu, cntr_mask64));
1319 }
1320
x86_pmu_num_counters_fixed(struct pmu * pmu)1321 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
1322 {
1323 return hweight64(hybrid(pmu, fixed_cntr_mask64));
1324 }
1325
x86_pmu_max_num_counters_fixed(struct pmu * pmu)1326 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu)
1327 {
1328 return fls64(hybrid(pmu, fixed_cntr_mask64));
1329 }
1330
x86_pmu_get_event_config(struct perf_event * event)1331 static inline u64 x86_pmu_get_event_config(struct perf_event *event)
1332 {
1333 return event->attr.config & hybrid(event->pmu, config_mask);
1334 }
1335
x86_pmu_has_rdpmc_user_disable(struct pmu * pmu)1336 static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu)
1337 {
1338 return !!(hybrid(pmu, config_mask) &
1339 ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE);
1340 }
1341
1342 extern struct event_constraint emptyconstraint;
1343
1344 extern struct event_constraint unconstrained;
1345
kernel_ip(unsigned long ip)1346 static inline bool kernel_ip(unsigned long ip)
1347 {
1348 #ifdef CONFIG_X86_32
1349 return ip > PAGE_OFFSET;
1350 #else
1351 return (long)ip < 0;
1352 #endif
1353 }
1354
1355 /*
1356 * Not all PMUs provide the right context information to place the reported IP
1357 * into full context. Specifically segment registers are typically not
1358 * supplied.
1359 *
1360 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1361 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1362 * to reflect this.
1363 *
1364 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1365 * much we can do about that but pray and treat it like a linear address.
1366 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)1367 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1368 {
1369 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1370 if (regs->flags & X86_VM_MASK)
1371 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1372 regs->ip = ip;
1373 }
1374
1375 /*
1376 * x86control flow change classification
1377 * x86control flow changes include branches, interrupts, traps, faults
1378 */
1379 enum {
1380 X86_BR_NONE = 0, /* unknown */
1381
1382 X86_BR_USER = 1 << 0, /* branch target is user */
1383 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
1384
1385 X86_BR_CALL = 1 << 2, /* call */
1386 X86_BR_RET = 1 << 3, /* return */
1387 X86_BR_SYSCALL = 1 << 4, /* syscall */
1388 X86_BR_SYSRET = 1 << 5, /* syscall return */
1389 X86_BR_INT = 1 << 6, /* sw interrupt */
1390 X86_BR_IRET = 1 << 7, /* return from interrupt */
1391 X86_BR_JCC = 1 << 8, /* conditional */
1392 X86_BR_JMP = 1 << 9, /* jump */
1393 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
1394 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
1395 X86_BR_ABORT = 1 << 12,/* transaction abort */
1396 X86_BR_IN_TX = 1 << 13,/* in transaction */
1397 X86_BR_NO_TX = 1 << 14,/* not in transaction */
1398 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
1399 X86_BR_CALL_STACK = 1 << 16,/* call stack */
1400 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
1401
1402 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
1403
1404 };
1405
1406 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
1407 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
1408
1409 #define X86_BR_ANY \
1410 (X86_BR_CALL |\
1411 X86_BR_RET |\
1412 X86_BR_SYSCALL |\
1413 X86_BR_SYSRET |\
1414 X86_BR_INT |\
1415 X86_BR_IRET |\
1416 X86_BR_JCC |\
1417 X86_BR_JMP |\
1418 X86_BR_IRQ |\
1419 X86_BR_ABORT |\
1420 X86_BR_IND_CALL |\
1421 X86_BR_IND_JMP |\
1422 X86_BR_ZERO_CALL)
1423
1424 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
1425
1426 #define X86_BR_ANY_CALL \
1427 (X86_BR_CALL |\
1428 X86_BR_IND_CALL |\
1429 X86_BR_ZERO_CALL |\
1430 X86_BR_SYSCALL |\
1431 X86_BR_IRQ |\
1432 X86_BR_INT)
1433
1434 int common_branch_type(int type);
1435 int branch_type(unsigned long from, unsigned long to, int abort);
1436 int branch_type_fused(unsigned long from, unsigned long to, int abort,
1437 int *offset);
1438
1439 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1440 ssize_t intel_event_sysfs_show(char *page, u64 config);
1441
1442 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1443 char *page);
1444 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1445 char *page);
1446 ssize_t events_hybrid_sysfs_show(struct device *dev,
1447 struct device_attribute *attr,
1448 char *page);
1449
fixed_counter_disabled(int i,struct pmu * pmu)1450 static inline bool fixed_counter_disabled(int i, struct pmu *pmu)
1451 {
1452 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
1453
1454 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1455 }
1456
1457 #ifdef CONFIG_CPU_SUP_AMD
1458
1459 int amd_pmu_init(void);
1460
1461 int amd_pmu_lbr_init(void);
1462 void amd_pmu_lbr_reset(void);
1463 void amd_pmu_lbr_read(void);
1464 void amd_pmu_lbr_add(struct perf_event *event);
1465 void amd_pmu_lbr_del(struct perf_event *event);
1466 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
1467 struct task_struct *task, bool sched_in);
1468 void amd_pmu_lbr_enable_all(void);
1469 void amd_pmu_lbr_disable_all(void);
1470 int amd_pmu_lbr_hw_config(struct perf_event *event);
1471
__amd_pmu_lbr_disable(void)1472 static __always_inline void __amd_pmu_lbr_disable(void)
1473 {
1474 u64 dbg_ctl, dbg_extn_cfg;
1475
1476 rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
1477 wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
1478
1479 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
1480 rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
1481 wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1482 }
1483 }
1484
1485 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1486
1487 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */
1488
1489 int amd_brs_init(void);
1490 void amd_brs_disable(void);
1491 void amd_brs_enable(void);
1492 void amd_brs_enable_all(void);
1493 void amd_brs_disable_all(void);
1494 void amd_brs_drain(void);
1495 void amd_brs_lopwr_init(void);
1496 int amd_brs_hw_config(struct perf_event *event);
1497 void amd_brs_reset(void);
1498
amd_pmu_brs_add(struct perf_event * event)1499 static inline void amd_pmu_brs_add(struct perf_event *event)
1500 {
1501 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1502
1503 perf_sched_cb_inc(event->pmu);
1504 cpuc->lbr_users++;
1505 /*
1506 * No need to reset BRS because it is reset
1507 * on brs_enable() and it is saturating
1508 */
1509 }
1510
amd_pmu_brs_del(struct perf_event * event)1511 static inline void amd_pmu_brs_del(struct perf_event *event)
1512 {
1513 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1514
1515 cpuc->lbr_users--;
1516 WARN_ON_ONCE(cpuc->lbr_users < 0);
1517
1518 perf_sched_cb_dec(event->pmu);
1519 }
1520
1521 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx,
1522 struct task_struct *task, bool sched_in);
1523 #else
amd_brs_init(void)1524 static inline int amd_brs_init(void)
1525 {
1526 return 0;
1527 }
amd_brs_disable(void)1528 static inline void amd_brs_disable(void) {}
amd_brs_enable(void)1529 static inline void amd_brs_enable(void) {}
amd_brs_drain(void)1530 static inline void amd_brs_drain(void) {}
amd_brs_lopwr_init(void)1531 static inline void amd_brs_lopwr_init(void) {}
amd_brs_disable_all(void)1532 static inline void amd_brs_disable_all(void) {}
amd_brs_hw_config(struct perf_event * event)1533 static inline int amd_brs_hw_config(struct perf_event *event)
1534 {
1535 return 0;
1536 }
amd_brs_reset(void)1537 static inline void amd_brs_reset(void) {}
1538
amd_pmu_brs_add(struct perf_event * event)1539 static inline void amd_pmu_brs_add(struct perf_event *event)
1540 {
1541 }
1542
amd_pmu_brs_del(struct perf_event * event)1543 static inline void amd_pmu_brs_del(struct perf_event *event)
1544 {
1545 }
1546
amd_pmu_brs_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)1547 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx,
1548 struct task_struct *task, bool sched_in)
1549 {
1550 }
1551
amd_brs_enable_all(void)1552 static inline void amd_brs_enable_all(void)
1553 {
1554 }
1555
1556 #endif
1557
1558 #else /* CONFIG_CPU_SUP_AMD */
1559
amd_pmu_init(void)1560 static inline int amd_pmu_init(void)
1561 {
1562 return 0;
1563 }
1564
amd_brs_init(void)1565 static inline int amd_brs_init(void)
1566 {
1567 return -EOPNOTSUPP;
1568 }
1569
amd_brs_drain(void)1570 static inline void amd_brs_drain(void)
1571 {
1572 }
1573
amd_brs_enable_all(void)1574 static inline void amd_brs_enable_all(void)
1575 {
1576 }
1577
amd_brs_disable_all(void)1578 static inline void amd_brs_disable_all(void)
1579 {
1580 }
1581 #endif /* CONFIG_CPU_SUP_AMD */
1582
is_pebs_pt(struct perf_event * event)1583 static inline int is_pebs_pt(struct perf_event *event)
1584 {
1585 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1586 }
1587
1588 #ifdef CONFIG_CPU_SUP_INTEL
1589
intel_pmu_has_bts_period(struct perf_event * event,u64 period)1590 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1591 {
1592 struct hw_perf_event *hwc = &event->hw;
1593 unsigned int hw_event, bts_event;
1594
1595 /*
1596 * Only use BTS for fixed rate period==1 events.
1597 */
1598 if (event->attr.freq || period != 1)
1599 return false;
1600
1601 /*
1602 * BTS doesn't virtualize.
1603 */
1604 if (event->attr.exclude_host)
1605 return false;
1606
1607 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1608 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1609
1610 return hw_event == bts_event;
1611 }
1612
intel_pmu_has_bts(struct perf_event * event)1613 static inline bool intel_pmu_has_bts(struct perf_event *event)
1614 {
1615 struct hw_perf_event *hwc = &event->hw;
1616
1617 return intel_pmu_has_bts_period(event, hwc->sample_period);
1618 }
1619
__intel_pmu_pebs_disable_all(void)1620 static __always_inline void __intel_pmu_pebs_disable_all(void)
1621 {
1622 wrmsrq(MSR_IA32_PEBS_ENABLE, 0);
1623 }
1624
__intel_pmu_arch_lbr_disable(void)1625 static __always_inline void __intel_pmu_arch_lbr_disable(void)
1626 {
1627 wrmsrq(MSR_ARCH_LBR_CTL, 0);
1628 }
1629
__intel_pmu_lbr_disable(void)1630 static __always_inline void __intel_pmu_lbr_disable(void)
1631 {
1632 u64 debugctl;
1633
1634 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
1635 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1636 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
1637 }
1638
1639 int intel_pmu_save_and_restart(struct perf_event *event);
1640
1641 struct event_constraint *
1642 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1643 struct perf_event *event);
1644
1645 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1646 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1647
1648 int intel_pmu_init(void);
1649
1650 int alloc_arch_pebs_buf_on_cpu(int cpu);
1651
1652 void release_arch_pebs_buf_on_cpu(int cpu);
1653
1654 void init_arch_pebs_on_cpu(int cpu);
1655
1656 void fini_arch_pebs_on_cpu(int cpu);
1657
1658 void init_debug_store_on_cpu(int cpu);
1659
1660 void fini_debug_store_on_cpu(int cpu);
1661
1662 void release_ds_buffers(void);
1663
1664 void reserve_ds_buffers(void);
1665
1666 void release_lbr_buffers(void);
1667
1668 void reserve_lbr_buffers(void);
1669
1670 extern struct event_constraint bts_constraint;
1671 extern struct event_constraint vlbr_constraint;
1672
1673 void intel_pmu_enable_bts(u64 config);
1674
1675 void intel_pmu_disable_bts(void);
1676
1677 int intel_pmu_drain_bts_buffer(void);
1678
1679 void intel_pmu_late_setup(void);
1680
1681 u64 grt_latency_data(struct perf_event *event, u64 status);
1682
1683 u64 cmt_latency_data(struct perf_event *event, u64 status);
1684
1685 u64 lnl_latency_data(struct perf_event *event, u64 status);
1686
1687 u64 arl_h_latency_data(struct perf_event *event, u64 status);
1688
1689 u64 pnc_latency_data(struct perf_event *event, u64 status);
1690
1691 u64 nvl_latency_data(struct perf_event *event, u64 status);
1692
1693 extern struct event_constraint intel_core2_pebs_event_constraints[];
1694
1695 extern struct event_constraint intel_atom_pebs_event_constraints[];
1696
1697 extern struct event_constraint intel_slm_pebs_event_constraints[];
1698
1699 extern struct event_constraint intel_glm_pebs_event_constraints[];
1700
1701 extern struct event_constraint intel_glp_pebs_event_constraints[];
1702
1703 extern struct event_constraint intel_grt_pebs_event_constraints[];
1704
1705 extern struct event_constraint intel_arw_pebs_event_constraints[];
1706
1707 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1708
1709 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1710
1711 extern struct event_constraint intel_snb_pebs_event_constraints[];
1712
1713 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1714
1715 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1716
1717 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1718
1719 extern struct event_constraint intel_skl_pebs_event_constraints[];
1720
1721 extern struct event_constraint intel_icl_pebs_event_constraints[];
1722
1723 extern struct event_constraint intel_glc_pebs_event_constraints[];
1724
1725 extern struct event_constraint intel_lnc_pebs_event_constraints[];
1726
1727 extern struct event_constraint intel_pnc_pebs_event_constraints[];
1728
1729 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1730
1731 void intel_pmu_pebs_add(struct perf_event *event);
1732
1733 void intel_pmu_pebs_del(struct perf_event *event);
1734
1735 void intel_pmu_pebs_enable(struct perf_event *event);
1736
1737 void intel_pmu_pebs_disable(struct perf_event *event);
1738
1739 void intel_pmu_pebs_enable_all(void);
1740
1741 void intel_pmu_pebs_disable_all(void);
1742
1743 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1744
1745 void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc);
1746
1747 void intel_pmu_drain_pebs_buffer(void);
1748
1749 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1750
1751 void intel_pebs_init(void);
1752
1753 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data,
1754 struct cpu_hw_events *cpuc,
1755 struct perf_event *event);
1756
1757 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
1758 struct task_struct *task, bool sched_in);
1759
1760 u64 lbr_from_signext_quirk_wr(u64 val);
1761
1762 void intel_pmu_lbr_reset(void);
1763
1764 void intel_pmu_lbr_reset_32(void);
1765
1766 void intel_pmu_lbr_reset_64(void);
1767
1768 void intel_pmu_lbr_add(struct perf_event *event);
1769
1770 void intel_pmu_lbr_del(struct perf_event *event);
1771
1772 void intel_pmu_lbr_enable_all(bool pmi);
1773
1774 void intel_pmu_lbr_disable_all(void);
1775
1776 void intel_pmu_lbr_read(void);
1777
1778 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1779
1780 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1781
1782 void intel_pmu_lbr_save(void *ctx);
1783
1784 void intel_pmu_lbr_restore(void *ctx);
1785
1786 void intel_pmu_lbr_init_core(void);
1787
1788 void intel_pmu_lbr_init_nhm(void);
1789
1790 void intel_pmu_lbr_init_atom(void);
1791
1792 void intel_pmu_lbr_init_slm(void);
1793
1794 void intel_pmu_lbr_init_snb(void);
1795
1796 void intel_pmu_lbr_init_hsw(void);
1797
1798 void intel_pmu_lbr_init_skl(void);
1799
1800 void intel_pmu_lbr_init_knl(void);
1801
1802 void intel_pmu_lbr_init(void);
1803
1804 void intel_pmu_arch_lbr_init(void);
1805
1806 void intel_pmu_pebs_data_source_nhm(void);
1807
1808 void intel_pmu_pebs_data_source_skl(bool pmem);
1809
1810 void intel_pmu_pebs_data_source_adl(void);
1811
1812 void intel_pmu_pebs_data_source_grt(void);
1813
1814 void intel_pmu_pebs_data_source_mtl(void);
1815
1816 void intel_pmu_pebs_data_source_arl_h(void);
1817
1818 void intel_pmu_pebs_data_source_cmt(void);
1819
1820 void intel_pmu_pebs_data_source_lnl(void);
1821
1822 u64 intel_get_arch_pebs_data_config(struct perf_event *event);
1823
1824 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1825
1826 void intel_pt_interrupt(void);
1827
1828 int intel_bts_interrupt(void);
1829
1830 void intel_bts_enable_local(void);
1831
1832 void intel_bts_disable_local(void);
1833
1834 int p4_pmu_init(void);
1835
1836 int p6_pmu_init(void);
1837
1838 int knc_pmu_init(void);
1839
is_ht_workaround_enabled(void)1840 static inline int is_ht_workaround_enabled(void)
1841 {
1842 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1843 }
1844
intel_pmu_pebs_mask(u64 cntr_mask)1845 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask)
1846 {
1847 return MAX_PEBS_EVENTS_MASK & cntr_mask;
1848 }
1849
intel_pmu_max_num_pebs(struct pmu * pmu)1850 static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
1851 {
1852 static_assert(MAX_PEBS_EVENTS == 32);
1853 return fls((u32)hybrid(pmu, pebs_events_mask));
1854 }
1855
intel_pmu_has_pebs(void)1856 static inline bool intel_pmu_has_pebs(void)
1857 {
1858 return x86_pmu.ds_pebs || x86_pmu.arch_pebs;
1859 }
1860
1861 #else /* CONFIG_CPU_SUP_INTEL */
1862
reserve_ds_buffers(void)1863 static inline void reserve_ds_buffers(void)
1864 {
1865 }
1866
release_ds_buffers(void)1867 static inline void release_ds_buffers(void)
1868 {
1869 }
1870
release_lbr_buffers(void)1871 static inline void release_lbr_buffers(void)
1872 {
1873 }
1874
reserve_lbr_buffers(void)1875 static inline void reserve_lbr_buffers(void)
1876 {
1877 }
1878
intel_pmu_init(void)1879 static inline int intel_pmu_init(void)
1880 {
1881 return 0;
1882 }
1883
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1884 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1885 {
1886 return 0;
1887 }
1888
intel_cpuc_finish(struct cpu_hw_events * cpuc)1889 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1890 {
1891 }
1892
is_ht_workaround_enabled(void)1893 static inline int is_ht_workaround_enabled(void)
1894 {
1895 return 0;
1896 }
1897 #endif /* CONFIG_CPU_SUP_INTEL */
1898
1899 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1900 int zhaoxin_pmu_init(void);
1901 #else
zhaoxin_pmu_init(void)1902 static inline int zhaoxin_pmu_init(void)
1903 {
1904 return 0;
1905 }
1906 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/
1907