1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
83
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
86
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
89
90 struct tod_reg {
91 u32 ctrl;
92 u32 status;
93 u32 uart_polarity;
94 u32 version;
95 u32 adj_sec;
96 u32 __pad0[3];
97 u32 uart_baud;
98 u32 __pad1[3];
99 u32 utc_status;
100 u32 leap;
101 };
102
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
109
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
114
115 struct ts_reg {
116 u32 enable;
117 u32 error;
118 u32 polarity;
119 u32 version;
120 u32 __pad0[4];
121 u32 cable_delay;
122 u32 __pad1[3];
123 u32 intr;
124 u32 intr_mask;
125 u32 event_count;
126 u32 __pad2[1];
127 u32 ts_count;
128 u32 time_ns;
129 u32 time_sec;
130 u32 data_width;
131 u32 data;
132 };
133
134 struct pps_reg {
135 u32 ctrl;
136 u32 status;
137 u32 __pad0[6];
138 u32 cable_delay;
139 };
140
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
143
144 struct img_reg {
145 u32 version;
146 };
147
148 struct gpio_reg {
149 u32 gpio1;
150 u32 __pad0;
151 u32 gpio2;
152 u32 __pad1;
153 };
154
155 struct irig_master_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_M_CTRL_ENABLE BIT(0)
165
166 struct irig_slave_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 u32 mode_ctrl;
173 };
174
175 #define IRIG_S_CTRL_ENABLE BIT(0)
176
177 struct dcf_master_reg {
178 u32 ctrl;
179 u32 status;
180 u32 __pad0;
181 u32 version;
182 u32 adj_sec;
183 };
184
185 #define DCF_M_CTRL_ENABLE BIT(0)
186
187 struct dcf_slave_reg {
188 u32 ctrl;
189 u32 status;
190 u32 __pad0;
191 u32 version;
192 u32 adj_sec;
193 };
194
195 #define DCF_S_CTRL_ENABLE BIT(0)
196
197 struct signal_reg {
198 u32 enable;
199 u32 status;
200 u32 polarity;
201 u32 version;
202 u32 __pad0[4];
203 u32 cable_delay;
204 u32 __pad1[3];
205 u32 intr;
206 u32 intr_mask;
207 u32 __pad2[2];
208 u32 start_ns;
209 u32 start_sec;
210 u32 pulse_ns;
211 u32 pulse_sec;
212 u32 period_ns;
213 u32 period_sec;
214 u32 repeat_count;
215 };
216
217 struct frequency_reg {
218 u32 ctrl;
219 u32 status;
220 };
221
222 struct board_config_reg {
223 u32 mro50_serial_activate;
224 };
225
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
230
231 struct ptp_ocp_flash_info {
232 const char *name;
233 int pci_offset;
234 int data_size;
235 void *data;
236 };
237
238 struct ptp_ocp_firmware_header {
239 char magic[4];
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
242 __be32 image_size;
243 __be16 hw_revision;
244 __be16 crc;
245 };
246
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
248
249 struct ptp_ocp_i2c_info {
250 const char *name;
251 unsigned long fixed_rate;
252 size_t data_size;
253 void *data;
254 };
255
256 struct ptp_ocp_ext_info {
257 int index;
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
260 };
261
262 struct ptp_ocp_ext_src {
263 void __iomem *mem;
264 struct ptp_ocp *bp;
265 struct ptp_ocp_ext_info *info;
266 int irq_vec;
267 };
268
269 enum ptp_ocp_sma_mode {
270 SMA_MODE_IN,
271 SMA_MODE_OUT,
272 };
273
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
279 };
280
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
283 bool fixed_fcn;
284 bool fixed_dir;
285 bool disabled;
286 u8 default_fcn;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318 #define OCP_SIGNAL_NUM 4
319 #define OCP_FREQ_NUM 4
320
321 enum {
322 PORT_GNSS,
323 PORT_GNSS2,
324 PORT_MAC, /* miniature atomic clock */
325 PORT_NMEA,
326
327 __PORT_COUNT,
328 };
329
330 struct ptp_ocp {
331 struct pci_dev *pdev;
332 struct device dev;
333 spinlock_t lock;
334 struct ocp_reg __iomem *reg;
335 struct tod_reg __iomem *tod;
336 struct pps_reg __iomem *pps_to_ext;
337 struct pps_reg __iomem *pps_to_clk;
338 struct board_config_reg __iomem *board_config;
339 struct gpio_reg __iomem *pps_select;
340 struct gpio_reg __iomem *sma_map1;
341 struct gpio_reg __iomem *sma_map2;
342 struct irig_master_reg __iomem *irig_out;
343 struct irig_slave_reg __iomem *irig_in;
344 struct dcf_master_reg __iomem *dcf_out;
345 struct dcf_slave_reg __iomem *dcf_in;
346 struct tod_reg __iomem *nmea_out;
347 struct frequency_reg __iomem *freq_in[OCP_FREQ_NUM];
348 struct ptp_ocp_ext_src *signal_out[OCP_SIGNAL_NUM];
349 struct ptp_ocp_ext_src *pps;
350 struct ptp_ocp_ext_src *ts0;
351 struct ptp_ocp_ext_src *ts1;
352 struct ptp_ocp_ext_src *ts2;
353 struct ptp_ocp_ext_src *ts3;
354 struct ptp_ocp_ext_src *ts4;
355 struct ocp_art_gpio_reg __iomem *art_sma;
356 struct img_reg __iomem *image;
357 struct ptp_clock *ptp;
358 struct ptp_clock_info ptp_info;
359 struct platform_device *i2c_ctrl;
360 struct platform_device *spi_flash;
361 struct clk_hw *i2c_clk;
362 struct timer_list watchdog;
363 const struct attribute_group **attr_group;
364 const struct ptp_ocp_eeprom_map *eeprom_map;
365 struct dentry *debug_root;
366 bool sync;
367 time64_t gnss_lost;
368 struct delayed_work sync_work;
369 int id;
370 int n_irqs;
371 struct ptp_ocp_serial_port port[__PORT_COUNT];
372 bool fw_loader;
373 u8 fw_tag;
374 u16 fw_version;
375 u8 board_id[OCP_BOARD_ID_LEN];
376 u8 serial[OCP_SERIAL_LEN];
377 bool has_eeprom_data;
378 u32 pps_req_map;
379 int flash_start;
380 u32 utc_tai_offset;
381 u32 ts_window_adjust;
382 u64 fw_cap;
383 struct ptp_ocp_signal signal[OCP_SIGNAL_NUM];
384 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
385 const struct ocp_sma_op *sma_op;
386 struct dpll_device *dpll;
387 int signals_nr;
388 int freq_in_nr;
389 };
390
391 #define OCP_REQ_TIMESTAMP BIT(0)
392 #define OCP_REQ_PPS BIT(1)
393
394 struct ocp_resource {
395 unsigned long offset;
396 int size;
397 int irq_vec;
398 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
399 void *extra;
400 unsigned long bp_offset;
401 const char * const name;
402 };
403
404 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
405 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
406 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
407 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
408 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
409 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
410 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
411 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
412 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
413 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
414 struct ptp_perout_request *req);
415 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
416 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
417
418 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
419
420 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
421
422 static const struct ocp_attr_group fb_timecard_groups[];
423
424 static const struct ocp_attr_group art_timecard_groups[];
425
426 static const struct ocp_attr_group adva_timecard_groups[];
427
428 struct ptp_ocp_eeprom_map {
429 u16 off;
430 u16 len;
431 u32 bp_offset;
432 const void * const tag;
433 };
434
435 #define EEPROM_ENTRY(addr, member) \
436 .off = addr, \
437 .len = sizeof_field(struct ptp_ocp, member), \
438 .bp_offset = offsetof(struct ptp_ocp, member)
439
440 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
441 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
442 })
443
444 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
445 { EEPROM_ENTRY(0x43, board_id) },
446 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
447 { }
448 };
449
450 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
451 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
452 { EEPROM_ENTRY(0x200 + 0x63, serial) },
453 { }
454 };
455
456 #define bp_assign_entry(bp, res, val) ({ \
457 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
458 *(typeof(val) *)addr = val; \
459 })
460
461 #define OCP_RES_LOCATION(member) \
462 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
463
464 #define OCP_MEM_RESOURCE(member) \
465 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
466
467 #define OCP_SERIAL_RESOURCE(member) \
468 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
469
470 #define OCP_I2C_RESOURCE(member) \
471 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
472
473 #define OCP_SPI_RESOURCE(member) \
474 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
475
476 #define OCP_EXT_RESOURCE(member) \
477 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
478
479 /* This is the MSI vector mapping used.
480 * 0: PPS (TS5)
481 * 1: TS0
482 * 2: TS1
483 * 3: GNSS1
484 * 4: GNSS2
485 * 5: MAC
486 * 6: TS2
487 * 7: I2C controller
488 * 8: HWICAP (notused)
489 * 9: SPI Flash
490 * 10: NMEA
491 * 11: Signal Generator 1
492 * 12: Signal Generator 2
493 * 13: Signal Generator 3
494 * 14: Signal Generator 4
495 * 15: TS3
496 * 16: TS4
497 --
498 * 8: Orolia TS1
499 * 10: Orolia TS2
500 * 11: Orolia TS0 (GNSS)
501 * 12: Orolia PPS
502 * 14: Orolia TS3
503 * 15: Orolia TS4
504 */
505
506 static struct ocp_resource ocp_fb_resource[] = {
507 {
508 OCP_MEM_RESOURCE(reg),
509 .offset = 0x01000000, .size = 0x10000,
510 },
511 {
512 OCP_EXT_RESOURCE(ts0),
513 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
514 .extra = &(struct ptp_ocp_ext_info) {
515 .index = 0,
516 .irq_fcn = ptp_ocp_ts_irq,
517 .enable = ptp_ocp_ts_enable,
518 },
519 },
520 {
521 OCP_EXT_RESOURCE(ts1),
522 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
523 .extra = &(struct ptp_ocp_ext_info) {
524 .index = 1,
525 .irq_fcn = ptp_ocp_ts_irq,
526 .enable = ptp_ocp_ts_enable,
527 },
528 },
529 {
530 OCP_EXT_RESOURCE(ts2),
531 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
532 .extra = &(struct ptp_ocp_ext_info) {
533 .index = 2,
534 .irq_fcn = ptp_ocp_ts_irq,
535 .enable = ptp_ocp_ts_enable,
536 },
537 },
538 {
539 OCP_EXT_RESOURCE(ts3),
540 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
541 .extra = &(struct ptp_ocp_ext_info) {
542 .index = 3,
543 .irq_fcn = ptp_ocp_ts_irq,
544 .enable = ptp_ocp_ts_enable,
545 },
546 },
547 {
548 OCP_EXT_RESOURCE(ts4),
549 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
550 .extra = &(struct ptp_ocp_ext_info) {
551 .index = 4,
552 .irq_fcn = ptp_ocp_ts_irq,
553 .enable = ptp_ocp_ts_enable,
554 },
555 },
556 /* Timestamp for PHC and/or PPS generator */
557 {
558 OCP_EXT_RESOURCE(pps),
559 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
560 .extra = &(struct ptp_ocp_ext_info) {
561 .index = 5,
562 .irq_fcn = ptp_ocp_ts_irq,
563 .enable = ptp_ocp_ts_enable,
564 },
565 },
566 {
567 OCP_EXT_RESOURCE(signal_out[0]),
568 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
569 .extra = &(struct ptp_ocp_ext_info) {
570 .index = 1,
571 .irq_fcn = ptp_ocp_signal_irq,
572 .enable = ptp_ocp_signal_enable,
573 },
574 },
575 {
576 OCP_EXT_RESOURCE(signal_out[1]),
577 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
578 .extra = &(struct ptp_ocp_ext_info) {
579 .index = 2,
580 .irq_fcn = ptp_ocp_signal_irq,
581 .enable = ptp_ocp_signal_enable,
582 },
583 },
584 {
585 OCP_EXT_RESOURCE(signal_out[2]),
586 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
587 .extra = &(struct ptp_ocp_ext_info) {
588 .index = 3,
589 .irq_fcn = ptp_ocp_signal_irq,
590 .enable = ptp_ocp_signal_enable,
591 },
592 },
593 {
594 OCP_EXT_RESOURCE(signal_out[3]),
595 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
596 .extra = &(struct ptp_ocp_ext_info) {
597 .index = 4,
598 .irq_fcn = ptp_ocp_signal_irq,
599 .enable = ptp_ocp_signal_enable,
600 },
601 },
602 {
603 OCP_MEM_RESOURCE(pps_to_ext),
604 .offset = 0x01030000, .size = 0x10000,
605 },
606 {
607 OCP_MEM_RESOURCE(pps_to_clk),
608 .offset = 0x01040000, .size = 0x10000,
609 },
610 {
611 OCP_MEM_RESOURCE(tod),
612 .offset = 0x01050000, .size = 0x10000,
613 },
614 {
615 OCP_MEM_RESOURCE(irig_in),
616 .offset = 0x01070000, .size = 0x10000,
617 },
618 {
619 OCP_MEM_RESOURCE(irig_out),
620 .offset = 0x01080000, .size = 0x10000,
621 },
622 {
623 OCP_MEM_RESOURCE(dcf_in),
624 .offset = 0x01090000, .size = 0x10000,
625 },
626 {
627 OCP_MEM_RESOURCE(dcf_out),
628 .offset = 0x010A0000, .size = 0x10000,
629 },
630 {
631 OCP_MEM_RESOURCE(nmea_out),
632 .offset = 0x010B0000, .size = 0x10000,
633 },
634 {
635 OCP_MEM_RESOURCE(image),
636 .offset = 0x00020000, .size = 0x1000,
637 },
638 {
639 OCP_MEM_RESOURCE(pps_select),
640 .offset = 0x00130000, .size = 0x1000,
641 },
642 {
643 OCP_MEM_RESOURCE(sma_map1),
644 .offset = 0x00140000, .size = 0x1000,
645 },
646 {
647 OCP_MEM_RESOURCE(sma_map2),
648 .offset = 0x00220000, .size = 0x1000,
649 },
650 {
651 OCP_I2C_RESOURCE(i2c_ctrl),
652 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
653 .extra = &(struct ptp_ocp_i2c_info) {
654 .name = "xiic-i2c",
655 .fixed_rate = 50000000,
656 .data_size = sizeof(struct xiic_i2c_platform_data),
657 .data = &(struct xiic_i2c_platform_data) {
658 .num_devices = 2,
659 .devices = (struct i2c_board_info[]) {
660 { I2C_BOARD_INFO("24c02", 0x50) },
661 { I2C_BOARD_INFO("24mac402", 0x58),
662 .platform_data = "mac" },
663 },
664 },
665 },
666 },
667 {
668 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
669 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
670 .extra = &(struct ptp_ocp_serial_port) {
671 .baud = 115200,
672 },
673 },
674 {
675 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
676 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
677 .extra = &(struct ptp_ocp_serial_port) {
678 .baud = 115200,
679 },
680 },
681 {
682 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
683 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
684 .extra = &(struct ptp_ocp_serial_port) {
685 .baud = 57600,
686 },
687 },
688 {
689 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
690 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
691 },
692 {
693 OCP_SPI_RESOURCE(spi_flash),
694 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
695 .extra = &(struct ptp_ocp_flash_info) {
696 .name = "xilinx_spi", .pci_offset = 0,
697 .data_size = sizeof(struct xspi_platform_data),
698 .data = &(struct xspi_platform_data) {
699 .num_chipselect = 1,
700 .bits_per_word = 8,
701 .num_devices = 1,
702 .force_irq = true,
703 .devices = &(struct spi_board_info) {
704 .modalias = "spi-nor",
705 },
706 },
707 },
708 },
709 {
710 OCP_MEM_RESOURCE(freq_in[0]),
711 .offset = 0x01200000, .size = 0x10000,
712 },
713 {
714 OCP_MEM_RESOURCE(freq_in[1]),
715 .offset = 0x01210000, .size = 0x10000,
716 },
717 {
718 OCP_MEM_RESOURCE(freq_in[2]),
719 .offset = 0x01220000, .size = 0x10000,
720 },
721 {
722 OCP_MEM_RESOURCE(freq_in[3]),
723 .offset = 0x01230000, .size = 0x10000,
724 },
725 {
726 .setup = ptp_ocp_fb_board_init,
727 .extra = &(struct ptp_ocp_servo_conf) {
728 .servo_offset_p = 0x2000,
729 .servo_offset_i = 0x1000,
730 .servo_drift_p = 0,
731 .servo_drift_i = 0,
732 },
733 },
734 { }
735 };
736
737 #define OCP_ART_CONFIG_SIZE 144
738 #define OCP_ART_TEMP_TABLE_SIZE 368
739
740 struct ocp_art_gpio_reg {
741 struct {
742 u32 gpio;
743 u32 __pad[3];
744 } map[4];
745 };
746
747 static struct ocp_resource ocp_art_resource[] = {
748 {
749 OCP_MEM_RESOURCE(reg),
750 .offset = 0x01000000, .size = 0x10000,
751 },
752 {
753 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
754 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
755 .extra = &(struct ptp_ocp_serial_port) {
756 .baud = 115200,
757 },
758 },
759 {
760 OCP_MEM_RESOURCE(art_sma),
761 .offset = 0x003C0000, .size = 0x1000,
762 },
763 /* Timestamp associated with GNSS1 receiver PPS */
764 {
765 OCP_EXT_RESOURCE(ts0),
766 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
767 .extra = &(struct ptp_ocp_ext_info) {
768 .index = 0,
769 .irq_fcn = ptp_ocp_ts_irq,
770 .enable = ptp_ocp_ts_enable,
771 },
772 },
773 {
774 OCP_EXT_RESOURCE(ts1),
775 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
776 .extra = &(struct ptp_ocp_ext_info) {
777 .index = 1,
778 .irq_fcn = ptp_ocp_ts_irq,
779 .enable = ptp_ocp_ts_enable,
780 },
781 },
782 {
783 OCP_EXT_RESOURCE(ts2),
784 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
785 .extra = &(struct ptp_ocp_ext_info) {
786 .index = 2,
787 .irq_fcn = ptp_ocp_ts_irq,
788 .enable = ptp_ocp_ts_enable,
789 },
790 },
791 {
792 OCP_EXT_RESOURCE(ts3),
793 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
794 .extra = &(struct ptp_ocp_ext_info) {
795 .index = 3,
796 .irq_fcn = ptp_ocp_ts_irq,
797 .enable = ptp_ocp_ts_enable,
798 },
799 },
800 {
801 OCP_EXT_RESOURCE(ts4),
802 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
803 .extra = &(struct ptp_ocp_ext_info) {
804 .index = 4,
805 .irq_fcn = ptp_ocp_ts_irq,
806 .enable = ptp_ocp_ts_enable,
807 },
808 },
809 /* Timestamp associated with Internal PPS of the card */
810 {
811 OCP_EXT_RESOURCE(pps),
812 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
813 .extra = &(struct ptp_ocp_ext_info) {
814 .index = 5,
815 .irq_fcn = ptp_ocp_ts_irq,
816 .enable = ptp_ocp_ts_enable,
817 },
818 },
819 {
820 OCP_SPI_RESOURCE(spi_flash),
821 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
822 .extra = &(struct ptp_ocp_flash_info) {
823 .name = "spi_altera", .pci_offset = 0,
824 .data_size = sizeof(struct altera_spi_platform_data),
825 .data = &(struct altera_spi_platform_data) {
826 .num_chipselect = 1,
827 .num_devices = 1,
828 .devices = &(struct spi_board_info) {
829 .modalias = "spi-nor",
830 },
831 },
832 },
833 },
834 {
835 OCP_I2C_RESOURCE(i2c_ctrl),
836 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
837 .extra = &(struct ptp_ocp_i2c_info) {
838 .name = "ocores-i2c",
839 .fixed_rate = 400000,
840 .data_size = sizeof(struct ocores_i2c_platform_data),
841 .data = &(struct ocores_i2c_platform_data) {
842 .clock_khz = 125000,
843 .bus_khz = 400,
844 .num_devices = 1,
845 .devices = &(struct i2c_board_info) {
846 I2C_BOARD_INFO("24c08", 0x50),
847 },
848 },
849 },
850 },
851 {
852 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
853 .offset = 0x00190000, .irq_vec = 7,
854 .extra = &(struct ptp_ocp_serial_port) {
855 .baud = 9600,
856 },
857 },
858 {
859 OCP_MEM_RESOURCE(board_config),
860 .offset = 0x210000, .size = 0x1000,
861 },
862 {
863 .setup = ptp_ocp_art_board_init,
864 .extra = &(struct ptp_ocp_servo_conf) {
865 .servo_offset_p = 0x2000,
866 .servo_offset_i = 0x1000,
867 .servo_drift_p = 0,
868 .servo_drift_i = 0,
869 },
870 },
871 { }
872 };
873
874 static struct ocp_resource ocp_adva_resource[] = {
875 {
876 OCP_MEM_RESOURCE(reg),
877 .offset = 0x01000000, .size = 0x10000,
878 },
879 {
880 OCP_EXT_RESOURCE(ts0),
881 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
882 .extra = &(struct ptp_ocp_ext_info) {
883 .index = 0,
884 .irq_fcn = ptp_ocp_ts_irq,
885 .enable = ptp_ocp_ts_enable,
886 },
887 },
888 {
889 OCP_EXT_RESOURCE(ts1),
890 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
891 .extra = &(struct ptp_ocp_ext_info) {
892 .index = 1,
893 .irq_fcn = ptp_ocp_ts_irq,
894 .enable = ptp_ocp_ts_enable,
895 },
896 },
897 {
898 OCP_EXT_RESOURCE(ts2),
899 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
900 .extra = &(struct ptp_ocp_ext_info) {
901 .index = 2,
902 .irq_fcn = ptp_ocp_ts_irq,
903 .enable = ptp_ocp_ts_enable,
904 },
905 },
906 /* Timestamp for PHC and/or PPS generator */
907 {
908 OCP_EXT_RESOURCE(pps),
909 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
910 .extra = &(struct ptp_ocp_ext_info) {
911 .index = 5,
912 .irq_fcn = ptp_ocp_ts_irq,
913 .enable = ptp_ocp_ts_enable,
914 },
915 },
916 {
917 OCP_EXT_RESOURCE(signal_out[0]),
918 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
919 .extra = &(struct ptp_ocp_ext_info) {
920 .index = 1,
921 .irq_fcn = ptp_ocp_signal_irq,
922 .enable = ptp_ocp_signal_enable,
923 },
924 },
925 {
926 OCP_EXT_RESOURCE(signal_out[1]),
927 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
928 .extra = &(struct ptp_ocp_ext_info) {
929 .index = 2,
930 .irq_fcn = ptp_ocp_signal_irq,
931 .enable = ptp_ocp_signal_enable,
932 },
933 },
934 {
935 OCP_MEM_RESOURCE(pps_to_ext),
936 .offset = 0x01030000, .size = 0x10000,
937 },
938 {
939 OCP_MEM_RESOURCE(pps_to_clk),
940 .offset = 0x01040000, .size = 0x10000,
941 },
942 {
943 OCP_MEM_RESOURCE(tod),
944 .offset = 0x01050000, .size = 0x10000,
945 },
946 {
947 OCP_MEM_RESOURCE(image),
948 .offset = 0x00020000, .size = 0x1000,
949 },
950 {
951 OCP_MEM_RESOURCE(pps_select),
952 .offset = 0x00130000, .size = 0x1000,
953 },
954 {
955 OCP_MEM_RESOURCE(sma_map1),
956 .offset = 0x00140000, .size = 0x1000,
957 },
958 {
959 OCP_MEM_RESOURCE(sma_map2),
960 .offset = 0x00220000, .size = 0x1000,
961 },
962 {
963 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
964 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
965 .extra = &(struct ptp_ocp_serial_port) {
966 .baud = 9600,
967 },
968 },
969 {
970 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
971 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
972 .extra = &(struct ptp_ocp_serial_port) {
973 .baud = 115200,
974 },
975 },
976 {
977 OCP_MEM_RESOURCE(freq_in[0]),
978 .offset = 0x01200000, .size = 0x10000,
979 },
980 {
981 OCP_MEM_RESOURCE(freq_in[1]),
982 .offset = 0x01210000, .size = 0x10000,
983 },
984 {
985 OCP_SPI_RESOURCE(spi_flash),
986 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
987 .extra = &(struct ptp_ocp_flash_info) {
988 .name = "spi_altera", .pci_offset = 0,
989 .data_size = sizeof(struct altera_spi_platform_data),
990 .data = &(struct altera_spi_platform_data) {
991 .num_chipselect = 1,
992 .num_devices = 1,
993 .devices = &(struct spi_board_info) {
994 .modalias = "spi-nor",
995 },
996 },
997 },
998 },
999 {
1000 OCP_I2C_RESOURCE(i2c_ctrl),
1001 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1002 .extra = &(struct ptp_ocp_i2c_info) {
1003 .name = "ocores-i2c",
1004 .fixed_rate = 50000000,
1005 .data_size = sizeof(struct ocores_i2c_platform_data),
1006 .data = &(struct ocores_i2c_platform_data) {
1007 .clock_khz = 50000,
1008 .bus_khz = 100,
1009 .reg_io_width = 4, // 32-bit/4-byte
1010 .reg_shift = 2, // 32-bit addressing
1011 .num_devices = 2,
1012 .devices = (struct i2c_board_info[]) {
1013 { I2C_BOARD_INFO("24c02", 0x50) },
1014 { I2C_BOARD_INFO("24mac402", 0x58),
1015 .platform_data = "mac" },
1016 },
1017 },
1018 },
1019 },
1020 {
1021 .setup = ptp_ocp_adva_board_init,
1022 .extra = &(struct ptp_ocp_servo_conf) {
1023 .servo_offset_p = 0xc000,
1024 .servo_offset_i = 0x1000,
1025 .servo_drift_p = 0,
1026 .servo_drift_i = 0,
1027 },
1028 },
1029 { }
1030 };
1031
1032 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1033 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1034 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1035 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1036 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1037 { }
1038 };
1039 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1040
1041 static DEFINE_MUTEX(ptp_ocp_lock);
1042 static DEFINE_IDR(ptp_ocp_idr);
1043
1044 struct ocp_selector {
1045 const char *name;
1046 int value;
1047 u64 frequency;
1048 };
1049
1050 static const struct ocp_selector ptp_ocp_clock[] = {
1051 { .name = "NONE", .value = 0 },
1052 { .name = "TOD", .value = 1 },
1053 { .name = "IRIG", .value = 2 },
1054 { .name = "PPS", .value = 3 },
1055 { .name = "PTP", .value = 4 },
1056 { .name = "RTC", .value = 5 },
1057 { .name = "DCF", .value = 6 },
1058 { .name = "REGS", .value = 0xfe },
1059 { .name = "EXT", .value = 0xff },
1060 { }
1061 };
1062
1063 #define SMA_DISABLE BIT(16)
1064 #define SMA_ENABLE BIT(15)
1065 #define SMA_SELECT_MASK GENMASK(14, 0)
1066
1067 static const struct ocp_selector ptp_ocp_sma_in[] = {
1068 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1069 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1070 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1071 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1072 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1073 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1074 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1075 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1076 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1077 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1078 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1079 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1080 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1081 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1082 { }
1083 };
1084
1085 static const struct ocp_selector ptp_ocp_sma_out[] = {
1086 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1087 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1088 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1089 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1090 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1091 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1092 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1093 { .name = "GEN1", .value = 0x0040 },
1094 { .name = "GEN2", .value = 0x0080 },
1095 { .name = "GEN3", .value = 0x0100 },
1096 { .name = "GEN4", .value = 0x0200 },
1097 { .name = "GND", .value = 0x2000 },
1098 { .name = "VCC", .value = 0x4000 },
1099 { }
1100 };
1101
1102 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1103 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1104 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1105 { }
1106 };
1107
1108 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1109 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1110 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1111 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1112 { }
1113 };
1114
1115 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1116 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1117 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1118 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1119 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1120 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1121 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1122 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1123 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1124 { }
1125 };
1126
1127 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1128 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1129 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1130 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1131 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1132 { .name = "GEN1", .value = 0x0040 },
1133 { .name = "GEN2", .value = 0x0080 },
1134 { .name = "GND", .value = 0x2000 },
1135 { .name = "VCC", .value = 0x4000 },
1136 { }
1137 };
1138
1139 struct ocp_sma_op {
1140 const struct ocp_selector *tbl[2];
1141 void (*init)(struct ptp_ocp *bp);
1142 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1143 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1144 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1145 };
1146
1147 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1148 ptp_ocp_sma_init(struct ptp_ocp *bp)
1149 {
1150 return bp->sma_op->init(bp);
1151 }
1152
1153 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1154 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1155 {
1156 return bp->sma_op->get(bp, sma_nr);
1157 }
1158
1159 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1160 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1161 {
1162 return bp->sma_op->set_inputs(bp, sma_nr, val);
1163 }
1164
1165 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1166 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1167 {
1168 return bp->sma_op->set_output(bp, sma_nr, val);
1169 }
1170
1171 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1172 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1173 {
1174 int i;
1175
1176 for (i = 0; tbl[i].name; i++)
1177 if (tbl[i].value == val)
1178 return tbl[i].name;
1179 return NULL;
1180 }
1181
1182 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1183 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1184 {
1185 const char *select;
1186 int i;
1187
1188 for (i = 0; tbl[i].name; i++) {
1189 select = tbl[i].name;
1190 if (!strncasecmp(name, select, strlen(select)))
1191 return tbl[i].value;
1192 }
1193 return -EINVAL;
1194 }
1195
1196 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1197 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1198 {
1199 ssize_t count;
1200 int i;
1201
1202 count = 0;
1203 for (i = 0; tbl[i].name; i++)
1204 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1205 if (count)
1206 count--;
1207 count += sysfs_emit_at(buf, count, "\n");
1208 return count;
1209 }
1210
1211 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1212 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1213 struct ptp_system_timestamp *sts)
1214 {
1215 u32 ctrl, time_sec, time_ns;
1216 int i;
1217
1218 ptp_read_system_prets(sts);
1219
1220 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1221 iowrite32(ctrl, &bp->reg->ctrl);
1222
1223 for (i = 0; i < 100; i++) {
1224 ctrl = ioread32(&bp->reg->ctrl);
1225 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1226 break;
1227 }
1228 ptp_read_system_postts(sts);
1229
1230 if (sts && bp->ts_window_adjust) {
1231 s64 ns = timespec64_to_ns(&sts->post_ts);
1232
1233 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1234 }
1235
1236 time_ns = ioread32(&bp->reg->time_ns);
1237 time_sec = ioread32(&bp->reg->time_sec);
1238
1239 ts->tv_sec = time_sec;
1240 ts->tv_nsec = time_ns;
1241
1242 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1243 }
1244
1245 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1246 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1247 struct ptp_system_timestamp *sts)
1248 {
1249 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1250 unsigned long flags;
1251 int err;
1252
1253 spin_lock_irqsave(&bp->lock, flags);
1254 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1255 spin_unlock_irqrestore(&bp->lock, flags);
1256
1257 return err;
1258 }
1259
1260 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1261 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1262 {
1263 u32 ctrl, time_sec, time_ns;
1264 u32 select;
1265
1266 time_ns = ts->tv_nsec;
1267 time_sec = ts->tv_sec;
1268
1269 select = ioread32(&bp->reg->select);
1270 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1271
1272 iowrite32(time_ns, &bp->reg->adjust_ns);
1273 iowrite32(time_sec, &bp->reg->adjust_sec);
1274
1275 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1276 iowrite32(ctrl, &bp->reg->ctrl);
1277
1278 /* restore clock selection */
1279 iowrite32(select >> 16, &bp->reg->select);
1280 }
1281
1282 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1283 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1284 {
1285 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1286 unsigned long flags;
1287
1288 spin_lock_irqsave(&bp->lock, flags);
1289 __ptp_ocp_settime_locked(bp, ts);
1290 spin_unlock_irqrestore(&bp->lock, flags);
1291
1292 return 0;
1293 }
1294
1295 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1296 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1297 {
1298 u32 select, ctrl;
1299
1300 select = ioread32(&bp->reg->select);
1301 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1302
1303 iowrite32(adj_val, &bp->reg->offset_ns);
1304 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1305
1306 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1307 iowrite32(ctrl, &bp->reg->ctrl);
1308
1309 /* restore clock selection */
1310 iowrite32(select >> 16, &bp->reg->select);
1311 }
1312
1313 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1314 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1315 {
1316 struct timespec64 ts;
1317 unsigned long flags;
1318 int err;
1319
1320 spin_lock_irqsave(&bp->lock, flags);
1321 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1322 if (likely(!err)) {
1323 set_normalized_timespec64(&ts, ts.tv_sec,
1324 ts.tv_nsec + delta_ns);
1325 __ptp_ocp_settime_locked(bp, &ts);
1326 }
1327 spin_unlock_irqrestore(&bp->lock, flags);
1328 }
1329
1330 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1331 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1332 {
1333 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1334 unsigned long flags;
1335 u32 adj_ns, sign;
1336
1337 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1338 ptp_ocp_adjtime_coarse(bp, delta_ns);
1339 return 0;
1340 }
1341
1342 sign = delta_ns < 0 ? BIT(31) : 0;
1343 adj_ns = sign ? -delta_ns : delta_ns;
1344
1345 spin_lock_irqsave(&bp->lock, flags);
1346 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1347 spin_unlock_irqrestore(&bp->lock, flags);
1348
1349 return 0;
1350 }
1351
1352 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1353 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1354 {
1355 if (scaled_ppm == 0)
1356 return 0;
1357
1358 return -EOPNOTSUPP;
1359 }
1360
1361 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1362 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1363 {
1364 return 0;
1365 }
1366
1367 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1368 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1369 {
1370 return -EOPNOTSUPP;
1371 }
1372
1373 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1374 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1375 int on)
1376 {
1377 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1378 struct ptp_ocp_ext_src *ext = NULL;
1379 u32 req;
1380 int err;
1381
1382 switch (rq->type) {
1383 case PTP_CLK_REQ_EXTTS:
1384 req = OCP_REQ_TIMESTAMP;
1385 switch (rq->extts.index) {
1386 case 0:
1387 ext = bp->ts0;
1388 break;
1389 case 1:
1390 ext = bp->ts1;
1391 break;
1392 case 2:
1393 ext = bp->ts2;
1394 break;
1395 case 3:
1396 ext = bp->ts3;
1397 break;
1398 case 4:
1399 ext = bp->ts4;
1400 break;
1401 case 5:
1402 ext = bp->pps;
1403 break;
1404 }
1405 break;
1406 case PTP_CLK_REQ_PPS:
1407 req = OCP_REQ_PPS;
1408 ext = bp->pps;
1409 break;
1410 case PTP_CLK_REQ_PEROUT:
1411 switch (rq->perout.index) {
1412 case 0:
1413 /* This is a request for 1PPS on an output SMA.
1414 * Allow, but assume manual configuration.
1415 */
1416 if (on && (rq->perout.period.sec != 1 ||
1417 rq->perout.period.nsec != 0))
1418 return -EINVAL;
1419 return 0;
1420 case 1:
1421 case 2:
1422 case 3:
1423 case 4:
1424 req = rq->perout.index - 1;
1425 ext = bp->signal_out[req];
1426 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1427 if (err)
1428 return err;
1429 break;
1430 }
1431 break;
1432 default:
1433 return -EOPNOTSUPP;
1434 }
1435
1436 err = -ENXIO;
1437 if (ext)
1438 err = ext->info->enable(ext, req, on);
1439
1440 return err;
1441 }
1442
1443 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1444 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1445 enum ptp_pin_function func, unsigned chan)
1446 {
1447 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1448 char buf[16];
1449
1450 switch (func) {
1451 case PTP_PF_NONE:
1452 snprintf(buf, sizeof(buf), "IN: None");
1453 break;
1454 case PTP_PF_EXTTS:
1455 /* Allow timestamps, but require sysfs configuration. */
1456 return 0;
1457 case PTP_PF_PEROUT:
1458 /* channel 0 is 1PPS from PHC.
1459 * channels 1..4 are the frequency generators.
1460 */
1461 if (chan)
1462 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1463 else
1464 snprintf(buf, sizeof(buf), "OUT: PHC");
1465 break;
1466 default:
1467 return -EOPNOTSUPP;
1468 }
1469
1470 return ptp_ocp_sma_store(bp, buf, pin + 1);
1471 }
1472
1473 static const struct ptp_clock_info ptp_ocp_clock_info = {
1474 .owner = THIS_MODULE,
1475 .name = KBUILD_MODNAME,
1476 .max_adj = 100000000,
1477 .gettimex64 = ptp_ocp_gettimex,
1478 .settime64 = ptp_ocp_settime,
1479 .adjtime = ptp_ocp_adjtime,
1480 .adjfine = ptp_ocp_null_adjfine,
1481 .adjphase = ptp_ocp_null_adjphase,
1482 .getmaxphase = ptp_ocp_null_getmaxphase,
1483 .enable = ptp_ocp_enable,
1484 .verify = ptp_ocp_verify,
1485 .pps = true,
1486 .n_ext_ts = 6,
1487 .n_per_out = 5,
1488 .supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE,
1489 .supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE,
1490 };
1491
1492 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1493 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1494 {
1495 u32 ctrl, select;
1496
1497 select = ioread32(&bp->reg->select);
1498 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1499
1500 iowrite32(0, &bp->reg->drift_ns);
1501
1502 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1503 iowrite32(ctrl, &bp->reg->ctrl);
1504
1505 /* restore clock selection */
1506 iowrite32(select >> 16, &bp->reg->select);
1507 }
1508
1509 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1510 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1511 {
1512 unsigned long flags;
1513
1514 spin_lock_irqsave(&bp->lock, flags);
1515
1516 bp->utc_tai_offset = val;
1517
1518 if (bp->irig_out)
1519 iowrite32(val, &bp->irig_out->adj_sec);
1520 if (bp->dcf_out)
1521 iowrite32(val, &bp->dcf_out->adj_sec);
1522 if (bp->nmea_out)
1523 iowrite32(val, &bp->nmea_out->adj_sec);
1524
1525 spin_unlock_irqrestore(&bp->lock, flags);
1526 }
1527
1528 static void
ptp_ocp_watchdog(struct timer_list * t)1529 ptp_ocp_watchdog(struct timer_list *t)
1530 {
1531 struct ptp_ocp *bp = timer_container_of(bp, t, watchdog);
1532 unsigned long flags;
1533 u32 status, utc_offset;
1534
1535 status = ioread32(&bp->pps_to_clk->status);
1536
1537 if (status & PPS_STATUS_SUPERV_ERR) {
1538 iowrite32(status, &bp->pps_to_clk->status);
1539 if (!bp->gnss_lost) {
1540 spin_lock_irqsave(&bp->lock, flags);
1541 __ptp_ocp_clear_drift_locked(bp);
1542 spin_unlock_irqrestore(&bp->lock, flags);
1543 bp->gnss_lost = ktime_get_real_seconds();
1544 }
1545
1546 } else if (bp->gnss_lost) {
1547 bp->gnss_lost = 0;
1548 }
1549
1550 /* if GNSS provides correct data we can rely on
1551 * it to get leap second information
1552 */
1553 if (bp->tod) {
1554 status = ioread32(&bp->tod->utc_status);
1555 utc_offset = status & TOD_STATUS_UTC_MASK;
1556 if (status & TOD_STATUS_UTC_VALID &&
1557 utc_offset != bp->utc_tai_offset)
1558 ptp_ocp_utc_distribute(bp, utc_offset);
1559 }
1560
1561 mod_timer(&bp->watchdog, jiffies + HZ);
1562 }
1563
1564 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1565 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1566 {
1567 ktime_t start, end, delay = U64_MAX;
1568 u32 ctrl;
1569 int i;
1570
1571 for (i = 0; i < 3; i++) {
1572 ctrl = ioread32(&bp->reg->ctrl);
1573 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1574
1575 iowrite32(ctrl, &bp->reg->ctrl);
1576
1577 start = ktime_get_raw_ns();
1578
1579 ctrl = ioread32(&bp->reg->ctrl);
1580
1581 end = ktime_get_raw_ns();
1582
1583 delay = min(delay, end - start);
1584 }
1585 bp->ts_window_adjust = (delay >> 5) * 3;
1586 }
1587
1588 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1589 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1590 {
1591 struct timespec64 ts;
1592 u32 ctrl;
1593
1594 ctrl = OCP_CTRL_ENABLE;
1595 iowrite32(ctrl, &bp->reg->ctrl);
1596
1597 /* servo configuration */
1598 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1599 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1600 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1601 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1602
1603 /* latch servo values */
1604 ctrl |= OCP_CTRL_ADJUST_SERVO;
1605 iowrite32(ctrl, &bp->reg->ctrl);
1606
1607 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1608 dev_err(&bp->pdev->dev, "clock not enabled\n");
1609 return -ENODEV;
1610 }
1611
1612 ptp_ocp_estimate_pci_timing(bp);
1613
1614 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1615 if (!bp->sync) {
1616 ktime_get_clocktai_ts64(&ts);
1617 ptp_ocp_settime(&bp->ptp_info, &ts);
1618 }
1619
1620 /* If there is a clock supervisor, then enable the watchdog */
1621 if (bp->pps_to_clk) {
1622 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1623 mod_timer(&bp->watchdog, jiffies + HZ);
1624 }
1625
1626 return 0;
1627 }
1628
1629 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1630 ptp_ocp_tod_init(struct ptp_ocp *bp)
1631 {
1632 u32 ctrl, reg;
1633
1634 ctrl = ioread32(&bp->tod->ctrl);
1635 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1636 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1637 iowrite32(ctrl, &bp->tod->ctrl);
1638
1639 reg = ioread32(&bp->tod->utc_status);
1640 if (reg & TOD_STATUS_UTC_VALID)
1641 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1642 }
1643
1644 static const char *
ptp_ocp_tod_proto_name(const int idx)1645 ptp_ocp_tod_proto_name(const int idx)
1646 {
1647 static const char * const proto_name[] = {
1648 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1649 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1650 };
1651 return proto_name[idx];
1652 }
1653
1654 static const char *
ptp_ocp_tod_gnss_name(int idx)1655 ptp_ocp_tod_gnss_name(int idx)
1656 {
1657 static const char * const gnss_name[] = {
1658 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1659 "Unknown"
1660 };
1661 if (idx >= ARRAY_SIZE(gnss_name))
1662 idx = ARRAY_SIZE(gnss_name) - 1;
1663 return gnss_name[idx];
1664 }
1665
1666 static const char *
ptp_ocp_tty_port_name(int idx)1667 ptp_ocp_tty_port_name(int idx)
1668 {
1669 static const char * const tty_name[] = {
1670 "GNSS", "GNSS2", "MAC", "NMEA"
1671 };
1672 return tty_name[idx];
1673 }
1674
1675 struct ptp_ocp_nvmem_match_info {
1676 struct ptp_ocp *bp;
1677 const void * const tag;
1678 };
1679
1680 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1681 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1682 {
1683 const struct ptp_ocp_nvmem_match_info *info = data;
1684
1685 dev = dev->parent;
1686 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1687 return 0;
1688
1689 while ((dev = dev->parent))
1690 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1691 return info->bp == dev_get_drvdata(dev);
1692 return 0;
1693 }
1694
1695 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1696 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1697 {
1698 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1699
1700 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1701 }
1702
1703 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1704 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1705 {
1706 if (!IS_ERR_OR_NULL(*nvmemp))
1707 nvmem_device_put(*nvmemp);
1708 *nvmemp = NULL;
1709 }
1710
1711 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1712 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1713 {
1714 const struct ptp_ocp_eeprom_map *map;
1715 struct nvmem_device *nvmem;
1716 const void *tag;
1717 int ret;
1718
1719 if (!bp->i2c_ctrl)
1720 return;
1721
1722 tag = NULL;
1723 nvmem = NULL;
1724
1725 for (map = bp->eeprom_map; map->len; map++) {
1726 if (map->tag != tag) {
1727 tag = map->tag;
1728 ptp_ocp_nvmem_device_put(&nvmem);
1729 }
1730 if (!nvmem) {
1731 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1732 if (IS_ERR(nvmem)) {
1733 ret = PTR_ERR(nvmem);
1734 goto fail;
1735 }
1736 }
1737 ret = nvmem_device_read(nvmem, map->off, map->len,
1738 BP_MAP_ENTRY_ADDR(bp, map));
1739 if (ret != map->len)
1740 goto fail;
1741 }
1742
1743 bp->has_eeprom_data = true;
1744
1745 out:
1746 ptp_ocp_nvmem_device_put(&nvmem);
1747 return;
1748
1749 fail:
1750 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1751 goto out;
1752 }
1753
1754 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1755 ptp_ocp_find_flash(struct ptp_ocp *bp)
1756 {
1757 struct device *dev, *last;
1758
1759 last = NULL;
1760 dev = &bp->spi_flash->dev;
1761
1762 while ((dev = device_find_any_child(dev))) {
1763 if (!strcmp("mtd", dev_bus_name(dev)))
1764 break;
1765 put_device(last);
1766 last = dev;
1767 }
1768 put_device(last);
1769
1770 return dev;
1771 }
1772
1773 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1774 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1775 const u8 **data, size_t *size)
1776 {
1777 struct ptp_ocp *bp = devlink_priv(devlink);
1778 const struct ptp_ocp_firmware_header *hdr;
1779 size_t offset, length;
1780 u16 crc;
1781
1782 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1783 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1784 devlink_flash_update_status_notify(devlink,
1785 "No firmware header found, cancel firmware upgrade",
1786 NULL, 0, 0);
1787 return -EINVAL;
1788 }
1789
1790 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1791 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1792 devlink_flash_update_status_notify(devlink,
1793 "Firmware image compatibility check failed",
1794 NULL, 0, 0);
1795 return -EINVAL;
1796 }
1797
1798 offset = sizeof(*hdr);
1799 length = be32_to_cpu(hdr->image_size);
1800 if (length != (fw->size - offset)) {
1801 devlink_flash_update_status_notify(devlink,
1802 "Firmware image size check failed",
1803 NULL, 0, 0);
1804 return -EINVAL;
1805 }
1806
1807 crc = crc16(0xffff, &fw->data[offset], length);
1808 if (be16_to_cpu(hdr->crc) != crc) {
1809 devlink_flash_update_status_notify(devlink,
1810 "Firmware image CRC check failed",
1811 NULL, 0, 0);
1812 return -EINVAL;
1813 }
1814
1815 *data = &fw->data[offset];
1816 *size = length;
1817
1818 return 0;
1819 }
1820
1821 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1822 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1823 const struct firmware *fw)
1824 {
1825 struct mtd_info *mtd = dev_get_drvdata(dev);
1826 struct ptp_ocp *bp = devlink_priv(devlink);
1827 size_t off, len, size, resid, wrote;
1828 struct erase_info erase;
1829 size_t base, blksz;
1830 const u8 *data;
1831 int err;
1832
1833 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1834 if (err)
1835 goto out;
1836
1837 off = 0;
1838 base = bp->flash_start;
1839 blksz = 4096;
1840 resid = size;
1841
1842 while (resid) {
1843 devlink_flash_update_status_notify(devlink, "Flashing",
1844 NULL, off, size);
1845
1846 len = min_t(size_t, resid, blksz);
1847 erase.addr = base + off;
1848 erase.len = blksz;
1849
1850 err = mtd_erase(mtd, &erase);
1851 if (err)
1852 goto out;
1853
1854 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1855 if (err)
1856 goto out;
1857
1858 off += blksz;
1859 resid -= len;
1860 }
1861 out:
1862 return err;
1863 }
1864
1865 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1866 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1867 struct devlink_flash_update_params *params,
1868 struct netlink_ext_ack *extack)
1869 {
1870 struct ptp_ocp *bp = devlink_priv(devlink);
1871 struct device *dev;
1872 const char *msg;
1873 int err;
1874
1875 dev = ptp_ocp_find_flash(bp);
1876 if (!dev) {
1877 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1878 return -ENODEV;
1879 }
1880
1881 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1882 NULL, 0, 0);
1883
1884 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1885
1886 msg = err ? "Flash error" : "Flash complete";
1887 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1888
1889 put_device(dev);
1890 return err;
1891 }
1892
1893 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1894 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1895 struct netlink_ext_ack *extack)
1896 {
1897 struct ptp_ocp *bp = devlink_priv(devlink);
1898 const char *fw_image;
1899 char buf[32];
1900 int err;
1901
1902 fw_image = bp->fw_loader ? "loader" : "fw";
1903 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1904 err = devlink_info_version_running_put(req, fw_image, buf);
1905 if (err)
1906 return err;
1907
1908 if (!bp->has_eeprom_data) {
1909 ptp_ocp_read_eeprom(bp);
1910 if (!bp->has_eeprom_data)
1911 return 0;
1912 }
1913
1914 sprintf(buf, "%pM", bp->serial);
1915 err = devlink_info_serial_number_put(req, buf);
1916 if (err)
1917 return err;
1918
1919 err = devlink_info_version_fixed_put(req,
1920 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1921 bp->board_id);
1922 if (err)
1923 return err;
1924
1925 return 0;
1926 }
1927
1928 static const struct devlink_ops ptp_ocp_devlink_ops = {
1929 .flash_update = ptp_ocp_devlink_flash_update,
1930 .info_get = ptp_ocp_devlink_info_get,
1931 };
1932
1933 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1934 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1935 {
1936 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1937
1938 return devm_ioremap_resource(&bp->pdev->dev, &res);
1939 }
1940
1941 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1942 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1943 {
1944 resource_size_t start;
1945
1946 start = pci_resource_start(bp->pdev, 0) + r->offset;
1947 return __ptp_ocp_get_mem(bp, start, r->size);
1948 }
1949
1950 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1951 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1952 {
1953 struct ptp_ocp_flash_info *info;
1954 struct pci_dev *pdev = bp->pdev;
1955 struct platform_device *p;
1956 struct resource res[2];
1957 resource_size_t start;
1958 int id;
1959
1960 start = pci_resource_start(pdev, 0) + r->offset;
1961 res[0] = DEFINE_RES_MEM(start, r->size);
1962 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1963
1964 info = r->extra;
1965 id = pci_dev_id(pdev) << 1;
1966 id += info->pci_offset;
1967
1968 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1969 res, ARRAY_SIZE(res), info->data,
1970 info->data_size);
1971 if (IS_ERR(p))
1972 return PTR_ERR(p);
1973
1974 bp_assign_entry(bp, r, p);
1975
1976 return 0;
1977 }
1978
1979 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1980 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1981 {
1982 struct ptp_ocp_i2c_info *info;
1983 struct resource res[2];
1984 resource_size_t start;
1985
1986 info = r->extra;
1987 start = pci_resource_start(pdev, 0) + r->offset;
1988 res[0] = DEFINE_RES_MEM(start, r->size);
1989 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1990
1991 return platform_device_register_resndata(&pdev->dev, info->name,
1992 id, res, ARRAY_SIZE(res),
1993 info->data, info->data_size);
1994 }
1995
1996 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1997 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1998 {
1999 struct pci_dev *pdev = bp->pdev;
2000 struct ptp_ocp_i2c_info *info;
2001 struct platform_device *p;
2002 struct clk_hw *clk;
2003 char buf[32];
2004 int id;
2005
2006 info = r->extra;
2007 id = pci_dev_id(bp->pdev);
2008
2009 sprintf(buf, "AXI.%d", id);
2010 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2011 info->fixed_rate);
2012 if (IS_ERR(clk))
2013 return PTR_ERR(clk);
2014 bp->i2c_clk = clk;
2015
2016 sprintf(buf, "%s.%d", info->name, id);
2017 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2018 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2019 if (IS_ERR(p))
2020 return PTR_ERR(p);
2021
2022 bp_assign_entry(bp, r, p);
2023
2024 return 0;
2025 }
2026
2027 /* The expectation is that this is triggered only on error. */
2028 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2029 ptp_ocp_signal_irq(int irq, void *priv)
2030 {
2031 struct ptp_ocp_ext_src *ext = priv;
2032 struct signal_reg __iomem *reg = ext->mem;
2033 struct ptp_ocp *bp = ext->bp;
2034 u32 enable, status;
2035 int gen;
2036
2037 gen = ext->info->index - 1;
2038
2039 enable = ioread32(®->enable);
2040 status = ioread32(®->status);
2041
2042 /* disable generator on error */
2043 if (status || !enable) {
2044 iowrite32(0, ®->intr_mask);
2045 iowrite32(0, ®->enable);
2046 bp->signal[gen].running = false;
2047 }
2048
2049 iowrite32(0, ®->intr); /* ack interrupt */
2050
2051 return IRQ_HANDLED;
2052 }
2053
2054 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2055 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2056 {
2057 struct ptp_system_timestamp sts;
2058 struct timespec64 ts;
2059 ktime_t start_ns;
2060 int err;
2061
2062 if (!s->period)
2063 return 0;
2064
2065 if (!s->pulse)
2066 s->pulse = ktime_divns(s->period * s->duty, 100);
2067
2068 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2069 if (err)
2070 return err;
2071
2072 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2073 if (!s->start) {
2074 /* roundup() does not work on 32-bit systems */
2075 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2076 s->start *= s->period;
2077 s->start = ktime_add(s->start, s->phase);
2078 }
2079
2080 if (s->duty < 1 || s->duty > 99)
2081 return -EINVAL;
2082
2083 if (s->pulse < 1 || s->pulse > s->period)
2084 return -EINVAL;
2085
2086 if (s->start < start_ns)
2087 return -EINVAL;
2088
2089 bp->signal[gen] = *s;
2090
2091 return 0;
2092 }
2093
2094 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2095 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2096 struct ptp_perout_request *req)
2097 {
2098 struct ptp_ocp_signal s = { };
2099
2100 s.polarity = bp->signal[gen].polarity;
2101 s.period = ktime_set(req->period.sec, req->period.nsec);
2102 if (!s.period)
2103 return 0;
2104
2105 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2106 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2107 s.duty = ktime_divns(s.pulse * 100, s.period);
2108 }
2109
2110 if (req->flags & PTP_PEROUT_PHASE)
2111 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2112 else
2113 s.start = ktime_set(req->start.sec, req->start.nsec);
2114
2115 return ptp_ocp_signal_set(bp, gen, &s);
2116 }
2117
2118 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2119 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2120 {
2121 struct ptp_ocp_ext_src *ext = priv;
2122 struct signal_reg __iomem *reg = ext->mem;
2123 struct ptp_ocp *bp = ext->bp;
2124 struct timespec64 ts;
2125 int gen;
2126
2127 gen = ext->info->index - 1;
2128
2129 iowrite32(0, ®->intr_mask);
2130 iowrite32(0, ®->enable);
2131 bp->signal[gen].running = false;
2132 if (!enable)
2133 return 0;
2134
2135 ts = ktime_to_timespec64(bp->signal[gen].start);
2136 iowrite32(ts.tv_sec, ®->start_sec);
2137 iowrite32(ts.tv_nsec, ®->start_ns);
2138
2139 ts = ktime_to_timespec64(bp->signal[gen].period);
2140 iowrite32(ts.tv_sec, ®->period_sec);
2141 iowrite32(ts.tv_nsec, ®->period_ns);
2142
2143 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2144 iowrite32(ts.tv_sec, ®->pulse_sec);
2145 iowrite32(ts.tv_nsec, ®->pulse_ns);
2146
2147 iowrite32(bp->signal[gen].polarity, ®->polarity);
2148 iowrite32(0, ®->repeat_count);
2149
2150 iowrite32(0, ®->intr); /* clear interrupt state */
2151 iowrite32(1, ®->intr_mask); /* enable interrupt */
2152 iowrite32(3, ®->enable); /* valid & enable */
2153
2154 bp->signal[gen].running = true;
2155
2156 return 0;
2157 }
2158
2159 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2160 ptp_ocp_ts_irq(int irq, void *priv)
2161 {
2162 struct ptp_ocp_ext_src *ext = priv;
2163 struct ts_reg __iomem *reg = ext->mem;
2164 struct ptp_clock_event ev;
2165 u32 sec, nsec;
2166
2167 if (ext == ext->bp->pps) {
2168 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2169 ev.type = PTP_CLOCK_PPS;
2170 ptp_clock_event(ext->bp->ptp, &ev);
2171 }
2172
2173 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2174 goto out;
2175 }
2176
2177 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2178 sec = ioread32(®->time_sec);
2179 nsec = ioread32(®->time_ns);
2180
2181 ev.type = PTP_CLOCK_EXTTS;
2182 ev.index = ext->info->index;
2183 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2184
2185 ptp_clock_event(ext->bp->ptp, &ev);
2186
2187 out:
2188 iowrite32(1, ®->intr); /* write 1 to ack */
2189
2190 return IRQ_HANDLED;
2191 }
2192
2193 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2194 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2195 {
2196 struct ptp_ocp_ext_src *ext = priv;
2197 struct ts_reg __iomem *reg = ext->mem;
2198 struct ptp_ocp *bp = ext->bp;
2199
2200 if (ext == bp->pps) {
2201 u32 old_map = bp->pps_req_map;
2202
2203 if (enable)
2204 bp->pps_req_map |= req;
2205 else
2206 bp->pps_req_map &= ~req;
2207
2208 /* if no state change, just return */
2209 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2210 return 0;
2211 }
2212
2213 if (enable) {
2214 iowrite32(1, ®->enable);
2215 iowrite32(1, ®->intr_mask);
2216 iowrite32(1, ®->intr);
2217 } else {
2218 iowrite32(0, ®->intr_mask);
2219 iowrite32(0, ®->enable);
2220 }
2221
2222 return 0;
2223 }
2224
2225 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2226 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2227 {
2228 ext->info->enable(ext, ~0, false);
2229 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2230 kfree(ext);
2231 }
2232
2233 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2234 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2235 {
2236 struct pci_dev *pdev = bp->pdev;
2237 struct ptp_ocp_ext_src *ext;
2238 int err;
2239
2240 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2241 if (!ext)
2242 return -ENOMEM;
2243
2244 ext->mem = ptp_ocp_get_mem(bp, r);
2245 if (IS_ERR(ext->mem)) {
2246 err = PTR_ERR(ext->mem);
2247 goto out;
2248 }
2249
2250 ext->bp = bp;
2251 ext->info = r->extra;
2252 ext->irq_vec = r->irq_vec;
2253
2254 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2255 ext, "ocp%d.%s", bp->id, r->name);
2256 if (err) {
2257 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2258 goto out;
2259 }
2260
2261 bp_assign_entry(bp, r, ext);
2262
2263 return 0;
2264
2265 out:
2266 kfree(ext);
2267 return err;
2268 }
2269
2270 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2271 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2272 {
2273 struct pci_dev *pdev = bp->pdev;
2274 struct uart_8250_port uart;
2275
2276 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2277 * the serial port device claim and release the pci resource.
2278 */
2279 memset(&uart, 0, sizeof(uart));
2280 uart.port.dev = &pdev->dev;
2281 uart.port.iotype = UPIO_MEM;
2282 uart.port.regshift = 2;
2283 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2284 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2285 uart.port.uartclk = 50000000;
2286 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2287 uart.port.type = PORT_16550A;
2288
2289 return serial8250_register_8250_port(&uart);
2290 }
2291
2292 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2293 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2294 {
2295 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2296 struct ptp_ocp_serial_port port = {};
2297
2298 port.line = ptp_ocp_serial_line(bp, r);
2299 if (port.line < 0)
2300 return port.line;
2301
2302 if (p)
2303 port.baud = p->baud;
2304
2305 bp_assign_entry(bp, r, port);
2306
2307 return 0;
2308 }
2309
2310 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2311 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2312 {
2313 void __iomem *mem;
2314
2315 mem = ptp_ocp_get_mem(bp, r);
2316 if (IS_ERR(mem))
2317 return PTR_ERR(mem);
2318
2319 bp_assign_entry(bp, r, mem);
2320
2321 return 0;
2322 }
2323
2324 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2325 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2326 {
2327 if (!bp->nmea_out)
2328 return;
2329
2330 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2331 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2332 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2333 }
2334
2335 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2336 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2337 {
2338 u32 val;
2339
2340 iowrite32(0, ®->enable); /* disable */
2341
2342 val = ioread32(®->polarity);
2343 s->polarity = val ? true : false;
2344 s->duty = 50;
2345 }
2346
2347 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2348 ptp_ocp_signal_init(struct ptp_ocp *bp)
2349 {
2350 int i;
2351
2352 for (i = 0; i < 4; i++)
2353 if (bp->signal_out[i])
2354 _ptp_ocp_signal_init(&bp->signal[i],
2355 bp->signal_out[i]->mem);
2356 }
2357
2358 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2359 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2360 {
2361 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2362 kfree(bp->attr_group);
2363 }
2364
2365 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2366 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2367 const struct ocp_attr_group *attr_tbl)
2368 {
2369 int count, i;
2370 int err;
2371
2372 count = 0;
2373 for (i = 0; attr_tbl[i].cap; i++)
2374 if (attr_tbl[i].cap & bp->fw_cap)
2375 count++;
2376
2377 bp->attr_group = kcalloc(count + 1, sizeof(*bp->attr_group),
2378 GFP_KERNEL);
2379 if (!bp->attr_group)
2380 return -ENOMEM;
2381
2382 count = 0;
2383 for (i = 0; attr_tbl[i].cap; i++)
2384 if (attr_tbl[i].cap & bp->fw_cap)
2385 bp->attr_group[count++] = attr_tbl[i].group;
2386
2387 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2388 if (err)
2389 bp->attr_group[0] = NULL;
2390
2391 return err;
2392 }
2393
2394 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2395 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2396 {
2397 u32 ctrl;
2398 bool on;
2399
2400 ctrl = ioread32(reg);
2401 on = ctrl & bit;
2402 if (on ^ enable) {
2403 ctrl &= ~bit;
2404 ctrl |= enable ? bit : 0;
2405 iowrite32(ctrl, reg);
2406 }
2407 }
2408
2409 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2410 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2411 {
2412 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2413 IRIG_M_CTRL_ENABLE, enable);
2414 }
2415
2416 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2417 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2418 {
2419 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2420 IRIG_S_CTRL_ENABLE, enable);
2421 }
2422
2423 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2424 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2425 {
2426 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2427 DCF_M_CTRL_ENABLE, enable);
2428 }
2429
2430 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2431 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2432 {
2433 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2434 DCF_S_CTRL_ENABLE, enable);
2435 }
2436
2437 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2438 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2439 {
2440 ptp_ocp_irig_out(bp, val & 0x00100010);
2441 ptp_ocp_dcf_out(bp, val & 0x00200020);
2442 }
2443
2444 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2445 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2446 {
2447 ptp_ocp_irig_in(bp, val & 0x00100010);
2448 ptp_ocp_dcf_in(bp, val & 0x00200020);
2449 }
2450
2451 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2452 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2453 {
2454 u32 __iomem *gpio;
2455 u32 shift;
2456
2457 if (bp->sma[sma_nr - 1].fixed_fcn)
2458 return (sma_nr - 1) & 1;
2459
2460 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2461 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2462 else
2463 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2464 shift = sma_nr & 1 ? 0 : 16;
2465
2466 return (ioread32(gpio) >> shift) & 0xffff;
2467 }
2468
2469 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2470 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2471 {
2472 u32 reg, mask, shift;
2473 unsigned long flags;
2474 u32 __iomem *gpio;
2475
2476 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2477 shift = sma_nr & 1 ? 0 : 16;
2478
2479 mask = 0xffff << (16 - shift);
2480
2481 spin_lock_irqsave(&bp->lock, flags);
2482
2483 reg = ioread32(gpio);
2484 reg = (reg & mask) | (val << shift);
2485
2486 __handle_signal_outputs(bp, reg);
2487
2488 iowrite32(reg, gpio);
2489
2490 spin_unlock_irqrestore(&bp->lock, flags);
2491
2492 return 0;
2493 }
2494
2495 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2496 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2497 {
2498 u32 reg, mask, shift;
2499 unsigned long flags;
2500 u32 __iomem *gpio;
2501
2502 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2503 shift = sma_nr & 1 ? 0 : 16;
2504
2505 mask = 0xffff << (16 - shift);
2506
2507 spin_lock_irqsave(&bp->lock, flags);
2508
2509 reg = ioread32(gpio);
2510 reg = (reg & mask) | (val << shift);
2511
2512 __handle_signal_inputs(bp, reg);
2513
2514 iowrite32(reg, gpio);
2515
2516 spin_unlock_irqrestore(&bp->lock, flags);
2517
2518 return 0;
2519 }
2520
2521 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2522 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2523 {
2524 struct dpll_pin_properties prop = {
2525 .board_label = NULL,
2526 .type = DPLL_PIN_TYPE_EXT,
2527 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2528 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2529 .freq_supported = ptp_ocp_sma_freq,
2530
2531 };
2532 u32 reg;
2533 int i;
2534
2535 /* defaults */
2536 for (i = 0; i < OCP_SMA_NUM; i++) {
2537 bp->sma[i].default_fcn = i & 1;
2538 bp->sma[i].dpll_prop = prop;
2539 bp->sma[i].dpll_prop.board_label =
2540 bp->ptp_info.pin_config[i].name;
2541 }
2542 bp->sma[0].mode = SMA_MODE_IN;
2543 bp->sma[1].mode = SMA_MODE_IN;
2544 bp->sma[2].mode = SMA_MODE_OUT;
2545 bp->sma[3].mode = SMA_MODE_OUT;
2546 /* If no SMA1 map, the pin functions and directions are fixed. */
2547 if (!bp->sma_map1) {
2548 for (i = 0; i < OCP_SMA_NUM; i++) {
2549 bp->sma[i].fixed_fcn = true;
2550 bp->sma[i].fixed_dir = true;
2551 bp->sma[1].dpll_prop.capabilities &=
2552 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2553 }
2554 return;
2555 }
2556
2557 /* If SMA2 GPIO output map is all 1, it is not present.
2558 * This indicates the firmware has fixed direction SMA pins.
2559 */
2560 reg = ioread32(&bp->sma_map2->gpio2);
2561 if (reg == 0xffffffff) {
2562 for (i = 0; i < OCP_SMA_NUM; i++)
2563 bp->sma[i].fixed_dir = true;
2564 } else {
2565 reg = ioread32(&bp->sma_map1->gpio1);
2566 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2567 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2568
2569 reg = ioread32(&bp->sma_map1->gpio2);
2570 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2571 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2572 }
2573 }
2574
2575 static const struct ocp_sma_op ocp_fb_sma_op = {
2576 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2577 .init = ptp_ocp_sma_fb_init,
2578 .get = ptp_ocp_sma_fb_get,
2579 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2580 .set_output = ptp_ocp_sma_fb_set_output,
2581 };
2582
2583 static int
ptp_ocp_sma_adva_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2584 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2585 {
2586 u32 reg, mask, shift;
2587 unsigned long flags;
2588 u32 __iomem *gpio;
2589
2590 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2591 shift = sma_nr & 1 ? 0 : 16;
2592
2593 mask = 0xffff << (16 - shift);
2594
2595 spin_lock_irqsave(&bp->lock, flags);
2596
2597 reg = ioread32(gpio);
2598 reg = (reg & mask) | (val << shift);
2599
2600 iowrite32(reg, gpio);
2601
2602 spin_unlock_irqrestore(&bp->lock, flags);
2603
2604 return 0;
2605 }
2606
2607 static int
ptp_ocp_sma_adva_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2608 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2609 {
2610 u32 reg, mask, shift;
2611 unsigned long flags;
2612 u32 __iomem *gpio;
2613
2614 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2615 shift = sma_nr & 1 ? 0 : 16;
2616
2617 mask = 0xffff << (16 - shift);
2618
2619 spin_lock_irqsave(&bp->lock, flags);
2620
2621 reg = ioread32(gpio);
2622 reg = (reg & mask) | (val << shift);
2623
2624 iowrite32(reg, gpio);
2625
2626 spin_unlock_irqrestore(&bp->lock, flags);
2627
2628 return 0;
2629 }
2630
2631 static const struct ocp_sma_op ocp_adva_sma_op = {
2632 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2633 .init = ptp_ocp_sma_fb_init,
2634 .get = ptp_ocp_sma_fb_get,
2635 .set_inputs = ptp_ocp_sma_adva_set_inputs,
2636 .set_output = ptp_ocp_sma_adva_set_output,
2637 };
2638
2639 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2640 ptp_ocp_set_pins(struct ptp_ocp *bp)
2641 {
2642 struct ptp_pin_desc *config;
2643 int i;
2644
2645 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2646 if (!config)
2647 return -ENOMEM;
2648
2649 for (i = 0; i < 4; i++) {
2650 sprintf(config[i].name, "sma%d", i + 1);
2651 config[i].index = i;
2652 }
2653
2654 bp->ptp_info.n_pins = 4;
2655 bp->ptp_info.pin_config = config;
2656
2657 return 0;
2658 }
2659
2660 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2661 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2662 {
2663 u64 cap = OCP_CAP_BASIC;
2664 u32 version;
2665
2666 version = ioread32(&bp->image->version);
2667
2668 /* if lower 16 bits are empty, this is the fw loader. */
2669 if ((version & 0xffff) == 0) {
2670 version = version >> 16;
2671 bp->fw_loader = true;
2672 }
2673
2674 bp->fw_tag = version >> 15;
2675 bp->fw_version = version & 0x7fff;
2676
2677 if (bp->fw_tag) {
2678 /* FPGA firmware */
2679 if (version >= 5)
2680 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2681 } else {
2682 /* SOM firmware */
2683 if (version >= 19)
2684 cap |= OCP_CAP_SIGNAL;
2685 if (version >= 20)
2686 cap |= OCP_CAP_FREQ;
2687 }
2688
2689 bp->fw_cap = cap;
2690 }
2691
2692 /* FB specific board initializers; last "resource" registered. */
2693 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2694 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2695 {
2696 int err;
2697
2698 bp->flash_start = 1024 * 4096;
2699 bp->eeprom_map = fb_eeprom_map;
2700 bp->fw_version = ioread32(&bp->image->version);
2701 bp->sma_op = &ocp_fb_sma_op;
2702 bp->signals_nr = 4;
2703 bp->freq_in_nr = 4;
2704
2705 ptp_ocp_fb_set_version(bp);
2706
2707 ptp_ocp_tod_init(bp);
2708 ptp_ocp_nmea_out_init(bp);
2709 ptp_ocp_signal_init(bp);
2710
2711 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2712 if (err)
2713 return err;
2714
2715 err = ptp_ocp_set_pins(bp);
2716 if (err)
2717 return err;
2718 ptp_ocp_sma_init(bp);
2719
2720 return ptp_ocp_init_clock(bp, r->extra);
2721 }
2722
2723 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2724 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2725 {
2726 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2727
2728 if (!allow)
2729 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2730 r->irq_vec, r->name);
2731 return allow;
2732 }
2733
2734 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2735 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2736 {
2737 struct ocp_resource *r, *table;
2738 int err = 0;
2739
2740 table = (struct ocp_resource *)driver_data;
2741 for (r = table; r->setup; r++) {
2742 if (!ptp_ocp_allow_irq(bp, r))
2743 continue;
2744 err = r->setup(bp, r);
2745 if (err) {
2746 dev_err(&bp->pdev->dev,
2747 "Could not register %s: err %d\n",
2748 r->name, err);
2749 break;
2750 }
2751 }
2752 return err;
2753 }
2754
2755 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2756 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2757 {
2758 struct dpll_pin_properties prop = {
2759 .board_label = NULL,
2760 .type = DPLL_PIN_TYPE_EXT,
2761 .capabilities = 0,
2762 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2763 .freq_supported = ptp_ocp_sma_freq,
2764
2765 };
2766 u32 reg;
2767 int i;
2768
2769 /* defaults */
2770 bp->sma[0].mode = SMA_MODE_IN;
2771 bp->sma[1].mode = SMA_MODE_IN;
2772 bp->sma[2].mode = SMA_MODE_OUT;
2773 bp->sma[3].mode = SMA_MODE_OUT;
2774
2775 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2776 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2777 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2778 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2779
2780 for (i = 0; i < OCP_SMA_NUM; i++) {
2781 /* If no SMA map, the pin functions and directions are fixed. */
2782 bp->sma[i].dpll_prop = prop;
2783 bp->sma[i].dpll_prop.board_label =
2784 bp->ptp_info.pin_config[i].name;
2785 if (!bp->art_sma) {
2786 bp->sma[i].fixed_fcn = true;
2787 bp->sma[i].fixed_dir = true;
2788 continue;
2789 }
2790 reg = ioread32(&bp->art_sma->map[i].gpio);
2791
2792 switch (reg & 0xff) {
2793 case 0:
2794 bp->sma[i].fixed_fcn = true;
2795 bp->sma[i].fixed_dir = true;
2796 break;
2797 case 1:
2798 case 8:
2799 bp->sma[i].mode = SMA_MODE_IN;
2800 bp->sma[i].dpll_prop.capabilities =
2801 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2802 break;
2803 default:
2804 bp->sma[i].mode = SMA_MODE_OUT;
2805 bp->sma[i].dpll_prop.capabilities =
2806 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2807 break;
2808 }
2809 }
2810 }
2811
2812 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2813 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2814 {
2815 if (bp->sma[sma_nr - 1].fixed_fcn)
2816 return bp->sma[sma_nr - 1].default_fcn;
2817
2818 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2819 }
2820
2821 /* note: store 0 is considered invalid. */
2822 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2823 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2824 {
2825 unsigned long flags;
2826 u32 __iomem *gpio;
2827 int err = 0;
2828 u32 reg;
2829
2830 val &= SMA_SELECT_MASK;
2831 if (hweight32(val) > 1)
2832 return -EINVAL;
2833
2834 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2835
2836 spin_lock_irqsave(&bp->lock, flags);
2837 reg = ioread32(gpio);
2838 if (((reg >> 16) & val) == 0) {
2839 err = -EOPNOTSUPP;
2840 } else {
2841 reg = (reg & 0xff00) | (val & 0xff);
2842 iowrite32(reg, gpio);
2843 }
2844 spin_unlock_irqrestore(&bp->lock, flags);
2845
2846 return err;
2847 }
2848
2849 static const struct ocp_sma_op ocp_art_sma_op = {
2850 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2851 .init = ptp_ocp_art_sma_init,
2852 .get = ptp_ocp_art_sma_get,
2853 .set_inputs = ptp_ocp_art_sma_set,
2854 .set_output = ptp_ocp_art_sma_set,
2855 };
2856
2857 /* ART specific board initializers; last "resource" registered. */
2858 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2859 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2860 {
2861 int err;
2862
2863 bp->flash_start = 0x1000000;
2864 bp->eeprom_map = art_eeprom_map;
2865 bp->fw_cap = OCP_CAP_BASIC;
2866 bp->fw_version = ioread32(&bp->reg->version);
2867 bp->fw_tag = 2;
2868 bp->sma_op = &ocp_art_sma_op;
2869 bp->signals_nr = 4;
2870 bp->freq_in_nr = 4;
2871
2872 /* Enable MAC serial port during initialisation */
2873 iowrite32(1, &bp->board_config->mro50_serial_activate);
2874
2875 err = ptp_ocp_set_pins(bp);
2876 if (err)
2877 return err;
2878 ptp_ocp_sma_init(bp);
2879
2880 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2881 if (err)
2882 return err;
2883
2884 return ptp_ocp_init_clock(bp, r->extra);
2885 }
2886
2887 /* ADVA specific board initializers; last "resource" registered. */
2888 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2889 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2890 {
2891 int err;
2892 u32 version;
2893
2894 bp->flash_start = 0xA00000;
2895 bp->eeprom_map = fb_eeprom_map;
2896 bp->sma_op = &ocp_adva_sma_op;
2897 bp->signals_nr = 2;
2898 bp->freq_in_nr = 2;
2899
2900 version = ioread32(&bp->image->version);
2901 /* if lower 16 bits are empty, this is the fw loader. */
2902 if ((version & 0xffff) == 0) {
2903 version = version >> 16;
2904 bp->fw_loader = true;
2905 }
2906 bp->fw_tag = 3;
2907 bp->fw_version = version & 0xffff;
2908 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2909
2910 ptp_ocp_tod_init(bp);
2911 ptp_ocp_nmea_out_init(bp);
2912 ptp_ocp_signal_init(bp);
2913
2914 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2915 if (err)
2916 return err;
2917
2918 err = ptp_ocp_set_pins(bp);
2919 if (err)
2920 return err;
2921 ptp_ocp_sma_init(bp);
2922
2923 return ptp_ocp_init_clock(bp, r->extra);
2924 }
2925
2926 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2927 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2928 int def_val)
2929 {
2930 const char *name;
2931 ssize_t count;
2932
2933 count = sysfs_emit(buf, "OUT: ");
2934 name = ptp_ocp_select_name_from_val(tbl, val);
2935 if (!name)
2936 name = ptp_ocp_select_name_from_val(tbl, def_val);
2937 count += sysfs_emit_at(buf, count, "%s\n", name);
2938 return count;
2939 }
2940
2941 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2942 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2943 int def_val)
2944 {
2945 const char *name;
2946 ssize_t count;
2947 int i;
2948
2949 count = sysfs_emit(buf, "IN: ");
2950 for (i = 0; tbl[i].name; i++) {
2951 if (val & tbl[i].value) {
2952 name = tbl[i].name;
2953 count += sysfs_emit_at(buf, count, "%s ", name);
2954 }
2955 }
2956 if (!val && def_val >= 0) {
2957 name = ptp_ocp_select_name_from_val(tbl, def_val);
2958 count += sysfs_emit_at(buf, count, "%s ", name);
2959 }
2960 if (count)
2961 count--;
2962 count += sysfs_emit_at(buf, count, "\n");
2963 return count;
2964 }
2965
2966 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2967 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2968 enum ptp_ocp_sma_mode *mode)
2969 {
2970 int idx, count, dir;
2971 char **argv;
2972 int ret;
2973
2974 argv = argv_split(GFP_KERNEL, buf, &count);
2975 if (!argv)
2976 return -ENOMEM;
2977
2978 ret = -EINVAL;
2979 if (!count)
2980 goto out;
2981
2982 idx = 0;
2983 dir = *mode == SMA_MODE_IN ? 0 : 1;
2984 if (!strcasecmp("IN:", argv[0])) {
2985 dir = 0;
2986 idx++;
2987 }
2988 if (!strcasecmp("OUT:", argv[0])) {
2989 dir = 1;
2990 idx++;
2991 }
2992 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2993
2994 ret = 0;
2995 for (; idx < count; idx++)
2996 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2997 if (ret < 0)
2998 ret = -EINVAL;
2999
3000 out:
3001 argv_free(argv);
3002 return ret;
3003 }
3004
3005 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)3006 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3007 int default_in_val, int default_out_val)
3008 {
3009 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3010 const struct ocp_selector * const *tbl;
3011 u32 val;
3012
3013 tbl = bp->sma_op->tbl;
3014 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3015
3016 if (sma->mode == SMA_MODE_IN) {
3017 if (sma->disabled)
3018 val = SMA_DISABLE;
3019 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3020 }
3021
3022 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3023 }
3024
3025 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)3026 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3027 {
3028 struct ptp_ocp *bp = dev_get_drvdata(dev);
3029
3030 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3031 }
3032
3033 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)3034 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3035 {
3036 struct ptp_ocp *bp = dev_get_drvdata(dev);
3037
3038 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3039 }
3040
3041 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)3042 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3043 {
3044 struct ptp_ocp *bp = dev_get_drvdata(dev);
3045
3046 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3047 }
3048
3049 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)3050 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3051 {
3052 struct ptp_ocp *bp = dev_get_drvdata(dev);
3053
3054 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3055 }
3056
3057 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3058 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3059 {
3060 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3061
3062 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3063 return -EOPNOTSUPP;
3064
3065 if (sma->fixed_fcn) {
3066 if (val != sma->default_fcn)
3067 return -EOPNOTSUPP;
3068 return 0;
3069 }
3070
3071 sma->disabled = !!(val & SMA_DISABLE);
3072
3073 if (mode != sma->mode) {
3074 if (mode == SMA_MODE_IN)
3075 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3076 else
3077 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3078 sma->mode = mode;
3079 }
3080
3081 if (!sma->fixed_dir)
3082 val |= SMA_ENABLE; /* add enable bit */
3083
3084 if (sma->disabled)
3085 val = 0;
3086
3087 if (mode == SMA_MODE_IN)
3088 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3089 else
3090 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3091
3092 return val;
3093 }
3094
3095 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3096 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3097 {
3098 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3099 enum ptp_ocp_sma_mode mode;
3100 int val;
3101
3102 mode = sma->mode;
3103 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3104 if (val < 0)
3105 return val;
3106 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3107 }
3108
3109 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3110 sma1_store(struct device *dev, struct device_attribute *attr,
3111 const char *buf, size_t count)
3112 {
3113 struct ptp_ocp *bp = dev_get_drvdata(dev);
3114 int err;
3115
3116 err = ptp_ocp_sma_store(bp, buf, 1);
3117 return err ? err : count;
3118 }
3119
3120 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3121 sma2_store(struct device *dev, struct device_attribute *attr,
3122 const char *buf, size_t count)
3123 {
3124 struct ptp_ocp *bp = dev_get_drvdata(dev);
3125 int err;
3126
3127 err = ptp_ocp_sma_store(bp, buf, 2);
3128 return err ? err : count;
3129 }
3130
3131 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3132 sma3_store(struct device *dev, struct device_attribute *attr,
3133 const char *buf, size_t count)
3134 {
3135 struct ptp_ocp *bp = dev_get_drvdata(dev);
3136 int err;
3137
3138 err = ptp_ocp_sma_store(bp, buf, 3);
3139 return err ? err : count;
3140 }
3141
3142 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3143 sma4_store(struct device *dev, struct device_attribute *attr,
3144 const char *buf, size_t count)
3145 {
3146 struct ptp_ocp *bp = dev_get_drvdata(dev);
3147 int err;
3148
3149 err = ptp_ocp_sma_store(bp, buf, 4);
3150 return err ? err : count;
3151 }
3152 static DEVICE_ATTR_RW(sma1);
3153 static DEVICE_ATTR_RW(sma2);
3154 static DEVICE_ATTR_RW(sma3);
3155 static DEVICE_ATTR_RW(sma4);
3156
3157 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3158 available_sma_inputs_show(struct device *dev,
3159 struct device_attribute *attr, char *buf)
3160 {
3161 struct ptp_ocp *bp = dev_get_drvdata(dev);
3162
3163 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3164 }
3165 static DEVICE_ATTR_RO(available_sma_inputs);
3166
3167 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3168 available_sma_outputs_show(struct device *dev,
3169 struct device_attribute *attr, char *buf)
3170 {
3171 struct ptp_ocp *bp = dev_get_drvdata(dev);
3172
3173 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3174 }
3175 static DEVICE_ATTR_RO(available_sma_outputs);
3176
3177 #define EXT_ATTR_RO(_group, _name, _val) \
3178 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3179 { __ATTR_RO(_name), (void *)_val }
3180 #define EXT_ATTR_RW(_group, _name, _val) \
3181 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3182 { __ATTR_RW(_name), (void *)_val }
3183 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3184
3185 /* period [duty [phase [polarity]]] */
3186 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3187 signal_store(struct device *dev, struct device_attribute *attr,
3188 const char *buf, size_t count)
3189 {
3190 struct dev_ext_attribute *ea = to_ext_attr(attr);
3191 struct ptp_ocp *bp = dev_get_drvdata(dev);
3192 struct ptp_ocp_signal s = { };
3193 int gen = (uintptr_t)ea->var;
3194 int argc, err;
3195 char **argv;
3196
3197 argv = argv_split(GFP_KERNEL, buf, &argc);
3198 if (!argv)
3199 return -ENOMEM;
3200
3201 err = -EINVAL;
3202 s.duty = bp->signal[gen].duty;
3203 s.phase = bp->signal[gen].phase;
3204 s.period = bp->signal[gen].period;
3205 s.polarity = bp->signal[gen].polarity;
3206
3207 switch (argc) {
3208 case 4:
3209 argc--;
3210 err = kstrtobool(argv[argc], &s.polarity);
3211 if (err)
3212 goto out;
3213 fallthrough;
3214 case 3:
3215 argc--;
3216 err = kstrtou64(argv[argc], 0, &s.phase);
3217 if (err)
3218 goto out;
3219 fallthrough;
3220 case 2:
3221 argc--;
3222 err = kstrtoint(argv[argc], 0, &s.duty);
3223 if (err)
3224 goto out;
3225 fallthrough;
3226 case 1:
3227 argc--;
3228 err = kstrtou64(argv[argc], 0, &s.period);
3229 if (err)
3230 goto out;
3231 break;
3232 default:
3233 goto out;
3234 }
3235
3236 err = ptp_ocp_signal_set(bp, gen, &s);
3237 if (err)
3238 goto out;
3239
3240 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3241
3242 out:
3243 argv_free(argv);
3244 return err ? err : count;
3245 }
3246
3247 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3248 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3249 {
3250 struct dev_ext_attribute *ea = to_ext_attr(attr);
3251 struct ptp_ocp *bp = dev_get_drvdata(dev);
3252 struct ptp_ocp_signal *signal;
3253 struct timespec64 ts;
3254 ssize_t count;
3255 int i;
3256
3257 i = (uintptr_t)ea->var;
3258 signal = &bp->signal[i];
3259
3260 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3261 signal->duty, signal->phase, signal->polarity);
3262
3263 ts = ktime_to_timespec64(signal->start);
3264 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3265
3266 return count;
3267 }
3268 static EXT_ATTR_RW(signal, signal, 0);
3269 static EXT_ATTR_RW(signal, signal, 1);
3270 static EXT_ATTR_RW(signal, signal, 2);
3271 static EXT_ATTR_RW(signal, signal, 3);
3272
3273 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3274 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3275 {
3276 struct dev_ext_attribute *ea = to_ext_attr(attr);
3277 struct ptp_ocp *bp = dev_get_drvdata(dev);
3278 int i = (uintptr_t)ea->var;
3279
3280 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3281 }
3282 static EXT_ATTR_RO(signal, duty, 0);
3283 static EXT_ATTR_RO(signal, duty, 1);
3284 static EXT_ATTR_RO(signal, duty, 2);
3285 static EXT_ATTR_RO(signal, duty, 3);
3286
3287 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3288 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3289 {
3290 struct dev_ext_attribute *ea = to_ext_attr(attr);
3291 struct ptp_ocp *bp = dev_get_drvdata(dev);
3292 int i = (uintptr_t)ea->var;
3293
3294 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3295 }
3296 static EXT_ATTR_RO(signal, period, 0);
3297 static EXT_ATTR_RO(signal, period, 1);
3298 static EXT_ATTR_RO(signal, period, 2);
3299 static EXT_ATTR_RO(signal, period, 3);
3300
3301 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3302 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3303 {
3304 struct dev_ext_attribute *ea = to_ext_attr(attr);
3305 struct ptp_ocp *bp = dev_get_drvdata(dev);
3306 int i = (uintptr_t)ea->var;
3307
3308 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3309 }
3310 static EXT_ATTR_RO(signal, phase, 0);
3311 static EXT_ATTR_RO(signal, phase, 1);
3312 static EXT_ATTR_RO(signal, phase, 2);
3313 static EXT_ATTR_RO(signal, phase, 3);
3314
3315 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3316 polarity_show(struct device *dev, struct device_attribute *attr,
3317 char *buf)
3318 {
3319 struct dev_ext_attribute *ea = to_ext_attr(attr);
3320 struct ptp_ocp *bp = dev_get_drvdata(dev);
3321 int i = (uintptr_t)ea->var;
3322
3323 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3324 }
3325 static EXT_ATTR_RO(signal, polarity, 0);
3326 static EXT_ATTR_RO(signal, polarity, 1);
3327 static EXT_ATTR_RO(signal, polarity, 2);
3328 static EXT_ATTR_RO(signal, polarity, 3);
3329
3330 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3331 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3332 {
3333 struct dev_ext_attribute *ea = to_ext_attr(attr);
3334 struct ptp_ocp *bp = dev_get_drvdata(dev);
3335 int i = (uintptr_t)ea->var;
3336
3337 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3338 }
3339 static EXT_ATTR_RO(signal, running, 0);
3340 static EXT_ATTR_RO(signal, running, 1);
3341 static EXT_ATTR_RO(signal, running, 2);
3342 static EXT_ATTR_RO(signal, running, 3);
3343
3344 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3345 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3346 {
3347 struct dev_ext_attribute *ea = to_ext_attr(attr);
3348 struct ptp_ocp *bp = dev_get_drvdata(dev);
3349 int i = (uintptr_t)ea->var;
3350 struct timespec64 ts;
3351
3352 ts = ktime_to_timespec64(bp->signal[i].start);
3353 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3354 }
3355 static EXT_ATTR_RO(signal, start, 0);
3356 static EXT_ATTR_RO(signal, start, 1);
3357 static EXT_ATTR_RO(signal, start, 2);
3358 static EXT_ATTR_RO(signal, start, 3);
3359
3360 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3361 seconds_store(struct device *dev, struct device_attribute *attr,
3362 const char *buf, size_t count)
3363 {
3364 struct dev_ext_attribute *ea = to_ext_attr(attr);
3365 struct ptp_ocp *bp = dev_get_drvdata(dev);
3366 int idx = (uintptr_t)ea->var;
3367 u32 val;
3368 int err;
3369
3370 err = kstrtou32(buf, 0, &val);
3371 if (err)
3372 return err;
3373 if (val > 0xff)
3374 return -EINVAL;
3375
3376 if (val)
3377 val = (val << 8) | 0x1;
3378
3379 iowrite32(val, &bp->freq_in[idx]->ctrl);
3380
3381 return count;
3382 }
3383
3384 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3385 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3386 {
3387 struct dev_ext_attribute *ea = to_ext_attr(attr);
3388 struct ptp_ocp *bp = dev_get_drvdata(dev);
3389 int idx = (uintptr_t)ea->var;
3390 u32 val;
3391
3392 val = ioread32(&bp->freq_in[idx]->ctrl);
3393 if (val & 1)
3394 val = (val >> 8) & 0xff;
3395 else
3396 val = 0;
3397
3398 return sysfs_emit(buf, "%u\n", val);
3399 }
3400 static EXT_ATTR_RW(freq, seconds, 0);
3401 static EXT_ATTR_RW(freq, seconds, 1);
3402 static EXT_ATTR_RW(freq, seconds, 2);
3403 static EXT_ATTR_RW(freq, seconds, 3);
3404
3405 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3406 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3407 {
3408 struct dev_ext_attribute *ea = to_ext_attr(attr);
3409 struct ptp_ocp *bp = dev_get_drvdata(dev);
3410 int idx = (uintptr_t)ea->var;
3411 u32 val;
3412
3413 val = ioread32(&bp->freq_in[idx]->status);
3414 if (val & FREQ_STATUS_ERROR)
3415 return sysfs_emit(buf, "error\n");
3416 if (val & FREQ_STATUS_OVERRUN)
3417 return sysfs_emit(buf, "overrun\n");
3418 if (val & FREQ_STATUS_VALID)
3419 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3420 return 0;
3421 }
3422 static EXT_ATTR_RO(freq, frequency, 0);
3423 static EXT_ATTR_RO(freq, frequency, 1);
3424 static EXT_ATTR_RO(freq, frequency, 2);
3425 static EXT_ATTR_RO(freq, frequency, 3);
3426
3427 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3428 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3429 {
3430 struct dev_ext_attribute *ea = to_ext_attr(attr);
3431 struct ptp_ocp *bp = dev_get_drvdata(dev);
3432
3433 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3434 }
3435
3436 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3437 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3438 {
3439 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3440 struct ptp_ocp_serial_port *port;
3441 struct device_attribute *dattr;
3442 struct dev_ext_attribute *ea;
3443
3444 if (strncmp(attr->name, "tty", 3))
3445 return attr->mode;
3446
3447 dattr = container_of(attr, struct device_attribute, attr);
3448 ea = container_of(dattr, struct dev_ext_attribute, attr);
3449 port = &bp->port[(uintptr_t)ea->var];
3450 return port->line == -1 ? 0 : 0444;
3451 }
3452
3453 #define EXT_TTY_ATTR_RO(_name, _val) \
3454 struct dev_ext_attribute dev_attr_tty##_name = \
3455 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3456
3457 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3458 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3459 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3460 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3461 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3462 &dev_attr_ttyGNSS.attr.attr,
3463 &dev_attr_ttyGNSS2.attr.attr,
3464 &dev_attr_ttyMAC.attr.attr,
3465 &dev_attr_ttyNMEA.attr.attr,
3466 NULL,
3467 };
3468
3469 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3470 .name = "tty",
3471 .attrs = ptp_ocp_timecard_tty_attrs,
3472 .is_visible = ptp_ocp_timecard_tty_is_visible,
3473 };
3474
3475 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3476 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3477 {
3478 struct ptp_ocp *bp = dev_get_drvdata(dev);
3479
3480 if (!bp->has_eeprom_data)
3481 ptp_ocp_read_eeprom(bp);
3482
3483 return sysfs_emit(buf, "%pM\n", bp->serial);
3484 }
3485 static DEVICE_ATTR_RO(serialnum);
3486
3487 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3488 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3489 {
3490 struct ptp_ocp *bp = dev_get_drvdata(dev);
3491 ssize_t ret;
3492
3493 if (bp->gnss_lost)
3494 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3495 else
3496 ret = sysfs_emit(buf, "SYNC\n");
3497
3498 return ret;
3499 }
3500 static DEVICE_ATTR_RO(gnss_sync);
3501
3502 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3503 utc_tai_offset_show(struct device *dev,
3504 struct device_attribute *attr, char *buf)
3505 {
3506 struct ptp_ocp *bp = dev_get_drvdata(dev);
3507
3508 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3509 }
3510
3511 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3512 utc_tai_offset_store(struct device *dev,
3513 struct device_attribute *attr,
3514 const char *buf, size_t count)
3515 {
3516 struct ptp_ocp *bp = dev_get_drvdata(dev);
3517 int err;
3518 u32 val;
3519
3520 err = kstrtou32(buf, 0, &val);
3521 if (err)
3522 return err;
3523
3524 ptp_ocp_utc_distribute(bp, val);
3525
3526 return count;
3527 }
3528 static DEVICE_ATTR_RW(utc_tai_offset);
3529
3530 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3531 ts_window_adjust_show(struct device *dev,
3532 struct device_attribute *attr, char *buf)
3533 {
3534 struct ptp_ocp *bp = dev_get_drvdata(dev);
3535
3536 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3537 }
3538
3539 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3540 ts_window_adjust_store(struct device *dev,
3541 struct device_attribute *attr,
3542 const char *buf, size_t count)
3543 {
3544 struct ptp_ocp *bp = dev_get_drvdata(dev);
3545 int err;
3546 u32 val;
3547
3548 err = kstrtou32(buf, 0, &val);
3549 if (err)
3550 return err;
3551
3552 bp->ts_window_adjust = val;
3553
3554 return count;
3555 }
3556 static DEVICE_ATTR_RW(ts_window_adjust);
3557
3558 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3559 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3560 {
3561 struct ptp_ocp *bp = dev_get_drvdata(dev);
3562 u32 val;
3563
3564 val = ioread32(&bp->irig_out->ctrl);
3565 val = (val >> 16) & 0x07;
3566 return sysfs_emit(buf, "%d\n", val);
3567 }
3568
3569 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3570 irig_b_mode_store(struct device *dev,
3571 struct device_attribute *attr,
3572 const char *buf, size_t count)
3573 {
3574 struct ptp_ocp *bp = dev_get_drvdata(dev);
3575 unsigned long flags;
3576 int err;
3577 u32 reg;
3578 u8 val;
3579
3580 err = kstrtou8(buf, 0, &val);
3581 if (err)
3582 return err;
3583 if (val > 7)
3584 return -EINVAL;
3585
3586 reg = ((val & 0x7) << 16);
3587
3588 spin_lock_irqsave(&bp->lock, flags);
3589 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3590 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3591 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3592 spin_unlock_irqrestore(&bp->lock, flags);
3593
3594 return count;
3595 }
3596 static DEVICE_ATTR_RW(irig_b_mode);
3597
3598 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3599 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3600 {
3601 struct ptp_ocp *bp = dev_get_drvdata(dev);
3602 const char *p;
3603 u32 select;
3604
3605 select = ioread32(&bp->reg->select);
3606 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3607
3608 return sysfs_emit(buf, "%s\n", p);
3609 }
3610
3611 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3612 clock_source_store(struct device *dev, struct device_attribute *attr,
3613 const char *buf, size_t count)
3614 {
3615 struct ptp_ocp *bp = dev_get_drvdata(dev);
3616 unsigned long flags;
3617 int val;
3618
3619 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3620 if (val < 0)
3621 return val;
3622
3623 spin_lock_irqsave(&bp->lock, flags);
3624 iowrite32(val, &bp->reg->select);
3625 spin_unlock_irqrestore(&bp->lock, flags);
3626
3627 return count;
3628 }
3629 static DEVICE_ATTR_RW(clock_source);
3630
3631 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3632 available_clock_sources_show(struct device *dev,
3633 struct device_attribute *attr, char *buf)
3634 {
3635 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3636 }
3637 static DEVICE_ATTR_RO(available_clock_sources);
3638
3639 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3640 clock_status_drift_show(struct device *dev,
3641 struct device_attribute *attr, char *buf)
3642 {
3643 struct ptp_ocp *bp = dev_get_drvdata(dev);
3644 u32 val;
3645 int res;
3646
3647 val = ioread32(&bp->reg->status_drift);
3648 res = (val & ~INT_MAX) ? -1 : 1;
3649 res *= (val & INT_MAX);
3650 return sysfs_emit(buf, "%d\n", res);
3651 }
3652 static DEVICE_ATTR_RO(clock_status_drift);
3653
3654 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3655 clock_status_offset_show(struct device *dev,
3656 struct device_attribute *attr, char *buf)
3657 {
3658 struct ptp_ocp *bp = dev_get_drvdata(dev);
3659 u32 val;
3660 int res;
3661
3662 val = ioread32(&bp->reg->status_offset);
3663 res = (val & ~INT_MAX) ? -1 : 1;
3664 res *= (val & INT_MAX);
3665 return sysfs_emit(buf, "%d\n", res);
3666 }
3667 static DEVICE_ATTR_RO(clock_status_offset);
3668
3669 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3670 tod_correction_show(struct device *dev,
3671 struct device_attribute *attr, char *buf)
3672 {
3673 struct ptp_ocp *bp = dev_get_drvdata(dev);
3674 u32 val;
3675 int res;
3676
3677 val = ioread32(&bp->tod->adj_sec);
3678 res = (val & ~INT_MAX) ? -1 : 1;
3679 res *= (val & INT_MAX);
3680 return sysfs_emit(buf, "%d\n", res);
3681 }
3682
3683 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3684 tod_correction_store(struct device *dev, struct device_attribute *attr,
3685 const char *buf, size_t count)
3686 {
3687 struct ptp_ocp *bp = dev_get_drvdata(dev);
3688 unsigned long flags;
3689 int err, res;
3690 u32 val = 0;
3691
3692 err = kstrtos32(buf, 0, &res);
3693 if (err)
3694 return err;
3695 if (res < 0) {
3696 res *= -1;
3697 val |= BIT(31);
3698 }
3699 val |= res;
3700
3701 spin_lock_irqsave(&bp->lock, flags);
3702 iowrite32(val, &bp->tod->adj_sec);
3703 spin_unlock_irqrestore(&bp->lock, flags);
3704
3705 return count;
3706 }
3707 static DEVICE_ATTR_RW(tod_correction);
3708
3709 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3710 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3711 &dev_attr_signal##_nr##_signal.attr.attr, \
3712 &dev_attr_signal##_nr##_duty.attr.attr, \
3713 &dev_attr_signal##_nr##_phase.attr.attr, \
3714 &dev_attr_signal##_nr##_period.attr.attr, \
3715 &dev_attr_signal##_nr##_polarity.attr.attr, \
3716 &dev_attr_signal##_nr##_running.attr.attr, \
3717 &dev_attr_signal##_nr##_start.attr.attr, \
3718 NULL, \
3719 }
3720
3721 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3722 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3723 static const struct attribute_group \
3724 fb_timecard_signal##_nr##_group = { \
3725 .name = #_name, \
3726 .attrs = fb_timecard_signal##_nr##_attrs, \
3727 }
3728
3729 DEVICE_SIGNAL_GROUP(gen1, 0);
3730 DEVICE_SIGNAL_GROUP(gen2, 1);
3731 DEVICE_SIGNAL_GROUP(gen3, 2);
3732 DEVICE_SIGNAL_GROUP(gen4, 3);
3733
3734 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3735 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3736 &dev_attr_freq##_nr##_seconds.attr.attr, \
3737 &dev_attr_freq##_nr##_frequency.attr.attr, \
3738 NULL, \
3739 }
3740
3741 #define DEVICE_FREQ_GROUP(_name, _nr) \
3742 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3743 static const struct attribute_group \
3744 fb_timecard_freq##_nr##_group = { \
3745 .name = #_name, \
3746 .attrs = fb_timecard_freq##_nr##_attrs, \
3747 }
3748
3749 DEVICE_FREQ_GROUP(freq1, 0);
3750 DEVICE_FREQ_GROUP(freq2, 1);
3751 DEVICE_FREQ_GROUP(freq3, 2);
3752 DEVICE_FREQ_GROUP(freq4, 3);
3753
3754 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3755 disciplining_config_read(struct file *filp, struct kobject *kobj,
3756 const struct bin_attribute *bin_attr, char *buf,
3757 loff_t off, size_t count)
3758 {
3759 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3760 size_t size = OCP_ART_CONFIG_SIZE;
3761 struct nvmem_device *nvmem;
3762 ssize_t err;
3763
3764 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3765 if (IS_ERR(nvmem))
3766 return PTR_ERR(nvmem);
3767
3768 if (off > size) {
3769 err = 0;
3770 goto out;
3771 }
3772
3773 if (off + count > size)
3774 count = size - off;
3775
3776 // the configuration is in the very beginning of the EEPROM
3777 err = nvmem_device_read(nvmem, off, count, buf);
3778 if (err != count) {
3779 err = -EFAULT;
3780 goto out;
3781 }
3782
3783 out:
3784 ptp_ocp_nvmem_device_put(&nvmem);
3785
3786 return err;
3787 }
3788
3789 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3790 disciplining_config_write(struct file *filp, struct kobject *kobj,
3791 const struct bin_attribute *bin_attr, char *buf,
3792 loff_t off, size_t count)
3793 {
3794 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3795 struct nvmem_device *nvmem;
3796 ssize_t err;
3797
3798 /* Allow write of the whole area only */
3799 if (off || count != OCP_ART_CONFIG_SIZE)
3800 return -EFAULT;
3801
3802 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3803 if (IS_ERR(nvmem))
3804 return PTR_ERR(nvmem);
3805
3806 err = nvmem_device_write(nvmem, 0x00, count, buf);
3807 if (err != count)
3808 err = -EFAULT;
3809
3810 ptp_ocp_nvmem_device_put(&nvmem);
3811
3812 return err;
3813 }
3814 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3815
3816 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3817 temperature_table_read(struct file *filp, struct kobject *kobj,
3818 const struct bin_attribute *bin_attr, char *buf,
3819 loff_t off, size_t count)
3820 {
3821 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3822 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3823 struct nvmem_device *nvmem;
3824 ssize_t err;
3825
3826 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3827 if (IS_ERR(nvmem))
3828 return PTR_ERR(nvmem);
3829
3830 if (off > size) {
3831 err = 0;
3832 goto out;
3833 }
3834
3835 if (off + count > size)
3836 count = size - off;
3837
3838 // the configuration is in the very beginning of the EEPROM
3839 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3840 if (err != count) {
3841 err = -EFAULT;
3842 goto out;
3843 }
3844
3845 out:
3846 ptp_ocp_nvmem_device_put(&nvmem);
3847
3848 return err;
3849 }
3850
3851 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3852 temperature_table_write(struct file *filp, struct kobject *kobj,
3853 const struct bin_attribute *bin_attr, char *buf,
3854 loff_t off, size_t count)
3855 {
3856 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3857 struct nvmem_device *nvmem;
3858 ssize_t err;
3859
3860 /* Allow write of the whole area only */
3861 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3862 return -EFAULT;
3863
3864 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3865 if (IS_ERR(nvmem))
3866 return PTR_ERR(nvmem);
3867
3868 err = nvmem_device_write(nvmem, 0x90, count, buf);
3869 if (err != count)
3870 err = -EFAULT;
3871
3872 ptp_ocp_nvmem_device_put(&nvmem);
3873
3874 return err;
3875 }
3876 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3877
3878 static struct attribute *fb_timecard_attrs[] = {
3879 &dev_attr_serialnum.attr,
3880 &dev_attr_gnss_sync.attr,
3881 &dev_attr_clock_source.attr,
3882 &dev_attr_available_clock_sources.attr,
3883 &dev_attr_sma1.attr,
3884 &dev_attr_sma2.attr,
3885 &dev_attr_sma3.attr,
3886 &dev_attr_sma4.attr,
3887 &dev_attr_available_sma_inputs.attr,
3888 &dev_attr_available_sma_outputs.attr,
3889 &dev_attr_clock_status_drift.attr,
3890 &dev_attr_clock_status_offset.attr,
3891 &dev_attr_irig_b_mode.attr,
3892 &dev_attr_utc_tai_offset.attr,
3893 &dev_attr_ts_window_adjust.attr,
3894 &dev_attr_tod_correction.attr,
3895 NULL,
3896 };
3897
3898 static const struct attribute_group fb_timecard_group = {
3899 .attrs = fb_timecard_attrs,
3900 };
3901
3902 static const struct ocp_attr_group fb_timecard_groups[] = {
3903 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3904 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3905 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3906 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3907 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3908 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3909 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3910 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3911 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3912 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3913 { },
3914 };
3915
3916 static struct attribute *art_timecard_attrs[] = {
3917 &dev_attr_serialnum.attr,
3918 &dev_attr_clock_source.attr,
3919 &dev_attr_available_clock_sources.attr,
3920 &dev_attr_utc_tai_offset.attr,
3921 &dev_attr_ts_window_adjust.attr,
3922 &dev_attr_sma1.attr,
3923 &dev_attr_sma2.attr,
3924 &dev_attr_sma3.attr,
3925 &dev_attr_sma4.attr,
3926 &dev_attr_available_sma_inputs.attr,
3927 &dev_attr_available_sma_outputs.attr,
3928 NULL,
3929 };
3930
3931 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
3932 &bin_attr_disciplining_config,
3933 &bin_attr_temperature_table,
3934 NULL,
3935 };
3936
3937 static const struct attribute_group art_timecard_group = {
3938 .attrs = art_timecard_attrs,
3939 .bin_attrs = bin_art_timecard_attrs,
3940 };
3941
3942 static const struct ocp_attr_group art_timecard_groups[] = {
3943 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3944 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3945 { },
3946 };
3947
3948 static struct attribute *adva_timecard_attrs[] = {
3949 &dev_attr_serialnum.attr,
3950 &dev_attr_gnss_sync.attr,
3951 &dev_attr_clock_source.attr,
3952 &dev_attr_available_clock_sources.attr,
3953 &dev_attr_sma1.attr,
3954 &dev_attr_sma2.attr,
3955 &dev_attr_sma3.attr,
3956 &dev_attr_sma4.attr,
3957 &dev_attr_available_sma_inputs.attr,
3958 &dev_attr_available_sma_outputs.attr,
3959 &dev_attr_clock_status_drift.attr,
3960 &dev_attr_clock_status_offset.attr,
3961 &dev_attr_ts_window_adjust.attr,
3962 &dev_attr_tod_correction.attr,
3963 NULL,
3964 };
3965
3966 static const struct attribute_group adva_timecard_group = {
3967 .attrs = adva_timecard_attrs,
3968 };
3969
3970 static const struct ocp_attr_group adva_timecard_groups[] = {
3971 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3972 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3973 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3974 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3975 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3976 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3977 { },
3978 };
3979
3980 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3981 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3982 const char *def)
3983 {
3984 int i;
3985
3986 for (i = 0; i < 4; i++) {
3987 if (bp->sma[i].mode != SMA_MODE_IN)
3988 continue;
3989 if (map[i][0] & (1 << bit)) {
3990 sprintf(buf, "sma%d", i + 1);
3991 return;
3992 }
3993 }
3994 if (!def)
3995 def = "----";
3996 strcpy(buf, def);
3997 }
3998
3999 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)4000 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
4001 {
4002 char *ans = buf;
4003 int i;
4004
4005 strcpy(ans, "----");
4006 for (i = 0; i < 4; i++) {
4007 if (bp->sma[i].mode != SMA_MODE_OUT)
4008 continue;
4009 if (map[i][1] & (1 << bit))
4010 ans += sprintf(ans, "sma%d ", i + 1);
4011 }
4012 }
4013
4014 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)4015 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
4016 {
4017 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
4018 struct ptp_ocp_signal *signal = &bp->signal[nr];
4019 char label[16];
4020 bool on;
4021 u32 val;
4022
4023 on = signal->running;
4024 sprintf(label, "GEN%d", nr + 1);
4025 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
4026 label, on ? " ON" : "OFF",
4027 signal->period, signal->duty, signal->phase,
4028 signal->polarity);
4029
4030 val = ioread32(®->enable);
4031 seq_printf(s, " [%x", val);
4032 val = ioread32(®->status);
4033 seq_printf(s, " %x]", val);
4034
4035 seq_printf(s, " start:%llu\n", signal->start);
4036 }
4037
4038 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)4039 _frequency_summary_show(struct seq_file *s, int nr,
4040 struct frequency_reg __iomem *reg)
4041 {
4042 char label[16];
4043 bool on;
4044 u32 val;
4045
4046 if (!reg)
4047 return;
4048
4049 sprintf(label, "FREQ%d", nr + 1);
4050 val = ioread32(®->ctrl);
4051 on = val & 1;
4052 val = (val >> 8) & 0xff;
4053 seq_printf(s, "%7s: %s, sec:%u",
4054 label,
4055 on ? " ON" : "OFF",
4056 val);
4057
4058 val = ioread32(®->status);
4059 if (val & FREQ_STATUS_ERROR)
4060 seq_printf(s, ", error");
4061 if (val & FREQ_STATUS_OVERRUN)
4062 seq_printf(s, ", overrun");
4063 if (val & FREQ_STATUS_VALID)
4064 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4065 seq_printf(s, " reg:%x\n", val);
4066 }
4067
4068 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4069 ptp_ocp_summary_show(struct seq_file *s, void *data)
4070 {
4071 struct device *dev = s->private;
4072 struct ptp_system_timestamp sts;
4073 struct ts_reg __iomem *ts_reg;
4074 char *buf, *src, *mac_src;
4075 struct timespec64 ts;
4076 struct ptp_ocp *bp;
4077 u16 sma_val[4][2];
4078 u32 ctrl, val;
4079 bool on, map;
4080 int i;
4081
4082 buf = (char *)__get_free_page(GFP_KERNEL);
4083 if (!buf)
4084 return -ENOMEM;
4085
4086 bp = dev_get_drvdata(dev);
4087
4088 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4089 for (i = 0; i < __PORT_COUNT; i++) {
4090 if (bp->port[i].line != -1)
4091 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4092 bp->port[i].line);
4093 }
4094
4095 memset(sma_val, 0xff, sizeof(sma_val));
4096 if (bp->sma_map1) {
4097 u32 reg;
4098
4099 reg = ioread32(&bp->sma_map1->gpio1);
4100 sma_val[0][0] = reg & 0xffff;
4101 sma_val[1][0] = reg >> 16;
4102
4103 reg = ioread32(&bp->sma_map1->gpio2);
4104 sma_val[2][1] = reg & 0xffff;
4105 sma_val[3][1] = reg >> 16;
4106
4107 reg = ioread32(&bp->sma_map2->gpio1);
4108 sma_val[2][0] = reg & 0xffff;
4109 sma_val[3][0] = reg >> 16;
4110
4111 reg = ioread32(&bp->sma_map2->gpio2);
4112 sma_val[0][1] = reg & 0xffff;
4113 sma_val[1][1] = reg >> 16;
4114 }
4115
4116 sma1_show(dev, NULL, buf);
4117 seq_printf(s, " sma1: %04x,%04x %s",
4118 sma_val[0][0], sma_val[0][1], buf);
4119
4120 sma2_show(dev, NULL, buf);
4121 seq_printf(s, " sma2: %04x,%04x %s",
4122 sma_val[1][0], sma_val[1][1], buf);
4123
4124 sma3_show(dev, NULL, buf);
4125 seq_printf(s, " sma3: %04x,%04x %s",
4126 sma_val[2][0], sma_val[2][1], buf);
4127
4128 sma4_show(dev, NULL, buf);
4129 seq_printf(s, " sma4: %04x,%04x %s",
4130 sma_val[3][0], sma_val[3][1], buf);
4131
4132 if (bp->ts0) {
4133 ts_reg = bp->ts0->mem;
4134 on = ioread32(&ts_reg->enable);
4135 src = "GNSS1";
4136 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4137 on ? " ON" : "OFF", src);
4138 }
4139
4140 if (bp->ts1) {
4141 ts_reg = bp->ts1->mem;
4142 on = ioread32(&ts_reg->enable);
4143 gpio_input_map(buf, bp, sma_val, 2, NULL);
4144 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4145 on ? " ON" : "OFF", buf);
4146 }
4147
4148 if (bp->ts2) {
4149 ts_reg = bp->ts2->mem;
4150 on = ioread32(&ts_reg->enable);
4151 gpio_input_map(buf, bp, sma_val, 3, NULL);
4152 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4153 on ? " ON" : "OFF", buf);
4154 }
4155
4156 if (bp->ts3) {
4157 ts_reg = bp->ts3->mem;
4158 on = ioread32(&ts_reg->enable);
4159 gpio_input_map(buf, bp, sma_val, 6, NULL);
4160 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4161 on ? " ON" : "OFF", buf);
4162 }
4163
4164 if (bp->ts4) {
4165 ts_reg = bp->ts4->mem;
4166 on = ioread32(&ts_reg->enable);
4167 gpio_input_map(buf, bp, sma_val, 7, NULL);
4168 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4169 on ? " ON" : "OFF", buf);
4170 }
4171
4172 if (bp->pps) {
4173 ts_reg = bp->pps->mem;
4174 src = "PHC";
4175 on = ioread32(&ts_reg->enable);
4176 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4177 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4178 on && map ? " ON" : "OFF", src);
4179
4180 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4181 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4182 on && map ? " ON" : "OFF", src);
4183 }
4184
4185 if (bp->fw_cap & OCP_CAP_SIGNAL)
4186 for (i = 0; i < bp->signals_nr; i++)
4187 _signal_summary_show(s, bp, i);
4188
4189 if (bp->fw_cap & OCP_CAP_FREQ)
4190 for (i = 0; i < bp->freq_in_nr; i++)
4191 _frequency_summary_show(s, i, bp->freq_in[i]);
4192
4193 if (bp->irig_out) {
4194 ctrl = ioread32(&bp->irig_out->ctrl);
4195 on = ctrl & IRIG_M_CTRL_ENABLE;
4196 val = ioread32(&bp->irig_out->status);
4197 gpio_output_map(buf, bp, sma_val, 4);
4198 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4199 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4200 }
4201
4202 if (bp->irig_in) {
4203 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4204 val = ioread32(&bp->irig_in->status);
4205 gpio_input_map(buf, bp, sma_val, 4, NULL);
4206 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4207 on ? " ON" : "OFF", val, buf);
4208 }
4209
4210 if (bp->dcf_out) {
4211 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4212 val = ioread32(&bp->dcf_out->status);
4213 gpio_output_map(buf, bp, sma_val, 5);
4214 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4215 on ? " ON" : "OFF", val, buf);
4216 }
4217
4218 if (bp->dcf_in) {
4219 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4220 val = ioread32(&bp->dcf_in->status);
4221 gpio_input_map(buf, bp, sma_val, 5, NULL);
4222 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4223 on ? " ON" : "OFF", val, buf);
4224 }
4225
4226 if (bp->nmea_out) {
4227 on = ioread32(&bp->nmea_out->ctrl) & 1;
4228 val = ioread32(&bp->nmea_out->status);
4229 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4230 on ? " ON" : "OFF", val);
4231 }
4232
4233 /* compute src for PPS1, used below. */
4234 if (bp->pps_select) {
4235 val = ioread32(&bp->pps_select->gpio1);
4236 src = &buf[80];
4237 mac_src = "GNSS1";
4238 if (val & 0x01) {
4239 gpio_input_map(src, bp, sma_val, 0, NULL);
4240 mac_src = src;
4241 } else if (val & 0x02) {
4242 src = "MAC";
4243 } else if (val & 0x04) {
4244 src = "GNSS1";
4245 } else {
4246 src = "----";
4247 mac_src = src;
4248 }
4249 } else {
4250 src = "?";
4251 mac_src = src;
4252 }
4253 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4254
4255 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4256 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4257
4258 /* assumes automatic switchover/selection */
4259 val = ioread32(&bp->reg->select);
4260 switch (val >> 16) {
4261 case 0:
4262 sprintf(buf, "----");
4263 break;
4264 case 2:
4265 sprintf(buf, "IRIG");
4266 break;
4267 case 3:
4268 sprintf(buf, "%s via PPS1", src);
4269 break;
4270 case 6:
4271 sprintf(buf, "DCF");
4272 break;
4273 default:
4274 strcpy(buf, "unknown");
4275 break;
4276 }
4277 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4278 bp->sync ? "sync" : "unsynced");
4279
4280 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4281 struct timespec64 sys_ts;
4282 s64 pre_ns, post_ns, ns;
4283
4284 pre_ns = timespec64_to_ns(&sts.pre_ts);
4285 post_ns = timespec64_to_ns(&sts.post_ts);
4286 ns = (pre_ns + post_ns) / 2;
4287 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4288 sys_ts = ns_to_timespec64(ns);
4289
4290 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4291 ts.tv_sec, ts.tv_nsec, &ts);
4292 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4293 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4294 bp->utc_tai_offset);
4295 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4296 timespec64_to_ns(&ts) - ns,
4297 post_ns - pre_ns);
4298 }
4299
4300 free_page((unsigned long)buf);
4301 return 0;
4302 }
4303 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4304
4305 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4306 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4307 {
4308 struct device *dev = s->private;
4309 struct ptp_ocp *bp;
4310 u32 val;
4311 int idx;
4312
4313 bp = dev_get_drvdata(dev);
4314
4315 val = ioread32(&bp->tod->ctrl);
4316 if (!(val & TOD_CTRL_ENABLE)) {
4317 seq_printf(s, "TOD Slave disabled\n");
4318 return 0;
4319 }
4320 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4321
4322 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4323 idx += (val >> 16) & 3;
4324 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4325
4326 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4327 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4328
4329 val = ioread32(&bp->tod->version);
4330 seq_printf(s, "TOD Version %d.%d.%d\n",
4331 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4332
4333 val = ioread32(&bp->tod->status);
4334 seq_printf(s, "Status register: 0x%08X\n", val);
4335
4336 val = ioread32(&bp->tod->adj_sec);
4337 idx = (val & ~INT_MAX) ? -1 : 1;
4338 idx *= (val & INT_MAX);
4339 seq_printf(s, "Correction seconds: %d\n", idx);
4340
4341 val = ioread32(&bp->tod->utc_status);
4342 seq_printf(s, "UTC status register: 0x%08X\n", val);
4343 seq_printf(s, "UTC offset: %ld valid:%d\n",
4344 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4345 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4346 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4347 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4348
4349 val = ioread32(&bp->tod->leap);
4350 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4351
4352 return 0;
4353 }
4354 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4355
4356 static struct dentry *ptp_ocp_debugfs_root;
4357
4358 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4359 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4360 {
4361 struct dentry *d;
4362
4363 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4364 bp->debug_root = d;
4365 debugfs_create_file("summary", 0444, bp->debug_root,
4366 &bp->dev, &ptp_ocp_summary_fops);
4367 if (bp->tod)
4368 debugfs_create_file("tod_status", 0444, bp->debug_root,
4369 &bp->dev, &ptp_ocp_tod_status_fops);
4370 }
4371
4372 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4373 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4374 {
4375 debugfs_remove_recursive(bp->debug_root);
4376 }
4377
4378 static void
ptp_ocp_debugfs_init(void)4379 ptp_ocp_debugfs_init(void)
4380 {
4381 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4382 }
4383
4384 static void
ptp_ocp_debugfs_fini(void)4385 ptp_ocp_debugfs_fini(void)
4386 {
4387 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4388 }
4389
4390 static void
ptp_ocp_dev_release(struct device * dev)4391 ptp_ocp_dev_release(struct device *dev)
4392 {
4393 struct ptp_ocp *bp = dev_get_drvdata(dev);
4394
4395 mutex_lock(&ptp_ocp_lock);
4396 idr_remove(&ptp_ocp_idr, bp->id);
4397 mutex_unlock(&ptp_ocp_lock);
4398 }
4399
4400 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4401 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4402 {
4403 int i, err;
4404
4405 mutex_lock(&ptp_ocp_lock);
4406 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4407 mutex_unlock(&ptp_ocp_lock);
4408 if (err < 0) {
4409 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4410 return err;
4411 }
4412 bp->id = err;
4413
4414 bp->ptp_info = ptp_ocp_clock_info;
4415 spin_lock_init(&bp->lock);
4416
4417 for (i = 0; i < __PORT_COUNT; i++)
4418 bp->port[i].line = -1;
4419
4420 bp->pdev = pdev;
4421
4422 device_initialize(&bp->dev);
4423 dev_set_name(&bp->dev, "ocp%d", bp->id);
4424 bp->dev.class = &timecard_class;
4425 bp->dev.parent = &pdev->dev;
4426 bp->dev.release = ptp_ocp_dev_release;
4427 dev_set_drvdata(&bp->dev, bp);
4428
4429 err = device_add(&bp->dev);
4430 if (err) {
4431 dev_err(&bp->dev, "device add failed: %d\n", err);
4432 goto out;
4433 }
4434
4435 pci_set_drvdata(pdev, bp);
4436
4437 return 0;
4438
4439 out:
4440 put_device(&bp->dev);
4441 return err;
4442 }
4443
4444 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4445 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4446 {
4447 struct device *dev = &bp->dev;
4448
4449 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4450 dev_err(dev, "%s symlink failed\n", link);
4451 }
4452
4453 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4454 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4455 {
4456 struct device *dev, *child;
4457
4458 dev = &bp->pdev->dev;
4459
4460 child = device_find_child_by_name(dev, name);
4461 if (!child) {
4462 dev_err(dev, "Could not find device %s\n", name);
4463 return;
4464 }
4465
4466 ptp_ocp_symlink(bp, child, link);
4467 put_device(child);
4468 }
4469
4470 static int
ptp_ocp_complete(struct ptp_ocp * bp)4471 ptp_ocp_complete(struct ptp_ocp *bp)
4472 {
4473 struct pps_device *pps;
4474 char buf[32];
4475
4476 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4477 ptp_ocp_link_child(bp, buf, "ptp");
4478
4479 pps = pps_lookup_dev(bp->ptp);
4480 if (pps)
4481 ptp_ocp_symlink(bp, &pps->dev, "pps");
4482
4483 ptp_ocp_debugfs_add_device(bp);
4484
4485 return 0;
4486 }
4487
4488 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4489 ptp_ocp_phc_info(struct ptp_ocp *bp)
4490 {
4491 struct timespec64 ts;
4492 u32 version, select;
4493
4494 version = ioread32(&bp->reg->version);
4495 select = ioread32(&bp->reg->select);
4496 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4497 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4498 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4499 ptp_clock_index(bp->ptp));
4500
4501 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4502 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4503 ts.tv_sec, ts.tv_nsec,
4504 bp->sync ? "in-sync" : "UNSYNCED");
4505 }
4506
4507 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4508 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4509 {
4510 if (port != -1)
4511 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4512 }
4513
4514 static void
ptp_ocp_info(struct ptp_ocp * bp)4515 ptp_ocp_info(struct ptp_ocp *bp)
4516 {
4517 static int nmea_baud[] = {
4518 1200, 2400, 4800, 9600, 19200, 38400,
4519 57600, 115200, 230400, 460800, 921600,
4520 1000000, 2000000
4521 };
4522 struct device *dev = &bp->pdev->dev;
4523 u32 reg;
4524 int i;
4525
4526 ptp_ocp_phc_info(bp);
4527
4528 for (i = 0; i < __PORT_COUNT; i++) {
4529 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4530 bp->port[PORT_NMEA].baud = -1;
4531
4532 reg = ioread32(&bp->nmea_out->uart_baud);
4533 if (reg < ARRAY_SIZE(nmea_baud))
4534 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4535 }
4536 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4537 bp->port[i].baud);
4538 }
4539 }
4540
4541 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4542 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4543 {
4544 struct device *dev = &bp->dev;
4545
4546 sysfs_remove_link(&dev->kobj, "ptp");
4547 sysfs_remove_link(&dev->kobj, "pps");
4548 }
4549
4550 static void
ptp_ocp_detach(struct ptp_ocp * bp)4551 ptp_ocp_detach(struct ptp_ocp *bp)
4552 {
4553 int i;
4554
4555 ptp_ocp_debugfs_remove_device(bp);
4556 ptp_ocp_detach_sysfs(bp);
4557 ptp_ocp_attr_group_del(bp);
4558 timer_delete_sync(&bp->watchdog);
4559 if (bp->ts0)
4560 ptp_ocp_unregister_ext(bp->ts0);
4561 if (bp->ts1)
4562 ptp_ocp_unregister_ext(bp->ts1);
4563 if (bp->ts2)
4564 ptp_ocp_unregister_ext(bp->ts2);
4565 if (bp->ts3)
4566 ptp_ocp_unregister_ext(bp->ts3);
4567 if (bp->ts4)
4568 ptp_ocp_unregister_ext(bp->ts4);
4569 if (bp->pps)
4570 ptp_ocp_unregister_ext(bp->pps);
4571 for (i = 0; i < 4; i++)
4572 if (bp->signal_out[i])
4573 ptp_ocp_unregister_ext(bp->signal_out[i]);
4574 for (i = 0; i < __PORT_COUNT; i++)
4575 if (bp->port[i].line != -1)
4576 serial8250_unregister_port(bp->port[i].line);
4577 platform_device_unregister(bp->spi_flash);
4578 platform_device_unregister(bp->i2c_ctrl);
4579 if (bp->i2c_clk)
4580 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4581 if (bp->n_irqs)
4582 pci_free_irq_vectors(bp->pdev);
4583 if (bp->ptp)
4584 ptp_clock_unregister(bp->ptp);
4585 kfree(bp->ptp_info.pin_config);
4586 device_unregister(&bp->dev);
4587 }
4588
4589 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4590 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4591 enum dpll_lock_status *status,
4592 enum dpll_lock_status_error *status_error,
4593 struct netlink_ext_ack *extack)
4594 {
4595 struct ptp_ocp *bp = priv;
4596
4597 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4598
4599 return 0;
4600 }
4601
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4602 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4603 const struct dpll_device *dpll, void *priv,
4604 enum dpll_pin_state *state,
4605 struct netlink_ext_ack *extack)
4606 {
4607 struct ptp_ocp *bp = priv;
4608 int idx;
4609
4610 if (bp->pps_select) {
4611 idx = ioread32(&bp->pps_select->gpio1);
4612 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4613 DPLL_PIN_STATE_SELECTABLE;
4614 return 0;
4615 }
4616 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4617 return -EINVAL;
4618 }
4619
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4620 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4621 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4622 {
4623 *mode = DPLL_MODE_AUTOMATIC;
4624 return 0;
4625 }
4626
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4627 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4628 void *pin_priv,
4629 const struct dpll_device *dpll,
4630 void *priv,
4631 enum dpll_pin_direction *direction,
4632 struct netlink_ext_ack *extack)
4633 {
4634 struct ptp_ocp_sma_connector *sma = pin_priv;
4635
4636 *direction = sma->mode == SMA_MODE_IN ?
4637 DPLL_PIN_DIRECTION_INPUT :
4638 DPLL_PIN_DIRECTION_OUTPUT;
4639 return 0;
4640 }
4641
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4642 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4643 void *pin_priv,
4644 const struct dpll_device *dpll,
4645 void *dpll_priv,
4646 enum dpll_pin_direction direction,
4647 struct netlink_ext_ack *extack)
4648 {
4649 struct ptp_ocp_sma_connector *sma = pin_priv;
4650 struct ptp_ocp *bp = dpll_priv;
4651 enum ptp_ocp_sma_mode mode;
4652 int sma_nr = (sma - bp->sma);
4653
4654 if (sma->fixed_dir)
4655 return -EOPNOTSUPP;
4656 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4657 SMA_MODE_IN : SMA_MODE_OUT;
4658 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4659 }
4660
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4661 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4662 void *pin_priv,
4663 const struct dpll_device *dpll,
4664 void *dpll_priv, u64 frequency,
4665 struct netlink_ext_ack *extack)
4666 {
4667 struct ptp_ocp_sma_connector *sma = pin_priv;
4668 struct ptp_ocp *bp = dpll_priv;
4669 const struct ocp_selector *tbl;
4670 int sma_nr = (sma - bp->sma);
4671 int i;
4672
4673 if (sma->fixed_fcn)
4674 return -EOPNOTSUPP;
4675
4676 tbl = bp->sma_op->tbl[sma->mode];
4677 for (i = 0; tbl[i].name; i++)
4678 if (tbl[i].frequency == frequency)
4679 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
4680 return -EINVAL;
4681 }
4682
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)4683 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4684 void *pin_priv,
4685 const struct dpll_device *dpll,
4686 void *dpll_priv, u64 *frequency,
4687 struct netlink_ext_ack *extack)
4688 {
4689 struct ptp_ocp_sma_connector *sma = pin_priv;
4690 struct ptp_ocp *bp = dpll_priv;
4691 const struct ocp_selector *tbl;
4692 int sma_nr = (sma - bp->sma);
4693 u32 val;
4694 int i;
4695
4696 val = bp->sma_op->get(bp, sma_nr + 1);
4697 tbl = bp->sma_op->tbl[sma->mode];
4698 for (i = 0; tbl[i].name; i++)
4699 if (val == tbl[i].value) {
4700 *frequency = tbl[i].frequency;
4701 return 0;
4702 }
4703
4704 return -EINVAL;
4705 }
4706
4707 static const struct dpll_device_ops dpll_ops = {
4708 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4709 .mode_get = ptp_ocp_dpll_mode_get,
4710 };
4711
4712 static const struct dpll_pin_ops dpll_pins_ops = {
4713 .frequency_get = ptp_ocp_dpll_frequency_get,
4714 .frequency_set = ptp_ocp_dpll_frequency_set,
4715 .direction_get = ptp_ocp_dpll_direction_get,
4716 .direction_set = ptp_ocp_dpll_direction_set,
4717 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4718 };
4719
4720 static void
ptp_ocp_sync_work(struct work_struct * work)4721 ptp_ocp_sync_work(struct work_struct *work)
4722 {
4723 struct ptp_ocp *bp;
4724 bool sync;
4725
4726 bp = container_of(work, struct ptp_ocp, sync_work.work);
4727 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4728
4729 if (bp->sync != sync)
4730 dpll_device_change_ntf(bp->dpll);
4731
4732 bp->sync = sync;
4733
4734 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4735 }
4736
4737 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4738 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4739 {
4740 struct devlink *devlink;
4741 struct ptp_ocp *bp;
4742 int err, i;
4743 u64 clkid;
4744
4745 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4746 if (!devlink) {
4747 dev_err(&pdev->dev, "devlink_alloc failed\n");
4748 return -ENOMEM;
4749 }
4750
4751 err = pci_enable_device(pdev);
4752 if (err) {
4753 dev_err(&pdev->dev, "pci_enable_device\n");
4754 goto out_free;
4755 }
4756
4757 bp = devlink_priv(devlink);
4758 err = ptp_ocp_device_init(bp, pdev);
4759 if (err)
4760 goto out_disable;
4761
4762 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4763
4764 /* compat mode.
4765 * Older FPGA firmware only returns 2 irq's.
4766 * allow this - if not all of the IRQ's are returned, skip the
4767 * extra devices and just register the clock.
4768 */
4769 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4770 if (err < 0) {
4771 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4772 goto out;
4773 }
4774 bp->n_irqs = err;
4775 pci_set_master(pdev);
4776
4777 err = ptp_ocp_register_resources(bp, id->driver_data);
4778 if (err)
4779 goto out;
4780
4781 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4782 if (IS_ERR(bp->ptp)) {
4783 err = PTR_ERR(bp->ptp);
4784 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4785 bp->ptp = NULL;
4786 goto out;
4787 }
4788
4789 err = ptp_ocp_complete(bp);
4790 if (err)
4791 goto out;
4792
4793 ptp_ocp_info(bp);
4794 devlink_register(devlink);
4795
4796 clkid = pci_get_dsn(pdev);
4797 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4798 if (IS_ERR(bp->dpll)) {
4799 err = PTR_ERR(bp->dpll);
4800 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4801 goto out;
4802 }
4803
4804 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4805 if (err)
4806 goto out;
4807
4808 for (i = 0; i < OCP_SMA_NUM; i++) {
4809 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4810 if (IS_ERR(bp->sma[i].dpll_pin)) {
4811 err = PTR_ERR(bp->sma[i].dpll_pin);
4812 goto out_dpll;
4813 }
4814
4815 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4816 &bp->sma[i]);
4817 if (err) {
4818 dpll_pin_put(bp->sma[i].dpll_pin);
4819 goto out_dpll;
4820 }
4821 }
4822 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4823
4824 return 0;
4825 out_dpll:
4826 while (i) {
4827 --i;
4828 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4829 dpll_pin_put(bp->sma[i].dpll_pin);
4830 }
4831 dpll_device_put(bp->dpll);
4832 out:
4833 ptp_ocp_detach(bp);
4834 out_disable:
4835 pci_disable_device(pdev);
4836 out_free:
4837 devlink_free(devlink);
4838 return err;
4839 }
4840
4841 static void
ptp_ocp_remove(struct pci_dev * pdev)4842 ptp_ocp_remove(struct pci_dev *pdev)
4843 {
4844 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4845 struct devlink *devlink = priv_to_devlink(bp);
4846 int i;
4847
4848 cancel_delayed_work_sync(&bp->sync_work);
4849 for (i = 0; i < OCP_SMA_NUM; i++) {
4850 if (bp->sma[i].dpll_pin) {
4851 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4852 dpll_pin_put(bp->sma[i].dpll_pin);
4853 }
4854 }
4855 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4856 dpll_device_put(bp->dpll);
4857 devlink_unregister(devlink);
4858 ptp_ocp_detach(bp);
4859 pci_disable_device(pdev);
4860
4861 devlink_free(devlink);
4862 }
4863
4864 static struct pci_driver ptp_ocp_driver = {
4865 .name = KBUILD_MODNAME,
4866 .id_table = ptp_ocp_pcidev_id,
4867 .probe = ptp_ocp_probe,
4868 .remove = ptp_ocp_remove,
4869 };
4870
4871 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4872 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4873 unsigned long action, void *data)
4874 {
4875 struct device *dev, *child = data;
4876 struct ptp_ocp *bp;
4877 bool add;
4878
4879 switch (action) {
4880 case BUS_NOTIFY_ADD_DEVICE:
4881 case BUS_NOTIFY_DEL_DEVICE:
4882 add = action == BUS_NOTIFY_ADD_DEVICE;
4883 break;
4884 default:
4885 return 0;
4886 }
4887
4888 if (!i2c_verify_adapter(child))
4889 return 0;
4890
4891 dev = child;
4892 while ((dev = dev->parent))
4893 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4894 goto found;
4895 return 0;
4896
4897 found:
4898 bp = dev_get_drvdata(dev);
4899 if (add)
4900 ptp_ocp_symlink(bp, child, "i2c");
4901 else
4902 sysfs_remove_link(&bp->dev.kobj, "i2c");
4903
4904 return 0;
4905 }
4906
4907 static struct notifier_block ptp_ocp_i2c_notifier = {
4908 .notifier_call = ptp_ocp_i2c_notifier_call,
4909 };
4910
4911 static int __init
ptp_ocp_init(void)4912 ptp_ocp_init(void)
4913 {
4914 const char *what;
4915 int err;
4916
4917 ptp_ocp_debugfs_init();
4918
4919 what = "timecard class";
4920 err = class_register(&timecard_class);
4921 if (err)
4922 goto out;
4923
4924 what = "i2c notifier";
4925 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4926 if (err)
4927 goto out_notifier;
4928
4929 what = "ptp_ocp driver";
4930 err = pci_register_driver(&ptp_ocp_driver);
4931 if (err)
4932 goto out_register;
4933
4934 return 0;
4935
4936 out_register:
4937 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4938 out_notifier:
4939 class_unregister(&timecard_class);
4940 out:
4941 ptp_ocp_debugfs_fini();
4942 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4943 return err;
4944 }
4945
4946 static void __exit
ptp_ocp_fini(void)4947 ptp_ocp_fini(void)
4948 {
4949 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4950 pci_unregister_driver(&ptp_ocp_driver);
4951 class_unregister(&timecard_class);
4952 ptp_ocp_debugfs_fini();
4953 }
4954
4955 module_init(ptp_ocp_init);
4956 module_exit(ptp_ocp_fini);
4957
4958 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4959 MODULE_LICENSE("GPL v2");
4960