1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the GalaxyCore GC0308 camera sensor.
4 *
5 * Copyright (c) 2023 Sebastian Reichel <sre@kernel.org>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16
17 #include <media/v4l2-cci.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22
23 /* Analog & CISCTL*/
24 #define GC0308_CHIP_ID CCI_REG8(0x000)
25 #define GC0308_HBLANK CCI_REG8(0x001)
26 #define GC0308_VBLANK CCI_REG8(0x002)
27 #define GC0308_EXP CCI_REG16(0x003)
28 #define GC0308_ROW_START CCI_REG16(0x005)
29 #define GC0308_COL_START CCI_REG16(0x007)
30 #define GC0308_WIN_HEIGHT CCI_REG16(0x009)
31 #define GC0308_WIN_WIDTH CCI_REG16(0x00b)
32 #define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */
33 #define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */
34 #define GC0308_VB_HB CCI_REG8(0x00f)
35 #define GC0308_RSH_WIDTH CCI_REG8(0x010)
36 #define GC0308_TSP_WIDTH CCI_REG8(0x011)
37 #define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012)
38 #define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013)
39 #define GC0308_CISCTL_MODE1 CCI_REG8(0x014)
40 #define GC0308_CISCTL_MODE2 CCI_REG8(0x015)
41 #define GC0308_CISCTL_MODE3 CCI_REG8(0x016)
42 #define GC0308_CISCTL_MODE4 CCI_REG8(0x017)
43 #define GC0308_ANALOG_MODE1 CCI_REG8(0x01a)
44 #define GC0308_ANALOG_MODE2 CCI_REG8(0x01b)
45 #define GC0308_HRST_RSG_V18 CCI_REG8(0x01c)
46 #define GC0308_VREF_V25 CCI_REG8(0x01d)
47 #define GC0308_ADC_R CCI_REG8(0x01e)
48 #define GC0308_PAD_DRV CCI_REG8(0x01f)
49 #define GC0308_SOFT_RESET CCI_REG8(0x0fe)
50
51 /* ISP */
52 #define GC0308_BLOCK_EN1 CCI_REG8(0x020)
53 #define GC0308_BLOCK_EN2 CCI_REG8(0x021)
54 #define GC0308_AAAA_EN CCI_REG8(0x022)
55 #define GC0308_SPECIAL_EFFECT CCI_REG8(0x023)
56 #define GC0308_OUT_FORMAT CCI_REG8(0x024)
57 #define GC0308_OUT_EN CCI_REG8(0x025)
58 #define GC0308_SYNC_MODE CCI_REG8(0x026)
59 #define GC0308_CLK_DIV_MODE CCI_REG8(0x028)
60 #define GC0308_BYPASS_MODE CCI_REG8(0x029)
61 #define GC0308_CLK_GATING CCI_REG8(0x02a)
62 #define GC0308_DITHER_MODE CCI_REG8(0x02b)
63 #define GC0308_DITHER_BIT CCI_REG8(0x02c)
64 #define GC0308_DEBUG_MODE1 CCI_REG8(0x02d)
65 #define GC0308_DEBUG_MODE2 CCI_REG8(0x02e)
66 #define GC0308_DEBUG_MODE3 CCI_REG8(0x02f)
67 #define GC0308_CROP_WIN_MODE CCI_REG8(0x046)
68 #define GC0308_CROP_WIN_Y1 CCI_REG8(0x047)
69 #define GC0308_CROP_WIN_X1 CCI_REG8(0x048)
70 #define GC0308_CROP_WIN_HEIGHT CCI_REG16(0x049)
71 #define GC0308_CROP_WIN_WIDTH CCI_REG16(0x04b)
72
73 /* BLK */
74 #define GC0308_BLK_MODE CCI_REG8(0x030)
75 #define GC0308_BLK_LIMIT_VAL CCI_REG8(0x031)
76 #define GC0308_GLOBAL_OFF CCI_REG8(0x032)
77 #define GC0308_CURRENT_R_OFF CCI_REG8(0x033)
78 #define GC0308_CURRENT_G_OFF CCI_REG8(0x034)
79 #define GC0308_CURRENT_B_OFF CCI_REG8(0x035)
80 #define GC0308_CURRENT_R_DARK_CURRENT CCI_REG8(0x036)
81 #define GC0308_CURRENT_G_DARK_CURRENT CCI_REG8(0x037)
82 #define GC0308_CURRENT_B_DARK_CURRENT CCI_REG8(0x038)
83 #define GC0308_EXP_RATE_DARKC CCI_REG8(0x039)
84 #define GC0308_OFF_SUBMODE CCI_REG8(0x03a)
85 #define GC0308_DARKC_SUBMODE CCI_REG8(0x03b)
86 #define GC0308_MANUAL_G1_OFF CCI_REG8(0x03c)
87 #define GC0308_MANUAL_R1_OFF CCI_REG8(0x03d)
88 #define GC0308_MANUAL_B2_OFF CCI_REG8(0x03e)
89 #define GC0308_MANUAL_G2_OFF CCI_REG8(0x03f)
90
91 /* PREGAIN */
92 #define GC0308_GLOBAL_GAIN CCI_REG8(0x050)
93 #define GC0308_AUTO_PREGAIN CCI_REG8(0x051)
94 #define GC0308_AUTO_POSTGAIN CCI_REG8(0x052)
95 #define GC0308_CHANNEL_GAIN_G1 CCI_REG8(0x053)
96 #define GC0308_CHANNEL_GAIN_R CCI_REG8(0x054)
97 #define GC0308_CHANNEL_GAIN_B CCI_REG8(0x055)
98 #define GC0308_CHANNEL_GAIN_G2 CCI_REG8(0x056)
99 #define GC0308_R_RATIO CCI_REG8(0x057)
100 #define GC0308_G_RATIO CCI_REG8(0x058)
101 #define GC0308_B_RATIO CCI_REG8(0x059)
102 #define GC0308_AWB_R_GAIN CCI_REG8(0x05a)
103 #define GC0308_AWB_G_GAIN CCI_REG8(0x05b)
104 #define GC0308_AWB_B_GAIN CCI_REG8(0x05c)
105 #define GC0308_LSC_DEC_LVL1 CCI_REG8(0x05d)
106 #define GC0308_LSC_DEC_LVL2 CCI_REG8(0x05e)
107 #define GC0308_LSC_DEC_LVL3 CCI_REG8(0x05f)
108
109 /* DNDD */
110 #define GC0308_DN_MODE_EN CCI_REG8(0x060)
111 #define GC0308_DN_MODE_RATIO CCI_REG8(0x061)
112 #define GC0308_DN_BILAT_B_BASE CCI_REG8(0x062)
113 #define GC0308_DN_B_INCR CCI_REG8(0x063)
114 #define GC0308_DN_BILAT_N_BASE CCI_REG8(0x064)
115 #define GC0308_DN_N_INCR CCI_REG8(0x065)
116 #define GC0308_DD_DARK_BRIGHT_TH CCI_REG8(0x066)
117 #define GC0308_DD_FLAT_TH CCI_REG8(0x067)
118 #define GC0308_DD_LIMIT CCI_REG8(0x068)
119
120 /* ASDE - Auto Saturation De-noise and Edge-Enhancement */
121 #define GC0308_ASDE_GAIN_TRESH CCI_REG8(0x069)
122 #define GC0308_ASDE_GAIN_MODE CCI_REG8(0x06a)
123 #define GC0308_ASDE_DN_SLOPE CCI_REG8(0x06b)
124 #define GC0308_ASDE_DD_BRIGHT CCI_REG8(0x06c)
125 #define GC0308_ASDE_DD_LIMIT CCI_REG8(0x06d)
126 #define GC0308_ASDE_AUTO_EE1 CCI_REG8(0x06e)
127 #define GC0308_ASDE_AUTO_EE2 CCI_REG8(0x06f)
128 #define GC0308_ASDE_AUTO_SAT_DEC_SLOPE CCI_REG8(0x070)
129 #define GC0308_ASDE_AUTO_SAT_LOW_LIMIT CCI_REG8(0x071)
130
131 /* INTPEE - Interpolation and Edge-Enhancement */
132 #define GC0308_EEINTP_MODE_1 CCI_REG8(0x072)
133 #define GC0308_EEINTP_MODE_2 CCI_REG8(0x073)
134 #define GC0308_DIRECTION_TH1 CCI_REG8(0x074)
135 #define GC0308_DIRECTION_TH2 CCI_REG8(0x075)
136 #define GC0308_DIFF_HV_TI_TH CCI_REG8(0x076)
137 #define GC0308_EDGE12_EFFECT CCI_REG8(0x077)
138 #define GC0308_EDGE_POS_RATIO CCI_REG8(0x078)
139 #define GC0308_EDGE1_MINMAX CCI_REG8(0x079)
140 #define GC0308_EDGE2_MINMAX CCI_REG8(0x07a)
141 #define GC0308_EDGE12_TH CCI_REG8(0x07b)
142 #define GC0308_EDGE_MAX CCI_REG8(0x07c)
143
144 /* ABB - Auto Black Balance */
145 #define GC0308_ABB_MODE CCI_REG8(0x080)
146 #define GC0308_ABB_TARGET_AVGH CCI_REG8(0x081)
147 #define GC0308_ABB_TARGET_AVGL CCI_REG8(0x082)
148 #define GC0308_ABB_LIMIT_VAL CCI_REG8(0x083)
149 #define GC0308_ABB_SPEED CCI_REG8(0x084)
150 #define GC0308_CURR_R_BLACK_LVL CCI_REG8(0x085)
151 #define GC0308_CURR_G_BLACK_LVL CCI_REG8(0x086)
152 #define GC0308_CURR_B_BLACK_LVL CCI_REG8(0x087)
153 #define GC0308_CURR_R_BLACK_FACTOR CCI_REG8(0x088)
154 #define GC0308_CURR_G_BLACK_FACTOR CCI_REG8(0x089)
155 #define GC0308_CURR_B_BLACK_FACTOR CCI_REG8(0x08a)
156
157 /* LSC - Lens Shading Correction */
158 #define GC0308_LSC_RED_B2 CCI_REG8(0x08b)
159 #define GC0308_LSC_GREEN_B2 CCI_REG8(0x08c)
160 #define GC0308_LSC_BLUE_B2 CCI_REG8(0x08d)
161 #define GC0308_LSC_RED_B4 CCI_REG8(0x08e)
162 #define GC0308_LSC_GREEN_B4 CCI_REG8(0x08f)
163 #define GC0308_LSC_BLUE_B4 CCI_REG8(0x090)
164 #define GC0308_LSC_ROW_CENTER CCI_REG8(0x091)
165 #define GC0308_LSC_COL_CENTER CCI_REG8(0x092)
166
167 /* CC - Channel Coefficient */
168 #define GC0308_CC_MATRIX_C11 CCI_REG8(0x093)
169 #define GC0308_CC_MATRIX_C12 CCI_REG8(0x094)
170 #define GC0308_CC_MATRIX_C13 CCI_REG8(0x095)
171 #define GC0308_CC_MATRIX_C21 CCI_REG8(0x096)
172 #define GC0308_CC_MATRIX_C22 CCI_REG8(0x097)
173 #define GC0308_CC_MATRIX_C23 CCI_REG8(0x098)
174 #define GC0308_CC_MATRIX_C41 CCI_REG8(0x09c)
175 #define GC0308_CC_MATRIX_C42 CCI_REG8(0x09d)
176 #define GC0308_CC_MATRIX_C43 CCI_REG8(0x09e)
177
178 /* GAMMA */
179 #define GC0308_GAMMA_OUT0 CCI_REG8(0x09f)
180 #define GC0308_GAMMA_OUT1 CCI_REG8(0x0a0)
181 #define GC0308_GAMMA_OUT2 CCI_REG8(0x0a1)
182 #define GC0308_GAMMA_OUT3 CCI_REG8(0x0a2)
183 #define GC0308_GAMMA_OUT4 CCI_REG8(0x0a3)
184 #define GC0308_GAMMA_OUT5 CCI_REG8(0x0a4)
185 #define GC0308_GAMMA_OUT6 CCI_REG8(0x0a5)
186 #define GC0308_GAMMA_OUT7 CCI_REG8(0x0a6)
187 #define GC0308_GAMMA_OUT8 CCI_REG8(0x0a7)
188 #define GC0308_GAMMA_OUT9 CCI_REG8(0x0a8)
189 #define GC0308_GAMMA_OUT10 CCI_REG8(0x0a9)
190 #define GC0308_GAMMA_OUT11 CCI_REG8(0x0aa)
191 #define GC0308_GAMMA_OUT12 CCI_REG8(0x0ab)
192 #define GC0308_GAMMA_OUT13 CCI_REG8(0x0ac)
193 #define GC0308_GAMMA_OUT14 CCI_REG8(0x0ad)
194 #define GC0308_GAMMA_OUT15 CCI_REG8(0x0ae)
195 #define GC0308_GAMMA_OUT16 CCI_REG8(0x0af)
196
197 /* YCP */
198 #define GC0308_GLOBAL_SATURATION CCI_REG8(0x0b0)
199 #define GC0308_SATURATION_CB CCI_REG8(0x0b1)
200 #define GC0308_SATURATION_CR CCI_REG8(0x0b2)
201 #define GC0308_LUMA_CONTRAST CCI_REG8(0x0b3)
202 #define GC0308_CONTRAST_CENTER CCI_REG8(0x0b4)
203 #define GC0308_LUMA_OFFSET CCI_REG8(0x0b5)
204 #define GC0308_SKIN_CB_CENTER CCI_REG8(0x0b6)
205 #define GC0308_SKIN_CR_CENTER CCI_REG8(0x0b7)
206 #define GC0308_SKIN_RADIUS_SQUARE CCI_REG8(0x0b8)
207 #define GC0308_SKIN_BRIGHTNESS CCI_REG8(0x0b9)
208 #define GC0308_FIXED_CB CCI_REG8(0x0ba)
209 #define GC0308_FIXED_CR CCI_REG8(0x0bb)
210 #define GC0308_EDGE_DEC_SA CCI_REG8(0x0bd)
211 #define GC0308_AUTO_GRAY_MODE CCI_REG8(0x0be)
212 #define GC0308_SATURATION_SUB_STRENGTH CCI_REG8(0x0bf)
213 #define GC0308_Y_GAMMA_OUT0 CCI_REG8(0x0c0)
214 #define GC0308_Y_GAMMA_OUT1 CCI_REG8(0x0c1)
215 #define GC0308_Y_GAMMA_OUT2 CCI_REG8(0x0c2)
216 #define GC0308_Y_GAMMA_OUT3 CCI_REG8(0x0c3)
217 #define GC0308_Y_GAMMA_OUT4 CCI_REG8(0x0c4)
218 #define GC0308_Y_GAMMA_OUT5 CCI_REG8(0x0c5)
219 #define GC0308_Y_GAMMA_OUT6 CCI_REG8(0x0c6)
220 #define GC0308_Y_GAMMA_OUT7 CCI_REG8(0x0c7)
221 #define GC0308_Y_GAMMA_OUT8 CCI_REG8(0x0c8)
222 #define GC0308_Y_GAMMA_OUT9 CCI_REG8(0x0c9)
223 #define GC0308_Y_GAMMA_OUT10 CCI_REG8(0x0ca)
224 #define GC0308_Y_GAMMA_OUT11 CCI_REG8(0x0cb)
225 #define GC0308_Y_GAMMA_OUT12 CCI_REG8(0x0cc)
226
227 /* AEC - Automatic Exposure Control */
228 #define GC0308_AEC_MODE1 CCI_REG8(0x0d0)
229 #define GC0308_AEC_MODE2 CCI_REG8(0x0d1)
230 #define GC0308_AEC_MODE3 CCI_REG8(0x0d2)
231 #define GC0308_AEC_TARGET_Y CCI_REG8(0x0d3)
232 #define GC0308_Y_AVG CCI_REG8(0x0d4)
233 #define GC0308_AEC_HIGH_LOW_RANGE CCI_REG8(0x0d5)
234 #define GC0308_AEC_IGNORE CCI_REG8(0x0d6)
235 #define GC0308_AEC_LIMIT_HIGH_RANGE CCI_REG8(0x0d7)
236 #define GC0308_AEC_R_OFFSET CCI_REG8(0x0d9)
237 #define GC0308_AEC_GB_OFFSET CCI_REG8(0x0da)
238 #define GC0308_AEC_SLOW_MARGIN CCI_REG8(0x0db)
239 #define GC0308_AEC_FAST_MARGIN CCI_REG8(0x0dc)
240 #define GC0308_AEC_EXP_CHANGE_GAIN CCI_REG8(0x0dd)
241 #define GC0308_AEC_STEP2_SUNLIGHT CCI_REG8(0x0de)
242 #define GC0308_AEC_I_FRAMES CCI_REG8(0x0df)
243 #define GC0308_AEC_I_STOP_L_MARGIN CCI_REG8(0x0e0)
244 #define GC0308_AEC_I_STOP_MARGIN CCI_REG8(0x0e1)
245 #define GC0308_ANTI_FLICKER_STEP CCI_REG16(0x0e2)
246 #define GC0308_EXP_LVL_1 CCI_REG16(0x0e4)
247 #define GC0308_EXP_LVL_2 CCI_REG16(0x0e6)
248 #define GC0308_EXP_LVL_3 CCI_REG16(0x0e8)
249 #define GC0308_EXP_LVL_4 CCI_REG16(0x0ea)
250 #define GC0308_MAX_EXP_LVL CCI_REG8(0x0ec)
251 #define GC0308_EXP_MIN_L CCI_REG8(0x0ed)
252 #define GC0308_MAX_POST_DF_GAIN CCI_REG8(0x0ee)
253 #define GC0308_MAX_PRE_DG_GAIN CCI_REG8(0x0ef)
254
255 /* ABS */
256 #define GC0308_ABS_RANGE_COMP CCI_REG8(0x0f0)
257 #define GC0308_ABS_STOP_MARGIN CCI_REG8(0x0f1)
258 #define GC0308_Y_S_COMP CCI_REG8(0x0f2)
259 #define GC0308_Y_STRETCH_LIMIT CCI_REG8(0x0f3)
260 #define GC0308_Y_TILT CCI_REG8(0x0f4)
261 #define GC0308_Y_STRETCH CCI_REG8(0x0f5)
262
263 /* Measure Window */
264 #define GC0308_BIG_WIN_X0 CCI_REG8(0x0f7)
265 #define GC0308_BIG_WIN_Y0 CCI_REG8(0x0f8)
266 #define GC0308_BIG_WIN_X1 CCI_REG8(0x0f9)
267 #define GC0308_BIG_WIN_Y1 CCI_REG8(0x0fa)
268 #define GC0308_DIFF_Y_BIG_THD CCI_REG8(0x0fb)
269
270 /* OUT Module (P1) */
271 #define GC0308_CLOSE_FRAME_EN CCI_REG8(0x150)
272 #define GC0308_CLOSE_FRAME_NUM1 CCI_REG8(0x151)
273 #define GC0308_CLOSE_FRAME_NUM2 CCI_REG8(0x152)
274 #define GC0308_BAYER_MODE CCI_REG8(0x153)
275 #define GC0308_SUBSAMPLE CCI_REG8(0x154)
276 #define GC0308_SUBMODE CCI_REG8(0x155)
277 #define GC0308_SUB_ROW_N1 CCI_REG8(0x156)
278 #define GC0308_SUB_ROW_N2 CCI_REG8(0x157)
279 #define GC0308_SUB_COL_N1 CCI_REG8(0x158)
280 #define GC0308_SUB_COL_N2 CCI_REG8(0x159)
281
282 /* AWB (P1) - Auto White Balance */
283 #define GC0308_AWB_RGB_HIGH_LOW CCI_REG8(0x100)
284 #define GC0308_AWB_Y_TO_C_DIFF2 CCI_REG8(0x102)
285 #define GC0308_AWB_C_MAX CCI_REG8(0x104)
286 #define GC0308_AWB_C_INTER CCI_REG8(0x105)
287 #define GC0308_AWB_C_INTER2 CCI_REG8(0x106)
288 #define GC0308_AWB_C_MAX_BIG CCI_REG8(0x108)
289 #define GC0308_AWB_Y_HIGH CCI_REG8(0x109)
290 #define GC0308_AWB_NUMBER_LIMIT CCI_REG8(0x10a)
291 #define GC0308_KWIN_RATIO CCI_REG8(0x10b)
292 #define GC0308_KWIN_THD CCI_REG8(0x10c)
293 #define GC0308_LIGHT_GAIN_RANGE CCI_REG8(0x10d)
294 #define GC0308_SMALL_WIN_WIDTH_STEP CCI_REG8(0x10e)
295 #define GC0308_SMALL_WIN_HEIGHT_STEP CCI_REG8(0x10f)
296 #define GC0308_AWB_YELLOW_TH CCI_REG8(0x110)
297 #define GC0308_AWB_MODE CCI_REG8(0x111)
298 #define GC0308_AWB_ADJUST_SPEED CCI_REG8(0x112)
299 #define GC0308_AWB_EVERY_N CCI_REG8(0x113)
300 #define GC0308_R_AVG_USE CCI_REG8(0x1d0)
301 #define GC0308_G_AVG_USE CCI_REG8(0x1d1)
302 #define GC0308_B_AVG_USE CCI_REG8(0x1d2)
303
304 #define GC0308_HBLANK_MIN 0x021
305 #define GC0308_HBLANK_MAX 0xfff
306 #define GC0308_HBLANK_DEF 0x040
307
308 #define GC0308_VBLANK_MIN 0x000
309 #define GC0308_VBLANK_MAX 0xfff
310 #define GC0308_VBLANK_DEF 0x020
311
312 #define GC0308_PIXEL_RATE 24000000
313
314 /*
315 * frame_time = (BT + height + 8) * row_time
316 * width = 640 (driver does not change window size)
317 * height = 480 (driver does not change window size)
318 * row_time = HBLANK + SAMPLE_HOLD_DELAY + width + 8 + 4
319 *
320 * When EXP_TIME > (BT + height):
321 * BT = EXP_TIME - height - 8 - VS_START_TIME + VS_END_TIME
322 * else:
323 * BT = VBLANK + VS_START_TIME + VS_END_TIME
324 *
325 * max is 30 FPS
326 *
327 * In my tests frame rate mostly depends on exposure time. Unfortuantely
328 * it's unclear how this is calculated exactly. Also since we enable AEC,
329 * the frame times vary depending on ambient light conditions.
330 */
331 #define GC0308_FRAME_RATE_MAX 30
332
333 enum gc0308_exp_val {
334 GC0308_EXP_M4 = 0,
335 GC0308_EXP_M3,
336 GC0308_EXP_M2,
337 GC0308_EXP_M1,
338 GC0308_EXP_0,
339 GC0308_EXP_P1,
340 GC0308_EXP_P2,
341 GC0308_EXP_P3,
342 GC0308_EXP_P4,
343 };
344
345 static const s64 gc0308_exposure_menu[] = {
346 -4, -3, -2, -1, 0, 1, 2, 3, 4
347 };
348
349 struct gc0308_exposure {
350 u8 luma_offset;
351 u8 aec_target_y;
352 };
353
354 #define GC0308_EXPOSURE(luma_offset_reg, aec_target_y_reg) \
355 { .luma_offset = luma_offset_reg, .aec_target_y = aec_target_y_reg }
356
357 static const struct gc0308_exposure gc0308_exposure_values[] = {
358 [GC0308_EXP_M4] = GC0308_EXPOSURE(0xc0, 0x30),
359 [GC0308_EXP_M3] = GC0308_EXPOSURE(0xd0, 0x38),
360 [GC0308_EXP_M2] = GC0308_EXPOSURE(0xe0, 0x40),
361 [GC0308_EXP_M1] = GC0308_EXPOSURE(0xf0, 0x48),
362 [GC0308_EXP_0] = GC0308_EXPOSURE(0x08, 0x50),
363 [GC0308_EXP_P1] = GC0308_EXPOSURE(0x10, 0x5c),
364 [GC0308_EXP_P2] = GC0308_EXPOSURE(0x20, 0x60),
365 [GC0308_EXP_P3] = GC0308_EXPOSURE(0x30, 0x68),
366 [GC0308_EXP_P4] = GC0308_EXPOSURE(0x40, 0x70),
367 };
368
369 struct gc0308_awb_gains {
370 u8 r;
371 u8 g;
372 u8 b;
373 };
374
375 #define GC0308_AWB_GAINS(red, green, blue) \
376 { .r = red, .g = green, .b = blue }
377
378 static const struct gc0308_awb_gains gc0308_awb_gains[] = {
379 [V4L2_WHITE_BALANCE_AUTO] = GC0308_AWB_GAINS(0x56, 0x40, 0x4a),
380 [V4L2_WHITE_BALANCE_CLOUDY] = GC0308_AWB_GAINS(0x8c, 0x50, 0x40),
381 [V4L2_WHITE_BALANCE_DAYLIGHT] = GC0308_AWB_GAINS(0x74, 0x52, 0x40),
382 [V4L2_WHITE_BALANCE_INCANDESCENT] = GC0308_AWB_GAINS(0x48, 0x40, 0x5c),
383 [V4L2_WHITE_BALANCE_FLUORESCENT] = GC0308_AWB_GAINS(0x40, 0x42, 0x50),
384 };
385
386 struct gc0308_format {
387 u32 code;
388 u8 regval;
389 };
390
391 #define GC0308_FORMAT(v4l2_code, gc0308_regval) \
392 { .code = v4l2_code, .regval = gc0308_regval }
393
394 static const struct gc0308_format gc0308_formats[] = {
395 GC0308_FORMAT(MEDIA_BUS_FMT_UYVY8_2X8, 0x00),
396 GC0308_FORMAT(MEDIA_BUS_FMT_VYUY8_2X8, 0x01),
397 GC0308_FORMAT(MEDIA_BUS_FMT_YUYV8_2X8, 0x02),
398 GC0308_FORMAT(MEDIA_BUS_FMT_YVYU8_2X8, 0x03),
399 GC0308_FORMAT(MEDIA_BUS_FMT_RGB565_2X8_BE, 0x06),
400 GC0308_FORMAT(MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 0x07),
401 GC0308_FORMAT(MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, 0x09),
402 };
403
404 struct gc0308_frame_size {
405 u8 subsample;
406 u32 width;
407 u32 height;
408 };
409
410 #define GC0308_FRAME_SIZE(s, w, h) \
411 { .subsample = s, .width = w, .height = h }
412
413 static const struct gc0308_frame_size gc0308_frame_sizes[] = {
414 GC0308_FRAME_SIZE(0x11, 640, 480),
415 GC0308_FRAME_SIZE(0x22, 320, 240),
416 GC0308_FRAME_SIZE(0x44, 160, 120),
417 };
418
419 struct gc0308_mode_registers {
420 u8 out_format;
421 u8 subsample;
422 u16 width;
423 u16 height;
424 };
425
426 struct gc0308 {
427 struct v4l2_subdev sd;
428 struct v4l2_ctrl_handler hdl;
429 struct media_pad pad;
430 struct device *dev;
431 struct clk *clk;
432 struct regmap *regmap;
433 struct regulator *vdd;
434 struct gpio_desc *pwdn_gpio;
435 struct gpio_desc *reset_gpio;
436 unsigned int mbus_config;
437 struct gc0308_mode_registers mode;
438 struct {
439 /* mirror cluster */
440 struct v4l2_ctrl *hflip;
441 struct v4l2_ctrl *vflip;
442 };
443 struct {
444 /* blanking cluster */
445 struct v4l2_ctrl *hblank;
446 struct v4l2_ctrl *vblank;
447 };
448 };
449
to_gc0308(struct v4l2_subdev * sd)450 static inline struct gc0308 *to_gc0308(struct v4l2_subdev *sd)
451 {
452 return container_of(sd, struct gc0308, sd);
453 }
454
455 static const struct regmap_range_cfg gc0308_ranges[] = {
456 {
457 .range_min = 0x0000,
458 .range_max = 0x01ff,
459 .selector_reg = 0xfe,
460 .selector_mask = 0x01,
461 .selector_shift = 0x00,
462 .window_start = 0x00,
463 .window_len = 0x100,
464 },
465 };
466
467 static const struct regmap_config gc0308_regmap_config = {
468 .reg_bits = 8,
469 .val_bits = 8,
470 .reg_format_endian = REGMAP_ENDIAN_BIG,
471 .max_register = 0x1ff,
472 .ranges = gc0308_ranges,
473 .num_ranges = ARRAY_SIZE(gc0308_ranges),
474 .disable_locking = true,
475 };
476
477 static const struct cci_reg_sequence sensor_default_regs[] = {
478 {GC0308_VB_HB, 0x00},
479 {GC0308_HBLANK, 0x40},
480 {GC0308_VBLANK, 0x20},
481 {GC0308_EXP, 0x0258},
482 {GC0308_AWB_R_GAIN, 0x56},
483 {GC0308_AWB_G_GAIN, 0x40},
484 {GC0308_AWB_B_GAIN, 0x4a},
485 {GC0308_ANTI_FLICKER_STEP, 0x0078},
486 {GC0308_EXP_LVL_1, 0x0258},
487 {GC0308_EXP_LVL_2, 0x0258},
488 {GC0308_EXP_LVL_3, 0x0258},
489 {GC0308_EXP_LVL_4, 0x0ea6},
490 {GC0308_MAX_EXP_LVL, 0x20},
491 {GC0308_ROW_START, 0x0000},
492 {GC0308_COL_START, 0x0000},
493 {GC0308_WIN_HEIGHT, 488},
494 {GC0308_WIN_WIDTH, 648},
495 {GC0308_VS_START_TIME, 0x02},
496 {GC0308_VS_END_TIME, 0x02},
497 {GC0308_RSH_WIDTH, 0x22},
498 {GC0308_TSP_WIDTH, 0x0d},
499 {GC0308_SAMPLE_HOLD_DELAY, 0x50},
500 {GC0308_ROW_TAIL_WIDTH, 0x0f},
501 {GC0308_CISCTL_MODE1, 0x10},
502 {GC0308_CISCTL_MODE2, 0x0a},
503 {GC0308_CISCTL_MODE3, 0x05},
504 {GC0308_CISCTL_MODE4, 0x01},
505 {CCI_REG8(0x018), 0x44}, /* undocumented */
506 {CCI_REG8(0x019), 0x44}, /* undocumented */
507 {GC0308_ANALOG_MODE1, 0x2a},
508 {GC0308_ANALOG_MODE2, 0x00},
509 {GC0308_HRST_RSG_V18, 0x49},
510 {GC0308_VREF_V25, 0x9a},
511 {GC0308_ADC_R, 0x61},
512 {GC0308_PAD_DRV, 0x01}, /* drv strength: pclk=4mA */
513 {GC0308_BLOCK_EN1, 0x7f},
514 {GC0308_BLOCK_EN2, 0xfa},
515 {GC0308_AAAA_EN, 0x57},
516 {GC0308_OUT_FORMAT, 0xa2}, /* YCbYCr */
517 {GC0308_OUT_EN, 0x0f},
518 {GC0308_SYNC_MODE, 0x03},
519 {GC0308_CLK_DIV_MODE, 0x00},
520 {GC0308_DEBUG_MODE1, 0x0a},
521 {GC0308_DEBUG_MODE2, 0x00},
522 {GC0308_DEBUG_MODE3, 0x01},
523 {GC0308_BLK_MODE, 0xf7},
524 {GC0308_BLK_LIMIT_VAL, 0x50},
525 {GC0308_GLOBAL_OFF, 0x00},
526 {GC0308_CURRENT_R_OFF, 0x28},
527 {GC0308_CURRENT_G_OFF, 0x2a},
528 {GC0308_CURRENT_B_OFF, 0x28},
529 {GC0308_EXP_RATE_DARKC, 0x04},
530 {GC0308_OFF_SUBMODE, 0x20},
531 {GC0308_DARKC_SUBMODE, 0x20},
532 {GC0308_MANUAL_G1_OFF, 0x00},
533 {GC0308_MANUAL_R1_OFF, 0x00},
534 {GC0308_MANUAL_B2_OFF, 0x00},
535 {GC0308_MANUAL_G2_OFF, 0x00},
536 {GC0308_GLOBAL_GAIN, 0x14},
537 {GC0308_AUTO_POSTGAIN, 0x41},
538 {GC0308_CHANNEL_GAIN_G1, 0x80},
539 {GC0308_CHANNEL_GAIN_R, 0x80},
540 {GC0308_CHANNEL_GAIN_B, 0x80},
541 {GC0308_CHANNEL_GAIN_G2, 0x80},
542 {GC0308_LSC_RED_B2, 0x20},
543 {GC0308_LSC_GREEN_B2, 0x20},
544 {GC0308_LSC_BLUE_B2, 0x20},
545 {GC0308_LSC_RED_B4, 0x14},
546 {GC0308_LSC_GREEN_B4, 0x10},
547 {GC0308_LSC_BLUE_B4, 0x14},
548 {GC0308_LSC_ROW_CENTER, 0x3c},
549 {GC0308_LSC_COL_CENTER, 0x50},
550 {GC0308_LSC_DEC_LVL1, 0x12},
551 {GC0308_LSC_DEC_LVL2, 0x1a},
552 {GC0308_LSC_DEC_LVL3, 0x24},
553 {GC0308_DN_MODE_EN, 0x07},
554 {GC0308_DN_MODE_RATIO, 0x15},
555 {GC0308_DN_BILAT_B_BASE, 0x08},
556 {GC0308_DN_BILAT_N_BASE, 0x03},
557 {GC0308_DD_DARK_BRIGHT_TH, 0xe8},
558 {GC0308_DD_FLAT_TH, 0x86},
559 {GC0308_DD_LIMIT, 0x82},
560 {GC0308_ASDE_GAIN_TRESH, 0x18},
561 {GC0308_ASDE_GAIN_MODE, 0x0f},
562 {GC0308_ASDE_DN_SLOPE, 0x00},
563 {GC0308_ASDE_DD_BRIGHT, 0x5f},
564 {GC0308_ASDE_DD_LIMIT, 0x8f},
565 {GC0308_ASDE_AUTO_EE1, 0x55},
566 {GC0308_ASDE_AUTO_EE2, 0x38},
567 {GC0308_ASDE_AUTO_SAT_DEC_SLOPE, 0x15},
568 {GC0308_ASDE_AUTO_SAT_LOW_LIMIT, 0x33},
569 {GC0308_EEINTP_MODE_1, 0xdc},
570 {GC0308_EEINTP_MODE_2, 0x00},
571 {GC0308_DIRECTION_TH1, 0x02},
572 {GC0308_DIRECTION_TH2, 0x3f},
573 {GC0308_DIFF_HV_TI_TH, 0x02},
574 {GC0308_EDGE12_EFFECT, 0x38},
575 {GC0308_EDGE_POS_RATIO, 0x88},
576 {GC0308_EDGE1_MINMAX, 0x81},
577 {GC0308_EDGE2_MINMAX, 0x81},
578 {GC0308_EDGE12_TH, 0x22},
579 {GC0308_EDGE_MAX, 0xff},
580 {GC0308_CC_MATRIX_C11, 0x48},
581 {GC0308_CC_MATRIX_C12, 0x02},
582 {GC0308_CC_MATRIX_C13, 0x07},
583 {GC0308_CC_MATRIX_C21, 0xe0},
584 {GC0308_CC_MATRIX_C22, 0x40},
585 {GC0308_CC_MATRIX_C23, 0xf0},
586 {GC0308_SATURATION_CB, 0x40},
587 {GC0308_SATURATION_CR, 0x40},
588 {GC0308_LUMA_CONTRAST, 0x40},
589 {GC0308_SKIN_CB_CENTER, 0xe0},
590 {GC0308_EDGE_DEC_SA, 0x38},
591 {GC0308_AUTO_GRAY_MODE, 0x36},
592 {GC0308_AEC_MODE1, 0xcb},
593 {GC0308_AEC_MODE2, 0x10},
594 {GC0308_AEC_MODE3, 0x90},
595 {GC0308_AEC_TARGET_Y, 0x48},
596 {GC0308_AEC_HIGH_LOW_RANGE, 0xf2},
597 {GC0308_AEC_IGNORE, 0x16},
598 {GC0308_AEC_SLOW_MARGIN, 0x92},
599 {GC0308_AEC_FAST_MARGIN, 0xa5},
600 {GC0308_AEC_I_FRAMES, 0x23},
601 {GC0308_AEC_R_OFFSET, 0x00},
602 {GC0308_AEC_GB_OFFSET, 0x00},
603 {GC0308_AEC_I_STOP_L_MARGIN, 0x09},
604 {GC0308_EXP_MIN_L, 0x04},
605 {GC0308_MAX_POST_DF_GAIN, 0xa0},
606 {GC0308_MAX_PRE_DG_GAIN, 0x40},
607 {GC0308_ABB_MODE, 0x03},
608 {GC0308_GAMMA_OUT0, 0x10},
609 {GC0308_GAMMA_OUT1, 0x20},
610 {GC0308_GAMMA_OUT2, 0x38},
611 {GC0308_GAMMA_OUT3, 0x4e},
612 {GC0308_GAMMA_OUT4, 0x63},
613 {GC0308_GAMMA_OUT5, 0x76},
614 {GC0308_GAMMA_OUT6, 0x87},
615 {GC0308_GAMMA_OUT7, 0xa2},
616 {GC0308_GAMMA_OUT8, 0xb8},
617 {GC0308_GAMMA_OUT9, 0xca},
618 {GC0308_GAMMA_OUT10, 0xd8},
619 {GC0308_GAMMA_OUT11, 0xe3},
620 {GC0308_GAMMA_OUT12, 0xeb},
621 {GC0308_GAMMA_OUT13, 0xf0},
622 {GC0308_GAMMA_OUT14, 0xf8},
623 {GC0308_GAMMA_OUT15, 0xfd},
624 {GC0308_GAMMA_OUT16, 0xff},
625 {GC0308_Y_GAMMA_OUT0, 0x00},
626 {GC0308_Y_GAMMA_OUT1, 0x10},
627 {GC0308_Y_GAMMA_OUT2, 0x1c},
628 {GC0308_Y_GAMMA_OUT3, 0x30},
629 {GC0308_Y_GAMMA_OUT4, 0x43},
630 {GC0308_Y_GAMMA_OUT5, 0x54},
631 {GC0308_Y_GAMMA_OUT6, 0x65},
632 {GC0308_Y_GAMMA_OUT7, 0x75},
633 {GC0308_Y_GAMMA_OUT8, 0x93},
634 {GC0308_Y_GAMMA_OUT9, 0xb0},
635 {GC0308_Y_GAMMA_OUT10, 0xcb},
636 {GC0308_Y_GAMMA_OUT11, 0xe6},
637 {GC0308_Y_GAMMA_OUT12, 0xff},
638 {GC0308_ABS_RANGE_COMP, 0x02},
639 {GC0308_ABS_STOP_MARGIN, 0x01},
640 {GC0308_Y_S_COMP, 0x02},
641 {GC0308_Y_STRETCH_LIMIT, 0x30},
642 {GC0308_BIG_WIN_X0, 0x12},
643 {GC0308_BIG_WIN_Y0, 0x0a},
644 {GC0308_BIG_WIN_X1, 0x9f},
645 {GC0308_BIG_WIN_Y1, 0x78},
646 {GC0308_AWB_RGB_HIGH_LOW, 0xf5},
647 {GC0308_AWB_Y_TO_C_DIFF2, 0x20},
648 {GC0308_AWB_C_MAX, 0x10},
649 {GC0308_AWB_C_INTER, 0x08},
650 {GC0308_AWB_C_INTER2, 0x20},
651 {GC0308_AWB_C_MAX_BIG, 0x0a},
652 {GC0308_AWB_NUMBER_LIMIT, 0xa0},
653 {GC0308_KWIN_RATIO, 0x60},
654 {GC0308_KWIN_THD, 0x08},
655 {GC0308_SMALL_WIN_WIDTH_STEP, 0x44},
656 {GC0308_SMALL_WIN_HEIGHT_STEP, 0x32},
657 {GC0308_AWB_YELLOW_TH, 0x41},
658 {GC0308_AWB_MODE, 0x37},
659 {GC0308_AWB_ADJUST_SPEED, 0x22},
660 {GC0308_AWB_EVERY_N, 0x19},
661 {CCI_REG8(0x114), 0x44}, /* AWB set1 */
662 {CCI_REG8(0x115), 0x44}, /* AWB set1 */
663 {CCI_REG8(0x116), 0xc2}, /* AWB set1 */
664 {CCI_REG8(0x117), 0xa8}, /* AWB set1 */
665 {CCI_REG8(0x118), 0x18}, /* AWB set1 */
666 {CCI_REG8(0x119), 0x50}, /* AWB set1 */
667 {CCI_REG8(0x11a), 0xd8}, /* AWB set1 */
668 {CCI_REG8(0x11b), 0xf5}, /* AWB set1 */
669 {CCI_REG8(0x170), 0x40}, /* AWB set2 */
670 {CCI_REG8(0x171), 0x58}, /* AWB set2 */
671 {CCI_REG8(0x172), 0x30}, /* AWB set2 */
672 {CCI_REG8(0x173), 0x48}, /* AWB set2 */
673 {CCI_REG8(0x174), 0x20}, /* AWB set2 */
674 {CCI_REG8(0x175), 0x60}, /* AWB set2 */
675 {CCI_REG8(0x177), 0x20}, /* AWB set2 */
676 {CCI_REG8(0x178), 0x32}, /* AWB set2 */
677 {CCI_REG8(0x130), 0x03}, /* undocumented */
678 {CCI_REG8(0x131), 0x40}, /* undocumented */
679 {CCI_REG8(0x132), 0x10}, /* undocumented */
680 {CCI_REG8(0x133), 0xe0}, /* undocumented */
681 {CCI_REG8(0x134), 0xe0}, /* undocumented */
682 {CCI_REG8(0x135), 0x00}, /* undocumented */
683 {CCI_REG8(0x136), 0x80}, /* undocumented */
684 {CCI_REG8(0x137), 0x00}, /* undocumented */
685 {CCI_REG8(0x138), 0x04}, /* undocumented */
686 {CCI_REG8(0x139), 0x09}, /* undocumented */
687 {CCI_REG8(0x13a), 0x12}, /* undocumented */
688 {CCI_REG8(0x13b), 0x1c}, /* undocumented */
689 {CCI_REG8(0x13c), 0x28}, /* undocumented */
690 {CCI_REG8(0x13d), 0x31}, /* undocumented */
691 {CCI_REG8(0x13e), 0x44}, /* undocumented */
692 {CCI_REG8(0x13f), 0x57}, /* undocumented */
693 {CCI_REG8(0x140), 0x6c}, /* undocumented */
694 {CCI_REG8(0x141), 0x81}, /* undocumented */
695 {CCI_REG8(0x142), 0x94}, /* undocumented */
696 {CCI_REG8(0x143), 0xa7}, /* undocumented */
697 {CCI_REG8(0x144), 0xb8}, /* undocumented */
698 {CCI_REG8(0x145), 0xd6}, /* undocumented */
699 {CCI_REG8(0x146), 0xee}, /* undocumented */
700 {CCI_REG8(0x147), 0x0d}, /* undocumented */
701 {CCI_REG8(0x162), 0xf7}, /* undocumented */
702 {CCI_REG8(0x163), 0x68}, /* undocumented */
703 {CCI_REG8(0x164), 0xd3}, /* undocumented */
704 {CCI_REG8(0x165), 0xd3}, /* undocumented */
705 {CCI_REG8(0x166), 0x60}, /* undocumented */
706 };
707
708 struct gc0308_colormode {
709 u8 special_effect;
710 u8 dbg_mode1;
711 u8 block_en1;
712 u8 aec_mode3;
713 u8 eeintp_mode_2;
714 u8 edge12_effect;
715 u8 luma_contrast;
716 u8 contrast_center;
717 u8 fixed_cb;
718 u8 fixed_cr;
719 };
720
721 #define GC0308_COLOR_FX(reg_special_effect, reg_dbg_mode1, reg_block_en1, \
722 reg_aec_mode3, reg_eeintp_mode_2, reg_edge12_effect, \
723 reg_luma_contrast, reg_contrast_center, \
724 reg_fixed_cb, reg_fixed_cr) \
725 { \
726 .special_effect = reg_special_effect, \
727 .dbg_mode1 = reg_dbg_mode1, \
728 .block_en1 = reg_block_en1, \
729 .aec_mode3 = reg_aec_mode3, \
730 .eeintp_mode_2 = reg_eeintp_mode_2, \
731 .edge12_effect = reg_edge12_effect, \
732 .luma_contrast = reg_luma_contrast, \
733 .contrast_center = reg_contrast_center, \
734 .fixed_cb = reg_fixed_cb, \
735 .fixed_cr = reg_fixed_cr, \
736 }
737
738 static const struct gc0308_colormode gc0308_colormodes[] = {
739 [V4L2_COLORFX_NONE] =
740 GC0308_COLOR_FX(0x00, 0x0a, 0xff, 0x90, 0x00,
741 0x54, 0x3c, 0x80, 0x00, 0x00),
742 [V4L2_COLORFX_BW] =
743 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
744 0x54, 0x40, 0x80, 0x00, 0x00),
745 [V4L2_COLORFX_SEPIA] =
746 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
747 0x38, 0x40, 0x80, 0xd0, 0x28),
748 [V4L2_COLORFX_NEGATIVE] =
749 GC0308_COLOR_FX(0x01, 0x0a, 0xff, 0x90, 0x00,
750 0x38, 0x40, 0x80, 0x00, 0x00),
751 [V4L2_COLORFX_EMBOSS] =
752 GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,
753 0x38, 0x40, 0x80, 0x00, 0x00),
754 [V4L2_COLORFX_SKETCH] =
755 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x10, 0x80,
756 0x38, 0x80, 0x90, 0x00, 0x00),
757 [V4L2_COLORFX_SKY_BLUE] =
758 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
759 0x38, 0x40, 0x80, 0x50, 0xe0),
760 [V4L2_COLORFX_GRASS_GREEN] =
761 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x01,
762 0x38, 0x40, 0x80, 0xc0, 0xc0),
763 [V4L2_COLORFX_SKIN_WHITEN] =
764 GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,
765 0x38, 0x60, 0x40, 0x00, 0x00),
766 };
767
gc0308_power_on(struct device * dev)768 static int gc0308_power_on(struct device *dev)
769 {
770 struct gc0308 *gc0308 = dev_get_drvdata(dev);
771 int ret;
772
773 ret = regulator_enable(gc0308->vdd);
774 if (ret)
775 return ret;
776
777 ret = clk_prepare_enable(gc0308->clk);
778 if (ret)
779 goto clk_fail;
780
781 gpiod_set_value_cansleep(gc0308->pwdn_gpio, 0);
782 usleep_range(10000, 20000);
783
784 gpiod_set_value_cansleep(gc0308->reset_gpio, 1);
785 usleep_range(10000, 20000);
786 gpiod_set_value_cansleep(gc0308->reset_gpio, 0);
787 msleep(30);
788
789 return 0;
790
791 clk_fail:
792 regulator_disable(gc0308->vdd);
793 return ret;
794 }
795
gc0308_power_off(struct device * dev)796 static int gc0308_power_off(struct device *dev)
797 {
798 struct gc0308 *gc0308 = dev_get_drvdata(dev);
799
800 gpiod_set_value_cansleep(gc0308->pwdn_gpio, 1);
801 clk_disable_unprepare(gc0308->clk);
802 regulator_disable(gc0308->vdd);
803
804 return 0;
805 }
806
807 #ifdef CONFIG_VIDEO_ADV_DEBUG
gc0308_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)808 static int gc0308_g_register(struct v4l2_subdev *sd,
809 struct v4l2_dbg_register *reg)
810 {
811 struct gc0308 *gc0308 = to_gc0308(sd);
812
813 return cci_read(gc0308->regmap, CCI_REG8(reg->reg), ®->val, NULL);
814 }
815
gc0308_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)816 static int gc0308_s_register(struct v4l2_subdev *sd,
817 const struct v4l2_dbg_register *reg)
818 {
819 struct gc0308 *gc0308 = to_gc0308(sd);
820
821 return cci_write(gc0308->regmap, CCI_REG8(reg->reg), reg->val, NULL);
822 }
823 #endif
824
gc0308_set_exposure(struct gc0308 * gc0308,enum gc0308_exp_val exp)825 static int gc0308_set_exposure(struct gc0308 *gc0308, enum gc0308_exp_val exp)
826 {
827 const struct gc0308_exposure *regs = &gc0308_exposure_values[exp];
828 struct cci_reg_sequence exposure_reg_seq[] = {
829 {GC0308_LUMA_OFFSET, regs->luma_offset},
830 {GC0308_AEC_TARGET_Y, regs->aec_target_y},
831 };
832
833 return cci_multi_reg_write(gc0308->regmap, exposure_reg_seq,
834 ARRAY_SIZE(exposure_reg_seq), NULL);
835 }
836
gc0308_set_awb_mode(struct gc0308 * gc0308,enum v4l2_auto_n_preset_white_balance val)837 static int gc0308_set_awb_mode(struct gc0308 *gc0308,
838 enum v4l2_auto_n_preset_white_balance val)
839 {
840 const struct gc0308_awb_gains *regs = &gc0308_awb_gains[val];
841 struct cci_reg_sequence awb_reg_seq[] = {
842 {GC0308_AWB_R_GAIN, regs->r},
843 {GC0308_AWB_G_GAIN, regs->g},
844 {GC0308_AWB_B_GAIN, regs->b},
845 };
846 int ret;
847
848 ret = cci_update_bits(gc0308->regmap, GC0308_AAAA_EN,
849 BIT(1), val == V4L2_WHITE_BALANCE_AUTO, NULL);
850 ret = cci_multi_reg_write(gc0308->regmap, awb_reg_seq,
851 ARRAY_SIZE(awb_reg_seq), &ret);
852
853 return ret;
854 }
855
gc0308_set_colormode(struct gc0308 * gc0308,enum v4l2_colorfx mode)856 static int gc0308_set_colormode(struct gc0308 *gc0308, enum v4l2_colorfx mode)
857 {
858 const struct gc0308_colormode *regs = &gc0308_colormodes[mode];
859 struct cci_reg_sequence colormode_reg_seq[] = {
860 {GC0308_SPECIAL_EFFECT, regs->special_effect},
861 {GC0308_DEBUG_MODE1, regs->dbg_mode1},
862 {GC0308_BLOCK_EN1, regs->block_en1},
863 {GC0308_AEC_MODE3, regs->aec_mode3},
864 {GC0308_EEINTP_MODE_2, regs->eeintp_mode_2},
865 {GC0308_EDGE12_EFFECT, regs->edge12_effect},
866 {GC0308_LUMA_CONTRAST, regs->luma_contrast},
867 {GC0308_CONTRAST_CENTER, regs->contrast_center},
868 {GC0308_FIXED_CB, regs->fixed_cb},
869 {GC0308_FIXED_CR, regs->fixed_cr},
870 };
871
872 return cci_multi_reg_write(gc0308->regmap, colormode_reg_seq,
873 ARRAY_SIZE(colormode_reg_seq), NULL);
874 }
875
gc0308_set_power_line_freq(struct gc0308 * gc0308,int frequency)876 static int gc0308_set_power_line_freq(struct gc0308 *gc0308, int frequency)
877 {
878 static const struct cci_reg_sequence pwr_line_50hz[] = {
879 {GC0308_ANTI_FLICKER_STEP, 0x0078},
880 {GC0308_EXP_LVL_1, 0x0258},
881 {GC0308_EXP_LVL_2, 0x0348},
882 {GC0308_EXP_LVL_3, 0x04b0},
883 {GC0308_EXP_LVL_4, 0x05a0},
884 };
885 static const struct cci_reg_sequence pwr_line_60hz[] = {
886 {GC0308_ANTI_FLICKER_STEP, 0x0064},
887 {GC0308_EXP_LVL_1, 0x0258},
888 {GC0308_EXP_LVL_2, 0x0384},
889 {GC0308_EXP_LVL_3, 0x04b0},
890 {GC0308_EXP_LVL_4, 0x05dc},
891 };
892
893 switch (frequency) {
894 case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
895 return cci_multi_reg_write(gc0308->regmap, pwr_line_60hz,
896 ARRAY_SIZE(pwr_line_60hz), NULL);
897 case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
898 return cci_multi_reg_write(gc0308->regmap, pwr_line_50hz,
899 ARRAY_SIZE(pwr_line_50hz), NULL);
900 }
901
902 return -EINVAL;
903 }
904
gc0308_update_mirror(struct gc0308 * gc0308)905 static int gc0308_update_mirror(struct gc0308 *gc0308)
906 {
907 u8 regval = 0x00;
908
909 if (gc0308->vflip->val)
910 regval |= BIT(1);
911
912 if (gc0308->hflip->val)
913 regval |= BIT(0);
914
915 return cci_update_bits(gc0308->regmap, GC0308_CISCTL_MODE1,
916 GENMASK(1, 0), regval, NULL);
917 }
918
gc0308_update_blanking(struct gc0308 * gc0308)919 static int gc0308_update_blanking(struct gc0308 *gc0308)
920 {
921 u16 vblank = gc0308->vblank->val;
922 u16 hblank = gc0308->hblank->val;
923 u8 vbhb = ((vblank >> 4) & 0xf0) | ((hblank >> 8) & 0x0f);
924 int ret = 0;
925
926 cci_write(gc0308->regmap, GC0308_VB_HB, vbhb, &ret);
927 cci_write(gc0308->regmap, GC0308_HBLANK, hblank & 0xff, &ret);
928 cci_write(gc0308->regmap, GC0308_VBLANK, vblank & 0xff, &ret);
929
930 return ret;
931 }
932
_gc0308_s_ctrl(struct v4l2_ctrl * ctrl)933 static int _gc0308_s_ctrl(struct v4l2_ctrl *ctrl)
934 {
935 struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl);
936 u8 flipval = ctrl->val ? 0xff : 0x00;
937
938 switch (ctrl->id) {
939 case V4L2_CID_HBLANK:
940 case V4L2_CID_VBLANK:
941 return gc0308_update_blanking(gc0308);
942 case V4L2_CID_VFLIP:
943 case V4L2_CID_HFLIP:
944 return gc0308_update_mirror(gc0308);
945 case V4L2_CID_AUTO_WHITE_BALANCE:
946 return cci_update_bits(gc0308->regmap, GC0308_AAAA_EN,
947 BIT(1), flipval, NULL);
948 case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
949 return gc0308_set_awb_mode(gc0308, ctrl->val);
950 case V4L2_CID_POWER_LINE_FREQUENCY:
951 return gc0308_set_power_line_freq(gc0308, ctrl->val);
952 case V4L2_CID_COLORFX:
953 return gc0308_set_colormode(gc0308, ctrl->val);
954 case V4L2_CID_TEST_PATTERN:
955 return cci_update_bits(gc0308->regmap, GC0308_DEBUG_MODE2,
956 GENMASK(1, 0), ctrl->val, NULL);
957 case V4L2_CID_AUTO_EXPOSURE_BIAS:
958 return gc0308_set_exposure(gc0308, ctrl->val);
959 }
960
961 return -EINVAL;
962 }
963
gc0308_s_ctrl(struct v4l2_ctrl * ctrl)964 static int gc0308_s_ctrl(struct v4l2_ctrl *ctrl)
965 {
966 struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl);
967 int ret;
968
969 if (!pm_runtime_get_if_in_use(gc0308->dev))
970 return 0;
971
972 ret = _gc0308_s_ctrl(ctrl);
973 if (ret)
974 dev_err(gc0308->dev, "failed to set control: %d\n", ret);
975
976 pm_runtime_put_autosuspend(gc0308->dev);
977
978 return ret;
979 }
980
981 static const struct v4l2_ctrl_ops gc0308_ctrl_ops = {
982 .s_ctrl = gc0308_s_ctrl,
983 };
984
985 static const struct v4l2_subdev_core_ops gc0308_core_ops = {
986 .log_status = v4l2_ctrl_subdev_log_status,
987 #ifdef CONFIG_VIDEO_ADV_DEBUG
988 .g_register = gc0308_g_register,
989 .s_register = gc0308_s_register,
990 #endif
991 };
992
gc0308_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)993 static int gc0308_enum_mbus_code(struct v4l2_subdev *sd,
994 struct v4l2_subdev_state *sd_state,
995 struct v4l2_subdev_mbus_code_enum *code)
996 {
997 if (code->index >= ARRAY_SIZE(gc0308_formats))
998 return -EINVAL;
999
1000 code->code = gc0308_formats[code->index].code;
1001
1002 return 0;
1003 }
1004
gc0308_get_format_idx(u32 code)1005 static int gc0308_get_format_idx(u32 code)
1006 {
1007 int i;
1008
1009 for (i = 0; i < ARRAY_SIZE(gc0308_formats); i++) {
1010 if (gc0308_formats[i].code == code)
1011 return i;
1012 }
1013
1014 return -1;
1015 }
1016
gc0308_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1017 static int gc0308_enum_frame_size(struct v4l2_subdev *subdev,
1018 struct v4l2_subdev_state *sd_state,
1019 struct v4l2_subdev_frame_size_enum *fse)
1020 {
1021 if (fse->index >= ARRAY_SIZE(gc0308_frame_sizes))
1022 return -EINVAL;
1023
1024 if (gc0308_get_format_idx(fse->code) < 0)
1025 return -EINVAL;
1026
1027 fse->min_width = gc0308_frame_sizes[fse->index].width;
1028 fse->max_width = gc0308_frame_sizes[fse->index].width;
1029 fse->min_height = gc0308_frame_sizes[fse->index].height;
1030 fse->max_height = gc0308_frame_sizes[fse->index].height;
1031
1032 return 0;
1033 }
1034
gc0308_update_pad_format(const struct gc0308_frame_size * mode,struct v4l2_mbus_framefmt * fmt,u32 code)1035 static void gc0308_update_pad_format(const struct gc0308_frame_size *mode,
1036 struct v4l2_mbus_framefmt *fmt, u32 code)
1037 {
1038 fmt->width = mode->width;
1039 fmt->height = mode->height;
1040 fmt->code = code;
1041 fmt->field = V4L2_FIELD_NONE;
1042 fmt->colorspace = V4L2_COLORSPACE_SRGB;
1043 }
1044
gc0308_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1045 static int gc0308_set_format(struct v4l2_subdev *sd,
1046 struct v4l2_subdev_state *sd_state,
1047 struct v4l2_subdev_format *fmt)
1048 {
1049 struct gc0308 *gc0308 = to_gc0308(sd);
1050 const struct gc0308_frame_size *mode;
1051 int i = gc0308_get_format_idx(fmt->format.code);
1052
1053 if (i < 0)
1054 i = 0;
1055
1056 mode = v4l2_find_nearest_size(gc0308_frame_sizes,
1057 ARRAY_SIZE(gc0308_frame_sizes), width,
1058 height, fmt->format.width,
1059 fmt->format.height);
1060
1061 gc0308_update_pad_format(mode, &fmt->format, gc0308_formats[i].code);
1062 *v4l2_subdev_state_get_format(sd_state, 0) = fmt->format;
1063
1064 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1065 return 0;
1066
1067 gc0308->mode.out_format = gc0308_formats[i].regval;
1068 gc0308->mode.subsample = mode->subsample;
1069 gc0308->mode.width = mode->width;
1070 gc0308->mode.height = mode->height;
1071
1072 return 0;
1073 }
1074
gc0308_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)1075 static int gc0308_init_state(struct v4l2_subdev *sd,
1076 struct v4l2_subdev_state *sd_state)
1077 {
1078 struct v4l2_mbus_framefmt *format =
1079 v4l2_subdev_state_get_format(sd_state, 0);
1080
1081 format->width = 640;
1082 format->height = 480;
1083 format->code = gc0308_formats[0].code;
1084 format->colorspace = V4L2_COLORSPACE_SRGB;
1085 format->field = V4L2_FIELD_NONE;
1086 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1087 format->quantization = V4L2_QUANTIZATION_DEFAULT;
1088 format->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1089
1090 return 0;
1091 }
1092
1093 static const struct v4l2_subdev_pad_ops gc0308_pad_ops = {
1094 .enum_mbus_code = gc0308_enum_mbus_code,
1095 .enum_frame_size = gc0308_enum_frame_size,
1096 .get_fmt = v4l2_subdev_get_fmt,
1097 .set_fmt = gc0308_set_format,
1098 };
1099
gc0308_set_resolution(struct gc0308 * gc0308,int * ret)1100 static int gc0308_set_resolution(struct gc0308 *gc0308, int *ret)
1101 {
1102 struct cci_reg_sequence resolution_regs[] = {
1103 {GC0308_SUBSAMPLE, gc0308->mode.subsample},
1104 {GC0308_SUBMODE, 0x03},
1105 {GC0308_SUB_ROW_N1, 0x00},
1106 {GC0308_SUB_ROW_N2, 0x00},
1107 {GC0308_SUB_COL_N1, 0x00},
1108 {GC0308_SUB_COL_N2, 0x00},
1109 {GC0308_CROP_WIN_MODE, 0x80},
1110 {GC0308_CROP_WIN_Y1, 0x00},
1111 {GC0308_CROP_WIN_X1, 0x00},
1112 {GC0308_CROP_WIN_HEIGHT, gc0308->mode.height},
1113 {GC0308_CROP_WIN_WIDTH, gc0308->mode.width},
1114 };
1115
1116 return cci_multi_reg_write(gc0308->regmap, resolution_regs,
1117 ARRAY_SIZE(resolution_regs), ret);
1118 }
1119
gc0308_start_stream(struct gc0308 * gc0308)1120 static int gc0308_start_stream(struct gc0308 *gc0308)
1121 {
1122 int ret, sync_mode;
1123
1124 ret = pm_runtime_resume_and_get(gc0308->dev);
1125 if (ret < 0)
1126 return ret;
1127
1128 cci_multi_reg_write(gc0308->regmap, sensor_default_regs,
1129 ARRAY_SIZE(sensor_default_regs), &ret);
1130 cci_update_bits(gc0308->regmap, GC0308_OUT_FORMAT,
1131 GENMASK(4, 0), gc0308->mode.out_format, &ret);
1132 gc0308_set_resolution(gc0308, &ret);
1133
1134 if (ret) {
1135 dev_err(gc0308->dev, "failed to update registers: %d\n", ret);
1136 goto disable_pm;
1137 }
1138
1139 ret = __v4l2_ctrl_handler_setup(&gc0308->hdl);
1140 if (ret) {
1141 dev_err(gc0308->dev, "failed to setup controls\n");
1142 goto disable_pm;
1143 }
1144
1145 /* HSYNC/VSYNC polarity */
1146 sync_mode = 0x3;
1147 if (gc0308->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1148 sync_mode &= ~BIT(0);
1149 if (gc0308->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1150 sync_mode &= ~BIT(1);
1151 ret = cci_write(gc0308->regmap, GC0308_SYNC_MODE, sync_mode, NULL);
1152 if (ret)
1153 goto disable_pm;
1154
1155 return 0;
1156
1157 disable_pm:
1158 pm_runtime_put_autosuspend(gc0308->dev);
1159 return ret;
1160 }
1161
gc0308_stop_stream(struct gc0308 * gc0308)1162 static int gc0308_stop_stream(struct gc0308 *gc0308)
1163 {
1164 pm_runtime_put_autosuspend(gc0308->dev);
1165 return 0;
1166 }
1167
gc0308_s_stream(struct v4l2_subdev * sd,int enable)1168 static int gc0308_s_stream(struct v4l2_subdev *sd, int enable)
1169 {
1170 struct gc0308 *gc0308 = to_gc0308(sd);
1171 struct v4l2_subdev_state *sd_state;
1172 int ret;
1173
1174 sd_state = v4l2_subdev_lock_and_get_active_state(sd);
1175
1176 if (enable)
1177 ret = gc0308_start_stream(gc0308);
1178 else
1179 ret = gc0308_stop_stream(gc0308);
1180
1181 v4l2_subdev_unlock_state(sd_state);
1182 return ret;
1183 }
1184
1185 static const struct v4l2_subdev_video_ops gc0308_video_ops = {
1186 .s_stream = gc0308_s_stream,
1187 };
1188
1189 static const struct v4l2_subdev_ops gc0308_subdev_ops = {
1190 .core = &gc0308_core_ops,
1191 .pad = &gc0308_pad_ops,
1192 .video = &gc0308_video_ops,
1193 };
1194
1195 static const struct v4l2_subdev_internal_ops gc0308_internal_ops = {
1196 .init_state = gc0308_init_state,
1197 };
1198
gc0308_bus_config(struct gc0308 * gc0308)1199 static int gc0308_bus_config(struct gc0308 *gc0308)
1200 {
1201 struct device *dev = gc0308->dev;
1202 struct v4l2_fwnode_endpoint bus_cfg = {
1203 .bus_type = V4L2_MBUS_PARALLEL
1204 };
1205 struct fwnode_handle *ep;
1206 int ret;
1207
1208 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);
1209 if (!ep)
1210 return -EINVAL;
1211
1212 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1213 fwnode_handle_put(ep);
1214 if (ret)
1215 return ret;
1216
1217 gc0308->mbus_config = bus_cfg.bus.parallel.flags;
1218
1219 return 0;
1220 }
1221
1222 static const char * const gc0308_test_pattern_menu[] = {
1223 "Disabled",
1224 "Test Image 1",
1225 "Test Image 2",
1226 };
1227
gc0308_init_controls(struct gc0308 * gc0308)1228 static int gc0308_init_controls(struct gc0308 *gc0308)
1229 {
1230 int ret;
1231
1232 v4l2_ctrl_handler_init(&gc0308->hdl, 11);
1233 gc0308->hblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1234 V4L2_CID_HBLANK, GC0308_HBLANK_MIN,
1235 GC0308_HBLANK_MAX, 1,
1236 GC0308_HBLANK_DEF);
1237 gc0308->vblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1238 V4L2_CID_VBLANK, GC0308_VBLANK_MIN,
1239 GC0308_VBLANK_MAX, 1,
1240 GC0308_VBLANK_DEF);
1241 gc0308->hflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1242 V4L2_CID_HFLIP, 0, 1, 1, 0);
1243 gc0308->vflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1244 V4L2_CID_VFLIP, 0, 1, 1, 0);
1245 v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, V4L2_CID_PIXEL_RATE,
1246 GC0308_PIXEL_RATE, GC0308_PIXEL_RATE, 1,
1247 GC0308_PIXEL_RATE);
1248 v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1249 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1250 v4l2_ctrl_new_std_menu_items(&gc0308->hdl, &gc0308_ctrl_ops,
1251 V4L2_CID_TEST_PATTERN,
1252 ARRAY_SIZE(gc0308_test_pattern_menu) - 1,
1253 0, 0, gc0308_test_pattern_menu);
1254 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1255 V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
1256 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
1257 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1258 V4L2_CID_COLORFX, 8, 0, V4L2_COLORFX_NONE);
1259 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1260 V4L2_CID_POWER_LINE_FREQUENCY,
1261 V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
1262 ~0x6, V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
1263 v4l2_ctrl_new_int_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1264 V4L2_CID_AUTO_EXPOSURE_BIAS,
1265 ARRAY_SIZE(gc0308_exposure_menu) - 1,
1266 ARRAY_SIZE(gc0308_exposure_menu) / 2,
1267 gc0308_exposure_menu);
1268
1269 gc0308->sd.ctrl_handler = &gc0308->hdl;
1270 if (gc0308->hdl.error) {
1271 ret = gc0308->hdl.error;
1272 v4l2_ctrl_handler_free(&gc0308->hdl);
1273 return ret;
1274 }
1275
1276 v4l2_ctrl_cluster(2, &gc0308->hflip);
1277 v4l2_ctrl_cluster(2, &gc0308->hblank);
1278
1279 return 0;
1280 }
1281
gc0308_probe(struct i2c_client * client)1282 static int gc0308_probe(struct i2c_client *client)
1283 {
1284 struct device *dev = &client->dev;
1285 struct gc0308 *gc0308;
1286 unsigned long clkrate;
1287 u64 regval;
1288 int ret;
1289
1290 gc0308 = devm_kzalloc(dev, sizeof(*gc0308), GFP_KERNEL);
1291 if (!gc0308)
1292 return -ENOMEM;
1293
1294 gc0308->dev = dev;
1295 dev_set_drvdata(dev, gc0308);
1296
1297 ret = gc0308_bus_config(gc0308);
1298 if (ret)
1299 return dev_err_probe(dev, ret, "failed to get bus config\n");
1300
1301 gc0308->clk = devm_clk_get_optional(dev, NULL);
1302 if (IS_ERR(gc0308->clk))
1303 return dev_err_probe(dev, PTR_ERR(gc0308->clk),
1304 "could not get clk\n");
1305
1306 gc0308->vdd = devm_regulator_get(dev, "vdd28");
1307 if (IS_ERR(gc0308->vdd))
1308 return dev_err_probe(dev, PTR_ERR(gc0308->vdd),
1309 "failed to get vdd28 regulator\n");
1310
1311 gc0308->pwdn_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_LOW);
1312 if (IS_ERR(gc0308->pwdn_gpio))
1313 return dev_err_probe(dev, PTR_ERR(gc0308->pwdn_gpio),
1314 "failed to get powerdown gpio\n");
1315
1316 gc0308->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1317 if (IS_ERR(gc0308->reset_gpio))
1318 return dev_err_probe(dev, PTR_ERR(gc0308->reset_gpio),
1319 "failed to get reset gpio\n");
1320
1321 /*
1322 * This is not using devm_cci_regmap_init_i2c(), because the driver
1323 * makes use of regmap's pagination feature. The chosen settings are
1324 * compatible with the CCI helpers.
1325 */
1326 gc0308->regmap = devm_regmap_init_i2c(client, &gc0308_regmap_config);
1327 if (IS_ERR(gc0308->regmap))
1328 return dev_err_probe(dev, PTR_ERR(gc0308->regmap),
1329 "failed to init regmap\n");
1330
1331 v4l2_i2c_subdev_init(&gc0308->sd, client, &gc0308_subdev_ops);
1332 gc0308->sd.internal_ops = &gc0308_internal_ops;
1333 gc0308->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1334
1335 ret = gc0308_init_controls(gc0308);
1336 if (ret)
1337 return dev_err_probe(dev, ret, "failed to init controls\n");
1338
1339 gc0308->sd.state_lock = gc0308->hdl.lock;
1340 gc0308->pad.flags = MEDIA_PAD_FL_SOURCE;
1341 gc0308->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1342 ret = media_entity_pads_init(&gc0308->sd.entity, 1, &gc0308->pad);
1343 if (ret < 0)
1344 goto fail_ctrl_hdl_cleanup;
1345
1346 ret = v4l2_subdev_init_finalize(&gc0308->sd);
1347 if (ret)
1348 goto fail_media_entity_cleanup;
1349
1350 ret = gc0308_power_on(dev);
1351 if (ret)
1352 goto fail_subdev_cleanup;
1353
1354 if (gc0308->clk) {
1355 clkrate = clk_get_rate(gc0308->clk);
1356 if (clkrate != 24000000)
1357 dev_warn(dev, "unexpected clock rate: %lu\n", clkrate);
1358 }
1359
1360 ret = cci_read(gc0308->regmap, GC0308_CHIP_ID, ®val, NULL);
1361 if (ret < 0) {
1362 dev_err_probe(dev, ret, "failed to read chip ID\n");
1363 goto fail_power_off;
1364 }
1365
1366 if (regval != 0x9b) {
1367 ret = -EINVAL;
1368 dev_err_probe(dev, ret, "invalid chip ID (%02llx)\n", regval);
1369 goto fail_power_off;
1370 }
1371
1372 /*
1373 * Enable runtime PM with autosuspend. As the device has been powered
1374 * manually, mark it as active, and increase the usage count without
1375 * resuming the device.
1376 */
1377 pm_runtime_set_active(dev);
1378 pm_runtime_get_noresume(dev);
1379 pm_runtime_enable(dev);
1380 pm_runtime_set_autosuspend_delay(dev, 1000);
1381 pm_runtime_use_autosuspend(dev);
1382
1383 ret = v4l2_async_register_subdev(&gc0308->sd);
1384 if (ret) {
1385 dev_err_probe(dev, ret, "failed to register v4l subdev\n");
1386 goto fail_rpm;
1387 }
1388
1389 return 0;
1390
1391 fail_rpm:
1392 pm_runtime_disable(dev);
1393 pm_runtime_put_noidle(dev);
1394 fail_power_off:
1395 gc0308_power_off(dev);
1396 fail_subdev_cleanup:
1397 v4l2_subdev_cleanup(&gc0308->sd);
1398 fail_media_entity_cleanup:
1399 media_entity_cleanup(&gc0308->sd.entity);
1400 fail_ctrl_hdl_cleanup:
1401 v4l2_ctrl_handler_free(&gc0308->hdl);
1402 return ret;
1403 }
1404
gc0308_remove(struct i2c_client * client)1405 static void gc0308_remove(struct i2c_client *client)
1406 {
1407 struct gc0308 *gc0308 = i2c_get_clientdata(client);
1408 struct device *dev = &client->dev;
1409
1410 v4l2_async_unregister_subdev(&gc0308->sd);
1411 v4l2_ctrl_handler_free(&gc0308->hdl);
1412 media_entity_cleanup(&gc0308->sd.entity);
1413
1414 pm_runtime_disable(dev);
1415 if (!pm_runtime_status_suspended(dev))
1416 gc0308_power_off(dev);
1417 pm_runtime_set_suspended(dev);
1418 }
1419
1420 static const struct dev_pm_ops gc0308_pm_ops = {
1421 SET_RUNTIME_PM_OPS(gc0308_power_off, gc0308_power_on, NULL)
1422 };
1423
1424 static const struct of_device_id gc0308_of_match[] = {
1425 { .compatible = "galaxycore,gc0308" },
1426 { /* sentinel */ }
1427 };
1428 MODULE_DEVICE_TABLE(of, gc0308_of_match);
1429
1430 static struct i2c_driver gc0308_i2c_driver = {
1431 .driver = {
1432 .name = "gc0308",
1433 .pm = &gc0308_pm_ops,
1434 .of_match_table = gc0308_of_match,
1435 },
1436 .probe = gc0308_probe,
1437 .remove = gc0308_remove,
1438 };
1439 module_i2c_driver(gc0308_i2c_driver);
1440
1441 MODULE_DESCRIPTION("GalaxyCore GC0308 Camera Driver");
1442 MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
1443 MODULE_LICENSE("GPL");
1444