1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Azoteq IQS7222A/B/C/D Capacitive Touch Controller
4 *
5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
6 */
7
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/input.h>
15 #include <linux/input/touchscreen.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/ktime.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/slab.h>
22 #include <linux/unaligned.h>
23
24 #define IQS7222_PROD_NUM 0x00
25 #define IQS7222_PROD_NUM_A 840
26 #define IQS7222_PROD_NUM_B 698
27 #define IQS7222_PROD_NUM_C 863
28 #define IQS7222_PROD_NUM_D 1046
29
30 #define IQS7222_SYS_STATUS 0x10
31 #define IQS7222_SYS_STATUS_RESET BIT(3)
32 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
33 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
34
35 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
36 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
37 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
38 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
39
40 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
41 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
42 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
43 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
44
45 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
46
47 #define IQS7222_SYS_SETUP 0xD0
48 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
49 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
50 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
51 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
52 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
53 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
54 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
55
56 #define IQS7222_EVENT_MASK_ATI BIT(12)
57 #define IQS7222_EVENT_MASK_SLDR BIT(10)
58 #define IQS7222_EVENT_MASK_TPAD IQS7222_EVENT_MASK_SLDR
59 #define IQS7222_EVENT_MASK_TOUCH BIT(1)
60 #define IQS7222_EVENT_MASK_PROX BIT(0)
61
62 #define IQS7222_COMMS_HOLD BIT(0)
63 #define IQS7222_COMMS_ERROR 0xEEEE
64 #define IQS7222_COMMS_RETRY_MS 50
65 #define IQS7222_COMMS_TIMEOUT_MS 100
66 #define IQS7222_RESET_TIMEOUT_MS 250
67 #define IQS7222_ATI_TIMEOUT_MS 2000
68
69 #define IQS7222_MAX_COLS_STAT 8
70 #define IQS7222_MAX_COLS_CYCLE 3
71 #define IQS7222_MAX_COLS_GLBL 3
72 #define IQS7222_MAX_COLS_BTN 3
73 #define IQS7222_MAX_COLS_CHAN 6
74 #define IQS7222_MAX_COLS_FILT 2
75 #define IQS7222_MAX_COLS_SLDR 11
76 #define IQS7222_MAX_COLS_TPAD 24
77 #define IQS7222_MAX_COLS_GPIO 3
78 #define IQS7222_MAX_COLS_SYS 13
79
80 #define IQS7222_MAX_CHAN 20
81 #define IQS7222_MAX_SLDR 2
82
83 #define IQS7222_NUM_RETRIES 5
84 #define IQS7222_REG_OFFSET 0x100
85
86 enum iqs7222_reg_key_id {
87 IQS7222_REG_KEY_NONE,
88 IQS7222_REG_KEY_PROX,
89 IQS7222_REG_KEY_TOUCH,
90 IQS7222_REG_KEY_DEBOUNCE,
91 IQS7222_REG_KEY_TAP,
92 IQS7222_REG_KEY_TAP_LEGACY,
93 IQS7222_REG_KEY_AXIAL,
94 IQS7222_REG_KEY_AXIAL_LEGACY,
95 IQS7222_REG_KEY_WHEEL,
96 IQS7222_REG_KEY_NO_WHEEL,
97 IQS7222_REG_KEY_RESERVED
98 };
99
100 enum iqs7222_reg_grp_id {
101 IQS7222_REG_GRP_STAT,
102 IQS7222_REG_GRP_CYCLE,
103 IQS7222_REG_GRP_GLBL,
104 IQS7222_REG_GRP_BTN,
105 IQS7222_REG_GRP_CHAN,
106 IQS7222_REG_GRP_FILT,
107 IQS7222_REG_GRP_SLDR,
108 IQS7222_REG_GRP_TPAD,
109 IQS7222_REG_GRP_GPIO,
110 IQS7222_REG_GRP_SYS,
111 IQS7222_NUM_REG_GRPS
112 };
113
114 static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = {
115 [IQS7222_REG_GRP_CYCLE] = "cycle-%d",
116 [IQS7222_REG_GRP_CHAN] = "channel-%d",
117 [IQS7222_REG_GRP_SLDR] = "slider-%d",
118 [IQS7222_REG_GRP_TPAD] = "trackpad",
119 [IQS7222_REG_GRP_GPIO] = "gpio-%d",
120 };
121
122 static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = {
123 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
124 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
125 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
126 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
127 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
128 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
129 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
130 [IQS7222_REG_GRP_TPAD] = IQS7222_MAX_COLS_TPAD,
131 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
132 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
133 };
134
135 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
136
137 struct iqs7222_event_desc {
138 const char *name;
139 u16 link;
140 u16 mask;
141 u16 val;
142 u16 strict;
143 u16 enable;
144 enum iqs7222_reg_key_id reg_key;
145 };
146
147 static const struct iqs7222_event_desc iqs7222_kp_events[] = {
148 {
149 .name = "event-prox",
150 .enable = IQS7222_EVENT_MASK_PROX,
151 .reg_key = IQS7222_REG_KEY_PROX,
152 },
153 {
154 .name = "event-touch",
155 .enable = IQS7222_EVENT_MASK_TOUCH,
156 .reg_key = IQS7222_REG_KEY_TOUCH,
157 },
158 };
159
160 static const struct iqs7222_event_desc iqs7222_sl_events[] = {
161 { .name = "event-press", },
162 {
163 .name = "event-tap",
164 .mask = BIT(0),
165 .val = BIT(0),
166 .enable = BIT(0),
167 .reg_key = IQS7222_REG_KEY_TAP,
168 },
169 {
170 .name = "event-swipe-pos",
171 .mask = BIT(5) | BIT(1),
172 .val = BIT(1),
173 .enable = BIT(1),
174 .reg_key = IQS7222_REG_KEY_AXIAL,
175 },
176 {
177 .name = "event-swipe-neg",
178 .mask = BIT(5) | BIT(1),
179 .val = BIT(5) | BIT(1),
180 .enable = BIT(1),
181 .reg_key = IQS7222_REG_KEY_AXIAL,
182 },
183 {
184 .name = "event-flick-pos",
185 .mask = BIT(5) | BIT(2),
186 .val = BIT(2),
187 .enable = BIT(2),
188 .reg_key = IQS7222_REG_KEY_AXIAL,
189 },
190 {
191 .name = "event-flick-neg",
192 .mask = BIT(5) | BIT(2),
193 .val = BIT(5) | BIT(2),
194 .enable = BIT(2),
195 .reg_key = IQS7222_REG_KEY_AXIAL,
196 },
197 };
198
199 static const struct iqs7222_event_desc iqs7222_tp_events[] = {
200 {
201 .name = "event-press",
202 .link = BIT(7),
203 },
204 {
205 .name = "event-tap",
206 .link = BIT(0),
207 .mask = BIT(0),
208 .val = BIT(0),
209 .enable = BIT(0),
210 .reg_key = IQS7222_REG_KEY_TAP,
211 },
212 {
213 .name = "event-swipe-x-pos",
214 .link = BIT(2),
215 .mask = BIT(2) | BIT(1),
216 .val = BIT(2),
217 .strict = BIT(4),
218 .enable = BIT(1),
219 .reg_key = IQS7222_REG_KEY_AXIAL,
220 },
221 {
222 .name = "event-swipe-y-pos",
223 .link = BIT(3),
224 .mask = BIT(3) | BIT(1),
225 .val = BIT(3),
226 .strict = BIT(3),
227 .enable = BIT(1),
228 .reg_key = IQS7222_REG_KEY_AXIAL,
229 },
230 {
231 .name = "event-swipe-x-neg",
232 .link = BIT(4),
233 .mask = BIT(4) | BIT(1),
234 .val = BIT(4),
235 .strict = BIT(4),
236 .enable = BIT(1),
237 .reg_key = IQS7222_REG_KEY_AXIAL,
238 },
239 {
240 .name = "event-swipe-y-neg",
241 .link = BIT(5),
242 .mask = BIT(5) | BIT(1),
243 .val = BIT(5),
244 .strict = BIT(3),
245 .enable = BIT(1),
246 .reg_key = IQS7222_REG_KEY_AXIAL,
247 },
248 {
249 .name = "event-flick-x-pos",
250 .link = BIT(2),
251 .mask = BIT(2) | BIT(1),
252 .val = BIT(2) | BIT(1),
253 .strict = BIT(4),
254 .enable = BIT(2),
255 .reg_key = IQS7222_REG_KEY_AXIAL,
256 },
257 {
258 .name = "event-flick-y-pos",
259 .link = BIT(3),
260 .mask = BIT(3) | BIT(1),
261 .val = BIT(3) | BIT(1),
262 .strict = BIT(3),
263 .enable = BIT(2),
264 .reg_key = IQS7222_REG_KEY_AXIAL,
265 },
266 {
267 .name = "event-flick-x-neg",
268 .link = BIT(4),
269 .mask = BIT(4) | BIT(1),
270 .val = BIT(4) | BIT(1),
271 .strict = BIT(4),
272 .enable = BIT(2),
273 .reg_key = IQS7222_REG_KEY_AXIAL,
274 },
275 {
276 .name = "event-flick-y-neg",
277 .link = BIT(5),
278 .mask = BIT(5) | BIT(1),
279 .val = BIT(5) | BIT(1),
280 .strict = BIT(3),
281 .enable = BIT(2),
282 .reg_key = IQS7222_REG_KEY_AXIAL,
283 },
284 };
285
286 struct iqs7222_reg_grp_desc {
287 u16 base;
288 u16 val_len;
289 int num_row;
290 int num_col;
291 };
292
293 struct iqs7222_dev_desc {
294 u16 prod_num;
295 u16 fw_major;
296 u16 fw_minor;
297 u16 sldr_res;
298 u16 touch_link;
299 u16 wheel_enable;
300 int allow_offset;
301 int event_offset;
302 int comms_offset;
303 int ext_chan;
304 bool legacy_gesture;
305 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
306 };
307
308 static const struct iqs7222_dev_desc iqs7222_devs[] = {
309 {
310 .prod_num = IQS7222_PROD_NUM_A,
311 .fw_major = 1,
312 .fw_minor = 13,
313 .sldr_res = U8_MAX * 16,
314 .touch_link = 1768,
315 .allow_offset = 9,
316 .event_offset = 10,
317 .comms_offset = 12,
318 .ext_chan = 10,
319 .reg_grps = {
320 [IQS7222_REG_GRP_STAT] = {
321 .base = IQS7222_SYS_STATUS,
322 .num_row = 1,
323 .num_col = 8,
324 },
325 [IQS7222_REG_GRP_CYCLE] = {
326 .base = 0x8000,
327 .num_row = 7,
328 .num_col = 3,
329 },
330 [IQS7222_REG_GRP_GLBL] = {
331 .base = 0x8700,
332 .num_row = 1,
333 .num_col = 3,
334 },
335 [IQS7222_REG_GRP_BTN] = {
336 .base = 0x9000,
337 .num_row = 12,
338 .num_col = 3,
339 },
340 [IQS7222_REG_GRP_CHAN] = {
341 .base = 0xA000,
342 .num_row = 12,
343 .num_col = 6,
344 },
345 [IQS7222_REG_GRP_FILT] = {
346 .base = 0xAC00,
347 .val_len = 3,
348 .num_row = 1,
349 .num_col = 2,
350 },
351 [IQS7222_REG_GRP_SLDR] = {
352 .base = 0xB000,
353 .num_row = 2,
354 .num_col = 11,
355 },
356 [IQS7222_REG_GRP_GPIO] = {
357 .base = 0xC000,
358 .num_row = 1,
359 .num_col = 3,
360 },
361 [IQS7222_REG_GRP_SYS] = {
362 .base = IQS7222_SYS_SETUP,
363 .num_row = 1,
364 .num_col = 13,
365 },
366 },
367 },
368 {
369 .prod_num = IQS7222_PROD_NUM_A,
370 .fw_major = 1,
371 .fw_minor = 12,
372 .sldr_res = U8_MAX * 16,
373 .touch_link = 1768,
374 .allow_offset = 9,
375 .event_offset = 10,
376 .comms_offset = 12,
377 .ext_chan = 10,
378 .legacy_gesture = true,
379 .reg_grps = {
380 [IQS7222_REG_GRP_STAT] = {
381 .base = IQS7222_SYS_STATUS,
382 .num_row = 1,
383 .num_col = 8,
384 },
385 [IQS7222_REG_GRP_CYCLE] = {
386 .base = 0x8000,
387 .num_row = 7,
388 .num_col = 3,
389 },
390 [IQS7222_REG_GRP_GLBL] = {
391 .base = 0x8700,
392 .num_row = 1,
393 .num_col = 3,
394 },
395 [IQS7222_REG_GRP_BTN] = {
396 .base = 0x9000,
397 .num_row = 12,
398 .num_col = 3,
399 },
400 [IQS7222_REG_GRP_CHAN] = {
401 .base = 0xA000,
402 .num_row = 12,
403 .num_col = 6,
404 },
405 [IQS7222_REG_GRP_FILT] = {
406 .base = 0xAC00,
407 .val_len = 3,
408 .num_row = 1,
409 .num_col = 2,
410 },
411 [IQS7222_REG_GRP_SLDR] = {
412 .base = 0xB000,
413 .num_row = 2,
414 .num_col = 11,
415 },
416 [IQS7222_REG_GRP_GPIO] = {
417 .base = 0xC000,
418 .num_row = 1,
419 .num_col = 3,
420 },
421 [IQS7222_REG_GRP_SYS] = {
422 .base = IQS7222_SYS_SETUP,
423 .num_row = 1,
424 .num_col = 13,
425 },
426 },
427 },
428 {
429 .prod_num = IQS7222_PROD_NUM_B,
430 .fw_major = 1,
431 .fw_minor = 43,
432 .event_offset = 10,
433 .comms_offset = 11,
434 .reg_grps = {
435 [IQS7222_REG_GRP_STAT] = {
436 .base = IQS7222_SYS_STATUS,
437 .num_row = 1,
438 .num_col = 6,
439 },
440 [IQS7222_REG_GRP_CYCLE] = {
441 .base = 0x8000,
442 .num_row = 10,
443 .num_col = 2,
444 },
445 [IQS7222_REG_GRP_GLBL] = {
446 .base = 0x8A00,
447 .num_row = 1,
448 .num_col = 3,
449 },
450 [IQS7222_REG_GRP_BTN] = {
451 .base = 0x9000,
452 .num_row = 20,
453 .num_col = 2,
454 },
455 [IQS7222_REG_GRP_CHAN] = {
456 .base = 0xB000,
457 .num_row = 20,
458 .num_col = 4,
459 },
460 [IQS7222_REG_GRP_FILT] = {
461 .base = 0xC400,
462 .val_len = 3,
463 .num_row = 1,
464 .num_col = 2,
465 },
466 [IQS7222_REG_GRP_SYS] = {
467 .base = IQS7222_SYS_SETUP,
468 .num_row = 1,
469 .num_col = 13,
470 },
471 },
472 },
473 {
474 .prod_num = IQS7222_PROD_NUM_B,
475 .fw_major = 1,
476 .fw_minor = 27,
477 .reg_grps = {
478 [IQS7222_REG_GRP_STAT] = {
479 .base = IQS7222_SYS_STATUS,
480 .num_row = 1,
481 .num_col = 6,
482 },
483 [IQS7222_REG_GRP_CYCLE] = {
484 .base = 0x8000,
485 .num_row = 10,
486 .num_col = 2,
487 },
488 [IQS7222_REG_GRP_GLBL] = {
489 .base = 0x8A00,
490 .num_row = 1,
491 .num_col = 3,
492 },
493 [IQS7222_REG_GRP_BTN] = {
494 .base = 0x9000,
495 .num_row = 20,
496 .num_col = 2,
497 },
498 [IQS7222_REG_GRP_CHAN] = {
499 .base = 0xB000,
500 .num_row = 20,
501 .num_col = 4,
502 },
503 [IQS7222_REG_GRP_FILT] = {
504 .base = 0xC400,
505 .val_len = 3,
506 .num_row = 1,
507 .num_col = 2,
508 },
509 [IQS7222_REG_GRP_SYS] = {
510 .base = IQS7222_SYS_SETUP,
511 .num_row = 1,
512 .num_col = 10,
513 },
514 },
515 },
516 {
517 .prod_num = IQS7222_PROD_NUM_C,
518 .fw_major = 2,
519 .fw_minor = 6,
520 .sldr_res = U16_MAX,
521 .touch_link = 1686,
522 .wheel_enable = BIT(3),
523 .event_offset = 9,
524 .comms_offset = 10,
525 .reg_grps = {
526 [IQS7222_REG_GRP_STAT] = {
527 .base = IQS7222_SYS_STATUS,
528 .num_row = 1,
529 .num_col = 6,
530 },
531 [IQS7222_REG_GRP_CYCLE] = {
532 .base = 0x8000,
533 .num_row = 5,
534 .num_col = 3,
535 },
536 [IQS7222_REG_GRP_GLBL] = {
537 .base = 0x8500,
538 .num_row = 1,
539 .num_col = 3,
540 },
541 [IQS7222_REG_GRP_BTN] = {
542 .base = 0x9000,
543 .num_row = 10,
544 .num_col = 3,
545 },
546 [IQS7222_REG_GRP_CHAN] = {
547 .base = 0xA000,
548 .num_row = 10,
549 .num_col = 6,
550 },
551 [IQS7222_REG_GRP_FILT] = {
552 .base = 0xAA00,
553 .val_len = 3,
554 .num_row = 1,
555 .num_col = 2,
556 },
557 [IQS7222_REG_GRP_SLDR] = {
558 .base = 0xB000,
559 .num_row = 2,
560 .num_col = 10,
561 },
562 [IQS7222_REG_GRP_GPIO] = {
563 .base = 0xC000,
564 .num_row = 3,
565 .num_col = 3,
566 },
567 [IQS7222_REG_GRP_SYS] = {
568 .base = IQS7222_SYS_SETUP,
569 .num_row = 1,
570 .num_col = 12,
571 },
572 },
573 },
574 {
575 .prod_num = IQS7222_PROD_NUM_C,
576 .fw_major = 1,
577 .fw_minor = 13,
578 .sldr_res = U16_MAX,
579 .touch_link = 1674,
580 .wheel_enable = BIT(3),
581 .event_offset = 9,
582 .comms_offset = 10,
583 .reg_grps = {
584 [IQS7222_REG_GRP_STAT] = {
585 .base = IQS7222_SYS_STATUS,
586 .num_row = 1,
587 .num_col = 6,
588 },
589 [IQS7222_REG_GRP_CYCLE] = {
590 .base = 0x8000,
591 .num_row = 5,
592 .num_col = 3,
593 },
594 [IQS7222_REG_GRP_GLBL] = {
595 .base = 0x8500,
596 .num_row = 1,
597 .num_col = 3,
598 },
599 [IQS7222_REG_GRP_BTN] = {
600 .base = 0x9000,
601 .num_row = 10,
602 .num_col = 3,
603 },
604 [IQS7222_REG_GRP_CHAN] = {
605 .base = 0xA000,
606 .num_row = 10,
607 .num_col = 6,
608 },
609 [IQS7222_REG_GRP_FILT] = {
610 .base = 0xAA00,
611 .val_len = 3,
612 .num_row = 1,
613 .num_col = 2,
614 },
615 [IQS7222_REG_GRP_SLDR] = {
616 .base = 0xB000,
617 .num_row = 2,
618 .num_col = 10,
619 },
620 [IQS7222_REG_GRP_GPIO] = {
621 .base = 0xC000,
622 .num_row = 1,
623 .num_col = 3,
624 },
625 [IQS7222_REG_GRP_SYS] = {
626 .base = IQS7222_SYS_SETUP,
627 .num_row = 1,
628 .num_col = 11,
629 },
630 },
631 },
632 {
633 .prod_num = IQS7222_PROD_NUM_D,
634 .fw_major = 1,
635 .fw_minor = 2,
636 .touch_link = 1770,
637 .allow_offset = 9,
638 .event_offset = 10,
639 .comms_offset = 11,
640 .reg_grps = {
641 [IQS7222_REG_GRP_STAT] = {
642 .base = IQS7222_SYS_STATUS,
643 .num_row = 1,
644 .num_col = 7,
645 },
646 [IQS7222_REG_GRP_CYCLE] = {
647 .base = 0x8000,
648 .num_row = 7,
649 .num_col = 2,
650 },
651 [IQS7222_REG_GRP_GLBL] = {
652 .base = 0x8700,
653 .num_row = 1,
654 .num_col = 3,
655 },
656 [IQS7222_REG_GRP_BTN] = {
657 .base = 0x9000,
658 .num_row = 14,
659 .num_col = 3,
660 },
661 [IQS7222_REG_GRP_CHAN] = {
662 .base = 0xA000,
663 .num_row = 14,
664 .num_col = 4,
665 },
666 [IQS7222_REG_GRP_FILT] = {
667 .base = 0xAE00,
668 .val_len = 3,
669 .num_row = 1,
670 .num_col = 2,
671 },
672 [IQS7222_REG_GRP_TPAD] = {
673 .base = 0xB000,
674 .num_row = 1,
675 .num_col = 24,
676 },
677 [IQS7222_REG_GRP_GPIO] = {
678 .base = 0xC000,
679 .num_row = 3,
680 .num_col = 3,
681 },
682 [IQS7222_REG_GRP_SYS] = {
683 .base = IQS7222_SYS_SETUP,
684 .num_row = 1,
685 .num_col = 12,
686 },
687 },
688 },
689 {
690 .prod_num = IQS7222_PROD_NUM_D,
691 .fw_major = 1,
692 .fw_minor = 1,
693 .touch_link = 1774,
694 .allow_offset = 9,
695 .event_offset = 10,
696 .comms_offset = 11,
697 .reg_grps = {
698 [IQS7222_REG_GRP_STAT] = {
699 .base = IQS7222_SYS_STATUS,
700 .num_row = 1,
701 .num_col = 7,
702 },
703 [IQS7222_REG_GRP_CYCLE] = {
704 .base = 0x8000,
705 .num_row = 7,
706 .num_col = 2,
707 },
708 [IQS7222_REG_GRP_GLBL] = {
709 .base = 0x8700,
710 .num_row = 1,
711 .num_col = 3,
712 },
713 [IQS7222_REG_GRP_BTN] = {
714 .base = 0x9000,
715 .num_row = 14,
716 .num_col = 3,
717 },
718 [IQS7222_REG_GRP_CHAN] = {
719 .base = 0xA000,
720 .num_row = 14,
721 .num_col = 4,
722 },
723 [IQS7222_REG_GRP_FILT] = {
724 .base = 0xAE00,
725 .val_len = 3,
726 .num_row = 1,
727 .num_col = 2,
728 },
729 [IQS7222_REG_GRP_TPAD] = {
730 .base = 0xB000,
731 .num_row = 1,
732 .num_col = 24,
733 },
734 [IQS7222_REG_GRP_GPIO] = {
735 .base = 0xC000,
736 .num_row = 3,
737 .num_col = 3,
738 },
739 [IQS7222_REG_GRP_SYS] = {
740 .base = IQS7222_SYS_SETUP,
741 .num_row = 1,
742 .num_col = 12,
743 },
744 },
745 },
746 {
747 .prod_num = IQS7222_PROD_NUM_D,
748 .fw_major = 0,
749 .fw_minor = 37,
750 .touch_link = 1770,
751 .allow_offset = 9,
752 .event_offset = 10,
753 .comms_offset = 11,
754 .reg_grps = {
755 [IQS7222_REG_GRP_STAT] = {
756 .base = IQS7222_SYS_STATUS,
757 .num_row = 1,
758 .num_col = 7,
759 },
760 [IQS7222_REG_GRP_CYCLE] = {
761 .base = 0x8000,
762 .num_row = 7,
763 .num_col = 2,
764 },
765 [IQS7222_REG_GRP_GLBL] = {
766 .base = 0x8700,
767 .num_row = 1,
768 .num_col = 3,
769 },
770 [IQS7222_REG_GRP_BTN] = {
771 .base = 0x9000,
772 .num_row = 14,
773 .num_col = 3,
774 },
775 [IQS7222_REG_GRP_CHAN] = {
776 .base = 0xA000,
777 .num_row = 14,
778 .num_col = 4,
779 },
780 [IQS7222_REG_GRP_FILT] = {
781 .base = 0xAE00,
782 .val_len = 3,
783 .num_row = 1,
784 .num_col = 2,
785 },
786 [IQS7222_REG_GRP_TPAD] = {
787 .base = 0xB000,
788 .num_row = 1,
789 .num_col = 24,
790 },
791 [IQS7222_REG_GRP_GPIO] = {
792 .base = 0xC000,
793 .num_row = 3,
794 .num_col = 3,
795 },
796 [IQS7222_REG_GRP_SYS] = {
797 .base = IQS7222_SYS_SETUP,
798 .num_row = 1,
799 .num_col = 12,
800 },
801 },
802 },
803 };
804
805 struct iqs7222_prop_desc {
806 const char *name;
807 enum iqs7222_reg_grp_id reg_grp;
808 enum iqs7222_reg_key_id reg_key;
809 int reg_offset;
810 int reg_shift;
811 int reg_width;
812 int val_pitch;
813 int val_min;
814 int val_max;
815 bool invert;
816 const char *label;
817 };
818
819 static const struct iqs7222_prop_desc iqs7222_props[] = {
820 {
821 .name = "azoteq,conv-period",
822 .reg_grp = IQS7222_REG_GRP_CYCLE,
823 .reg_offset = 0,
824 .reg_shift = 8,
825 .reg_width = 8,
826 .label = "conversion period",
827 },
828 {
829 .name = "azoteq,conv-frac",
830 .reg_grp = IQS7222_REG_GRP_CYCLE,
831 .reg_offset = 0,
832 .reg_shift = 0,
833 .reg_width = 8,
834 .label = "conversion frequency fractional divider",
835 },
836 {
837 .name = "azoteq,rx-float-inactive",
838 .reg_grp = IQS7222_REG_GRP_CYCLE,
839 .reg_offset = 1,
840 .reg_shift = 6,
841 .reg_width = 1,
842 .invert = true,
843 },
844 {
845 .name = "azoteq,dead-time-enable",
846 .reg_grp = IQS7222_REG_GRP_CYCLE,
847 .reg_offset = 1,
848 .reg_shift = 5,
849 .reg_width = 1,
850 },
851 {
852 .name = "azoteq,tx-freq-fosc",
853 .reg_grp = IQS7222_REG_GRP_CYCLE,
854 .reg_offset = 1,
855 .reg_shift = 4,
856 .reg_width = 1,
857 },
858 {
859 .name = "azoteq,vbias-enable",
860 .reg_grp = IQS7222_REG_GRP_CYCLE,
861 .reg_offset = 1,
862 .reg_shift = 3,
863 .reg_width = 1,
864 },
865 {
866 .name = "azoteq,sense-mode",
867 .reg_grp = IQS7222_REG_GRP_CYCLE,
868 .reg_offset = 1,
869 .reg_shift = 0,
870 .reg_width = 3,
871 .val_max = 3,
872 .label = "sensing mode",
873 },
874 {
875 .name = "azoteq,iref-enable",
876 .reg_grp = IQS7222_REG_GRP_CYCLE,
877 .reg_offset = 2,
878 .reg_shift = 10,
879 .reg_width = 1,
880 },
881 {
882 .name = "azoteq,iref-level",
883 .reg_grp = IQS7222_REG_GRP_CYCLE,
884 .reg_offset = 2,
885 .reg_shift = 4,
886 .reg_width = 4,
887 .label = "current reference level",
888 },
889 {
890 .name = "azoteq,iref-trim",
891 .reg_grp = IQS7222_REG_GRP_CYCLE,
892 .reg_offset = 2,
893 .reg_shift = 0,
894 .reg_width = 4,
895 .label = "current reference trim",
896 },
897 {
898 .name = "azoteq,max-counts",
899 .reg_grp = IQS7222_REG_GRP_GLBL,
900 .reg_offset = 0,
901 .reg_shift = 13,
902 .reg_width = 2,
903 .label = "maximum counts",
904 },
905 {
906 .name = "azoteq,auto-mode",
907 .reg_grp = IQS7222_REG_GRP_GLBL,
908 .reg_offset = 0,
909 .reg_shift = 2,
910 .reg_width = 2,
911 .label = "number of conversions",
912 },
913 {
914 .name = "azoteq,ati-frac-div-fine",
915 .reg_grp = IQS7222_REG_GRP_GLBL,
916 .reg_offset = 1,
917 .reg_shift = 9,
918 .reg_width = 5,
919 .label = "ATI fine fractional divider",
920 },
921 {
922 .name = "azoteq,ati-frac-div-coarse",
923 .reg_grp = IQS7222_REG_GRP_GLBL,
924 .reg_offset = 1,
925 .reg_shift = 0,
926 .reg_width = 5,
927 .label = "ATI coarse fractional divider",
928 },
929 {
930 .name = "azoteq,ati-comp-select",
931 .reg_grp = IQS7222_REG_GRP_GLBL,
932 .reg_offset = 2,
933 .reg_shift = 0,
934 .reg_width = 10,
935 .label = "ATI compensation selection",
936 },
937 {
938 .name = "azoteq,ati-band",
939 .reg_grp = IQS7222_REG_GRP_CHAN,
940 .reg_offset = 0,
941 .reg_shift = 12,
942 .reg_width = 2,
943 .label = "ATI band",
944 },
945 {
946 .name = "azoteq,global-halt",
947 .reg_grp = IQS7222_REG_GRP_CHAN,
948 .reg_offset = 0,
949 .reg_shift = 11,
950 .reg_width = 1,
951 },
952 {
953 .name = "azoteq,invert-enable",
954 .reg_grp = IQS7222_REG_GRP_CHAN,
955 .reg_offset = 0,
956 .reg_shift = 10,
957 .reg_width = 1,
958 },
959 {
960 .name = "azoteq,dual-direction",
961 .reg_grp = IQS7222_REG_GRP_CHAN,
962 .reg_offset = 0,
963 .reg_shift = 9,
964 .reg_width = 1,
965 },
966 {
967 .name = "azoteq,samp-cap-double",
968 .reg_grp = IQS7222_REG_GRP_CHAN,
969 .reg_offset = 0,
970 .reg_shift = 3,
971 .reg_width = 1,
972 },
973 {
974 .name = "azoteq,vref-half",
975 .reg_grp = IQS7222_REG_GRP_CHAN,
976 .reg_offset = 0,
977 .reg_shift = 2,
978 .reg_width = 1,
979 },
980 {
981 .name = "azoteq,proj-bias",
982 .reg_grp = IQS7222_REG_GRP_CHAN,
983 .reg_offset = 0,
984 .reg_shift = 0,
985 .reg_width = 2,
986 .label = "projected bias current",
987 },
988 {
989 .name = "azoteq,ati-target",
990 .reg_grp = IQS7222_REG_GRP_CHAN,
991 .reg_offset = 1,
992 .reg_shift = 8,
993 .reg_width = 8,
994 .val_pitch = 8,
995 .label = "ATI target",
996 },
997 {
998 .name = "azoteq,ati-base",
999 .reg_grp = IQS7222_REG_GRP_CHAN,
1000 .reg_offset = 1,
1001 .reg_shift = 3,
1002 .reg_width = 5,
1003 .val_pitch = 16,
1004 .label = "ATI base",
1005 },
1006 {
1007 .name = "azoteq,ati-mode",
1008 .reg_grp = IQS7222_REG_GRP_CHAN,
1009 .reg_offset = 1,
1010 .reg_shift = 0,
1011 .reg_width = 3,
1012 .val_max = 5,
1013 .label = "ATI mode",
1014 },
1015 {
1016 .name = "azoteq,ati-frac-div-fine",
1017 .reg_grp = IQS7222_REG_GRP_CHAN,
1018 .reg_offset = 2,
1019 .reg_shift = 9,
1020 .reg_width = 5,
1021 .label = "ATI fine fractional divider",
1022 },
1023 {
1024 .name = "azoteq,ati-frac-mult-coarse",
1025 .reg_grp = IQS7222_REG_GRP_CHAN,
1026 .reg_offset = 2,
1027 .reg_shift = 5,
1028 .reg_width = 4,
1029 .label = "ATI coarse fractional multiplier",
1030 },
1031 {
1032 .name = "azoteq,ati-frac-div-coarse",
1033 .reg_grp = IQS7222_REG_GRP_CHAN,
1034 .reg_offset = 2,
1035 .reg_shift = 0,
1036 .reg_width = 5,
1037 .label = "ATI coarse fractional divider",
1038 },
1039 {
1040 .name = "azoteq,ati-comp-div",
1041 .reg_grp = IQS7222_REG_GRP_CHAN,
1042 .reg_offset = 3,
1043 .reg_shift = 11,
1044 .reg_width = 5,
1045 .label = "ATI compensation divider",
1046 },
1047 {
1048 .name = "azoteq,ati-comp-select",
1049 .reg_grp = IQS7222_REG_GRP_CHAN,
1050 .reg_offset = 3,
1051 .reg_shift = 0,
1052 .reg_width = 10,
1053 .label = "ATI compensation selection",
1054 },
1055 {
1056 .name = "azoteq,debounce-exit",
1057 .reg_grp = IQS7222_REG_GRP_BTN,
1058 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1059 .reg_offset = 0,
1060 .reg_shift = 12,
1061 .reg_width = 4,
1062 .label = "debounce exit factor",
1063 },
1064 {
1065 .name = "azoteq,debounce-enter",
1066 .reg_grp = IQS7222_REG_GRP_BTN,
1067 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1068 .reg_offset = 0,
1069 .reg_shift = 8,
1070 .reg_width = 4,
1071 .label = "debounce entrance factor",
1072 },
1073 {
1074 .name = "azoteq,thresh",
1075 .reg_grp = IQS7222_REG_GRP_BTN,
1076 .reg_key = IQS7222_REG_KEY_PROX,
1077 .reg_offset = 0,
1078 .reg_shift = 0,
1079 .reg_width = 8,
1080 .val_max = 127,
1081 .label = "threshold",
1082 },
1083 {
1084 .name = "azoteq,thresh",
1085 .reg_grp = IQS7222_REG_GRP_BTN,
1086 .reg_key = IQS7222_REG_KEY_TOUCH,
1087 .reg_offset = 1,
1088 .reg_shift = 0,
1089 .reg_width = 8,
1090 .label = "threshold",
1091 },
1092 {
1093 .name = "azoteq,hyst",
1094 .reg_grp = IQS7222_REG_GRP_BTN,
1095 .reg_key = IQS7222_REG_KEY_TOUCH,
1096 .reg_offset = 1,
1097 .reg_shift = 8,
1098 .reg_width = 8,
1099 .label = "hysteresis",
1100 },
1101 {
1102 .name = "azoteq,lta-beta-lp",
1103 .reg_grp = IQS7222_REG_GRP_FILT,
1104 .reg_offset = 0,
1105 .reg_shift = 12,
1106 .reg_width = 4,
1107 .label = "low-power mode long-term average beta",
1108 },
1109 {
1110 .name = "azoteq,lta-beta-np",
1111 .reg_grp = IQS7222_REG_GRP_FILT,
1112 .reg_offset = 0,
1113 .reg_shift = 8,
1114 .reg_width = 4,
1115 .label = "normal-power mode long-term average beta",
1116 },
1117 {
1118 .name = "azoteq,counts-beta-lp",
1119 .reg_grp = IQS7222_REG_GRP_FILT,
1120 .reg_offset = 0,
1121 .reg_shift = 4,
1122 .reg_width = 4,
1123 .label = "low-power mode counts beta",
1124 },
1125 {
1126 .name = "azoteq,counts-beta-np",
1127 .reg_grp = IQS7222_REG_GRP_FILT,
1128 .reg_offset = 0,
1129 .reg_shift = 0,
1130 .reg_width = 4,
1131 .label = "normal-power mode counts beta",
1132 },
1133 {
1134 .name = "azoteq,lta-fast-beta-lp",
1135 .reg_grp = IQS7222_REG_GRP_FILT,
1136 .reg_offset = 1,
1137 .reg_shift = 4,
1138 .reg_width = 4,
1139 .label = "low-power mode long-term average fast beta",
1140 },
1141 {
1142 .name = "azoteq,lta-fast-beta-np",
1143 .reg_grp = IQS7222_REG_GRP_FILT,
1144 .reg_offset = 1,
1145 .reg_shift = 0,
1146 .reg_width = 4,
1147 .label = "normal-power mode long-term average fast beta",
1148 },
1149 {
1150 .name = "azoteq,lower-cal",
1151 .reg_grp = IQS7222_REG_GRP_SLDR,
1152 .reg_offset = 0,
1153 .reg_shift = 8,
1154 .reg_width = 8,
1155 .label = "lower calibration",
1156 },
1157 {
1158 .name = "azoteq,static-beta",
1159 .reg_grp = IQS7222_REG_GRP_SLDR,
1160 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1161 .reg_offset = 0,
1162 .reg_shift = 6,
1163 .reg_width = 1,
1164 },
1165 {
1166 .name = "azoteq,bottom-beta",
1167 .reg_grp = IQS7222_REG_GRP_SLDR,
1168 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1169 .reg_offset = 0,
1170 .reg_shift = 3,
1171 .reg_width = 3,
1172 .label = "bottom beta",
1173 },
1174 {
1175 .name = "azoteq,static-beta",
1176 .reg_grp = IQS7222_REG_GRP_SLDR,
1177 .reg_key = IQS7222_REG_KEY_WHEEL,
1178 .reg_offset = 0,
1179 .reg_shift = 7,
1180 .reg_width = 1,
1181 },
1182 {
1183 .name = "azoteq,bottom-beta",
1184 .reg_grp = IQS7222_REG_GRP_SLDR,
1185 .reg_key = IQS7222_REG_KEY_WHEEL,
1186 .reg_offset = 0,
1187 .reg_shift = 4,
1188 .reg_width = 3,
1189 .label = "bottom beta",
1190 },
1191 {
1192 .name = "azoteq,bottom-speed",
1193 .reg_grp = IQS7222_REG_GRP_SLDR,
1194 .reg_offset = 1,
1195 .reg_shift = 8,
1196 .reg_width = 8,
1197 .label = "bottom speed",
1198 },
1199 {
1200 .name = "azoteq,upper-cal",
1201 .reg_grp = IQS7222_REG_GRP_SLDR,
1202 .reg_offset = 1,
1203 .reg_shift = 0,
1204 .reg_width = 8,
1205 .label = "upper calibration",
1206 },
1207 {
1208 .name = "azoteq,gesture-max-ms",
1209 .reg_grp = IQS7222_REG_GRP_SLDR,
1210 .reg_key = IQS7222_REG_KEY_TAP,
1211 .reg_offset = 9,
1212 .reg_shift = 8,
1213 .reg_width = 8,
1214 .val_pitch = 16,
1215 .label = "maximum gesture time",
1216 },
1217 {
1218 .name = "azoteq,gesture-max-ms",
1219 .reg_grp = IQS7222_REG_GRP_SLDR,
1220 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1221 .reg_offset = 9,
1222 .reg_shift = 8,
1223 .reg_width = 8,
1224 .val_pitch = 4,
1225 .label = "maximum gesture time",
1226 },
1227 {
1228 .name = "azoteq,gesture-min-ms",
1229 .reg_grp = IQS7222_REG_GRP_SLDR,
1230 .reg_key = IQS7222_REG_KEY_TAP,
1231 .reg_offset = 9,
1232 .reg_shift = 3,
1233 .reg_width = 5,
1234 .val_pitch = 16,
1235 .label = "minimum gesture time",
1236 },
1237 {
1238 .name = "azoteq,gesture-min-ms",
1239 .reg_grp = IQS7222_REG_GRP_SLDR,
1240 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1241 .reg_offset = 9,
1242 .reg_shift = 3,
1243 .reg_width = 5,
1244 .val_pitch = 4,
1245 .label = "minimum gesture time",
1246 },
1247 {
1248 .name = "azoteq,gesture-dist",
1249 .reg_grp = IQS7222_REG_GRP_SLDR,
1250 .reg_key = IQS7222_REG_KEY_AXIAL,
1251 .reg_offset = 10,
1252 .reg_shift = 8,
1253 .reg_width = 8,
1254 .val_pitch = 16,
1255 .label = "gesture distance",
1256 },
1257 {
1258 .name = "azoteq,gesture-dist",
1259 .reg_grp = IQS7222_REG_GRP_SLDR,
1260 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1261 .reg_offset = 10,
1262 .reg_shift = 8,
1263 .reg_width = 8,
1264 .val_pitch = 16,
1265 .label = "gesture distance",
1266 },
1267 {
1268 .name = "azoteq,gesture-max-ms",
1269 .reg_grp = IQS7222_REG_GRP_SLDR,
1270 .reg_key = IQS7222_REG_KEY_AXIAL,
1271 .reg_offset = 10,
1272 .reg_shift = 0,
1273 .reg_width = 8,
1274 .val_pitch = 16,
1275 .label = "maximum gesture time",
1276 },
1277 {
1278 .name = "azoteq,gesture-max-ms",
1279 .reg_grp = IQS7222_REG_GRP_SLDR,
1280 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1281 .reg_offset = 10,
1282 .reg_shift = 0,
1283 .reg_width = 8,
1284 .val_pitch = 4,
1285 .label = "maximum gesture time",
1286 },
1287 {
1288 .name = "azoteq,num-rows",
1289 .reg_grp = IQS7222_REG_GRP_TPAD,
1290 .reg_offset = 0,
1291 .reg_shift = 4,
1292 .reg_width = 4,
1293 .val_min = 1,
1294 .val_max = 12,
1295 .label = "number of rows",
1296 },
1297 {
1298 .name = "azoteq,num-cols",
1299 .reg_grp = IQS7222_REG_GRP_TPAD,
1300 .reg_offset = 0,
1301 .reg_shift = 0,
1302 .reg_width = 4,
1303 .val_min = 1,
1304 .val_max = 12,
1305 .label = "number of columns",
1306 },
1307 {
1308 .name = "azoteq,lower-cal-y",
1309 .reg_grp = IQS7222_REG_GRP_TPAD,
1310 .reg_offset = 1,
1311 .reg_shift = 8,
1312 .reg_width = 8,
1313 .label = "lower vertical calibration",
1314 },
1315 {
1316 .name = "azoteq,lower-cal-x",
1317 .reg_grp = IQS7222_REG_GRP_TPAD,
1318 .reg_offset = 1,
1319 .reg_shift = 0,
1320 .reg_width = 8,
1321 .label = "lower horizontal calibration",
1322 },
1323 {
1324 .name = "azoteq,upper-cal-y",
1325 .reg_grp = IQS7222_REG_GRP_TPAD,
1326 .reg_offset = 2,
1327 .reg_shift = 8,
1328 .reg_width = 8,
1329 .label = "upper vertical calibration",
1330 },
1331 {
1332 .name = "azoteq,upper-cal-x",
1333 .reg_grp = IQS7222_REG_GRP_TPAD,
1334 .reg_offset = 2,
1335 .reg_shift = 0,
1336 .reg_width = 8,
1337 .label = "upper horizontal calibration",
1338 },
1339 {
1340 .name = "azoteq,top-speed",
1341 .reg_grp = IQS7222_REG_GRP_TPAD,
1342 .reg_offset = 3,
1343 .reg_shift = 8,
1344 .reg_width = 8,
1345 .val_pitch = 4,
1346 .label = "top speed",
1347 },
1348 {
1349 .name = "azoteq,bottom-speed",
1350 .reg_grp = IQS7222_REG_GRP_TPAD,
1351 .reg_offset = 3,
1352 .reg_shift = 0,
1353 .reg_width = 8,
1354 .label = "bottom speed",
1355 },
1356 {
1357 .name = "azoteq,gesture-min-ms",
1358 .reg_grp = IQS7222_REG_GRP_TPAD,
1359 .reg_key = IQS7222_REG_KEY_TAP,
1360 .reg_offset = 20,
1361 .reg_shift = 8,
1362 .reg_width = 8,
1363 .val_pitch = 16,
1364 .label = "minimum gesture time",
1365 },
1366 {
1367 .name = "azoteq,gesture-max-ms",
1368 .reg_grp = IQS7222_REG_GRP_TPAD,
1369 .reg_key = IQS7222_REG_KEY_AXIAL,
1370 .reg_offset = 21,
1371 .reg_shift = 8,
1372 .reg_width = 8,
1373 .val_pitch = 16,
1374 .label = "maximum gesture time",
1375 },
1376 {
1377 .name = "azoteq,gesture-max-ms",
1378 .reg_grp = IQS7222_REG_GRP_TPAD,
1379 .reg_key = IQS7222_REG_KEY_TAP,
1380 .reg_offset = 21,
1381 .reg_shift = 0,
1382 .reg_width = 8,
1383 .val_pitch = 16,
1384 .label = "maximum gesture time",
1385 },
1386 {
1387 .name = "azoteq,gesture-dist",
1388 .reg_grp = IQS7222_REG_GRP_TPAD,
1389 .reg_key = IQS7222_REG_KEY_TAP,
1390 .reg_offset = 22,
1391 .reg_shift = 0,
1392 .reg_width = 16,
1393 .label = "gesture distance",
1394 },
1395 {
1396 .name = "azoteq,gesture-dist",
1397 .reg_grp = IQS7222_REG_GRP_TPAD,
1398 .reg_key = IQS7222_REG_KEY_AXIAL,
1399 .reg_offset = 23,
1400 .reg_shift = 0,
1401 .reg_width = 16,
1402 .label = "gesture distance",
1403 },
1404 {
1405 .name = "drive-open-drain",
1406 .reg_grp = IQS7222_REG_GRP_GPIO,
1407 .reg_offset = 0,
1408 .reg_shift = 1,
1409 .reg_width = 1,
1410 },
1411 {
1412 .name = "azoteq,timeout-ati-ms",
1413 .reg_grp = IQS7222_REG_GRP_SYS,
1414 .reg_offset = 1,
1415 .reg_shift = 0,
1416 .reg_width = 16,
1417 .val_pitch = 500,
1418 .label = "ATI error timeout",
1419 },
1420 {
1421 .name = "azoteq,rate-ati-ms",
1422 .reg_grp = IQS7222_REG_GRP_SYS,
1423 .reg_offset = 2,
1424 .reg_shift = 0,
1425 .reg_width = 16,
1426 .label = "ATI report rate",
1427 },
1428 {
1429 .name = "azoteq,timeout-np-ms",
1430 .reg_grp = IQS7222_REG_GRP_SYS,
1431 .reg_offset = 3,
1432 .reg_shift = 0,
1433 .reg_width = 16,
1434 .label = "normal-power mode timeout",
1435 },
1436 {
1437 .name = "azoteq,rate-np-ms",
1438 .reg_grp = IQS7222_REG_GRP_SYS,
1439 .reg_offset = 4,
1440 .reg_shift = 0,
1441 .reg_width = 16,
1442 .val_max = 3000,
1443 .label = "normal-power mode report rate",
1444 },
1445 {
1446 .name = "azoteq,timeout-lp-ms",
1447 .reg_grp = IQS7222_REG_GRP_SYS,
1448 .reg_offset = 5,
1449 .reg_shift = 0,
1450 .reg_width = 16,
1451 .label = "low-power mode timeout",
1452 },
1453 {
1454 .name = "azoteq,rate-lp-ms",
1455 .reg_grp = IQS7222_REG_GRP_SYS,
1456 .reg_offset = 6,
1457 .reg_shift = 0,
1458 .reg_width = 16,
1459 .val_max = 3000,
1460 .label = "low-power mode report rate",
1461 },
1462 {
1463 .name = "azoteq,timeout-ulp-ms",
1464 .reg_grp = IQS7222_REG_GRP_SYS,
1465 .reg_offset = 7,
1466 .reg_shift = 0,
1467 .reg_width = 16,
1468 .label = "ultra-low-power mode timeout",
1469 },
1470 {
1471 .name = "azoteq,rate-ulp-ms",
1472 .reg_grp = IQS7222_REG_GRP_SYS,
1473 .reg_offset = 8,
1474 .reg_shift = 0,
1475 .reg_width = 16,
1476 .val_max = 3000,
1477 .label = "ultra-low-power mode report rate",
1478 },
1479 };
1480
1481 struct iqs7222_private {
1482 const struct iqs7222_dev_desc *dev_desc;
1483 struct gpio_desc *reset_gpio;
1484 struct gpio_desc *irq_gpio;
1485 struct i2c_client *client;
1486 struct input_dev *keypad;
1487 struct touchscreen_properties prop;
1488 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1489 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1490 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1491 unsigned int sl_axis[IQS7222_MAX_SLDR];
1492 unsigned int tp_code[ARRAY_SIZE(iqs7222_tp_events)];
1493 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1494 u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1495 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1496 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1497 u16 filt_setup[IQS7222_MAX_COLS_FILT];
1498 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1499 u16 tpad_setup[IQS7222_MAX_COLS_TPAD];
1500 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1501 u16 sys_setup[IQS7222_MAX_COLS_SYS];
1502 };
1503
iqs7222_setup(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int row)1504 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1505 enum iqs7222_reg_grp_id reg_grp, int row)
1506 {
1507 switch (reg_grp) {
1508 case IQS7222_REG_GRP_CYCLE:
1509 return iqs7222->cycle_setup[row];
1510
1511 case IQS7222_REG_GRP_GLBL:
1512 return iqs7222->glbl_setup;
1513
1514 case IQS7222_REG_GRP_BTN:
1515 return iqs7222->btn_setup[row];
1516
1517 case IQS7222_REG_GRP_CHAN:
1518 return iqs7222->chan_setup[row];
1519
1520 case IQS7222_REG_GRP_FILT:
1521 return iqs7222->filt_setup;
1522
1523 case IQS7222_REG_GRP_SLDR:
1524 return iqs7222->sldr_setup[row];
1525
1526 case IQS7222_REG_GRP_TPAD:
1527 return iqs7222->tpad_setup;
1528
1529 case IQS7222_REG_GRP_GPIO:
1530 return iqs7222->gpio_setup[row];
1531
1532 case IQS7222_REG_GRP_SYS:
1533 return iqs7222->sys_setup;
1534
1535 default:
1536 return NULL;
1537 }
1538 }
1539
iqs7222_irq_poll(struct iqs7222_private * iqs7222,u16 timeout_ms)1540 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1541 {
1542 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1543 int ret;
1544
1545 do {
1546 usleep_range(1000, 1100);
1547
1548 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1549 if (ret < 0)
1550 return ret;
1551 else if (ret > 0)
1552 return 0;
1553 } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1554
1555 return -EBUSY;
1556 }
1557
iqs7222_hard_reset(struct iqs7222_private * iqs7222)1558 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1559 {
1560 struct i2c_client *client = iqs7222->client;
1561 int error;
1562
1563 if (!iqs7222->reset_gpio)
1564 return 0;
1565
1566 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1567 usleep_range(1000, 1100);
1568
1569 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1570
1571 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1572 if (error)
1573 dev_err(&client->dev, "Failed to reset device: %d\n", error);
1574
1575 return error;
1576 }
1577
iqs7222_force_comms(struct iqs7222_private * iqs7222)1578 static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1579 {
1580 u8 msg_buf[] = { 0xFF, };
1581 int ret;
1582
1583 /*
1584 * The device cannot communicate until it asserts its interrupt (RDY)
1585 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1586 * ever all write data is ignored, and all read data returns 0xEE.
1587 *
1588 * Unsolicited communication must be preceded by a special force com-
1589 * munication command, after which the device eventually asserts its
1590 * RDY pin and agrees to communicate.
1591 *
1592 * Regardless of whether communication is forced or the result of an
1593 * interrupt, the device automatically deasserts its RDY pin once it
1594 * detects an I2C stop condition, or a timeout expires.
1595 */
1596 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1597 if (ret < 0)
1598 return ret;
1599 else if (ret > 0)
1600 return 0;
1601
1602 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1603 if (ret < (int)sizeof(msg_buf)) {
1604 if (ret >= 0)
1605 ret = -EIO;
1606
1607 /*
1608 * The datasheet states that the host must wait to retry any
1609 * failed attempt to communicate over I2C.
1610 */
1611 msleep(IQS7222_COMMS_RETRY_MS);
1612 return ret;
1613 }
1614
1615 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1616 }
1617
iqs7222_read_burst(struct iqs7222_private * iqs7222,u16 reg,void * val,u16 val_len)1618 static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1619 u16 reg, void *val, u16 val_len)
1620 {
1621 u8 reg_buf[sizeof(__be16)];
1622 int ret, i;
1623 struct i2c_client *client = iqs7222->client;
1624 struct i2c_msg msg[] = {
1625 {
1626 .addr = client->addr,
1627 .flags = 0,
1628 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1629 .buf = reg_buf,
1630 },
1631 {
1632 .addr = client->addr,
1633 .flags = I2C_M_RD,
1634 .len = val_len,
1635 .buf = (u8 *)val,
1636 },
1637 };
1638
1639 if (reg > U8_MAX)
1640 put_unaligned_be16(reg, reg_buf);
1641 else
1642 *reg_buf = (u8)reg;
1643
1644 /*
1645 * The following loop protects against an edge case in which the RDY
1646 * pin is automatically deasserted just as the read is initiated. In
1647 * that case, the read must be retried using forced communication.
1648 */
1649 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1650 ret = iqs7222_force_comms(iqs7222);
1651 if (ret < 0)
1652 continue;
1653
1654 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1655 if (ret < (int)ARRAY_SIZE(msg)) {
1656 if (ret >= 0)
1657 ret = -EIO;
1658
1659 msleep(IQS7222_COMMS_RETRY_MS);
1660 continue;
1661 }
1662
1663 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1664 ret = -ENODATA;
1665 continue;
1666 }
1667
1668 ret = 0;
1669 break;
1670 }
1671
1672 /*
1673 * The following delay ensures the device has deasserted the RDY pin
1674 * following the I2C stop condition.
1675 */
1676 usleep_range(50, 100);
1677
1678 if (ret < 0)
1679 dev_err(&client->dev,
1680 "Failed to read from address 0x%04X: %d\n", reg, ret);
1681
1682 return ret;
1683 }
1684
iqs7222_read_word(struct iqs7222_private * iqs7222,u16 reg,u16 * val)1685 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1686 {
1687 __le16 val_buf;
1688 int error;
1689
1690 error = iqs7222_read_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1691 if (error)
1692 return error;
1693
1694 *val = le16_to_cpu(val_buf);
1695
1696 return 0;
1697 }
1698
iqs7222_write_burst(struct iqs7222_private * iqs7222,u16 reg,const void * val,u16 val_len)1699 static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1700 u16 reg, const void *val, u16 val_len)
1701 {
1702 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1703 int msg_len = reg_len + val_len;
1704 int ret, i;
1705 struct i2c_client *client = iqs7222->client;
1706 u8 *msg_buf;
1707
1708 msg_buf = kzalloc(msg_len, GFP_KERNEL);
1709 if (!msg_buf)
1710 return -ENOMEM;
1711
1712 if (reg > U8_MAX)
1713 put_unaligned_be16(reg, msg_buf);
1714 else
1715 *msg_buf = (u8)reg;
1716
1717 memcpy(msg_buf + reg_len, val, val_len);
1718
1719 /*
1720 * The following loop protects against an edge case in which the RDY
1721 * pin is automatically asserted just before the force communication
1722 * command is sent.
1723 *
1724 * In that case, the subsequent I2C stop condition tricks the device
1725 * into preemptively deasserting the RDY pin and the command must be
1726 * sent again.
1727 */
1728 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1729 ret = iqs7222_force_comms(iqs7222);
1730 if (ret < 0)
1731 continue;
1732
1733 ret = i2c_master_send(client, msg_buf, msg_len);
1734 if (ret < msg_len) {
1735 if (ret >= 0)
1736 ret = -EIO;
1737
1738 msleep(IQS7222_COMMS_RETRY_MS);
1739 continue;
1740 }
1741
1742 ret = 0;
1743 break;
1744 }
1745
1746 kfree(msg_buf);
1747
1748 usleep_range(50, 100);
1749
1750 if (ret < 0)
1751 dev_err(&client->dev,
1752 "Failed to write to address 0x%04X: %d\n", reg, ret);
1753
1754 return ret;
1755 }
1756
iqs7222_write_word(struct iqs7222_private * iqs7222,u16 reg,u16 val)1757 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1758 {
1759 __le16 val_buf = cpu_to_le16(val);
1760
1761 return iqs7222_write_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1762 }
1763
iqs7222_ati_trigger(struct iqs7222_private * iqs7222)1764 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1765 {
1766 struct i2c_client *client = iqs7222->client;
1767 ktime_t ati_timeout;
1768 u16 sys_status = 0;
1769 u16 sys_setup;
1770 int error, i;
1771
1772 /*
1773 * The reserved fields of the system setup register may have changed
1774 * as a result of other registers having been written. As such, read
1775 * the register's latest value to avoid unexpected behavior when the
1776 * register is written in the loop that follows.
1777 */
1778 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup);
1779 if (error)
1780 return error;
1781
1782 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1783 /*
1784 * Trigger ATI from streaming and normal-power modes so that
1785 * the RDY pin continues to be asserted during ATI.
1786 */
1787 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1788 sys_setup |
1789 IQS7222_SYS_SETUP_REDO_ATI);
1790 if (error)
1791 return error;
1792
1793 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1794
1795 do {
1796 error = iqs7222_irq_poll(iqs7222,
1797 IQS7222_COMMS_TIMEOUT_MS);
1798 if (error)
1799 continue;
1800
1801 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1802 &sys_status);
1803 if (error)
1804 return error;
1805
1806 if (sys_status & IQS7222_SYS_STATUS_RESET)
1807 return 0;
1808
1809 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1810 break;
1811
1812 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1813 continue;
1814
1815 /*
1816 * Use stream-in-touch mode if either slider reports
1817 * absolute position.
1818 */
1819 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1820 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1821 : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1822 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1823
1824 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1825 sys_setup);
1826 } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1827
1828 dev_err(&client->dev,
1829 "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1830 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1831 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1832 }
1833
1834 return -ETIMEDOUT;
1835 }
1836
iqs7222_dev_init(struct iqs7222_private * iqs7222,int dir)1837 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1838 {
1839 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1840 int comms_offset = dev_desc->comms_offset;
1841 int error, i, j, k;
1842
1843 /*
1844 * Acknowledge reset before writing any registers in case the device
1845 * suffers a spurious reset during initialization.
1846 */
1847 if (dir == WRITE) {
1848 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1849 iqs7222->sys_setup[0] |
1850 IQS7222_SYS_SETUP_ACK_RESET);
1851 if (error)
1852 return error;
1853 }
1854
1855 /*
1856 * Take advantage of the stop-bit disable function, if available, to
1857 * save the trouble of having to reopen a communication window after
1858 * each burst read or write.
1859 */
1860 if (comms_offset) {
1861 u16 comms_setup;
1862
1863 error = iqs7222_read_word(iqs7222,
1864 IQS7222_SYS_SETUP + comms_offset,
1865 &comms_setup);
1866 if (error)
1867 return error;
1868
1869 error = iqs7222_write_word(iqs7222,
1870 IQS7222_SYS_SETUP + comms_offset,
1871 comms_setup | IQS7222_COMMS_HOLD);
1872 if (error)
1873 return error;
1874 }
1875
1876 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1877 int num_row = dev_desc->reg_grps[i].num_row;
1878 int num_col = dev_desc->reg_grps[i].num_col;
1879 u16 reg = dev_desc->reg_grps[i].base;
1880 __le16 *val_buf;
1881 u16 val_len = dev_desc->reg_grps[i].val_len ? : num_col * sizeof(*val_buf);
1882 u16 *val;
1883
1884 if (!num_col)
1885 continue;
1886
1887 val = iqs7222_setup(iqs7222, i, 0);
1888 if (!val)
1889 continue;
1890
1891 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1892 if (!val_buf)
1893 return -ENOMEM;
1894
1895 for (j = 0; j < num_row; j++) {
1896 switch (dir) {
1897 case READ:
1898 error = iqs7222_read_burst(iqs7222, reg,
1899 val_buf, val_len);
1900 for (k = 0; k < num_col; k++)
1901 val[k] = le16_to_cpu(val_buf[k]);
1902 break;
1903
1904 case WRITE:
1905 for (k = 0; k < num_col; k++)
1906 val_buf[k] = cpu_to_le16(val[k]);
1907 error = iqs7222_write_burst(iqs7222, reg,
1908 val_buf, val_len);
1909 break;
1910
1911 default:
1912 error = -EINVAL;
1913 }
1914
1915 if (error)
1916 break;
1917
1918 reg += IQS7222_REG_OFFSET;
1919 val += iqs7222_max_cols[i];
1920 }
1921
1922 kfree(val_buf);
1923
1924 if (error)
1925 return error;
1926 }
1927
1928 if (comms_offset) {
1929 u16 comms_setup;
1930
1931 error = iqs7222_read_word(iqs7222,
1932 IQS7222_SYS_SETUP + comms_offset,
1933 &comms_setup);
1934 if (error)
1935 return error;
1936
1937 error = iqs7222_write_word(iqs7222,
1938 IQS7222_SYS_SETUP + comms_offset,
1939 comms_setup & ~IQS7222_COMMS_HOLD);
1940 if (error)
1941 return error;
1942 }
1943
1944 if (dir == READ) {
1945 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1946 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1947 return 0;
1948 }
1949
1950 return iqs7222_ati_trigger(iqs7222);
1951 }
1952
iqs7222_dev_info(struct iqs7222_private * iqs7222)1953 static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1954 {
1955 struct i2c_client *client = iqs7222->client;
1956 bool prod_num_valid = false;
1957 __le16 dev_id[3];
1958 int error, i;
1959
1960 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1961 sizeof(dev_id));
1962 if (error)
1963 return error;
1964
1965 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1966 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1967 continue;
1968
1969 prod_num_valid = true;
1970
1971 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1972 continue;
1973
1974 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1975 continue;
1976
1977 iqs7222->dev_desc = &iqs7222_devs[i];
1978 return 0;
1979 }
1980
1981 if (prod_num_valid)
1982 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1983 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1984 else
1985 dev_err(&client->dev, "Unrecognized product number: %u\n",
1986 le16_to_cpu(dev_id[0]));
1987
1988 return -EINVAL;
1989 }
1990
iqs7222_gpio_select(struct iqs7222_private * iqs7222,struct fwnode_handle * child_node,int child_enable,u16 child_link)1991 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1992 struct fwnode_handle *child_node,
1993 int child_enable, u16 child_link)
1994 {
1995 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1996 struct i2c_client *client = iqs7222->client;
1997 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1998 int error, count, i;
1999 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
2000
2001 if (!num_gpio)
2002 return 0;
2003
2004 if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
2005 return 0;
2006
2007 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
2008 if (count > num_gpio) {
2009 dev_err(&client->dev, "Invalid number of %s GPIOs\n",
2010 fwnode_get_name(child_node));
2011 return -EINVAL;
2012 } else if (count < 0) {
2013 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
2014 fwnode_get_name(child_node), count);
2015 return count;
2016 }
2017
2018 error = fwnode_property_read_u32_array(child_node,
2019 "azoteq,gpio-select",
2020 gpio_sel, count);
2021 if (error) {
2022 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
2023 fwnode_get_name(child_node), error);
2024 return error;
2025 }
2026
2027 for (i = 0; i < count; i++) {
2028 u16 *gpio_setup;
2029
2030 if (gpio_sel[i] >= num_gpio) {
2031 dev_err(&client->dev, "Invalid %s GPIO: %u\n",
2032 fwnode_get_name(child_node), gpio_sel[i]);
2033 return -EINVAL;
2034 }
2035
2036 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
2037
2038 if (gpio_setup[2] && child_link != gpio_setup[2]) {
2039 dev_err(&client->dev,
2040 "Conflicting GPIO %u event types\n",
2041 gpio_sel[i]);
2042 return -EINVAL;
2043 }
2044
2045 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
2046 gpio_setup[1] |= child_enable;
2047 gpio_setup[2] = child_link;
2048 }
2049
2050 return 0;
2051 }
2052
iqs7222_parse_props(struct iqs7222_private * iqs7222,struct fwnode_handle * reg_grp_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key)2053 static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
2054 struct fwnode_handle *reg_grp_node,
2055 int reg_grp_index,
2056 enum iqs7222_reg_grp_id reg_grp,
2057 enum iqs7222_reg_key_id reg_key)
2058 {
2059 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index);
2060 struct i2c_client *client = iqs7222->client;
2061 int i;
2062
2063 if (!setup)
2064 return 0;
2065
2066 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
2067 const char *name = iqs7222_props[i].name;
2068 int reg_offset = iqs7222_props[i].reg_offset;
2069 int reg_shift = iqs7222_props[i].reg_shift;
2070 int reg_width = iqs7222_props[i].reg_width;
2071 int val_pitch = iqs7222_props[i].val_pitch ? : 1;
2072 int val_min = iqs7222_props[i].val_min;
2073 int val_max = iqs7222_props[i].val_max;
2074 bool invert = iqs7222_props[i].invert;
2075 const char *label = iqs7222_props[i].label ? : name;
2076 unsigned int val;
2077 int error;
2078
2079 if (iqs7222_props[i].reg_grp != reg_grp ||
2080 iqs7222_props[i].reg_key != reg_key)
2081 continue;
2082
2083 /*
2084 * Boolean register fields are one bit wide; they are forcibly
2085 * reset to provide a means to undo changes by a bootloader if
2086 * necessary.
2087 *
2088 * Scalar fields, on the other hand, are left untouched unless
2089 * their corresponding properties are present.
2090 */
2091 if (reg_width == 1) {
2092 if (invert)
2093 setup[reg_offset] |= BIT(reg_shift);
2094 else
2095 setup[reg_offset] &= ~BIT(reg_shift);
2096 }
2097
2098 if (!fwnode_property_present(reg_grp_node, name))
2099 continue;
2100
2101 if (reg_width == 1) {
2102 if (invert)
2103 setup[reg_offset] &= ~BIT(reg_shift);
2104 else
2105 setup[reg_offset] |= BIT(reg_shift);
2106
2107 continue;
2108 }
2109
2110 error = fwnode_property_read_u32(reg_grp_node, name, &val);
2111 if (error) {
2112 dev_err(&client->dev, "Failed to read %s %s: %d\n",
2113 fwnode_get_name(reg_grp_node), label, error);
2114 return error;
2115 }
2116
2117 if (!val_max)
2118 val_max = GENMASK(reg_width - 1, 0) * val_pitch;
2119
2120 if (val < val_min || val > val_max) {
2121 dev_err(&client->dev, "Invalid %s %s: %u\n",
2122 fwnode_get_name(reg_grp_node), label, val);
2123 return -EINVAL;
2124 }
2125
2126 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
2127 reg_shift);
2128 setup[reg_offset] |= (val / val_pitch << reg_shift);
2129 }
2130
2131 return 0;
2132 }
2133
iqs7222_parse_event(struct iqs7222_private * iqs7222,struct fwnode_handle * event_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key,u16 event_enable,u16 event_link,unsigned int * event_type,unsigned int * event_code)2134 static int iqs7222_parse_event(struct iqs7222_private *iqs7222,
2135 struct fwnode_handle *event_node,
2136 int reg_grp_index,
2137 enum iqs7222_reg_grp_id reg_grp,
2138 enum iqs7222_reg_key_id reg_key,
2139 u16 event_enable, u16 event_link,
2140 unsigned int *event_type,
2141 unsigned int *event_code)
2142 {
2143 struct i2c_client *client = iqs7222->client;
2144 int error;
2145
2146 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index,
2147 reg_grp, reg_key);
2148 if (error)
2149 return error;
2150
2151 error = iqs7222_gpio_select(iqs7222, event_node, event_enable,
2152 event_link);
2153 if (error)
2154 return error;
2155
2156 error = fwnode_property_read_u32(event_node, "linux,code", event_code);
2157 if (error == -EINVAL) {
2158 return 0;
2159 } else if (error) {
2160 dev_err(&client->dev, "Failed to read %s code: %d\n",
2161 fwnode_get_name(event_node), error);
2162 return error;
2163 }
2164
2165 if (!event_type) {
2166 input_set_capability(iqs7222->keypad, EV_KEY, *event_code);
2167 return 0;
2168 }
2169
2170 error = fwnode_property_read_u32(event_node, "linux,input-type",
2171 event_type);
2172 if (error == -EINVAL) {
2173 *event_type = EV_KEY;
2174 } else if (error) {
2175 dev_err(&client->dev, "Failed to read %s input type: %d\n",
2176 fwnode_get_name(event_node), error);
2177 return error;
2178 } else if (*event_type != EV_KEY && *event_type != EV_SW) {
2179 dev_err(&client->dev, "Invalid %s input type: %d\n",
2180 fwnode_get_name(event_node), *event_type);
2181 return -EINVAL;
2182 }
2183
2184 input_set_capability(iqs7222->keypad, *event_type, *event_code);
2185
2186 return 0;
2187 }
2188
iqs7222_parse_cycle(struct iqs7222_private * iqs7222,struct fwnode_handle * cycle_node,int cycle_index)2189 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222,
2190 struct fwnode_handle *cycle_node, int cycle_index)
2191 {
2192 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
2193 struct i2c_client *client = iqs7222->client;
2194 unsigned int pins[9];
2195 int error, count, i;
2196
2197 /*
2198 * Each channel shares a cycle with one other channel; the mapping of
2199 * channels to cycles is fixed. Properties defined for a cycle impact
2200 * both channels tied to the cycle.
2201 *
2202 * Unlike channels which are restricted to a select range of CRx pins
2203 * based on channel number, any cycle can claim any of the device's 9
2204 * CTx pins (CTx0-8).
2205 */
2206 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
2207 return 0;
2208
2209 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
2210 if (count < 0) {
2211 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
2212 fwnode_get_name(cycle_node), count);
2213 return count;
2214 } else if (count > ARRAY_SIZE(pins)) {
2215 dev_err(&client->dev, "Invalid number of %s CTx pins\n",
2216 fwnode_get_name(cycle_node));
2217 return -EINVAL;
2218 }
2219
2220 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
2221 pins, count);
2222 if (error) {
2223 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
2224 fwnode_get_name(cycle_node), error);
2225 return error;
2226 }
2227
2228 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
2229
2230 for (i = 0; i < count; i++) {
2231 if (pins[i] > 8) {
2232 dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
2233 fwnode_get_name(cycle_node), pins[i]);
2234 return -EINVAL;
2235 }
2236
2237 cycle_setup[1] |= BIT(pins[i] + 7);
2238 }
2239
2240 return 0;
2241 }
2242
iqs7222_parse_chan(struct iqs7222_private * iqs7222,struct fwnode_handle * chan_node,int chan_index)2243 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
2244 struct fwnode_handle *chan_node, int chan_index)
2245 {
2246 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2247 struct i2c_client *client = iqs7222->client;
2248 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2249 int ext_chan = dev_desc->ext_chan ? : num_chan;
2250 int error, i;
2251 u16 *chan_setup = iqs7222->chan_setup[chan_index];
2252 u16 *sys_setup = iqs7222->sys_setup;
2253 unsigned int val;
2254
2255 if (dev_desc->allow_offset &&
2256 fwnode_property_present(chan_node, "azoteq,ulp-allow"))
2257 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
2258
2259 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
2260
2261 /*
2262 * The reference channel function allows for differential measurements
2263 * and is only available in the case of IQS7222A or IQS7222C.
2264 */
2265 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
2266 fwnode_property_present(chan_node, "azoteq,ref-select")) {
2267 u16 *ref_setup;
2268
2269 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
2270 &val);
2271 if (error) {
2272 dev_err(&client->dev,
2273 "Failed to read %s reference channel: %d\n",
2274 fwnode_get_name(chan_node), error);
2275 return error;
2276 }
2277
2278 if (val >= ext_chan) {
2279 dev_err(&client->dev,
2280 "Invalid %s reference channel: %u\n",
2281 fwnode_get_name(chan_node), val);
2282 return -EINVAL;
2283 }
2284
2285 ref_setup = iqs7222->chan_setup[val];
2286
2287 /*
2288 * Configure the current channel as a follower of the selected
2289 * reference channel.
2290 */
2291 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
2292 chan_setup[4] = val * 42 + 1048;
2293
2294 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
2295 &val);
2296 if (!error) {
2297 if (val > U16_MAX) {
2298 dev_err(&client->dev,
2299 "Invalid %s reference weight: %u\n",
2300 fwnode_get_name(chan_node), val);
2301 return -EINVAL;
2302 }
2303
2304 chan_setup[5] = val;
2305 } else if (error != -EINVAL) {
2306 dev_err(&client->dev,
2307 "Failed to read %s reference weight: %d\n",
2308 fwnode_get_name(chan_node), error);
2309 return error;
2310 }
2311
2312 /*
2313 * Configure the selected channel as a reference channel which
2314 * serves the current channel.
2315 */
2316 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2317 ref_setup[5] |= BIT(chan_index);
2318
2319 ref_setup[4] = dev_desc->touch_link;
2320 if (fwnode_property_present(chan_node, "azoteq,use-prox"))
2321 ref_setup[4] -= 2;
2322 } else if (dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row &&
2323 fwnode_property_present(chan_node,
2324 "azoteq,counts-filt-enable")) {
2325 /*
2326 * In the case of IQS7222D, however, the reference mode field
2327 * is partially repurposed as a counts filter enable control.
2328 */
2329 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2330 }
2331
2332 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
2333 /*
2334 * Each channel can claim up to 4 CRx pins. The first half of
2335 * the channels can use CRx0-3, while the second half can use
2336 * CRx4-7.
2337 */
2338 unsigned int pins[4];
2339 int count;
2340
2341 count = fwnode_property_count_u32(chan_node,
2342 "azoteq,rx-enable");
2343 if (count < 0) {
2344 dev_err(&client->dev,
2345 "Failed to count %s CRx pins: %d\n",
2346 fwnode_get_name(chan_node), count);
2347 return count;
2348 } else if (count > ARRAY_SIZE(pins)) {
2349 dev_err(&client->dev,
2350 "Invalid number of %s CRx pins\n",
2351 fwnode_get_name(chan_node));
2352 return -EINVAL;
2353 }
2354
2355 error = fwnode_property_read_u32_array(chan_node,
2356 "azoteq,rx-enable",
2357 pins, count);
2358 if (error) {
2359 dev_err(&client->dev,
2360 "Failed to read %s CRx pins: %d\n",
2361 fwnode_get_name(chan_node), error);
2362 return error;
2363 }
2364
2365 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
2366
2367 for (i = 0; i < count; i++) {
2368 int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
2369
2370 if (pins[i] < min_crx || pins[i] > min_crx + 3) {
2371 dev_err(&client->dev,
2372 "Invalid %s CRx pin: %u\n",
2373 fwnode_get_name(chan_node), pins[i]);
2374 return -EINVAL;
2375 }
2376
2377 chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
2378 }
2379 }
2380
2381 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
2382 const char *event_name = iqs7222_kp_events[i].name;
2383 u16 event_enable = iqs7222_kp_events[i].enable;
2384
2385 struct fwnode_handle *event_node __free(fwnode_handle) =
2386 fwnode_get_named_child_node(chan_node, event_name);
2387 if (!event_node)
2388 continue;
2389
2390 error = fwnode_property_read_u32(event_node,
2391 "azoteq,timeout-press-ms",
2392 &val);
2393 if (!error) {
2394 /*
2395 * The IQS7222B employs a global pair of press timeout
2396 * registers as opposed to channel-specific registers.
2397 */
2398 u16 *setup = dev_desc->reg_grps
2399 [IQS7222_REG_GRP_BTN].num_col > 2 ?
2400 &iqs7222->btn_setup[chan_index][2] :
2401 &sys_setup[9];
2402
2403 if (val > U8_MAX * 500) {
2404 dev_err(&client->dev,
2405 "Invalid %s press timeout: %u\n",
2406 fwnode_get_name(event_node), val);
2407 return -EINVAL;
2408 }
2409
2410 *setup &= ~(U8_MAX << i * 8);
2411 *setup |= (val / 500 << i * 8);
2412 } else if (error != -EINVAL) {
2413 dev_err(&client->dev,
2414 "Failed to read %s press timeout: %d\n",
2415 fwnode_get_name(event_node), error);
2416 return error;
2417 }
2418
2419 error = iqs7222_parse_event(iqs7222, event_node, chan_index,
2420 IQS7222_REG_GRP_BTN,
2421 iqs7222_kp_events[i].reg_key,
2422 BIT(chan_index),
2423 dev_desc->touch_link - (i ? 0 : 2),
2424 &iqs7222->kp_type[chan_index][i],
2425 &iqs7222->kp_code[chan_index][i]);
2426 if (error)
2427 return error;
2428
2429 if (!iqs7222->kp_type[chan_index][i])
2430 continue;
2431
2432 if (!dev_desc->event_offset)
2433 continue;
2434
2435 sys_setup[dev_desc->event_offset] |= event_enable;
2436 }
2437
2438 /*
2439 * The following call handles a special pair of properties that apply
2440 * to a channel node, but reside within the button (event) group.
2441 */
2442 return iqs7222_parse_props(iqs7222, chan_node, chan_index,
2443 IQS7222_REG_GRP_BTN,
2444 IQS7222_REG_KEY_DEBOUNCE);
2445 }
2446
iqs7222_parse_sldr(struct iqs7222_private * iqs7222,struct fwnode_handle * sldr_node,int sldr_index)2447 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222,
2448 struct fwnode_handle *sldr_node, int sldr_index)
2449 {
2450 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2451 struct i2c_client *client = iqs7222->client;
2452 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2453 int ext_chan = dev_desc->ext_chan ? : num_chan;
2454 int count, error, reg_offset, i;
2455 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2456 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2457 unsigned int chan_sel[4], val;
2458
2459 /*
2460 * Each slider can be spread across 3 to 4 channels. It is possible to
2461 * select only 2 channels, but doing so prevents the slider from using
2462 * the specified resolution.
2463 */
2464 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
2465 if (count < 0) {
2466 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2467 fwnode_get_name(sldr_node), count);
2468 return count;
2469 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2470 dev_err(&client->dev, "Invalid number of %s channels\n",
2471 fwnode_get_name(sldr_node));
2472 return -EINVAL;
2473 }
2474
2475 error = fwnode_property_read_u32_array(sldr_node,
2476 "azoteq,channel-select",
2477 chan_sel, count);
2478 if (error) {
2479 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2480 fwnode_get_name(sldr_node), error);
2481 return error;
2482 }
2483
2484 /*
2485 * Resolution and top speed, if small enough, are packed into a single
2486 * register. Otherwise, each occupies its own register and the rest of
2487 * the slider-related register addresses are offset by one.
2488 */
2489 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2490
2491 sldr_setup[0] |= count;
2492 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2493
2494 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2495 sldr_setup[5 + reg_offset + i] = 0;
2496 if (i >= count)
2497 continue;
2498
2499 if (chan_sel[i] >= ext_chan) {
2500 dev_err(&client->dev, "Invalid %s channel: %u\n",
2501 fwnode_get_name(sldr_node), chan_sel[i]);
2502 return -EINVAL;
2503 }
2504
2505 /*
2506 * The following fields indicate which channels participate in
2507 * the slider, as well as each channel's relative placement.
2508 */
2509 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2510 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2511 }
2512
2513 sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2514 if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2515 sldr_setup[4 + reg_offset] -= 2;
2516
2517 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val);
2518 if (!error) {
2519 if (val > dev_desc->sldr_res) {
2520 dev_err(&client->dev, "Invalid %s size: %u\n",
2521 fwnode_get_name(sldr_node), val);
2522 return -EINVAL;
2523 }
2524
2525 if (reg_offset) {
2526 sldr_setup[3] = val;
2527 } else {
2528 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2529 sldr_setup[2] |= (val / 16 <<
2530 IQS7222_SLDR_SETUP_2_RES_SHIFT);
2531 }
2532 } else if (error != -EINVAL) {
2533 dev_err(&client->dev, "Failed to read %s size: %d\n",
2534 fwnode_get_name(sldr_node), error);
2535 return error;
2536 }
2537
2538 if (!(reg_offset ? sldr_setup[3]
2539 : sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) {
2540 dev_err(&client->dev, "Undefined %s size\n",
2541 fwnode_get_name(sldr_node));
2542 return -EINVAL;
2543 }
2544
2545 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val);
2546 if (!error) {
2547 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2548 dev_err(&client->dev, "Invalid %s top speed: %u\n",
2549 fwnode_get_name(sldr_node), val);
2550 return -EINVAL;
2551 }
2552
2553 if (reg_offset) {
2554 sldr_setup[2] = val;
2555 } else {
2556 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2557 sldr_setup[2] |= (val / 4);
2558 }
2559 } else if (error != -EINVAL) {
2560 dev_err(&client->dev, "Failed to read %s top speed: %d\n",
2561 fwnode_get_name(sldr_node), error);
2562 return error;
2563 }
2564
2565 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val);
2566 if (!error) {
2567 u16 sldr_max = sldr_setup[3] - 1;
2568
2569 if (!reg_offset) {
2570 sldr_max = sldr_setup[2];
2571
2572 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2573 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2574
2575 sldr_max = sldr_max * 16 - 1;
2576 }
2577
2578 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2579 iqs7222->sl_axis[sldr_index] = val;
2580 } else if (error != -EINVAL) {
2581 dev_err(&client->dev, "Failed to read %s axis: %d\n",
2582 fwnode_get_name(sldr_node), error);
2583 return error;
2584 }
2585
2586 if (dev_desc->wheel_enable) {
2587 sldr_setup[0] &= ~dev_desc->wheel_enable;
2588 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2589 sldr_setup[0] |= dev_desc->wheel_enable;
2590 }
2591
2592 /*
2593 * The absence of a register offset makes it safe to assume the device
2594 * supports gestures, each of which is first disabled until explicitly
2595 * enabled.
2596 */
2597 if (!reg_offset)
2598 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2599 sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2600
2601 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2602 const char *event_name = iqs7222_sl_events[i].name;
2603 enum iqs7222_reg_key_id reg_key;
2604
2605 struct fwnode_handle *event_node __free(fwnode_handle) =
2606 fwnode_get_named_child_node(sldr_node, event_name);
2607 if (!event_node)
2608 continue;
2609
2610 /*
2611 * Depending on the device, gestures are either offered using
2612 * one of two timing resolutions, or are not supported at all.
2613 */
2614 if (reg_offset)
2615 reg_key = IQS7222_REG_KEY_RESERVED;
2616 else if (dev_desc->legacy_gesture &&
2617 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP)
2618 reg_key = IQS7222_REG_KEY_TAP_LEGACY;
2619 else if (dev_desc->legacy_gesture &&
2620 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL)
2621 reg_key = IQS7222_REG_KEY_AXIAL_LEGACY;
2622 else
2623 reg_key = iqs7222_sl_events[i].reg_key;
2624
2625 /*
2626 * The press/release event does not expose a direct GPIO link,
2627 * but one can be emulated by tying each of the participating
2628 * channels to the same GPIO.
2629 */
2630 error = iqs7222_parse_event(iqs7222, event_node, sldr_index,
2631 IQS7222_REG_GRP_SLDR, reg_key,
2632 i ? iqs7222_sl_events[i].enable
2633 : sldr_setup[3 + reg_offset],
2634 i ? 1568 + sldr_index * 30
2635 : sldr_setup[4 + reg_offset],
2636 NULL,
2637 &iqs7222->sl_code[sldr_index][i]);
2638 if (error)
2639 return error;
2640
2641 if (!reg_offset)
2642 sldr_setup[9] |= iqs7222_sl_events[i].enable;
2643
2644 if (!dev_desc->event_offset)
2645 continue;
2646
2647 /*
2648 * The press/release event is determined based on whether the
2649 * coordinate field reports 0xFFFF and solely relies on touch
2650 * or proximity interrupts to be unmasked.
2651 */
2652 if (i && !reg_offset)
2653 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2654 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2655 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2656 else
2657 *event_mask |= IQS7222_EVENT_MASK_PROX;
2658 }
2659
2660 /*
2661 * The following call handles a special pair of properties that shift
2662 * to make room for a wheel enable control in the case of IQS7222C.
2663 */
2664 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index,
2665 IQS7222_REG_GRP_SLDR,
2666 dev_desc->wheel_enable ?
2667 IQS7222_REG_KEY_WHEEL :
2668 IQS7222_REG_KEY_NO_WHEEL);
2669 }
2670
iqs7222_parse_tpad(struct iqs7222_private * iqs7222,struct fwnode_handle * tpad_node,int tpad_index)2671 static int iqs7222_parse_tpad(struct iqs7222_private *iqs7222,
2672 struct fwnode_handle *tpad_node, int tpad_index)
2673 {
2674 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2675 struct touchscreen_properties *prop = &iqs7222->prop;
2676 struct i2c_client *client = iqs7222->client;
2677 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2678 int count, error, i;
2679 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2680 u16 *tpad_setup = iqs7222->tpad_setup;
2681 unsigned int chan_sel[12];
2682
2683 error = iqs7222_parse_props(iqs7222, tpad_node, tpad_index,
2684 IQS7222_REG_GRP_TPAD,
2685 IQS7222_REG_KEY_NONE);
2686 if (error)
2687 return error;
2688
2689 count = fwnode_property_count_u32(tpad_node, "azoteq,channel-select");
2690 if (count < 0) {
2691 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2692 fwnode_get_name(tpad_node), count);
2693 return count;
2694 } else if (!count || count > ARRAY_SIZE(chan_sel)) {
2695 dev_err(&client->dev, "Invalid number of %s channels\n",
2696 fwnode_get_name(tpad_node));
2697 return -EINVAL;
2698 }
2699
2700 error = fwnode_property_read_u32_array(tpad_node,
2701 "azoteq,channel-select",
2702 chan_sel, count);
2703 if (error) {
2704 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2705 fwnode_get_name(tpad_node), error);
2706 return error;
2707 }
2708
2709 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);
2710
2711 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2712 tpad_setup[8 + i] = 0;
2713 if (i >= count || chan_sel[i] == U8_MAX)
2714 continue;
2715
2716 if (chan_sel[i] >= num_chan) {
2717 dev_err(&client->dev, "Invalid %s channel: %u\n",
2718 fwnode_get_name(tpad_node), chan_sel[i]);
2719 return -EINVAL;
2720 }
2721
2722 /*
2723 * The following fields indicate which channels participate in
2724 * the trackpad, as well as each channel's relative placement.
2725 */
2726 tpad_setup[6] |= BIT(chan_sel[i]);
2727 tpad_setup[8 + i] = chan_sel[i] * 34 + 1072;
2728 }
2729
2730 tpad_setup[7] = dev_desc->touch_link;
2731 if (fwnode_property_present(tpad_node, "azoteq,use-prox"))
2732 tpad_setup[7] -= 2;
2733
2734 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++)
2735 tpad_setup[20] &= ~(iqs7222_tp_events[i].strict |
2736 iqs7222_tp_events[i].enable);
2737
2738 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) {
2739 const char *event_name = iqs7222_tp_events[i].name;
2740
2741 struct fwnode_handle *event_node __free(fwnode_handle) =
2742 fwnode_get_named_child_node(tpad_node, event_name);
2743 if (!event_node)
2744 continue;
2745
2746 if (fwnode_property_present(event_node,
2747 "azoteq,gesture-angle-tighten"))
2748 tpad_setup[20] |= iqs7222_tp_events[i].strict;
2749
2750 tpad_setup[20] |= iqs7222_tp_events[i].enable;
2751
2752 error = iqs7222_parse_event(iqs7222, event_node, tpad_index,
2753 IQS7222_REG_GRP_TPAD,
2754 iqs7222_tp_events[i].reg_key,
2755 iqs7222_tp_events[i].link, 1566,
2756 NULL,
2757 &iqs7222->tp_code[i]);
2758 if (error)
2759 return error;
2760
2761 if (!dev_desc->event_offset)
2762 continue;
2763
2764 /*
2765 * The press/release event is determined based on whether the
2766 * coordinate fields report 0xFFFF and solely relies on touch
2767 * or proximity interrupts to be unmasked.
2768 */
2769 if (i)
2770 *event_mask |= IQS7222_EVENT_MASK_TPAD;
2771 else if (tpad_setup[7] == dev_desc->touch_link)
2772 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2773 else
2774 *event_mask |= IQS7222_EVENT_MASK_PROX;
2775 }
2776
2777 if (!iqs7222->tp_code[0])
2778 return 0;
2779
2780 input_set_abs_params(iqs7222->keypad, ABS_X,
2781 0, (tpad_setup[4] ? : 1) - 1, 0, 0);
2782
2783 input_set_abs_params(iqs7222->keypad, ABS_Y,
2784 0, (tpad_setup[5] ? : 1) - 1, 0, 0);
2785
2786 touchscreen_parse_properties(iqs7222->keypad, false, prop);
2787
2788 if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2789 dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2790 prop->max_x, prop->max_y);
2791 return -EINVAL;
2792 }
2793
2794 tpad_setup[4] = prop->max_x + 1;
2795 tpad_setup[5] = prop->max_y + 1;
2796
2797 return 0;
2798 }
2799
2800 static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS])
2801 (struct iqs7222_private *iqs7222,
2802 struct fwnode_handle *reg_grp_node,
2803 int reg_grp_index) = {
2804 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle,
2805 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan,
2806 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr,
2807 [IQS7222_REG_GRP_TPAD] = iqs7222_parse_tpad,
2808 };
2809
iqs7222_parse_reg_grp(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int reg_grp_index)2810 static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222,
2811 enum iqs7222_reg_grp_id reg_grp,
2812 int reg_grp_index)
2813 {
2814 struct i2c_client *client = iqs7222->client;
2815 int error;
2816
2817 struct fwnode_handle *reg_grp_node __free(fwnode_handle) = NULL;
2818 if (iqs7222_reg_grp_names[reg_grp]) {
2819 char reg_grp_name[16];
2820
2821 snprintf(reg_grp_name, sizeof(reg_grp_name),
2822 iqs7222_reg_grp_names[reg_grp], reg_grp_index);
2823
2824 reg_grp_node = device_get_named_child_node(&client->dev,
2825 reg_grp_name);
2826 } else {
2827 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2828 }
2829
2830 if (!reg_grp_node)
2831 return 0;
2832
2833 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index,
2834 reg_grp, IQS7222_REG_KEY_NONE);
2835 if (error)
2836 return error;
2837
2838 if (iqs7222_parse_extra[reg_grp]) {
2839 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node,
2840 reg_grp_index);
2841 if (error)
2842 return error;
2843 }
2844
2845 return 0;
2846 }
2847
iqs7222_parse_all(struct iqs7222_private * iqs7222)2848 static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2849 {
2850 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2851 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2852 u16 *sys_setup = iqs7222->sys_setup;
2853 int error, i, j;
2854
2855 if (dev_desc->allow_offset)
2856 sys_setup[dev_desc->allow_offset] = U16_MAX;
2857
2858 if (dev_desc->event_offset)
2859 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2860
2861 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2862 u16 *gpio_setup = iqs7222->gpio_setup[i];
2863
2864 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2865 gpio_setup[1] = 0;
2866 gpio_setup[2] = 0;
2867
2868 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2869 continue;
2870
2871 /*
2872 * The IQS7222C and IQS7222D expose multiple GPIO and must be
2873 * informed as to which GPIO this group represents.
2874 */
2875 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2876 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2877
2878 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2879 }
2880
2881 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2882 u16 *chan_setup = iqs7222->chan_setup[i];
2883
2884 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2885 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2886
2887 chan_setup[5] = 0;
2888 }
2889
2890 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2891 u16 *sldr_setup = iqs7222->sldr_setup[i];
2892
2893 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2894 }
2895
2896 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
2897 for (j = 0; j < reg_grps[i].num_row; j++) {
2898 error = iqs7222_parse_reg_grp(iqs7222, i, j);
2899 if (error)
2900 return error;
2901 }
2902 }
2903
2904 return 0;
2905 }
2906
iqs7222_report(struct iqs7222_private * iqs7222)2907 static int iqs7222_report(struct iqs7222_private *iqs7222)
2908 {
2909 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2910 struct i2c_client *client = iqs7222->client;
2911 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2912 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2913 int error, i, j;
2914 __le16 status[IQS7222_MAX_COLS_STAT];
2915
2916 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2917 num_stat * sizeof(*status));
2918 if (error)
2919 return error;
2920
2921 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2922 dev_err(&client->dev, "Unexpected device reset\n");
2923 return iqs7222_dev_init(iqs7222, WRITE);
2924 }
2925
2926 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2927 dev_err(&client->dev, "Unexpected ATI error\n");
2928 return iqs7222_ati_trigger(iqs7222);
2929 }
2930
2931 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2932 return 0;
2933
2934 for (i = 0; i < num_chan; i++) {
2935 u16 *chan_setup = iqs7222->chan_setup[i];
2936
2937 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2938 continue;
2939
2940 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2941 /*
2942 * Proximity state begins at offset 2 and spills into
2943 * offset 3 for devices with more than 16 channels.
2944 *
2945 * Touch state begins at the first offset immediately
2946 * following proximity state.
2947 */
2948 int k = 2 + j * (num_chan > 16 ? 2 : 1);
2949 u16 state = le16_to_cpu(status[k + i / 16]);
2950
2951 if (!iqs7222->kp_type[i][j])
2952 continue;
2953
2954 input_event(iqs7222->keypad,
2955 iqs7222->kp_type[i][j],
2956 iqs7222->kp_code[i][j],
2957 !!(state & BIT(i % 16)));
2958 }
2959 }
2960
2961 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2962 u16 *sldr_setup = iqs7222->sldr_setup[i];
2963 u16 sldr_pos = le16_to_cpu(status[4 + i]);
2964 u16 state = le16_to_cpu(status[6 + i]);
2965
2966 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2967 continue;
2968
2969 if (sldr_pos < dev_desc->sldr_res)
2970 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2971 sldr_pos);
2972
2973 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],
2974 sldr_pos < dev_desc->sldr_res);
2975
2976 /*
2977 * A maximum resolution indicates the device does not support
2978 * gestures, in which case the remaining fields are ignored.
2979 */
2980 if (dev_desc->sldr_res == U16_MAX)
2981 continue;
2982
2983 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2984 continue;
2985
2986 /*
2987 * Skip the press/release event, as it does not have separate
2988 * status fields and is handled separately.
2989 */
2990 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2991 u16 mask = iqs7222_sl_events[j].mask;
2992 u16 val = iqs7222_sl_events[j].val;
2993
2994 input_report_key(iqs7222->keypad,
2995 iqs7222->sl_code[i][j],
2996 (state & mask) == val);
2997 }
2998
2999 input_sync(iqs7222->keypad);
3000
3001 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
3002 input_report_key(iqs7222->keypad,
3003 iqs7222->sl_code[i][j], 0);
3004 }
3005
3006 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) {
3007 u16 tpad_pos_x = le16_to_cpu(status[4]);
3008 u16 tpad_pos_y = le16_to_cpu(status[5]);
3009 u16 state = le16_to_cpu(status[6]);
3010
3011 input_report_key(iqs7222->keypad, iqs7222->tp_code[0],
3012 tpad_pos_x < U16_MAX);
3013
3014 if (tpad_pos_x < U16_MAX)
3015 touchscreen_report_pos(iqs7222->keypad, &iqs7222->prop,
3016 tpad_pos_x, tpad_pos_y, false);
3017
3018 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_TPAD))
3019 continue;
3020
3021 /*
3022 * Skip the press/release event, as it does not have separate
3023 * status fields and is handled separately.
3024 */
3025 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++) {
3026 u16 mask = iqs7222_tp_events[j].mask;
3027 u16 val = iqs7222_tp_events[j].val;
3028
3029 input_report_key(iqs7222->keypad,
3030 iqs7222->tp_code[j],
3031 (state & mask) == val);
3032 }
3033
3034 input_sync(iqs7222->keypad);
3035
3036 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++)
3037 input_report_key(iqs7222->keypad,
3038 iqs7222->tp_code[j], 0);
3039 }
3040
3041 input_sync(iqs7222->keypad);
3042
3043 return 0;
3044 }
3045
iqs7222_irq(int irq,void * context)3046 static irqreturn_t iqs7222_irq(int irq, void *context)
3047 {
3048 struct iqs7222_private *iqs7222 = context;
3049
3050 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
3051 }
3052
iqs7222_probe(struct i2c_client * client)3053 static int iqs7222_probe(struct i2c_client *client)
3054 {
3055 struct iqs7222_private *iqs7222;
3056 unsigned long irq_flags;
3057 int error, irq;
3058
3059 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
3060 if (!iqs7222)
3061 return -ENOMEM;
3062
3063 i2c_set_clientdata(client, iqs7222);
3064 iqs7222->client = client;
3065
3066 iqs7222->keypad = devm_input_allocate_device(&client->dev);
3067 if (!iqs7222->keypad)
3068 return -ENOMEM;
3069
3070 iqs7222->keypad->name = client->name;
3071 iqs7222->keypad->id.bustype = BUS_I2C;
3072
3073 /*
3074 * The RDY pin behaves as an interrupt, but must also be polled ahead
3075 * of unsolicited I2C communication. As such, it is first opened as a
3076 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
3077 */
3078 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
3079 if (IS_ERR(iqs7222->irq_gpio)) {
3080 error = PTR_ERR(iqs7222->irq_gpio);
3081 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
3082 error);
3083 return error;
3084 }
3085
3086 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3087 GPIOD_OUT_HIGH);
3088 if (IS_ERR(iqs7222->reset_gpio)) {
3089 error = PTR_ERR(iqs7222->reset_gpio);
3090 dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
3091 error);
3092 return error;
3093 }
3094
3095 error = iqs7222_hard_reset(iqs7222);
3096 if (error)
3097 return error;
3098
3099 error = iqs7222_dev_info(iqs7222);
3100 if (error)
3101 return error;
3102
3103 error = iqs7222_dev_init(iqs7222, READ);
3104 if (error)
3105 return error;
3106
3107 error = iqs7222_parse_all(iqs7222);
3108 if (error)
3109 return error;
3110
3111 error = iqs7222_dev_init(iqs7222, WRITE);
3112 if (error)
3113 return error;
3114
3115 error = iqs7222_report(iqs7222);
3116 if (error)
3117 return error;
3118
3119 error = input_register_device(iqs7222->keypad);
3120 if (error) {
3121 dev_err(&client->dev, "Failed to register device: %d\n", error);
3122 return error;
3123 }
3124
3125 irq = gpiod_to_irq(iqs7222->irq_gpio);
3126 if (irq < 0)
3127 return irq;
3128
3129 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
3130 : IRQF_TRIGGER_HIGH;
3131 irq_flags |= IRQF_ONESHOT;
3132
3133 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
3134 irq_flags, client->name, iqs7222);
3135 if (error)
3136 dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
3137
3138 return error;
3139 }
3140
3141 static const struct of_device_id iqs7222_of_match[] = {
3142 { .compatible = "azoteq,iqs7222a" },
3143 { .compatible = "azoteq,iqs7222b" },
3144 { .compatible = "azoteq,iqs7222c" },
3145 { .compatible = "azoteq,iqs7222d" },
3146 { }
3147 };
3148 MODULE_DEVICE_TABLE(of, iqs7222_of_match);
3149
3150 static struct i2c_driver iqs7222_i2c_driver = {
3151 .driver = {
3152 .name = "iqs7222",
3153 .of_match_table = iqs7222_of_match,
3154 },
3155 .probe = iqs7222_probe,
3156 };
3157 module_i2c_driver(iqs7222_i2c_driver);
3158
3159 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
3160 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C/D Capacitive Touch Controller");
3161 MODULE_LICENSE("GPL");
3162