1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28
29 #include "dc_types.h"
30 #include "core_types.h"
31
32 #include "include/grph_object_id.h"
33 #include "include/logger_interface.h"
34
35 #include "dce_clock_source.h"
36 #include "clk_mgr.h"
37 #include "dccg.h"
38
39 #include "reg_helper.h"
40
41 #define REG(reg)\
42 (clk_src->regs->reg)
43
44 #define CTX \
45 clk_src->base.ctx
46
47 #define DC_LOGGER \
48 calc_pll_cs->ctx->logger
49 #define DC_LOGGER_INIT() \
50 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll
51
52 #undef FN
53 #define FN(reg_name, field_name) \
54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
55
56 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
57 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
58 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
59
get_ss_data_entry(struct dce110_clk_src * clk_src,enum signal_type signal,uint32_t pix_clk_khz)60 static const struct spread_spectrum_data *get_ss_data_entry(
61 struct dce110_clk_src *clk_src,
62 enum signal_type signal,
63 uint32_t pix_clk_khz)
64 {
65
66 uint32_t entrys_num;
67 uint32_t i;
68 struct spread_spectrum_data *ss_parm = NULL;
69 struct spread_spectrum_data *ret = NULL;
70
71 switch (signal) {
72 case SIGNAL_TYPE_DVI_SINGLE_LINK:
73 case SIGNAL_TYPE_DVI_DUAL_LINK:
74 ss_parm = clk_src->dvi_ss_params;
75 entrys_num = clk_src->dvi_ss_params_cnt;
76 break;
77
78 case SIGNAL_TYPE_HDMI_TYPE_A:
79 ss_parm = clk_src->hdmi_ss_params;
80 entrys_num = clk_src->hdmi_ss_params_cnt;
81 break;
82
83 case SIGNAL_TYPE_LVDS:
84 ss_parm = clk_src->lvds_ss_params;
85 entrys_num = clk_src->lvds_ss_params_cnt;
86 break;
87
88 case SIGNAL_TYPE_DISPLAY_PORT:
89 case SIGNAL_TYPE_DISPLAY_PORT_MST:
90 case SIGNAL_TYPE_EDP:
91 case SIGNAL_TYPE_VIRTUAL:
92 ss_parm = clk_src->dp_ss_params;
93 entrys_num = clk_src->dp_ss_params_cnt;
94 break;
95
96 default:
97 ss_parm = NULL;
98 entrys_num = 0;
99 break;
100 }
101
102 if (ss_parm == NULL)
103 return ret;
104
105 for (i = 0; i < entrys_num; ++i, ++ss_parm) {
106 if (ss_parm->freq_range_khz >= pix_clk_khz) {
107 ret = ss_parm;
108 break;
109 }
110 }
111
112 return ret;
113 }
114
115 /**
116 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
117 * feedback dividers values
118 *
119 * @calc_pll_cs: Pointer to clock source information
120 * @target_pix_clk_100hz: Desired frequency in 100 Hz
121 * @ref_divider: Reference divider (already known)
122 * @post_divider: Post Divider (already known)
123 * @feedback_divider_param: Pointer where to store
124 * calculated feedback divider value
125 * @fract_feedback_divider_param: Pointer where to store
126 * calculated fract feedback divider value
127 *
128 * return:
129 * It fills the locations pointed by feedback_divider_param
130 * and fract_feedback_divider_param
131 * It returns - true if feedback divider not 0
132 * - false should never happen)
133 */
calculate_fb_and_fractional_fb_divider(struct calc_pll_clock_source * calc_pll_cs,uint32_t target_pix_clk_100hz,uint32_t ref_divider,uint32_t post_divider,uint32_t * feedback_divider_param,uint32_t * fract_feedback_divider_param)134 static bool calculate_fb_and_fractional_fb_divider(
135 struct calc_pll_clock_source *calc_pll_cs,
136 uint32_t target_pix_clk_100hz,
137 uint32_t ref_divider,
138 uint32_t post_divider,
139 uint32_t *feedback_divider_param,
140 uint32_t *fract_feedback_divider_param)
141 {
142 uint64_t feedback_divider;
143
144 feedback_divider =
145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
146 feedback_divider *= 10;
147 /* additional factor, since we divide by 10 afterwards */
148 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
149 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
150
151 /*Round to the number of precision
152 * The following code replace the old code (ullfeedbackDivider + 5)/10
153 * for example if the difference between the number
154 * of fractional feedback decimal point and the fractional FB Divider precision
155 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
156
157 feedback_divider += 5ULL *
158 calc_pll_cs->fract_fb_divider_precision_factor;
159 feedback_divider =
160 div_u64(feedback_divider,
161 calc_pll_cs->fract_fb_divider_precision_factor * 10);
162 feedback_divider *= (uint64_t)
163 (calc_pll_cs->fract_fb_divider_precision_factor);
164
165 *feedback_divider_param =
166 div_u64_rem(
167 feedback_divider,
168 calc_pll_cs->fract_fb_divider_factor,
169 fract_feedback_divider_param);
170
171 if (*feedback_divider_param != 0)
172 return true;
173 return false;
174 }
175
176 /**
177 * calc_fb_divider_checking_tolerance - Calculates Feedback and
178 * Fractional Feedback divider values
179 * for passed Reference and Post divider,
180 * checking for tolerance.
181 * @calc_pll_cs: Pointer to clock source information
182 * @pll_settings: Pointer to PLL settings
183 * @ref_divider: Reference divider (already known)
184 * @post_divider: Post Divider (already known)
185 * @tolerance: Tolerance for Calculated Pixel Clock to be within
186 *
187 * return:
188 * It fills the PLLSettings structure with PLL Dividers values
189 * if calculated values are within required tolerance
190 * It returns - true if error is within tolerance
191 * - false if error is not within tolerance
192 */
calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance)193 static bool calc_fb_divider_checking_tolerance(
194 struct calc_pll_clock_source *calc_pll_cs,
195 struct pll_settings *pll_settings,
196 uint32_t ref_divider,
197 uint32_t post_divider,
198 uint32_t tolerance)
199 {
200 uint32_t feedback_divider;
201 uint32_t fract_feedback_divider;
202 uint32_t actual_calculated_clock_100hz;
203 uint32_t abs_err;
204 uint64_t actual_calc_clk_100hz;
205
206 calculate_fb_and_fractional_fb_divider(
207 calc_pll_cs,
208 pll_settings->adjusted_pix_clk_100hz,
209 ref_divider,
210 post_divider,
211 &feedback_divider,
212 &fract_feedback_divider);
213
214 /*Actual calculated value*/
215 actual_calc_clk_100hz = (uint64_t)feedback_divider *
216 calc_pll_cs->fract_fb_divider_factor +
217 fract_feedback_divider;
218 actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10;
219 actual_calc_clk_100hz =
220 div_u64(actual_calc_clk_100hz,
221 ref_divider * post_divider *
222 calc_pll_cs->fract_fb_divider_factor);
223
224 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
225
226 abs_err = (actual_calculated_clock_100hz >
227 pll_settings->adjusted_pix_clk_100hz)
228 ? actual_calculated_clock_100hz -
229 pll_settings->adjusted_pix_clk_100hz
230 : pll_settings->adjusted_pix_clk_100hz -
231 actual_calculated_clock_100hz;
232
233 if (abs_err <= tolerance) {
234 /*found good values*/
235 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
236 pll_settings->reference_divider = ref_divider;
237 pll_settings->feedback_divider = feedback_divider;
238 pll_settings->fract_feedback_divider = fract_feedback_divider;
239 pll_settings->pix_clk_post_divider = post_divider;
240 pll_settings->calculated_pix_clk_100hz =
241 actual_calculated_clock_100hz;
242 pll_settings->vco_freq =
243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
244 return true;
245 }
246 return false;
247 }
248
calc_pll_dividers_in_range(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t min_ref_divider,uint32_t max_ref_divider,uint32_t min_post_divider,uint32_t max_post_divider,uint32_t err_tolerance)249 static bool calc_pll_dividers_in_range(
250 struct calc_pll_clock_source *calc_pll_cs,
251 struct pll_settings *pll_settings,
252 uint32_t min_ref_divider,
253 uint32_t max_ref_divider,
254 uint32_t min_post_divider,
255 uint32_t max_post_divider,
256 uint32_t err_tolerance)
257 {
258 uint32_t ref_divider;
259 uint32_t post_divider;
260 uint32_t tolerance;
261
262 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
263 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
264 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
265 100000;
266 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
267 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
268
269 for (
270 post_divider = max_post_divider;
271 post_divider >= min_post_divider;
272 --post_divider) {
273 for (
274 ref_divider = min_ref_divider;
275 ref_divider <= max_ref_divider;
276 ++ref_divider) {
277 if (calc_fb_divider_checking_tolerance(
278 calc_pll_cs,
279 pll_settings,
280 ref_divider,
281 post_divider,
282 tolerance)) {
283 return true;
284 }
285 }
286 }
287
288 return false;
289 }
290
calculate_pixel_clock_pll_dividers(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings)291 static uint32_t calculate_pixel_clock_pll_dividers(
292 struct calc_pll_clock_source *calc_pll_cs,
293 struct pll_settings *pll_settings)
294 {
295 uint32_t err_tolerance;
296 uint32_t min_post_divider;
297 uint32_t max_post_divider;
298 uint32_t min_ref_divider;
299 uint32_t max_ref_divider;
300
301 if (pll_settings->adjusted_pix_clk_100hz == 0) {
302 DC_LOG_ERROR(
303 "%s Bad requested pixel clock", __func__);
304 return MAX_PLL_CALC_ERROR;
305 }
306
307 /* 1) Find Post divider ranges */
308 if (pll_settings->pix_clk_post_divider) {
309 min_post_divider = pll_settings->pix_clk_post_divider;
310 max_post_divider = pll_settings->pix_clk_post_divider;
311 } else {
312 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
313 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
314 calc_pll_cs->min_vco_khz * 10) {
315 min_post_divider = calc_pll_cs->min_vco_khz * 10 /
316 pll_settings->adjusted_pix_clk_100hz;
317 if ((min_post_divider *
318 pll_settings->adjusted_pix_clk_100hz) <
319 calc_pll_cs->min_vco_khz * 10)
320 min_post_divider++;
321 }
322
323 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
324 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
325 > calc_pll_cs->max_vco_khz * 10)
326 max_post_divider = calc_pll_cs->max_vco_khz * 10 /
327 pll_settings->adjusted_pix_clk_100hz;
328 }
329
330 /* 2) Find Reference divider ranges
331 * When SS is enabled, or for Display Port even without SS,
332 * pll_settings->referenceDivider is not zero.
333 * So calculate PPLL FB and fractional FB divider
334 * using the passed reference divider*/
335
336 if (pll_settings->reference_divider) {
337 min_ref_divider = pll_settings->reference_divider;
338 max_ref_divider = pll_settings->reference_divider;
339 } else {
340 min_ref_divider = ((calc_pll_cs->ref_freq_khz
341 / calc_pll_cs->max_pll_input_freq_khz)
342 > calc_pll_cs->min_pll_ref_divider)
343 ? calc_pll_cs->ref_freq_khz
344 / calc_pll_cs->max_pll_input_freq_khz
345 : calc_pll_cs->min_pll_ref_divider;
346
347 max_ref_divider = ((calc_pll_cs->ref_freq_khz
348 / calc_pll_cs->min_pll_input_freq_khz)
349 < calc_pll_cs->max_pll_ref_divider)
350 ? calc_pll_cs->ref_freq_khz /
351 calc_pll_cs->min_pll_input_freq_khz
352 : calc_pll_cs->max_pll_ref_divider;
353 }
354
355 /* If some parameters are invalid we could have scenario when "min">"max"
356 * which produced endless loop later.
357 * We should investigate why we get the wrong parameters.
358 * But to follow the similar logic when "adjustedPixelClock" is set to be 0
359 * it is better to return here than cause system hang/watchdog timeout later.
360 * ## SVS Wed 15 Jul 2009 */
361
362 if (min_post_divider > max_post_divider) {
363 DC_LOG_ERROR(
364 "%s Post divider range is invalid", __func__);
365 return MAX_PLL_CALC_ERROR;
366 }
367
368 if (min_ref_divider > max_ref_divider) {
369 DC_LOG_ERROR(
370 "%s Reference divider range is invalid", __func__);
371 return MAX_PLL_CALC_ERROR;
372 }
373
374 /* 3) Try to find PLL dividers given ranges
375 * starting with minimal error tolerance.
376 * Increase error tolerance until PLL dividers found*/
377 err_tolerance = MAX_PLL_CALC_ERROR;
378
379 while (!calc_pll_dividers_in_range(
380 calc_pll_cs,
381 pll_settings,
382 min_ref_divider,
383 max_ref_divider,
384 min_post_divider,
385 max_post_divider,
386 err_tolerance))
387 err_tolerance += (err_tolerance > 10)
388 ? (err_tolerance / 10)
389 : 1;
390
391 return err_tolerance;
392 }
393
pll_adjust_pix_clk(struct dce110_clk_src * clk_src,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)394 static bool pll_adjust_pix_clk(
395 struct dce110_clk_src *clk_src,
396 struct pixel_clk_params *pix_clk_params,
397 struct pll_settings *pll_settings)
398 {
399 uint32_t actual_pix_clk_100hz = 0;
400 uint32_t requested_clk_100hz = 0;
401 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
402 0 };
403 enum bp_result bp_result;
404 switch (pix_clk_params->signal_type) {
405 case SIGNAL_TYPE_HDMI_TYPE_A: {
406 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
407 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
408 switch (pix_clk_params->color_depth) {
409 case COLOR_DEPTH_101010:
410 requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
411 break; /* x1.25*/
412 case COLOR_DEPTH_121212:
413 requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
414 break; /* x1.5*/
415 case COLOR_DEPTH_161616:
416 requested_clk_100hz = requested_clk_100hz * 2;
417 break; /* x2.0*/
418 default:
419 break;
420 }
421 }
422 actual_pix_clk_100hz = requested_clk_100hz;
423 }
424 break;
425
426 case SIGNAL_TYPE_DISPLAY_PORT:
427 case SIGNAL_TYPE_DISPLAY_PORT_MST:
428 case SIGNAL_TYPE_EDP:
429 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
430 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
431 break;
432
433 default:
434 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
435 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
436 break;
437 }
438
439 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
440 bp_adjust_pixel_clock_params.
441 encoder_object_id = pix_clk_params->encoder_object_id;
442 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
443 bp_adjust_pixel_clock_params.
444 ss_enable = pix_clk_params->flags.ENABLE_SS;
445 bp_result = clk_src->bios->funcs->adjust_pixel_clock(
446 clk_src->bios, &bp_adjust_pixel_clock_params);
447 if (bp_result == BP_RESULT_OK) {
448 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
449 pll_settings->adjusted_pix_clk_100hz =
450 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
451 pll_settings->reference_divider =
452 bp_adjust_pixel_clock_params.reference_divider;
453 pll_settings->pix_clk_post_divider =
454 bp_adjust_pixel_clock_params.pixel_clock_post_divider;
455
456 return true;
457 }
458
459 return false;
460 }
461
462 /*
463 * Calculate PLL Dividers for given Clock Value.
464 * First will call VBIOS Adjust Exec table to check if requested Pixel clock
465 * will be Adjusted based on usage.
466 * Then it will calculate PLL Dividers for this Adjusted clock using preferred
467 * method (Maximum VCO frequency).
468 *
469 * \return
470 * Calculation error in units of 0.01%
471 */
472
dce110_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)473 static uint32_t dce110_get_pix_clk_dividers_helper (
474 struct dce110_clk_src *clk_src,
475 struct pll_settings *pll_settings,
476 struct pixel_clk_params *pix_clk_params)
477 {
478 uint32_t field = 0;
479 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
480 DC_LOGGER_INIT();
481 /* Check if reference clock is external (not pcie/xtalin)
482 * HW Dce80 spec:
483 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
484 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
485 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
486 pll_settings->use_external_clk = (field > 1);
487
488 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
489 * (we do not care any more from SI for some older DP Sink which
490 * does not report SS support, no known issues) */
491 if ((pix_clk_params->flags.ENABLE_SS) ||
492 (dc_is_dp_signal(pix_clk_params->signal_type))) {
493
494 const struct spread_spectrum_data *ss_data = get_ss_data_entry(
495 clk_src,
496 pix_clk_params->signal_type,
497 pll_settings->adjusted_pix_clk_100hz / 10);
498
499 if (NULL != ss_data)
500 pll_settings->ss_percentage = ss_data->percentage;
501 }
502
503 /* Check VBIOS AdjustPixelClock Exec table */
504 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
505 /* Should never happen, ASSERT and fill up values to be able
506 * to continue. */
507 DC_LOG_ERROR(
508 "%s: Failed to adjust pixel clock!!", __func__);
509 pll_settings->actual_pix_clk_100hz =
510 pix_clk_params->requested_pix_clk_100hz;
511 pll_settings->adjusted_pix_clk_100hz =
512 pix_clk_params->requested_pix_clk_100hz;
513
514 if (dc_is_dp_signal(pix_clk_params->signal_type))
515 pll_settings->adjusted_pix_clk_100hz = 1000000;
516 }
517
518 /* Calculate Dividers */
519 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
520 /*Calculate Dividers by HDMI object, no SS case or SS case */
521 pll_calc_error =
522 calculate_pixel_clock_pll_dividers(
523 &clk_src->calc_pll_hdmi,
524 pll_settings);
525 else
526 /*Calculate Dividers by default object, no SS case or SS case */
527 pll_calc_error =
528 calculate_pixel_clock_pll_dividers(
529 &clk_src->calc_pll,
530 pll_settings);
531
532 return pll_calc_error;
533 }
534
dce112_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)535 static void dce112_get_pix_clk_dividers_helper (
536 struct dce110_clk_src *clk_src,
537 struct pll_settings *pll_settings,
538 struct pixel_clk_params *pix_clk_params)
539 {
540 (void)clk_src;
541 uint32_t actual_pixel_clock_100hz;
542
543 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
544 /* Calculate Dividers */
545 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
546 switch (pix_clk_params->color_depth) {
547 case COLOR_DEPTH_101010:
548 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
549 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
550 break;
551 case COLOR_DEPTH_121212:
552 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
553 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
554 break;
555 case COLOR_DEPTH_161616:
556 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
557 break;
558 default:
559 break;
560 }
561 }
562 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
563 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
564 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
565 }
566
dce110_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)567 static uint32_t dce110_get_pix_clk_dividers(
568 struct clock_source *cs,
569 struct pixel_clk_params *pix_clk_params,
570 struct pll_settings *pll_settings)
571 {
572 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
573 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
574 DC_LOGGER_INIT();
575
576 if (pix_clk_params == NULL || pll_settings == NULL
577 || pix_clk_params->requested_pix_clk_100hz == 0) {
578 DC_LOG_ERROR(
579 "%s: Invalid parameters!!\n", __func__);
580 return pll_calc_error;
581 }
582
583 memset(pll_settings, 0, sizeof(*pll_settings));
584
585 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
586 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
587 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
588 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
589 pll_settings->actual_pix_clk_100hz =
590 pix_clk_params->requested_pix_clk_100hz;
591 return 0;
592 }
593
594 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
595 pll_settings, pix_clk_params);
596
597 return pll_calc_error;
598 }
599
dce112_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)600 static uint32_t dce112_get_pix_clk_dividers(
601 struct clock_source *cs,
602 struct pixel_clk_params *pix_clk_params,
603 struct pll_settings *pll_settings)
604 {
605 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
606 DC_LOGGER_INIT();
607
608 if (pix_clk_params == NULL || pll_settings == NULL
609 || pix_clk_params->requested_pix_clk_100hz == 0) {
610 DC_LOG_ERROR(
611 "%s: Invalid parameters!!\n", __func__);
612 return (uint32_t)-1;
613 }
614
615 memset(pll_settings, 0, sizeof(*pll_settings));
616
617 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
618 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
619 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
620 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
621 pll_settings->actual_pix_clk_100hz =
622 pix_clk_params->requested_pix_clk_100hz;
623 return (uint32_t)-1;
624 }
625
626 dce112_get_pix_clk_dividers_helper(clk_src,
627 pll_settings, pix_clk_params);
628
629 return 0;
630 }
631
disable_spread_spectrum(struct dce110_clk_src * clk_src)632 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
633 {
634 enum bp_result result;
635 struct bp_spread_spectrum_parameters bp_ss_params = {0};
636
637 bp_ss_params.pll_id = clk_src->base.id;
638
639 /*Call ASICControl to process ATOMBIOS Exec table*/
640 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
641 clk_src->bios,
642 &bp_ss_params,
643 false);
644
645 return result == BP_RESULT_OK;
646 }
647
calculate_ss(const struct pll_settings * pll_settings,const struct spread_spectrum_data * ss_data,struct delta_sigma_data * ds_data)648 static bool calculate_ss(
649 const struct pll_settings *pll_settings,
650 const struct spread_spectrum_data *ss_data,
651 struct delta_sigma_data *ds_data)
652 {
653 struct fixed31_32 fb_div;
654 struct fixed31_32 ss_amount;
655 struct fixed31_32 ss_nslip_amount;
656 struct fixed31_32 ss_ds_frac_amount;
657 struct fixed31_32 ss_step_size;
658 struct fixed31_32 modulation_time;
659
660 if (ds_data == NULL)
661 return false;
662 if (ss_data == NULL)
663 return false;
664 if (ss_data->percentage == 0)
665 return false;
666 if (pll_settings == NULL)
667 return false;
668
669 memset(ds_data, 0, sizeof(struct delta_sigma_data));
670
671 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
672 /* 6 decimal point support in fractional feedback divider */
673 fb_div = dc_fixpt_from_fraction(
674 pll_settings->fract_feedback_divider, 1000000);
675 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
676
677 ds_data->ds_frac_amount = 0;
678 /*spreadSpectrumPercentage is in the unit of .01%,
679 * so have to divided by 100 * 100*/
680 ss_amount = dc_fixpt_mul(
681 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
682 100 * (long long)ss_data->percentage_divider));
683 ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
684
685 ss_nslip_amount = dc_fixpt_sub(ss_amount,
686 dc_fixpt_from_int(ds_data->feedback_amount));
687 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
688 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
689
690 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
691 dc_fixpt_from_int(ds_data->nfrac_amount));
692 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
693 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
694
695 /* compute SS_STEP_SIZE_DSFRAC */
696 modulation_time = dc_fixpt_from_fraction(
697 pll_settings->reference_freq * (uint64_t)1000,
698 pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz);
699
700 if (ss_data->flags.CENTER_SPREAD)
701 modulation_time = dc_fixpt_div_int(modulation_time, 4);
702 else
703 modulation_time = dc_fixpt_div_int(modulation_time, 2);
704
705 ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
706 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
707 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
708 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size);
709
710 return true;
711 }
712
enable_spread_spectrum(struct dce110_clk_src * clk_src,enum signal_type signal,struct pll_settings * pll_settings)713 static bool enable_spread_spectrum(
714 struct dce110_clk_src *clk_src,
715 enum signal_type signal, struct pll_settings *pll_settings)
716 {
717 struct bp_spread_spectrum_parameters bp_params = {0};
718 struct delta_sigma_data d_s_data;
719 const struct spread_spectrum_data *ss_data = NULL;
720
721 ss_data = get_ss_data_entry(
722 clk_src,
723 signal,
724 pll_settings->calculated_pix_clk_100hz / 10);
725
726 /* Pixel clock PLL has been programmed to generate desired pixel clock,
727 * now enable SS on pixel clock */
728 /* TODO is it OK to return true not doing anything ??*/
729 if (ss_data != NULL && pll_settings->ss_percentage != 0) {
730 if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
731 bp_params.ds.feedback_amount =
732 d_s_data.feedback_amount;
733 bp_params.ds.nfrac_amount =
734 d_s_data.nfrac_amount;
735 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
736 bp_params.ds_frac_amount =
737 d_s_data.ds_frac_amount;
738 bp_params.flags.DS_TYPE = 1;
739 bp_params.pll_id = clk_src->base.id;
740 bp_params.percentage = ss_data->percentage;
741 if (ss_data->flags.CENTER_SPREAD)
742 bp_params.flags.CENTER_SPREAD = 1;
743 if (ss_data->flags.EXTERNAL_SS)
744 bp_params.flags.EXTERNAL_SS = 1;
745
746 if (BP_RESULT_OK !=
747 clk_src->bios->funcs->
748 enable_spread_spectrum_on_ppll(
749 clk_src->bios,
750 &bp_params,
751 true))
752 return false;
753 } else
754 return false;
755 }
756 return true;
757 }
758
dce110_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth)759 static void dce110_program_pixel_clk_resync(
760 struct dce110_clk_src *clk_src,
761 enum signal_type signal_type,
762 enum dc_color_depth colordepth)
763 {
764 REG_UPDATE(RESYNC_CNTL,
765 DCCG_DEEP_COLOR_CNTL1, 0);
766 /*
767 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
768 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
769 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
770 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
771 */
772 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
773 return;
774
775 switch (colordepth) {
776 case COLOR_DEPTH_888:
777 REG_UPDATE(RESYNC_CNTL,
778 DCCG_DEEP_COLOR_CNTL1, 0);
779 break;
780 case COLOR_DEPTH_101010:
781 REG_UPDATE(RESYNC_CNTL,
782 DCCG_DEEP_COLOR_CNTL1, 1);
783 break;
784 case COLOR_DEPTH_121212:
785 REG_UPDATE(RESYNC_CNTL,
786 DCCG_DEEP_COLOR_CNTL1, 2);
787 break;
788 case COLOR_DEPTH_161616:
789 REG_UPDATE(RESYNC_CNTL,
790 DCCG_DEEP_COLOR_CNTL1, 3);
791 break;
792 default:
793 break;
794 }
795 }
796
dce112_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth,bool enable_ycbcr420)797 static void dce112_program_pixel_clk_resync(
798 struct dce110_clk_src *clk_src,
799 enum signal_type signal_type,
800 enum dc_color_depth colordepth,
801 bool enable_ycbcr420)
802 {
803 uint32_t deep_color_cntl = 0;
804 uint32_t double_rate_enable = 0;
805
806 /*
807 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
808 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
809 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
810 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
811 */
812 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
813 double_rate_enable = enable_ycbcr420 ? 1 : 0;
814
815 switch (colordepth) {
816 case COLOR_DEPTH_888:
817 deep_color_cntl = 0;
818 break;
819 case COLOR_DEPTH_101010:
820 deep_color_cntl = 1;
821 break;
822 case COLOR_DEPTH_121212:
823 deep_color_cntl = 2;
824 break;
825 case COLOR_DEPTH_161616:
826 deep_color_cntl = 3;
827 break;
828 default:
829 break;
830 }
831 }
832
833 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
834 REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
835 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
836 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
837 else
838 REG_UPDATE(PIXCLK_RESYNC_CNTL,
839 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
840
841 }
842
dce110_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)843 static bool dce110_program_pix_clk(
844 struct clock_source *clock_source,
845 struct pixel_clk_params *pix_clk_params,
846 enum dp_link_encoding encoding,
847 struct pll_settings *pll_settings)
848 {
849 (void)encoding;
850 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
851 struct bp_pixel_clock_parameters bp_pc_params = {0};
852
853 /* First disable SS
854 * ATOMBIOS will enable by default SS on PLL for DP,
855 * do not disable it here
856 */
857 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
858 !dc_is_dp_signal(pix_clk_params->signal_type) &&
859 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
860 disable_spread_spectrum(clk_src);
861
862 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
863 bp_pc_params.controller_id = pix_clk_params->controller_id;
864 bp_pc_params.pll_id = clock_source->id;
865 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
866 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
867 bp_pc_params.signal_type = pix_clk_params->signal_type;
868
869 bp_pc_params.reference_divider = pll_settings->reference_divider;
870 bp_pc_params.feedback_divider = pll_settings->feedback_divider;
871 bp_pc_params.fractional_feedback_divider =
872 pll_settings->fract_feedback_divider;
873 bp_pc_params.pixel_clock_post_divider =
874 pll_settings->pix_clk_post_divider;
875 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
876 pll_settings->use_external_clk;
877
878 switch (pix_clk_params->color_depth) {
879 case COLOR_DEPTH_101010:
880 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
881 break;
882 case COLOR_DEPTH_121212:
883 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
884 break;
885 case COLOR_DEPTH_161616:
886 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
887 break;
888 default:
889 break;
890 }
891
892 if (clk_src->bios->funcs->set_pixel_clock(
893 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
894 return false;
895 /* Enable SS
896 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
897 * based on HW display PLL team, SS control settings should be programmed
898 * during PLL Reset, but they do not have effect
899 * until SS_EN is asserted.*/
900 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
901 && !dc_is_dp_signal(pix_clk_params->signal_type)) {
902
903 if (pix_clk_params->flags.ENABLE_SS)
904 if (!enable_spread_spectrum(clk_src,
905 pix_clk_params->signal_type,
906 pll_settings))
907 return false;
908
909 /* Resync deep color DTO */
910 dce110_program_pixel_clk_resync(clk_src,
911 pix_clk_params->signal_type,
912 pix_clk_params->color_depth);
913 }
914
915 return true;
916 }
917
dce112_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)918 static bool dce112_program_pix_clk(
919 struct clock_source *clock_source,
920 struct pixel_clk_params *pix_clk_params,
921 enum dp_link_encoding encoding,
922 struct pll_settings *pll_settings)
923 {
924 (void)encoding;
925 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
926 struct bp_pixel_clock_parameters bp_pc_params = {0};
927
928 /* First disable SS
929 * ATOMBIOS will enable by default SS on PLL for DP,
930 * do not disable it here
931 */
932 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
933 !dc_is_dp_signal(pix_clk_params->signal_type) &&
934 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
935 disable_spread_spectrum(clk_src);
936
937 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
938 bp_pc_params.controller_id = pix_clk_params->controller_id;
939 bp_pc_params.pll_id = clock_source->id;
940 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
941 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
942 bp_pc_params.signal_type = pix_clk_params->signal_type;
943
944 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
945 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
946 pll_settings->use_external_clk;
947 bp_pc_params.flags.SET_XTALIN_REF_SRC =
948 !pll_settings->use_external_clk;
949 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
950 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
951 }
952 }
953 if (clk_src->bios->funcs->set_pixel_clock(
954 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
955 return false;
956 /* Resync deep color DTO */
957 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
958 dce112_program_pixel_clk_resync(clk_src,
959 pix_clk_params->signal_type,
960 pix_clk_params->color_depth,
961 pix_clk_params->flags.SUPPORT_YCBCR420);
962
963 return true;
964 }
965
dcn31_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)966 static bool dcn31_program_pix_clk(
967 struct clock_source *clock_source,
968 struct pixel_clk_params *pix_clk_params,
969 enum dp_link_encoding encoding,
970 struct pll_settings *pll_settings)
971 {
972 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
973 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
974 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
975 const struct pixel_rate_range_table_entry *e =
976 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
977 struct bp_pixel_clock_parameters bp_pc_params = {0};
978 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
979
980 // Apply ssed(spread spectrum) dpref clock for edp and dp
981 if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&
982 dc_is_dp_signal(pix_clk_params->signal_type) &&
983 encoding == DP_8b_10b_ENCODING)
984 dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;
985
986 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
987 if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
988 if (e) {
989 /* Set DTO values: phase = target clock, modulo = reference clock*/
990 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
991 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
992 } else {
993 /* Set DTO values: phase = target clock, modulo = reference clock*/
994 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
995 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
996 }
997 /* Enable DTO */
998 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
999 if (encoding == DP_128b_132b_ENCODING)
1000 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1001 DP_DTO0_ENABLE, 1,
1002 PIPE0_DTO_SRC_SEL, 2);
1003 else
1004 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1005 DP_DTO0_ENABLE, 1,
1006 PIPE0_DTO_SRC_SEL, 1);
1007 else
1008 REG_UPDATE(PIXEL_RATE_CNTL[inst],
1009 DP_DTO0_ENABLE, 1);
1010 } else {
1011
1012 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1013 REG_UPDATE(PIXEL_RATE_CNTL[inst],
1014 PIPE0_DTO_SRC_SEL, 0);
1015
1016 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1017 bp_pc_params.controller_id = pix_clk_params->controller_id;
1018 bp_pc_params.pll_id = clock_source->id;
1019 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1020 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1021 bp_pc_params.signal_type = pix_clk_params->signal_type;
1022
1023 // Make sure we send the correct color depth to DMUB for HDMI
1024 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1025 switch (pix_clk_params->color_depth) {
1026 case COLOR_DEPTH_888:
1027 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1028 break;
1029 case COLOR_DEPTH_101010:
1030 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1031 break;
1032 case COLOR_DEPTH_121212:
1033 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1034 break;
1035 case COLOR_DEPTH_161616:
1036 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1037 break;
1038 default:
1039 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1040 break;
1041 }
1042 bp_pc_params.color_depth = bp_pc_colour_depth;
1043 }
1044
1045 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1046 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1047 pll_settings->use_external_clk;
1048 bp_pc_params.flags.SET_XTALIN_REF_SRC =
1049 !pll_settings->use_external_clk;
1050 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1051 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1052 }
1053 }
1054 if (clk_src->bios->funcs->set_pixel_clock(
1055 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1056 return false;
1057 /* Resync deep color DTO */
1058 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1059 dce112_program_pixel_clk_resync(clk_src,
1060 pix_clk_params->signal_type,
1061 pix_clk_params->color_depth,
1062 pix_clk_params->flags.SUPPORT_YCBCR420);
1063 }
1064
1065 return true;
1066 }
1067
dcn401_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)1068 static bool dcn401_program_pix_clk(
1069 struct clock_source *clock_source,
1070 struct pixel_clk_params *pix_clk_params,
1071 enum dp_link_encoding encoding,
1072 struct pll_settings *pll_settings)
1073 {
1074 (void)encoding;
1075 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1076 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1077 const struct pixel_rate_range_table_entry *e =
1078 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1079 struct bp_pixel_clock_parameters bp_pc_params = {0};
1080 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1081 struct dp_dto_params dto_params = { 0 };
1082
1083 dto_params.otg_inst = inst;
1084 dto_params.signal = pix_clk_params->signal_type;
1085
1086 // all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table
1087 if (!dc_is_tmds_signal(pix_clk_params->signal_type)) {
1088 long long dtbclk_p_src_clk_khz;
1089
1090 dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1091 dto_params.clk_src = DPREFCLK;
1092
1093 if (e) {
1094 dto_params.pixclk_hz = e->target_pixel_rate_khz;
1095 dto_params.pixclk_hz *= e->mult_factor;
1096 dto_params.refclk_hz = dtbclk_p_src_clk_khz;
1097 dto_params.refclk_hz *= e->div_factor;
1098 } else {
1099 dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz;
1100 dto_params.pixclk_hz *= 100;
1101 dto_params.refclk_hz = dtbclk_p_src_clk_khz;
1102 dto_params.refclk_hz *= 1000;
1103 }
1104
1105 /* enable DP DTO */
1106 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
1107 clock_source->ctx->dc->res_pool->dccg,
1108 &dto_params);
1109
1110 } else {
1111 if (pll_settings->actual_pix_clk_100hz > 6000000UL)
1112 return false;
1113
1114 /* disables DP DTO when provided with TMDS signal type */
1115 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
1116 clock_source->ctx->dc->res_pool->dccg,
1117 &dto_params);
1118
1119 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1120 bp_pc_params.controller_id = pix_clk_params->controller_id;
1121 bp_pc_params.pll_id = clock_source->id;
1122 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1123 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1124 bp_pc_params.signal_type = pix_clk_params->signal_type;
1125
1126 // Make sure we send the correct color depth to DMUB for HDMI
1127 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1128 switch (pix_clk_params->color_depth) {
1129 case COLOR_DEPTH_888:
1130 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1131 break;
1132 case COLOR_DEPTH_101010:
1133 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1134 break;
1135 case COLOR_DEPTH_121212:
1136 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1137 break;
1138 case COLOR_DEPTH_161616:
1139 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1140 break;
1141 default:
1142 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1143 break;
1144 }
1145 bp_pc_params.color_depth = bp_pc_colour_depth;
1146 }
1147
1148 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1149 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1150 pll_settings->use_external_clk;
1151 bp_pc_params.flags.SET_XTALIN_REF_SRC =
1152 !pll_settings->use_external_clk;
1153 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1154 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1155 }
1156 }
1157 if (clk_src->bios->funcs->set_pixel_clock(
1158 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1159 return false;
1160 /* Resync deep color DTO */
1161 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1162 dce112_program_pixel_clk_resync(clk_src,
1163 pix_clk_params->signal_type,
1164 pix_clk_params->color_depth,
1165 pix_clk_params->flags.SUPPORT_YCBCR420);
1166 }
1167
1168 return true;
1169 }
1170
dce110_clock_source_power_down(struct clock_source * clk_src)1171 static bool dce110_clock_source_power_down(
1172 struct clock_source *clk_src)
1173 {
1174 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
1175 enum bp_result bp_result;
1176 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
1177
1178 if (clk_src->dp_clk_src)
1179 return true;
1180
1181 /* If Pixel Clock is 0 it means Power Down Pll*/
1182 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
1183 bp_pixel_clock_params.pll_id = clk_src->id;
1184 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
1185
1186 /*Call ASICControl to process ATOMBIOS Exec table*/
1187 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
1188 dce110_clk_src->bios,
1189 &bp_pixel_clock_params);
1190
1191 return bp_result == BP_RESULT_OK;
1192 }
1193
get_pixel_clk_frequency_100hz(const struct clock_source * clock_source,unsigned int inst,unsigned int * pixel_clk_khz)1194 static bool get_pixel_clk_frequency_100hz(
1195 const struct clock_source *clock_source,
1196 unsigned int inst,
1197 unsigned int *pixel_clk_khz)
1198 {
1199 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1200 unsigned int clock_hz = 0;
1201 unsigned int modulo_hz = 0;
1202 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1203
1204 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1205 clock_hz = REG_READ(PHASE[inst]);
1206
1207 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1208 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1209 /* NOTE: In case VBLANK syncronization is enabled, MODULO may
1210 * not be programmed equal to DPREFCLK
1211 */
1212 modulo_hz = REG_READ(MODULO[inst]);
1213 if (modulo_hz)
1214 *pixel_clk_khz = div_u64((uint64_t)clock_hz*
1215 dp_dto_ref_khz*10,
1216 modulo_hz);
1217 else
1218 *pixel_clk_khz = 0;
1219 } else {
1220 /* NOTE: There is agreement with VBIOS here that MODULO is
1221 * programmed equal to DPREFCLK, in which case PHASE will be
1222 * equivalent to pixel clock.
1223 */
1224 *pixel_clk_khz = clock_hz / 100;
1225 }
1226 return true;
1227 }
1228
1229 return false;
1230 }
1231
1232 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1233 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1234 // /1.001 rates
1235 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1236 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1237 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1238 {89910, 90000, 90000, 1000, 1001}, //90Mhz -> 89.91
1239 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1240 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1241 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1242 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1243 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
1244 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
1245 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857
1246 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6
1247 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091
1248 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055
1249 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325
1250 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231
1251 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974
1252 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455
1253 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066
1254 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377
1255 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308
1256 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987
1257 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209
1258 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099
1259 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131
1260
1261 // *1.001 rates
1262 {27020, 27030, 27000, 1001, 1000}, //27Mhz
1263 {54050, 54060, 54000, 1001, 1000}, //54Mhz
1264 {108100, 108110, 108000, 1001, 1000},//108Mhz
1265 };
1266
look_up_in_video_optimized_rate_tlb(unsigned int pixel_rate_khz)1267 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1268 unsigned int pixel_rate_khz)
1269 {
1270 int i;
1271
1272 for (i = 0; i < ARRAY_SIZE(video_optimized_pixel_rates); i++) {
1273 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1274
1275 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1276 return e;
1277 }
1278 }
1279
1280 return NULL;
1281 }
1282
dcn20_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)1283 static bool dcn20_program_pix_clk(
1284 struct clock_source *clock_source,
1285 struct pixel_clk_params *pix_clk_params,
1286 enum dp_link_encoding encoding,
1287 struct pll_settings *pll_settings)
1288 {
1289 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1290 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1291
1292 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1293
1294 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1295 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1296 /* NOTE: In case VBLANK syncronization is enabled,
1297 * we need to set modulo to default DPREFCLK first
1298 * dce112_program_pix_clk does not set default DPREFCLK
1299 */
1300 REG_WRITE(MODULO[inst],
1301 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);
1302 }
1303 return true;
1304 }
1305
dcn20_override_dp_pix_clk(struct clock_source * clock_source,unsigned int inst,unsigned int pixel_clk,unsigned int ref_clk)1306 static bool dcn20_override_dp_pix_clk(
1307 struct clock_source *clock_source,
1308 unsigned int inst,
1309 unsigned int pixel_clk,
1310 unsigned int ref_clk)
1311 {
1312 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1313
1314 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
1315 REG_WRITE(PHASE[inst], pixel_clk);
1316 REG_WRITE(MODULO[inst], ref_clk);
1317 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1318 return true;
1319 }
1320
1321 static const struct clock_source_funcs dcn20_clk_src_funcs = {
1322 .cs_power_down = dce110_clock_source_power_down,
1323 .program_pix_clk = dcn20_program_pix_clk,
1324 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1325 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
1326 .override_dp_pix_clk = dcn20_override_dp_pix_clk
1327 };
1328
dcn3_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)1329 static bool dcn3_program_pix_clk(
1330 struct clock_source *clock_source,
1331 struct pixel_clk_params *pix_clk_params,
1332 enum dp_link_encoding encoding,
1333 struct pll_settings *pll_settings)
1334 {
1335 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1336 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1337 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1338 const struct pixel_rate_range_table_entry *e =
1339 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1340
1341 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
1342 if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1343 if (e) {
1344 /* Set DTO values: phase = target clock, modulo = reference clock*/
1345 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1346 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1347 } else {
1348 /* Set DTO values: phase = target clock, modulo = reference clock*/
1349 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1350 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1351 }
1352 /* Enable DTO */
1353 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1354 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1355 DP_DTO0_ENABLE, 1,
1356 PIPE0_DTO_SRC_SEL, 1);
1357 else
1358 REG_UPDATE(PIXEL_RATE_CNTL[inst],
1359 DP_DTO0_ENABLE, 1);
1360 } else
1361 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1362 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1363
1364 return true;
1365 }
1366
dcn3_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1367 static uint32_t dcn3_get_pix_clk_dividers(
1368 struct clock_source *cs,
1369 struct pixel_clk_params *pix_clk_params,
1370 struct pll_settings *pll_settings)
1371 {
1372 unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0;
1373 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
1374
1375 DC_LOGGER_INIT();
1376
1377 if (pix_clk_params == NULL || pll_settings == NULL
1378 || pix_clk_params->requested_pix_clk_100hz == 0) {
1379 DC_LOG_ERROR(
1380 "%s: Invalid parameters!!\n", __func__);
1381 return UINT_MAX;
1382 }
1383
1384 memset(pll_settings, 0, sizeof(*pll_settings));
1385 /* Adjust for HDMI Type A deep color */
1386 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1387 switch (pix_clk_params->color_depth) {
1388 case COLOR_DEPTH_101010:
1389 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1390 break;
1391 case COLOR_DEPTH_121212:
1392 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1393 break;
1394 case COLOR_DEPTH_161616:
1395 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1396 break;
1397 default:
1398 break;
1399 }
1400 }
1401 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1402 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1403 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1404
1405 return 0;
1406 }
1407
1408 static const struct clock_source_funcs dcn3_clk_src_funcs = {
1409 .cs_power_down = dce110_clock_source_power_down,
1410 .program_pix_clk = dcn3_program_pix_clk,
1411 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1412 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1413 };
1414
1415 static const struct clock_source_funcs dcn31_clk_src_funcs = {
1416 .cs_power_down = dce110_clock_source_power_down,
1417 .program_pix_clk = dcn31_program_pix_clk,
1418 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1419 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1420 };
1421
1422 static const struct clock_source_funcs dcn401_clk_src_funcs = {
1423 .cs_power_down = dce110_clock_source_power_down,
1424 .program_pix_clk = dcn401_program_pix_clk,
1425 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1426 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1427 };
1428
1429 /*****************************************/
1430 /* Constructor */
1431 /*****************************************/
1432
1433 static const struct clock_source_funcs dce112_clk_src_funcs = {
1434 .cs_power_down = dce110_clock_source_power_down,
1435 .program_pix_clk = dce112_program_pix_clk,
1436 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1437 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1438 };
1439 static const struct clock_source_funcs dce110_clk_src_funcs = {
1440 .cs_power_down = dce110_clock_source_power_down,
1441 .program_pix_clk = dce110_program_pix_clk,
1442 .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1443 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1444 };
1445
1446
get_ss_info_from_atombios(struct dce110_clk_src * clk_src,enum as_signal_type as_signal,struct spread_spectrum_data * spread_spectrum_data[],uint32_t * ss_entries_num)1447 static void get_ss_info_from_atombios(
1448 struct dce110_clk_src *clk_src,
1449 enum as_signal_type as_signal,
1450 struct spread_spectrum_data *spread_spectrum_data[],
1451 uint32_t *ss_entries_num)
1452 {
1453 enum bp_result bp_result = BP_RESULT_FAILURE;
1454 struct spread_spectrum_info *ss_info;
1455 struct spread_spectrum_data *ss_data;
1456 struct spread_spectrum_info *ss_info_cur;
1457 struct spread_spectrum_data *ss_data_cur;
1458 uint32_t i;
1459 DC_LOGGER_INIT();
1460 if (ss_entries_num == NULL) {
1461 DC_LOG_SYNC(
1462 "Invalid entry !!!\n");
1463 return;
1464 }
1465 if (spread_spectrum_data == NULL) {
1466 DC_LOG_SYNC(
1467 "Invalid array pointer!!!\n");
1468 return;
1469 }
1470
1471 spread_spectrum_data[0] = NULL;
1472 *ss_entries_num = 0;
1473
1474 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1475 clk_src->bios,
1476 as_signal);
1477
1478 if (*ss_entries_num == 0)
1479 return;
1480
1481 ss_info = kzalloc_objs(struct spread_spectrum_info, *ss_entries_num);
1482 ss_info_cur = ss_info;
1483 if (ss_info == NULL)
1484 return;
1485
1486 ss_data = kzalloc_objs(struct spread_spectrum_data, *ss_entries_num);
1487 if (ss_data == NULL)
1488 goto out_free_info;
1489
1490 for (i = 0, ss_info_cur = ss_info;
1491 i < (*ss_entries_num);
1492 ++i, ++ss_info_cur) {
1493
1494 bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1495 clk_src->bios,
1496 as_signal,
1497 i,
1498 ss_info_cur);
1499
1500 if (bp_result != BP_RESULT_OK)
1501 goto out_free_data;
1502 }
1503
1504 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1505 i < (*ss_entries_num);
1506 ++i, ++ss_info_cur, ++ss_data_cur) {
1507
1508 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1509 DC_LOG_SYNC(
1510 "Invalid ATOMBIOS SS Table!!!\n");
1511 goto out_free_data;
1512 }
1513
1514 /* for HDMI check SS percentage,
1515 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1516 if (as_signal == AS_SIGNAL_TYPE_HDMI
1517 && ss_info_cur->spread_spectrum_percentage > 6){
1518 /* invalid input, do nothing */
1519 DC_LOG_SYNC(
1520 "Invalid SS percentage ");
1521 DC_LOG_SYNC(
1522 "for HDMI in ATOMBIOS info Table!!!\n");
1523 continue;
1524 }
1525 if (ss_info_cur->spread_percentage_divider == 1000) {
1526 /* Keep previous precision from ATOMBIOS for these
1527 * in case new precision set by ATOMBIOS for these
1528 * (otherwise all code in DCE specific classes
1529 * for all previous ASICs would need
1530 * to be updated for SS calculations,
1531 * Audio SS compensation and DP DTO SS compensation
1532 * which assumes fixed SS percentage Divider = 100)*/
1533 ss_info_cur->spread_spectrum_percentage /= 10;
1534 ss_info_cur->spread_percentage_divider = 100;
1535 }
1536
1537 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1538 ss_data_cur->percentage =
1539 ss_info_cur->spread_spectrum_percentage;
1540 ss_data_cur->percentage_divider =
1541 ss_info_cur->spread_percentage_divider;
1542 ss_data_cur->modulation_freq_hz =
1543 ss_info_cur->spread_spectrum_range;
1544
1545 if (ss_info_cur->type.CENTER_MODE)
1546 ss_data_cur->flags.CENTER_SPREAD = 1;
1547
1548 if (ss_info_cur->type.EXTERNAL)
1549 ss_data_cur->flags.EXTERNAL_SS = 1;
1550
1551 }
1552
1553 *spread_spectrum_data = ss_data;
1554 kfree(ss_info);
1555 return;
1556
1557 out_free_data:
1558 kfree(ss_data);
1559 *ss_entries_num = 0;
1560 out_free_info:
1561 kfree(ss_info);
1562 }
1563
ss_info_from_atombios_create(struct dce110_clk_src * clk_src)1564 static void ss_info_from_atombios_create(
1565 struct dce110_clk_src *clk_src)
1566 {
1567 get_ss_info_from_atombios(
1568 clk_src,
1569 AS_SIGNAL_TYPE_DISPLAY_PORT,
1570 &clk_src->dp_ss_params,
1571 &clk_src->dp_ss_params_cnt);
1572 get_ss_info_from_atombios(
1573 clk_src,
1574 AS_SIGNAL_TYPE_HDMI,
1575 &clk_src->hdmi_ss_params,
1576 &clk_src->hdmi_ss_params_cnt);
1577 get_ss_info_from_atombios(
1578 clk_src,
1579 AS_SIGNAL_TYPE_DVI,
1580 &clk_src->dvi_ss_params,
1581 &clk_src->dvi_ss_params_cnt);
1582 get_ss_info_from_atombios(
1583 clk_src,
1584 AS_SIGNAL_TYPE_LVDS,
1585 &clk_src->lvds_ss_params,
1586 &clk_src->lvds_ss_params_cnt);
1587 }
1588
calc_pll_max_vco_construct(struct calc_pll_clock_source * calc_pll_cs,struct calc_pll_clock_source_init_data * init_data)1589 static bool calc_pll_max_vco_construct(
1590 struct calc_pll_clock_source *calc_pll_cs,
1591 struct calc_pll_clock_source_init_data *init_data)
1592 {
1593 uint32_t i;
1594 struct dc_firmware_info *fw_info;
1595 if (calc_pll_cs == NULL ||
1596 init_data == NULL ||
1597 init_data->bp == NULL)
1598 return false;
1599
1600 if (!init_data->bp->fw_info_valid)
1601 return false;
1602
1603 fw_info = &init_data->bp->fw_info;
1604 calc_pll_cs->ctx = init_data->ctx;
1605 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1606 calc_pll_cs->min_vco_khz =
1607 fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1608 calc_pll_cs->max_vco_khz =
1609 fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1610
1611 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1612 calc_pll_cs->max_pll_input_freq_khz =
1613 init_data->max_override_input_pxl_clk_pll_freq_khz;
1614 else
1615 calc_pll_cs->max_pll_input_freq_khz =
1616 fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1617
1618 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1619 calc_pll_cs->min_pll_input_freq_khz =
1620 init_data->min_override_input_pxl_clk_pll_freq_khz;
1621 else
1622 calc_pll_cs->min_pll_input_freq_khz =
1623 fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1624
1625 calc_pll_cs->min_pix_clock_pll_post_divider =
1626 init_data->min_pix_clk_pll_post_divider;
1627 calc_pll_cs->max_pix_clock_pll_post_divider =
1628 init_data->max_pix_clk_pll_post_divider;
1629 calc_pll_cs->min_pll_ref_divider =
1630 init_data->min_pll_ref_divider;
1631 calc_pll_cs->max_pll_ref_divider =
1632 init_data->max_pll_ref_divider;
1633
1634 if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1635 init_data->num_fract_fb_divider_decimal_point_precision >
1636 init_data->num_fract_fb_divider_decimal_point) {
1637 DC_LOG_ERROR(
1638 "The dec point num or precision is incorrect!");
1639 return false;
1640 }
1641 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1642 DC_LOG_ERROR(
1643 "Incorrect fract feedback divider precision num!");
1644 return false;
1645 }
1646
1647 calc_pll_cs->fract_fb_divider_decimal_points_num =
1648 init_data->num_fract_fb_divider_decimal_point;
1649 calc_pll_cs->fract_fb_divider_precision =
1650 init_data->num_fract_fb_divider_decimal_point_precision;
1651 calc_pll_cs->fract_fb_divider_factor = 1;
1652 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1653 calc_pll_cs->fract_fb_divider_factor *= 10;
1654
1655 calc_pll_cs->fract_fb_divider_precision_factor = 1;
1656 for (
1657 i = 0;
1658 i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1659 calc_pll_cs->fract_fb_divider_precision);
1660 ++i)
1661 calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1662
1663 return true;
1664 }
1665
dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1666 bool dce110_clk_src_construct(
1667 struct dce110_clk_src *clk_src,
1668 struct dc_context *ctx,
1669 struct dc_bios *bios,
1670 enum clock_source_id id,
1671 const struct dce110_clk_src_regs *regs,
1672 const struct dce110_clk_src_shift *cs_shift,
1673 const struct dce110_clk_src_mask *cs_mask)
1674 {
1675 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1676 struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1677
1678 clk_src->base.ctx = ctx;
1679 clk_src->bios = bios;
1680 clk_src->base.id = id;
1681 clk_src->base.funcs = &dce110_clk_src_funcs;
1682
1683 clk_src->regs = regs;
1684 clk_src->cs_shift = cs_shift;
1685 clk_src->cs_mask = cs_mask;
1686
1687 if (!clk_src->bios->fw_info_valid) {
1688 ASSERT_CRITICAL(false);
1689 goto unexpected_failure;
1690 }
1691
1692 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1693
1694 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1695 calc_pll_cs_init_data.bp = bios;
1696 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1697 calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1698 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1699 calc_pll_cs_init_data.min_pll_ref_divider = 1;
1700 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1701 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1702 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
1703 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1704 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0;
1705 /*numberOfFractFBDividerDecimalPoints*/
1706 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1707 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1708 /*number of decimal point to round off for fractional feedback divider value*/
1709 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1710 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1711 calc_pll_cs_init_data.ctx = ctx;
1712
1713 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1714 calc_pll_cs_init_data_hdmi.bp = bios;
1715 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1716 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1717 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1718 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1719 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1720 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1721 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1722 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1723 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1724 /*numberOfFractFBDividerDecimalPoints*/
1725 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1726 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1727 /*number of decimal point to round off for fractional feedback divider value*/
1728 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1729 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1730 calc_pll_cs_init_data_hdmi.ctx = ctx;
1731
1732 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1733
1734 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1735 return true;
1736
1737 /* PLL only from here on */
1738 ss_info_from_atombios_create(clk_src);
1739
1740 if (!calc_pll_max_vco_construct(
1741 &clk_src->calc_pll,
1742 &calc_pll_cs_init_data)) {
1743 ASSERT_CRITICAL(false);
1744 goto unexpected_failure;
1745 }
1746
1747
1748 calc_pll_cs_init_data_hdmi.
1749 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1750 calc_pll_cs_init_data_hdmi.
1751 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1752
1753
1754 if (!calc_pll_max_vco_construct(
1755 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1756 ASSERT_CRITICAL(false);
1757 goto unexpected_failure;
1758 }
1759
1760 return true;
1761
1762 unexpected_failure:
1763 return false;
1764 }
1765
dce112_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1766 bool dce112_clk_src_construct(
1767 struct dce110_clk_src *clk_src,
1768 struct dc_context *ctx,
1769 struct dc_bios *bios,
1770 enum clock_source_id id,
1771 const struct dce110_clk_src_regs *regs,
1772 const struct dce110_clk_src_shift *cs_shift,
1773 const struct dce110_clk_src_mask *cs_mask)
1774 {
1775 clk_src->base.ctx = ctx;
1776 clk_src->bios = bios;
1777 clk_src->base.id = id;
1778 clk_src->base.funcs = &dce112_clk_src_funcs;
1779
1780 clk_src->regs = regs;
1781 clk_src->cs_shift = cs_shift;
1782 clk_src->cs_mask = cs_mask;
1783
1784 if (!clk_src->bios->fw_info_valid) {
1785 ASSERT_CRITICAL(false);
1786 return false;
1787 }
1788
1789 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1790
1791 return true;
1792 }
1793
dcn20_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1794 bool dcn20_clk_src_construct(
1795 struct dce110_clk_src *clk_src,
1796 struct dc_context *ctx,
1797 struct dc_bios *bios,
1798 enum clock_source_id id,
1799 const struct dce110_clk_src_regs *regs,
1800 const struct dce110_clk_src_shift *cs_shift,
1801 const struct dce110_clk_src_mask *cs_mask)
1802 {
1803 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1804
1805 clk_src->base.funcs = &dcn20_clk_src_funcs;
1806
1807 return ret;
1808 }
1809
dcn3_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1810 bool dcn3_clk_src_construct(
1811 struct dce110_clk_src *clk_src,
1812 struct dc_context *ctx,
1813 struct dc_bios *bios,
1814 enum clock_source_id id,
1815 const struct dce110_clk_src_regs *regs,
1816 const struct dce110_clk_src_shift *cs_shift,
1817 const struct dce110_clk_src_mask *cs_mask)
1818 {
1819 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1820
1821 clk_src->base.funcs = &dcn3_clk_src_funcs;
1822
1823 return ret;
1824 }
1825
dcn31_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1826 bool dcn31_clk_src_construct(
1827 struct dce110_clk_src *clk_src,
1828 struct dc_context *ctx,
1829 struct dc_bios *bios,
1830 enum clock_source_id id,
1831 const struct dce110_clk_src_regs *regs,
1832 const struct dce110_clk_src_shift *cs_shift,
1833 const struct dce110_clk_src_mask *cs_mask)
1834 {
1835 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1836
1837 clk_src->base.funcs = &dcn31_clk_src_funcs;
1838
1839 return ret;
1840 }
1841
dcn401_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1842 bool dcn401_clk_src_construct(
1843 struct dce110_clk_src *clk_src,
1844 struct dc_context *ctx,
1845 struct dc_bios *bios,
1846 enum clock_source_id id,
1847 const struct dce110_clk_src_regs *regs,
1848 const struct dce110_clk_src_shift *cs_shift,
1849 const struct dce110_clk_src_mask *cs_mask)
1850 {
1851 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1852
1853 clk_src->base.funcs = &dcn401_clk_src_funcs;
1854
1855 return ret;
1856 }
dcn301_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1857 bool dcn301_clk_src_construct(
1858 struct dce110_clk_src *clk_src,
1859 struct dc_context *ctx,
1860 struct dc_bios *bios,
1861 enum clock_source_id id,
1862 const struct dce110_clk_src_regs *regs,
1863 const struct dce110_clk_src_shift *cs_shift,
1864 const struct dce110_clk_src_mask *cs_mask)
1865 {
1866 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1867
1868 clk_src->base.funcs = &dcn3_clk_src_funcs;
1869
1870 return ret;
1871 }
1872