1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/dim.h>
34 #include <linux/ethtool_netlink.h>
35 #include <net/netdev_queues.h>
36
37 #include "en.h"
38 #include "en/channels.h"
39 #include "en/dim.h"
40 #include "en/port.h"
41 #include "en/params.h"
42 #include "en/ptp.h"
43 #include "lib/clock.h"
44 #include "en/fs_ethtool.h"
45
46 #define LANES_UNKNOWN 0
47
48 #define MLX5E_MAX_INDIR_RQT_SIZE \
49 roundup_pow_of_two(MLX5E_MAX_NUM_CHANNELS * \
50 MLX5E_UNIFORM_SPREAD_RQT_FACTOR)
51
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)52 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
53 struct ethtool_drvinfo *drvinfo)
54 {
55 struct mlx5_core_dev *mdev = priv->mdev;
56 int count;
57
58 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
59 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
60 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),
61 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id);
62 if (count >= sizeof(drvinfo->fw_version))
63 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
64 "%d.%d.%04d", fw_rev_maj(mdev),
65 fw_rev_min(mdev), fw_rev_sub(mdev));
66
67 strscpy(drvinfo->bus_info, dev_name(mdev->device),
68 sizeof(drvinfo->bus_info));
69 }
70
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)71 static void mlx5e_get_drvinfo(struct net_device *dev,
72 struct ethtool_drvinfo *drvinfo)
73 {
74 struct mlx5e_priv *priv = netdev_priv(dev);
75
76 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
77 }
78
79 struct ptys2ethtool_config {
80 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
81 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
82 };
83
84 static
85 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
86 static
87 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
88
89 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
90 ({ \
91 struct ptys2ethtool_config *cfg; \
92 const unsigned int modes[] = { __VA_ARGS__ }; \
93 unsigned int i; \
94 cfg = &ptys2##table##_ethtool_table[reg_]; \
95 bitmap_zero(cfg->supported, \
96 __ETHTOOL_LINK_MODE_MASK_NBITS); \
97 bitmap_zero(cfg->advertised, \
98 __ETHTOOL_LINK_MODE_MASK_NBITS); \
99 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
100 bitmap_set(cfg->supported, modes[i], 1); \
101 bitmap_set(cfg->advertised, modes[i], 1); \
102 } \
103 })
104
mlx5e_build_ptys2ethtool_map(void)105 void mlx5e_build_ptys2ethtool_map(void)
106 {
107 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
108 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
110 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
112 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
114 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
116 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
118 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
120 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
122 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
124 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
126 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
128 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
130 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
132 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
134 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
136 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
138 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
140 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
142 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
144 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
146 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
148 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
150 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
154 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
156 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
158 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
160 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
161 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
162 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
164 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
166 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
167 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
168 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
170 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
171 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
172 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
173 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
174 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
175 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
176 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
178 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
180 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
181 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
182 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
185 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
186 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
187 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
188 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
189 ext,
190 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
191 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
192 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
193 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
194 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
195 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
196 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
197 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
198 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
199 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
200 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
201 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
202 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
203 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
204 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
205 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
206 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
207 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
208 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
209 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
210 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
211 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
212 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
213 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
214 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
215 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
216 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
217 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
218 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
219 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
220 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
221 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
222 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
223 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
224 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
225 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
226 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
227 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
228 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
229 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
230 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
231 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
232 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
233 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
234 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
235 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
236 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
237 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
238 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
239 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
240 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext,
241 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
242 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
243 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
244 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
245 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
246 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
247 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext,
248 ETHTOOL_LINK_MODE_200000baseCR_Full_BIT,
249 ETHTOOL_LINK_MODE_200000baseKR_Full_BIT,
250 ETHTOOL_LINK_MODE_200000baseDR_Full_BIT,
251 ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT,
252 ETHTOOL_LINK_MODE_200000baseSR_Full_BIT,
253 ETHTOOL_LINK_MODE_200000baseVR_Full_BIT);
254 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext,
255 ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT,
256 ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT,
257 ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT,
258 ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT,
259 ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT,
260 ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT);
261 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext,
262 ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT,
263 ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT,
264 ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT,
265 ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
266 ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
267 ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
268 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8, ext,
269 ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT,
270 ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT,
271 ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT,
272 ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT);
273 }
274
mlx5e_ethtool_get_speed_arr(bool ext,struct ptys2ethtool_config ** arr,u32 * size)275 static void mlx5e_ethtool_get_speed_arr(bool ext,
276 struct ptys2ethtool_config **arr,
277 u32 *size)
278 {
279 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
280 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
281 ARRAY_SIZE(ptys2legacy_ethtool_table);
282 }
283
284 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
285
286 struct pflag_desc {
287 char name[ETH_GSTRING_LEN];
288 mlx5e_pflag_handler handler;
289 };
290
291 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
292
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)293 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
294 {
295 switch (sset) {
296 case ETH_SS_STATS:
297 return mlx5e_stats_total_num(priv);
298 case ETH_SS_PRIV_FLAGS:
299 return MLX5E_NUM_PFLAGS;
300 case ETH_SS_TEST:
301 return mlx5e_self_test_num(priv);
302 default:
303 return -EOPNOTSUPP;
304 }
305 }
306
mlx5e_get_sset_count(struct net_device * dev,int sset)307 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
308 {
309 struct mlx5e_priv *priv = netdev_priv(dev);
310
311 return mlx5e_ethtool_get_sset_count(priv, sset);
312 }
313
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)314 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
315 {
316 int i;
317
318 switch (stringset) {
319 case ETH_SS_PRIV_FLAGS:
320 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
321 ethtool_puts(&data, mlx5e_priv_flags[i].name);
322 break;
323
324 case ETH_SS_TEST:
325 mlx5e_self_test_fill_strings(priv, data);
326 break;
327
328 case ETH_SS_STATS:
329 mlx5e_stats_fill_strings(priv, data);
330 break;
331 }
332 }
333
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)334 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
335 {
336 struct mlx5e_priv *priv = netdev_priv(dev);
337
338 mlx5e_ethtool_get_strings(priv, stringset, data);
339 }
340
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)341 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
342 struct ethtool_stats *stats, u64 *data)
343 {
344 int idx = 0;
345
346 mutex_lock(&priv->state_lock);
347 mlx5e_stats_update(priv);
348 mutex_unlock(&priv->state_lock);
349
350 mlx5e_stats_fill(priv, data, idx);
351 }
352
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)353 static void mlx5e_get_ethtool_stats(struct net_device *dev,
354 struct ethtool_stats *stats,
355 u64 *data)
356 {
357 struct mlx5e_priv *priv = netdev_priv(dev);
358
359 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
360 }
361
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param)362 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
363 struct ethtool_ringparam *param,
364 struct kernel_ethtool_ringparam *kernel_param)
365 {
366 /* Limitation for regular RQ. XSK RQ may clamp the queue length in
367 * mlx5e_mpwqe_get_log_rq_size.
368 */
369 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev,
370 PAGE_SHIFT,
371 MLX5E_MPWRQ_UMR_MODE_ALIGNED);
372
373 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE,
374 max_log_mpwrq_pkts);
375 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
376 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
377 param->tx_pending = 1 << priv->channels.params.log_sq_size;
378
379 kernel_param->hds_thresh = 0;
380 kernel_param->hds_thresh_max = 0;
381 }
382
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)383 static void mlx5e_get_ringparam(struct net_device *dev,
384 struct ethtool_ringparam *param,
385 struct kernel_ethtool_ringparam *kernel_param,
386 struct netlink_ext_ack *extack)
387 {
388 struct mlx5e_priv *priv = netdev_priv(dev);
389
390 mlx5e_ethtool_get_ringparam(priv, param, kernel_param);
391 }
392
mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv * priv,u8 tcp_data_split,struct netlink_ext_ack * extack)393 static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv,
394 u8 tcp_data_split,
395 struct netlink_ext_ack *extack)
396 {
397 struct net_device *dev = priv->netdev;
398
399 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
400 !(dev->features & NETIF_F_GRO_HW)) {
401 NL_SET_ERR_MSG_MOD(extack,
402 "TCP-data-split is not supported when GRO HW is disabled");
403 return false;
404 }
405
406 /* Might need to disable HW-GRO if it was kept on due to hds. */
407 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED &&
408 dev->cfg->hds_config == ETHTOOL_TCP_DATA_SPLIT_ENABLED)
409 netdev_update_features(priv->netdev);
410
411 return true;
412 }
413
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct netlink_ext_ack * extack)414 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
415 struct ethtool_ringparam *param,
416 struct netlink_ext_ack *extack)
417 {
418 struct mlx5e_params new_params;
419 u8 log_rq_size;
420 u8 log_sq_size;
421 int err = 0;
422
423 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
424 NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)",
425 param->rx_pending,
426 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
427 return -EINVAL;
428 }
429
430 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
431 NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)",
432 param->tx_pending,
433 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
434 return -EINVAL;
435 }
436
437 log_rq_size = order_base_2(param->rx_pending);
438 log_sq_size = order_base_2(param->tx_pending);
439
440 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
441 log_sq_size == priv->channels.params.log_sq_size)
442 return 0;
443
444 mutex_lock(&priv->state_lock);
445
446 new_params = priv->channels.params;
447 new_params.log_rq_mtu_frames = log_rq_size;
448 new_params.log_sq_size = log_sq_size;
449
450 err = mlx5e_validate_params(priv->mdev, &new_params);
451 if (err)
452 goto unlock;
453
454 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
455
456 unlock:
457 mutex_unlock(&priv->state_lock);
458
459 if (!err)
460 netdev_update_features(priv->netdev);
461
462 return err;
463 }
464
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)465 static int mlx5e_set_ringparam(struct net_device *dev,
466 struct ethtool_ringparam *param,
467 struct kernel_ethtool_ringparam *kernel_param,
468 struct netlink_ext_ack *extack)
469 {
470 struct mlx5e_priv *priv = netdev_priv(dev);
471
472 if (!mlx5e_ethtool_set_tcp_data_split(priv,
473 kernel_param->tcp_data_split,
474 extack))
475 return -EINVAL;
476
477 return mlx5e_ethtool_set_ringparam(priv, param, extack);
478 }
479
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)480 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
481 struct ethtool_channels *ch)
482 {
483 mutex_lock(&priv->state_lock);
484 ch->max_combined = priv->max_nch;
485 ch->combined_count = priv->channels.params.num_channels;
486 mutex_unlock(&priv->state_lock);
487 }
488
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)489 static void mlx5e_get_channels(struct net_device *dev,
490 struct ethtool_channels *ch)
491 {
492 struct mlx5e_priv *priv = netdev_priv(dev);
493
494 mlx5e_ethtool_get_channels(priv, ch);
495 }
496
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)497 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
498 struct ethtool_channels *ch)
499 {
500 struct mlx5e_params *cur_params = &priv->channels.params;
501 unsigned int count = ch->combined_count;
502 int new_rqt_size, cur_rqt_size;
503 struct mlx5e_params new_params;
504 struct mlx5e_rss *rss0;
505 bool arfs_enabled;
506 bool has_rss_ctxs;
507 bool opened;
508 int err = 0;
509
510 ASSERT_RTNL();
511
512 if (!count) {
513 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
514 __func__);
515 return -EINVAL;
516 }
517
518 if (cur_params->num_channels == count)
519 return 0;
520
521 new_rqt_size = mlx5e_rqt_size(priv->mdev, count);
522 /* Validate that all non-default RSS contexts can be resized before
523 * committing to the channel count change.
524 * ethtool_rxfh_ctxs_can_resize() acquires rss_lock internally and
525 * cannot be called under state_lock (rss_lock -> state_lock ordering).
526 */
527 has_rss_ctxs = priv->rx_res && mlx5e_rx_res_rss_cnt(priv->rx_res) > 1;
528 if (has_rss_ctxs) {
529 err = ethtool_rxfh_ctxs_can_resize(priv->netdev, new_rqt_size);
530 if (err)
531 return err;
532 }
533
534 mutex_lock(&priv->state_lock);
535
536 if (!priv->rx_res) {
537 err = -EINVAL;
538 goto out;
539 }
540
541 cur_rqt_size = mlx5e_rqt_size(priv->mdev, cur_params->num_channels);
542 rss0 = mlx5e_rx_res_rss_get(priv->rx_res, 0);
543
544 if (!ethtool_rxfh_indir_can_resize(priv->netdev,
545 mlx5e_rss_get_indir_table(rss0),
546 cur_rqt_size, new_rqt_size)) {
547 netdev_err(priv->netdev,
548 "%s: cannot resize RSS table (%u -> %u); reset indirection table to allow this change\n",
549 __func__, cur_rqt_size, new_rqt_size);
550 err = -EINVAL;
551 goto out;
552 }
553
554 /* Don't allow changing the number of channels if HTB offload is active,
555 * because the numeration of the QoS SQs will change, while per-queue
556 * qdiscs are attached.
557 */
558 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
559 err = -EINVAL;
560 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
561 __func__);
562 goto out;
563 }
564
565 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active,
566 * because it defines a partition over the channels queues.
567 */
568 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
569 err = -EINVAL;
570 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n",
571 __func__);
572 goto out;
573 }
574
575 new_params = *cur_params;
576 new_params.num_channels = count;
577
578 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
579
580 arfs_enabled = opened && mlx5e_fs_want_arfs(priv->netdev);
581 if (arfs_enabled)
582 mlx5e_arfs_disable(priv->fs);
583
584 /* Switch to new channels, set new parameters and close old ones */
585 err = mlx5e_safe_switch_params(priv, &new_params,
586 mlx5e_num_channels_changed_ctx, NULL, true);
587
588 if (arfs_enabled) {
589 int err2 = mlx5e_arfs_enable(priv->fs);
590
591 if (err2)
592 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
593 __func__, err2);
594 }
595
596 out:
597 mutex_unlock(&priv->state_lock);
598
599 /* After a successful channel count change that altered the RQT size,
600 * fold or unfold the indirection tables of all non-default RSS
601 * contexts. Must run after state_lock is released because
602 * ethtool_rxfh_ctxs_resize() acquires rss_lock internally.
603 */
604 if (!err && cur_rqt_size != new_rqt_size && has_rss_ctxs)
605 ethtool_rxfh_ctxs_resize(priv->netdev, new_rqt_size);
606
607 return err;
608 }
609
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)610 static int mlx5e_set_channels(struct net_device *dev,
611 struct ethtool_channels *ch)
612 {
613 struct mlx5e_priv *priv = netdev_priv(dev);
614
615 return mlx5e_ethtool_set_channels(priv, ch);
616 }
617
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)618 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
619 struct ethtool_coalesce *coal,
620 struct kernel_ethtool_coalesce *kernel_coal,
621 struct netlink_ext_ack *extack)
622 {
623 struct dim_cq_moder *rx_moder, *tx_moder;
624
625 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) {
626 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
627 return -EOPNOTSUPP;
628 }
629
630 rx_moder = &priv->channels.params.rx_cq_moderation;
631 coal->rx_coalesce_usecs = rx_moder->usec;
632 coal->rx_max_coalesced_frames = rx_moder->pkts;
633 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
634 kernel_coal->use_cqe_mode_rx = priv->channels.params.rx_moder_use_cqe_mode;
635
636 tx_moder = &priv->channels.params.tx_cq_moderation;
637 coal->tx_coalesce_usecs = tx_moder->usec;
638 coal->tx_max_coalesced_frames = tx_moder->pkts;
639 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
640 kernel_coal->use_cqe_mode_tx = priv->channels.params.tx_moder_use_cqe_mode;
641
642 return 0;
643 }
644
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)645 static int mlx5e_get_coalesce(struct net_device *netdev,
646 struct ethtool_coalesce *coal,
647 struct kernel_ethtool_coalesce *kernel_coal,
648 struct netlink_ext_ack *extack)
649 {
650 struct mlx5e_priv *priv = netdev_priv(netdev);
651
652 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack);
653 }
654
mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)655 static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
656 struct ethtool_coalesce *coal)
657 {
658 struct dim_cq_moder cur_moder;
659 struct mlx5e_channels *chs;
660 struct mlx5e_channel *c;
661
662 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
663 return -EOPNOTSUPP;
664
665 mutex_lock(&priv->state_lock);
666
667 chs = &priv->channels;
668 if (chs->num <= queue) {
669 mutex_unlock(&priv->state_lock);
670 return -EINVAL;
671 }
672
673 c = chs->c[queue];
674
675 coal->use_adaptive_rx_coalesce = !!c->rq.dim;
676 if (coal->use_adaptive_rx_coalesce) {
677 cur_moder = net_dim_get_rx_moderation(c->rq.dim->mode,
678 c->rq.dim->profile_ix);
679
680 coal->rx_coalesce_usecs = cur_moder.usec;
681 coal->rx_max_coalesced_frames = cur_moder.pkts;
682 } else {
683 coal->rx_coalesce_usecs = c->rx_cq_moder.usec;
684 coal->rx_max_coalesced_frames = c->rx_cq_moder.pkts;
685 }
686
687 coal->use_adaptive_tx_coalesce = !!c->sq[0].dim;
688 if (coal->use_adaptive_tx_coalesce) {
689 /* NOTE: Will only display DIM coalesce profile information of
690 * first channel. The current interface cannot display this
691 * information for all tc.
692 */
693 cur_moder = net_dim_get_tx_moderation(c->sq[0].dim->mode,
694 c->sq[0].dim->profile_ix);
695
696 coal->tx_coalesce_usecs = cur_moder.usec;
697 coal->tx_max_coalesced_frames = cur_moder.pkts;
698
699 } else {
700 coal->tx_coalesce_usecs = c->tx_cq_moder.usec;
701 coal->tx_max_coalesced_frames = c->tx_cq_moder.pkts;
702 }
703
704 mutex_unlock(&priv->state_lock);
705
706 return 0;
707 }
708
mlx5e_get_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)709 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
710 struct ethtool_coalesce *coal)
711 {
712 struct mlx5e_priv *priv = netdev_priv(dev);
713
714 return mlx5e_ethtool_get_per_queue_coalesce(priv, queue, coal);
715 }
716
717 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
718 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
719
720 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)721 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
722 {
723 int tc;
724 int i;
725
726 for (i = 0; i < priv->channels.num; ++i) {
727 struct mlx5e_channel *c = priv->channels.c[i];
728 struct mlx5_core_dev *mdev = c->mdev;
729 enum mlx5_cq_period_mode mode;
730
731 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
732 c->tx_cq_moder = *moder;
733
734 for (tc = 0; tc < c->num_tc; tc++) {
735 mlx5e_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
736 moder->usec, moder->pkts,
737 mode);
738 }
739 }
740 }
741
742 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct dim_cq_moder * moder)743 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder)
744 {
745 int i;
746
747 for (i = 0; i < priv->channels.num; ++i) {
748 struct mlx5e_channel *c = priv->channels.c[i];
749 struct mlx5_core_dev *mdev = c->mdev;
750 enum mlx5_cq_period_mode mode;
751
752 mode = mlx5e_cq_period_mode(moder->cq_period_mode);
753 c->rx_cq_moder = *moder;
754
755 mlx5e_modify_cq_moderation(mdev, &c->rq.cq.mcq, moder->usec, moder->pkts,
756 mode);
757 }
758 }
759
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)760 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
761 struct ethtool_coalesce *coal,
762 struct kernel_ethtool_coalesce *kernel_coal,
763 struct netlink_ext_ack *extack)
764 {
765 struct dim_cq_moder *rx_moder, *tx_moder;
766 struct mlx5_core_dev *mdev = priv->mdev;
767 bool rx_dim_enabled, tx_dim_enabled;
768 struct mlx5e_params new_params;
769 bool reset_rx, reset_tx;
770 u8 cq_period_mode;
771 int err = 0;
772
773 if (!MLX5_CAP_GEN(mdev, cq_moderation) ||
774 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) {
775 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported");
776 return -EOPNOTSUPP;
777 }
778
779 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
780 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
781 NL_SET_ERR_MSG_FMT_MOD(
782 extack,
783 "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)",
784 MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs,
785 coal->rx_coalesce_usecs);
786 return -ERANGE;
787 }
788
789 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
790 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
791 NL_SET_ERR_MSG_FMT_MOD(
792 extack,
793 "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)",
794 MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames,
795 coal->rx_max_coalesced_frames);
796 return -ERANGE;
797 }
798
799 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
800 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) {
801 NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device");
802 return -EOPNOTSUPP;
803 }
804
805 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
806 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
807
808 mutex_lock(&priv->state_lock);
809 new_params = priv->channels.params;
810
811 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_rx);
812 reset_rx = mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
813 rx_dim_enabled, false);
814 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, cq_period_mode);
815
816 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_tx);
817 reset_tx = mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
818 tx_dim_enabled, false);
819 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, cq_period_mode);
820
821 reset_rx |= rx_dim_enabled != new_params.rx_dim_enabled;
822 reset_tx |= tx_dim_enabled != new_params.tx_dim_enabled;
823
824 /* Solely used for global ethtool get coalesce */
825 rx_moder = &new_params.rx_cq_moderation;
826 new_params.rx_dim_enabled = rx_dim_enabled;
827 new_params.rx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_rx;
828
829 tx_moder = &new_params.tx_cq_moderation;
830 new_params.tx_dim_enabled = tx_dim_enabled;
831 new_params.tx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_tx;
832
833 if (reset_rx) {
834 mlx5e_channels_rx_change_dim(&priv->channels, false);
835 mlx5e_reset_rx_moderation(rx_moder, new_params.rx_moder_use_cqe_mode,
836 rx_dim_enabled);
837
838 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
839 } else if (!rx_dim_enabled) {
840 rx_moder->usec = coal->rx_coalesce_usecs;
841 rx_moder->pkts = coal->rx_max_coalesced_frames;
842
843 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder);
844 }
845
846 if (reset_tx) {
847 mlx5e_channels_tx_change_dim(&priv->channels, false);
848 mlx5e_reset_tx_moderation(tx_moder, new_params.tx_moder_use_cqe_mode,
849 tx_dim_enabled);
850
851 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
852 } else if (!tx_dim_enabled) {
853 tx_moder->usec = coal->tx_coalesce_usecs;
854 tx_moder->pkts = coal->tx_max_coalesced_frames;
855
856 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder);
857 }
858
859 /* DIM enable/disable Rx and Tx channels */
860 err = mlx5e_channels_rx_change_dim(&priv->channels, rx_dim_enabled);
861 if (err)
862 goto state_unlock;
863 err = mlx5e_channels_tx_change_dim(&priv->channels, tx_dim_enabled);
864 if (err)
865 goto state_unlock;
866
867 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
868 state_unlock:
869 mutex_unlock(&priv->state_lock);
870 return err;
871 }
872
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)873 static int mlx5e_set_coalesce(struct net_device *netdev,
874 struct ethtool_coalesce *coal,
875 struct kernel_ethtool_coalesce *kernel_coal,
876 struct netlink_ext_ack *extack)
877 {
878 struct mlx5e_priv *priv = netdev_priv(netdev);
879
880 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack);
881 }
882
mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv * priv,u32 queue,struct ethtool_coalesce * coal)883 static int mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue,
884 struct ethtool_coalesce *coal)
885 {
886 struct mlx5_core_dev *mdev = priv->mdev;
887 bool rx_dim_enabled, tx_dim_enabled;
888 struct mlx5e_channels *chs;
889 struct mlx5e_channel *c;
890 int err = 0;
891 int tc;
892
893 if (!MLX5_CAP_GEN(mdev, cq_moderation))
894 return -EOPNOTSUPP;
895
896 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
897 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
898 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
899 __func__, MLX5E_MAX_COAL_TIME);
900 return -ERANGE;
901 }
902
903 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
904 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
905 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
906 __func__, MLX5E_MAX_COAL_FRAMES);
907 return -ERANGE;
908 }
909
910 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
911 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
912
913 mutex_lock(&priv->state_lock);
914
915 chs = &priv->channels;
916 if (chs->num <= queue) {
917 mutex_unlock(&priv->state_lock);
918 return -EINVAL;
919 }
920
921 c = chs->c[queue];
922
923 err = mlx5e_dim_rx_change(&c->rq, rx_dim_enabled);
924 if (err)
925 goto state_unlock;
926
927 for (tc = 0; tc < c->num_tc; tc++) {
928 err = mlx5e_dim_tx_change(&c->sq[tc], tx_dim_enabled);
929 if (err)
930 goto state_unlock;
931 }
932
933 if (!rx_dim_enabled) {
934 c->rx_cq_moder.usec = coal->rx_coalesce_usecs;
935 c->rx_cq_moder.pkts = coal->rx_max_coalesced_frames;
936
937 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
938 coal->rx_coalesce_usecs,
939 coal->rx_max_coalesced_frames);
940 }
941
942 if (!tx_dim_enabled) {
943 c->tx_cq_moder.usec = coal->tx_coalesce_usecs;
944 c->tx_cq_moder.pkts = coal->tx_max_coalesced_frames;
945
946 for (tc = 0; tc < c->num_tc; tc++)
947 mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq,
948 coal->tx_coalesce_usecs,
949 coal->tx_max_coalesced_frames);
950 }
951
952 state_unlock:
953 mutex_unlock(&priv->state_lock);
954 return err;
955 }
956
mlx5e_set_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * coal)957 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
958 struct ethtool_coalesce *coal)
959 {
960 struct mlx5e_priv *priv = netdev_priv(dev);
961
962 return mlx5e_ethtool_set_per_queue_coalesce(priv, queue, coal);
963 }
964
ptys2ethtool_process_link(u32 eth_eproto,bool ext,bool advertised,unsigned long * modes)965 static void ptys2ethtool_process_link(u32 eth_eproto, bool ext, bool advertised,
966 unsigned long *modes)
967 {
968 unsigned long eproto = eth_eproto;
969 struct ptys2ethtool_config *table;
970 u32 max_size;
971 int proto;
972
973 mlx5e_ethtool_get_speed_arr(ext, &table, &max_size);
974 for_each_set_bit(proto, &eproto, max_size)
975 bitmap_or(modes, modes,
976 advertised ?
977 table[proto].advertised : table[proto].supported,
978 __ETHTOOL_LINK_MODE_MASK_NBITS);
979 }
980
981 static const u32 pplm_fec_2_ethtool[] = {
982 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
983 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
984 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
985 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
986 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
987 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS,
988 };
989
pplm2ethtool_fec(u_long fec_mode,unsigned long size)990 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
991 {
992 int mode = 0;
993
994 if (!fec_mode)
995 return ETHTOOL_FEC_AUTO;
996
997 mode = find_first_bit(&fec_mode, size);
998
999 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
1000 return pplm_fec_2_ethtool[mode];
1001
1002 return 0;
1003 }
1004
1005 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
1006 do { \
1007 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
1008 __set_bit(ethtool_fec, \
1009 link_ksettings->link_modes.supported);\
1010 } while (0)
1011
1012 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
1013 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1014 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1015 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
1016 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
1017 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1018 };
1019
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)1020 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
1021 struct ethtool_link_ksettings *link_ksettings)
1022 {
1023 unsigned long active_fec_long;
1024 u32 active_fec;
1025 u32 bitn;
1026 int err;
1027
1028 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
1029 if (err)
1030 return (err == -EOPNOTSUPP) ? 0 : err;
1031
1032 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
1033 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
1034 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
1035 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
1036 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
1037 ETHTOOL_LINK_MODE_FEC_RS_BIT);
1038 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
1039 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
1040
1041 active_fec_long = active_fec;
1042 /* active fec is a bit set, find out which bit is set and
1043 * advertise the corresponding ethtool bit
1044 */
1045 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
1046 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
1047 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
1048 link_ksettings->link_modes.advertising);
1049
1050 return 0;
1051 }
1052
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)1053 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
1054 struct ethtool_link_ksettings *link_ksettings,
1055 u32 eth_proto_cap, u8 connector_type)
1056 {
1057 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
1058 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
1059 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
1060 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
1061 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
1062 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
1063 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1064 ethtool_link_ksettings_add_link_mode(link_ksettings,
1065 supported,
1066 FIBRE);
1067 ethtool_link_ksettings_add_link_mode(link_ksettings,
1068 advertising,
1069 FIBRE);
1070 }
1071
1072 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
1073 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
1074 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
1075 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
1076 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
1077 ethtool_link_ksettings_add_link_mode(link_ksettings,
1078 supported,
1079 Backplane);
1080 ethtool_link_ksettings_add_link_mode(link_ksettings,
1081 advertising,
1082 Backplane);
1083 }
1084 return;
1085 }
1086
1087 switch (connector_type) {
1088 case MLX5E_PORT_TP:
1089 ethtool_link_ksettings_add_link_mode(link_ksettings,
1090 supported, TP);
1091 ethtool_link_ksettings_add_link_mode(link_ksettings,
1092 advertising, TP);
1093 break;
1094 case MLX5E_PORT_AUI:
1095 ethtool_link_ksettings_add_link_mode(link_ksettings,
1096 supported, AUI);
1097 ethtool_link_ksettings_add_link_mode(link_ksettings,
1098 advertising, AUI);
1099 break;
1100 case MLX5E_PORT_BNC:
1101 ethtool_link_ksettings_add_link_mode(link_ksettings,
1102 supported, BNC);
1103 ethtool_link_ksettings_add_link_mode(link_ksettings,
1104 advertising, BNC);
1105 break;
1106 case MLX5E_PORT_MII:
1107 ethtool_link_ksettings_add_link_mode(link_ksettings,
1108 supported, MII);
1109 ethtool_link_ksettings_add_link_mode(link_ksettings,
1110 advertising, MII);
1111 break;
1112 case MLX5E_PORT_FIBRE:
1113 ethtool_link_ksettings_add_link_mode(link_ksettings,
1114 supported, FIBRE);
1115 ethtool_link_ksettings_add_link_mode(link_ksettings,
1116 advertising, FIBRE);
1117 break;
1118 case MLX5E_PORT_DA:
1119 ethtool_link_ksettings_add_link_mode(link_ksettings,
1120 supported, Backplane);
1121 ethtool_link_ksettings_add_link_mode(link_ksettings,
1122 advertising, Backplane);
1123 break;
1124 case MLX5E_PORT_NONE:
1125 case MLX5E_PORT_OTHER:
1126 default:
1127 break;
1128 }
1129 }
1130
get_link_properties(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)1131 static void get_link_properties(struct net_device *netdev,
1132 u32 eth_proto_oper, bool force_legacy,
1133 u16 data_rate_oper,
1134 struct ethtool_link_ksettings *link_ksettings)
1135 {
1136 struct mlx5e_priv *priv = netdev_priv(netdev);
1137 const struct mlx5_link_info *info;
1138 u8 duplex = DUPLEX_UNKNOWN;
1139 u32 speed = SPEED_UNKNOWN;
1140 u32 lanes = LANES_UNKNOWN;
1141
1142 if (!netif_carrier_ok(netdev))
1143 goto out;
1144
1145 info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy);
1146 if (info) {
1147 speed = info->speed;
1148 lanes = info->lanes;
1149 duplex = DUPLEX_FULL;
1150 } else if (data_rate_oper)
1151 speed = 100 * data_rate_oper;
1152
1153 out:
1154 link_ksettings->base.duplex = duplex;
1155 link_ksettings->base.speed = speed;
1156 link_ksettings->lanes = lanes;
1157 }
1158
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)1159 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
1160 struct ethtool_link_ksettings *link_ksettings)
1161 {
1162 unsigned long *supported = link_ksettings->link_modes.supported;
1163 bool ext = mlx5_ptys_ext_supported(mdev);
1164
1165 ptys2ethtool_process_link(eth_proto_cap, ext, false, supported);
1166
1167 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
1168 }
1169
get_advertising(u32 eth_proto_admin,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)1170 static void get_advertising(u32 eth_proto_admin, u8 tx_pause, u8 rx_pause,
1171 struct ethtool_link_ksettings *link_ksettings,
1172 bool ext)
1173 {
1174 unsigned long *advertising = link_ksettings->link_modes.advertising;
1175 ptys2ethtool_process_link(eth_proto_admin, ext, true, advertising);
1176 if (rx_pause)
1177 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
1178 if (tx_pause ^ rx_pause)
1179 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
1180 }
1181
1182 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
1183 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
1184 [MLX5E_PORT_NONE] = PORT_NONE,
1185 [MLX5E_PORT_TP] = PORT_TP,
1186 [MLX5E_PORT_AUI] = PORT_AUI,
1187 [MLX5E_PORT_BNC] = PORT_BNC,
1188 [MLX5E_PORT_MII] = PORT_MII,
1189 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
1190 [MLX5E_PORT_DA] = PORT_DA,
1191 [MLX5E_PORT_OTHER] = PORT_OTHER,
1192 };
1193
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)1194 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
1195 {
1196 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
1197 return ptys2connector_type[connector_type];
1198
1199 if (eth_proto &
1200 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
1201 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
1202 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
1203 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
1204 return PORT_FIBRE;
1205 }
1206
1207 if (eth_proto &
1208 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
1209 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
1210 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
1211 return PORT_DA;
1212 }
1213
1214 if (eth_proto &
1215 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
1216 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
1217 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
1218 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
1219 return PORT_NONE;
1220 }
1221
1222 return PORT_OTHER;
1223 }
1224
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)1225 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
1226 struct ethtool_link_ksettings *link_ksettings)
1227 {
1228 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
1229 bool ext = mlx5_ptys_ext_supported(mdev);
1230
1231 ptys2ethtool_process_link(eth_proto_lp, ext, true, lp_advertising);
1232 }
1233
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)1234 static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1235 struct ethtool_link_ksettings *link_ksettings)
1236 {
1237 struct mlx5_core_dev *mdev = priv->mdev;
1238 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
1239 u32 eth_proto_admin;
1240 u8 an_disable_admin;
1241 u16 data_rate_oper;
1242 u32 eth_proto_oper;
1243 u32 eth_proto_cap;
1244 u8 connector_type;
1245 u32 rx_pause = 0;
1246 u32 tx_pause = 0;
1247 u32 eth_proto_lp;
1248 bool admin_ext;
1249 u8 an_status;
1250 bool ext;
1251 int err;
1252
1253 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0);
1254 if (err) {
1255 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1256 __func__, err);
1257 goto err_query_regs;
1258 }
1259 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
1260 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1261 eth_proto_capability);
1262 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1263 eth_proto_admin);
1264 /* Fields: eth_proto_admin and ext_eth_proto_admin are
1265 * mutually exclusive. Hence try reading legacy advertising
1266 * when extended advertising is zero.
1267 * admin_ext indicates which proto_admin (ext vs. legacy)
1268 * should be read and interpreted
1269 */
1270 admin_ext = ext;
1271 if (ext && !eth_proto_admin) {
1272 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
1273 eth_proto_admin);
1274 admin_ext = false;
1275 }
1276
1277 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
1278 eth_proto_oper);
1279 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1280 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1281 an_status = MLX5_GET(ptys_reg, out, an_status);
1282 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1283 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
1284
1285 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1286
1287 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1288 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1289
1290 get_supported(mdev, eth_proto_cap, link_ksettings);
1291 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
1292 admin_ext);
1293 get_link_properties(priv->netdev, eth_proto_oper, !admin_ext,
1294 data_rate_oper, link_ksettings);
1295
1296 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1297 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
1298 connector_type : MLX5E_PORT_UNKNOWN;
1299 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
1300 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
1301 connector_type);
1302 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
1303
1304 if (an_status == MLX5_AN_COMPLETE)
1305 ethtool_link_ksettings_add_link_mode(link_ksettings,
1306 lp_advertising, Autoneg);
1307
1308 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1309 AUTONEG_ENABLE;
1310 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1311 Autoneg);
1312
1313 err = get_fec_supported_advertised(mdev, link_ksettings);
1314 if (err) {
1315 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1316 __func__, err);
1317 err = 0; /* don't fail caps query because of FEC error */
1318 }
1319
1320 if (!an_disable_admin)
1321 ethtool_link_ksettings_add_link_mode(link_ksettings,
1322 advertising, Autoneg);
1323
1324 err_query_regs:
1325 return err;
1326 }
1327
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1328 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1329 struct ethtool_link_ksettings *link_ksettings)
1330 {
1331 struct mlx5e_priv *priv = netdev_priv(netdev);
1332
1333 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1334 }
1335
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1336 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1337 const unsigned long link_modes, u8 autoneg)
1338 {
1339 /* Extended link-mode has no speed limitations. */
1340 if (ext)
1341 return 0;
1342
1343 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1344 autoneg != AUTONEG_ENABLE) {
1345 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1346 __func__);
1347 return -EINVAL;
1348 }
1349 return 0;
1350 }
1351
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1352 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1353 {
1354 u32 i, ptys_modes = 0;
1355
1356 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1357 if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised,
1358 __ETHTOOL_LINK_MODE_MASK_NBITS))
1359 continue;
1360 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1361 link_modes,
1362 __ETHTOOL_LINK_MODE_MASK_NBITS))
1363 ptys_modes |= MLX5E_PROT_MASK(i);
1364 }
1365
1366 return ptys_modes;
1367 }
1368
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1369 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1370 {
1371 u32 i, ptys_modes = 0;
1372 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes);
1373
1374 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1375 if (bitmap_empty(ptys2ext_ethtool_table[i].advertised,
1376 __ETHTOOL_LINK_MODE_MASK_NBITS))
1377 continue;
1378 bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1379 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1380 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1381
1382 if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised,
1383 __ETHTOOL_LINK_MODE_MASK_NBITS))
1384 ptys_modes |= MLX5E_PROT_MASK(i);
1385 }
1386 return ptys_modes;
1387 }
1388
ext_link_mode_requested(const unsigned long * adver)1389 static bool ext_link_mode_requested(const unsigned long *adver)
1390 {
1391 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1392 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1393 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1394
1395 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1396 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1397 }
1398
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1399 static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1400 const struct ethtool_link_ksettings *link_ksettings)
1401 {
1402 struct mlx5_core_dev *mdev = priv->mdev;
1403 struct mlx5_port_eth_proto eproto;
1404 struct mlx5_link_info info = {};
1405 const unsigned long *adver;
1406 bool an_changes = false;
1407 u8 an_disable_admin;
1408 bool ext_supported;
1409 bool ext_requested;
1410 u8 an_disable_cap;
1411 bool an_disable;
1412 u32 link_modes;
1413 u8 an_status;
1414 u8 autoneg;
1415 bool ext;
1416 int err;
1417
1418 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1419
1420 adver = link_ksettings->link_modes.advertising;
1421 autoneg = link_ksettings->base.autoneg;
1422 info.speed = link_ksettings->base.speed;
1423 info.lanes = link_ksettings->lanes;
1424
1425 ext_supported = mlx5_ptys_ext_supported(mdev);
1426 ext_requested = ext_link_mode_requested(adver);
1427 if (!ext_supported && ext_requested)
1428 return -EOPNOTSUPP;
1429
1430 ext = autoneg == AUTONEG_ENABLE ? ext_requested : ext_supported;
1431 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1432 mlx5e_ethtool2ptys_adver_link;
1433 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1434 if (err) {
1435 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1436 __func__, err);
1437 goto out;
1438 }
1439 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1440 mlx5_port_info2linkmodes(mdev, &info, !ext);
1441
1442 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1443 if (err)
1444 goto out;
1445
1446 link_modes = link_modes & eproto.cap;
1447 if (!link_modes) {
1448 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1449 __func__);
1450 err = -EINVAL;
1451 goto out;
1452 }
1453
1454 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1455 &an_disable_admin);
1456
1457 an_disable = autoneg == AUTONEG_DISABLE;
1458 an_changes = ((!an_disable && an_disable_admin) ||
1459 (an_disable && !an_disable_admin));
1460
1461 if (!an_changes && link_modes == eproto.admin)
1462 goto out;
1463
1464 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1465 if (err) {
1466 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err);
1467 goto out;
1468 }
1469
1470 mlx5_toggle_port_link(mdev);
1471
1472 out:
1473 return err;
1474 }
1475
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1476 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1477 const struct ethtool_link_ksettings *link_ksettings)
1478 {
1479 struct mlx5e_priv *priv = netdev_priv(netdev);
1480
1481 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1482 }
1483
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1484 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1485 {
1486 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key);
1487 }
1488
mlx5e_get_rxfh_key_size(struct net_device * netdev)1489 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1490 {
1491 struct mlx5e_priv *priv = netdev_priv(netdev);
1492
1493 return mlx5e_ethtool_get_rxfh_key_size(priv);
1494 }
1495
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1496 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1497 {
1498 return mlx5e_rqt_size(priv->mdev, priv->channels.params.num_channels);
1499 }
1500
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1501 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1502 {
1503 struct mlx5e_priv *priv = netdev_priv(netdev);
1504
1505 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1506 }
1507
mlx5e_get_rxfh(struct net_device * netdev,struct ethtool_rxfh_param * rxfh)1508 static int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)
1509 {
1510 struct mlx5e_priv *priv = netdev_priv(netdev);
1511 bool symmetric;
1512
1513 mutex_lock(&priv->state_lock);
1514 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, 0, rxfh->indir, rxfh->key,
1515 &rxfh->hfunc, &symmetric);
1516 mutex_unlock(&priv->state_lock);
1517
1518 if (symmetric)
1519 rxfh->input_xfrm = RXH_XFRM_SYM_OR_XOR;
1520
1521 return 0;
1522 }
1523
mlx5e_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1524 static int mlx5e_set_rxfh(struct net_device *dev,
1525 struct ethtool_rxfh_param *rxfh,
1526 struct netlink_ext_ack *extack)
1527 {
1528 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1529 struct mlx5e_priv *priv = netdev_priv(dev);
1530 u8 hfunc = rxfh->hfunc;
1531 int err;
1532
1533 mutex_lock(&priv->state_lock);
1534
1535 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1536 rxfh->indir, rxfh->key,
1537 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1538 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1539
1540 mutex_unlock(&priv->state_lock);
1541 return err;
1542 }
1543
mlx5e_create_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1544 static int mlx5e_create_rxfh_context(struct net_device *dev,
1545 struct ethtool_rxfh_context *ctx,
1546 const struct ethtool_rxfh_param *rxfh,
1547 struct netlink_ext_ack *extack)
1548 {
1549 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1550 struct mlx5e_priv *priv = netdev_priv(dev);
1551 u8 hfunc = rxfh->hfunc;
1552 int err;
1553
1554 mutex_lock(&priv->state_lock);
1555
1556 err = mlx5e_rx_res_rss_init(priv->rx_res, rxfh->rss_context,
1557 priv->channels.params.num_channels);
1558 if (err)
1559 goto unlock;
1560
1561 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1562 rxfh->indir, rxfh->key,
1563 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1564 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1565 if (err) {
1566 WARN_ON(mlx5e_rx_res_rss_destroy(priv->rx_res,
1567 rxfh->rss_context));
1568 goto unlock;
1569 }
1570
1571 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rxfh->rss_context,
1572 ethtool_rxfh_context_indir(ctx),
1573 ethtool_rxfh_context_key(ctx),
1574 &ctx->hfunc, &symmetric);
1575 if (symmetric)
1576 ctx->input_xfrm = RXH_XFRM_SYM_OR_XOR;
1577
1578 unlock:
1579 mutex_unlock(&priv->state_lock);
1580 return err;
1581 }
1582
mlx5e_modify_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1583 static int mlx5e_modify_rxfh_context(struct net_device *dev,
1584 struct ethtool_rxfh_context *ctx,
1585 const struct ethtool_rxfh_param *rxfh,
1586 struct netlink_ext_ack *extack)
1587 {
1588 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR;
1589 struct mlx5e_priv *priv = netdev_priv(dev);
1590 u8 hfunc = rxfh->hfunc;
1591 int err;
1592
1593 mutex_lock(&priv->state_lock);
1594
1595 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context,
1596 rxfh->indir, rxfh->key,
1597 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc,
1598 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric);
1599
1600 mutex_unlock(&priv->state_lock);
1601 return err;
1602 }
1603
mlx5e_remove_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,u32 rss_context,struct netlink_ext_ack * extack)1604 static int mlx5e_remove_rxfh_context(struct net_device *dev,
1605 struct ethtool_rxfh_context *ctx,
1606 u32 rss_context,
1607 struct netlink_ext_ack *extack)
1608 {
1609 struct mlx5e_priv *priv = netdev_priv(dev);
1610 int err;
1611
1612 mutex_lock(&priv->state_lock);
1613 err = mlx5e_rx_res_rss_destroy(priv->rx_res, rss_context);
1614 mutex_unlock(&priv->state_lock);
1615 return err;
1616 }
1617
1618 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1619 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1620 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1621 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1622 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1623 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1624 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1625
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1626 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1627 u16 *pfc_prevention_tout)
1628 {
1629 struct mlx5e_priv *priv = netdev_priv(netdev);
1630 struct mlx5_core_dev *mdev = priv->mdev;
1631
1632 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1633 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1634 return -EOPNOTSUPP;
1635
1636 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1637 }
1638
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1639 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1640 u16 pfc_preven)
1641 {
1642 struct mlx5e_priv *priv = netdev_priv(netdev);
1643 struct mlx5_core_dev *mdev = priv->mdev;
1644 u16 critical_tout;
1645 u16 minor;
1646
1647 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1648 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1649 return -EOPNOTSUPP;
1650
1651 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1652 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1653 pfc_preven;
1654
1655 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1656 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1657 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1658 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1659 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1660 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1661 return -EINVAL;
1662 }
1663
1664 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1665 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1666 minor);
1667 }
1668
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1669 static int mlx5e_get_tunable(struct net_device *dev,
1670 const struct ethtool_tunable *tuna,
1671 void *data)
1672 {
1673 int err;
1674
1675 switch (tuna->id) {
1676 case ETHTOOL_PFC_PREVENTION_TOUT:
1677 err = mlx5e_get_pfc_prevention_tout(dev, data);
1678 break;
1679 default:
1680 err = -EINVAL;
1681 break;
1682 }
1683
1684 return err;
1685 }
1686
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1687 static int mlx5e_set_tunable(struct net_device *dev,
1688 const struct ethtool_tunable *tuna,
1689 const void *data)
1690 {
1691 struct mlx5e_priv *priv = netdev_priv(dev);
1692 int err;
1693
1694 mutex_lock(&priv->state_lock);
1695
1696 switch (tuna->id) {
1697 case ETHTOOL_PFC_PREVENTION_TOUT:
1698 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1699 break;
1700 default:
1701 err = -EINVAL;
1702 break;
1703 }
1704
1705 mutex_unlock(&priv->state_lock);
1706 return err;
1707 }
1708
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1709 static void mlx5e_get_pause_stats(struct net_device *netdev,
1710 struct ethtool_pause_stats *pause_stats)
1711 {
1712 struct mlx5e_priv *priv = netdev_priv(netdev);
1713
1714 mlx5e_stats_pause_get(priv, pause_stats);
1715 }
1716
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1717 static void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1718 struct ethtool_pauseparam *pauseparam)
1719 {
1720 struct mlx5_core_dev *mdev = priv->mdev;
1721 int err;
1722
1723 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1724 &pauseparam->tx_pause);
1725 if (err) {
1726 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1727 __func__, err);
1728 }
1729 }
1730
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1731 static void mlx5e_get_pauseparam(struct net_device *netdev,
1732 struct ethtool_pauseparam *pauseparam)
1733 {
1734 struct mlx5e_priv *priv = netdev_priv(netdev);
1735
1736 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1737 }
1738
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1739 static int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1740 struct ethtool_pauseparam *pauseparam)
1741 {
1742 struct mlx5_core_dev *mdev = priv->mdev;
1743 int err;
1744
1745 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1746 return -EOPNOTSUPP;
1747
1748 if (pauseparam->autoneg)
1749 return -EINVAL;
1750
1751 err = mlx5_set_port_pause(mdev,
1752 pauseparam->rx_pause ? 1 : 0,
1753 pauseparam->tx_pause ? 1 : 0);
1754 if (err) {
1755 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1756 __func__, err);
1757 }
1758
1759 return err;
1760 }
1761
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1762 static int mlx5e_set_pauseparam(struct net_device *netdev,
1763 struct ethtool_pauseparam *pauseparam)
1764 {
1765 struct mlx5e_priv *priv = netdev_priv(netdev);
1766
1767 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1768 }
1769
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct kernel_ethtool_ts_info * info)1770 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1771 struct kernel_ethtool_ts_info *info)
1772 {
1773 struct mlx5_core_dev *mdev = priv->mdev;
1774
1775 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1776
1777 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1778 info->phc_index == -1)
1779 return 0;
1780
1781 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1782 SOF_TIMESTAMPING_TX_SOFTWARE |
1783 SOF_TIMESTAMPING_RX_HARDWARE |
1784 SOF_TIMESTAMPING_RAW_HARDWARE;
1785
1786 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1787 BIT(HWTSTAMP_TX_ON);
1788
1789 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1790 BIT(HWTSTAMP_FILTER_ALL);
1791
1792 return 0;
1793 }
1794
mlx5e_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)1795 static int mlx5e_get_ts_info(struct net_device *dev,
1796 struct kernel_ethtool_ts_info *info)
1797 {
1798 struct mlx5e_priv *priv = netdev_priv(dev);
1799
1800 return mlx5e_ethtool_get_ts_info(priv, info);
1801 }
1802
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1803 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1804 {
1805 __u32 ret = 0;
1806
1807 if (MLX5_CAP_GEN(mdev, wol_g))
1808 ret |= WAKE_MAGIC;
1809
1810 if (MLX5_CAP_GEN(mdev, wol_s))
1811 ret |= WAKE_MAGICSECURE;
1812
1813 if (MLX5_CAP_GEN(mdev, wol_a))
1814 ret |= WAKE_ARP;
1815
1816 if (MLX5_CAP_GEN(mdev, wol_b))
1817 ret |= WAKE_BCAST;
1818
1819 if (MLX5_CAP_GEN(mdev, wol_m))
1820 ret |= WAKE_MCAST;
1821
1822 if (MLX5_CAP_GEN(mdev, wol_u))
1823 ret |= WAKE_UCAST;
1824
1825 if (MLX5_CAP_GEN(mdev, wol_p))
1826 ret |= WAKE_PHY;
1827
1828 return ret;
1829 }
1830
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1831 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1832 {
1833 __u32 ret = 0;
1834
1835 if (mode & MLX5_WOL_MAGIC)
1836 ret |= WAKE_MAGIC;
1837
1838 if (mode & MLX5_WOL_SECURED_MAGIC)
1839 ret |= WAKE_MAGICSECURE;
1840
1841 if (mode & MLX5_WOL_ARP)
1842 ret |= WAKE_ARP;
1843
1844 if (mode & MLX5_WOL_BROADCAST)
1845 ret |= WAKE_BCAST;
1846
1847 if (mode & MLX5_WOL_MULTICAST)
1848 ret |= WAKE_MCAST;
1849
1850 if (mode & MLX5_WOL_UNICAST)
1851 ret |= WAKE_UCAST;
1852
1853 if (mode & MLX5_WOL_PHY_ACTIVITY)
1854 ret |= WAKE_PHY;
1855
1856 return ret;
1857 }
1858
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1859 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1860 {
1861 u8 ret = 0;
1862
1863 if (mode & WAKE_MAGIC)
1864 ret |= MLX5_WOL_MAGIC;
1865
1866 if (mode & WAKE_MAGICSECURE)
1867 ret |= MLX5_WOL_SECURED_MAGIC;
1868
1869 if (mode & WAKE_ARP)
1870 ret |= MLX5_WOL_ARP;
1871
1872 if (mode & WAKE_BCAST)
1873 ret |= MLX5_WOL_BROADCAST;
1874
1875 if (mode & WAKE_MCAST)
1876 ret |= MLX5_WOL_MULTICAST;
1877
1878 if (mode & WAKE_UCAST)
1879 ret |= MLX5_WOL_UNICAST;
1880
1881 if (mode & WAKE_PHY)
1882 ret |= MLX5_WOL_PHY_ACTIVITY;
1883
1884 return ret;
1885 }
1886
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1887 static void mlx5e_get_wol(struct net_device *netdev,
1888 struct ethtool_wolinfo *wol)
1889 {
1890 struct mlx5e_priv *priv = netdev_priv(netdev);
1891 struct mlx5_core_dev *mdev = priv->mdev;
1892 u8 mlx5_wol_mode;
1893 int err;
1894
1895 memset(wol, 0, sizeof(*wol));
1896
1897 wol->supported = mlx5e_get_wol_supported(mdev);
1898 if (!wol->supported)
1899 return;
1900
1901 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1902 if (err)
1903 return;
1904
1905 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1906 }
1907
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1908 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1909 {
1910 struct mlx5e_priv *priv = netdev_priv(netdev);
1911 struct mlx5_core_dev *mdev = priv->mdev;
1912 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1913 u32 mlx5_wol_mode;
1914
1915 if (!wol_supported)
1916 return -EOPNOTSUPP;
1917
1918 if (wol->wolopts & ~wol_supported)
1919 return -EINVAL;
1920
1921 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1922
1923 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1924 }
1925
mlx5e_get_fec_stats(struct net_device * netdev,struct ethtool_fec_stats * fec_stats,struct ethtool_fec_hist * hist)1926 static void mlx5e_get_fec_stats(struct net_device *netdev,
1927 struct ethtool_fec_stats *fec_stats,
1928 struct ethtool_fec_hist *hist)
1929 {
1930 struct mlx5e_priv *priv = netdev_priv(netdev);
1931
1932 mlx5e_stats_fec_get(priv, fec_stats, hist);
1933 }
1934
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1935 static int mlx5e_get_fecparam(struct net_device *netdev,
1936 struct ethtool_fecparam *fecparam)
1937 {
1938 struct mlx5e_priv *priv = netdev_priv(netdev);
1939 struct mlx5_core_dev *mdev = priv->mdev;
1940 u16 fec_configured;
1941 u32 fec_active;
1942 int err;
1943
1944 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1945
1946 if (err)
1947 return err;
1948
1949 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1950 sizeof(unsigned long) * BITS_PER_BYTE);
1951
1952 if (!fecparam->active_fec)
1953 return -EOPNOTSUPP;
1954
1955 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1956 sizeof(unsigned long) * BITS_PER_BYTE);
1957
1958 return 0;
1959 }
1960
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1961 static int mlx5e_set_fecparam(struct net_device *netdev,
1962 struct ethtool_fecparam *fecparam)
1963 {
1964 struct mlx5e_priv *priv = netdev_priv(netdev);
1965 struct mlx5_core_dev *mdev = priv->mdev;
1966 unsigned long fec_bitmap;
1967 u16 fec_policy = 0;
1968 int mode;
1969 int err;
1970
1971 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1972 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1973 return -EOPNOTSUPP;
1974
1975 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1976 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1977 continue;
1978 fec_policy |= (1 << mode);
1979 break;
1980 }
1981
1982 err = mlx5e_set_fec_mode(mdev, fec_policy);
1983
1984 if (err)
1985 return err;
1986
1987 mlx5_toggle_port_link(mdev);
1988
1989 return 0;
1990 }
1991
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1992 static int mlx5e_set_phys_id(struct net_device *dev,
1993 enum ethtool_phys_id_state state)
1994 {
1995 struct mlx5e_priv *priv = netdev_priv(dev);
1996 struct mlx5_core_dev *mdev = priv->mdev;
1997 u16 beacon_duration;
1998
1999 if (!MLX5_CAP_GEN(mdev, beacon_led))
2000 return -EOPNOTSUPP;
2001
2002 switch (state) {
2003 case ETHTOOL_ID_ACTIVE:
2004 beacon_duration = MLX5_BEACON_DURATION_INF;
2005 break;
2006 case ETHTOOL_ID_INACTIVE:
2007 beacon_duration = MLX5_BEACON_DURATION_OFF;
2008 break;
2009 default:
2010 return -EOPNOTSUPP;
2011 }
2012
2013 return mlx5_set_port_beacon(mdev, beacon_duration);
2014 }
2015
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)2016 static int mlx5e_get_module_info(struct net_device *netdev,
2017 struct ethtool_modinfo *modinfo)
2018 {
2019 struct mlx5e_priv *priv = netdev_priv(netdev);
2020 struct mlx5_core_dev *dev = priv->mdev;
2021 int size_read = 0;
2022 u8 data[4] = {0};
2023
2024 size_read = mlx5_query_module_eeprom(dev, 0, 2, data, NULL);
2025 if (size_read < 2)
2026 return -EIO;
2027
2028 /* data[0] = identifier byte */
2029 switch (data[0]) {
2030 case MLX5_MODULE_ID_QSFP:
2031 modinfo->type = ETH_MODULE_SFF_8436;
2032 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
2033 break;
2034 case MLX5_MODULE_ID_QSFP_PLUS:
2035 case MLX5_MODULE_ID_QSFP28:
2036 /* data[1] = revision id */
2037 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
2038 modinfo->type = ETH_MODULE_SFF_8636;
2039 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
2040 } else {
2041 modinfo->type = ETH_MODULE_SFF_8436;
2042 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
2043 }
2044 break;
2045 case MLX5_MODULE_ID_SFP:
2046 modinfo->type = ETH_MODULE_SFF_8472;
2047 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2048 break;
2049 default:
2050 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
2051 __func__, data[0]);
2052 return -EINVAL;
2053 }
2054
2055 return 0;
2056 }
2057
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)2058 static int mlx5e_get_module_eeprom(struct net_device *netdev,
2059 struct ethtool_eeprom *ee,
2060 u8 *data)
2061 {
2062 struct mlx5e_priv *priv = netdev_priv(netdev);
2063 struct mlx5_core_dev *mdev = priv->mdev;
2064 int offset = ee->offset;
2065 int size_read;
2066 u8 status = 0;
2067 int i = 0;
2068
2069 if (!ee->len)
2070 return -EINVAL;
2071
2072 memset(data, 0, ee->len);
2073
2074 while (i < ee->len) {
2075 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
2076 data + i, &status);
2077 if (!size_read)
2078 /* Done reading */
2079 return 0;
2080
2081 if (size_read < 0) {
2082 netdev_err(netdev,
2083 "%s: mlx5_query_eeprom failed:0x%x, status %u\n",
2084 __func__, size_read, status);
2085 return size_read;
2086 }
2087
2088 i += size_read;
2089 offset += size_read;
2090 }
2091
2092 return 0;
2093 }
2094
mlx5e_get_module_eeprom_by_page(struct net_device * netdev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)2095 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev,
2096 const struct ethtool_module_eeprom *page_data,
2097 struct netlink_ext_ack *extack)
2098 {
2099 struct mlx5e_priv *priv = netdev_priv(netdev);
2100 struct mlx5_module_eeprom_query_params query;
2101 struct mlx5_core_dev *mdev = priv->mdev;
2102 u8 *data = page_data->data;
2103 int size_read;
2104 u8 status = 0;
2105 int i = 0;
2106
2107 if (!page_data->length)
2108 return -EINVAL;
2109
2110 memset(data, 0, page_data->length);
2111
2112 query.offset = page_data->offset;
2113 query.i2c_address = page_data->i2c_address;
2114 query.bank = page_data->bank;
2115 query.page = page_data->page;
2116 while (i < page_data->length) {
2117 query.size = page_data->length - i;
2118 size_read = mlx5_query_module_eeprom_by_page(mdev, &query,
2119 data + i, &status);
2120
2121 /* Done reading, return how many bytes was read */
2122 if (!size_read)
2123 return i;
2124
2125 if (size_read < 0) {
2126 NL_SET_ERR_MSG_FMT_MOD(
2127 extack,
2128 "Query module eeprom by page failed, read %u bytes, err %d, status %u",
2129 i, size_read, status);
2130 return size_read;
2131 }
2132
2133 i += size_read;
2134 query.offset += size_read;
2135 }
2136
2137 return i;
2138 }
2139
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)2140 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
2141 struct ethtool_flash *flash)
2142 {
2143 struct mlx5_core_dev *mdev = priv->mdev;
2144 struct net_device *dev = priv->netdev;
2145 const struct firmware *fw;
2146 int err;
2147
2148 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2149 return -EOPNOTSUPP;
2150
2151 err = request_firmware_direct(&fw, flash->data, &dev->dev);
2152 if (err)
2153 return err;
2154
2155 err = mlx5_firmware_flash(mdev, fw, NULL);
2156 release_firmware(fw);
2157
2158 return err;
2159 }
2160
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)2161 static int mlx5e_flash_device(struct net_device *dev,
2162 struct ethtool_flash *flash)
2163 {
2164 struct mlx5e_priv *priv = netdev_priv(dev);
2165
2166 return mlx5e_ethtool_flash_device(priv, flash);
2167 }
2168
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)2169 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
2170 bool is_rx_cq)
2171 {
2172 struct mlx5e_priv *priv = netdev_priv(netdev);
2173 u8 cq_period_mode, current_cq_period_mode;
2174 struct mlx5e_params new_params;
2175
2176 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2177 return -EOPNOTSUPP;
2178
2179 cq_period_mode = mlx5e_dim_cq_period_mode(enable);
2180
2181 current_cq_period_mode = is_rx_cq ?
2182 priv->channels.params.rx_cq_moderation.cq_period_mode :
2183 priv->channels.params.tx_cq_moderation.cq_period_mode;
2184
2185 if (cq_period_mode == current_cq_period_mode)
2186 return 0;
2187
2188 new_params = priv->channels.params;
2189 if (is_rx_cq) {
2190 mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode,
2191 false, true);
2192 mlx5e_channels_rx_toggle_dim(&priv->channels);
2193 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
2194 cq_period_mode);
2195 } else {
2196 mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode,
2197 false, true);
2198 mlx5e_channels_tx_toggle_dim(&priv->channels);
2199 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
2200 cq_period_mode);
2201 }
2202
2203 /* Update pflags of existing channels without resetting them */
2204 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false);
2205 }
2206
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)2207 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
2208 {
2209 return set_pflag_cqe_based_moder(netdev, enable, false);
2210 }
2211
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)2212 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
2213 {
2214 return set_pflag_cqe_based_moder(netdev, enable, true);
2215 }
2216
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val,bool rx_filter)2217 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
2218 {
2219 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
2220 struct mlx5e_params new_params;
2221 int err = 0;
2222
2223 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
2224 return new_val ? -EOPNOTSUPP : 0;
2225
2226 if (curr_val == new_val)
2227 return 0;
2228
2229 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) {
2230 netdev_err(priv->netdev,
2231 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
2232 return -EINVAL;
2233 }
2234
2235 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
2236 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n");
2237 return -EINVAL;
2238 }
2239
2240 new_params = priv->channels.params;
2241 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
2242 if (rx_filter)
2243 new_params.ptp_rx = new_val;
2244
2245 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
2246 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2247 else
2248 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
2249 &new_params.ptp_rx, true);
2250 if (err)
2251 return err;
2252
2253 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n",
2254 MLX5E_GET_PFLAG(&priv->channels.params,
2255 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
2256
2257 return 0;
2258 }
2259
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)2260 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
2261 bool enable)
2262 {
2263 struct mlx5e_priv *priv = netdev_priv(netdev);
2264 struct mlx5_core_dev *mdev = priv->mdev;
2265 bool rx_filter;
2266 int err;
2267
2268 if (!MLX5_CAP_GEN(mdev, cqe_compression))
2269 return -EOPNOTSUPP;
2270
2271 rx_filter = priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE;
2272 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
2273 if (err)
2274 return err;
2275
2276 priv->channels.params.rx_cqe_compress_def = enable;
2277
2278 return 0;
2279 }
2280
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)2281 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
2282 {
2283 struct mlx5e_priv *priv = netdev_priv(netdev);
2284 struct mlx5_core_dev *mdev = priv->mdev;
2285 struct mlx5e_params new_params;
2286
2287 if (enable) {
2288 /* Checking the regular RQ here; mlx5e_validate_xsk_param called
2289 * from mlx5e_open_xsk will check for each XSK queue, and
2290 * mlx5e_safe_switch_params will be reverted if any check fails.
2291 */
2292 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params);
2293
2294 if (err)
2295 return err;
2296 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
2297 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n");
2298 return -EINVAL;
2299 }
2300
2301 new_params = priv->channels.params;
2302
2303 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
2304 mlx5e_set_rq_type(mdev, &new_params);
2305
2306 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2307 }
2308
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)2309 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
2310 {
2311 struct mlx5e_priv *priv = netdev_priv(netdev);
2312 struct mlx5e_channels *channels = &priv->channels;
2313 struct mlx5e_channel *c;
2314 int i;
2315
2316 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
2317 priv->channels.params.xdp_prog)
2318 return 0;
2319
2320 for (i = 0; i < channels->num; i++) {
2321 c = channels->c[i];
2322 if (enable)
2323 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2324 else
2325 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2326 }
2327
2328 return 0;
2329 }
2330
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)2331 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
2332 {
2333 struct mlx5e_priv *priv = netdev_priv(netdev);
2334 struct mlx5_core_dev *mdev = priv->mdev;
2335 struct mlx5e_params new_params;
2336
2337 if (enable && !mlx5e_tx_mpwqe_supported(mdev))
2338 return -EOPNOTSUPP;
2339
2340 new_params = priv->channels.params;
2341
2342 MLX5E_SET_PFLAG(&new_params, flag, enable);
2343
2344 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2345 }
2346
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)2347 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
2348 {
2349 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
2350 }
2351
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)2352 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
2353 {
2354 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
2355 }
2356
set_pflag_tx_port_ts(struct net_device * netdev,bool enable)2357 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
2358 {
2359 struct mlx5e_priv *priv = netdev_priv(netdev);
2360 struct mlx5_core_dev *mdev = priv->mdev;
2361 struct mlx5e_params new_params;
2362 int err;
2363
2364 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) ||
2365 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter))
2366 return -EOPNOTSUPP;
2367
2368 /* Don't allow changing the PTP state if HTB offload is active, because
2369 * the numeration of the QoS SQs will change, while per-queue qdiscs are
2370 * attached.
2371 */
2372 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
2373 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
2374 __func__);
2375 return -EINVAL;
2376 }
2377
2378 new_params = priv->channels.params;
2379 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is
2380 * active, since it defines explicitly which TC accepts the packet.
2381 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific
2382 * HW TX-queue.
2383 */
2384 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
2385 netdev_err(priv->netdev,
2386 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n",
2387 __func__);
2388 return -EINVAL;
2389 }
2390 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable);
2391 /* No need to verify SQ stop room as
2392 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2393 * has the same log_sq_size.
2394 */
2395
2396 err = mlx5e_safe_switch_params(priv, &new_params,
2397 mlx5e_update_tc_and_tx_queues_ctx, NULL, true);
2398 if (!err)
2399 priv->tx_ptp_opened = true;
2400
2401 return err;
2402 }
2403
2404 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2405 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
2406 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
2407 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
2408 { "rx_striding_rq", set_pflag_rx_striding_rq },
2409 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2410 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
2411 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
2412 { "tx_port_ts", set_pflag_tx_port_ts },
2413 };
2414
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)2415 static int mlx5e_handle_pflag(struct net_device *netdev,
2416 u32 wanted_flags,
2417 enum mlx5e_priv_flag flag)
2418 {
2419 struct mlx5e_priv *priv = netdev_priv(netdev);
2420 bool enable = !!(wanted_flags & BIT(flag));
2421 u32 changes = wanted_flags ^ priv->channels.params.pflags;
2422 int err;
2423
2424 if (!(changes & BIT(flag)))
2425 return 0;
2426
2427 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2428 if (err) {
2429 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2430 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2431 return err;
2432 }
2433
2434 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2435 return 0;
2436 }
2437
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2438 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2439 {
2440 struct mlx5e_priv *priv = netdev_priv(netdev);
2441 enum mlx5e_priv_flag pflag;
2442 int err;
2443
2444 mutex_lock(&priv->state_lock);
2445
2446 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2447 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2448 if (err)
2449 break;
2450 }
2451
2452 mutex_unlock(&priv->state_lock);
2453
2454 /* Need to fix some features.. */
2455 netdev_update_features(netdev);
2456
2457 return err;
2458 }
2459
mlx5e_get_priv_flags(struct net_device * netdev)2460 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2461 {
2462 struct mlx5e_priv *priv = netdev_priv(netdev);
2463
2464 return priv->channels.params.pflags;
2465 }
2466
mlx5e_get_rxfh_fields(struct net_device * dev,struct ethtool_rxfh_fields * info)2467 static int mlx5e_get_rxfh_fields(struct net_device *dev,
2468 struct ethtool_rxfh_fields *info)
2469 {
2470 struct mlx5e_priv *priv = netdev_priv(dev);
2471
2472 return mlx5e_ethtool_get_rxfh_fields(priv, info);
2473 }
2474
mlx5e_set_rxfh_fields(struct net_device * dev,const struct ethtool_rxfh_fields * cmd,struct netlink_ext_ack * extack)2475 static int mlx5e_set_rxfh_fields(struct net_device *dev,
2476 const struct ethtool_rxfh_fields *cmd,
2477 struct netlink_ext_ack *extack)
2478 {
2479 struct mlx5e_priv *priv = netdev_priv(dev);
2480
2481 return mlx5e_ethtool_set_rxfh_fields(priv, cmd, extack);
2482 }
2483
mlx5e_get_rx_ring_count(struct net_device * dev)2484 static u32 mlx5e_get_rx_ring_count(struct net_device *dev)
2485 {
2486 struct mlx5e_priv *priv = netdev_priv(dev);
2487
2488 return priv->channels.params.num_channels;
2489 }
2490
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2491 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2492 u32 *rule_locs)
2493 {
2494 struct mlx5e_priv *priv = netdev_priv(dev);
2495
2496 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs);
2497 }
2498
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2499 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2500 {
2501 struct mlx5e_priv *priv = netdev_priv(dev);
2502
2503 return mlx5e_ethtool_set_rxnfc(priv, cmd);
2504 }
2505
query_port_status_opcode(struct mlx5_core_dev * mdev,u32 * status_opcode)2506 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode)
2507 {
2508 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page;
2509 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {};
2510 u32 out[MLX5_ST_SZ_DW(pddr_reg)];
2511 int err;
2512
2513 MLX5_SET(pddr_reg, in, local_port, 1);
2514 MLX5_SET(pddr_reg, in, page_select,
2515 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE);
2516
2517 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data);
2518 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2519 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR);
2520 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
2521 sizeof(out), MLX5_REG_PDDR, 0, 0);
2522 if (err)
2523 return err;
2524
2525 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data);
2526 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2527 status_opcode);
2528 return 0;
2529 }
2530
2531 struct mlx5e_ethtool_link_ext_state_opcode_mapping {
2532 u32 status_opcode;
2533 enum ethtool_link_ext_state link_ext_state;
2534 u8 link_ext_substate;
2535 };
2536
2537 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping
2538 mlx5e_link_ext_state_opcode_map[] = {
2539 /* States relating to the autonegotiation or issues therein */
2540 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2541 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
2542 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2543 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
2544 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2545 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
2546 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2547 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
2548 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2549 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
2550 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2551 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
2552
2553 /* Failure during link training */
2554 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2555 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
2556 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2557 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
2558 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2559 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
2560 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
2561 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2562 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
2563
2564 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */
2565 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2566 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
2567 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2568 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
2569 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2570 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
2571 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2572 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
2573 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2574 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
2575
2576 /* Signal integrity issues */
2577 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
2578 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2579 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
2580 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2581 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
2582
2583 /* No cable connected */
2584 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
2585
2586 /* Failure is related to cable, e.g., unsupported cable */
2587 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2588 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2589 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2590 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2591 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2592 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2593 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2594 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2595 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2596 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2597 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
2598
2599 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */
2600 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
2601
2602 /* Failure during calibration algorithm */
2603 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
2604
2605 /* The hardware is not able to provide the power required from cable or module */
2606 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
2607
2608 /* The module is overheated */
2609 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
2610 };
2611
2612 static void
mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)2613 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping
2614 link_ext_state_mapping,
2615 struct ethtool_link_ext_state_info *link_ext_state_info)
2616 {
2617 switch (link_ext_state_mapping.link_ext_state) {
2618 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
2619 link_ext_state_info->autoneg =
2620 link_ext_state_mapping.link_ext_substate;
2621 break;
2622 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
2623 link_ext_state_info->link_training =
2624 link_ext_state_mapping.link_ext_substate;
2625 break;
2626 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
2627 link_ext_state_info->link_logical_mismatch =
2628 link_ext_state_mapping.link_ext_substate;
2629 break;
2630 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
2631 link_ext_state_info->bad_signal_integrity =
2632 link_ext_state_mapping.link_ext_substate;
2633 break;
2634 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
2635 link_ext_state_info->cable_issue =
2636 link_ext_state_mapping.link_ext_substate;
2637 break;
2638 default:
2639 break;
2640 }
2641
2642 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
2643 }
2644
2645 static int
mlx5e_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)2646 mlx5e_get_link_ext_state(struct net_device *dev,
2647 struct ethtool_link_ext_state_info *link_ext_state_info)
2648 {
2649 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
2650 struct mlx5e_priv *priv = netdev_priv(dev);
2651 u32 status_opcode = 0;
2652 int i;
2653
2654 /* Exit without data if the interface state is OK, since no extended data is
2655 * available in such case
2656 */
2657 if (netif_carrier_ok(dev))
2658 return -ENODATA;
2659
2660 if (query_port_status_opcode(priv->mdev, &status_opcode) ||
2661 !status_opcode)
2662 return -ENODATA;
2663
2664 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) {
2665 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i];
2666 if (link_ext_state_mapping.status_opcode == status_opcode) {
2667 mlx5e_set_link_ext_state(link_ext_state_mapping,
2668 link_ext_state_info);
2669 return 0;
2670 }
2671 }
2672
2673 return -ENODATA;
2674 }
2675
mlx5e_get_eth_phy_stats(struct net_device * netdev,struct ethtool_eth_phy_stats * phy_stats)2676 static void mlx5e_get_eth_phy_stats(struct net_device *netdev,
2677 struct ethtool_eth_phy_stats *phy_stats)
2678 {
2679 struct mlx5e_priv *priv = netdev_priv(netdev);
2680
2681 mlx5e_stats_eth_phy_get(priv, phy_stats);
2682 }
2683
mlx5e_get_eth_mac_stats(struct net_device * netdev,struct ethtool_eth_mac_stats * mac_stats)2684 static void mlx5e_get_eth_mac_stats(struct net_device *netdev,
2685 struct ethtool_eth_mac_stats *mac_stats)
2686 {
2687 struct mlx5e_priv *priv = netdev_priv(netdev);
2688
2689 mlx5e_stats_eth_mac_get(priv, mac_stats);
2690 }
2691
mlx5e_get_eth_ctrl_stats(struct net_device * netdev,struct ethtool_eth_ctrl_stats * ctrl_stats)2692 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev,
2693 struct ethtool_eth_ctrl_stats *ctrl_stats)
2694 {
2695 struct mlx5e_priv *priv = netdev_priv(netdev);
2696
2697 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats);
2698 }
2699
mlx5e_get_rmon_stats(struct net_device * netdev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)2700 static void mlx5e_get_rmon_stats(struct net_device *netdev,
2701 struct ethtool_rmon_stats *rmon_stats,
2702 const struct ethtool_rmon_hist_range **ranges)
2703 {
2704 struct mlx5e_priv *priv = netdev_priv(netdev);
2705
2706 mlx5e_stats_rmon_get(priv, rmon_stats, ranges);
2707 }
2708
mlx5e_get_ts_stats(struct net_device * netdev,struct ethtool_ts_stats * ts_stats)2709 static void mlx5e_get_ts_stats(struct net_device *netdev,
2710 struct ethtool_ts_stats *ts_stats)
2711 {
2712 struct mlx5e_priv *priv = netdev_priv(netdev);
2713
2714 mlx5e_stats_ts_get(priv, ts_stats);
2715 }
2716
2717 const struct ethtool_ops mlx5e_ethtool_ops = {
2718 .cap_link_lanes_supported = true,
2719 .rxfh_per_ctx_fields = true,
2720 .rxfh_per_ctx_key = true,
2721 .rxfh_max_num_contexts = MLX5E_MAX_NUM_RSS,
2722 .op_needs_rtnl = ETHTOOL_OP_NEEDS_RTNL_SCHANNELS |
2723 ETHTOOL_OP_NEEDS_RTNL_SRINGPARAM |
2724 ETHTOOL_OP_NEEDS_RTNL_SPFLAGS |
2725 ETHTOOL_OP_NEEDS_RTNL_GLINK,
2726 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2727 ETHTOOL_COALESCE_MAX_FRAMES |
2728 ETHTOOL_COALESCE_USE_ADAPTIVE |
2729 ETHTOOL_COALESCE_USE_CQE,
2730 .supported_input_xfrm = RXH_XFRM_SYM_OR_XOR,
2731 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT |
2732 ETHTOOL_RING_USE_HDS_THRS,
2733 .rxfh_indir_space = MLX5E_MAX_INDIR_RQT_SIZE,
2734 .get_drvinfo = mlx5e_get_drvinfo,
2735 .get_link = ethtool_op_get_link,
2736 .get_link_ext_state = mlx5e_get_link_ext_state,
2737 .get_strings = mlx5e_get_strings,
2738 .get_sset_count = mlx5e_get_sset_count,
2739 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2740 .get_ringparam = mlx5e_get_ringparam,
2741 .set_ringparam = mlx5e_set_ringparam,
2742 .get_channels = mlx5e_get_channels,
2743 .set_channels = mlx5e_set_channels,
2744 .get_coalesce = mlx5e_get_coalesce,
2745 .set_coalesce = mlx5e_set_coalesce,
2746 .get_per_queue_coalesce = mlx5e_get_per_queue_coalesce,
2747 .set_per_queue_coalesce = mlx5e_set_per_queue_coalesce,
2748 .get_link_ksettings = mlx5e_get_link_ksettings,
2749 .set_link_ksettings = mlx5e_set_link_ksettings,
2750 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2751 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2752 .get_rxfh = mlx5e_get_rxfh,
2753 .set_rxfh = mlx5e_set_rxfh,
2754 .get_rxfh_fields = mlx5e_get_rxfh_fields,
2755 .set_rxfh_fields = mlx5e_set_rxfh_fields,
2756 .create_rxfh_context = mlx5e_create_rxfh_context,
2757 .modify_rxfh_context = mlx5e_modify_rxfh_context,
2758 .remove_rxfh_context = mlx5e_remove_rxfh_context,
2759 .get_rxnfc = mlx5e_get_rxnfc,
2760 .set_rxnfc = mlx5e_set_rxnfc,
2761 .get_rx_ring_count = mlx5e_get_rx_ring_count,
2762 .get_tunable = mlx5e_get_tunable,
2763 .set_tunable = mlx5e_set_tunable,
2764 .get_pause_stats = mlx5e_get_pause_stats,
2765 .get_pauseparam = mlx5e_get_pauseparam,
2766 .set_pauseparam = mlx5e_set_pauseparam,
2767 .get_ts_info = mlx5e_get_ts_info,
2768 .set_phys_id = mlx5e_set_phys_id,
2769 .get_wol = mlx5e_get_wol,
2770 .set_wol = mlx5e_set_wol,
2771 .get_module_info = mlx5e_get_module_info,
2772 .get_module_eeprom = mlx5e_get_module_eeprom,
2773 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page,
2774 .flash_device = mlx5e_flash_device,
2775 .get_priv_flags = mlx5e_get_priv_flags,
2776 .set_priv_flags = mlx5e_set_priv_flags,
2777 .self_test = mlx5e_self_test,
2778 .get_fec_stats = mlx5e_get_fec_stats,
2779 .get_fecparam = mlx5e_get_fecparam,
2780 .set_fecparam = mlx5e_set_fecparam,
2781 .get_eth_phy_stats = mlx5e_get_eth_phy_stats,
2782 .get_eth_mac_stats = mlx5e_get_eth_mac_stats,
2783 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats,
2784 .get_rmon_stats = mlx5e_get_rmon_stats,
2785 .get_ts_stats = mlx5e_get_ts_stats,
2786 .get_link_ext_stats = mlx5e_get_link_ext_stats
2787 };
2788