1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2016 Broadcom
4 */
5
6 #include <linux/module.h>
7 #include <linux/io.h>
8 #include <linux/clk.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/platform_device.h>
14
15 #include <linux/iio/iio.h>
16
17 /* Below Register's are common to IPROC ADC and Touchscreen IP */
18 #define IPROC_REGCTL1 0x00
19 #define IPROC_REGCTL2 0x04
20 #define IPROC_INTERRUPT_THRES 0x08
21 #define IPROC_INTERRUPT_MASK 0x0c
22 #define IPROC_INTERRUPT_STATUS 0x10
23 #define IPROC_ANALOG_CONTROL 0x1c
24 #define IPROC_CONTROLLER_STATUS 0x14
25 #define IPROC_AUX_DATA 0x20
26 #define IPROC_SOFT_BYPASS_CONTROL 0x38
27 #define IPROC_SOFT_BYPASS_DATA 0x3C
28
29 /* IPROC ADC Channel register offsets */
30 #define IPROC_ADC_CHANNEL_REGCTL1 0x800
31 #define IPROC_ADC_CHANNEL_REGCTL2 0x804
32 #define IPROC_ADC_CHANNEL_STATUS 0x808
33 #define IPROC_ADC_CHANNEL_INTERRUPT_STATUS 0x80c
34 #define IPROC_ADC_CHANNEL_INTERRUPT_MASK 0x810
35 #define IPROC_ADC_CHANNEL_DATA 0x814
36 #define IPROC_ADC_CHANNEL_OFFSET 0x20
37
38 /* Bit definitions for IPROC_REGCTL2 */
39 #define IPROC_ADC_AUXIN_SCAN_ENA BIT(0)
40 #define IPROC_ADC_PWR_LDO BIT(5)
41 #define IPROC_ADC_PWR_ADC BIT(4)
42 #define IPROC_ADC_PWR_BG BIT(3)
43 #define IPROC_ADC_CONTROLLER_EN BIT(17)
44
45 /* Bit definitions for IPROC_INTERRUPT_MASK and IPROC_INTERRUPT_STATUS */
46 #define IPROC_ADC_AUXDATA_RDY_INTR BIT(3)
47 #define IPROC_ADC_INTR 9
48 #define IPROC_ADC_INTR_MASK (0xFF << IPROC_ADC_INTR)
49
50 /* Bit definitions for IPROC_ANALOG_CONTROL */
51 #define IPROC_ADC_CHANNEL_SEL 11
52 #define IPROC_ADC_CHANNEL_SEL_MASK (0x7 << IPROC_ADC_CHANNEL_SEL)
53
54 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL1 */
55 #define IPROC_ADC_CHANNEL_ROUNDS 0x2
56 #define IPROC_ADC_CHANNEL_ROUNDS_MASK (0x3F << IPROC_ADC_CHANNEL_ROUNDS)
57 #define IPROC_ADC_CHANNEL_MODE 0x1
58 #define IPROC_ADC_CHANNEL_MODE_MASK (0x1 << IPROC_ADC_CHANNEL_MODE)
59 #define IPROC_ADC_CHANNEL_MODE_TDM 0x1
60 #define IPROC_ADC_CHANNEL_MODE_SNAPSHOT 0x0
61 #define IPROC_ADC_CHANNEL_ENABLE 0x0
62 #define IPROC_ADC_CHANNEL_ENABLE_MASK 0x1
63
64 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL2 */
65 #define IPROC_ADC_CHANNEL_WATERMARK 0x0
66 #define IPROC_ADC_CHANNEL_WATERMARK_MASK \
67 (0x3F << IPROC_ADC_CHANNEL_WATERMARK)
68
69 #define IPROC_ADC_WATER_MARK_LEVEL 0x1
70
71 /* Bit definitions for IPROC_ADC_CHANNEL_STATUS */
72 #define IPROC_ADC_CHANNEL_DATA_LOST 0x0
73 #define IPROC_ADC_CHANNEL_DATA_LOST_MASK \
74 (0x0 << IPROC_ADC_CHANNEL_DATA_LOST)
75 #define IPROC_ADC_CHANNEL_VALID_ENTERIES 0x1
76 #define IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK \
77 (0xFF << IPROC_ADC_CHANNEL_VALID_ENTERIES)
78 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES 0x9
79 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK \
80 (0xFF << IPROC_ADC_CHANNEL_TOTAL_ENTERIES)
81
82 /* Bit definitions for IPROC_ADC_CHANNEL_INTERRUPT_MASK */
83 #define IPROC_ADC_CHANNEL_WTRMRK_INTR 0x0
84 #define IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK \
85 (0x1 << IPROC_ADC_CHANNEL_WTRMRK_INTR)
86 #define IPROC_ADC_CHANNEL_FULL_INTR 0x1
87 #define IPROC_ADC_CHANNEL_FULL_INTR_MASK \
88 (0x1 << IPROC_ADC_IPROC_ADC_CHANNEL_FULL_INTR)
89 #define IPROC_ADC_CHANNEL_EMPTY_INTR 0x2
90 #define IPROC_ADC_CHANNEL_EMPTY_INTR_MASK \
91 (0x1 << IPROC_ADC_CHANNEL_EMPTY_INTR)
92
93 #define IPROC_ADC_WATER_MARK_INTR_ENABLE 0x1
94
95 /* Number of time to retry a set of the interrupt mask reg */
96 #define IPROC_ADC_INTMASK_RETRY_ATTEMPTS 10
97
98 #define IPROC_ADC_READ_TIMEOUT (HZ*2)
99
100 #define iproc_adc_dbg_reg(dev, priv, reg) \
101 do { \
102 u32 val; \
103 regmap_read(priv->regmap, reg, &val); \
104 dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \
105 } while (0)
106
107 struct iproc_adc_priv {
108 struct regmap *regmap;
109 struct clk *adc_clk;
110 struct mutex mutex;
111 int irqno;
112 int chan_val;
113 int chan_id;
114 struct completion completion;
115 };
116
iproc_adc_reg_dump(struct iio_dev * indio_dev)117 static void iproc_adc_reg_dump(struct iio_dev *indio_dev)
118 {
119 struct device *dev = &indio_dev->dev;
120 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
121
122 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL1);
123 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL2);
124 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_THRES);
125 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_MASK);
126 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_STATUS);
127 iproc_adc_dbg_reg(dev, adc_priv, IPROC_CONTROLLER_STATUS);
128 iproc_adc_dbg_reg(dev, adc_priv, IPROC_ANALOG_CONTROL);
129 iproc_adc_dbg_reg(dev, adc_priv, IPROC_AUX_DATA);
130 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_CONTROL);
131 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA);
132 }
133
iproc_adc_interrupt_thread(int irq,void * data)134 static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data)
135 {
136 u32 channel_intr_status;
137 u32 intr_status;
138 u32 intr_mask;
139 struct iio_dev *indio_dev = data;
140 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
141
142 /*
143 * This interrupt is shared with the touchscreen driver.
144 * Make sure this interrupt is intended for us.
145 * Handle only ADC channel specific interrupts.
146 */
147 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);
148 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &intr_mask);
149 intr_status = intr_status & intr_mask;
150 channel_intr_status = (intr_status & IPROC_ADC_INTR_MASK) >>
151 IPROC_ADC_INTR;
152 if (channel_intr_status)
153 return IRQ_WAKE_THREAD;
154
155 return IRQ_NONE;
156 }
157
iproc_adc_interrupt_handler(int irq,void * data)158 static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data)
159 {
160 irqreturn_t retval = IRQ_NONE;
161 struct iproc_adc_priv *adc_priv;
162 struct iio_dev *indio_dev = data;
163 unsigned int valid_entries;
164 u32 intr_status;
165 u32 intr_channels;
166 u32 channel_status;
167 u32 ch_intr_status;
168
169 adc_priv = iio_priv(indio_dev);
170
171 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);
172 dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_handler(),INTRPT_STS:%x\n",
173 intr_status);
174
175 intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR;
176 if (intr_channels) {
177 regmap_read(adc_priv->regmap,
178 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
179 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,
180 &ch_intr_status);
181
182 if (ch_intr_status & IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK) {
183 regmap_read(adc_priv->regmap,
184 IPROC_ADC_CHANNEL_STATUS +
185 IPROC_ADC_CHANNEL_OFFSET *
186 adc_priv->chan_id,
187 &channel_status);
188
189 valid_entries = ((channel_status &
190 IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK) >>
191 IPROC_ADC_CHANNEL_VALID_ENTERIES);
192 if (valid_entries >= 1) {
193 regmap_read(adc_priv->regmap,
194 IPROC_ADC_CHANNEL_DATA +
195 IPROC_ADC_CHANNEL_OFFSET *
196 adc_priv->chan_id,
197 &adc_priv->chan_val);
198 complete(&adc_priv->completion);
199 } else {
200 dev_err(&indio_dev->dev,
201 "No data rcvd on channel %d\n",
202 adc_priv->chan_id);
203 }
204 regmap_write(adc_priv->regmap,
205 IPROC_ADC_CHANNEL_INTERRUPT_MASK +
206 IPROC_ADC_CHANNEL_OFFSET *
207 adc_priv->chan_id,
208 (ch_intr_status &
209 ~(IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK)));
210 }
211 regmap_write(adc_priv->regmap,
212 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
213 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,
214 ch_intr_status);
215 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
216 intr_channels);
217 retval = IRQ_HANDLED;
218 }
219
220 return retval;
221 }
222
iproc_adc_do_read(struct iio_dev * indio_dev,int channel,u16 * p_adc_data)223 static int iproc_adc_do_read(struct iio_dev *indio_dev,
224 int channel,
225 u16 *p_adc_data)
226 {
227 int read_len = 0;
228 u32 val;
229 u32 mask;
230 u32 val_check;
231 int failed_cnt = 0;
232 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
233
234 mutex_lock(&adc_priv->mutex);
235
236 /*
237 * After a read is complete the ADC interrupts will be disabled so
238 * we can assume this section of code is safe from interrupts.
239 */
240 adc_priv->chan_val = -1;
241 adc_priv->chan_id = channel;
242
243 reinit_completion(&adc_priv->completion);
244 /* Clear any pending interrupt */
245 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
246 IPROC_ADC_INTR_MASK | IPROC_ADC_AUXDATA_RDY_INTR,
247 ((0x0 << channel) << IPROC_ADC_INTR) |
248 IPROC_ADC_AUXDATA_RDY_INTR);
249
250 /* Configure channel for snapshot mode and enable */
251 val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) |
252 (IPROC_ADC_CHANNEL_MODE_SNAPSHOT << IPROC_ADC_CHANNEL_MODE) |
253 (0x1 << IPROC_ADC_CHANNEL_ENABLE));
254
255 mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK |
256 IPROC_ADC_CHANNEL_ENABLE_MASK;
257 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL1 +
258 IPROC_ADC_CHANNEL_OFFSET * channel),
259 mask, val);
260
261 /* Set the Watermark for a channel */
262 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL2 +
263 IPROC_ADC_CHANNEL_OFFSET * channel),
264 IPROC_ADC_CHANNEL_WATERMARK_MASK,
265 0x1);
266
267 /* Enable water mark interrupt */
268 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_INTERRUPT_MASK +
269 IPROC_ADC_CHANNEL_OFFSET *
270 channel),
271 IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK,
272 IPROC_ADC_WATER_MARK_INTR_ENABLE);
273 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val);
274
275 /* Enable ADC interrupt for a channel */
276 val |= (BIT(channel) << IPROC_ADC_INTR);
277 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val);
278
279 /*
280 * There seems to be a very rare issue where writing to this register
281 * does not take effect. To work around the issue we will try multiple
282 * writes. In total we will spend about 10*10 = 100 us attempting this.
283 * Testing has shown that this may loop a few time, but we have never
284 * hit the full count.
285 */
286 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
287 while (val_check != val) {
288 failed_cnt++;
289
290 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS)
291 break;
292
293 udelay(10);
294 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,
295 IPROC_ADC_INTR_MASK,
296 ((0x1 << channel) <<
297 IPROC_ADC_INTR));
298
299 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
300 }
301
302 if (failed_cnt) {
303 dev_dbg(&indio_dev->dev,
304 "IntMask failed (%d times)", failed_cnt);
305 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) {
306 dev_err(&indio_dev->dev,
307 "IntMask set failed. Read will likely fail.");
308 read_len = -EIO;
309 goto adc_err;
310 }
311 }
312 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
313
314 if (wait_for_completion_timeout(&adc_priv->completion,
315 IPROC_ADC_READ_TIMEOUT) > 0) {
316
317 /* Only the lower 16 bits are relevant */
318 *p_adc_data = adc_priv->chan_val & 0xFFFF;
319 read_len = sizeof(*p_adc_data);
320
321 } else {
322 /*
323 * We never got the interrupt, something went wrong.
324 * Perhaps the interrupt may still be coming, we do not want
325 * that now. Lets disable the ADC interrupt, and clear the
326 * status to put it back in to normal state.
327 */
328 read_len = -ETIMEDOUT;
329 goto adc_err;
330 }
331 mutex_unlock(&adc_priv->mutex);
332
333 return read_len;
334
335 adc_err:
336 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,
337 IPROC_ADC_INTR_MASK,
338 ((0x0 << channel) << IPROC_ADC_INTR));
339
340 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
341 IPROC_ADC_INTR_MASK,
342 ((0x0 << channel) << IPROC_ADC_INTR));
343
344 dev_err(&indio_dev->dev, "Timed out waiting for ADC data!\n");
345 iproc_adc_reg_dump(indio_dev);
346 mutex_unlock(&adc_priv->mutex);
347
348 return read_len;
349 }
350
iproc_adc_enable(struct iio_dev * indio_dev)351 static int iproc_adc_enable(struct iio_dev *indio_dev)
352 {
353 u32 val;
354 u32 channel_id;
355 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
356 int ret;
357
358 /* Set i_amux = 3b'000, select channel 0 */
359 ret = regmap_clear_bits(adc_priv->regmap, IPROC_ANALOG_CONTROL,
360 IPROC_ADC_CHANNEL_SEL_MASK);
361 if (ret) {
362 dev_err(&indio_dev->dev,
363 "failed to write IPROC_ANALOG_CONTROL %d\n", ret);
364 return ret;
365 }
366 adc_priv->chan_val = -1;
367
368 /*
369 * PWR up LDO, ADC, and Band Gap (0 to enable)
370 * Also enable ADC controller (set high)
371 */
372 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
373 if (ret) {
374 dev_err(&indio_dev->dev,
375 "failed to read IPROC_REGCTL2 %d\n", ret);
376 return ret;
377 }
378
379 val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG);
380
381 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
382 if (ret) {
383 dev_err(&indio_dev->dev,
384 "failed to write IPROC_REGCTL2 %d\n", ret);
385 return ret;
386 }
387
388 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
389 if (ret) {
390 dev_err(&indio_dev->dev,
391 "failed to read IPROC_REGCTL2 %d\n", ret);
392 return ret;
393 }
394
395 val |= IPROC_ADC_CONTROLLER_EN;
396 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
397 if (ret) {
398 dev_err(&indio_dev->dev,
399 "failed to write IPROC_REGCTL2 %d\n", ret);
400 return ret;
401 }
402
403 for (channel_id = 0; channel_id < indio_dev->num_channels;
404 channel_id++) {
405 ret = regmap_write(adc_priv->regmap,
406 IPROC_ADC_CHANNEL_INTERRUPT_MASK +
407 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);
408 if (ret) {
409 dev_err(&indio_dev->dev,
410 "failed to write ADC_CHANNEL_INTERRUPT_MASK %d\n",
411 ret);
412 return ret;
413 }
414
415 ret = regmap_write(adc_priv->regmap,
416 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
417 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);
418 if (ret) {
419 dev_err(&indio_dev->dev,
420 "failed to write ADC_CHANNEL_INTERRUPT_STATUS %d\n",
421 ret);
422 return ret;
423 }
424 }
425
426 return 0;
427 }
428
iproc_adc_disable(struct iio_dev * indio_dev)429 static void iproc_adc_disable(struct iio_dev *indio_dev)
430 {
431 u32 val;
432 int ret;
433 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
434
435 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
436 if (ret) {
437 dev_err(&indio_dev->dev,
438 "failed to read IPROC_REGCTL2 %d\n", ret);
439 return;
440 }
441
442 val &= ~IPROC_ADC_CONTROLLER_EN;
443 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
444 if (ret) {
445 dev_err(&indio_dev->dev,
446 "failed to write IPROC_REGCTL2 %d\n", ret);
447 return;
448 }
449 }
450
iproc_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)451 static int iproc_adc_read_raw(struct iio_dev *indio_dev,
452 struct iio_chan_spec const *chan,
453 int *val,
454 int *val2,
455 long mask)
456 {
457 u16 adc_data;
458 int err;
459
460 switch (mask) {
461 case IIO_CHAN_INFO_RAW:
462 err = iproc_adc_do_read(indio_dev, chan->channel, &adc_data);
463 if (err < 0)
464 return err;
465 *val = adc_data;
466 return IIO_VAL_INT;
467 case IIO_CHAN_INFO_SCALE:
468 switch (chan->type) {
469 case IIO_VOLTAGE:
470 *val = 1800;
471 *val2 = 10;
472 return IIO_VAL_FRACTIONAL_LOG2;
473 default:
474 return -EINVAL;
475 }
476 default:
477 return -EINVAL;
478 }
479 }
480
481 static const struct iio_info iproc_adc_iio_info = {
482 .read_raw = &iproc_adc_read_raw,
483 };
484
485 #define IPROC_ADC_CHANNEL(_index, _id) { \
486 .type = IIO_VOLTAGE, \
487 .indexed = 1, \
488 .channel = _index, \
489 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
490 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
491 .datasheet_name = _id, \
492 }
493
494 static const struct iio_chan_spec iproc_adc_iio_channels[] = {
495 IPROC_ADC_CHANNEL(0, "adc0"),
496 IPROC_ADC_CHANNEL(1, "adc1"),
497 IPROC_ADC_CHANNEL(2, "adc2"),
498 IPROC_ADC_CHANNEL(3, "adc3"),
499 IPROC_ADC_CHANNEL(4, "adc4"),
500 IPROC_ADC_CHANNEL(5, "adc5"),
501 IPROC_ADC_CHANNEL(6, "adc6"),
502 IPROC_ADC_CHANNEL(7, "adc7"),
503 };
504
iproc_adc_probe(struct platform_device * pdev)505 static int iproc_adc_probe(struct platform_device *pdev)
506 {
507 struct iproc_adc_priv *adc_priv;
508 struct iio_dev *indio_dev = NULL;
509 int ret;
510
511 indio_dev = devm_iio_device_alloc(&pdev->dev,
512 sizeof(*adc_priv));
513 if (!indio_dev)
514 return -ENOMEM;
515
516 adc_priv = iio_priv(indio_dev);
517 platform_set_drvdata(pdev, indio_dev);
518
519 mutex_init(&adc_priv->mutex);
520
521 init_completion(&adc_priv->completion);
522
523 adc_priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
524 "adc-syscon");
525 if (IS_ERR(adc_priv->regmap)) {
526 dev_err(&pdev->dev, "failed to get handle for tsc syscon\n");
527 ret = PTR_ERR(adc_priv->regmap);
528 return ret;
529 }
530
531 adc_priv->adc_clk = devm_clk_get(&pdev->dev, "tsc_clk");
532 if (IS_ERR(adc_priv->adc_clk)) {
533 dev_err(&pdev->dev,
534 "failed getting clock tsc_clk\n");
535 ret = PTR_ERR(adc_priv->adc_clk);
536 return ret;
537 }
538
539 adc_priv->irqno = platform_get_irq(pdev, 0);
540 if (adc_priv->irqno < 0)
541 return adc_priv->irqno;
542
543 ret = regmap_clear_bits(adc_priv->regmap, IPROC_REGCTL2,
544 IPROC_ADC_AUXIN_SCAN_ENA);
545 if (ret) {
546 dev_err(&pdev->dev, "failed to write IPROC_REGCTL2 %d\n", ret);
547 return ret;
548 }
549
550 ret = devm_request_threaded_irq(&pdev->dev, adc_priv->irqno,
551 iproc_adc_interrupt_handler,
552 iproc_adc_interrupt_thread,
553 IRQF_SHARED, "iproc-adc", indio_dev);
554 if (ret) {
555 dev_err(&pdev->dev, "request_irq error %d\n", ret);
556 return ret;
557 }
558
559 ret = clk_prepare_enable(adc_priv->adc_clk);
560 if (ret) {
561 dev_err(&pdev->dev,
562 "clk_prepare_enable failed %d\n", ret);
563 return ret;
564 }
565
566 ret = iproc_adc_enable(indio_dev);
567 if (ret) {
568 dev_err(&pdev->dev, "failed to enable adc %d\n", ret);
569 goto err_adc_enable;
570 }
571
572 indio_dev->name = "iproc-static-adc";
573 indio_dev->info = &iproc_adc_iio_info;
574 indio_dev->modes = INDIO_DIRECT_MODE;
575 indio_dev->channels = iproc_adc_iio_channels;
576 indio_dev->num_channels = ARRAY_SIZE(iproc_adc_iio_channels);
577
578 ret = iio_device_register(indio_dev);
579 if (ret) {
580 dev_err(&pdev->dev, "iio_device_register failed:err %d\n", ret);
581 goto err_clk;
582 }
583
584 return 0;
585
586 err_clk:
587 iproc_adc_disable(indio_dev);
588 err_adc_enable:
589 clk_disable_unprepare(adc_priv->adc_clk);
590
591 return ret;
592 }
593
iproc_adc_remove(struct platform_device * pdev)594 static void iproc_adc_remove(struct platform_device *pdev)
595 {
596 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
597 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
598
599 iio_device_unregister(indio_dev);
600 iproc_adc_disable(indio_dev);
601 clk_disable_unprepare(adc_priv->adc_clk);
602 }
603
604 static const struct of_device_id iproc_adc_of_match[] = {
605 {.compatible = "brcm,iproc-static-adc", },
606 { }
607 };
608 MODULE_DEVICE_TABLE(of, iproc_adc_of_match);
609
610 static struct platform_driver iproc_adc_driver = {
611 .probe = iproc_adc_probe,
612 .remove = iproc_adc_remove,
613 .driver = {
614 .name = "iproc-static-adc",
615 .of_match_table = iproc_adc_of_match,
616 },
617 };
618 module_platform_driver(iproc_adc_driver);
619
620 MODULE_DESCRIPTION("Broadcom iProc ADC controller driver");
621 MODULE_AUTHOR("Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>");
622 MODULE_LICENSE("GPL v2");
623